]> git.proxmox.com Git - mirror_ubuntu-jammy-kernel.git/blame - drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
projects / mirror_ubuntu-jammy-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/amd/powerplay: fix copy error in powerplay.
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / amdgpu / gfx_v9_0.c
CommitLineData
b1023571
KW		 1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include "drmP.h"
25#include "amdgpu.h"
26#include "amdgpu_gfx.h"
27#include "soc15.h"
28#include "soc15d.h"
29
30#include "vega10/soc15ip.h"
31#include "vega10/GC/gc_9_0_offset.h"
32#include "vega10/GC/gc_9_0_sh_mask.h"
33#include "vega10/vega10_enum.h"
34#include "vega10/HDP/hdp_4_0_offset.h"
35
36#include "soc15_common.h"
37#include "clearstate_gfx9.h"
38#include "v9_structs.h"
39
40#define GFX9_NUM_GFX_RINGS 1
268cb4c7 41#define GFX9_MEC_HPD_SIZE 2048
6bce4667
HZ		 42#define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
43#define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L
44#define GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH 34
b1023571 45
91d3130a
HZ		 46#define mmPWR_MISC_CNTL_STATUS 0x0183
47#define mmPWR_MISC_CNTL_STATUS_BASE_IDX 0
48#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT 0x0
49#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT 0x1
50#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK 0x00000001L
51#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK 0x00000006L
52
b1023571
KW		 53MODULE_FIRMWARE("amdgpu/vega10_ce.bin");
54MODULE_FIRMWARE("amdgpu/vega10_pfp.bin");
55MODULE_FIRMWARE("amdgpu/vega10_me.bin");
56MODULE_FIRMWARE("amdgpu/vega10_mec.bin");
57MODULE_FIRMWARE("amdgpu/vega10_mec2.bin");
58MODULE_FIRMWARE("amdgpu/vega10_rlc.bin");
59
060d124b
CZ		 60MODULE_FIRMWARE("amdgpu/raven_ce.bin");
61MODULE_FIRMWARE("amdgpu/raven_pfp.bin");
62MODULE_FIRMWARE("amdgpu/raven_me.bin");
63MODULE_FIRMWARE("amdgpu/raven_mec.bin");
64MODULE_FIRMWARE("amdgpu/raven_mec2.bin");
65MODULE_FIRMWARE("amdgpu/raven_rlc.bin");
66
b1023571
KW		 67static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
68{
69 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
70 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0)},
71 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_SIZE),
72 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID1), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID1)},
73 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_SIZE),
74 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID2), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID2)},
75 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_SIZE),
76 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID3), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID3)},
77 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_SIZE),
78 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID4), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID4)},
79 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_SIZE),
80 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID5), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID5)},
81 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_SIZE),
82 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID6), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID6)},
83 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_SIZE),
84 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID7), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID7)},
85 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_SIZE),
86 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID8), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID8)},
87 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_SIZE),
88 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID9), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID9)},
89 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_SIZE),
90 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID10), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID10)},
91 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_SIZE),
92 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID11), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID11)},
93 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_SIZE),
94 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID12), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID12)},
95 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_SIZE),
96 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID13), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID13)},
97 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_SIZE),
98 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID14), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID14)},
99 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_SIZE),
100 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID15), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID15)}
101};
102
103static const u32 golden_settings_gc_9_0[] =
104{
f8af9332
KW		 105 SOC15_REG_OFFSET(GC, 0, mmCPC_UTCL1_CNTL), 0x08000000, 0x08000080,
106 SOC15_REG_OFFSET(GC, 0, mmCPF_UTCL1_CNTL), 0x08000000, 0x08000080,
107 SOC15_REG_OFFSET(GC, 0, mmCPG_UTCL1_CNTL), 0x08000000, 0x08000080,
108 SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00fffff, 0x00000420,
109 SOC15_REG_OFFSET(GC, 0, mmGB_GPU_ID), 0x0000000f, 0x00000000,
110 SOC15_REG_OFFSET(GC, 0, mmIA_UTCL1_CNTL), 0x08000000, 0x08000080,
b1023571
KW		 111 SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024,
112 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001,
113 SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000,
f8af9332
KW		 114 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_0), 0x08000000, 0x08000080,
115 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_1), 0x08000000, 0x08000080,
116 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_2), 0x08000000, 0x08000080,
117 SOC15_REG_OFFSET(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL), 0x08000000, 0x08000080,
118 SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_UTCL1_CNTL), 0x08000000, 0x08000080,
119 SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_1), 0x0000000f, 0x01000107,
b1023571
KW		 120 SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000,
121 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x4a2c0e68,
122 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0xb5d3f197,
f8af9332
KW		 123 SOC15_REG_OFFSET(GC, 0, mmVGT_CACHE_INVALIDATION), 0x3fff3af3, 0x19200000,
124 SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000003ff,
125 SOC15_REG_OFFSET(GC, 0, mmWD_UTCL1_CNTL), 0x08000000, 0x08000080
b1023571
KW		 126};
127
128static const u32 golden_settings_gc_9_0_vg10[] =
129{
130 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0x0000f000, 0x00012107,
131 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL_3), 0x30000000, 0x10000000,
132 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x2a114042,
133 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x2a114042,
134 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0x00008000, 0x00048000,
135 SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000,
f8af9332 136 SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x00001800, 0x00000800
b1023571
KW		 137};
138
a5fdb336
CZ		 139static const u32 golden_settings_gc_9_1[] =
140{
141 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0xfffdf3cf, 0x00014104,
01b5cc36
HZ		 142 SOC15_REG_OFFSET(GC, 0, mmCPC_UTCL1_CNTL), 0x08000000, 0x08000080,
143 SOC15_REG_OFFSET(GC, 0, mmCPF_UTCL1_CNTL), 0x08000000, 0x08000080,
144 SOC15_REG_OFFSET(GC, 0, mmCPG_UTCL1_CNTL), 0x08000000, 0x08000080,
a5fdb336
CZ		 145 SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00fffff, 0x00000420,
146 SOC15_REG_OFFSET(GC, 0, mmGB_GPU_ID), 0x0000000f, 0x00000000,
01b5cc36 147 SOC15_REG_OFFSET(GC, 0, mmIA_UTCL1_CNTL), 0x08000000, 0x08000080,
a5fdb336
CZ		 148 SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024,
149 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001,
150 SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000,
01b5cc36
HZ		 151 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_0), 0x08000000, 0x08000080,
152 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_1), 0x08000000, 0x08000080,
153 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_2), 0x08000000, 0x08000080,
154 SOC15_REG_OFFSET(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL), 0x08000000, 0x08000080,
155 SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_UTCL1_CNTL), 0x08000000, 0x08000080,
a5fdb336
CZ		 156 SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000,
157 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x00000000,
158 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0x00003120,
01b5cc36
HZ		 159 SOC15_REG_OFFSET(GC, 0, mmVGT_CACHE_INVALIDATION), 0x3fff3af3, 0x19200000,
160 SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000000ff,
161 SOC15_REG_OFFSET(GC, 0, mmWD_UTCL1_CNTL), 0x08000000, 0x08000080
a5fdb336
CZ		 162};
163
164static const u32 golden_settings_gc_9_1_rv1[] =
165{
7b6ba9ea
HZ		 166 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL_3), 0x30000000, 0x10000000,
167 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x24000042,
168 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x24000042,
169 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0xffffffff, 0x04048000,
170 SOC15_REG_OFFSET(GC, 0, mmPA_SC_MODE_CNTL_1), 0x06000000, 0x06000000,
171 SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000,
a5fdb336
CZ		 172 SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x01bd9f33, 0x00000800
173};
b1023571 174
5cf7433d 175#define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
7b6ba9ea 176#define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042
5cf7433d 177
b1023571
KW		 178static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev);
179static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev);
180static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev);
181static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev);
182static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
183 struct amdgpu_cu_info *cu_info);
184static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
185static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
635e7132 186static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring);
b1023571
KW		 187
188static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
189{
190 switch (adev->asic_type) {
191 case CHIP_VEGA10:
192 amdgpu_program_register_sequence(adev,
193 golden_settings_gc_9_0,
194 (const u32)ARRAY_SIZE(golden_settings_gc_9_0));
195 amdgpu_program_register_sequence(adev,
196 golden_settings_gc_9_0_vg10,
197 (const u32)ARRAY_SIZE(golden_settings_gc_9_0_vg10));
198 break;
a5fdb336
CZ		 199 case CHIP_RAVEN:
200 amdgpu_program_register_sequence(adev,
201 golden_settings_gc_9_1,
202 (const u32)ARRAY_SIZE(golden_settings_gc_9_1));
203 amdgpu_program_register_sequence(adev,
204 golden_settings_gc_9_1_rv1,
205 (const u32)ARRAY_SIZE(golden_settings_gc_9_1_rv1));
206 break;
b1023571
KW		 207 default:
208 break;
209 }
210}
211
212static void gfx_v9_0_scratch_init(struct amdgpu_device *adev)
213{
214 adev->gfx.scratch.num_reg = 7;
215 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
216 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
217}
218
219static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
220 bool wc, uint32_t reg, uint32_t val)
221{
222 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
223 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
224 WRITE_DATA_DST_SEL(0) |
225 (wc ? WR_CONFIRM : 0));
226 amdgpu_ring_write(ring, reg);
227 amdgpu_ring_write(ring, 0);
228 amdgpu_ring_write(ring, val);
229}
230
231static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
232 int mem_space, int opt, uint32_t addr0,
233 uint32_t addr1, uint32_t ref, uint32_t mask,
234 uint32_t inv)
235{
236 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
237 amdgpu_ring_write(ring,
238 /* memory (1) or register (0) */
239 (WAIT_REG_MEM_MEM_SPACE(mem_space) |
240 WAIT_REG_MEM_OPERATION(opt) | /* wait */
241 WAIT_REG_MEM_FUNCTION(3) | /* equal */
242 WAIT_REG_MEM_ENGINE(eng_sel)));
243
244 if (mem_space)
245 BUG_ON(addr0 & 0x3); /* Dword align */
246 amdgpu_ring_write(ring, addr0);
247 amdgpu_ring_write(ring, addr1);
248 amdgpu_ring_write(ring, ref);
249 amdgpu_ring_write(ring, mask);
250 amdgpu_ring_write(ring, inv); /* poll interval */
251}
252
253static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring)
254{
255 struct amdgpu_device *adev = ring->adev;
256 uint32_t scratch;
257 uint32_t tmp = 0;
258 unsigned i;
259 int r;
260
261 r = amdgpu_gfx_scratch_get(adev, &scratch);
262 if (r) {
263 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
264 return r;
265 }
266 WREG32(scratch, 0xCAFEDEAD);
267 r = amdgpu_ring_alloc(ring, 3);
268 if (r) {
269 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
270 ring->idx, r);
271 amdgpu_gfx_scratch_free(adev, scratch);
272 return r;
273 }
274 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
275 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
276 amdgpu_ring_write(ring, 0xDEADBEEF);
277 amdgpu_ring_commit(ring);
278
279 for (i = 0; i < adev->usec_timeout; i++) {
280 tmp = RREG32(scratch);
281 if (tmp == 0xDEADBEEF)
282 break;
283 DRM_UDELAY(1);
284 }
285 if (i < adev->usec_timeout) {
286 DRM_INFO("ring test on %d succeeded in %d usecs\n",
287 ring->idx, i);
288 } else {
289 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
290 ring->idx, scratch, tmp);
291 r = -EINVAL;
292 }
293 amdgpu_gfx_scratch_free(adev, scratch);
294 return r;
295}
296
297static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
298{
299 struct amdgpu_device *adev = ring->adev;
300 struct amdgpu_ib ib;
301 struct dma_fence *f = NULL;
302 uint32_t scratch;
303 uint32_t tmp = 0;
304 long r;
305
306 r = amdgpu_gfx_scratch_get(adev, &scratch);
307 if (r) {
308 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
309 return r;
310 }
311 WREG32(scratch, 0xCAFEDEAD);
312 memset(&ib, 0, sizeof(ib));
313 r = amdgpu_ib_get(adev, NULL, 256, &ib);
314 if (r) {
315 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
316 goto err1;
317 }
318 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
319 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
320 ib.ptr[2] = 0xDEADBEEF;
321 ib.length_dw = 3;
322
323 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
324 if (r)
325 goto err2;
326
327 r = dma_fence_wait_timeout(f, false, timeout);
328 if (r == 0) {
329 DRM_ERROR("amdgpu: IB test timed out.\n");
330 r = -ETIMEDOUT;
331 goto err2;
332 } else if (r < 0) {
333 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
334 goto err2;
335 }
336 tmp = RREG32(scratch);
337 if (tmp == 0xDEADBEEF) {
338 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
339 r = 0;
340 } else {
341 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
342 scratch, tmp);
343 r = -EINVAL;
344 }
345err2:
346 amdgpu_ib_free(adev, &ib, NULL);
347 dma_fence_put(f);
348err1:
349 amdgpu_gfx_scratch_free(adev, scratch);
350 return r;
351}
352
353static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
354{
355 const char *chip_name;
356 char fw_name[30];
357 int err;
358 struct amdgpu_firmware_info *info = NULL;
359 const struct common_firmware_header *header = NULL;
360 const struct gfx_firmware_header_v1_0 *cp_hdr;
a4d41ad0
HZ		 361 const struct rlc_firmware_header_v2_0 *rlc_hdr;
362 unsigned int *tmp = NULL;
363 unsigned int i = 0;
b1023571
KW		 364
365 DRM_DEBUG("\n");
366
367 switch (adev->asic_type) {
368 case CHIP_VEGA10:
369 chip_name = "vega10";
370 break;
eaa85724
CZ		 371 case CHIP_RAVEN:
372 chip_name = "raven";
373 break;
b1023571
KW		 374 default:
375 BUG();
376 }
377
378 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
379 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
380 if (err)
381 goto out;
382 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
383 if (err)
384 goto out;
385 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
386 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
387 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
388
389 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
390 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
391 if (err)
392 goto out;
393 err = amdgpu_ucode_validate(adev->gfx.me_fw);
394 if (err)
395 goto out;
396 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
397 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
398 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
399
400 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
401 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
402 if (err)
403 goto out;
404 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
405 if (err)
406 goto out;
407 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
408 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
409 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
410
411 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
412 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
413 if (err)
414 goto out;
415 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
a4d41ad0
HZ		 416 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
417 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
418 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
419 adev->gfx.rlc.save_and_restore_offset =
420 le32_to_cpu(rlc_hdr->save_and_restore_offset);
421 adev->gfx.rlc.clear_state_descriptor_offset =
422 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
423 adev->gfx.rlc.avail_scratch_ram_locations =
424 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
425 adev->gfx.rlc.reg_restore_list_size =
426 le32_to_cpu(rlc_hdr->reg_restore_list_size);
427 adev->gfx.rlc.reg_list_format_start =
428 le32_to_cpu(rlc_hdr->reg_list_format_start);
429 adev->gfx.rlc.reg_list_format_separate_start =
430 le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
431 adev->gfx.rlc.starting_offsets_start =
432 le32_to_cpu(rlc_hdr->starting_offsets_start);
433 adev->gfx.rlc.reg_list_format_size_bytes =
434 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
435 adev->gfx.rlc.reg_list_size_bytes =
436 le32_to_cpu(rlc_hdr->reg_list_size_bytes);
437 adev->gfx.rlc.register_list_format =
438 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
439 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
440 if (!adev->gfx.rlc.register_list_format) {
441 err = -ENOMEM;
442 goto out;
443 }
444
445 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
446 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
447 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
448 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
449
450 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
451
452 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
453 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
454 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
455 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
b1023571
KW		 456
457 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
458 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
459 if (err)
460 goto out;
461 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
462 if (err)
463 goto out;
464 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
465 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
466 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
467
468
469 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
470 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
471 if (!err) {
472 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
473 if (err)
474 goto out;
475 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
476 adev->gfx.mec2_fw->data;
477 adev->gfx.mec2_fw_version =
478 le32_to_cpu(cp_hdr->header.ucode_version);
479 adev->gfx.mec2_feature_version =
480 le32_to_cpu(cp_hdr->ucode_feature_version);
481 } else {
482 err = 0;
483 adev->gfx.mec2_fw = NULL;
484 }
485
486 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
487 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
488 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
489 info->fw = adev->gfx.pfp_fw;
490 header = (const struct common_firmware_header *)info->fw->data;
491 adev->firmware.fw_size +=
492 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
493
494 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
495 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
496 info->fw = adev->gfx.me_fw;
497 header = (const struct common_firmware_header *)info->fw->data;
498 adev->firmware.fw_size +=
499 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
500
501 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
502 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
503 info->fw = adev->gfx.ce_fw;
504 header = (const struct common_firmware_header *)info->fw->data;
505 adev->firmware.fw_size +=
506 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
507
508 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
509 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
510 info->fw = adev->gfx.rlc_fw;
511 header = (const struct common_firmware_header *)info->fw->data;
512 adev->firmware.fw_size +=
513 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
514
515 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
516 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
517 info->fw = adev->gfx.mec_fw;
518 header = (const struct common_firmware_header *)info->fw->data;
519 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
520 adev->firmware.fw_size +=
521 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
522
523 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
524 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
525 info->fw = adev->gfx.mec_fw;
526 adev->firmware.fw_size +=
527 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
528
529 if (adev->gfx.mec2_fw) {
530 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
531 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
532 info->fw = adev->gfx.mec2_fw;
533 header = (const struct common_firmware_header *)info->fw->data;
534 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
535 adev->firmware.fw_size +=
536 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
537 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
538 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
539 info->fw = adev->gfx.mec2_fw;
540 adev->firmware.fw_size +=
541 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
542 }
543
544 }
545
546out:
547 if (err) {
548 dev_err(adev->dev,
549 "gfx9: Failed to load firmware \"%s\"\n",
550 fw_name);
551 release_firmware(adev->gfx.pfp_fw);
552 adev->gfx.pfp_fw = NULL;
553 release_firmware(adev->gfx.me_fw);
554 adev->gfx.me_fw = NULL;
555 release_firmware(adev->gfx.ce_fw);
556 adev->gfx.ce_fw = NULL;
557 release_firmware(adev->gfx.rlc_fw);
558 adev->gfx.rlc_fw = NULL;
559 release_firmware(adev->gfx.mec_fw);
560 adev->gfx.mec_fw = NULL;
561 release_firmware(adev->gfx.mec2_fw);
562 adev->gfx.mec2_fw = NULL;
563 }
564 return err;
565}
566
c9719c69
HZ		 567static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev)
568{
569 u32 count = 0;
570 const struct cs_section_def *sect = NULL;
571 const struct cs_extent_def *ext = NULL;
572
573 /* begin clear state */
574 count += 2;
575 /* context control state */
576 count += 3;
577
578 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
579 for (ext = sect->section; ext->extent != NULL; ++ext) {
580 if (sect->id == SECT_CONTEXT)
581 count += 2 + ext->reg_count;
582 else
583 return 0;
584 }
585 }
586
587 /* end clear state */
588 count += 2;
589 /* clear state */
590 count += 2;
591
592 return count;
593}
594
595static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev,
596 volatile u32 *buffer)
597{
598 u32 count = 0, i;
599 const struct cs_section_def *sect = NULL;
600 const struct cs_extent_def *ext = NULL;
601
602 if (adev->gfx.rlc.cs_data == NULL)
603 return;
604 if (buffer == NULL)
605 return;
606
607 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
608 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
609
610 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
611 buffer[count++] = cpu_to_le32(0x80000000);
612 buffer[count++] = cpu_to_le32(0x80000000);
613
614 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
615 for (ext = sect->section; ext->extent != NULL; ++ext) {
616 if (sect->id == SECT_CONTEXT) {
617 buffer[count++] =
618 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
619 buffer[count++] = cpu_to_le32(ext->reg_index -
620 PACKET3_SET_CONTEXT_REG_START);
621 for (i = 0; i < ext->reg_count; i++)
622 buffer[count++] = cpu_to_le32(ext->extent[i]);
623 } else {
624 return;
625 }
626 }
627 }
628
629 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
630 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
631
632 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
633 buffer[count++] = cpu_to_le32(0);
634}
635
ba7bb665
HZ		 636static void gfx_v9_0_init_lbpw(struct amdgpu_device *adev)
637{
638 uint32_t data = 0;
639
640 /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */
641 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F);
642 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x0333A5A7);
643 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077);
644 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x30 | 0x40 << 8 | 0x02FA << 16));
645
646 /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */
647 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000);
648
649 /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */
650 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000500);
651
652 mutex_lock(&adev->grbm_idx_mutex);
653 /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/
654 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
655 WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff);
656
657 /* set mmRLC_LB_PARAMS = 0x003F_1006 */
658 data |= (0x0003 << RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT) &
659 RLC_LB_PARAMS__FIFO_SAMPLES_MASK;
660 data |= (0x0010 << RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT) &
661 RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK;
662 data |= (0x033F << RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT) &
663 RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK;
664 WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data);
665
666 /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */
667 data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7);
668 data &= 0x0000FFFF;
669 data |= 0x00C00000;
670 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data);
671
672 /* set RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xFFF */
673 WREG32_SOC15(GC, 0, mmRLC_LB_ALWAYS_ACTIVE_CU_MASK, 0xFFF);
674
675 /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved,
676 * but used for RLC_LB_CNTL configuration */
677 data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK;
678 data |= (0x09 << RLC_LB_CNTL__CU_MASK_USED_OFF_HYST__SHIFT) &
679 RLC_LB_CNTL__CU_MASK_USED_OFF_HYST_MASK;
680 data |= (0x80000 << RLC_LB_CNTL__RESERVED__SHIFT) &
681 RLC_LB_CNTL__RESERVED_MASK;
682 WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data);
683 mutex_unlock(&adev->grbm_idx_mutex);
684}
685
e8835e0e
HZ		 686static void gfx_v9_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
687{
688 uint32_t data = 0;
689
690 data = RREG32_SOC15(GC, 0, mmRLC_LB_CNTL);
691 if (enable)
692 data |= RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
693 else
694 data &= ~RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
695 WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data);
696}
697
c9719c69
HZ		 698static void rv_init_cp_jump_table(struct amdgpu_device *adev)
699{
700 const __le32 *fw_data;
701 volatile u32 *dst_ptr;
702 int me, i, max_me = 5;
703 u32 bo_offset = 0;
704 u32 table_offset, table_size;
705
706 /* write the cp table buffer */
707 dst_ptr = adev->gfx.rlc.cp_table_ptr;
708 for (me = 0; me < max_me; me++) {
709 if (me == 0) {
710 const struct gfx_firmware_header_v1_0 *hdr =
711 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
712 fw_data = (const __le32 *)
713 (adev->gfx.ce_fw->data +
714 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
715 table_offset = le32_to_cpu(hdr->jt_offset);
716 table_size = le32_to_cpu(hdr->jt_size);
717 } else if (me == 1) {
718 const struct gfx_firmware_header_v1_0 *hdr =
719 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
720 fw_data = (const __le32 *)
721 (adev->gfx.pfp_fw->data +
722 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
723 table_offset = le32_to_cpu(hdr->jt_offset);
724 table_size = le32_to_cpu(hdr->jt_size);
725 } else if (me == 2) {
726 const struct gfx_firmware_header_v1_0 *hdr =
727 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
728 fw_data = (const __le32 *)
729 (adev->gfx.me_fw->data +
730 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
731 table_offset = le32_to_cpu(hdr->jt_offset);
732 table_size = le32_to_cpu(hdr->jt_size);
733 } else if (me == 3) {
734 const struct gfx_firmware_header_v1_0 *hdr =
735 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
736 fw_data = (const __le32 *)
737 (adev->gfx.mec_fw->data +
738 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
739 table_offset = le32_to_cpu(hdr->jt_offset);
740 table_size = le32_to_cpu(hdr->jt_size);
741 } else if (me == 4) {
742 const struct gfx_firmware_header_v1_0 *hdr =
743 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
744 fw_data = (const __le32 *)
745 (adev->gfx.mec2_fw->data +
746 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
747 table_offset = le32_to_cpu(hdr->jt_offset);
748 table_size = le32_to_cpu(hdr->jt_size);
749 }
750
751 for (i = 0; i < table_size; i ++) {
752 dst_ptr[bo_offset + i] =
753 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
754 }
755
756 bo_offset += table_size;
757 }
758}
759
760static void gfx_v9_0_rlc_fini(struct amdgpu_device *adev)
761{
762 /* clear state block */
763 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
764 &adev->gfx.rlc.clear_state_gpu_addr,
765 (void **)&adev->gfx.rlc.cs_ptr);
766
767 /* jump table block */
768 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
769 &adev->gfx.rlc.cp_table_gpu_addr,
770 (void **)&adev->gfx.rlc.cp_table_ptr);
771}
772
773static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
774{
775 volatile u32 *dst_ptr;
776 u32 dws;
777 const struct cs_section_def *cs_data;
778 int r;
779
780 adev->gfx.rlc.cs_data = gfx9_cs_data;
781
782 cs_data = adev->gfx.rlc.cs_data;
783
784 if (cs_data) {
785 /* clear state block */
786 adev->gfx.rlc.clear_state_size = dws = gfx_v9_0_get_csb_size(adev);
787 if (adev->gfx.rlc.clear_state_obj == NULL) {
788 r = amdgpu_bo_create_kernel(adev, dws * 4, PAGE_SIZE,
789 AMDGPU_GEM_DOMAIN_VRAM,
790 &adev->gfx.rlc.clear_state_obj,
791 &adev->gfx.rlc.clear_state_gpu_addr,
792 (void **)&adev->gfx.rlc.cs_ptr);
793 if (r) {
794 dev_err(adev->dev,
795 "(%d) failed to create rlc csb bo\n", r);
796 gfx_v9_0_rlc_fini(adev);
797 return r;
798 }
799 }
800 /* set up the cs buffer */
801 dst_ptr = adev->gfx.rlc.cs_ptr;
802 gfx_v9_0_get_csb_buffer(adev, dst_ptr);
803 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
804 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
805 }
806
807 if (adev->asic_type == CHIP_RAVEN) {
808 /* TODO: double check the cp_table_size for RV */
809 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
810 if (adev->gfx.rlc.cp_table_obj == NULL) {
811 r = amdgpu_bo_create_kernel(adev, adev->gfx.rlc.cp_table_size,
812 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
813 &adev->gfx.rlc.cp_table_obj,
814 &adev->gfx.rlc.cp_table_gpu_addr,
815 (void **)&adev->gfx.rlc.cp_table_ptr);
816 if (r) {
817 dev_err(adev->dev,
818 "(%d) failed to create cp table bo\n", r);
819 gfx_v9_0_rlc_fini(adev);
820 return r;
821 }
822 }
823
824 rv_init_cp_jump_table(adev);
825 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
826 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
ba7bb665
HZ		 827
828 gfx_v9_0_init_lbpw(adev);
c9719c69
HZ		 829 }
830
831 return 0;
832}
833
b1023571
KW		 834static void gfx_v9_0_mec_fini(struct amdgpu_device *adev)
835{
836 int r;
837
838 if (adev->gfx.mec.hpd_eop_obj) {
c81a1a74 839 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, true);
b1023571
KW		 840 if (unlikely(r != 0))
841 dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
842 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
843 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
844
845 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
846 adev->gfx.mec.hpd_eop_obj = NULL;
847 }
848 if (adev->gfx.mec.mec_fw_obj) {
c81a1a74 849 r = amdgpu_bo_reserve(adev->gfx.mec.mec_fw_obj, true);
b1023571
KW		 850 if (unlikely(r != 0))
851 dev_warn(adev->dev, "(%d) reserve mec firmware bo failed\n", r);
852 amdgpu_bo_unpin(adev->gfx.mec.mec_fw_obj);
853 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
854
855 amdgpu_bo_unref(&adev->gfx.mec.mec_fw_obj);
856 adev->gfx.mec.mec_fw_obj = NULL;
857 }
858}
859
b1023571
KW		 860static int gfx_v9_0_mec_init(struct amdgpu_device *adev)
861{
862 int r;
863 u32 *hpd;
864 const __le32 *fw_data;
865 unsigned fw_size;
866 u32 *fw;
42794b27 867 size_t mec_hpd_size;
b1023571
KW		 868
869 const struct gfx_firmware_header_v1_0 *mec_hdr;
870
78c16834
AR		 871 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
872
78c16834 873 /* take ownership of the relevant compute queues */
41f6a99a 874 amdgpu_gfx_compute_queue_acquire(adev);
78c16834 875 mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE;
b1023571
KW		 876
877 if (adev->gfx.mec.hpd_eop_obj == NULL) {
878 r = amdgpu_bo_create(adev,
42794b27 879 mec_hpd_size,
b1023571
KW		 880 PAGE_SIZE, true,
881 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
882 &adev->gfx.mec.hpd_eop_obj);
883 if (r) {
884 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
885 return r;
886 }
887 }
888
889 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
890 if (unlikely(r != 0)) {
891 gfx_v9_0_mec_fini(adev);
892 return r;
893 }
894 r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
895 &adev->gfx.mec.hpd_eop_gpu_addr);
896 if (r) {
897 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
898 gfx_v9_0_mec_fini(adev);
899 return r;
900 }
901 r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
902 if (r) {
903 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
904 gfx_v9_0_mec_fini(adev);
905 return r;
906 }
907
908 memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size);
909
910 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
911 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
912
913 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
914
915 fw_data = (const __le32 *)
916 (adev->gfx.mec_fw->data +
917 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
918 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
919
920 if (adev->gfx.mec.mec_fw_obj == NULL) {
921 r = amdgpu_bo_create(adev,
922 mec_hdr->header.ucode_size_bytes,
923 PAGE_SIZE, true,
924 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
925 &adev->gfx.mec.mec_fw_obj);
926 if (r) {
927 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r);
928 return r;
929 }
930 }
931
932 r = amdgpu_bo_reserve(adev->gfx.mec.mec_fw_obj, false);
933 if (unlikely(r != 0)) {
934 gfx_v9_0_mec_fini(adev);
935 return r;
936 }
937 r = amdgpu_bo_pin(adev->gfx.mec.mec_fw_obj, AMDGPU_GEM_DOMAIN_GTT,
938 &adev->gfx.mec.mec_fw_gpu_addr);
939 if (r) {
940 dev_warn(adev->dev, "(%d) pin mec firmware bo failed\n", r);
941 gfx_v9_0_mec_fini(adev);
942 return r;
943 }
944 r = amdgpu_bo_kmap(adev->gfx.mec.mec_fw_obj, (void **)&fw);
945 if (r) {
946 dev_warn(adev->dev, "(%d) map firmware bo failed\n", r);
947 gfx_v9_0_mec_fini(adev);
948 return r;
949 }
950 memcpy(fw, fw_data, fw_size);
951
952 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
953 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
954
955
956 return 0;
957}
958
959static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
960{
5e78835a 961 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
b1023571
KW		 962 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
963 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
964 (address << SQ_IND_INDEX__INDEX__SHIFT) |
965 (SQ_IND_INDEX__FORCE_READ_MASK));
5e78835a 966 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
b1023571
KW		 967}
968
969static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
970 uint32_t wave, uint32_t thread,
971 uint32_t regno, uint32_t num, uint32_t *out)
972{
5e78835a 973 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
b1023571
KW		 974 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
975 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
976 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
977 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
978 (SQ_IND_INDEX__FORCE_READ_MASK) |
979 (SQ_IND_INDEX__AUTO_INCR_MASK));
980 while (num--)
5e78835a 981 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
b1023571
KW		 982}
983
984static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
985{
986 /* type 1 wave data */
987 dst[(*no_fields)++] = 1;
988 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
989 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
990 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
991 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
992 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
993 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
994 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
995 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
996 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
997 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
998 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
999 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
1000 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
1001 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
1002}
1003
1004static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
1005 uint32_t wave, uint32_t start,
1006 uint32_t size, uint32_t *dst)
1007{
1008 wave_read_regs(
1009 adev, simd, wave, 0,
1010 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
1011}
1012
1013
1014static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = {
1015 .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter,
1016 .select_se_sh = &gfx_v9_0_select_se_sh,
1017 .read_wave_data = &gfx_v9_0_read_wave_data,
1018 .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs,
1019};
1020
1021static void gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
1022{
1023 u32 gb_addr_config;
1024
1025 adev->gfx.funcs = &gfx_v9_0_gfx_funcs;
1026
1027 switch (adev->asic_type) {
1028 case CHIP_VEGA10:
b1023571 1029 adev->gfx.config.max_hw_contexts = 8;
b1023571
KW		 1030 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1031 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1032 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1033 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1034 gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN;
1035 break;
5cf7433d
CZ		 1036 case CHIP_RAVEN:
1037 adev->gfx.config.max_hw_contexts = 8;
1038 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1039 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1040 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1041 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1042 gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN;
1043 break;
b1023571
KW		 1044 default:
1045 BUG();
1046 break;
1047 }
1048
1049 adev->gfx.config.gb_addr_config = gb_addr_config;
1050
1051 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
1052 REG_GET_FIELD(
1053 adev->gfx.config.gb_addr_config,
1054 GB_ADDR_CONFIG,
1055 NUM_PIPES);
ad7d0ff3
AD		 1056
1057 adev->gfx.config.max_tile_pipes =
1058 adev->gfx.config.gb_addr_config_fields.num_pipes;
1059
b1023571
KW		 1060 adev->gfx.config.gb_addr_config_fields.num_banks = 1 <<
1061 REG_GET_FIELD(
1062 adev->gfx.config.gb_addr_config,
1063 GB_ADDR_CONFIG,
1064 NUM_BANKS);
1065 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
1066 REG_GET_FIELD(
1067 adev->gfx.config.gb_addr_config,
1068 GB_ADDR_CONFIG,
1069 MAX_COMPRESSED_FRAGS);
1070 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
1071 REG_GET_FIELD(
1072 adev->gfx.config.gb_addr_config,
1073 GB_ADDR_CONFIG,
1074 NUM_RB_PER_SE);
1075 adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
1076 REG_GET_FIELD(
1077 adev->gfx.config.gb_addr_config,
1078 GB_ADDR_CONFIG,
1079 NUM_SHADER_ENGINES);
1080 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
1081 REG_GET_FIELD(
1082 adev->gfx.config.gb_addr_config,
1083 GB_ADDR_CONFIG,
1084 PIPE_INTERLEAVE_SIZE));
1085}
1086
1087static int gfx_v9_0_ngg_create_buf(struct amdgpu_device *adev,
1088 struct amdgpu_ngg_buf *ngg_buf,
1089 int size_se,
1090 int default_size_se)
1091{
1092 int r;
1093
1094 if (size_se < 0) {
1095 dev_err(adev->dev, "Buffer size is invalid: %d\n", size_se);
1096 return -EINVAL;
1097 }
1098 size_se = size_se ? size_se : default_size_se;
1099
42ce2243 1100 ngg_buf->size = size_se * adev->gfx.config.max_shader_engines;
b1023571
KW		 1101 r = amdgpu_bo_create_kernel(adev, ngg_buf->size,
1102 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1103 &ngg_buf->bo,
1104 &ngg_buf->gpu_addr,
1105 NULL);
1106 if (r) {
1107 dev_err(adev->dev, "(%d) failed to create NGG buffer\n", r);
1108 return r;
1109 }
1110 ngg_buf->bo_size = amdgpu_bo_size(ngg_buf->bo);
1111
1112 return r;
1113}
1114
1115static int gfx_v9_0_ngg_fini(struct amdgpu_device *adev)
1116{
1117 int i;
1118
1119 for (i = 0; i < NGG_BUF_MAX; i++)
1120 amdgpu_bo_free_kernel(&adev->gfx.ngg.buf[i].bo,
1121 &adev->gfx.ngg.buf[i].gpu_addr,
1122 NULL);
1123
1124 memset(&adev->gfx.ngg.buf[0], 0,
1125 sizeof(struct amdgpu_ngg_buf) * NGG_BUF_MAX);
1126
1127 adev->gfx.ngg.init = false;
1128
1129 return 0;
1130}
1131
1132static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)
1133{
1134 int r;
1135
1136 if (!amdgpu_ngg || adev->gfx.ngg.init == true)
1137 return 0;
1138
1139 /* GDS reserve memory: 64 bytes alignment */
1140 adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40);
1141 adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size;
1142 adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size;
1143 adev->gfx.ngg.gds_reserve_addr = amdgpu_gds_reg_offset[0].mem_base;
1144 adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size;
1145
1146 /* Primitive Buffer */
af8baf15 1147 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM],
b1023571
KW		 1148 amdgpu_prim_buf_per_se,
1149 64 * 1024);
1150 if (r) {
1151 dev_err(adev->dev, "Failed to create Primitive Buffer\n");
1152 goto err;
1153 }
1154
1155 /* Position Buffer */
af8baf15 1156 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_POS],
b1023571
KW		 1157 amdgpu_pos_buf_per_se,
1158 256 * 1024);
1159 if (r) {
1160 dev_err(adev->dev, "Failed to create Position Buffer\n");
1161 goto err;
1162 }
1163
1164 /* Control Sideband */
af8baf15 1165 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_CNTL],
b1023571
KW		 1166 amdgpu_cntl_sb_buf_per_se,
1167 256);
1168 if (r) {
1169 dev_err(adev->dev, "Failed to create Control Sideband Buffer\n");
1170 goto err;
1171 }
1172
1173 /* Parameter Cache, not created by default */
1174 if (amdgpu_param_buf_per_se <= 0)
1175 goto out;
1176
af8baf15 1177 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PARAM],
b1023571
KW		 1178 amdgpu_param_buf_per_se,
1179 512 * 1024);
1180 if (r) {
1181 dev_err(adev->dev, "Failed to create Parameter Cache\n");
1182 goto err;
1183 }
1184
1185out:
1186 adev->gfx.ngg.init = true;
1187 return 0;
1188err:
1189 gfx_v9_0_ngg_fini(adev);
1190 return r;
1191}
1192
1193static int gfx_v9_0_ngg_en(struct amdgpu_device *adev)
1194{
1195 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
1196 int r;
1197 u32 data;
1198 u32 size;
1199 u32 base;
1200
1201 if (!amdgpu_ngg)
1202 return 0;
1203
1204 /* Program buffer size */
1205 data = 0;
af8baf15 1206 size = adev->gfx.ngg.buf[NGG_PRIM].size / 256;
b1023571
KW		 1207 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, INDEX_BUF_SIZE, size);
1208
af8baf15 1209 size = adev->gfx.ngg.buf[NGG_POS].size / 256;
b1023571
KW		 1210 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, POS_BUF_SIZE, size);
1211
5e78835a 1212 WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_1, data);
b1023571
KW		 1213
1214 data = 0;
af8baf15 1215 size = adev->gfx.ngg.buf[NGG_CNTL].size / 256;
b1023571
KW		 1216 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, CNTL_SB_BUF_SIZE, size);
1217
af8baf15 1218 size = adev->gfx.ngg.buf[NGG_PARAM].size / 1024;
b1023571
KW		 1219 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, PARAM_BUF_SIZE, size);
1220
5e78835a 1221 WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_2, data);
b1023571
KW		 1222
1223 /* Program buffer base address */
af8baf15 1224 base = lower_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
b1023571 1225 data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE, BASE, base);
5e78835a 1226 WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE, data);
b1023571 1227
af8baf15 1228 base = upper_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
b1023571 1229 data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE_HI, BASE_HI, base);
5e78835a 1230 WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE_HI, data);
b1023571 1231
af8baf15 1232 base = lower_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
b1023571 1233 data = REG_SET_FIELD(0, WD_POS_BUF_BASE, BASE, base);
5e78835a 1234 WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE, data);
b1023571 1235
af8baf15 1236 base = upper_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
b1023571 1237 data = REG_SET_FIELD(0, WD_POS_BUF_BASE_HI, BASE_HI, base);
5e78835a 1238 WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE_HI, data);
b1023571 1239
af8baf15 1240 base = lower_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
b1023571 1241 data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE, BASE, base);
5e78835a 1242 WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE, data);
b1023571 1243
af8baf15 1244 base = upper_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
b1023571 1245 data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE_HI, BASE_HI, base);
5e78835a 1246 WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE_HI, data);
b1023571
KW		 1247
1248 /* Clear GDS reserved memory */
1249 r = amdgpu_ring_alloc(ring, 17);
1250 if (r) {
1251 DRM_ERROR("amdgpu: NGG failed to lock ring %d (%d).\n",
1252 ring->idx, r);
1253 return r;
1254 }
1255
1256 gfx_v9_0_write_data_to_reg(ring, 0, false,
1257 amdgpu_gds_reg_offset[0].mem_size,
1258 (adev->gds.mem.total_size +
1259 adev->gfx.ngg.gds_reserve_size) >>
1260 AMDGPU_GDS_SHIFT);
1261
1262 amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
1263 amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
1264 PACKET3_DMA_DATA_SRC_SEL(2)));
1265 amdgpu_ring_write(ring, 0);
1266 amdgpu_ring_write(ring, 0);
1267 amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr);
1268 amdgpu_ring_write(ring, 0);
1269 amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_size);
1270
1271
1272 gfx_v9_0_write_data_to_reg(ring, 0, false,
1273 amdgpu_gds_reg_offset[0].mem_size, 0);
1274
1275 amdgpu_ring_commit(ring);
1276
1277 return 0;
1278}
1279
1361f455
AD		 1280static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
1281 int mec, int pipe, int queue)
1282{
1283 int r;
1284 unsigned irq_type;
1285 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
1286
1287 ring = &adev->gfx.compute_ring[ring_id];
1288
1289 /* mec0 is me1 */
1290 ring->me = mec + 1;
1291 ring->pipe = pipe;
1292 ring->queue = queue;
1293
1294 ring->ring_obj = NULL;
1295 ring->use_doorbell = true;
1296 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + ring_id;
1297 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
1298 + (ring_id * GFX9_MEC_HPD_SIZE);
1299 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1300
1301 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
1302 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
1303 + ring->pipe;
1304
1305 /* type-2 packets are deprecated on MEC, use type-3 instead */
1306 r = amdgpu_ring_init(adev, ring, 1024,
1307 &adev->gfx.eop_irq, irq_type);
1308 if (r)
1309 return r;
1310
1311
1312 return 0;
1313}
1314
b1023571
KW		 1315static int gfx_v9_0_sw_init(void *handle)
1316{
1361f455 1317 int i, j, k, r, ring_id;
b1023571 1318 struct amdgpu_ring *ring;
ac104e99 1319 struct amdgpu_kiq *kiq;
b1023571
KW		 1320 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1321
4853bbb6
AD		 1322 switch (adev->asic_type) {
1323 case CHIP_VEGA10:
1324 case CHIP_RAVEN:
1325 adev->gfx.mec.num_mec = 2;
1326 break;
1327 default:
1328 adev->gfx.mec.num_mec = 1;
1329 break;
1330 }
1331
1332 adev->gfx.mec.num_pipe_per_mec = 4;
1333 adev->gfx.mec.num_queue_per_pipe = 8;
1334
97031e25
XY		 1335 /* KIQ event */
1336 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 178, &adev->gfx.kiq.irq);
1337 if (r)
1338 return r;
1339
b1023571
KW		 1340 /* EOP Event */
1341 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 181, &adev->gfx.eop_irq);
1342 if (r)
1343 return r;
1344
1345 /* Privileged reg */
1346 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 184,
1347 &adev->gfx.priv_reg_irq);
1348 if (r)
1349 return r;
1350
1351 /* Privileged inst */
1352 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 185,
1353 &adev->gfx.priv_inst_irq);
1354 if (r)
1355 return r;
1356
1357 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1358
1359 gfx_v9_0_scratch_init(adev);
1360
1361 r = gfx_v9_0_init_microcode(adev);
1362 if (r) {
1363 DRM_ERROR("Failed to load gfx firmware!\n");
1364 return r;
1365 }
1366
c9719c69
HZ		 1367 r = gfx_v9_0_rlc_init(adev);
1368 if (r) {
1369 DRM_ERROR("Failed to init rlc BOs!\n");
1370 return r;
1371 }
1372
b1023571
KW		 1373 r = gfx_v9_0_mec_init(adev);
1374 if (r) {
1375 DRM_ERROR("Failed to init MEC BOs!\n");
1376 return r;
1377 }
1378
1379 /* set up the gfx ring */
1380 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
1381 ring = &adev->gfx.gfx_ring[i];
1382 ring->ring_obj = NULL;
1383 sprintf(ring->name, "gfx");
1384 ring->use_doorbell = true;
1385 ring->doorbell_index = AMDGPU_DOORBELL64_GFX_RING0 << 1;
1386 r = amdgpu_ring_init(adev, ring, 1024,
1387 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
1388 if (r)
1389 return r;
1390 }
1391
1361f455
AD		 1392 /* set up the compute queues - allocate horizontally across pipes */
1393 ring_id = 0;
1394 for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
1395 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
1396 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
2db0cdbe 1397 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j))
1361f455
AD		 1398 continue;
1399
1400 r = gfx_v9_0_compute_ring_init(adev,
1401 ring_id,
1402 i, k, j);
1403 if (r)
1404 return r;
1405
1406 ring_id++;
1407 }
b1023571 1408 }
b1023571
KW		 1409 }
1410
71c37505 1411 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE);
e30a5223
AD		 1412 if (r) {
1413 DRM_ERROR("Failed to init KIQ BOs!\n");
1414 return r;
1415 }
ac104e99 1416
e30a5223 1417 kiq = &adev->gfx.kiq;
71c37505 1418 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
e30a5223
AD		 1419 if (r)
1420 return r;
464826d6 1421
e30a5223 1422 /* create MQD for all compute queues as wel as KIQ for SRIOV case */
b9683c21 1423 r = amdgpu_gfx_compute_mqd_sw_init(adev, sizeof(struct v9_mqd));
e30a5223
AD		 1424 if (r)
1425 return r;
ac104e99 1426
b1023571
KW		 1427 /* reserve GDS, GWS and OA resource for gfx */
1428 r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size,
1429 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS,
1430 &adev->gds.gds_gfx_bo, NULL, NULL);
1431 if (r)
1432 return r;
1433
1434 r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size,
1435 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS,
1436 &adev->gds.gws_gfx_bo, NULL, NULL);
1437 if (r)
1438 return r;
1439
1440 r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size,
1441 PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA,
1442 &adev->gds.oa_gfx_bo, NULL, NULL);
1443 if (r)
1444 return r;
1445
1446 adev->gfx.ce_ram_size = 0x8000;
1447
1448 gfx_v9_0_gpu_early_init(adev);
1449
1450 r = gfx_v9_0_ngg_init(adev);
1451 if (r)
1452 return r;
1453
1454 return 0;
1455}
1456
1457
1458static int gfx_v9_0_sw_fini(void *handle)
1459{
1460 int i;
1461 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1462
1463 amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL);
1464 amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL);
1465 amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL);
1466
1467 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1468 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1469 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1470 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1471
b9683c21 1472 amdgpu_gfx_compute_mqd_sw_fini(adev);
71c37505
AD		 1473 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
1474 amdgpu_gfx_kiq_fini(adev);
ac104e99 1475
b1023571
KW		 1476 gfx_v9_0_mec_fini(adev);
1477 gfx_v9_0_ngg_fini(adev);
1478
1479 return 0;
1480}
1481
1482
1483static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev)
1484{
1485 /* TODO */
1486}
1487
1488static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance)
1489{
1490 u32 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1491
1492 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) {
1493 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1494 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1495 } else if (se_num == 0xffffffff) {
1496 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1497 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1498 } else if (sh_num == 0xffffffff) {
1499 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1500 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1501 } else {
1502 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1503 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1504 }
5e78835a 1505 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
b1023571
KW		 1506}
1507
b1023571
KW		 1508static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1509{
1510 u32 data, mask;
1511
5e78835a
TSD		 1512 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
1513 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
b1023571
KW		 1514
1515 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1516 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1517
378506a7
AD		 1518 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
1519 adev->gfx.config.max_sh_per_se);
b1023571
KW		 1520
1521 return (~data) & mask;
1522}
1523
1524static void gfx_v9_0_setup_rb(struct amdgpu_device *adev)
1525{
1526 int i, j;
2572c24c 1527 u32 data;
b1023571
KW		 1528 u32 active_rbs = 0;
1529 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1530 adev->gfx.config.max_sh_per_se;
1531
1532 mutex_lock(&adev->grbm_idx_mutex);
1533 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1534 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1535 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1536 data = gfx_v9_0_get_rb_active_bitmap(adev);
1537 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1538 rb_bitmap_width_per_sh);
1539 }
1540 }
1541 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1542 mutex_unlock(&adev->grbm_idx_mutex);
1543
1544 adev->gfx.config.backend_enable_mask = active_rbs;
2572c24c 1545 adev->gfx.config.num_rbs = hweight32(active_rbs);
b1023571
KW		 1546}
1547
1548#define DEFAULT_SH_MEM_BASES (0x6000)
1549#define FIRST_COMPUTE_VMID (8)
1550#define LAST_COMPUTE_VMID (16)
1551static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
1552{
1553 int i;
1554 uint32_t sh_mem_config;
1555 uint32_t sh_mem_bases;
1556
1557 /*
1558 * Configure apertures:
1559 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
1560 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
1561 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
1562 */
1563 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1564
1565 sh_mem_config = SH_MEM_ADDRESS_MODE_64 |
1566 SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
eaa05d52 1567 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
b1023571
KW		 1568
1569 mutex_lock(&adev->srbm_mutex);
1570 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1571 soc15_grbm_select(adev, 0, 0, 0, i);
1572 /* CP and shaders */
5e78835a
TSD		 1573 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
1574 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
b1023571
KW		 1575 }
1576 soc15_grbm_select(adev, 0, 0, 0, 0);
1577 mutex_unlock(&adev->srbm_mutex);
1578}
1579
1580static void gfx_v9_0_gpu_init(struct amdgpu_device *adev)
1581{
1582 u32 tmp;
1583 int i;
1584
40f06773 1585 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
b1023571
KW		 1586
1587 gfx_v9_0_tiling_mode_table_init(adev);
1588
1589 gfx_v9_0_setup_rb(adev);
1590 gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info);
1591
1592 /* XXX SH_MEM regs */
1593 /* where to put LDS, scratch, GPUVM in FSA64 space */
1594 mutex_lock(&adev->srbm_mutex);
1595 for (i = 0; i < 16; i++) {
1596 soc15_grbm_select(adev, 0, 0, 0, i);
1597 /* CP and shaders */
1598 tmp = 0;
1599 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
1600 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
5e78835a
TSD		 1601 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
1602 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, 0);
b1023571
KW		 1603 }
1604 soc15_grbm_select(adev, 0, 0, 0, 0);
1605
1606 mutex_unlock(&adev->srbm_mutex);
1607
1608 gfx_v9_0_init_compute_vmid(adev);
1609
1610 mutex_lock(&adev->grbm_idx_mutex);
1611 /*
1612 * making sure that the following register writes will be broadcasted
1613 * to all the shaders
1614 */
1615 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1616
5e78835a 1617 WREG32_SOC15(GC, 0, mmPA_SC_FIFO_SIZE,
b1023571
KW		 1618 (adev->gfx.config.sc_prim_fifo_size_frontend <<
1619 PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1620 (adev->gfx.config.sc_prim_fifo_size_backend <<
1621 PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1622 (adev->gfx.config.sc_hiz_tile_fifo_size <<
1623 PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1624 (adev->gfx.config.sc_earlyz_tile_fifo_size <<
1625 PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
1626 mutex_unlock(&adev->grbm_idx_mutex);
1627
1628}
1629
1630static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
1631{
1632 u32 i, j, k;
1633 u32 mask;
1634
1635 mutex_lock(&adev->grbm_idx_mutex);
1636 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1637 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1638 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1639 for (k = 0; k < adev->usec_timeout; k++) {
5e78835a 1640 if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0)
b1023571
KW		 1641 break;
1642 udelay(1);
1643 }
1644 }
1645 }
1646 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1647 mutex_unlock(&adev->grbm_idx_mutex);
1648
1649 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
1650 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
1651 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
1652 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
1653 for (k = 0; k < adev->usec_timeout; k++) {
5e78835a 1654 if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
b1023571
KW		 1655 break;
1656 udelay(1);
1657 }
1658}
1659
1660static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1661 bool enable)
1662{
5e78835a 1663 u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
b1023571 1664
b1023571
KW		 1665 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
1666 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
1667 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
1668 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
1669
5e78835a 1670 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
b1023571
KW		 1671}
1672
6bce4667
HZ		 1673static void gfx_v9_0_init_csb(struct amdgpu_device *adev)
1674{
1675 /* csib */
1676 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI),
1677 adev->gfx.rlc.clear_state_gpu_addr >> 32);
1678 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO),
1679 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
1680 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH),
1681 adev->gfx.rlc.clear_state_size);
1682}
1683
1684static void gfx_v9_0_parse_ind_reg_list(int *register_list_format,
1685 int indirect_offset,
1686 int list_size,
1687 int *unique_indirect_regs,
1688 int *unique_indirect_reg_count,
1689 int max_indirect_reg_count,
1690 int *indirect_start_offsets,
1691 int *indirect_start_offsets_count,
1692 int max_indirect_start_offsets_count)
1693{
1694 int idx;
1695 bool new_entry = true;
1696
1697 for (; indirect_offset < list_size; indirect_offset++) {
1698
1699 if (new_entry) {
1700 new_entry = false;
1701 indirect_start_offsets[*indirect_start_offsets_count] = indirect_offset;
1702 *indirect_start_offsets_count = *indirect_start_offsets_count + 1;
1703 BUG_ON(*indirect_start_offsets_count >= max_indirect_start_offsets_count);
1704 }
1705
1706 if (register_list_format[indirect_offset] == 0xFFFFFFFF) {
1707 new_entry = true;
1708 continue;
1709 }
1710
1711 indirect_offset += 2;
1712
1713 /* look for the matching indice */
1714 for (idx = 0; idx < *unique_indirect_reg_count; idx++) {
1715 if (unique_indirect_regs[idx] ==
1716 register_list_format[indirect_offset])
1717 break;
1718 }
1719
1720 if (idx >= *unique_indirect_reg_count) {
1721 unique_indirect_regs[*unique_indirect_reg_count] =
1722 register_list_format[indirect_offset];
1723 idx = *unique_indirect_reg_count;
1724 *unique_indirect_reg_count = *unique_indirect_reg_count + 1;
1725 BUG_ON(*unique_indirect_reg_count >= max_indirect_reg_count);
1726 }
1727
1728 register_list_format[indirect_offset] = idx;
1729 }
1730}
1731
1732static int gfx_v9_0_init_rlc_save_restore_list(struct amdgpu_device *adev)
1733{
1734 int unique_indirect_regs[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
1735 int unique_indirect_reg_count = 0;
1736
1737 int indirect_start_offsets[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
1738 int indirect_start_offsets_count = 0;
1739
1740 int list_size = 0;
1741 int i = 0;
1742 u32 tmp = 0;
1743
1744 u32 *register_list_format =
1745 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL);
1746 if (!register_list_format)
1747 return -ENOMEM;
1748 memcpy(register_list_format, adev->gfx.rlc.register_list_format,
1749 adev->gfx.rlc.reg_list_format_size_bytes);
1750
1751 /* setup unique_indirect_regs array and indirect_start_offsets array */
1752 gfx_v9_0_parse_ind_reg_list(register_list_format,
1753 GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH,
1754 adev->gfx.rlc.reg_list_format_size_bytes >> 2,
1755 unique_indirect_regs,
1756 &unique_indirect_reg_count,
1757 sizeof(unique_indirect_regs)/sizeof(int),
1758 indirect_start_offsets,
1759 &indirect_start_offsets_count,
1760 sizeof(indirect_start_offsets)/sizeof(int));
1761
1762 /* enable auto inc in case it is disabled */
1763 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
1764 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
1765 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
1766
1767 /* write register_restore table to offset 0x0 using RLC_SRM_ARAM_ADDR/DATA */
1768 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR),
1769 RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET);
1770 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
1771 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),
1772 adev->gfx.rlc.register_restore[i]);
1773
1774 /* load direct register */
1775 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR), 0);
1776 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
1777 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),
1778 adev->gfx.rlc.register_restore[i]);
1779
1780 /* load indirect register */
1781 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1782 adev->gfx.rlc.reg_list_format_start);
1783 for (i = 0; i < adev->gfx.rlc.reg_list_format_size_bytes >> 2; i++)
1784 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
1785 register_list_format[i]);
1786
1787 /* set save/restore list size */
1788 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2;
1789 list_size = list_size >> 1;
1790 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1791 adev->gfx.rlc.reg_restore_list_size);
1792 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size);
1793
1794 /* write the starting offsets to RLC scratch ram */
1795 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1796 adev->gfx.rlc.starting_offsets_start);
1797 for (i = 0; i < sizeof(indirect_start_offsets)/sizeof(int); i++)
1798 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
1799 indirect_start_offsets[i]);
1800
1801 /* load unique indirect regs*/
1802 for (i = 0; i < sizeof(unique_indirect_regs)/sizeof(int); i++) {
1803 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0) + i,
1804 unique_indirect_regs[i] & 0x3FFFF);
1805 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0) + i,
1806 unique_indirect_regs[i] >> 20);
1807 }
1808
1809 kfree(register_list_format);
1810 return 0;
1811}
1812
1813static void gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev)
1814{
1815 u32 tmp = 0;
1816
1817 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
1818 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
1819 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
1820}
1821
91d3130a
HZ		 1822static void pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device *adev,
1823 bool enable)
1824{
1825 uint32_t data = 0;
1826 uint32_t default_data = 0;
1827
1828 default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS));
1829 if (enable == true) {
1830 /* enable GFXIP control over CGPG */
1831 data |= PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
1832 if(default_data != data)
1833 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
1834
1835 /* update status */
1836 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK;
1837 data |= (2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT);
1838 if(default_data != data)
1839 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
1840 } else {
1841 /* restore GFXIP control over GCPG */
1842 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
1843 if(default_data != data)
1844 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
1845 }
1846}
1847
1848static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev)
1849{
1850 uint32_t data = 0;
1851
1852 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
1853 AMD_PG_SUPPORT_GFX_SMG |
1854 AMD_PG_SUPPORT_GFX_DMG)) {
1855 /* init IDLE_POLL_COUNT = 60 */
1856 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL));
1857 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
1858 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
1859 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data);
1860
1861 /* init RLC PG Delay */
1862 data = 0;
1863 data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT);
1864 data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT);
1865 data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT);
1866 data |= (0x40 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT);
1867 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data);
1868
1869 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2));
1870 data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK;
1871 data |= (0x4 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT);
1872 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data);
1873
1874 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3));
1875 data &= ~RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK;
1876 data |= (0xff << RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT);
1877 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data);
1878
1879 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL));
1880 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
1881
1882 /* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */
1883 data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
1884 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data);
1885
1886 pwr_10_0_gfxip_control_over_cgpg(adev, true);
1887 }
1888}
1889
ed5ad1e4
HZ		 1890static void gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev,
1891 bool enable)
1892{
1893 uint32_t data = 0;
1894 uint32_t default_data = 0;
1895
1896 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
1897
1898 if (enable == true) {
1899 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
1900 if (default_data != data)
1901 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1902 } else {
1903 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
1904 if(default_data != data)
1905 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1906 }
1907}
1908
1909static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,
1910 bool enable)
1911{
1912 uint32_t data = 0;
1913 uint32_t default_data = 0;
1914
1915 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
1916
1917 if (enable == true) {
1918 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
1919 if(default_data != data)
1920 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1921 } else {
1922 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
1923 if(default_data != data)
1924 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1925 }
1926}
1927
3a6cc477
HZ		 1928static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev,
1929 bool enable)
1930{
1931 uint32_t data = 0;
1932 uint32_t default_data = 0;
1933
1934 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
1935
1936 if (enable == true) {
1937 data &= ~RLC_PG_CNTL__CP_PG_DISABLE_MASK;
1938 if(default_data != data)
1939 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1940 } else {
1941 data |= RLC_PG_CNTL__CP_PG_DISABLE_MASK;
1942 if(default_data != data)
1943 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1944 }
1945}
1946
197f95c8
HZ		 1947static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev,
1948 bool enable)
1949{
1950 uint32_t data, default_data;
1951
1952 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
1953 if (enable == true)
1954 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
1955 else
1956 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
1957 if(default_data != data)
1958 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1959}
1960
1961static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev,
1962 bool enable)
1963{
1964 uint32_t data, default_data;
1965
1966 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
1967 if (enable == true)
1968 data |= RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK;
1969 else
1970 data &= ~RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK;
1971 if(default_data != data)
1972 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1973
1974 if (!enable)
1975 /* read any GFX register to wake up GFX */
1976 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL));
1977}
1978
18924c71
HZ		 1979void gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
1980 bool enable)
1981{
1982 uint32_t data, default_data;
1983
1984 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
1985 if (enable == true)
1986 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
1987 else
1988 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
1989 if(default_data != data)
1990 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1991}
1992
1993void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,
1994 bool enable)
1995{
1996 uint32_t data, default_data;
1997
1998 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
1999 if (enable == true)
2000 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
2001 else
2002 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
2003 if(default_data != data)
2004 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2005}
2006
6bce4667
HZ		 2007static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
2008{
2009 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2010 AMD_PG_SUPPORT_GFX_SMG |
2011 AMD_PG_SUPPORT_GFX_DMG |
2012 AMD_PG_SUPPORT_CP |
2013 AMD_PG_SUPPORT_GDS |
2014 AMD_PG_SUPPORT_RLC_SMU_HS)) {
2015 gfx_v9_0_init_csb(adev);
2016 gfx_v9_0_init_rlc_save_restore_list(adev);
2017 gfx_v9_0_enable_save_restore_machine(adev);
91d3130a
HZ		 2018
2019 if (adev->asic_type == CHIP_RAVEN) {
2020 WREG32(mmRLC_JUMP_TABLE_RESTORE,
2021 adev->gfx.rlc.cp_table_gpu_addr >> 8);
2022 gfx_v9_0_init_gfx_power_gating(adev);
3a6cc477 2023
ed5ad1e4
HZ		 2024 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
2025 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
2026 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
2027 } else {
2028 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false);
2029 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false);
2030 }
3a6cc477
HZ		 2031
2032 if (adev->pg_flags & AMD_PG_SUPPORT_CP)
2033 gfx_v9_0_enable_cp_power_gating(adev, true);
2034 else
2035 gfx_v9_0_enable_cp_power_gating(adev, false);
91d3130a 2036 }
6bce4667
HZ		 2037 }
2038}
2039
b1023571
KW		 2040void gfx_v9_0_rlc_stop(struct amdgpu_device *adev)
2041{
5e78835a 2042 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
b1023571
KW		 2043
2044 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
5e78835a 2045 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
b1023571
KW		 2046
2047 gfx_v9_0_enable_gui_idle_interrupt(adev, false);
2048
2049 gfx_v9_0_wait_for_rlc_serdes(adev);
2050}
2051
2052static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev)
2053{
596c8e8b 2054 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
b1023571 2055 udelay(50);
596c8e8b 2056 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
b1023571
KW		 2057 udelay(50);
2058}
2059
2060static void gfx_v9_0_rlc_start(struct amdgpu_device *adev)
2061{
2062#ifdef AMDGPU_RLC_DEBUG_RETRY
2063 u32 rlc_ucode_ver;
2064#endif
b1023571 2065
342cda25 2066 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
b1023571
KW		 2067
2068 /* carrizo do enable cp interrupt after cp inited */
2069 if (!(adev->flags & AMD_IS_APU))
2070 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
2071
2072 udelay(50);
2073
2074#ifdef AMDGPU_RLC_DEBUG_RETRY
2075 /* RLC_GPM_GENERAL_6 : RLC Ucode version */
5e78835a 2076 rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6);
b1023571
KW		 2077 if(rlc_ucode_ver == 0x108) {
2078 DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n",
2079 rlc_ucode_ver, adev->gfx.rlc_fw_version);
2080 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles,
2081 * default is 0x9C4 to create a 100us interval */
5e78835a 2082 WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4);
b1023571 2083 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr
eaa05d52 2084 * to disable the page fault retry interrupts, default is
b1023571 2085 * 0x100 (256) */
5e78835a 2086 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100);
b1023571
KW		 2087 }
2088#endif
2089}
2090
2091static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev)
2092{
2093 const struct rlc_firmware_header_v2_0 *hdr;
2094 const __le32 *fw_data;
2095 unsigned i, fw_size;
2096
2097 if (!adev->gfx.rlc_fw)
2098 return -EINVAL;
2099
2100 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
2101 amdgpu_ucode_print_rlc_hdr(&hdr->header);
2102
2103 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2104 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2105 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2106
5e78835a 2107 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
b1023571
KW		 2108 RLCG_UCODE_LOADING_START_ADDRESS);
2109 for (i = 0; i < fw_size; i++)
5e78835a
TSD		 2110 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
2111 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
b1023571
KW		 2112
2113 return 0;
2114}
2115
2116static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
2117{
2118 int r;
2119
cfee05bc
ML		 2120 if (amdgpu_sriov_vf(adev))
2121 return 0;
2122
b1023571
KW		 2123 gfx_v9_0_rlc_stop(adev);
2124
2125 /* disable CG */
5e78835a 2126 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
b1023571
KW		 2127
2128 /* disable PG */
5e78835a 2129 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
b1023571
KW		 2130
2131 gfx_v9_0_rlc_reset(adev);
2132
6bce4667
HZ		 2133 gfx_v9_0_init_pg(adev);
2134
b1023571
KW		 2135 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2136 /* legacy rlc firmware loading */
2137 r = gfx_v9_0_rlc_load_microcode(adev);
2138 if (r)
2139 return r;
2140 }
2141
e8835e0e
HZ		 2142 if (adev->asic_type == CHIP_RAVEN) {
2143 if (amdgpu_lbpw != 0)
2144 gfx_v9_0_enable_lbpw(adev, true);
2145 else
2146 gfx_v9_0_enable_lbpw(adev, false);
2147 }
2148
b1023571
KW		 2149 gfx_v9_0_rlc_start(adev);
2150
2151 return 0;
2152}
2153
2154static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2155{
2156 int i;
5e78835a 2157 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
b1023571 2158
ea64468e
TSD		 2159 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
2160 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
2161 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
2162 if (!enable) {
b1023571
KW		 2163 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2164 adev->gfx.gfx_ring[i].ready = false;
2165 }
5e78835a 2166 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
b1023571
KW		 2167 udelay(50);
2168}
2169
2170static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2171{
2172 const struct gfx_firmware_header_v1_0 *pfp_hdr;
2173 const struct gfx_firmware_header_v1_0 *ce_hdr;
2174 const struct gfx_firmware_header_v1_0 *me_hdr;
2175 const __le32 *fw_data;
2176 unsigned i, fw_size;
2177
2178 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2179 return -EINVAL;
2180
2181 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2182 adev->gfx.pfp_fw->data;
2183 ce_hdr = (const struct gfx_firmware_header_v1_0 *)
2184 adev->gfx.ce_fw->data;
2185 me_hdr = (const struct gfx_firmware_header_v1_0 *)
2186 adev->gfx.me_fw->data;
2187
2188 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2189 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2190 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2191
2192 gfx_v9_0_cp_gfx_enable(adev, false);
2193
2194 /* PFP */
2195 fw_data = (const __le32 *)
2196 (adev->gfx.pfp_fw->data +
2197 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2198 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
5e78835a 2199 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, 0);
b1023571 2200 for (i = 0; i < fw_size; i++)
5e78835a
TSD		 2201 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2202 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
b1023571
KW		 2203
2204 /* CE */
2205 fw_data = (const __le32 *)
2206 (adev->gfx.ce_fw->data +
2207 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2208 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
5e78835a 2209 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, 0);
b1023571 2210 for (i = 0; i < fw_size; i++)
5e78835a
TSD		 2211 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2212 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
b1023571
KW		 2213
2214 /* ME */
2215 fw_data = (const __le32 *)
2216 (adev->gfx.me_fw->data +
2217 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2218 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
5e78835a 2219 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, 0);
b1023571 2220 for (i = 0; i < fw_size; i++)
5e78835a
TSD		 2221 WREG32_SOC15(GC, 0, mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2222 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
b1023571
KW		 2223
2224 return 0;
2225}
2226
b1023571
KW		 2227static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev)
2228{
2229 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2230 const struct cs_section_def *sect = NULL;
2231 const struct cs_extent_def *ext = NULL;
2232 int r, i;
2233
2234 /* init the CP */
5e78835a
TSD		 2235 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2236 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
b1023571
KW		 2237
2238 gfx_v9_0_cp_gfx_enable(adev, true);
2239
2240 r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4);
2241 if (r) {
2242 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2243 return r;
2244 }
2245
2246 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2247 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2248
2249 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2250 amdgpu_ring_write(ring, 0x80000000);
2251 amdgpu_ring_write(ring, 0x80000000);
2252
2253 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
2254 for (ext = sect->section; ext->extent != NULL; ++ext) {
2255 if (sect->id == SECT_CONTEXT) {
2256 amdgpu_ring_write(ring,
2257 PACKET3(PACKET3_SET_CONTEXT_REG,
2258 ext->reg_count));
2259 amdgpu_ring_write(ring,
2260 ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2261 for (i = 0; i < ext->reg_count; i++)
2262 amdgpu_ring_write(ring, ext->extent[i]);
2263 }
2264 }
2265 }
2266
2267 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2268 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2269
2270 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2271 amdgpu_ring_write(ring, 0);
2272
2273 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2274 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2275 amdgpu_ring_write(ring, 0x8000);
2276 amdgpu_ring_write(ring, 0x8000);
2277
2278 amdgpu_ring_commit(ring);
2279
2280 return 0;
2281}
2282
2283static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)
2284{
2285 struct amdgpu_ring *ring;
2286 u32 tmp;
2287 u32 rb_bufsz;
3fc08b61 2288 u64 rb_addr, rptr_addr, wptr_gpu_addr;
b1023571
KW		 2289
2290 /* Set the write pointer delay */
5e78835a 2291 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
b1023571
KW		 2292
2293 /* set the RB to use vmid 0 */
5e78835a 2294 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
b1023571
KW		 2295
2296 /* Set ring buffer size */
2297 ring = &adev->gfx.gfx_ring[0];
2298 rb_bufsz = order_base_2(ring->ring_size / 8);
2299 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
2300 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
2301#ifdef __BIG_ENDIAN
2302 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
2303#endif
5e78835a 2304 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
b1023571
KW		 2305
2306 /* Initialize the ring buffer's write pointers */
2307 ring->wptr = 0;
5e78835a
TSD		 2308 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2309 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
b1023571
KW		 2310
2311 /* set the wb address wether it's enabled or not */
2312 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
5e78835a
TSD		 2313 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2314 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
b1023571 2315
3fc08b61 2316 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
5e78835a
TSD		 2317 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr));
2318 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr));
3fc08b61 2319
b1023571 2320 mdelay(1);
5e78835a 2321 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
b1023571
KW		 2322
2323 rb_addr = ring->gpu_addr >> 8;
5e78835a
TSD		 2324 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
2325 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
b1023571 2326
5e78835a 2327 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
b1023571
KW		 2328 if (ring->use_doorbell) {
2329 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2330 DOORBELL_OFFSET, ring->doorbell_index);
2331 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2332 DOORBELL_EN, 1);
2333 } else {
2334 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);
2335 }
5e78835a 2336 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
b1023571
KW		 2337
2338 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
2339 DOORBELL_RANGE_LOWER, ring->doorbell_index);
5e78835a 2340 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
b1023571 2341
5e78835a 2342 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
b1023571
KW		 2343 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
2344
2345
2346 /* start the ring */
2347 gfx_v9_0_cp_gfx_start(adev);
2348 ring->ready = true;
2349
2350 return 0;
2351}
2352
2353static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2354{
2355 int i;
2356
2357 if (enable) {
5e78835a 2358 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
b1023571 2359 } else {
5e78835a 2360 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
b1023571
KW		 2361 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2362 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2363 adev->gfx.compute_ring[i].ready = false;
ac104e99 2364 adev->gfx.kiq.ring.ready = false;
b1023571
KW		 2365 }
2366 udelay(50);
2367}
2368
b1023571
KW		 2369static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2370{
2371 const struct gfx_firmware_header_v1_0 *mec_hdr;
2372 const __le32 *fw_data;
2373 unsigned i;
2374 u32 tmp;
2375
2376 if (!adev->gfx.mec_fw)
2377 return -EINVAL;
2378
2379 gfx_v9_0_cp_compute_enable(adev, false);
2380
2381 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2382 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2383
2384 fw_data = (const __le32 *)
2385 (adev->gfx.mec_fw->data +
2386 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2387 tmp = 0;
2388 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
2389 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
5e78835a 2390 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
b1023571 2391
5e78835a 2392 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
b1023571 2393 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000);
5e78835a 2394 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
b1023571 2395 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
eaa05d52 2396
b1023571 2397 /* MEC1 */
5e78835a 2398 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
b1023571
KW		 2399 mec_hdr->jt_offset);
2400 for (i = 0; i < mec_hdr->jt_size; i++)
5e78835a 2401 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
b1023571
KW		 2402 le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
2403
5e78835a 2404 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
b1023571
KW		 2405 adev->gfx.mec_fw_version);
2406 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
2407
2408 return 0;
2409}
2410
464826d6
XY		 2411/* KIQ functions */
2412static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring)
2413{
2414 uint32_t tmp;
2415 struct amdgpu_device *adev = ring->adev;
2416
2417 /* tell RLC which is KIQ queue */
5e78835a 2418 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
464826d6
XY		 2419 tmp &= 0xffffff00;
2420 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
5e78835a 2421 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
464826d6 2422 tmp |= 0x80;
5e78835a 2423 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
464826d6
XY		 2424}
2425
0f1dfd52 2426static int gfx_v9_0_kiq_kcq_enable(struct amdgpu_device *adev)
464826d6 2427{
bd3402ea 2428 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
2fdde9fa 2429 uint32_t scratch, tmp = 0;
de65513a 2430 uint64_t queue_mask = 0;
2fdde9fa
AD		 2431 int r, i;
2432
de65513a
AR		 2433 for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
2434 if (!test_bit(i, adev->gfx.mec.queue_bitmap))
2435 continue;
2436
2437 /* This situation may be hit in the future if a new HW
2438 * generation exposes more than 64 queues. If so, the
2439 * definition of queue_mask needs updating */
2440 if (WARN_ON(i > (sizeof(queue_mask)*8))) {
2441 DRM_ERROR("Invalid KCQ enabled: %d\n", i);
2442 break;
2443 }
2444
2445 queue_mask |= (1ull << i);
2446 }
2447
2fdde9fa
AD		 2448 r = amdgpu_gfx_scratch_get(adev, &scratch);
2449 if (r) {
2450 DRM_ERROR("Failed to get scratch reg (%d).\n", r);
2451 return r;
2452 }
2453 WREG32(scratch, 0xCAFEDEAD);
2454
0f1dfd52 2455 r = amdgpu_ring_alloc(kiq_ring, (7 * adev->gfx.num_compute_rings) + 11);
2fdde9fa
AD		 2456 if (r) {
2457 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
2458 amdgpu_gfx_scratch_free(adev, scratch);
2459 return r;
2460 }
464826d6 2461
0f1dfd52
AD		 2462 /* set resources */
2463 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
2464 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
2465 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
de65513a
AR		 2466 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
2467 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
0f1dfd52
AD		 2468 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
2469 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
2470 amdgpu_ring_write(kiq_ring, 0); /* oac mask */
2471 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
bd3402ea
AD		 2472 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2473 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2474 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
2475 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2476
2477 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
2478 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
2479 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
2480 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
2481 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
2482 PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
2483 PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
2484 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
2485 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
2486 PACKET3_MAP_QUEUES_ALLOC_FORMAT(1) | /* alloc format: all_on_one_pipe */
2487 PACKET3_MAP_QUEUES_ENGINE_SEL(0) | /* engine_sel: compute */
2488 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
2489 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
2490 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
2491 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
2492 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
2493 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
2494 }
2fdde9fa
AD		 2495 /* write to scratch for completion */
2496 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
2497 amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
2498 amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
464826d6 2499 amdgpu_ring_commit(kiq_ring);
2fdde9fa
AD		 2500
2501 for (i = 0; i < adev->usec_timeout; i++) {
2502 tmp = RREG32(scratch);
2503 if (tmp == 0xDEADBEEF)
2504 break;
2505 DRM_UDELAY(1);
2506 }
2507 if (i >= adev->usec_timeout) {
2508 DRM_ERROR("KCQ enable failed (scratch(0x%04X)=0x%08X)\n",
2509 scratch, tmp);
2510 r = -EINVAL;
2511 }
2512 amdgpu_gfx_scratch_free(adev, scratch);
2513
2514 return r;
464826d6
XY		 2515}
2516
e30a5223
AD		 2517static int gfx_v9_0_kiq_kcq_disable(struct amdgpu_device *adev)
2518{
2519 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
2520 uint32_t scratch, tmp = 0;
2521 int r, i;
2522
2523 r = amdgpu_gfx_scratch_get(adev, &scratch);
2524 if (r) {
2525 DRM_ERROR("Failed to get scratch reg (%d).\n", r);
2526 return r;
2527 }
2528 WREG32(scratch, 0xCAFEDEAD);
2529
2530 r = amdgpu_ring_alloc(kiq_ring, 6 + 3);
2531 if (r) {
2532 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
2533 amdgpu_gfx_scratch_free(adev, scratch);
2534 return r;
2535 }
2536 /* unmap queues */
2537 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
2538 amdgpu_ring_write(kiq_ring,
2539 PACKET3_UNMAP_QUEUES_ACTION(1)| /* RESET_QUEUES */
2540 PACKET3_UNMAP_QUEUES_QUEUE_SEL(2)); /* select all queues */
2541 amdgpu_ring_write(kiq_ring, 0);
2542 amdgpu_ring_write(kiq_ring, 0);
2543 amdgpu_ring_write(kiq_ring, 0);
2544 amdgpu_ring_write(kiq_ring, 0);
2545 /* write to scratch for completion */
2546 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
2547 amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
2548 amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
2549 amdgpu_ring_commit(kiq_ring);
2550
2551 for (i = 0; i < adev->usec_timeout; i++) {
2552 tmp = RREG32(scratch);
2553 if (tmp == 0xDEADBEEF)
2554 break;
2555 DRM_UDELAY(1);
2556 }
2557 if (i >= adev->usec_timeout) {
2558 DRM_ERROR("KCQ disable failed (scratch(0x%04X)=0x%08X)\n",
2559 scratch, tmp);
2560 r = -EINVAL;
2561 }
2562 amdgpu_gfx_scratch_free(adev, scratch);
2563
2564 return r;
2565}
2566
e322edc3 2567static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
464826d6 2568{
33fb8698 2569 struct amdgpu_device *adev = ring->adev;
e322edc3 2570 struct v9_mqd *mqd = ring->mqd_ptr;
464826d6
XY		 2571 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
2572 uint32_t tmp;
2573
2574 mqd->header = 0xC0310800;
2575 mqd->compute_pipelinestat_enable = 0x00000001;
2576 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
2577 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
2578 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
2579 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
2580 mqd->compute_misc_reserved = 0x00000003;
2581
d72f2f46 2582 eop_base_addr = ring->eop_gpu_addr >> 8;
464826d6
XY		 2583 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
2584 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
2585
2586 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
5e78835a 2587 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
464826d6 2588 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
268cb4c7 2589 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1));
464826d6
XY		 2590
2591 mqd->cp_hqd_eop_control = tmp;
2592
2593 /* enable doorbell? */
5e78835a 2594 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
464826d6
XY		 2595
2596 if (ring->use_doorbell) {
2597 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2598 DOORBELL_OFFSET, ring->doorbell_index);
2599 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2600 DOORBELL_EN, 1);
2601 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2602 DOORBELL_SOURCE, 0);
2603 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2604 DOORBELL_HIT, 0);
2605 }
2606 else
2607 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2608 DOORBELL_EN, 0);
2609
2610 mqd->cp_hqd_pq_doorbell_control = tmp;
2611
2612 /* disable the queue if it's active */
2613 ring->wptr = 0;
2614 mqd->cp_hqd_dequeue_request = 0;
2615 mqd->cp_hqd_pq_rptr = 0;
2616 mqd->cp_hqd_pq_wptr_lo = 0;
2617 mqd->cp_hqd_pq_wptr_hi = 0;
2618
2619 /* set the pointer to the MQD */
33fb8698
AD		 2620 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
2621 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
464826d6
XY		 2622
2623 /* set MQD vmid to 0 */
5e78835a 2624 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
464826d6
XY		 2625 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
2626 mqd->cp_mqd_control = tmp;
2627
2628 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2629 hqd_gpu_addr = ring->gpu_addr >> 8;
2630 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
2631 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
2632
2633 /* set up the HQD, this is similar to CP_RB0_CNTL */
5e78835a 2634 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
464826d6
XY		 2635 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
2636 (order_base_2(ring->ring_size / 4) - 1));
2637 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
2638 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
2639#ifdef __BIG_ENDIAN
2640 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
2641#endif
2642 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
2643 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
2644 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
2645 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
2646 mqd->cp_hqd_pq_control = tmp;
2647
2648 /* set the wb address whether it's enabled or not */
2649 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2650 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
2651 mqd->cp_hqd_pq_rptr_report_addr_hi =
2652 upper_32_bits(wb_gpu_addr) & 0xffff;
2653
2654 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2655 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2656 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
2657 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
2658
2659 tmp = 0;
2660 /* enable the doorbell if requested */
2661 if (ring->use_doorbell) {
5e78835a 2662 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
464826d6
XY		 2663 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2664 DOORBELL_OFFSET, ring->doorbell_index);
2665
2666 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2667 DOORBELL_EN, 1);
2668 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2669 DOORBELL_SOURCE, 0);
2670 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2671 DOORBELL_HIT, 0);
2672 }
2673
2674 mqd->cp_hqd_pq_doorbell_control = tmp;
2675
2676 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2677 ring->wptr = 0;
0274a9c5 2678 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
464826d6
XY		 2679
2680 /* set the vmid for the queue */
2681 mqd->cp_hqd_vmid = 0;
2682
0274a9c5 2683 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
464826d6
XY		 2684 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
2685 mqd->cp_hqd_persistent_state = tmp;
2686
fca4ce69
AD		 2687 /* set MIN_IB_AVAIL_SIZE */
2688 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
2689 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
2690 mqd->cp_hqd_ib_control = tmp;
2691
464826d6
XY		 2692 /* activate the queue */
2693 mqd->cp_hqd_active = 1;
2694
2695 return 0;
2696}
2697
e322edc3 2698static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)
464826d6 2699{
33fb8698 2700 struct amdgpu_device *adev = ring->adev;
e322edc3 2701 struct v9_mqd *mqd = ring->mqd_ptr;
464826d6
XY		 2702 int j;
2703
2704 /* disable wptr polling */
72edadd5 2705 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
464826d6 2706
5e78835a 2707 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
464826d6 2708 mqd->cp_hqd_eop_base_addr_lo);
5e78835a 2709 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
464826d6
XY		 2710 mqd->cp_hqd_eop_base_addr_hi);
2711
2712 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
5e78835a 2713 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
464826d6
XY		 2714 mqd->cp_hqd_eop_control);
2715
2716 /* enable doorbell? */
5e78835a 2717 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
464826d6
XY		 2718 mqd->cp_hqd_pq_doorbell_control);
2719
2720 /* disable the queue if it's active */
5e78835a
TSD		 2721 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
2722 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
464826d6 2723 for (j = 0; j < adev->usec_timeout; j++) {
5e78835a 2724 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
464826d6
XY		 2725 break;
2726 udelay(1);
2727 }
5e78835a 2728 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
464826d6 2729 mqd->cp_hqd_dequeue_request);
5e78835a 2730 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
464826d6 2731 mqd->cp_hqd_pq_rptr);
5e78835a 2732 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
464826d6 2733 mqd->cp_hqd_pq_wptr_lo);
5e78835a 2734 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
464826d6
XY		 2735 mqd->cp_hqd_pq_wptr_hi);
2736 }
2737
2738 /* set the pointer to the MQD */
5e78835a 2739 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
464826d6 2740 mqd->cp_mqd_base_addr_lo);
5e78835a 2741 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
464826d6
XY		 2742 mqd->cp_mqd_base_addr_hi);
2743
2744 /* set MQD vmid to 0 */
5e78835a 2745 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
464826d6
XY		 2746 mqd->cp_mqd_control);
2747
2748 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
5e78835a 2749 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
464826d6 2750 mqd->cp_hqd_pq_base_lo);
5e78835a 2751 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
464826d6
XY		 2752 mqd->cp_hqd_pq_base_hi);
2753
2754 /* set up the HQD, this is similar to CP_RB0_CNTL */
5e78835a 2755 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
464826d6
XY		 2756 mqd->cp_hqd_pq_control);
2757
2758 /* set the wb address whether it's enabled or not */
5e78835a 2759 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
464826d6 2760 mqd->cp_hqd_pq_rptr_report_addr_lo);
5e78835a 2761 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
464826d6
XY		 2762 mqd->cp_hqd_pq_rptr_report_addr_hi);
2763
2764 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
5e78835a 2765 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
464826d6 2766 mqd->cp_hqd_pq_wptr_poll_addr_lo);
5e78835a 2767 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
464826d6
XY		 2768 mqd->cp_hqd_pq_wptr_poll_addr_hi);
2769
2770 /* enable the doorbell if requested */
2771 if (ring->use_doorbell) {
5e78835a 2772 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
464826d6 2773 (AMDGPU_DOORBELL64_KIQ *2) << 2);
5e78835a 2774 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
464826d6
XY		 2775 (AMDGPU_DOORBELL64_USERQUEUE_END * 2) << 2);
2776 }
2777
5e78835a 2778 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
464826d6
XY		 2779 mqd->cp_hqd_pq_doorbell_control);
2780
2781 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
5e78835a 2782 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
464826d6 2783 mqd->cp_hqd_pq_wptr_lo);
5e78835a 2784 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
464826d6
XY		 2785 mqd->cp_hqd_pq_wptr_hi);
2786
2787 /* set the vmid for the queue */
5e78835a 2788 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
464826d6 2789
5e78835a 2790 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
464826d6
XY		 2791 mqd->cp_hqd_persistent_state);
2792
2793 /* activate the queue */
5e78835a 2794 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
464826d6
XY		 2795 mqd->cp_hqd_active);
2796
72edadd5
TSD		 2797 if (ring->use_doorbell)
2798 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
464826d6
XY		 2799
2800 return 0;
2801}
2802
e322edc3 2803static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring)
464826d6
XY		 2804{
2805 struct amdgpu_device *adev = ring->adev;
e322edc3 2806 struct v9_mqd *mqd = ring->mqd_ptr;
464826d6
XY		 2807 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
2808
898b7893 2809 gfx_v9_0_kiq_setting(ring);
464826d6 2810
ba0c19f5 2811 if (adev->gfx.in_reset) { /* for GPU_RESET case */
464826d6 2812 /* reset MQD to a clean status */
0ef376ca
AD		 2813 if (adev->gfx.mec.mqd_backup[mqd_idx])
2814 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
464826d6
XY		 2815
2816 /* reset ring buffer */
2817 ring->wptr = 0;
b98724db 2818 amdgpu_ring_clear_ring(ring);
464826d6 2819
898b7893
AD		 2820 mutex_lock(&adev->srbm_mutex);
2821 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
2822 gfx_v9_0_kiq_init_register(ring);
2823 soc15_grbm_select(adev, 0, 0, 0, 0);
2824 mutex_unlock(&adev->srbm_mutex);
ba0c19f5
AD		 2825 } else {
2826 memset((void *)mqd, 0, sizeof(*mqd));
2827 mutex_lock(&adev->srbm_mutex);
2828 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
2829 gfx_v9_0_mqd_init(ring);
2830 gfx_v9_0_kiq_init_register(ring);
2831 soc15_grbm_select(adev, 0, 0, 0, 0);
2832 mutex_unlock(&adev->srbm_mutex);
2833
2834 if (adev->gfx.mec.mqd_backup[mqd_idx])
2835 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
464826d6
XY		 2836 }
2837
0f1dfd52 2838 return 0;
898b7893
AD		 2839}
2840
2841static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring)
2842{
2843 struct amdgpu_device *adev = ring->adev;
898b7893
AD		 2844 struct v9_mqd *mqd = ring->mqd_ptr;
2845 int mqd_idx = ring - &adev->gfx.compute_ring[0];
898b7893 2846
e30a5223 2847 if (!adev->gfx.in_reset && !adev->gfx.in_suspend) {
898b7893
AD		 2848 memset((void *)mqd, 0, sizeof(*mqd));
2849 mutex_lock(&adev->srbm_mutex);
2850 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
2851 gfx_v9_0_mqd_init(ring);
2852 soc15_grbm_select(adev, 0, 0, 0, 0);
2853 mutex_unlock(&adev->srbm_mutex);
2854
2855 if (adev->gfx.mec.mqd_backup[mqd_idx])
2856 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
ba0c19f5 2857 } else if (adev->gfx.in_reset) { /* for GPU_RESET case */
898b7893
AD		 2858 /* reset MQD to a clean status */
2859 if (adev->gfx.mec.mqd_backup[mqd_idx])
2860 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
2861
2862 /* reset ring buffer */
2863 ring->wptr = 0;
2864 amdgpu_ring_clear_ring(ring);
ba0c19f5
AD		 2865 } else {
2866 amdgpu_ring_clear_ring(ring);
898b7893
AD		 2867 }
2868
bd3402ea 2869 return 0;
464826d6
XY		 2870}
2871
2872static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev)
2873{
2874 struct amdgpu_ring *ring = NULL;
2875 int r = 0, i;
2876
2877 gfx_v9_0_cp_compute_enable(adev, true);
2878
2879 ring = &adev->gfx.kiq.ring;
e1d53aa8
AD		 2880
2881 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2882 if (unlikely(r != 0))
2883 goto done;
2884
2885 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
2886 if (!r) {
e322edc3 2887 r = gfx_v9_0_kiq_init_queue(ring);
464826d6
XY		 2888 amdgpu_bo_kunmap(ring->mqd_obj);
2889 ring->mqd_ptr = NULL;
464826d6 2890 }
e1d53aa8
AD		 2891 amdgpu_bo_unreserve(ring->mqd_obj);
2892 if (r)
2893 goto done;
464826d6
XY		 2894
2895 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2896 ring = &adev->gfx.compute_ring[i];
e1d53aa8
AD		 2897
2898 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2899 if (unlikely(r != 0))
2900 goto done;
2901 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
2902 if (!r) {
898b7893 2903 r = gfx_v9_0_kcq_init_queue(ring);
464826d6
XY		 2904 amdgpu_bo_kunmap(ring->mqd_obj);
2905 ring->mqd_ptr = NULL;
464826d6 2906 }
e1d53aa8
AD		 2907 amdgpu_bo_unreserve(ring->mqd_obj);
2908 if (r)
2909 goto done;
464826d6
XY		 2910 }
2911
0f1dfd52 2912 r = gfx_v9_0_kiq_kcq_enable(adev);
e1d53aa8
AD		 2913done:
2914 return r;
464826d6
XY		 2915}
2916
b1023571
KW		 2917static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
2918{
bd3402ea 2919 int r, i;
b1023571
KW		 2920 struct amdgpu_ring *ring;
2921
2922 if (!(adev->flags & AMD_IS_APU))
2923 gfx_v9_0_enable_gui_idle_interrupt(adev, false);
2924
2925 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2926 /* legacy firmware loading */
2927 r = gfx_v9_0_cp_gfx_load_microcode(adev);
2928 if (r)
2929 return r;
2930
2931 r = gfx_v9_0_cp_compute_load_microcode(adev);
2932 if (r)
2933 return r;
2934 }
2935
2936 r = gfx_v9_0_cp_gfx_resume(adev);
2937 if (r)
2938 return r;
2939
e30a5223 2940 r = gfx_v9_0_kiq_resume(adev);
b1023571
KW		 2941 if (r)
2942 return r;
2943
2944 ring = &adev->gfx.gfx_ring[0];
2945 r = amdgpu_ring_test_ring(ring);
2946 if (r) {
2947 ring->ready = false;
2948 return r;
2949 }
e30a5223
AD		 2950
2951 ring = &adev->gfx.kiq.ring;
2952 ring->ready = true;
2953 r = amdgpu_ring_test_ring(ring);
2954 if (r)
2955 ring->ready = false;
2956
b1023571
KW		 2957 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2958 ring = &adev->gfx.compute_ring[i];
2959
2960 ring->ready = true;
2961 r = amdgpu_ring_test_ring(ring);
2962 if (r)
2963 ring->ready = false;
2964 }
2965
2966 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
2967
2968 return 0;
2969}
2970
2971static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable)
2972{
2973 gfx_v9_0_cp_gfx_enable(adev, enable);
2974 gfx_v9_0_cp_compute_enable(adev, enable);
2975}
2976
2977static int gfx_v9_0_hw_init(void *handle)
2978{
2979 int r;
2980 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2981
2982 gfx_v9_0_init_golden_registers(adev);
2983
2984 gfx_v9_0_gpu_init(adev);
2985
2986 r = gfx_v9_0_rlc_resume(adev);
2987 if (r)
2988 return r;
2989
2990 r = gfx_v9_0_cp_resume(adev);
2991 if (r)
2992 return r;
2993
2994 r = gfx_v9_0_ngg_en(adev);
2995 if (r)
2996 return r;
2997
2998 return r;
2999}
3000
3001static int gfx_v9_0_hw_fini(void *handle)
3002{
3003 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3004
3005 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
3006 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
464826d6
XY		 3007 if (amdgpu_sriov_vf(adev)) {
3008 pr_debug("For SRIOV client, shouldn't do anything.\n");
3009 return 0;
3010 }
e30a5223 3011 gfx_v9_0_kiq_kcq_disable(adev);
b1023571
KW		 3012 gfx_v9_0_cp_enable(adev, false);
3013 gfx_v9_0_rlc_stop(adev);
b1023571
KW		 3014
3015 return 0;
3016}
3017
3018static int gfx_v9_0_suspend(void *handle)
3019{
3020 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3021
e30a5223 3022 adev->gfx.in_suspend = true;
b1023571
KW		 3023 return gfx_v9_0_hw_fini(adev);
3024}
3025
3026static int gfx_v9_0_resume(void *handle)
3027{
3028 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
e30a5223 3029 int r;
b1023571 3030
e30a5223
AD		 3031 r = gfx_v9_0_hw_init(adev);
3032 adev->gfx.in_suspend = false;
3033 return r;
b1023571
KW		 3034}
3035
3036static bool gfx_v9_0_is_idle(void *handle)
3037{
3038 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3039
5e78835a 3040 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
b1023571
KW		 3041 GRBM_STATUS, GUI_ACTIVE))
3042 return false;
3043 else
3044 return true;
3045}
3046
3047static int gfx_v9_0_wait_for_idle(void *handle)
3048{
3049 unsigned i;
3050 u32 tmp;
3051 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3052
3053 for (i = 0; i < adev->usec_timeout; i++) {
3054 /* read MC_STATUS */
5e78835a 3055 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
b1023571
KW		 3056 GRBM_STATUS__GUI_ACTIVE_MASK;
3057
3058 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
3059 return 0;
3060 udelay(1);
3061 }
3062 return -ETIMEDOUT;
3063}
3064
b1023571
KW		 3065static int gfx_v9_0_soft_reset(void *handle)
3066{
3067 u32 grbm_soft_reset = 0;
3068 u32 tmp;
3069 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3070
3071 /* GRBM_STATUS */
5e78835a 3072 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
b1023571
KW		 3073 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
3074 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
3075 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
3076 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
3077 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
3078 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
3079 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3080 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3081 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3082 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
3083 }
3084
3085 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
3086 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3087 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3088 }
3089
3090 /* GRBM_STATUS2 */
5e78835a 3091 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
b1023571
KW		 3092 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
3093 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3094 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
3095
3096
75bac5c6 3097 if (grbm_soft_reset) {
b1023571
KW		 3098 /* stop the rlc */
3099 gfx_v9_0_rlc_stop(adev);
3100
3101 /* Disable GFX parsing/prefetching */
3102 gfx_v9_0_cp_gfx_enable(adev, false);
3103
3104 /* Disable MEC parsing/prefetching */
3105 gfx_v9_0_cp_compute_enable(adev, false);
3106
3107 if (grbm_soft_reset) {
5e78835a 3108 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
b1023571
KW		 3109 tmp |= grbm_soft_reset;
3110 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
5e78835a
TSD		 3111 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3112 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
b1023571
KW		 3113
3114 udelay(50);
3115
3116 tmp &= ~grbm_soft_reset;
5e78835a
TSD		 3117 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3118 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
b1023571
KW		 3119 }
3120
3121 /* Wait a little for things to settle down */
3122 udelay(50);
b1023571
KW		 3123 }
3124 return 0;
3125}
3126
3127static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3128{
3129 uint64_t clock;
3130
3131 mutex_lock(&adev->gfx.gpu_clock_mutex);
5e78835a
TSD		 3132 WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3133 clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
3134 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
b1023571
KW		 3135 mutex_unlock(&adev->gfx.gpu_clock_mutex);
3136 return clock;
3137}
3138
3139static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
3140 uint32_t vmid,
3141 uint32_t gds_base, uint32_t gds_size,
3142 uint32_t gws_base, uint32_t gws_size,
3143 uint32_t oa_base, uint32_t oa_size)
3144{
3145 gds_base = gds_base >> AMDGPU_GDS_SHIFT;
3146 gds_size = gds_size >> AMDGPU_GDS_SHIFT;
3147
3148 gws_base = gws_base >> AMDGPU_GWS_SHIFT;
3149 gws_size = gws_size >> AMDGPU_GWS_SHIFT;
3150
3151 oa_base = oa_base >> AMDGPU_OA_SHIFT;
3152 oa_size = oa_size >> AMDGPU_OA_SHIFT;
3153
3154 /* GDS Base */
3155 gfx_v9_0_write_data_to_reg(ring, 0, false,
3156 amdgpu_gds_reg_offset[vmid].mem_base,
3157 gds_base);
3158
3159 /* GDS Size */
3160 gfx_v9_0_write_data_to_reg(ring, 0, false,
3161 amdgpu_gds_reg_offset[vmid].mem_size,
3162 gds_size);
3163
3164 /* GWS */
3165 gfx_v9_0_write_data_to_reg(ring, 0, false,
3166 amdgpu_gds_reg_offset[vmid].gws,
3167 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
3168
3169 /* OA */
3170 gfx_v9_0_write_data_to_reg(ring, 0, false,
3171 amdgpu_gds_reg_offset[vmid].oa,
3172 (1 << (oa_size + oa_base)) - (1 << oa_base));
3173}
3174
3175static int gfx_v9_0_early_init(void *handle)
3176{
3177 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3178
3179 adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
78c16834 3180 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
b1023571
KW		 3181 gfx_v9_0_set_ring_funcs(adev);
3182 gfx_v9_0_set_irq_funcs(adev);
3183 gfx_v9_0_set_gds_init(adev);
3184 gfx_v9_0_set_rlc_funcs(adev);
3185
3186 return 0;
3187}
3188
3189static int gfx_v9_0_late_init(void *handle)
3190{
3191 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3192 int r;
3193
3194 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
3195 if (r)
3196 return r;
3197
3198 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
3199 if (r)
3200 return r;
3201
3202 return 0;
3203}
3204
3205static void gfx_v9_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
3206{
3207 uint32_t rlc_setting, data;
3208 unsigned i;
3209
3210 if (adev->gfx.rlc.in_safe_mode)
3211 return;
3212
3213 /* if RLC is not enabled, do nothing */
5e78835a 3214 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
b1023571
KW		 3215 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
3216 return;
3217
3218 if (adev->cg_flags &
3219 (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG |
3220 AMD_CG_SUPPORT_GFX_3D_CGCG)) {
3221 data = RLC_SAFE_MODE__CMD_MASK;
3222 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
5e78835a 3223 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
b1023571
KW		 3224
3225 /* wait for RLC_SAFE_MODE */
3226 for (i = 0; i < adev->usec_timeout; i++) {
3227 if (!REG_GET_FIELD(SOC15_REG_OFFSET(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
3228 break;
3229 udelay(1);
3230 }
3231 adev->gfx.rlc.in_safe_mode = true;
3232 }
3233}
3234
3235static void gfx_v9_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
3236{
3237 uint32_t rlc_setting, data;
3238
3239 if (!adev->gfx.rlc.in_safe_mode)
3240 return;
3241
3242 /* if RLC is not enabled, do nothing */
5e78835a 3243 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
b1023571
KW		 3244 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
3245 return;
3246
3247 if (adev->cg_flags &
3248 (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) {
3249 /*
3250 * Try to exit safe mode only if it is already in safe
3251 * mode.
3252 */
3253 data = RLC_SAFE_MODE__CMD_MASK;
5e78835a 3254 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
b1023571
KW		 3255 adev->gfx.rlc.in_safe_mode = false;
3256 }
3257}
3258
197f95c8
HZ		 3259static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
3260 bool enable)
3261{
3262 /* TODO: double check if we need to perform under safe mdoe */
3263 /* gfx_v9_0_enter_rlc_safe_mode(adev); */
3264
3265 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
3266 gfx_v9_0_enable_gfx_cg_power_gating(adev, true);
3267 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE)
3268 gfx_v9_0_enable_gfx_pipeline_powergating(adev, true);
3269 } else {
3270 gfx_v9_0_enable_gfx_cg_power_gating(adev, false);
3271 gfx_v9_0_enable_gfx_pipeline_powergating(adev, false);
3272 }
3273
3274 /* gfx_v9_0_exit_rlc_safe_mode(adev); */
3275}
3276
18924c71
HZ		 3277static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev,
3278 bool enable)
3279{
3280 /* TODO: double check if we need to perform under safe mode */
3281 /* gfx_v9_0_enter_rlc_safe_mode(adev); */
3282
3283 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
3284 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, true);
3285 else
3286 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, false);
3287
3288 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)
3289 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, true);
3290 else
3291 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, false);
3292
3293 /* gfx_v9_0_exit_rlc_safe_mode(adev); */
3294}
3295
b1023571
KW		 3296static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
3297 bool enable)
3298{
3299 uint32_t data, def;
3300
3301 /* It is disabled by HW by default */
3302 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
3303 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
5e78835a 3304 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
b1023571
KW		 3305 data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
3306 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
3307 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
3308 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
3309
3310 /* only for Vega10 & Raven1 */
3311 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK;
3312
3313 if (def != data)
5e78835a 3314 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
b1023571
KW		 3315
3316 /* MGLS is a global flag to control all MGLS in GFX */
3317 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
3318 /* 2 - RLC memory Light sleep */
3319 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
5e78835a 3320 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
b1023571
KW		 3321 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3322 if (def != data)
5e78835a 3323 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
b1023571
KW		 3324 }
3325 /* 3 - CP memory Light sleep */
3326 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
5e78835a 3327 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
b1023571
KW		 3328 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3329 if (def != data)
5e78835a 3330 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
b1023571
KW		 3331 }
3332 }
3333 } else {
3334 /* 1 - MGCG_OVERRIDE */
5e78835a 3335 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
b1023571
KW		 3336 data |= (RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
3337 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
3338 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
3339 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
3340 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
3341 if (def != data)
5e78835a 3342 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
b1023571
KW		 3343
3344 /* 2 - disable MGLS in RLC */
5e78835a 3345 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
b1023571
KW		 3346 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
3347 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
5e78835a 3348 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
b1023571
KW		 3349 }
3350
3351 /* 3 - disable MGLS in CP */
5e78835a 3352 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
b1023571
KW		 3353 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
3354 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
5e78835a 3355 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
b1023571
KW		 3356 }
3357 }
3358}
3359
3360static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
3361 bool enable)
3362{
3363 uint32_t data, def;
3364
3365 adev->gfx.rlc.funcs->enter_safe_mode(adev);
3366
3367 /* Enable 3D CGCG/CGLS */
3368 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
3369 /* write cmd to clear cgcg/cgls ov */
5e78835a 3370 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
b1023571
KW		 3371 /* unset CGCG override */
3372 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
3373 /* update CGCG and CGLS override bits */
3374 if (def != data)
5e78835a 3375 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
b1023571 3376 /* enable 3Dcgcg FSM(0x0020003f) */
5e78835a 3377 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
b1023571
KW		 3378 data = (0x2000 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
3379 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
3380 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
3381 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
3382 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
3383 if (def != data)
5e78835a 3384 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
b1023571
KW		 3385
3386 /* set IDLE_POLL_COUNT(0x00900100) */
5e78835a 3387 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
b1023571
KW		 3388 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
3389 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3390 if (def != data)
5e78835a 3391 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
b1023571
KW		 3392 } else {
3393 /* Disable CGCG/CGLS */
5e78835a 3394 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
b1023571
KW		 3395 /* disable cgcg, cgls should be disabled */
3396 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
3397 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
3398 /* disable cgcg and cgls in FSM */
3399 if (def != data)
5e78835a 3400 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
b1023571
KW		 3401 }
3402
3403 adev->gfx.rlc.funcs->exit_safe_mode(adev);
3404}
3405
3406static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
3407 bool enable)
3408{
3409 uint32_t def, data;
3410
3411 adev->gfx.rlc.funcs->enter_safe_mode(adev);
3412
3413 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
5e78835a 3414 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
b1023571
KW		 3415 /* unset CGCG override */
3416 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
3417 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
3418 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
3419 else
3420 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
3421 /* update CGCG and CGLS override bits */
3422 if (def != data)
5e78835a 3423 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
b1023571
KW		 3424
3425 /* enable cgcg FSM(0x0020003F) */
5e78835a 3426 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
b1023571
KW		 3427 data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
3428 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
3429 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
3430 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
3431 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
3432 if (def != data)
5e78835a 3433 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
b1023571
KW		 3434
3435 /* set IDLE_POLL_COUNT(0x00900100) */
5e78835a 3436 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
b1023571
KW		 3437 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
3438 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3439 if (def != data)
5e78835a 3440 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
b1023571 3441 } else {
5e78835a 3442 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
b1023571
KW		 3443 /* reset CGCG/CGLS bits */
3444 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
3445 /* disable cgcg and cgls in FSM */
3446 if (def != data)
5e78835a 3447 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
b1023571
KW		 3448 }
3449
3450 adev->gfx.rlc.funcs->exit_safe_mode(adev);
3451}
3452
3453static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev,
3454 bool enable)
3455{
3456 if (enable) {
3457 /* CGCG/CGLS should be enabled after MGCG/MGLS
3458 * === MGCG + MGLS ===
3459 */
3460 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
3461 /* === CGCG /CGLS for GFX 3D Only === */
3462 gfx_v9_0_update_3d_clock_gating(adev, enable);
3463 /* === CGCG + CGLS === */
3464 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
3465 } else {
3466 /* CGCG/CGLS should be disabled before MGCG/MGLS
3467 * === CGCG + CGLS ===
3468 */
3469 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
3470 /* === CGCG /CGLS for GFX 3D Only === */
3471 gfx_v9_0_update_3d_clock_gating(adev, enable);
3472 /* === MGCG + MGLS === */
3473 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
3474 }
3475 return 0;
3476}
3477
3478static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {
3479 .enter_safe_mode = gfx_v9_0_enter_rlc_safe_mode,
3480 .exit_safe_mode = gfx_v9_0_exit_rlc_safe_mode
3481};
3482
3483static int gfx_v9_0_set_powergating_state(void *handle,
3484 enum amd_powergating_state state)
3485{
5897c99e 3486 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
197f95c8 3487 bool enable = (state == AMD_PG_STATE_GATE) ? true : false;
5897c99e
HZ		 3488
3489 switch (adev->asic_type) {
3490 case CHIP_RAVEN:
3491 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
3492 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
3493 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
3494 } else {
3495 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false);
3496 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false);
3497 }
3498
3499 if (adev->pg_flags & AMD_PG_SUPPORT_CP)
3500 gfx_v9_0_enable_cp_power_gating(adev, true);
3501 else
3502 gfx_v9_0_enable_cp_power_gating(adev, false);
197f95c8
HZ		 3503
3504 /* update gfx cgpg state */
3505 gfx_v9_0_update_gfx_cg_power_gating(adev, enable);
18924c71
HZ		 3506
3507 /* update mgcg state */
3508 gfx_v9_0_update_gfx_mg_power_gating(adev, enable);
5897c99e
HZ		 3509 break;
3510 default:
3511 break;
3512 }
3513
b1023571
KW		 3514 return 0;
3515}
3516
3517static int gfx_v9_0_set_clockgating_state(void *handle,
3518 enum amd_clockgating_state state)
3519{
3520 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3521
fb82afab
XY		 3522 if (amdgpu_sriov_vf(adev))
3523 return 0;
3524
b1023571
KW		 3525 switch (adev->asic_type) {
3526 case CHIP_VEGA10:
a4dc61f5 3527 case CHIP_RAVEN:
b1023571
KW		 3528 gfx_v9_0_update_gfx_clock_gating(adev,
3529 state == AMD_CG_STATE_GATE ? true : false);
3530 break;
3531 default:
3532 break;
3533 }
3534 return 0;
3535}
3536
12ad27fa
HR		 3537static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags)
3538{
3539 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3540 int data;
3541
3542 if (amdgpu_sriov_vf(adev))
3543 *flags = 0;
3544
3545 /* AMD_CG_SUPPORT_GFX_MGCG */
5e78835a 3546 data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
12ad27fa
HR		 3547 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
3548 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
3549
3550 /* AMD_CG_SUPPORT_GFX_CGCG */
5e78835a 3551 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
12ad27fa
HR		 3552 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
3553 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
3554
3555 /* AMD_CG_SUPPORT_GFX_CGLS */
3556 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
3557 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
3558
3559 /* AMD_CG_SUPPORT_GFX_RLC_LS */
5e78835a 3560 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
12ad27fa
HR		 3561 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
3562 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
3563
3564 /* AMD_CG_SUPPORT_GFX_CP_LS */
5e78835a 3565 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
12ad27fa
HR		 3566 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
3567 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
3568
3569 /* AMD_CG_SUPPORT_GFX_3D_CGCG */
5e78835a 3570 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
12ad27fa
HR		 3571 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
3572 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
3573
3574 /* AMD_CG_SUPPORT_GFX_3D_CGLS */
3575 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
3576 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
3577}
3578
b1023571
KW		 3579static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
3580{
3581 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 is 32bit rptr*/
3582}
3583
3584static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
3585{
3586 struct amdgpu_device *adev = ring->adev;
3587 u64 wptr;
3588
3589 /* XXX check if swapping is necessary on BE */
3590 if (ring->use_doorbell) {
3591 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
3592 } else {
5e78835a
TSD		 3593 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
3594 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
b1023571
KW		 3595 }
3596
3597 return wptr;
3598}
3599
3600static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
3601{
3602 struct amdgpu_device *adev = ring->adev;
3603
3604 if (ring->use_doorbell) {
3605 /* XXX check if swapping is necessary on BE */
3606 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
3607 WDOORBELL64(ring->doorbell_index, ring->wptr);
3608 } else {
5e78835a
TSD		 3609 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
3610 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
b1023571
KW		 3611 }
3612}
3613
3614static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
3615{
3616 u32 ref_and_mask, reg_mem_engine;
3617 struct nbio_hdp_flush_reg *nbio_hf_reg;
3618
3619 if (ring->adev->asic_type == CHIP_VEGA10)
3620 nbio_hf_reg = &nbio_v6_1_hdp_flush_reg;
3621
3622 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
3623 switch (ring->me) {
3624 case 1:
3625 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
3626 break;
3627 case 2:
3628 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
3629 break;
3630 default:
3631 return;
3632 }
3633 reg_mem_engine = 0;
3634 } else {
3635 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
3636 reg_mem_engine = 1; /* pfp */
3637 }
3638
3639 gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
3640 nbio_hf_reg->hdp_flush_req_offset,
3641 nbio_hf_reg->hdp_flush_done_offset,
3642 ref_and_mask, ref_and_mask, 0x20);
3643}
3644
3645static void gfx_v9_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
3646{
3647 gfx_v9_0_write_data_to_reg(ring, 0, true,
3648 SOC15_REG_OFFSET(HDP, 0, mmHDP_DEBUG0), 1);
3649}
3650
3651static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
3652 struct amdgpu_ib *ib,
3653 unsigned vm_id, bool ctx_switch)
3654{
eaa05d52 3655 u32 header, control = 0;
b1023571 3656
eaa05d52
ML		 3657 if (ib->flags & AMDGPU_IB_FLAG_CE)
3658 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
3659 else
3660 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
b1023571 3661
eaa05d52 3662 control |= ib->length_dw | (vm_id << 24);
b1023571 3663
635e7132 3664 if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
eaa05d52 3665 control |= INDIRECT_BUFFER_PRE_ENB(1);
9ccd52eb 3666
635e7132
ML		 3667 if (!(ib->flags & AMDGPU_IB_FLAG_CE))
3668 gfx_v9_0_ring_emit_de_meta(ring);
3669 }
3670
eaa05d52
ML		 3671 amdgpu_ring_write(ring, header);
3672BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
3673 amdgpu_ring_write(ring,
b1023571 3674#ifdef __BIG_ENDIAN
eaa05d52 3675 (2 << 0) |
b1023571 3676#endif
eaa05d52
ML		 3677 lower_32_bits(ib->gpu_addr));
3678 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
3679 amdgpu_ring_write(ring, control);
b1023571
KW		 3680}
3681
b1023571
KW		 3682static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
3683 struct amdgpu_ib *ib,
3684 unsigned vm_id, bool ctx_switch)
3685{
3686 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24);
3687
3688 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
3689 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
3690 amdgpu_ring_write(ring,
3691#ifdef __BIG_ENDIAN
3692 (2 << 0) |
3693#endif
3694 lower_32_bits(ib->gpu_addr));
3695 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
3696 amdgpu_ring_write(ring, control);
3697}
3698
3699static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
3700 u64 seq, unsigned flags)
3701{
3702 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
3703 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
3704
3705 /* RELEASE_MEM - flush caches, send int */
3706 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
3707 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
3708 EOP_TC_ACTION_EN |
3709 EOP_TC_WB_ACTION_EN |
3710 EOP_TC_MD_ACTION_EN |
3711 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
3712 EVENT_INDEX(5)));
3713 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
3714
3715 /*
3716 * the address should be Qword aligned if 64bit write, Dword
3717 * aligned if only send 32bit data low (discard data high)
3718 */
3719 if (write64bit)
3720 BUG_ON(addr & 0x7);
3721 else
3722 BUG_ON(addr & 0x3);
3723 amdgpu_ring_write(ring, lower_32_bits(addr));
3724 amdgpu_ring_write(ring, upper_32_bits(addr));
3725 amdgpu_ring_write(ring, lower_32_bits(seq));
3726 amdgpu_ring_write(ring, upper_32_bits(seq));
3727 amdgpu_ring_write(ring, 0);
3728}
3729
3730static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
3731{
3732 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
3733 uint32_t seq = ring->fence_drv.sync_seq;
3734 uint64_t addr = ring->fence_drv.gpu_addr;
3735
3736 gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0,
3737 lower_32_bits(addr), upper_32_bits(addr),
3738 seq, 0xffffffff, 4);
3739}
3740
3741static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3742 unsigned vm_id, uint64_t pd_addr)
3743{
2e819849 3744 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
b1023571 3745 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
03f89feb 3746 uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
4789c463 3747 unsigned eng = ring->vm_inv_eng;
b1023571 3748
b1166325
CK		 3749 pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr);
3750 pd_addr |= AMDGPU_PTE_VALID;
b1023571 3751
2e819849
CK		 3752 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
3753 hub->ctx0_ptb_addr_lo32 + (2 * vm_id),
3754 lower_32_bits(pd_addr));
b1023571 3755
2e819849
CK		 3756 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
3757 hub->ctx0_ptb_addr_hi32 + (2 * vm_id),
3758 upper_32_bits(pd_addr));
b1023571 3759
2e819849
CK		 3760 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
3761 hub->vm_inv_eng0_req + eng, req);
b1023571 3762
2e819849
CK		 3763 /* wait for the invalidate to complete */
3764 gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, hub->vm_inv_eng0_ack +
3765 eng, 0, 1 << vm_id, 1 << vm_id, 0x20);
b1023571
KW		 3766
3767 /* compute doesn't have PFP */
3768 if (usepfp) {
3769 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3770 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3771 amdgpu_ring_write(ring, 0x0);
b1023571
KW		 3772 }
3773}
3774
3775static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
3776{
3777 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */
3778}
3779
3780static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
3781{
3782 u64 wptr;
3783
3784 /* XXX check if swapping is necessary on BE */
3785 if (ring->use_doorbell)
3786 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
3787 else
3788 BUG();
3789 return wptr;
3790}
3791
3792static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
3793{
3794 struct amdgpu_device *adev = ring->adev;
3795
3796 /* XXX check if swapping is necessary on BE */
3797 if (ring->use_doorbell) {
3798 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
3799 WDOORBELL64(ring->doorbell_index, ring->wptr);
3800 } else{
3801 BUG(); /* only DOORBELL method supported on gfx9 now */
3802 }
3803}
3804
aa6faa44
XY		 3805static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
3806 u64 seq, unsigned int flags)
3807{
3808 /* we only allocate 32bit for each seq wb address */
3809 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
3810
3811 /* write fence seq to the "addr" */
3812 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3813 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3814 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
3815 amdgpu_ring_write(ring, lower_32_bits(addr));
3816 amdgpu_ring_write(ring, upper_32_bits(addr));
3817 amdgpu_ring_write(ring, lower_32_bits(seq));
3818
3819 if (flags & AMDGPU_FENCE_FLAG_INT) {
3820 /* set register to trigger INT */
3821 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3822 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3823 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
3824 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
3825 amdgpu_ring_write(ring, 0);
3826 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
3827 }
3828}
3829
b1023571
KW		 3830static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring)
3831{
3832 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3833 amdgpu_ring_write(ring, 0);
3834}
3835
cca02cd3
XY		 3836static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
3837{
3838 static struct v9_ce_ib_state ce_payload = {0};
3839 uint64_t csa_addr;
3840 int cnt;
3841
3842 cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
3843 csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096;
3844
3845 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
3846 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
3847 WRITE_DATA_DST_SEL(8) |
3848 WR_CONFIRM) |
3849 WRITE_DATA_CACHE_POLICY(0));
3850 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
3851 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
3852 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, sizeof(ce_payload) >> 2);
3853}
3854
3855static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring)
3856{
3857 static struct v9_de_ib_state de_payload = {0};
3858 uint64_t csa_addr, gds_addr;
3859 int cnt;
3860
3861 csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096;
3862 gds_addr = csa_addr + 4096;
3863 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
3864 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
3865
3866 cnt = (sizeof(de_payload) >> 2) + 4 - 2;
3867 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
3868 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
3869 WRITE_DATA_DST_SEL(8) |
3870 WR_CONFIRM) |
3871 WRITE_DATA_CACHE_POLICY(0));
3872 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
3873 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
3874 amdgpu_ring_write_multiple(ring, (void *)&de_payload, sizeof(de_payload) >> 2);
3875}
3876
b1023571
KW		 3877static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
3878{
3879 uint32_t dw2 = 0;
3880
cca02cd3
XY		 3881 if (amdgpu_sriov_vf(ring->adev))
3882 gfx_v9_0_ring_emit_ce_meta(ring);
3883
b1023571
KW		 3884 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
3885 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
3886 /* set load_global_config & load_global_uconfig */
3887 dw2 |= 0x8001;
3888 /* set load_cs_sh_regs */
3889 dw2 |= 0x01000000;
3890 /* set load_per_context_state & load_gfx_sh_regs for GFX */
3891 dw2 |= 0x10002;
3892
3893 /* set load_ce_ram if preamble presented */
3894 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
3895 dw2 |= 0x10000000;
3896 } else {
3897 /* still load_ce_ram if this is the first time preamble presented
3898 * although there is no context switch happens.
3899 */
3900 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
3901 dw2 |= 0x10000000;
3902 }
3903
3904 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3905 amdgpu_ring_write(ring, dw2);
3906 amdgpu_ring_write(ring, 0);
3907}
3908
9a5e02b5
ML		 3909static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
3910{
3911 unsigned ret;
3912 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
3913 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
3914 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
3915 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
3916 ret = ring->wptr & ring->buf_mask;
3917 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
3918 return ret;
3919}
3920
3921static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
3922{
3923 unsigned cur;
3924 BUG_ON(offset > ring->buf_mask);
3925 BUG_ON(ring->ring[offset] != 0x55aa55aa);
3926
3927 cur = (ring->wptr & ring->buf_mask) - 1;
3928 if (likely(cur > offset))
3929 ring->ring[offset] = cur - offset;
3930 else
3931 ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
3932}
3933
3b4d68e9
ML		 3934static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start)
3935{
3936 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
3937 amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */
3938}
3939
aa6faa44
XY		 3940static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
3941{
3942 struct amdgpu_device *adev = ring->adev;
3943
3944 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
3945 amdgpu_ring_write(ring, 0 | /* src: register*/
3946 (5 << 8) | /* dst: memory */
3947 (1 << 20)); /* write confirm */
3948 amdgpu_ring_write(ring, reg);
3949 amdgpu_ring_write(ring, 0);
3950 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
3951 adev->virt.reg_val_offs * 4));
3952 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
3953 adev->virt.reg_val_offs * 4));
3954}
3955
3956static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
3957 uint32_t val)
3958{
3959 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3960 amdgpu_ring_write(ring, (1 << 16)); /* no inc addr */
3961 amdgpu_ring_write(ring, reg);
3962 amdgpu_ring_write(ring, 0);
3963 amdgpu_ring_write(ring, val);
3964}
3965
b1023571
KW		 3966static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
3967 enum amdgpu_interrupt_state state)
3968{
b1023571
KW		 3969 switch (state) {
3970 case AMDGPU_IRQ_STATE_DISABLE:
b1023571 3971 case AMDGPU_IRQ_STATE_ENABLE:
9da2c652
TSD		 3972 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
3973 TIME_STAMP_INT_ENABLE,
3974 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
b1023571
KW		 3975 break;
3976 default:
3977 break;
3978 }
3979}
3980
3981static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
3982 int me, int pipe,
3983 enum amdgpu_interrupt_state state)
3984{
763a47b8
AR		 3985 /* Me 0 is reserved for graphics */
3986 if (me < 1 || me > adev->gfx.mec.num_mec) {
3987 DRM_ERROR("Ignoring request to enable interrupts for invalid me:%d\n", me);
b1023571
KW		 3988 return;
3989 }
3990
763a47b8
AR		 3991 if (pipe >= adev->gfx.mec.num_pipe_per_mec) {
3992 DRM_ERROR("Ignoring request to enable interrupts for invalid "
3993 "me:%d pipe:%d\n", pipe, me);
3994 return;
b1023571 3995 }
763a47b8
AR		 3996
3997 mutex_lock(&adev->srbm_mutex);
3998 soc15_grbm_select(adev, me, pipe, 0, 0);
3999
4000 WREG32_FIELD(CPC_INT_CNTL, TIME_STAMP_INT_ENABLE,
4001 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);
4002
4003 soc15_grbm_select(adev, 0, 0, 0, 0);
4004 mutex_unlock(&adev->srbm_mutex);
b1023571
KW		 4005}
4006
4007static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4008 struct amdgpu_irq_src *source,
4009 unsigned type,
4010 enum amdgpu_interrupt_state state)
4011{
b1023571
KW		 4012 switch (state) {
4013 case AMDGPU_IRQ_STATE_DISABLE:
b1023571 4014 case AMDGPU_IRQ_STATE_ENABLE:
8dd553e1
TSD		 4015 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4016 PRIV_REG_INT_ENABLE,
4017 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
b1023571
KW		 4018 break;
4019 default:
4020 break;
4021 }
4022
4023 return 0;
4024}
4025
4026static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4027 struct amdgpu_irq_src *source,
4028 unsigned type,
4029 enum amdgpu_interrupt_state state)
4030{
b1023571
KW		 4031 switch (state) {
4032 case AMDGPU_IRQ_STATE_DISABLE:
b1023571 4033 case AMDGPU_IRQ_STATE_ENABLE:
98709ca6
TSD		 4034 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4035 PRIV_INSTR_INT_ENABLE,
4036 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
b1023571
KW		 4037 default:
4038 break;
4039 }
4040
4041 return 0;
4042}
4043
4044static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4045 struct amdgpu_irq_src *src,
4046 unsigned type,
4047 enum amdgpu_interrupt_state state)
4048{
4049 switch (type) {
4050 case AMDGPU_CP_IRQ_GFX_EOP:
4051 gfx_v9_0_set_gfx_eop_interrupt_state(adev, state);
4052 break;
4053 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4054 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4055 break;
4056 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4057 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4058 break;
4059 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4060 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4061 break;
4062 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4063 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4064 break;
4065 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4066 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4067 break;
4068 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4069 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4070 break;
4071 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4072 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4073 break;
4074 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4075 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4076 break;
4077 default:
4078 break;
4079 }
4080 return 0;
4081}
4082
4083static int gfx_v9_0_eop_irq(struct amdgpu_device *adev,
4084 struct amdgpu_irq_src *source,
4085 struct amdgpu_iv_entry *entry)
4086{
4087 int i;
4088 u8 me_id, pipe_id, queue_id;
4089 struct amdgpu_ring *ring;
4090
4091 DRM_DEBUG("IH: CP EOP\n");
4092 me_id = (entry->ring_id & 0x0c) >> 2;
4093 pipe_id = (entry->ring_id & 0x03) >> 0;
4094 queue_id = (entry->ring_id & 0x70) >> 4;
4095
4096 switch (me_id) {
4097 case 0:
4098 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4099 break;
4100 case 1:
4101 case 2:
4102 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4103 ring = &adev->gfx.compute_ring[i];
4104 /* Per-queue interrupt is supported for MEC starting from VI.
4105 * The interrupt can only be enabled/disabled per pipe instead of per queue.
4106 */
4107 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
4108 amdgpu_fence_process(ring);
4109 }
4110 break;
4111 }
4112 return 0;
4113}
4114
4115static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev,
4116 struct amdgpu_irq_src *source,
4117 struct amdgpu_iv_entry *entry)
4118{
4119 DRM_ERROR("Illegal register access in command stream\n");
4120 schedule_work(&adev->reset_work);
4121 return 0;
4122}
4123
4124static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev,
4125 struct amdgpu_irq_src *source,
4126 struct amdgpu_iv_entry *entry)
4127{
4128 DRM_ERROR("Illegal instruction in command stream\n");
4129 schedule_work(&adev->reset_work);
4130 return 0;
4131}
4132
97031e25
XY		 4133static int gfx_v9_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
4134 struct amdgpu_irq_src *src,
4135 unsigned int type,
4136 enum amdgpu_interrupt_state state)
4137{
4138 uint32_t tmp, target;
1c4ecf48 4139 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
97031e25
XY		 4140
4141 if (ring->me == 1)
4142 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
4143 else
4144 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
4145 target += ring->pipe;
4146
4147 switch (type) {
4148 case AMDGPU_CP_KIQ_IRQ_DRIVER0:
4149 if (state == AMDGPU_IRQ_STATE_DISABLE) {
5e78835a 4150 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
97031e25
XY		 4151 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
4152 GENERIC2_INT_ENABLE, 0);
5e78835a 4153 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
97031e25
XY		 4154
4155 tmp = RREG32(target);
4156 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
4157 GENERIC2_INT_ENABLE, 0);
4158 WREG32(target, tmp);
4159 } else {
5e78835a 4160 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
97031e25
XY		 4161 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
4162 GENERIC2_INT_ENABLE, 1);
5e78835a 4163 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
97031e25
XY		 4164
4165 tmp = RREG32(target);
4166 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
4167 GENERIC2_INT_ENABLE, 1);
4168 WREG32(target, tmp);
4169 }
4170 break;
4171 default:
4172 BUG(); /* kiq only support GENERIC2_INT now */
4173 break;
4174 }
4175 return 0;
4176}
4177
4178static int gfx_v9_0_kiq_irq(struct amdgpu_device *adev,
4179 struct amdgpu_irq_src *source,
4180 struct amdgpu_iv_entry *entry)
4181{
4182 u8 me_id, pipe_id, queue_id;
1c4ecf48 4183 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
97031e25
XY		 4184
4185 me_id = (entry->ring_id & 0x0c) >> 2;
4186 pipe_id = (entry->ring_id & 0x03) >> 0;
4187 queue_id = (entry->ring_id & 0x70) >> 4;
4188 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
4189 me_id, pipe_id, queue_id);
4190
4191 amdgpu_fence_process(ring);
4192 return 0;
4193}
4194
b1023571
KW		 4195const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
4196 .name = "gfx_v9_0",
4197 .early_init = gfx_v9_0_early_init,
4198 .late_init = gfx_v9_0_late_init,
4199 .sw_init = gfx_v9_0_sw_init,
4200 .sw_fini = gfx_v9_0_sw_fini,
4201 .hw_init = gfx_v9_0_hw_init,
4202 .hw_fini = gfx_v9_0_hw_fini,
4203 .suspend = gfx_v9_0_suspend,
4204 .resume = gfx_v9_0_resume,
4205 .is_idle = gfx_v9_0_is_idle,
4206 .wait_for_idle = gfx_v9_0_wait_for_idle,
4207 .soft_reset = gfx_v9_0_soft_reset,
4208 .set_clockgating_state = gfx_v9_0_set_clockgating_state,
4209 .set_powergating_state = gfx_v9_0_set_powergating_state,
12ad27fa 4210 .get_clockgating_state = gfx_v9_0_get_clockgating_state,
b1023571
KW		 4211};
4212
4213static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
4214 .type = AMDGPU_RING_TYPE_GFX,
4215 .align_mask = 0xff,
4216 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4217 .support_64bit_ptrs = true,
0eeb68b3 4218 .vmhub = AMDGPU_GFXHUB,
b1023571
KW		 4219 .get_rptr = gfx_v9_0_ring_get_rptr_gfx,
4220 .get_wptr = gfx_v9_0_ring_get_wptr_gfx,
4221 .set_wptr = gfx_v9_0_ring_set_wptr_gfx,
e9d672b2
ML		 4222 .emit_frame_size = /* totally 242 maximum if 16 IBs */
4223 5 + /* COND_EXEC */
4224 7 + /* PIPELINE_SYNC */
2e819849 4225 24 + /* VM_FLUSH */
e9d672b2
ML		 4226 8 + /* FENCE for VM_FLUSH */
4227 20 + /* GDS switch */
4228 4 + /* double SWITCH_BUFFER,
4229 the first COND_EXEC jump to the place just
4230 prior to this double SWITCH_BUFFER */
4231 5 + /* COND_EXEC */
4232 7 + /* HDP_flush */
4233 4 + /* VGT_flush */
4234 14 + /* CE_META */
4235 31 + /* DE_META */
4236 3 + /* CNTX_CTRL */
4237 5 + /* HDP_INVL */
4238 8 + 8 + /* FENCE x2 */
4239 2, /* SWITCH_BUFFER */
b1023571
KW		 4240 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */
4241 .emit_ib = gfx_v9_0_ring_emit_ib_gfx,
4242 .emit_fence = gfx_v9_0_ring_emit_fence,
4243 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
4244 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
4245 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
4246 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
4247 .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate,
4248 .test_ring = gfx_v9_0_ring_test_ring,
4249 .test_ib = gfx_v9_0_ring_test_ib,
4250 .insert_nop = amdgpu_ring_insert_nop,
4251 .pad_ib = amdgpu_ring_generic_pad_ib,
4252 .emit_switch_buffer = gfx_v9_ring_emit_sb,
4253 .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl,
9a5e02b5
ML		 4254 .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec,
4255 .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec,
3b4d68e9 4256 .emit_tmz = gfx_v9_0_ring_emit_tmz,
b1023571
KW		 4257};
4258
4259static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
4260 .type = AMDGPU_RING_TYPE_COMPUTE,
4261 .align_mask = 0xff,
4262 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4263 .support_64bit_ptrs = true,
0eeb68b3 4264 .vmhub = AMDGPU_GFXHUB,
b1023571
KW		 4265 .get_rptr = gfx_v9_0_ring_get_rptr_compute,
4266 .get_wptr = gfx_v9_0_ring_get_wptr_compute,
4267 .set_wptr = gfx_v9_0_ring_set_wptr_compute,
4268 .emit_frame_size =
4269 20 + /* gfx_v9_0_ring_emit_gds_switch */
4270 7 + /* gfx_v9_0_ring_emit_hdp_flush */
4271 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
4272 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
2e819849 4273 24 + /* gfx_v9_0_ring_emit_vm_flush */
b1023571
KW		 4274 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
4275 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
4276 .emit_ib = gfx_v9_0_ring_emit_ib_compute,
4277 .emit_fence = gfx_v9_0_ring_emit_fence,
4278 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
4279 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
4280 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
4281 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
4282 .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate,
4283 .test_ring = gfx_v9_0_ring_test_ring,
4284 .test_ib = gfx_v9_0_ring_test_ib,
4285 .insert_nop = amdgpu_ring_insert_nop,
4286 .pad_ib = amdgpu_ring_generic_pad_ib,
4287};
4288
aa6faa44
XY		 4289static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
4290 .type = AMDGPU_RING_TYPE_KIQ,
4291 .align_mask = 0xff,
4292 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4293 .support_64bit_ptrs = true,
0eeb68b3 4294 .vmhub = AMDGPU_GFXHUB,
aa6faa44
XY		 4295 .get_rptr = gfx_v9_0_ring_get_rptr_compute,
4296 .get_wptr = gfx_v9_0_ring_get_wptr_compute,
4297 .set_wptr = gfx_v9_0_ring_set_wptr_compute,
4298 .emit_frame_size =
4299 20 + /* gfx_v9_0_ring_emit_gds_switch */
4300 7 + /* gfx_v9_0_ring_emit_hdp_flush */
4301 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
4302 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
2e819849 4303 24 + /* gfx_v9_0_ring_emit_vm_flush */
aa6faa44
XY		 4304 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */
4305 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
4306 .emit_ib = gfx_v9_0_ring_emit_ib_compute,
4307 .emit_fence = gfx_v9_0_ring_emit_fence_kiq,
aa6faa44
XY		 4308 .test_ring = gfx_v9_0_ring_test_ring,
4309 .test_ib = gfx_v9_0_ring_test_ib,
4310 .insert_nop = amdgpu_ring_insert_nop,
4311 .pad_ib = amdgpu_ring_generic_pad_ib,
4312 .emit_rreg = gfx_v9_0_ring_emit_rreg,
4313 .emit_wreg = gfx_v9_0_ring_emit_wreg,
4314};
b1023571
KW		 4315
4316static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev)
4317{
4318 int i;
4319
aa6faa44
XY		 4320 adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq;
4321
b1023571
KW		 4322 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4323 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx;
4324
4325 for (i = 0; i < adev->gfx.num_compute_rings; i++)
4326 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute;
4327}
4328
97031e25
XY		 4329static const struct amdgpu_irq_src_funcs gfx_v9_0_kiq_irq_funcs = {
4330 .set = gfx_v9_0_kiq_set_interrupt_state,
4331 .process = gfx_v9_0_kiq_irq,
4332};
4333
b1023571
KW		 4334static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = {
4335 .set = gfx_v9_0_set_eop_interrupt_state,
4336 .process = gfx_v9_0_eop_irq,
4337};
4338
4339static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = {
4340 .set = gfx_v9_0_set_priv_reg_fault_state,
4341 .process = gfx_v9_0_priv_reg_irq,
4342};
4343
4344static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = {
4345 .set = gfx_v9_0_set_priv_inst_fault_state,
4346 .process = gfx_v9_0_priv_inst_irq,
4347};
4348
4349static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev)
4350{
4351 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
4352 adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs;
4353
4354 adev->gfx.priv_reg_irq.num_types = 1;
4355 adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs;
4356
4357 adev->gfx.priv_inst_irq.num_types = 1;
4358 adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs;
97031e25
XY		 4359
4360 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
4361 adev->gfx.kiq.irq.funcs = &gfx_v9_0_kiq_irq_funcs;
b1023571
KW		 4362}
4363
4364static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
4365{
4366 switch (adev->asic_type) {
4367 case CHIP_VEGA10:
a4dc61f5 4368 case CHIP_RAVEN:
b1023571
KW		 4369 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs;
4370 break;
4371 default:
4372 break;
4373 }
4374}
4375
4376static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
4377{
4378 /* init asci gds info */
5e78835a 4379 adev->gds.mem.total_size = RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE);
b1023571
KW		 4380 adev->gds.gws.total_size = 64;
4381 adev->gds.oa.total_size = 16;
4382
4383 if (adev->gds.mem.total_size == 64 * 1024) {
4384 adev->gds.mem.gfx_partition_size = 4096;
4385 adev->gds.mem.cs_partition_size = 4096;
4386
4387 adev->gds.gws.gfx_partition_size = 4;
4388 adev->gds.gws.cs_partition_size = 4;
4389
4390 adev->gds.oa.gfx_partition_size = 4;
4391 adev->gds.oa.cs_partition_size = 1;
4392 } else {
4393 adev->gds.mem.gfx_partition_size = 1024;
4394 adev->gds.mem.cs_partition_size = 1024;
4395
4396 adev->gds.gws.gfx_partition_size = 16;
4397 adev->gds.gws.cs_partition_size = 16;
4398
4399 adev->gds.oa.gfx_partition_size = 4;
4400 adev->gds.oa.cs_partition_size = 4;
4401 }
4402}
4403
4404static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev)
4405{
4406 u32 data, mask;
4407
5e78835a
TSD		 4408 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
4409 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
b1023571
KW		 4410
4411 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4412 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4413
378506a7 4414 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
b1023571
KW		 4415
4416 return (~data) & mask;
4417}
4418
4419static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
4420 struct amdgpu_cu_info *cu_info)
4421{
4422 int i, j, k, counter, active_cu_number = 0;
4423 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
4424
4425 if (!adev || !cu_info)
4426 return -EINVAL;
4427
4428 memset(cu_info, 0, sizeof(*cu_info));
4429
4430 mutex_lock(&adev->grbm_idx_mutex);
4431 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4432 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4433 mask = 1;
4434 ao_bitmap = 0;
4435 counter = 0;
4436 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
4437 bitmap = gfx_v9_0_get_cu_active_bitmap(adev);
4438 cu_info->bitmap[i][j] = bitmap;
4439
fe723cd3 4440 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
b1023571 4441 if (bitmap & mask) {
fe723cd3 4442 if (counter < adev->gfx.config.max_cu_per_sh)
b1023571
KW		 4443 ao_bitmap |= mask;
4444 counter ++;
4445 }
4446 mask <<= 1;
4447 }
4448 active_cu_number += counter;
4449 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
4450 }
4451 }
4452 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4453 mutex_unlock(&adev->grbm_idx_mutex);
4454
4455 cu_info->number = active_cu_number;
4456 cu_info->ao_cu_mask = ao_cu_mask;
4457
4458 return 0;
4459}
4460
b1023571
KW		 4461const struct amdgpu_ip_block_version gfx_v9_0_ip_block =
4462{
4463 .type = AMD_IP_BLOCK_TYPE_GFX,
4464 .major = 9,
4465 .minor = 0,
4466 .rev = 0,
4467 .funcs = &gfx_v9_0_ip_funcs,
4468};
Ubuntu Jammy Linux kernel mirror