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f9df67e9 HZ |
1 | /* |
2 | * Copyright 2019 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | */ | |
23 | #include <linux/firmware.h> | |
d7929c1e | 24 | #include <linux/pci.h> |
f9df67e9 HZ |
25 | #include "amdgpu.h" |
26 | #include "amdgpu_atomfirmware.h" | |
27 | #include "gmc_v10_0.h" | |
01eee24f | 28 | #include "umc_v8_7.h" |
f9df67e9 | 29 | |
ea930000 AS |
30 | #include "athub/athub_2_0_0_sh_mask.h" |
31 | #include "athub/athub_2_0_0_offset.h" | |
f9df67e9 HZ |
32 | #include "dcn/dcn_2_0_0_offset.h" |
33 | #include "dcn/dcn_2_0_0_sh_mask.h" | |
34 | #include "oss/osssys_5_0_0_offset.h" | |
35 | #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" | |
36 | #include "navi10_enum.h" | |
37 | ||
38 | #include "soc15.h" | |
ea930000 | 39 | #include "soc15d.h" |
f9df67e9 HZ |
40 | #include "soc15_common.h" |
41 | ||
42 | #include "nbio_v2_3.h" | |
43 | ||
44 | #include "gfxhub_v2_0.h" | |
0b3df16b | 45 | #include "gfxhub_v2_1.h" |
f9df67e9 | 46 | #include "mmhub_v2_0.h" |
4d8d75a4 | 47 | #include "mmhub_v2_3.h" |
f9df67e9 | 48 | #include "athub_v2_0.h" |
920a4cd3 | 49 | #include "athub_v2_1.h" |
f9df67e9 HZ |
50 | |
51 | #if 0 | |
52 | static const struct soc15_reg_golden golden_settings_navi10_hdp[] = | |
53 | { | |
54 | /* TODO add golden setting for hdp */ | |
55 | }; | |
56 | #endif | |
57 | ||
01eee24f JC |
58 | static int gmc_v10_0_ecc_interrupt_state(struct amdgpu_device *adev, |
59 | struct amdgpu_irq_src *src, | |
60 | unsigned type, | |
61 | enum amdgpu_interrupt_state state) | |
62 | { | |
63 | return 0; | |
64 | } | |
65 | ||
f9df67e9 HZ |
66 | static int |
67 | gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev, | |
68 | struct amdgpu_irq_src *src, unsigned type, | |
69 | enum amdgpu_interrupt_state state) | |
70 | { | |
f9df67e9 HZ |
71 | switch (state) { |
72 | case AMDGPU_IRQ_STATE_DISABLE: | |
73 | /* MM HUB */ | |
f2c1b5c1 | 74 | amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, false); |
f9df67e9 | 75 | /* GFX HUB */ |
f2c1b5c1 | 76 | amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, false); |
f9df67e9 HZ |
77 | break; |
78 | case AMDGPU_IRQ_STATE_ENABLE: | |
79 | /* MM HUB */ | |
f2c1b5c1 | 80 | amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, true); |
f9df67e9 | 81 | /* GFX HUB */ |
f2c1b5c1 | 82 | amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, true); |
f9df67e9 HZ |
83 | break; |
84 | default: | |
85 | break; | |
86 | } | |
87 | ||
88 | return 0; | |
89 | } | |
90 | ||
91 | static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev, | |
92 | struct amdgpu_irq_src *source, | |
93 | struct amdgpu_iv_entry *entry) | |
94 | { | |
a2a8857c | 95 | bool retry_fault = !!(entry->src_data[1] & 0x80); |
f9df67e9 | 96 | struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src]; |
45d87b85 | 97 | struct amdgpu_task_info task_info; |
f9df67e9 HZ |
98 | uint32_t status = 0; |
99 | u64 addr; | |
100 | ||
101 | addr = (u64)entry->src_data[0] << 12; | |
102 | addr |= ((u64)entry->src_data[1] & 0xf) << 44; | |
103 | ||
a2a8857c CK |
104 | if (retry_fault) { |
105 | /* Returning 1 here also prevents sending the IV to the KFD */ | |
106 | ||
107 | /* Process it onyl if it's the first fault for this address */ | |
108 | if (entry->ih != &adev->irq.ih_soft && | |
109 | amdgpu_gmc_filter_faults(adev, addr, entry->pasid, | |
110 | entry->timestamp)) | |
111 | return 1; | |
112 | ||
113 | /* Delegate it to a different ring if the hardware hasn't | |
114 | * already done it. | |
115 | */ | |
58df0d71 | 116 | if (entry->ih == &adev->irq.ih) { |
a2a8857c CK |
117 | amdgpu_irq_delegate(adev, entry, 8); |
118 | return 1; | |
119 | } | |
120 | ||
121 | /* Try to handle the recoverable page faults by filling page | |
122 | * tables | |
123 | */ | |
124 | if (amdgpu_vm_handle_fault(adev, entry->pasid, addr)) | |
125 | return 1; | |
126 | } | |
127 | ||
f9df67e9 | 128 | if (!amdgpu_sriov_vf(adev)) { |
53499173 XY |
129 | /* |
130 | * Issue a dummy read to wait for the status register to | |
131 | * be updated to avoid reading an incorrect value due to | |
132 | * the new fast GRBM interface. | |
133 | */ | |
5c46c492 AD |
134 | if ((entry->vmid_src == AMDGPU_GFXHUB_0) && |
135 | (adev->asic_type < CHIP_SIENNA_CICHLID)) | |
53499173 XY |
136 | RREG32(hub->vm_l2_pro_fault_status); |
137 | ||
f9df67e9 HZ |
138 | status = RREG32(hub->vm_l2_pro_fault_status); |
139 | WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); | |
140 | } | |
141 | ||
45d87b85 CK |
142 | if (!printk_ratelimit()) |
143 | return 0; | |
144 | ||
145 | memset(&task_info, 0, sizeof(struct amdgpu_task_info)); | |
146 | amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); | |
147 | ||
148 | dev_err(adev->dev, | |
149 | "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, " | |
150 | "for process %s pid %d thread %s pid %d)\n", | |
151 | entry->vmid_src ? "mmhub" : "gfxhub", | |
152 | entry->src_id, entry->ring_id, entry->vmid, | |
153 | entry->pasid, task_info.process_name, task_info.tgid, | |
154 | task_info.task_name, task_info.pid); | |
be14729a YZ |
155 | dev_err(adev->dev, " in page starting at address 0x%016llx from client 0x%x (%s)\n", |
156 | addr, entry->client_id, | |
157 | soc15_ih_clientid_name[entry->client_id]); | |
45d87b85 CK |
158 | |
159 | if (!amdgpu_sriov_vf(adev)) | |
160 | hub->vmhub_funcs->print_l2_protection_fault_status(adev, | |
161 | status); | |
f9df67e9 HZ |
162 | |
163 | return 0; | |
164 | } | |
165 | ||
166 | static const struct amdgpu_irq_src_funcs gmc_v10_0_irq_funcs = { | |
167 | .set = gmc_v10_0_vm_fault_interrupt_state, | |
168 | .process = gmc_v10_0_process_interrupt, | |
169 | }; | |
170 | ||
01eee24f JC |
171 | static const struct amdgpu_irq_src_funcs gmc_v10_0_ecc_funcs = { |
172 | .set = gmc_v10_0_ecc_interrupt_state, | |
173 | .process = amdgpu_umc_process_ecc_irq, | |
174 | }; | |
175 | ||
94ba290d | 176 | static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev) |
f9df67e9 HZ |
177 | { |
178 | adev->gmc.vm_fault.num_types = 1; | |
179 | adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs; | |
01eee24f JC |
180 | |
181 | if (!amdgpu_sriov_vf(adev)) { | |
182 | adev->gmc.ecc_irq.num_types = 1; | |
183 | adev->gmc.ecc_irq.funcs = &gmc_v10_0_ecc_funcs; | |
184 | } | |
f9df67e9 HZ |
185 | } |
186 | ||
f271fe18 | 187 | /** |
188 | * gmc_v10_0_use_invalidate_semaphore - judge whether to use semaphore | |
189 | * | |
190 | * @adev: amdgpu_device pointer | |
191 | * @vmhub: vmhub type | |
192 | * | |
193 | */ | |
194 | static bool gmc_v10_0_use_invalidate_semaphore(struct amdgpu_device *adev, | |
195 | uint32_t vmhub) | |
196 | { | |
197 | return ((vmhub == AMDGPU_MMHUB_0 || | |
198 | vmhub == AMDGPU_MMHUB_1) && | |
199 | (!amdgpu_sriov_vf(adev))); | |
200 | } | |
201 | ||
ea930000 AS |
202 | static bool gmc_v10_0_get_atc_vmid_pasid_mapping_info( |
203 | struct amdgpu_device *adev, | |
204 | uint8_t vmid, uint16_t *p_pasid) | |
205 | { | |
206 | uint32_t value; | |
207 | ||
208 | value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) | |
209 | + vmid); | |
210 | *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; | |
211 | ||
212 | return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); | |
213 | } | |
214 | ||
f9df67e9 HZ |
215 | /* |
216 | * GART | |
217 | * VMID 0 is the physical GPU addresses as used by the kernel. | |
218 | * VMIDs 1-15 are used for userspace clients and are handled | |
219 | * by the amdgpu vm/hsa code. | |
220 | */ | |
221 | ||
222 | static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, | |
223 | unsigned int vmhub, uint32_t flush_type) | |
224 | { | |
f271fe18 | 225 | bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(adev, vmhub); |
f9df67e9 | 226 | struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; |
caa9f483 | 227 | u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); |
37c58ddf | 228 | u32 tmp; |
f9df67e9 HZ |
229 | /* Use register 17 for GART */ |
230 | const unsigned eng = 17; | |
231 | unsigned int i; | |
6ba3f59e PJZ |
232 | unsigned char hub_ip = 0; |
233 | ||
234 | hub_ip = (vmhub == AMDGPU_GFXHUB_0) ? | |
235 | GC_HWIP : MMHUB_HWIP; | |
f9df67e9 | 236 | |
f920d1bb | 237 | spin_lock(&adev->gmc.invalidate_lock); |
238 | /* | |
239 | * It may lose gpuvm invalidate acknowldege state across power-gating | |
240 | * off cycle, add semaphore acquire before invalidation and semaphore | |
241 | * release after invalidation to avoid entering power gated state | |
242 | * to WA the Issue | |
243 | */ | |
244 | ||
245 | /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ | |
f271fe18 | 246 | if (use_semaphore) { |
f920d1bb | 247 | for (i = 0; i < adev->usec_timeout; i++) { |
248 | /* a read return value of 1 means semaphore acuqire */ | |
6ba3f59e PJZ |
249 | tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem + |
250 | hub->eng_distance * eng, hub_ip); | |
251 | ||
f920d1bb | 252 | if (tmp & 0x1) |
253 | break; | |
254 | udelay(1); | |
255 | } | |
256 | ||
257 | if (i >= adev->usec_timeout) | |
258 | DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); | |
259 | } | |
260 | ||
6ba3f59e PJZ |
261 | WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req + |
262 | hub->eng_distance * eng, | |
263 | inv_req, hub_ip); | |
f9df67e9 | 264 | |
53499173 XY |
265 | /* |
266 | * Issue a dummy read to wait for the ACK register to be cleared | |
267 | * to avoid a false ACK due to the new fast GRBM interface. | |
268 | */ | |
5c46c492 AD |
269 | if ((vmhub == AMDGPU_GFXHUB_0) && |
270 | (adev->asic_type < CHIP_SIENNA_CICHLID)) | |
6ba3f59e PJZ |
271 | RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req + |
272 | hub->eng_distance * eng, hub_ip); | |
53499173 | 273 | |
f9df67e9 HZ |
274 | /* Wait for ACK with a delay.*/ |
275 | for (i = 0; i < adev->usec_timeout; i++) { | |
6ba3f59e PJZ |
276 | tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_ack + |
277 | hub->eng_distance * eng, hub_ip); | |
278 | ||
f9df67e9 HZ |
279 | tmp &= 1 << vmid; |
280 | if (tmp) | |
281 | break; | |
282 | ||
283 | udelay(1); | |
284 | } | |
285 | ||
f920d1bb | 286 | /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ |
f271fe18 | 287 | if (use_semaphore) |
f920d1bb | 288 | /* |
289 | * add semaphore release after invalidation, | |
290 | * write with 0 means semaphore release | |
291 | */ | |
6ba3f59e PJZ |
292 | WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem + |
293 | hub->eng_distance * eng, 0, hub_ip); | |
f920d1bb | 294 | |
295 | spin_unlock(&adev->gmc.invalidate_lock); | |
296 | ||
f9df67e9 HZ |
297 | if (i < adev->usec_timeout) |
298 | return; | |
299 | ||
d9c7f753 | 300 | DRM_ERROR("Timeout waiting for VM flush hub: %d!\n", vmhub); |
f9df67e9 HZ |
301 | } |
302 | ||
303 | /** | |
304 | * gmc_v10_0_flush_gpu_tlb - gart tlb flush callback | |
305 | * | |
306 | * @adev: amdgpu_device pointer | |
307 | * @vmid: vm instance to flush | |
185ef9ef LJ |
308 | * @vmhub: vmhub type |
309 | * @flush_type: the flush type | |
f9df67e9 HZ |
310 | * |
311 | * Flush the TLB for the requested page table. | |
312 | */ | |
3ff98548 OZ |
313 | static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, |
314 | uint32_t vmhub, uint32_t flush_type) | |
f9df67e9 HZ |
315 | { |
316 | struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; | |
317 | struct dma_fence *fence; | |
318 | struct amdgpu_job *job; | |
319 | ||
320 | int r; | |
321 | ||
322 | /* flush hdp cache */ | |
bf087285 | 323 | adev->hdp.funcs->flush_hdp(adev, NULL); |
f9df67e9 | 324 | |
8db1015b | 325 | /* For SRIOV run time, driver shouldn't access the register through MMIO |
326 | * Directly use kiq to do the vm invalidation instead | |
327 | */ | |
328 | if (adev->gfx.kiq.ring.sched.ready && | |
329 | (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) && | |
81202807 | 330 | down_read_trylock(&adev->reset_sem)) { |
8db1015b | 331 | struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; |
332 | const unsigned eng = 17; | |
caa9f483 | 333 | u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); |
af6c5c4f HR |
334 | u32 req = hub->vm_inv_eng0_req + hub->eng_distance * eng; |
335 | u32 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; | |
8db1015b | 336 | |
337 | amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req, | |
338 | 1 << vmid); | |
81202807 DL |
339 | |
340 | up_read(&adev->reset_sem); | |
8db1015b | 341 | return; |
342 | } | |
343 | ||
f9df67e9 HZ |
344 | mutex_lock(&adev->mman.gtt_window_lock); |
345 | ||
3ff98548 OZ |
346 | if (vmhub == AMDGPU_MMHUB_0) { |
347 | gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB_0, 0); | |
348 | mutex_unlock(&adev->mman.gtt_window_lock); | |
349 | return; | |
350 | } | |
351 | ||
352 | BUG_ON(vmhub != AMDGPU_GFXHUB_0); | |
353 | ||
767acabd KW |
354 | if (!adev->mman.buffer_funcs_enabled || |
355 | !adev->ib_pool_ready || | |
53b3f8f4 | 356 | amdgpu_in_reset(adev) || |
e2195f7d | 357 | ring->sched.ready == false) { |
a2d15ed7 | 358 | gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0); |
f9df67e9 HZ |
359 | mutex_unlock(&adev->mman.gtt_window_lock); |
360 | return; | |
361 | } | |
362 | ||
363 | /* The SDMA on Navi has a bug which can theoretically result in memory | |
364 | * corruption if an invalidation happens at the same time as an VA | |
365 | * translation. Avoid this by doing the invalidation from the SDMA | |
366 | * itself. | |
367 | */ | |
9ecefb19 CK |
368 | r = amdgpu_job_alloc_with_ib(adev, 16 * 4, AMDGPU_IB_POOL_IMMEDIATE, |
369 | &job); | |
f9df67e9 HZ |
370 | if (r) |
371 | goto error_alloc; | |
372 | ||
373 | job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo); | |
374 | job->vm_needs_flush = true; | |
3f378758 | 375 | job->ibs->ptr[job->ibs->length_dw++] = ring->funcs->nop; |
f9df67e9 HZ |
376 | amdgpu_ring_pad_ib(ring, &job->ibs[0]); |
377 | r = amdgpu_job_submit(job, &adev->mman.entity, | |
378 | AMDGPU_FENCE_OWNER_UNDEFINED, &fence); | |
379 | if (r) | |
380 | goto error_submit; | |
381 | ||
382 | mutex_unlock(&adev->mman.gtt_window_lock); | |
383 | ||
384 | dma_fence_wait(fence, false); | |
385 | dma_fence_put(fence); | |
386 | ||
387 | return; | |
388 | ||
389 | error_submit: | |
390 | amdgpu_job_free(job); | |
391 | ||
392 | error_alloc: | |
393 | mutex_unlock(&adev->mman.gtt_window_lock); | |
394 | DRM_ERROR("Error flushing GPU TLB using the SDMA (%d)!\n", r); | |
395 | } | |
396 | ||
ea930000 AS |
397 | /** |
398 | * gmc_v10_0_flush_gpu_tlb_pasid - tlb flush via pasid | |
399 | * | |
400 | * @adev: amdgpu_device pointer | |
401 | * @pasid: pasid to be flush | |
185ef9ef LJ |
402 | * @flush_type: the flush type |
403 | * @all_hub: Used with PACKET3_INVALIDATE_TLBS_ALL_HUB() | |
ea930000 AS |
404 | * |
405 | * Flush the TLB for the requested pasid. | |
406 | */ | |
407 | static int gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, | |
408 | uint16_t pasid, uint32_t flush_type, | |
409 | bool all_hub) | |
410 | { | |
411 | int vmid, i; | |
412 | signed long r; | |
413 | uint32_t seq; | |
414 | uint16_t queried_pasid; | |
415 | bool ret; | |
416 | struct amdgpu_ring *ring = &adev->gfx.kiq.ring; | |
417 | struct amdgpu_kiq *kiq = &adev->gfx.kiq; | |
418 | ||
419 | if (amdgpu_emu_mode == 0 && ring->sched.ready) { | |
420 | spin_lock(&adev->gfx.kiq.ring_lock); | |
36a1707a AS |
421 | /* 2 dwords flush + 8 dwords fence */ |
422 | amdgpu_ring_alloc(ring, kiq->pmf->invalidate_tlbs_size + 8); | |
ea930000 AS |
423 | kiq->pmf->kiq_invalidate_tlbs(ring, |
424 | pasid, flush_type, all_hub); | |
04e4e2e9 YT |
425 | r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); |
426 | if (r) { | |
427 | amdgpu_ring_undo(ring); | |
abb17b1e | 428 | spin_unlock(&adev->gfx.kiq.ring_lock); |
04e4e2e9 YT |
429 | return -ETIME; |
430 | } | |
431 | ||
ea930000 AS |
432 | amdgpu_ring_commit(ring); |
433 | spin_unlock(&adev->gfx.kiq.ring_lock); | |
434 | r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout); | |
435 | if (r < 1) { | |
aac89168 | 436 | dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r); |
ea930000 AS |
437 | return -ETIME; |
438 | } | |
439 | ||
440 | return 0; | |
441 | } | |
442 | ||
68fce5f0 | 443 | for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { |
ea930000 AS |
444 | |
445 | ret = gmc_v10_0_get_atc_vmid_pasid_mapping_info(adev, vmid, | |
446 | &queried_pasid); | |
447 | if (ret && queried_pasid == pasid) { | |
448 | if (all_hub) { | |
449 | for (i = 0; i < adev->num_vmhubs; i++) | |
450 | gmc_v10_0_flush_gpu_tlb(adev, vmid, | |
fa34edbe | 451 | i, flush_type); |
ea930000 AS |
452 | } else { |
453 | gmc_v10_0_flush_gpu_tlb(adev, vmid, | |
fa34edbe | 454 | AMDGPU_GFXHUB_0, flush_type); |
ea930000 AS |
455 | } |
456 | break; | |
457 | } | |
458 | } | |
459 | ||
460 | return 0; | |
461 | } | |
462 | ||
f9df67e9 HZ |
463 | static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, |
464 | unsigned vmid, uint64_t pd_addr) | |
465 | { | |
f271fe18 | 466 | bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub); |
f9df67e9 | 467 | struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; |
caa9f483 | 468 | uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); |
f9df67e9 HZ |
469 | unsigned eng = ring->vm_inv_eng; |
470 | ||
f920d1bb | 471 | /* |
472 | * It may lose gpuvm invalidate acknowldege state across power-gating | |
473 | * off cycle, add semaphore acquire before invalidation and semaphore | |
474 | * release after invalidation to avoid entering power gated state | |
475 | * to WA the Issue | |
476 | */ | |
477 | ||
478 | /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ | |
f271fe18 | 479 | if (use_semaphore) |
f920d1bb | 480 | /* a read return value of 1 means semaphore acuqire */ |
481 | amdgpu_ring_emit_reg_wait(ring, | |
af6c5c4f HR |
482 | hub->vm_inv_eng0_sem + |
483 | hub->eng_distance * eng, 0x1, 0x1); | |
f920d1bb | 484 | |
af6c5c4f HR |
485 | amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + |
486 | (hub->ctx_addr_distance * vmid), | |
f9df67e9 HZ |
487 | lower_32_bits(pd_addr)); |
488 | ||
af6c5c4f HR |
489 | amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + |
490 | (hub->ctx_addr_distance * vmid), | |
f9df67e9 HZ |
491 | upper_32_bits(pd_addr)); |
492 | ||
af6c5c4f HR |
493 | amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + |
494 | hub->eng_distance * eng, | |
495 | hub->vm_inv_eng0_ack + | |
496 | hub->eng_distance * eng, | |
589b64a7 | 497 | req, 1 << vmid); |
f9df67e9 | 498 | |
f920d1bb | 499 | /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ |
f271fe18 | 500 | if (use_semaphore) |
f920d1bb | 501 | /* |
502 | * add semaphore release after invalidation, | |
503 | * write with 0 means semaphore release | |
504 | */ | |
af6c5c4f HR |
505 | amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + |
506 | hub->eng_distance * eng, 0); | |
f920d1bb | 507 | |
f9df67e9 HZ |
508 | return pd_addr; |
509 | } | |
510 | ||
511 | static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, | |
512 | unsigned pasid) | |
513 | { | |
514 | struct amdgpu_device *adev = ring->adev; | |
515 | uint32_t reg; | |
516 | ||
a2d15ed7 | 517 | if (ring->funcs->vmhub == AMDGPU_GFXHUB_0) |
f9df67e9 HZ |
518 | reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; |
519 | else | |
520 | reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; | |
521 | ||
522 | amdgpu_ring_emit_wreg(ring, reg, pasid); | |
523 | } | |
524 | ||
525 | /* | |
526 | * PTE format on NAVI 10: | |
527 | * 63:59 reserved | |
4005809b LG |
528 | * 58 reserved and for sienna_cichlid is used for MALL noalloc |
529 | * 57 reserved | |
f9df67e9 HZ |
530 | * 56 F |
531 | * 55 L | |
532 | * 54 reserved | |
533 | * 53:52 SW | |
534 | * 51 T | |
535 | * 50:48 mtype | |
536 | * 47:12 4k physical page base address | |
537 | * 11:7 fragment | |
538 | * 6 write | |
539 | * 5 read | |
540 | * 4 exe | |
541 | * 3 Z | |
542 | * 2 snooped | |
543 | * 1 system | |
544 | * 0 valid | |
545 | * | |
546 | * PDE format on NAVI 10: | |
547 | * 63:59 block fragment size | |
548 | * 58:55 reserved | |
549 | * 54 P | |
550 | * 53:48 reserved | |
551 | * 47:6 physical base address of PD or PTE | |
552 | * 5:3 reserved | |
553 | * 2 C | |
554 | * 1 system | |
555 | * 0 valid | |
556 | */ | |
f9df67e9 | 557 | |
71776b6d CK |
558 | static uint64_t gmc_v10_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) |
559 | { | |
560 | switch (flags) { | |
f9df67e9 | 561 | case AMDGPU_VM_MTYPE_DEFAULT: |
71776b6d | 562 | return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); |
f9df67e9 | 563 | case AMDGPU_VM_MTYPE_NC: |
71776b6d | 564 | return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); |
f9df67e9 | 565 | case AMDGPU_VM_MTYPE_WC: |
71776b6d | 566 | return AMDGPU_PTE_MTYPE_NV10(MTYPE_WC); |
f9df67e9 | 567 | case AMDGPU_VM_MTYPE_CC: |
71776b6d | 568 | return AMDGPU_PTE_MTYPE_NV10(MTYPE_CC); |
f9df67e9 | 569 | case AMDGPU_VM_MTYPE_UC: |
71776b6d | 570 | return AMDGPU_PTE_MTYPE_NV10(MTYPE_UC); |
f9df67e9 | 571 | default: |
71776b6d | 572 | return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); |
f9df67e9 | 573 | } |
f9df67e9 HZ |
574 | } |
575 | ||
576 | static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level, | |
577 | uint64_t *addr, uint64_t *flags) | |
578 | { | |
579 | if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) | |
0ca565ab | 580 | *addr = amdgpu_gmc_vram_mc2pa(adev, *addr); |
f9df67e9 HZ |
581 | BUG_ON(*addr & 0xFFFF00000000003FULL); |
582 | ||
583 | if (!adev->gmc.translate_further) | |
584 | return; | |
585 | ||
586 | if (level == AMDGPU_VM_PDB1) { | |
587 | /* Set the block fragment size */ | |
588 | if (!(*flags & AMDGPU_PDE_PTE)) | |
589 | *flags |= AMDGPU_PDE_BFS(0x9); | |
590 | ||
591 | } else if (level == AMDGPU_VM_PDB0) { | |
592 | if (*flags & AMDGPU_PDE_PTE) | |
593 | *flags &= ~AMDGPU_PDE_PTE; | |
594 | else | |
595 | *flags |= AMDGPU_PTE_TF; | |
596 | } | |
597 | } | |
598 | ||
cbfae36c CK |
599 | static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev, |
600 | struct amdgpu_bo_va_mapping *mapping, | |
601 | uint64_t *flags) | |
602 | { | |
603 | *flags &= ~AMDGPU_PTE_EXECUTABLE; | |
604 | *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; | |
605 | ||
606 | *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK; | |
607 | *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK); | |
608 | ||
609 | if (mapping->flags & AMDGPU_PTE_PRT) { | |
610 | *flags |= AMDGPU_PTE_PRT; | |
611 | *flags |= AMDGPU_PTE_SNOOPED; | |
612 | *flags |= AMDGPU_PTE_LOG; | |
613 | *flags |= AMDGPU_PTE_SYSTEM; | |
614 | *flags &= ~AMDGPU_PTE_VALID; | |
615 | } | |
616 | } | |
617 | ||
7348c20a AD |
618 | static unsigned gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev) |
619 | { | |
620 | u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); | |
621 | unsigned size; | |
622 | ||
623 | if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { | |
624 | size = AMDGPU_VBIOS_VGA_ALLOCATION; | |
625 | } else { | |
626 | u32 viewport; | |
627 | u32 pitch; | |
628 | ||
629 | viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); | |
630 | pitch = RREG32_SOC15(DCE, 0, mmHUBPREQ0_DCSURF_SURFACE_PITCH); | |
631 | size = (REG_GET_FIELD(viewport, | |
632 | HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * | |
633 | REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) * | |
634 | 4); | |
635 | } | |
636 | ||
637 | return size; | |
638 | } | |
639 | ||
f9df67e9 HZ |
640 | static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = { |
641 | .flush_gpu_tlb = gmc_v10_0_flush_gpu_tlb, | |
ea930000 | 642 | .flush_gpu_tlb_pasid = gmc_v10_0_flush_gpu_tlb_pasid, |
f9df67e9 HZ |
643 | .emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb, |
644 | .emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping, | |
71776b6d | 645 | .map_mtype = gmc_v10_0_map_mtype, |
cbfae36c | 646 | .get_vm_pde = gmc_v10_0_get_vm_pde, |
7348c20a AD |
647 | .get_vm_pte = gmc_v10_0_get_vm_pte, |
648 | .get_vbios_fb_size = gmc_v10_0_get_vbios_fb_size, | |
f9df67e9 HZ |
649 | }; |
650 | ||
651 | static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev) | |
652 | { | |
653 | if (adev->gmc.gmc_funcs == NULL) | |
654 | adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs; | |
655 | } | |
656 | ||
01eee24f JC |
657 | static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev) |
658 | { | |
659 | switch (adev->asic_type) { | |
660 | case CHIP_SIENNA_CICHLID: | |
661 | adev->umc.max_ras_err_cnt_per_query = UMC_V8_7_TOTAL_CHANNEL_NUM; | |
662 | adev->umc.channel_inst_num = UMC_V8_7_CHANNEL_INSTANCE_NUM; | |
663 | adev->umc.umc_inst_num = UMC_V8_7_UMC_INSTANCE_NUM; | |
664 | adev->umc.channel_offs = UMC_V8_7_PER_CHANNEL_OFFSET_SIENNA; | |
665 | adev->umc.channel_idx_tbl = &umc_v8_7_channel_idx_tbl[0][0]; | |
49070c4e | 666 | adev->umc.ras_funcs = &umc_v8_7_ras_funcs; |
01eee24f JC |
667 | break; |
668 | default: | |
669 | break; | |
670 | } | |
671 | } | |
672 | ||
9fb1506e OZ |
673 | |
674 | static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev) | |
675 | { | |
4d8d75a4 HR |
676 | switch (adev->asic_type) { |
677 | case CHIP_VANGOGH: | |
c817cfa3 | 678 | case CHIP_YELLOW_CARP: |
4d8d75a4 HR |
679 | adev->mmhub.funcs = &mmhub_v2_3_funcs; |
680 | break; | |
681 | default: | |
682 | adev->mmhub.funcs = &mmhub_v2_0_funcs; | |
683 | break; | |
684 | } | |
9fb1506e OZ |
685 | } |
686 | ||
8ffff9b4 OZ |
687 | static void gmc_v10_0_set_gfxhub_funcs(struct amdgpu_device *adev) |
688 | { | |
689 | switch (adev->asic_type) { | |
690 | case CHIP_SIENNA_CICHLID: | |
691 | case CHIP_NAVY_FLOUNDER: | |
6405e627 | 692 | case CHIP_VANGOGH: |
3e02ad44 | 693 | case CHIP_DIMGREY_CAVEFISH: |
2d527ea6 | 694 | case CHIP_BEIGE_GOBY: |
c817cfa3 | 695 | case CHIP_YELLOW_CARP: |
8ffff9b4 OZ |
696 | adev->gfxhub.funcs = &gfxhub_v2_1_funcs; |
697 | break; | |
698 | default: | |
699 | adev->gfxhub.funcs = &gfxhub_v2_0_funcs; | |
700 | break; | |
701 | } | |
702 | } | |
703 | ||
704 | ||
f9df67e9 HZ |
705 | static int gmc_v10_0_early_init(void *handle) |
706 | { | |
707 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
708 | ||
9fb1506e | 709 | gmc_v10_0_set_mmhub_funcs(adev); |
8ffff9b4 | 710 | gmc_v10_0_set_gfxhub_funcs(adev); |
f9df67e9 HZ |
711 | gmc_v10_0_set_gmc_funcs(adev); |
712 | gmc_v10_0_set_irq_funcs(adev); | |
01eee24f | 713 | gmc_v10_0_set_umc_funcs(adev); |
f9df67e9 HZ |
714 | |
715 | adev->gmc.shared_aperture_start = 0x2000000000000000ULL; | |
716 | adev->gmc.shared_aperture_end = | |
717 | adev->gmc.shared_aperture_start + (4ULL << 30) - 1; | |
718 | adev->gmc.private_aperture_start = 0x1000000000000000ULL; | |
719 | adev->gmc.private_aperture_end = | |
720 | adev->gmc.private_aperture_start + (4ULL << 30) - 1; | |
721 | ||
722 | return 0; | |
723 | } | |
724 | ||
725 | static int gmc_v10_0_late_init(void *handle) | |
726 | { | |
727 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
5677c520 | 728 | int r; |
f9df67e9 | 729 | |
5677c520 AD |
730 | r = amdgpu_gmc_allocate_vm_inv_eng(adev); |
731 | if (r) | |
732 | return r; | |
f9df67e9 | 733 | |
0ad7a64d JC |
734 | r = amdgpu_gmc_ras_late_init(adev); |
735 | if (r) | |
736 | return r; | |
737 | ||
f9df67e9 HZ |
738 | return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); |
739 | } | |
740 | ||
741 | static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev, | |
742 | struct amdgpu_gmc *mc) | |
743 | { | |
744 | u64 base = 0; | |
745 | ||
8ffff9b4 | 746 | base = adev->gfxhub.funcs->get_fb_location(adev); |
f9df67e9 | 747 | |
fdb8483b JC |
748 | /* add the xgmi offset of the physical node */ |
749 | base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; | |
750 | ||
f9df67e9 HZ |
751 | amdgpu_gmc_vram_location(adev, &adev->gmc, base); |
752 | amdgpu_gmc_gart_location(adev, mc); | |
99698b51 | 753 | amdgpu_gmc_agp_location(adev, mc); |
f9df67e9 HZ |
754 | |
755 | /* base offset of vram pages */ | |
8ffff9b4 | 756 | adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev); |
fdb8483b JC |
757 | |
758 | /* add the xgmi offset of the physical node */ | |
759 | adev->vm_manager.vram_base_offset += | |
760 | adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; | |
f9df67e9 HZ |
761 | } |
762 | ||
763 | /** | |
764 | * gmc_v10_0_mc_init - initialize the memory controller driver params | |
765 | * | |
766 | * @adev: amdgpu_device pointer | |
767 | * | |
768 | * Look up the amount of vram, vram width, and decide how to place | |
769 | * vram and gart within the GPU's physical address space. | |
770 | * Returns 0 for success. | |
771 | */ | |
772 | static int gmc_v10_0_mc_init(struct amdgpu_device *adev) | |
773 | { | |
78b7dfd9 | 774 | int r; |
f9df67e9 HZ |
775 | |
776 | /* size in MB on si */ | |
777 | adev->gmc.mc_vram_size = | |
bebc0762 | 778 | adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; |
f9df67e9 | 779 | adev->gmc.real_vram_size = adev->gmc.mc_vram_size; |
78b7dfd9 AS |
780 | |
781 | if (!(adev->flags & AMD_IS_APU)) { | |
782 | r = amdgpu_device_resize_fb_bar(adev); | |
783 | if (r) | |
784 | return r; | |
785 | } | |
786 | adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); | |
787 | adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); | |
f9df67e9 | 788 | |
6405e627 HR |
789 | #ifdef CONFIG_X86_64 |
790 | if (adev->flags & AMD_IS_APU) { | |
791 | adev->gmc.aper_base = adev->gfxhub.funcs->get_mc_fb_offset(adev); | |
792 | adev->gmc.aper_size = adev->gmc.real_vram_size; | |
793 | } | |
794 | #endif | |
795 | ||
f9df67e9 | 796 | /* In case the PCI BAR is larger than the actual amount of vram */ |
78b7dfd9 | 797 | adev->gmc.visible_vram_size = adev->gmc.aper_size; |
f9df67e9 HZ |
798 | if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) |
799 | adev->gmc.visible_vram_size = adev->gmc.real_vram_size; | |
800 | ||
801 | /* set the gart size */ | |
802 | if (amdgpu_gart_size == -1) { | |
803 | switch (adev->asic_type) { | |
804 | case CHIP_NAVI10: | |
05d72b8d | 805 | case CHIP_NAVI14: |
4a0e815f | 806 | case CHIP_NAVI12: |
57d70602 | 807 | case CHIP_SIENNA_CICHLID: |
0287ac57 | 808 | case CHIP_NAVY_FLOUNDER: |
6405e627 | 809 | case CHIP_VANGOGH: |
a1435469 | 810 | case CHIP_DIMGREY_CAVEFISH: |
d2bfc50d | 811 | case CHIP_BEIGE_GOBY: |
c817cfa3 | 812 | case CHIP_YELLOW_CARP: |
f9df67e9 HZ |
813 | default: |
814 | adev->gmc.gart_size = 512ULL << 20; | |
815 | break; | |
816 | } | |
817 | } else | |
818 | adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; | |
819 | ||
820 | gmc_v10_0_vram_gtt_location(adev, &adev->gmc); | |
821 | ||
822 | return 0; | |
823 | } | |
824 | ||
825 | static int gmc_v10_0_gart_init(struct amdgpu_device *adev) | |
826 | { | |
827 | int r; | |
828 | ||
829 | if (adev->gart.bo) { | |
830 | WARN(1, "NAVI10 PCIE GART already initialized\n"); | |
831 | return 0; | |
832 | } | |
833 | ||
834 | /* Initialize common gart structure */ | |
835 | r = amdgpu_gart_init(adev); | |
836 | if (r) | |
837 | return r; | |
838 | ||
839 | adev->gart.table_size = adev->gart.num_gpu_pages * 8; | |
840 | adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) | | |
841 | AMDGPU_PTE_EXECUTABLE; | |
842 | ||
843 | return amdgpu_gart_table_vram_alloc(adev); | |
844 | } | |
845 | ||
f9df67e9 HZ |
846 | static int gmc_v10_0_sw_init(void *handle) |
847 | { | |
ad02e08e | 848 | int r, vram_width = 0, vram_type = 0, vram_vendor = 0; |
f9df67e9 HZ |
849 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
850 | ||
8ffff9b4 | 851 | adev->gfxhub.funcs->init(adev); |
0b3df16b | 852 | |
9fb1506e | 853 | adev->mmhub.funcs->init(adev); |
f9df67e9 HZ |
854 | |
855 | spin_lock_init(&adev->gmc.invalidate_lock); | |
856 | ||
6405e627 HR |
857 | if ((adev->flags & AMD_IS_APU) && amdgpu_emu_mode == 1) { |
858 | adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4; | |
859 | adev->gmc.vram_width = 64; | |
860 | } else if (amdgpu_emu_mode == 1) { | |
0b3df16b | 861 | adev->gmc.vram_type = AMDGPU_VRAM_TYPE_GDDR6; |
631cdbd2 | 862 | adev->gmc.vram_width = 1 * 128; /* numchan * chansize */ |
0b3df16b LG |
863 | } else { |
864 | r = amdgpu_atomfirmware_get_vram_info(adev, | |
865 | &vram_width, &vram_type, &vram_vendor); | |
866 | adev->gmc.vram_width = vram_width; | |
867 | ||
868 | adev->gmc.vram_type = vram_type; | |
869 | adev->gmc.vram_vendor = vram_vendor; | |
870 | } | |
631cdbd2 | 871 | |
f9df67e9 HZ |
872 | switch (adev->asic_type) { |
873 | case CHIP_NAVI10: | |
05d72b8d | 874 | case CHIP_NAVI14: |
4a0e815f | 875 | case CHIP_NAVI12: |
57d70602 | 876 | case CHIP_SIENNA_CICHLID: |
0287ac57 | 877 | case CHIP_NAVY_FLOUNDER: |
6405e627 | 878 | case CHIP_VANGOGH: |
a1435469 | 879 | case CHIP_DIMGREY_CAVEFISH: |
d2bfc50d | 880 | case CHIP_BEIGE_GOBY: |
c817cfa3 | 881 | case CHIP_YELLOW_CARP: |
1daa2bfa | 882 | adev->num_vmhubs = 2; |
f9df67e9 HZ |
883 | /* |
884 | * To fulfill 4-level page support, | |
4a0e815f | 885 | * vm size is 256TB (48bit), maximum size of Navi10/Navi14/Navi12, |
f9df67e9 HZ |
886 | * block size 512 (9bit) |
887 | */ | |
888 | amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); | |
889 | break; | |
890 | default: | |
891 | break; | |
892 | } | |
893 | ||
894 | /* This interrupt is VMC page fault.*/ | |
895 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, | |
896 | VMC_1_0__SRCID__VM_FAULT, | |
897 | &adev->gmc.vm_fault); | |
5021e9a8 ND |
898 | |
899 | if (r) | |
900 | return r; | |
901 | ||
f9df67e9 HZ |
902 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, |
903 | UTCL2_1_0__SRCID__FAULT, | |
904 | &adev->gmc.vm_fault); | |
905 | if (r) | |
906 | return r; | |
907 | ||
01eee24f JC |
908 | if (!amdgpu_sriov_vf(adev)) { |
909 | /* interrupt sent to DF. */ | |
910 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0, | |
911 | &adev->gmc.ecc_irq); | |
912 | if (r) | |
913 | return r; | |
914 | } | |
915 | ||
f9df67e9 HZ |
916 | /* |
917 | * Set the internal MC address mask This is the max address of the GPU's | |
918 | * internal address space. | |
919 | */ | |
920 | adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ | |
921 | ||
244511f3 | 922 | r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); |
f9df67e9 | 923 | if (r) { |
f9df67e9 | 924 | printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); |
244511f3 | 925 | return r; |
f9df67e9 HZ |
926 | } |
927 | ||
fdb8483b | 928 | if (adev->gmc.xgmi.supported) { |
8ffff9b4 | 929 | r = adev->gfxhub.funcs->get_xgmi_info(adev); |
fdb8483b JC |
930 | if (r) |
931 | return r; | |
932 | } | |
933 | ||
f9df67e9 HZ |
934 | r = gmc_v10_0_mc_init(adev); |
935 | if (r) | |
936 | return r; | |
937 | ||
7348c20a | 938 | amdgpu_gmc_get_vbios_allocations(adev); |
e15a5fb9 | 939 | amdgpu_gmc_get_reserved_allocation(adev); |
f9df67e9 HZ |
940 | |
941 | /* Memory manager */ | |
942 | r = amdgpu_bo_init(adev); | |
943 | if (r) | |
944 | return r; | |
945 | ||
946 | r = gmc_v10_0_gart_init(adev); | |
947 | if (r) | |
948 | return r; | |
949 | ||
950 | /* | |
951 | * number of VMs | |
952 | * VMID 0 is reserved for System | |
953 | * amdgpu graphics/compute will use VMIDs 1-7 | |
954 | * amdkfd will use VMIDs 8-15 | |
955 | */ | |
40111ec2 | 956 | adev->vm_manager.first_kfd_vmid = 8; |
f9df67e9 HZ |
957 | |
958 | amdgpu_vm_manager_init(adev); | |
959 | ||
960 | return 0; | |
961 | } | |
962 | ||
963 | /** | |
2cce318c | 964 | * gmc_v10_0_gart_fini - vm fini callback |
f9df67e9 HZ |
965 | * |
966 | * @adev: amdgpu_device pointer | |
967 | * | |
968 | * Tears down the driver GART/VM setup (CIK). | |
969 | */ | |
970 | static void gmc_v10_0_gart_fini(struct amdgpu_device *adev) | |
971 | { | |
972 | amdgpu_gart_table_vram_free(adev); | |
f9df67e9 HZ |
973 | } |
974 | ||
975 | static int gmc_v10_0_sw_fini(void *handle) | |
976 | { | |
977 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
978 | ||
979 | amdgpu_vm_manager_fini(adev); | |
980 | gmc_v10_0_gart_fini(adev); | |
981 | amdgpu_gem_force_release(adev); | |
982 | amdgpu_bo_fini(adev); | |
983 | ||
984 | return 0; | |
985 | } | |
986 | ||
987 | static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev) | |
988 | { | |
989 | switch (adev->asic_type) { | |
990 | case CHIP_NAVI10: | |
05d72b8d | 991 | case CHIP_NAVI14: |
4a0e815f | 992 | case CHIP_NAVI12: |
57d70602 | 993 | case CHIP_SIENNA_CICHLID: |
0287ac57 | 994 | case CHIP_NAVY_FLOUNDER: |
6405e627 | 995 | case CHIP_VANGOGH: |
a1435469 | 996 | case CHIP_DIMGREY_CAVEFISH: |
d2bfc50d | 997 | case CHIP_BEIGE_GOBY: |
c817cfa3 | 998 | case CHIP_YELLOW_CARP: |
f9df67e9 HZ |
999 | break; |
1000 | default: | |
1001 | break; | |
1002 | } | |
1003 | } | |
1004 | ||
1005 | /** | |
1006 | * gmc_v10_0_gart_enable - gart enable | |
1007 | * | |
1008 | * @adev: amdgpu_device pointer | |
1009 | */ | |
1010 | static int gmc_v10_0_gart_enable(struct amdgpu_device *adev) | |
1011 | { | |
1012 | int r; | |
1013 | bool value; | |
f9df67e9 HZ |
1014 | |
1015 | if (adev->gart.bo == NULL) { | |
1016 | dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); | |
1017 | return -EINVAL; | |
1018 | } | |
1019 | ||
1020 | r = amdgpu_gart_table_vram_pin(adev); | |
1021 | if (r) | |
1022 | return r; | |
1023 | ||
8ffff9b4 | 1024 | r = adev->gfxhub.funcs->gart_enable(adev); |
f9df67e9 HZ |
1025 | if (r) |
1026 | return r; | |
1027 | ||
9fb1506e | 1028 | r = adev->mmhub.funcs->gart_enable(adev); |
f9df67e9 HZ |
1029 | if (r) |
1030 | return r; | |
1031 | ||
bf087285 | 1032 | adev->hdp.funcs->init_registers(adev); |
f9df67e9 HZ |
1033 | |
1034 | /* Flush HDP after it is initialized */ | |
bf087285 | 1035 | adev->hdp.funcs->flush_hdp(adev, NULL); |
f9df67e9 HZ |
1036 | |
1037 | value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? | |
1038 | false : true; | |
1039 | ||
8ffff9b4 | 1040 | adev->gfxhub.funcs->set_fault_enable_default(adev, value); |
9fb1506e | 1041 | adev->mmhub.funcs->set_fault_enable_default(adev, value); |
3ff98548 OZ |
1042 | gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB_0, 0); |
1043 | gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0); | |
f9df67e9 HZ |
1044 | |
1045 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", | |
1046 | (unsigned)(adev->gmc.gart_size >> 20), | |
1047 | (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); | |
1048 | ||
1049 | adev->gart.ready = true; | |
1050 | ||
1051 | return 0; | |
1052 | } | |
1053 | ||
1054 | static int gmc_v10_0_hw_init(void *handle) | |
1055 | { | |
1056 | int r; | |
1057 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1058 | ||
1059 | /* The sequence of these two function calls matters.*/ | |
1060 | gmc_v10_0_init_golden_registers(adev); | |
1061 | ||
1062 | r = gmc_v10_0_gart_enable(adev); | |
1063 | if (r) | |
1064 | return r; | |
1065 | ||
01eee24f JC |
1066 | if (adev->umc.funcs && adev->umc.funcs->init_registers) |
1067 | adev->umc.funcs->init_registers(adev); | |
1068 | ||
f9df67e9 HZ |
1069 | return 0; |
1070 | } | |
1071 | ||
1072 | /** | |
1073 | * gmc_v10_0_gart_disable - gart disable | |
1074 | * | |
1075 | * @adev: amdgpu_device pointer | |
1076 | * | |
1077 | * This disables all VM page table. | |
1078 | */ | |
1079 | static void gmc_v10_0_gart_disable(struct amdgpu_device *adev) | |
1080 | { | |
8ffff9b4 | 1081 | adev->gfxhub.funcs->gart_disable(adev); |
9fb1506e | 1082 | adev->mmhub.funcs->gart_disable(adev); |
f9df67e9 HZ |
1083 | amdgpu_gart_table_vram_unpin(adev); |
1084 | } | |
1085 | ||
1086 | static int gmc_v10_0_hw_fini(void *handle) | |
1087 | { | |
1088 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1089 | ||
1090 | if (amdgpu_sriov_vf(adev)) { | |
1091 | /* full access mode, so don't touch any GMC register */ | |
1092 | DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); | |
1093 | return 0; | |
1094 | } | |
1095 | ||
01eee24f | 1096 | amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); |
f9df67e9 HZ |
1097 | amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); |
1098 | gmc_v10_0_gart_disable(adev); | |
1099 | ||
1100 | return 0; | |
1101 | } | |
1102 | ||
1103 | static int gmc_v10_0_suspend(void *handle) | |
1104 | { | |
1105 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1106 | ||
1107 | gmc_v10_0_hw_fini(adev); | |
1108 | ||
1109 | return 0; | |
1110 | } | |
1111 | ||
1112 | static int gmc_v10_0_resume(void *handle) | |
1113 | { | |
1114 | int r; | |
1115 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1116 | ||
1117 | r = gmc_v10_0_hw_init(adev); | |
1118 | if (r) | |
1119 | return r; | |
1120 | ||
1121 | amdgpu_vmid_reset_all(adev); | |
1122 | ||
1123 | return 0; | |
1124 | } | |
1125 | ||
1126 | static bool gmc_v10_0_is_idle(void *handle) | |
1127 | { | |
1128 | /* MC is always ready in GMC v10.*/ | |
1129 | return true; | |
1130 | } | |
1131 | ||
1132 | static int gmc_v10_0_wait_for_idle(void *handle) | |
1133 | { | |
1134 | /* There is no need to wait for MC idle in GMC v10.*/ | |
1135 | return 0; | |
1136 | } | |
1137 | ||
1138 | static int gmc_v10_0_soft_reset(void *handle) | |
1139 | { | |
1140 | return 0; | |
1141 | } | |
1142 | ||
1143 | static int gmc_v10_0_set_clockgating_state(void *handle, | |
1144 | enum amd_clockgating_state state) | |
1145 | { | |
1146 | int r; | |
1147 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1148 | ||
9fb1506e | 1149 | r = adev->mmhub.funcs->set_clockgating(adev, state); |
f9df67e9 HZ |
1150 | if (r) |
1151 | return r; | |
1152 | ||
f267242e | 1153 | if (adev->asic_type >= CHIP_SIENNA_CICHLID && |
c817cfa3 | 1154 | adev->asic_type <= CHIP_YELLOW_CARP) |
920a4cd3 LG |
1155 | return athub_v2_1_set_clockgating(adev, state); |
1156 | else | |
1157 | return athub_v2_0_set_clockgating(adev, state); | |
f9df67e9 HZ |
1158 | } |
1159 | ||
1160 | static void gmc_v10_0_get_clockgating_state(void *handle, u32 *flags) | |
1161 | { | |
1162 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1163 | ||
9fb1506e | 1164 | adev->mmhub.funcs->get_clockgating(adev, flags); |
f9df67e9 | 1165 | |
f267242e | 1166 | if (adev->asic_type >= CHIP_SIENNA_CICHLID && |
c817cfa3 | 1167 | adev->asic_type <= CHIP_YELLOW_CARP) |
920a4cd3 LG |
1168 | athub_v2_1_get_clockgating(adev, flags); |
1169 | else | |
1170 | athub_v2_0_get_clockgating(adev, flags); | |
f9df67e9 HZ |
1171 | } |
1172 | ||
1173 | static int gmc_v10_0_set_powergating_state(void *handle, | |
1174 | enum amd_powergating_state state) | |
1175 | { | |
1176 | return 0; | |
1177 | } | |
1178 | ||
1179 | const struct amd_ip_funcs gmc_v10_0_ip_funcs = { | |
1180 | .name = "gmc_v10_0", | |
1181 | .early_init = gmc_v10_0_early_init, | |
1182 | .late_init = gmc_v10_0_late_init, | |
1183 | .sw_init = gmc_v10_0_sw_init, | |
1184 | .sw_fini = gmc_v10_0_sw_fini, | |
1185 | .hw_init = gmc_v10_0_hw_init, | |
1186 | .hw_fini = gmc_v10_0_hw_fini, | |
1187 | .suspend = gmc_v10_0_suspend, | |
1188 | .resume = gmc_v10_0_resume, | |
1189 | .is_idle = gmc_v10_0_is_idle, | |
1190 | .wait_for_idle = gmc_v10_0_wait_for_idle, | |
1191 | .soft_reset = gmc_v10_0_soft_reset, | |
1192 | .set_clockgating_state = gmc_v10_0_set_clockgating_state, | |
1193 | .set_powergating_state = gmc_v10_0_set_powergating_state, | |
1194 | .get_clockgating_state = gmc_v10_0_get_clockgating_state, | |
1195 | }; | |
1196 | ||
1197 | const struct amdgpu_ip_block_version gmc_v10_0_ip_block = | |
1198 | { | |
1199 | .type = AMD_IP_BLOCK_TYPE_GMC, | |
1200 | .major = 10, | |
1201 | .minor = 0, | |
1202 | .rev = 0, | |
1203 | .funcs = &gmc_v10_0_ip_funcs, | |
1204 | }; |