]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/amdgpu: change default sched jobs to 32
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / amdgpu / gmc_v8_0.c
CommitLineData
aaa36a97
AD		 1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include "drmP.h"
25#include "amdgpu.h"
26#include "gmc_v8_0.h"
27#include "amdgpu_ucode.h"
28
29#include "gmc/gmc_8_1_d.h"
30#include "gmc/gmc_8_1_sh_mask.h"
31
32#include "bif/bif_5_0_d.h"
33#include "bif/bif_5_0_sh_mask.h"
34
35#include "oss/oss_3_0_d.h"
36#include "oss/oss_3_0_sh_mask.h"
37
38#include "vid.h"
39#include "vi.h"
40
81c59f54 41
aaa36a97
AD		 42static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev);
43static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev);
44
c65444fe
JZ		 45MODULE_FIRMWARE("amdgpu/topaz_mc.bin");
46MODULE_FIRMWARE("amdgpu/tonga_mc.bin");
127a2628 47MODULE_FIRMWARE("amdgpu/fiji_mc.bin");
aaa36a97
AD		 48
49static const u32 golden_settings_tonga_a11[] =
50{
51 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
52 mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028,
53 mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991,
54 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
55 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
56 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
57 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
58};
59
60static const u32 tonga_mgcg_cgcg_init[] =
61{
62 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
63};
64
127a2628
DZ		 65static const u32 golden_settings_fiji_a10[] =
66{
67 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
68 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
69 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
70 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
71};
72
73static const u32 fiji_mgcg_cgcg_init[] =
74{
75 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
76};
77
aaa36a97
AD		 78static const u32 golden_settings_iceland_a11[] =
79{
80 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
81 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
82 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
83 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
84};
85
86static const u32 iceland_mgcg_cgcg_init[] =
87{
c61bf649 88 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
aaa36a97
AD		 89};
90
91static const u32 cz_mgcg_cgcg_init[] =
92{
93 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
94};
95
aade2f04
SL		 96static const u32 stoney_mgcg_cgcg_init[] =
97{
98 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
99};
100
101
aaa36a97
AD		 102static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
103{
104 switch (adev->asic_type) {
105 case CHIP_TOPAZ:
106 amdgpu_program_register_sequence(adev,
107 iceland_mgcg_cgcg_init,
108 (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
109 amdgpu_program_register_sequence(adev,
110 golden_settings_iceland_a11,
111 (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
112 break;
127a2628
DZ		 113 case CHIP_FIJI:
114 amdgpu_program_register_sequence(adev,
115 fiji_mgcg_cgcg_init,
116 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
117 amdgpu_program_register_sequence(adev,
118 golden_settings_fiji_a10,
119 (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
120 break;
aaa36a97
AD		 121 case CHIP_TONGA:
122 amdgpu_program_register_sequence(adev,
123 tonga_mgcg_cgcg_init,
124 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
125 amdgpu_program_register_sequence(adev,
126 golden_settings_tonga_a11,
127 (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
128 break;
129 case CHIP_CARRIZO:
130 amdgpu_program_register_sequence(adev,
131 cz_mgcg_cgcg_init,
132 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
133 break;
aade2f04
SL		 134 case CHIP_STONEY:
135 amdgpu_program_register_sequence(adev,
136 stoney_mgcg_cgcg_init,
137 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
138 break;
aaa36a97
AD		 139 default:
140 break;
141 }
142}
143
144/**
145 * gmc8_mc_wait_for_idle - wait for MC idle callback.
146 *
147 * @adev: amdgpu_device pointer
148 *
149 * Wait for the MC (memory controller) to be idle.
150 * (evergreen+).
151 * Returns 0 if the MC is idle, -1 if not.
152 */
153int gmc_v8_0_mc_wait_for_idle(struct amdgpu_device *adev)
154{
155 unsigned i;
156 u32 tmp;
157
158 for (i = 0; i < adev->usec_timeout; i++) {
159 /* read MC_STATUS */
160 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__VMC_BUSY_MASK |
161 SRBM_STATUS__MCB_BUSY_MASK |
162 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
163 SRBM_STATUS__MCC_BUSY_MASK |
164 SRBM_STATUS__MCD_BUSY_MASK |
165 SRBM_STATUS__VMC1_BUSY_MASK);
166 if (!tmp)
167 return 0;
168 udelay(1);
169 }
170 return -1;
171}
172
173void gmc_v8_0_mc_stop(struct amdgpu_device *adev,
174 struct amdgpu_mode_mc_save *save)
175{
176 u32 blackout;
177
178 if (adev->mode_info.num_crtc)
179 amdgpu_display_stop_mc_access(adev, save);
180
181 amdgpu_asic_wait_for_mc_idle(adev);
182
183 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
184 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
185 /* Block CPU access */
186 WREG32(mmBIF_FB_EN, 0);
187 /* blackout the MC */
188 blackout = REG_SET_FIELD(blackout,
189 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 1);
190 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
191 }
192 /* wait for the MC to settle */
193 udelay(100);
194}
195
196void gmc_v8_0_mc_resume(struct amdgpu_device *adev,
197 struct amdgpu_mode_mc_save *save)
198{
199 u32 tmp;
200
201 /* unblackout the MC */
202 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
203 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
204 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
205 /* allow CPU access */
206 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
207 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
208 WREG32(mmBIF_FB_EN, tmp);
209
210 if (adev->mode_info.num_crtc)
211 amdgpu_display_resume_mc_access(adev, save);
212}
213
214/**
215 * gmc_v8_0_init_microcode - load ucode images from disk
216 *
217 * @adev: amdgpu_device pointer
218 *
219 * Use the firmware interface to load the ucode images into
220 * the driver (not loaded into hw).
221 * Returns 0 on success, error on failure.
222 */
223static int gmc_v8_0_init_microcode(struct amdgpu_device *adev)
224{
225 const char *chip_name;
226 char fw_name[30];
227 int err;
228
229 DRM_DEBUG("\n");
230
231 switch (adev->asic_type) {
232 case CHIP_TOPAZ:
233 chip_name = "topaz";
234 break;
235 case CHIP_TONGA:
236 chip_name = "tonga";
237 break;
127a2628
DZ		 238 case CHIP_FIJI:
239 chip_name = "fiji";
240 break;
aaa36a97 241 case CHIP_CARRIZO:
aade2f04 242 case CHIP_STONEY:
aaa36a97
AD		 243 return 0;
244 default: BUG();
245 }
246
c65444fe 247 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
aaa36a97
AD		 248 err = request_firmware(&adev->mc.fw, fw_name, adev->dev);
249 if (err)
250 goto out;
251 err = amdgpu_ucode_validate(adev->mc.fw);
252
253out:
254 if (err) {
255 printk(KERN_ERR
256 "mc: Failed to load firmware \"%s\"\n",
257 fw_name);
258 release_firmware(adev->mc.fw);
259 adev->mc.fw = NULL;
260 }
261 return err;
262}
263
264/**
265 * gmc_v8_0_mc_load_microcode - load MC ucode into the hw
266 *
267 * @adev: amdgpu_device pointer
268 *
269 * Load the GDDR MC ucode into the hw (CIK).
270 * Returns 0 on success, error on failure.
271 */
272static int gmc_v8_0_mc_load_microcode(struct amdgpu_device *adev)
273{
274 const struct mc_firmware_header_v1_0 *hdr;
275 const __le32 *fw_data = NULL;
276 const __le32 *io_mc_regs = NULL;
277 u32 running, blackout = 0;
278 int i, ucode_size, regs_size;
279
280 if (!adev->mc.fw)
281 return -EINVAL;
282
283 hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
284 amdgpu_ucode_print_mc_hdr(&hdr->header);
285
286 adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
287 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
288 io_mc_regs = (const __le32 *)
289 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
290 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
291 fw_data = (const __le32 *)
292 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
293
294 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
295
296 if (running == 0) {
297 if (running) {
298 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
299 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
300 }
301
302 /* reset the engine and set to writable */
303 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
304 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
305
306 /* load mc io regs */
307 for (i = 0; i < regs_size; i++) {
308 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
309 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
310 }
311 /* load the MC ucode */
312 for (i = 0; i < ucode_size; i++)
313 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
314
315 /* put the engine back into the active state */
316 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
317 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
318 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
319
320 /* wait for training to complete */
321 for (i = 0; i < adev->usec_timeout; i++) {
322 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
323 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
324 break;
325 udelay(1);
326 }
327 for (i = 0; i < adev->usec_timeout; i++) {
328 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
329 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
330 break;
331 udelay(1);
332 }
333
334 if (running)
335 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
336 }
337
338 return 0;
339}
340
341static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev,
342 struct amdgpu_mc *mc)
343{
344 if (mc->mc_vram_size > 0xFFC0000000ULL) {
345 /* leave room for at least 1024M GTT */
346 dev_warn(adev->dev, "limiting VRAM\n");
347 mc->real_vram_size = 0xFFC0000000ULL;
348 mc->mc_vram_size = 0xFFC0000000ULL;
349 }
350 amdgpu_vram_location(adev, &adev->mc, 0);
351 adev->mc.gtt_base_align = 0;
352 amdgpu_gtt_location(adev, mc);
353}
354
355/**
356 * gmc_v8_0_mc_program - program the GPU memory controller
357 *
358 * @adev: amdgpu_device pointer
359 *
360 * Set the location of vram, gart, and AGP in the GPU's
361 * physical address space (CIK).
362 */
363static void gmc_v8_0_mc_program(struct amdgpu_device *adev)
364{
365 struct amdgpu_mode_mc_save save;
366 u32 tmp;
367 int i, j;
368
369 /* Initialize HDP */
370 for (i = 0, j = 0; i < 32; i++, j += 0x6) {
371 WREG32((0xb05 + j), 0x00000000);
372 WREG32((0xb06 + j), 0x00000000);
373 WREG32((0xb07 + j), 0x00000000);
374 WREG32((0xb08 + j), 0x00000000);
375 WREG32((0xb09 + j), 0x00000000);
376 }
377 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
378
379 if (adev->mode_info.num_crtc)
380 amdgpu_display_set_vga_render_state(adev, false);
381
382 gmc_v8_0_mc_stop(adev, &save);
383 if (amdgpu_asic_wait_for_mc_idle(adev)) {
384 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
385 }
386 /* Update configuration */
387 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
388 adev->mc.vram_start >> 12);
389 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
390 adev->mc.vram_end >> 12);
391 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
392 adev->vram_scratch.gpu_addr >> 12);
393 tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16;
394 tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF);
395 WREG32(mmMC_VM_FB_LOCATION, tmp);
396 /* XXX double check these! */
397 WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8));
398 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
399 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
400 WREG32(mmMC_VM_AGP_BASE, 0);
401 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
402 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
403 if (amdgpu_asic_wait_for_mc_idle(adev)) {
404 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
405 }
406 gmc_v8_0_mc_resume(adev, &save);
407
408 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
409
410 tmp = RREG32(mmHDP_MISC_CNTL);
411 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
412 WREG32(mmHDP_MISC_CNTL, tmp);
413
414 tmp = RREG32(mmHDP_HOST_PATH_CNTL);
415 WREG32(mmHDP_HOST_PATH_CNTL, tmp);
416}
417
418/**
419 * gmc_v8_0_mc_init - initialize the memory controller driver params
420 *
421 * @adev: amdgpu_device pointer
422 *
423 * Look up the amount of vram, vram width, and decide how to place
424 * vram and gart within the GPU's physical address space (CIK).
425 * Returns 0 for success.
426 */
427static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
428{
429 u32 tmp;
430 int chansize, numchan;
431
432 /* Get VRAM informations */
433 tmp = RREG32(mmMC_ARB_RAMCFG);
434 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
435 chansize = 64;
436 } else {
437 chansize = 32;
438 }
439 tmp = RREG32(mmMC_SHARED_CHMAP);
440 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
441 case 0:
442 default:
443 numchan = 1;
444 break;
445 case 1:
446 numchan = 2;
447 break;
448 case 2:
449 numchan = 4;
450 break;
451 case 3:
452 numchan = 8;
453 break;
454 case 4:
455 numchan = 3;
456 break;
457 case 5:
458 numchan = 6;
459 break;
460 case 6:
461 numchan = 10;
462 break;
463 case 7:
464 numchan = 12;
465 break;
466 case 8:
467 numchan = 16;
468 break;
469 }
470 adev->mc.vram_width = numchan * chansize;
471 /* Could aper size report 0 ? */
472 adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
473 adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
474 /* size in MB on si */
475 adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
476 adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
477 adev->mc.visible_vram_size = adev->mc.aper_size;
478
479 /* unless the user had overridden it, set the gart
480 * size equal to the 1024 or vram, whichever is larger.
481 */
482 if (amdgpu_gart_size == -1)
483 adev->mc.gtt_size = max((1024ULL << 20), adev->mc.mc_vram_size);
484 else
485 adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20;
486
487 gmc_v8_0_vram_gtt_location(adev, &adev->mc);
488
489 return 0;
490}
491
492/*
493 * GART
494 * VMID 0 is the physical GPU addresses as used by the kernel.
495 * VMIDs 1-15 are used for userspace clients and are handled
496 * by the amdgpu vm/hsa code.
497 */
498
499/**
500 * gmc_v8_0_gart_flush_gpu_tlb - gart tlb flush callback
501 *
502 * @adev: amdgpu_device pointer
503 * @vmid: vm instance to flush
504 *
505 * Flush the TLB for the requested page table (CIK).
506 */
507static void gmc_v8_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
508 uint32_t vmid)
509{
510 /* flush hdp cache */
511 WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
512
513 /* bits 0-15 are the VM contexts0-15 */
514 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
515}
516
517/**
518 * gmc_v8_0_gart_set_pte_pde - update the page tables using MMIO
519 *
520 * @adev: amdgpu_device pointer
521 * @cpu_pt_addr: cpu address of the page table
522 * @gpu_page_idx: entry in the page table to update
523 * @addr: dst addr to write into pte/pde
524 * @flags: access flags
525 *
526 * Update the page tables using the CPU.
527 */
528static int gmc_v8_0_gart_set_pte_pde(struct amdgpu_device *adev,
529 void *cpu_pt_addr,
530 uint32_t gpu_page_idx,
531 uint64_t addr,
532 uint32_t flags)
533{
534 void __iomem *ptr = (void *)cpu_pt_addr;
535 uint64_t value;
536
537 /*
538 * PTE format on VI:
539 * 63:40 reserved
540 * 39:12 4k physical page base address
541 * 11:7 fragment
542 * 6 write
543 * 5 read
544 * 4 exe
545 * 3 reserved
546 * 2 snooped
547 * 1 system
548 * 0 valid
549 *
550 * PDE format on VI:
551 * 63:59 block fragment size
552 * 58:40 reserved
553 * 39:1 physical base address of PTE
554 * bits 5:1 must be 0.
555 * 0 valid
556 */
557 value = addr & 0x000000FFFFFFF000ULL;
558 value |= flags;
559 writeq(value, ptr + (gpu_page_idx * 8));
560
561 return 0;
562}
563
d9c13156
CK		 564/**
565 * gmc_v8_0_set_fault_enable_default - update VM fault handling
566 *
567 * @adev: amdgpu_device pointer
568 * @value: true redirects VM faults to the default page
569 */
570static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev,
571 bool value)
572{
573 u32 tmp;
574
575 tmp = RREG32(mmVM_CONTEXT1_CNTL);
576 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
577 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
578 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
579 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
580 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
581 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
582 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
583 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
584 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
585 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
586 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
587 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
588 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
589 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
590 WREG32(mmVM_CONTEXT1_CNTL, tmp);
591}
592
aaa36a97
AD		 593/**
594 * gmc_v8_0_gart_enable - gart enable
595 *
596 * @adev: amdgpu_device pointer
597 *
598 * This sets up the TLBs, programs the page tables for VMID0,
599 * sets up the hw for VMIDs 1-15 which are allocated on
600 * demand, and sets up the global locations for the LDS, GDS,
601 * and GPUVM for FSA64 clients (CIK).
602 * Returns 0 for success, errors for failure.
603 */
604static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
605{
606 int r, i;
607 u32 tmp;
608
609 if (adev->gart.robj == NULL) {
610 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
611 return -EINVAL;
612 }
613 r = amdgpu_gart_table_vram_pin(adev);
614 if (r)
615 return r;
616 /* Setup TLB control */
617 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
618 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
619 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
620 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
621 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
622 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
623 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
624 /* Setup L2 cache */
625 tmp = RREG32(mmVM_L2_CNTL);
626 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
627 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
628 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
629 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
630 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
631 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
a80b3047 632 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
aaa36a97
AD		 633 WREG32(mmVM_L2_CNTL, tmp);
634 tmp = RREG32(mmVM_L2_CNTL2);
635 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
636 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
637 WREG32(mmVM_L2_CNTL2, tmp);
638 tmp = RREG32(mmVM_L2_CNTL3);
639 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
640 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 4);
641 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 4);
642 WREG32(mmVM_L2_CNTL3, tmp);
643 /* XXX: set to enable PTE/PDE in system memory */
644 tmp = RREG32(mmVM_L2_CNTL4);
645 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0);
646 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0);
647 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0);
648 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0);
649 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0);
650 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0);
651 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0);
652 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0);
653 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0);
654 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0);
655 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0);
656 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0);
657 WREG32(mmVM_L2_CNTL4, tmp);
658 /* setup context0 */
659 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12);
25a595e4 660 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, (adev->mc.gtt_end >> 12) - 1);
aaa36a97
AD		 661 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
662 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
663 (u32)(adev->dummy_page.addr >> 12));
664 WREG32(mmVM_CONTEXT0_CNTL2, 0);
665 tmp = RREG32(mmVM_CONTEXT0_CNTL);
666 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
667 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
668 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
669 WREG32(mmVM_CONTEXT0_CNTL, tmp);
670
671 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0);
672 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0);
673 WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0);
674
675 /* empty context1-15 */
676 /* FIXME start with 4G, once using 2 level pt switch to full
677 * vm size space
678 */
679 /* set vm size, must be a multiple of 4 */
680 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
25a595e4 681 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
aaa36a97
AD		 682 for (i = 1; i < 16; i++) {
683 if (i < 8)
684 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
685 adev->gart.table_addr >> 12);
686 else
687 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
688 adev->gart.table_addr >> 12);
689 }
690
691 /* enable context1-15 */
692 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
693 (u32)(adev->dummy_page.addr >> 12));
694 WREG32(mmVM_CONTEXT1_CNTL2, 4);
695 tmp = RREG32(mmVM_CONTEXT1_CNTL);
696 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
697 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
aaa36a97 698 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
aaa36a97 699 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
aaa36a97 700 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
aaa36a97 701 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
aaa36a97 702 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
aaa36a97 703 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
aaa36a97
AD		 704 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
705 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
706 amdgpu_vm_block_size - 9);
707 WREG32(mmVM_CONTEXT1_CNTL, tmp);
d9c13156
CK		 708 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
709 gmc_v8_0_set_fault_enable_default(adev, false);
710 else
711 gmc_v8_0_set_fault_enable_default(adev, true);
aaa36a97
AD		 712
713 gmc_v8_0_gart_flush_gpu_tlb(adev, 0);
714 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
715 (unsigned)(adev->mc.gtt_size >> 20),
716 (unsigned long long)adev->gart.table_addr);
717 adev->gart.ready = true;
718 return 0;
719}
720
721static int gmc_v8_0_gart_init(struct amdgpu_device *adev)
722{
723 int r;
724
725 if (adev->gart.robj) {
726 WARN(1, "R600 PCIE GART already initialized\n");
727 return 0;
728 }
729 /* Initialize common gart structure */
730 r = amdgpu_gart_init(adev);
731 if (r)
732 return r;
733 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
734 return amdgpu_gart_table_vram_alloc(adev);
735}
736
737/**
738 * gmc_v8_0_gart_disable - gart disable
739 *
740 * @adev: amdgpu_device pointer
741 *
742 * This disables all VM page table (CIK).
743 */
744static void gmc_v8_0_gart_disable(struct amdgpu_device *adev)
745{
746 u32 tmp;
747
748 /* Disable all tables */
749 WREG32(mmVM_CONTEXT0_CNTL, 0);
750 WREG32(mmVM_CONTEXT1_CNTL, 0);
751 /* Setup TLB control */
752 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
753 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
754 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
755 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
756 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
757 /* Setup L2 cache */
758 tmp = RREG32(mmVM_L2_CNTL);
759 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
760 WREG32(mmVM_L2_CNTL, tmp);
761 WREG32(mmVM_L2_CNTL2, 0);
762 amdgpu_gart_table_vram_unpin(adev);
763}
764
765/**
766 * gmc_v8_0_gart_fini - vm fini callback
767 *
768 * @adev: amdgpu_device pointer
769 *
770 * Tears down the driver GART/VM setup (CIK).
771 */
772static void gmc_v8_0_gart_fini(struct amdgpu_device *adev)
773{
774 amdgpu_gart_table_vram_free(adev);
775 amdgpu_gart_fini(adev);
776}
777
778/*
779 * vm
780 * VMID 0 is the physical GPU addresses as used by the kernel.
781 * VMIDs 1-15 are used for userspace clients and are handled
782 * by the amdgpu vm/hsa code.
783 */
784/**
785 * gmc_v8_0_vm_init - cik vm init callback
786 *
787 * @adev: amdgpu_device pointer
788 *
789 * Inits cik specific vm parameters (number of VMs, base of vram for
790 * VMIDs 1-15) (CIK).
791 * Returns 0 for success.
792 */
793static int gmc_v8_0_vm_init(struct amdgpu_device *adev)
794{
795 /*
796 * number of VMs
797 * VMID 0 is reserved for System
798 * amdgpu graphics/compute will use VMIDs 1-7
799 * amdkfd will use VMIDs 8-15
800 */
801 adev->vm_manager.nvm = AMDGPU_NUM_OF_VMIDS;
802
803 /* base offset of vram pages */
2f7d10b3 804 if (adev->flags & AMD_IS_APU) {
aaa36a97
AD		 805 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
806 tmp <<= 22;
807 adev->vm_manager.vram_base_offset = tmp;
808 } else
809 adev->vm_manager.vram_base_offset = 0;
810
811 return 0;
812}
813
814/**
815 * gmc_v8_0_vm_fini - cik vm fini callback
816 *
817 * @adev: amdgpu_device pointer
818 *
819 * Tear down any asic specific VM setup (CIK).
820 */
821static void gmc_v8_0_vm_fini(struct amdgpu_device *adev)
822{
823}
824
825/**
826 * gmc_v8_0_vm_decode_fault - print human readable fault info
827 *
828 * @adev: amdgpu_device pointer
829 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
830 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
831 *
832 * Print human readable fault information (CIK).
833 */
834static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev,
835 u32 status, u32 addr, u32 mc_client)
836{
837 u32 mc_id;
838 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
839 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
840 PROTECTIONS);
841 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
842 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
843
844 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
845 MEMORY_CLIENT_ID);
846
847 printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
848 protections, vmid, addr,
849 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
850 MEMORY_CLIENT_RW) ?
851 "write" : "read", block, mc_client, mc_id);
852}
853
81c59f54
KW		 854static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type)
855{
856 switch (mc_seq_vram_type) {
857 case MC_SEQ_MISC0__MT__GDDR1:
858 return AMDGPU_VRAM_TYPE_GDDR1;
859 case MC_SEQ_MISC0__MT__DDR2:
860 return AMDGPU_VRAM_TYPE_DDR2;
861 case MC_SEQ_MISC0__MT__GDDR3:
862 return AMDGPU_VRAM_TYPE_GDDR3;
863 case MC_SEQ_MISC0__MT__GDDR4:
864 return AMDGPU_VRAM_TYPE_GDDR4;
865 case MC_SEQ_MISC0__MT__GDDR5:
866 return AMDGPU_VRAM_TYPE_GDDR5;
867 case MC_SEQ_MISC0__MT__HBM:
868 return AMDGPU_VRAM_TYPE_HBM;
869 case MC_SEQ_MISC0__MT__DDR3:
870 return AMDGPU_VRAM_TYPE_DDR3;
871 default:
872 return AMDGPU_VRAM_TYPE_UNKNOWN;
873 }
874}
875
5fc3aeeb 876static int gmc_v8_0_early_init(void *handle)
aaa36a97 877{
5fc3aeeb 878 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
879
aaa36a97
AD		 880 gmc_v8_0_set_gart_funcs(adev);
881 gmc_v8_0_set_irq_funcs(adev);
882
2f7d10b3 883 if (adev->flags & AMD_IS_APU) {
81c59f54 884 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
aaa36a97
AD		 885 } else {
886 u32 tmp = RREG32(mmMC_SEQ_MISC0);
81c59f54
KW		 887 tmp &= MC_SEQ_MISC0__MT__MASK;
888 adev->mc.vram_type = gmc_v8_0_convert_vram_type(tmp);
aaa36a97
AD		 889 }
890
891 return 0;
892}
893
140b519f
CK		 894static int gmc_v8_0_late_init(void *handle)
895{
896 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
897
898 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
899}
900
5fc3aeeb 901static int gmc_v8_0_sw_init(void *handle)
aaa36a97
AD		 902{
903 int r;
904 int dma_bits;
5fc3aeeb 905 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 906
907 r = amdgpu_gem_init(adev);
908 if (r)
909 return r;
910
911 r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault);
912 if (r)
913 return r;
914
915 r = amdgpu_irq_add_id(adev, 147, &adev->mc.vm_fault);
916 if (r)
917 return r;
918
919 /* Adjust VM size here.
920 * Currently set to 4GB ((1 << 20) 4k pages).
921 * Max GPUVM size for cayman and SI is 40 bits.
922 */
923 adev->vm_manager.max_pfn = amdgpu_vm_size << 18;
924
925 /* Set the internal MC address mask
926 * This is the max address of the GPU's
927 * internal address space.
928 */
929 adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
930
931 /* set DMA mask + need_dma32 flags.
932 * PCIE - can handle 40-bits.
933 * IGP - can handle 40-bits
934 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
935 */
936 adev->need_dma32 = false;
937 dma_bits = adev->need_dma32 ? 32 : 40;
938 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
939 if (r) {
940 adev->need_dma32 = true;
941 dma_bits = 32;
942 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
943 }
944 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
945 if (r) {
946 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
947 printk(KERN_WARNING "amdgpu: No coherent DMA available.\n");
948 }
949
950 r = gmc_v8_0_init_microcode(adev);
951 if (r) {
952 DRM_ERROR("Failed to load mc firmware!\n");
953 return r;
954 }
955
956 r = gmc_v8_0_mc_init(adev);
957 if (r)
958 return r;
959
960 /* Memory manager */
961 r = amdgpu_bo_init(adev);
962 if (r)
963 return r;
964
965 r = gmc_v8_0_gart_init(adev);
966 if (r)
967 return r;
968
969 if (!adev->vm_manager.enabled) {
970 r = gmc_v8_0_vm_init(adev);
971 if (r) {
972 dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
973 return r;
974 }
975 adev->vm_manager.enabled = true;
976 }
977
978 return r;
979}
980
5fc3aeeb 981static int gmc_v8_0_sw_fini(void *handle)
aaa36a97 982{
5fc3aeeb 983 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 984
985 if (adev->vm_manager.enabled) {
ea89f8c9 986 amdgpu_vm_manager_fini(adev);
aaa36a97
AD		 987 gmc_v8_0_vm_fini(adev);
988 adev->vm_manager.enabled = false;
989 }
990 gmc_v8_0_gart_fini(adev);
991 amdgpu_gem_fini(adev);
992 amdgpu_bo_fini(adev);
993
994 return 0;
995}
996
5fc3aeeb 997static int gmc_v8_0_hw_init(void *handle)
aaa36a97
AD		 998{
999 int r;
5fc3aeeb 1000 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1001
1002 gmc_v8_0_init_golden_registers(adev);
1003
1004 gmc_v8_0_mc_program(adev);
1005
2f7d10b3 1006 if (!(adev->flags & AMD_IS_APU)) {
aaa36a97
AD		 1007 r = gmc_v8_0_mc_load_microcode(adev);
1008 if (r) {
1009 DRM_ERROR("Failed to load MC firmware!\n");
1010 return r;
1011 }
1012 }
1013
1014 r = gmc_v8_0_gart_enable(adev);
1015 if (r)
1016 return r;
1017
1018 return r;
1019}
1020
5fc3aeeb 1021static int gmc_v8_0_hw_fini(void *handle)
aaa36a97 1022{
5fc3aeeb 1023 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1024
140b519f 1025 amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
aaa36a97
AD		 1026 gmc_v8_0_gart_disable(adev);
1027
1028 return 0;
1029}
1030
5fc3aeeb 1031static int gmc_v8_0_suspend(void *handle)
aaa36a97 1032{
5fc3aeeb 1033 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1034
1035 if (adev->vm_manager.enabled) {
ea89f8c9 1036 amdgpu_vm_manager_fini(adev);
aaa36a97
AD		 1037 gmc_v8_0_vm_fini(adev);
1038 adev->vm_manager.enabled = false;
1039 }
1040 gmc_v8_0_hw_fini(adev);
1041
1042 return 0;
1043}
1044
5fc3aeeb 1045static int gmc_v8_0_resume(void *handle)
aaa36a97
AD		 1046{
1047 int r;
5fc3aeeb 1048 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1049
1050 r = gmc_v8_0_hw_init(adev);
1051 if (r)
1052 return r;
1053
1054 if (!adev->vm_manager.enabled) {
1055 r = gmc_v8_0_vm_init(adev);
1056 if (r) {
1057 dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
1058 return r;
1059 }
1060 adev->vm_manager.enabled = true;
1061 }
1062
1063 return r;
1064}
1065
5fc3aeeb 1066static bool gmc_v8_0_is_idle(void *handle)
aaa36a97 1067{
5fc3aeeb 1068 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1069 u32 tmp = RREG32(mmSRBM_STATUS);
1070
1071 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1072 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1073 return false;
1074
1075 return true;
1076}
1077
5fc3aeeb 1078static int gmc_v8_0_wait_for_idle(void *handle)
aaa36a97
AD		 1079{
1080 unsigned i;
1081 u32 tmp;
5fc3aeeb 1082 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1083
1084 for (i = 0; i < adev->usec_timeout; i++) {
1085 /* read MC_STATUS */
1086 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1087 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1088 SRBM_STATUS__MCC_BUSY_MASK |
1089 SRBM_STATUS__MCD_BUSY_MASK |
1090 SRBM_STATUS__VMC_BUSY_MASK |
1091 SRBM_STATUS__VMC1_BUSY_MASK);
1092 if (!tmp)
1093 return 0;
1094 udelay(1);
1095 }
1096 return -ETIMEDOUT;
1097
1098}
1099
5fc3aeeb 1100static void gmc_v8_0_print_status(void *handle)
aaa36a97
AD		 1101{
1102 int i, j;
5fc3aeeb 1103 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1104
1105 dev_info(adev->dev, "GMC 8.x registers\n");
1106 dev_info(adev->dev, " SRBM_STATUS=0x%08X\n",
1107 RREG32(mmSRBM_STATUS));
1108 dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
1109 RREG32(mmSRBM_STATUS2));
1110
1111 dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1112 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR));
1113 dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1114 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS));
1115 dev_info(adev->dev, " MC_VM_MX_L1_TLB_CNTL=0x%08X\n",
1116 RREG32(mmMC_VM_MX_L1_TLB_CNTL));
1117 dev_info(adev->dev, " VM_L2_CNTL=0x%08X\n",
1118 RREG32(mmVM_L2_CNTL));
1119 dev_info(adev->dev, " VM_L2_CNTL2=0x%08X\n",
1120 RREG32(mmVM_L2_CNTL2));
1121 dev_info(adev->dev, " VM_L2_CNTL3=0x%08X\n",
1122 RREG32(mmVM_L2_CNTL3));
1123 dev_info(adev->dev, " VM_L2_CNTL4=0x%08X\n",
1124 RREG32(mmVM_L2_CNTL4));
1125 dev_info(adev->dev, " VM_CONTEXT0_PAGE_TABLE_START_ADDR=0x%08X\n",
1126 RREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR));
1127 dev_info(adev->dev, " VM_CONTEXT0_PAGE_TABLE_END_ADDR=0x%08X\n",
1128 RREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR));
1129 dev_info(adev->dev, " VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n",
1130 RREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR));
1131 dev_info(adev->dev, " VM_CONTEXT0_CNTL2=0x%08X\n",
1132 RREG32(mmVM_CONTEXT0_CNTL2));
1133 dev_info(adev->dev, " VM_CONTEXT0_CNTL=0x%08X\n",
1134 RREG32(mmVM_CONTEXT0_CNTL));
1135 dev_info(adev->dev, " VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR=0x%08X\n",
1136 RREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR));
1137 dev_info(adev->dev, " VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR=0x%08X\n",
1138 RREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR));
1139 dev_info(adev->dev, " mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET=0x%08X\n",
1140 RREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET));
1141 dev_info(adev->dev, " VM_CONTEXT1_PAGE_TABLE_START_ADDR=0x%08X\n",
1142 RREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR));
1143 dev_info(adev->dev, " VM_CONTEXT1_PAGE_TABLE_END_ADDR=0x%08X\n",
1144 RREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR));
1145 dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n",
1146 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR));
1147 dev_info(adev->dev, " VM_CONTEXT1_CNTL2=0x%08X\n",
1148 RREG32(mmVM_CONTEXT1_CNTL2));
1149 dev_info(adev->dev, " VM_CONTEXT1_CNTL=0x%08X\n",
1150 RREG32(mmVM_CONTEXT1_CNTL));
1151 for (i = 0; i < 16; i++) {
1152 if (i < 8)
1153 dev_info(adev->dev, " VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n",
1154 i, RREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i));
1155 else
1156 dev_info(adev->dev, " VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n",
1157 i, RREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8));
1158 }
1159 dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_LOW_ADDR=0x%08X\n",
1160 RREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR));
1161 dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_HIGH_ADDR=0x%08X\n",
1162 RREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR));
1163 dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR=0x%08X\n",
1164 RREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR));
1165 dev_info(adev->dev, " MC_VM_FB_LOCATION=0x%08X\n",
1166 RREG32(mmMC_VM_FB_LOCATION));
1167 dev_info(adev->dev, " MC_VM_AGP_BASE=0x%08X\n",
1168 RREG32(mmMC_VM_AGP_BASE));
1169 dev_info(adev->dev, " MC_VM_AGP_TOP=0x%08X\n",
1170 RREG32(mmMC_VM_AGP_TOP));
1171 dev_info(adev->dev, " MC_VM_AGP_BOT=0x%08X\n",
1172 RREG32(mmMC_VM_AGP_BOT));
1173
1174 dev_info(adev->dev, " HDP_REG_COHERENCY_FLUSH_CNTL=0x%08X\n",
1175 RREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL));
1176 dev_info(adev->dev, " HDP_NONSURFACE_BASE=0x%08X\n",
1177 RREG32(mmHDP_NONSURFACE_BASE));
1178 dev_info(adev->dev, " HDP_NONSURFACE_INFO=0x%08X\n",
1179 RREG32(mmHDP_NONSURFACE_INFO));
1180 dev_info(adev->dev, " HDP_NONSURFACE_SIZE=0x%08X\n",
1181 RREG32(mmHDP_NONSURFACE_SIZE));
1182 dev_info(adev->dev, " HDP_MISC_CNTL=0x%08X\n",
1183 RREG32(mmHDP_MISC_CNTL));
1184 dev_info(adev->dev, " HDP_HOST_PATH_CNTL=0x%08X\n",
1185 RREG32(mmHDP_HOST_PATH_CNTL));
1186
1187 for (i = 0, j = 0; i < 32; i++, j += 0x6) {
1188 dev_info(adev->dev, " %d:\n", i);
1189 dev_info(adev->dev, " 0x%04X=0x%08X\n",
1190 0xb05 + j, RREG32(0xb05 + j));
1191 dev_info(adev->dev, " 0x%04X=0x%08X\n",
1192 0xb06 + j, RREG32(0xb06 + j));
1193 dev_info(adev->dev, " 0x%04X=0x%08X\n",
1194 0xb07 + j, RREG32(0xb07 + j));
1195 dev_info(adev->dev, " 0x%04X=0x%08X\n",
1196 0xb08 + j, RREG32(0xb08 + j));
1197 dev_info(adev->dev, " 0x%04X=0x%08X\n",
1198 0xb09 + j, RREG32(0xb09 + j));
1199 }
1200
1201 dev_info(adev->dev, " BIF_FB_EN=0x%08X\n",
1202 RREG32(mmBIF_FB_EN));
1203}
1204
5fc3aeeb 1205static int gmc_v8_0_soft_reset(void *handle)
aaa36a97
AD		 1206{
1207 struct amdgpu_mode_mc_save save;
1208 u32 srbm_soft_reset = 0;
5fc3aeeb 1209 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1210 u32 tmp = RREG32(mmSRBM_STATUS);
1211
1212 if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1213 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1214 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1215
1216 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1217 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
2f7d10b3 1218 if (!(adev->flags & AMD_IS_APU))
aaa36a97
AD		 1219 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1220 SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1221 }
1222
1223 if (srbm_soft_reset) {
5fc3aeeb 1224 gmc_v8_0_print_status((void *)adev);
aaa36a97
AD		 1225
1226 gmc_v8_0_mc_stop(adev, &save);
1227 if (gmc_v8_0_wait_for_idle(adev)) {
1228 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1229 }
1230
1231
1232 tmp = RREG32(mmSRBM_SOFT_RESET);
1233 tmp |= srbm_soft_reset;
1234 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1235 WREG32(mmSRBM_SOFT_RESET, tmp);
1236 tmp = RREG32(mmSRBM_SOFT_RESET);
1237
1238 udelay(50);
1239
1240 tmp &= ~srbm_soft_reset;
1241 WREG32(mmSRBM_SOFT_RESET, tmp);
1242 tmp = RREG32(mmSRBM_SOFT_RESET);
1243
1244 /* Wait a little for things to settle down */
1245 udelay(50);
1246
1247 gmc_v8_0_mc_resume(adev, &save);
1248 udelay(50);
1249
5fc3aeeb 1250 gmc_v8_0_print_status((void *)adev);
aaa36a97
AD		 1251 }
1252
1253 return 0;
1254}
1255
1256static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1257 struct amdgpu_irq_src *src,
1258 unsigned type,
1259 enum amdgpu_interrupt_state state)
1260{
1261 u32 tmp;
1262 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1263 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1264 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1265 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1266 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1267 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1268 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1269
1270 switch (state) {
1271 case AMDGPU_IRQ_STATE_DISABLE:
1272 /* system context */
1273 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1274 tmp &= ~bits;
1275 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1276 /* VMs */
1277 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1278 tmp &= ~bits;
1279 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1280 break;
1281 case AMDGPU_IRQ_STATE_ENABLE:
1282 /* system context */
1283 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1284 tmp |= bits;
1285 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1286 /* VMs */
1287 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1288 tmp |= bits;
1289 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1290 break;
1291 default:
1292 break;
1293 }
1294
1295 return 0;
1296}
1297
1298static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev,
1299 struct amdgpu_irq_src *source,
1300 struct amdgpu_iv_entry *entry)
1301{
1302 u32 addr, status, mc_client;
1303
1304 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1305 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1306 mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
ce0c6bcd
CK		 1307 /* reset addr and status */
1308 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1309
1310 if (!addr && !status)
1311 return 0;
1312
d9c13156
CK		 1313 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1314 gmc_v8_0_set_fault_enable_default(adev, false);
1315
aaa36a97
AD		 1316 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1317 entry->src_id, entry->src_data);
1318 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1319 addr);
1320 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1321 status);
1322 gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client);
aaa36a97
AD		 1323
1324 return 0;
1325}
1326
5fc3aeeb 1327static int gmc_v8_0_set_clockgating_state(void *handle,
1328 enum amd_clockgating_state state)
aaa36a97 1329{
aaa36a97
AD		 1330 return 0;
1331}
1332
5fc3aeeb 1333static int gmc_v8_0_set_powergating_state(void *handle,
1334 enum amd_powergating_state state)
aaa36a97
AD		 1335{
1336 return 0;
1337}
1338
5fc3aeeb 1339const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
aaa36a97 1340 .early_init = gmc_v8_0_early_init,
140b519f 1341 .late_init = gmc_v8_0_late_init,
aaa36a97
AD		 1342 .sw_init = gmc_v8_0_sw_init,
1343 .sw_fini = gmc_v8_0_sw_fini,
1344 .hw_init = gmc_v8_0_hw_init,
1345 .hw_fini = gmc_v8_0_hw_fini,
1346 .suspend = gmc_v8_0_suspend,
1347 .resume = gmc_v8_0_resume,
1348 .is_idle = gmc_v8_0_is_idle,
1349 .wait_for_idle = gmc_v8_0_wait_for_idle,
1350 .soft_reset = gmc_v8_0_soft_reset,
1351 .print_status = gmc_v8_0_print_status,
1352 .set_clockgating_state = gmc_v8_0_set_clockgating_state,
1353 .set_powergating_state = gmc_v8_0_set_powergating_state,
1354};
1355
1356static const struct amdgpu_gart_funcs gmc_v8_0_gart_funcs = {
1357 .flush_gpu_tlb = gmc_v8_0_gart_flush_gpu_tlb,
1358 .set_pte_pde = gmc_v8_0_gart_set_pte_pde,
1359};
1360
1361static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = {
1362 .set = gmc_v8_0_vm_fault_interrupt_state,
1363 .process = gmc_v8_0_process_interrupt,
1364};
1365
1366static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev)
1367{
1368 if (adev->gart.gart_funcs == NULL)
1369 adev->gart.gart_funcs = &gmc_v8_0_gart_funcs;
1370}
1371
1372static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev)
1373{
1374 adev->mc.vm_fault.num_types = 1;
1375 adev->mc.vm_fault.funcs = &gmc_v8_0_irq_funcs;
1376}
ubuntu-bionic-kernel mirror