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e60f8db5 AX |
1 | /* |
2 | * Copyright 2016 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | */ | |
f867723b | 23 | |
e60f8db5 | 24 | #include <linux/firmware.h> |
f867723b SR |
25 | #include <linux/pci.h> |
26 | ||
fd5fd480 | 27 | #include <drm/drm_cache.h> |
f867723b | 28 | |
e60f8db5 AX |
29 | #include "amdgpu.h" |
30 | #include "gmc_v9_0.h" | |
8d6a5230 | 31 | #include "amdgpu_atomfirmware.h" |
2cddc50e | 32 | #include "amdgpu_gem.h" |
e60f8db5 | 33 | |
75199b8c FX |
34 | #include "hdp/hdp_4_0_offset.h" |
35 | #include "hdp/hdp_4_0_sh_mask.h" | |
cde5c34f | 36 | #include "gc/gc_9_0_sh_mask.h" |
135d4b10 FX |
37 | #include "dce/dce_12_0_offset.h" |
38 | #include "dce/dce_12_0_sh_mask.h" | |
fb960bd2 | 39 | #include "vega10_enum.h" |
65417d9f | 40 | #include "mmhub/mmhub_1_0_offset.h" |
6ce68225 | 41 | #include "athub/athub_1_0_offset.h" |
250b4228 | 42 | #include "oss/osssys_4_0_offset.h" |
e60f8db5 | 43 | |
946a4d5b | 44 | #include "soc15.h" |
e60f8db5 | 45 | #include "soc15_common.h" |
90c7a935 | 46 | #include "umc/umc_6_0_sh_mask.h" |
e60f8db5 | 47 | |
e60f8db5 AX |
48 | #include "gfxhub_v1_0.h" |
49 | #include "mmhub_v1_0.h" | |
bee7b51a | 50 | #include "athub_v1_0.h" |
bf0a60b7 | 51 | #include "gfxhub_v1_1.h" |
51cce480 | 52 | #include "mmhub_v9_4.h" |
5b6b35aa | 53 | #include "umc_v6_1.h" |
e60f8db5 | 54 | |
44a99b65 AG |
55 | #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" |
56 | ||
791c4769 | 57 | #include "amdgpu_ras.h" |
58 | ||
ebdef28e AD |
59 | /* add these here since we already include dce12 headers and these are for DCN */ |
60 | #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d | |
61 | #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 | |
62 | #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 | |
63 | #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 | |
64 | #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL | |
65 | #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L | |
66 | ||
e60f8db5 AX |
67 | /* XXX Move this macro to VEGA10 header file, which is like vid.h for VI.*/ |
68 | #define AMDGPU_NUM_OF_VMIDS 8 | |
69 | ||
70 | static const u32 golden_settings_vega10_hdp[] = | |
71 | { | |
72 | 0xf64, 0x0fffffff, 0x00000000, | |
73 | 0xf65, 0x0fffffff, 0x00000000, | |
74 | 0xf66, 0x0fffffff, 0x00000000, | |
75 | 0xf67, 0x0fffffff, 0x00000000, | |
76 | 0xf68, 0x0fffffff, 0x00000000, | |
77 | 0xf6a, 0x0fffffff, 0x00000000, | |
78 | 0xf6b, 0x0fffffff, 0x00000000, | |
79 | 0xf6c, 0x0fffffff, 0x00000000, | |
80 | 0xf6d, 0x0fffffff, 0x00000000, | |
81 | 0xf6e, 0x0fffffff, 0x00000000, | |
82 | }; | |
83 | ||
946a4d5b | 84 | static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] = |
5c583018 | 85 | { |
946a4d5b SL |
86 | SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa), |
87 | SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565) | |
5c583018 EQ |
88 | }; |
89 | ||
946a4d5b | 90 | static const struct soc15_reg_golden golden_settings_athub_1_0_0[] = |
5c583018 | 91 | { |
946a4d5b SL |
92 | SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800), |
93 | SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008) | |
5c583018 EQ |
94 | }; |
95 | ||
791c4769 | 96 | static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = { |
97 | (0x000143c0 + 0x00000000), | |
98 | (0x000143c0 + 0x00000800), | |
99 | (0x000143c0 + 0x00001000), | |
100 | (0x000143c0 + 0x00001800), | |
101 | (0x000543c0 + 0x00000000), | |
102 | (0x000543c0 + 0x00000800), | |
103 | (0x000543c0 + 0x00001000), | |
104 | (0x000543c0 + 0x00001800), | |
105 | (0x000943c0 + 0x00000000), | |
106 | (0x000943c0 + 0x00000800), | |
107 | (0x000943c0 + 0x00001000), | |
108 | (0x000943c0 + 0x00001800), | |
109 | (0x000d43c0 + 0x00000000), | |
110 | (0x000d43c0 + 0x00000800), | |
111 | (0x000d43c0 + 0x00001000), | |
112 | (0x000d43c0 + 0x00001800), | |
113 | (0x001143c0 + 0x00000000), | |
114 | (0x001143c0 + 0x00000800), | |
115 | (0x001143c0 + 0x00001000), | |
116 | (0x001143c0 + 0x00001800), | |
117 | (0x001543c0 + 0x00000000), | |
118 | (0x001543c0 + 0x00000800), | |
119 | (0x001543c0 + 0x00001000), | |
120 | (0x001543c0 + 0x00001800), | |
121 | (0x001943c0 + 0x00000000), | |
122 | (0x001943c0 + 0x00000800), | |
123 | (0x001943c0 + 0x00001000), | |
124 | (0x001943c0 + 0x00001800), | |
125 | (0x001d43c0 + 0x00000000), | |
126 | (0x001d43c0 + 0x00000800), | |
127 | (0x001d43c0 + 0x00001000), | |
128 | (0x001d43c0 + 0x00001800), | |
02bab923 DP |
129 | }; |
130 | ||
791c4769 | 131 | static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = { |
132 | (0x000143e0 + 0x00000000), | |
133 | (0x000143e0 + 0x00000800), | |
134 | (0x000143e0 + 0x00001000), | |
135 | (0x000143e0 + 0x00001800), | |
136 | (0x000543e0 + 0x00000000), | |
137 | (0x000543e0 + 0x00000800), | |
138 | (0x000543e0 + 0x00001000), | |
139 | (0x000543e0 + 0x00001800), | |
140 | (0x000943e0 + 0x00000000), | |
141 | (0x000943e0 + 0x00000800), | |
142 | (0x000943e0 + 0x00001000), | |
143 | (0x000943e0 + 0x00001800), | |
144 | (0x000d43e0 + 0x00000000), | |
145 | (0x000d43e0 + 0x00000800), | |
146 | (0x000d43e0 + 0x00001000), | |
147 | (0x000d43e0 + 0x00001800), | |
148 | (0x001143e0 + 0x00000000), | |
149 | (0x001143e0 + 0x00000800), | |
150 | (0x001143e0 + 0x00001000), | |
151 | (0x001143e0 + 0x00001800), | |
152 | (0x001543e0 + 0x00000000), | |
153 | (0x001543e0 + 0x00000800), | |
154 | (0x001543e0 + 0x00001000), | |
155 | (0x001543e0 + 0x00001800), | |
156 | (0x001943e0 + 0x00000000), | |
157 | (0x001943e0 + 0x00000800), | |
158 | (0x001943e0 + 0x00001000), | |
159 | (0x001943e0 + 0x00001800), | |
160 | (0x001d43e0 + 0x00000000), | |
161 | (0x001d43e0 + 0x00000800), | |
162 | (0x001d43e0 + 0x00001000), | |
163 | (0x001d43e0 + 0x00001800), | |
02bab923 DP |
164 | }; |
165 | ||
791c4769 | 166 | static const uint32_t ecc_umc_mcumc_status_addrs[] = { |
167 | (0x000143c2 + 0x00000000), | |
168 | (0x000143c2 + 0x00000800), | |
169 | (0x000143c2 + 0x00001000), | |
170 | (0x000143c2 + 0x00001800), | |
171 | (0x000543c2 + 0x00000000), | |
172 | (0x000543c2 + 0x00000800), | |
173 | (0x000543c2 + 0x00001000), | |
174 | (0x000543c2 + 0x00001800), | |
175 | (0x000943c2 + 0x00000000), | |
176 | (0x000943c2 + 0x00000800), | |
177 | (0x000943c2 + 0x00001000), | |
178 | (0x000943c2 + 0x00001800), | |
179 | (0x000d43c2 + 0x00000000), | |
180 | (0x000d43c2 + 0x00000800), | |
181 | (0x000d43c2 + 0x00001000), | |
182 | (0x000d43c2 + 0x00001800), | |
183 | (0x001143c2 + 0x00000000), | |
184 | (0x001143c2 + 0x00000800), | |
185 | (0x001143c2 + 0x00001000), | |
186 | (0x001143c2 + 0x00001800), | |
187 | (0x001543c2 + 0x00000000), | |
188 | (0x001543c2 + 0x00000800), | |
189 | (0x001543c2 + 0x00001000), | |
190 | (0x001543c2 + 0x00001800), | |
191 | (0x001943c2 + 0x00000000), | |
192 | (0x001943c2 + 0x00000800), | |
193 | (0x001943c2 + 0x00001000), | |
194 | (0x001943c2 + 0x00001800), | |
195 | (0x001d43c2 + 0x00000000), | |
196 | (0x001d43c2 + 0x00000800), | |
197 | (0x001d43c2 + 0x00001000), | |
198 | (0x001d43c2 + 0x00001800), | |
02bab923 DP |
199 | }; |
200 | ||
791c4769 | 201 | static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev, |
202 | struct amdgpu_irq_src *src, | |
203 | unsigned type, | |
204 | enum amdgpu_interrupt_state state) | |
205 | { | |
206 | u32 bits, i, tmp, reg; | |
207 | ||
208 | bits = 0x7f; | |
209 | ||
210 | switch (state) { | |
211 | case AMDGPU_IRQ_STATE_DISABLE: | |
212 | for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { | |
213 | reg = ecc_umc_mcumc_ctrl_addrs[i]; | |
214 | tmp = RREG32(reg); | |
215 | tmp &= ~bits; | |
216 | WREG32(reg, tmp); | |
217 | } | |
218 | for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { | |
219 | reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; | |
220 | tmp = RREG32(reg); | |
221 | tmp &= ~bits; | |
222 | WREG32(reg, tmp); | |
223 | } | |
224 | break; | |
225 | case AMDGPU_IRQ_STATE_ENABLE: | |
226 | for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { | |
227 | reg = ecc_umc_mcumc_ctrl_addrs[i]; | |
228 | tmp = RREG32(reg); | |
229 | tmp |= bits; | |
230 | WREG32(reg, tmp); | |
231 | } | |
232 | for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { | |
233 | reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; | |
234 | tmp = RREG32(reg); | |
235 | tmp |= bits; | |
236 | WREG32(reg, tmp); | |
237 | } | |
238 | break; | |
239 | default: | |
240 | break; | |
241 | } | |
242 | ||
243 | return 0; | |
244 | } | |
245 | ||
246 | static int gmc_v9_0_process_ras_data_cb(struct amdgpu_device *adev, | |
81e02619 | 247 | struct ras_err_data *err_data, |
791c4769 | 248 | struct amdgpu_iv_entry *entry) |
249 | { | |
9b54d201 | 250 | kgd2kfd_set_sram_ecc_flag(adev->kfd.dev); |
045c0216 | 251 | if (adev->umc.funcs->query_ras_error_count) |
81e02619 | 252 | adev->umc.funcs->query_ras_error_count(adev, err_data); |
13b7c46c TZ |
253 | /* umc query_ras_error_address is also responsible for clearing |
254 | * error status | |
255 | */ | |
256 | if (adev->umc.funcs->query_ras_error_address) | |
257 | adev->umc.funcs->query_ras_error_address(adev, err_data); | |
91ba68f8 TZ |
258 | |
259 | /* only uncorrectable error needs gpu reset */ | |
260 | if (err_data->ue_count) | |
261 | amdgpu_ras_reset_gpu(adev, 0); | |
262 | ||
bd2280da | 263 | return AMDGPU_RAS_SUCCESS; |
791c4769 | 264 | } |
265 | ||
266 | static int gmc_v9_0_process_ecc_irq(struct amdgpu_device *adev, | |
267 | struct amdgpu_irq_src *source, | |
268 | struct amdgpu_iv_entry *entry) | |
269 | { | |
145b03eb | 270 | struct ras_common_if *ras_if = adev->gmc.umc_ras_if; |
791c4769 | 271 | struct ras_dispatch_if ih_data = { |
791c4769 | 272 | .entry = entry, |
273 | }; | |
14cfde84 | 274 | |
275 | if (!ras_if) | |
276 | return 0; | |
277 | ||
278 | ih_data.head = *ras_if; | |
279 | ||
791c4769 | 280 | amdgpu_ras_interrupt_dispatch(adev, &ih_data); |
281 | return 0; | |
282 | } | |
283 | ||
e60f8db5 AX |
284 | static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, |
285 | struct amdgpu_irq_src *src, | |
286 | unsigned type, | |
287 | enum amdgpu_interrupt_state state) | |
288 | { | |
289 | struct amdgpu_vmhub *hub; | |
ae6d1416 | 290 | u32 tmp, reg, bits, i, j; |
e60f8db5 | 291 | |
11250164 CK |
292 | bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | |
293 | VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | | |
294 | VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | | |
295 | VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | | |
296 | VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | | |
297 | VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | | |
298 | VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; | |
299 | ||
e60f8db5 AX |
300 | switch (state) { |
301 | case AMDGPU_IRQ_STATE_DISABLE: | |
1daa2bfa | 302 | for (j = 0; j < adev->num_vmhubs; j++) { |
ae6d1416 TSD |
303 | hub = &adev->vmhub[j]; |
304 | for (i = 0; i < 16; i++) { | |
305 | reg = hub->vm_context0_cntl + i; | |
306 | tmp = RREG32(reg); | |
307 | tmp &= ~bits; | |
308 | WREG32(reg, tmp); | |
309 | } | |
e60f8db5 AX |
310 | } |
311 | break; | |
312 | case AMDGPU_IRQ_STATE_ENABLE: | |
1daa2bfa | 313 | for (j = 0; j < adev->num_vmhubs; j++) { |
ae6d1416 TSD |
314 | hub = &adev->vmhub[j]; |
315 | for (i = 0; i < 16; i++) { | |
316 | reg = hub->vm_context0_cntl + i; | |
317 | tmp = RREG32(reg); | |
318 | tmp |= bits; | |
319 | WREG32(reg, tmp); | |
320 | } | |
e60f8db5 | 321 | } |
e60f8db5 AX |
322 | default: |
323 | break; | |
324 | } | |
325 | ||
326 | return 0; | |
327 | } | |
328 | ||
329 | static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, | |
330 | struct amdgpu_irq_src *source, | |
331 | struct amdgpu_iv_entry *entry) | |
332 | { | |
51c60898 | 333 | struct amdgpu_vmhub *hub; |
c468f9e2 | 334 | bool retry_fault = !!(entry->src_data[1] & 0x80); |
4d6cbde3 | 335 | uint32_t status = 0; |
e60f8db5 | 336 | u64 addr; |
51c60898 | 337 | char hub_name[10]; |
e60f8db5 AX |
338 | |
339 | addr = (u64)entry->src_data[0] << 12; | |
340 | addr |= ((u64)entry->src_data[1] & 0xf) << 44; | |
341 | ||
c1a8abd9 CK |
342 | if (retry_fault && amdgpu_gmc_filter_faults(adev, addr, entry->pasid, |
343 | entry->timestamp)) | |
22666cc1 CK |
344 | return 1; /* This also prevents sending it to KFD */ |
345 | ||
51c60898 LM |
346 | if (entry->client_id == SOC15_IH_CLIENTID_VMC) { |
347 | snprintf(hub_name, sizeof(hub_name), "mmhub0"); | |
348 | hub = &adev->vmhub[AMDGPU_MMHUB_0]; | |
349 | } else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) { | |
350 | snprintf(hub_name, sizeof(hub_name), "mmhub1"); | |
351 | hub = &adev->vmhub[AMDGPU_MMHUB_1]; | |
352 | } else { | |
353 | snprintf(hub_name, sizeof(hub_name), "gfxhub0"); | |
354 | hub = &adev->vmhub[AMDGPU_GFXHUB_0]; | |
355 | } | |
356 | ||
c1a8abd9 | 357 | /* If it's the first fault for this address, process it normally */ |
79a0c465 | 358 | if (!amdgpu_sriov_vf(adev)) { |
53499173 XY |
359 | /* |
360 | * Issue a dummy read to wait for the status register to | |
361 | * be updated to avoid reading an incorrect value due to | |
362 | * the new fast GRBM interface. | |
363 | */ | |
364 | if (entry->vmid_src == AMDGPU_GFXHUB_0) | |
365 | RREG32(hub->vm_l2_pro_fault_status); | |
366 | ||
5a9b8e8a CK |
367 | status = RREG32(hub->vm_l2_pro_fault_status); |
368 | WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); | |
4d6cbde3 | 369 | } |
e60f8db5 | 370 | |
4d6cbde3 | 371 | if (printk_ratelimit()) { |
05794eff | 372 | struct amdgpu_task_info task_info; |
efaa9646 | 373 | |
05794eff | 374 | memset(&task_info, 0, sizeof(struct amdgpu_task_info)); |
efaa9646 AG |
375 | amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); |
376 | ||
4d6cbde3 | 377 | dev_err(adev->dev, |
c468f9e2 CK |
378 | "[%s] %s page fault (src_id:%u ring:%u vmid:%u " |
379 | "pasid:%u, for process %s pid %d thread %s pid %d)\n", | |
51c60898 | 380 | hub_name, retry_fault ? "retry" : "no-retry", |
c4f46f22 | 381 | entry->src_id, entry->ring_id, entry->vmid, |
efaa9646 AG |
382 | entry->pasid, task_info.process_name, task_info.tgid, |
383 | task_info.task_name, task_info.pid); | |
5ddd4a9a | 384 | dev_err(adev->dev, " in page starting at address 0x%016llx from client %d\n", |
4d6cbde3 | 385 | addr, entry->client_id); |
5ddd4a9a | 386 | if (!amdgpu_sriov_vf(adev)) { |
4d6cbde3 FK |
387 | dev_err(adev->dev, |
388 | "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", | |
389 | status); | |
5ddd4a9a YZ |
390 | dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", |
391 | REG_GET_FIELD(status, | |
392 | VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); | |
393 | dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", | |
394 | REG_GET_FIELD(status, | |
395 | VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); | |
396 | dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", | |
397 | REG_GET_FIELD(status, | |
398 | VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); | |
399 | dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", | |
400 | REG_GET_FIELD(status, | |
401 | VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); | |
4e0ae5e2 YZ |
402 | dev_err(adev->dev, "\t RW: 0x%lx\n", |
403 | REG_GET_FIELD(status, | |
404 | VM_L2_PROTECTION_FAULT_STATUS, RW)); | |
5ddd4a9a YZ |
405 | |
406 | } | |
79a0c465 | 407 | } |
e60f8db5 AX |
408 | |
409 | return 0; | |
410 | } | |
411 | ||
412 | static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = { | |
413 | .set = gmc_v9_0_vm_fault_interrupt_state, | |
414 | .process = gmc_v9_0_process_interrupt, | |
415 | }; | |
416 | ||
791c4769 | 417 | |
418 | static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = { | |
419 | .set = gmc_v9_0_ecc_interrupt_state, | |
420 | .process = gmc_v9_0_process_ecc_irq, | |
421 | }; | |
422 | ||
e60f8db5 AX |
423 | static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev) |
424 | { | |
770d13b1 CK |
425 | adev->gmc.vm_fault.num_types = 1; |
426 | adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs; | |
791c4769 | 427 | |
428 | adev->gmc.ecc_irq.num_types = 1; | |
429 | adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs; | |
e60f8db5 AX |
430 | } |
431 | ||
2a79d868 YZ |
432 | static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid, |
433 | uint32_t flush_type) | |
03f89feb CK |
434 | { |
435 | u32 req = 0; | |
436 | ||
03f89feb | 437 | req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, |
c4f46f22 | 438 | PER_VMID_INVALIDATE_REQ, 1 << vmid); |
2a79d868 | 439 | req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); |
03f89feb CK |
440 | req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); |
441 | req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); | |
442 | req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); | |
443 | req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); | |
444 | req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); | |
445 | req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, | |
446 | CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); | |
447 | ||
448 | return req; | |
449 | } | |
450 | ||
e60f8db5 AX |
451 | /* |
452 | * GART | |
453 | * VMID 0 is the physical GPU addresses as used by the kernel. | |
454 | * VMIDs 1-15 are used for userspace clients and are handled | |
455 | * by the amdgpu vm/hsa code. | |
456 | */ | |
457 | ||
458 | /** | |
2a79d868 | 459 | * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type |
e60f8db5 AX |
460 | * |
461 | * @adev: amdgpu_device pointer | |
462 | * @vmid: vm instance to flush | |
2a79d868 | 463 | * @flush_type: the flush type |
e60f8db5 | 464 | * |
2a79d868 | 465 | * Flush the TLB for the requested page table using certain type. |
e60f8db5 | 466 | */ |
3ff98548 OZ |
467 | static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, |
468 | uint32_t vmhub, uint32_t flush_type) | |
e60f8db5 | 469 | { |
e60f8db5 | 470 | const unsigned eng = 17; |
3ff98548 OZ |
471 | u32 j, tmp; |
472 | struct amdgpu_vmhub *hub; | |
e60f8db5 | 473 | |
3ff98548 | 474 | BUG_ON(vmhub >= adev->num_vmhubs); |
e60f8db5 | 475 | |
3ff98548 OZ |
476 | hub = &adev->vmhub[vmhub]; |
477 | tmp = gmc_v9_0_get_invalidate_req(vmid, flush_type); | |
3890d111 | 478 | |
3ff98548 OZ |
479 | /* This is necessary for a HW workaround under SRIOV as well |
480 | * as GFXOFF under bare metal | |
481 | */ | |
482 | if (adev->gfx.kiq.ring.sched.ready && | |
483 | (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) && | |
484 | !adev->in_gpu_reset) { | |
485 | uint32_t req = hub->vm_inv_eng0_req + eng; | |
486 | uint32_t ack = hub->vm_inv_eng0_ack + eng; | |
487 | ||
488 | amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, tmp, | |
489 | 1 << vmid); | |
490 | return; | |
491 | } | |
396557b0 | 492 | |
3ff98548 OZ |
493 | spin_lock(&adev->gmc.invalidate_lock); |
494 | WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp); | |
53499173 XY |
495 | |
496 | /* | |
497 | * Issue a dummy read to wait for the ACK register to be cleared | |
498 | * to avoid a false ACK due to the new fast GRBM interface. | |
499 | */ | |
500 | if (vmhub == AMDGPU_GFXHUB_0) | |
501 | RREG32_NO_KIQ(hub->vm_inv_eng0_req + eng); | |
502 | ||
3ff98548 OZ |
503 | for (j = 0; j < adev->usec_timeout; j++) { |
504 | tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng); | |
505 | if (tmp & (1 << vmid)) | |
506 | break; | |
507 | udelay(1); | |
e60f8db5 | 508 | } |
3ff98548 OZ |
509 | spin_unlock(&adev->gmc.invalidate_lock); |
510 | if (j < adev->usec_timeout) | |
511 | return; | |
512 | ||
513 | DRM_ERROR("Timeout waiting for VM flush ACK!\n"); | |
e60f8db5 AX |
514 | } |
515 | ||
9096d6e5 | 516 | static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, |
c633c00b | 517 | unsigned vmid, uint64_t pd_addr) |
9096d6e5 | 518 | { |
250b4228 CK |
519 | struct amdgpu_device *adev = ring->adev; |
520 | struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub]; | |
2a79d868 | 521 | uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0); |
9096d6e5 CK |
522 | unsigned eng = ring->vm_inv_eng; |
523 | ||
9096d6e5 CK |
524 | amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid), |
525 | lower_32_bits(pd_addr)); | |
526 | ||
527 | amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid), | |
528 | upper_32_bits(pd_addr)); | |
529 | ||
f8bc9037 AD |
530 | amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + eng, |
531 | hub->vm_inv_eng0_ack + eng, | |
532 | req, 1 << vmid); | |
f732b6b3 | 533 | |
9096d6e5 CK |
534 | return pd_addr; |
535 | } | |
536 | ||
c633c00b CK |
537 | static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, |
538 | unsigned pasid) | |
539 | { | |
540 | struct amdgpu_device *adev = ring->adev; | |
541 | uint32_t reg; | |
542 | ||
f2d66571 LM |
543 | /* Do nothing because there's no lut register for mmhub1. */ |
544 | if (ring->funcs->vmhub == AMDGPU_MMHUB_1) | |
545 | return; | |
546 | ||
a2d15ed7 | 547 | if (ring->funcs->vmhub == AMDGPU_GFXHUB_0) |
c633c00b CK |
548 | reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; |
549 | else | |
550 | reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; | |
551 | ||
552 | amdgpu_ring_emit_wreg(ring, reg, pasid); | |
553 | } | |
554 | ||
6490bd76 YZ |
555 | /* |
556 | * PTE format on VEGA 10: | |
557 | * 63:59 reserved | |
558 | * 58:57 mtype | |
559 | * 56 F | |
560 | * 55 L | |
561 | * 54 P | |
562 | * 53 SW | |
563 | * 52 T | |
564 | * 50:48 reserved | |
565 | * 47:12 4k physical page base address | |
566 | * 11:7 fragment | |
567 | * 6 write | |
568 | * 5 read | |
569 | * 4 exe | |
570 | * 3 Z | |
571 | * 2 snooped | |
572 | * 1 system | |
573 | * 0 valid | |
e60f8db5 | 574 | * |
6490bd76 YZ |
575 | * PDE format on VEGA 10: |
576 | * 63:59 block fragment size | |
577 | * 58:55 reserved | |
578 | * 54 P | |
579 | * 53:48 reserved | |
580 | * 47:6 physical base address of PD or PTE | |
581 | * 5:3 reserved | |
582 | * 2 C | |
583 | * 1 system | |
584 | * 0 valid | |
e60f8db5 | 585 | */ |
e60f8db5 AX |
586 | |
587 | static uint64_t gmc_v9_0_get_vm_pte_flags(struct amdgpu_device *adev, | |
588 | uint32_t flags) | |
589 | ||
590 | { | |
591 | uint64_t pte_flag = 0; | |
592 | ||
593 | if (flags & AMDGPU_VM_PAGE_EXECUTABLE) | |
594 | pte_flag |= AMDGPU_PTE_EXECUTABLE; | |
595 | if (flags & AMDGPU_VM_PAGE_READABLE) | |
596 | pte_flag |= AMDGPU_PTE_READABLE; | |
597 | if (flags & AMDGPU_VM_PAGE_WRITEABLE) | |
598 | pte_flag |= AMDGPU_PTE_WRITEABLE; | |
599 | ||
600 | switch (flags & AMDGPU_VM_MTYPE_MASK) { | |
601 | case AMDGPU_VM_MTYPE_DEFAULT: | |
7596ab68 | 602 | pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); |
e60f8db5 AX |
603 | break; |
604 | case AMDGPU_VM_MTYPE_NC: | |
7596ab68 | 605 | pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); |
e60f8db5 AX |
606 | break; |
607 | case AMDGPU_VM_MTYPE_WC: | |
7596ab68 | 608 | pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_WC); |
e60f8db5 AX |
609 | break; |
610 | case AMDGPU_VM_MTYPE_CC: | |
7596ab68 | 611 | pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_CC); |
e60f8db5 AX |
612 | break; |
613 | case AMDGPU_VM_MTYPE_UC: | |
7596ab68 | 614 | pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_UC); |
e60f8db5 AX |
615 | break; |
616 | default: | |
7596ab68 | 617 | pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); |
e60f8db5 AX |
618 | break; |
619 | } | |
620 | ||
621 | if (flags & AMDGPU_VM_PAGE_PRT) | |
622 | pte_flag |= AMDGPU_PTE_PRT; | |
623 | ||
624 | return pte_flag; | |
625 | } | |
626 | ||
3de676d8 CK |
627 | static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level, |
628 | uint64_t *addr, uint64_t *flags) | |
e60f8db5 | 629 | { |
bbc9fb10 | 630 | if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) |
3de676d8 | 631 | *addr = adev->vm_manager.vram_base_offset + *addr - |
770d13b1 | 632 | adev->gmc.vram_start; |
3de676d8 | 633 | BUG_ON(*addr & 0xFFFF00000000003FULL); |
6a42fd6f | 634 | |
770d13b1 | 635 | if (!adev->gmc.translate_further) |
6a42fd6f CK |
636 | return; |
637 | ||
638 | if (level == AMDGPU_VM_PDB1) { | |
639 | /* Set the block fragment size */ | |
640 | if (!(*flags & AMDGPU_PDE_PTE)) | |
641 | *flags |= AMDGPU_PDE_BFS(0x9); | |
642 | ||
643 | } else if (level == AMDGPU_VM_PDB0) { | |
644 | if (*flags & AMDGPU_PDE_PTE) | |
645 | *flags &= ~AMDGPU_PDE_PTE; | |
646 | else | |
647 | *flags |= AMDGPU_PTE_TF; | |
648 | } | |
e60f8db5 AX |
649 | } |
650 | ||
132f34e4 CK |
651 | static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = { |
652 | .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb, | |
9096d6e5 | 653 | .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb, |
c633c00b | 654 | .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping, |
b1166325 CK |
655 | .get_vm_pte_flags = gmc_v9_0_get_vm_pte_flags, |
656 | .get_vm_pde = gmc_v9_0_get_vm_pde | |
e60f8db5 AX |
657 | }; |
658 | ||
132f34e4 | 659 | static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev) |
e60f8db5 | 660 | { |
f54b30d7 | 661 | adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs; |
e60f8db5 AX |
662 | } |
663 | ||
5b6b35aa HZ |
664 | static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev) |
665 | { | |
666 | switch (adev->asic_type) { | |
667 | case CHIP_VEGA20: | |
3aacf4ea TZ |
668 | adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; |
669 | adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; | |
670 | adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; | |
671 | adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET; | |
672 | adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; | |
045c0216 | 673 | adev->umc.funcs = &umc_v6_1_funcs; |
5b6b35aa HZ |
674 | break; |
675 | default: | |
676 | break; | |
677 | } | |
678 | } | |
679 | ||
3d093da0 TZ |
680 | static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev) |
681 | { | |
682 | switch (adev->asic_type) { | |
683 | case CHIP_VEGA20: | |
684 | adev->mmhub_funcs = &mmhub_v1_0_funcs; | |
685 | break; | |
686 | default: | |
687 | break; | |
688 | } | |
689 | } | |
690 | ||
e60f8db5 AX |
691 | static int gmc_v9_0_early_init(void *handle) |
692 | { | |
693 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
694 | ||
132f34e4 | 695 | gmc_v9_0_set_gmc_funcs(adev); |
e60f8db5 | 696 | gmc_v9_0_set_irq_funcs(adev); |
5b6b35aa | 697 | gmc_v9_0_set_umc_funcs(adev); |
3d093da0 | 698 | gmc_v9_0_set_mmhub_funcs(adev); |
e60f8db5 | 699 | |
770d13b1 CK |
700 | adev->gmc.shared_aperture_start = 0x2000000000000000ULL; |
701 | adev->gmc.shared_aperture_end = | |
702 | adev->gmc.shared_aperture_start + (4ULL << 30) - 1; | |
bfa8eea2 | 703 | adev->gmc.private_aperture_start = 0x1000000000000000ULL; |
770d13b1 CK |
704 | adev->gmc.private_aperture_end = |
705 | adev->gmc.private_aperture_start + (4ULL << 30) - 1; | |
a7ea6548 | 706 | |
e60f8db5 AX |
707 | return 0; |
708 | } | |
709 | ||
cd2b5623 AD |
710 | static bool gmc_v9_0_keep_stolen_memory(struct amdgpu_device *adev) |
711 | { | |
712 | ||
713 | /* | |
714 | * TODO: | |
715 | * Currently there is a bug where some memory client outside | |
716 | * of the driver writes to first 8M of VRAM on S3 resume, | |
717 | * this overrides GART which by default gets placed in first 8M and | |
718 | * causes VM_FAULTS once GTT is accessed. | |
719 | * Keep the stolen memory reservation until the while this is not solved. | |
720 | * Also check code in gmc_v9_0_get_vbios_fb_size and gmc_v9_0_late_init | |
721 | */ | |
722 | switch (adev->asic_type) { | |
6abc0c8f | 723 | case CHIP_VEGA10: |
cd2b5623 | 724 | case CHIP_RAVEN: |
bfa3a9bb | 725 | case CHIP_ARCTURUS: |
8787ee01 | 726 | case CHIP_RENOIR: |
02122753 | 727 | return true; |
cd2b5623 AD |
728 | case CHIP_VEGA12: |
729 | case CHIP_VEGA20: | |
730 | default: | |
6abc0c8f | 731 | return false; |
cd2b5623 AD |
732 | } |
733 | } | |
734 | ||
c713a461 | 735 | static int gmc_v9_0_allocate_vm_inv_eng(struct amdgpu_device *adev) |
e60f8db5 | 736 | { |
c713a461 EQ |
737 | struct amdgpu_ring *ring; |
738 | unsigned vm_inv_engs[AMDGPU_MAX_VMHUBS] = | |
c8a6e2a3 LM |
739 | {GFXHUB_FREE_VM_INV_ENGS_BITMAP, MMHUB_FREE_VM_INV_ENGS_BITMAP, |
740 | GFXHUB_FREE_VM_INV_ENGS_BITMAP}; | |
4789c463 | 741 | unsigned i; |
c713a461 | 742 | unsigned vmhub, inv_eng; |
4789c463 | 743 | |
c713a461 EQ |
744 | for (i = 0; i < adev->num_rings; ++i) { |
745 | ring = adev->rings[i]; | |
746 | vmhub = ring->funcs->vmhub; | |
6f752ec2 | 747 | |
c713a461 EQ |
748 | inv_eng = ffs(vm_inv_engs[vmhub]); |
749 | if (!inv_eng) { | |
750 | dev_err(adev->dev, "no VM inv eng for ring %s\n", | |
751 | ring->name); | |
752 | return -EINVAL; | |
753 | } | |
754 | ||
755 | ring->vm_inv_eng = inv_eng - 1; | |
72464382 | 756 | vm_inv_engs[vmhub] &= ~(1 << ring->vm_inv_eng); |
4789c463 | 757 | |
6e82c6e0 CK |
758 | dev_info(adev->dev, "ring %s uses VM inv eng %u on hub %u\n", |
759 | ring->name, ring->vm_inv_eng, ring->funcs->vmhub); | |
4789c463 CK |
760 | } |
761 | ||
c713a461 EQ |
762 | return 0; |
763 | } | |
764 | ||
145b03eb TZ |
765 | static int gmc_v9_0_ecc_late_init(void *handle) |
766 | { | |
767 | int r; | |
2452e778 HZ |
768 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
769 | struct ras_ih_if mmhub_ih_info; | |
145b03eb TZ |
770 | struct ras_fs_if umc_fs_info = { |
771 | .sysfs_name = "umc_err_count", | |
772 | .debugfs_name = "umc_err_inject", | |
773 | }; | |
2452e778 HZ |
774 | struct ras_ih_if umc_ih_info = { |
775 | .cb = gmc_v9_0_process_ras_data_cb, | |
145b03eb TZ |
776 | }; |
777 | struct ras_fs_if mmhub_fs_info = { | |
778 | .sysfs_name = "mmhub_err_count", | |
779 | .debugfs_name = "mmhub_err_inject", | |
780 | }; | |
145b03eb | 781 | |
2452e778 HZ |
782 | if (!adev->gmc.umc_ras_if) { |
783 | adev->gmc.umc_ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL); | |
784 | if (!adev->gmc.umc_ras_if) | |
785 | return -ENOMEM; | |
786 | adev->gmc.umc_ras_if->block = AMDGPU_RAS_BLOCK__UMC; | |
787 | adev->gmc.umc_ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; | |
788 | adev->gmc.umc_ras_if->sub_block_index = 0; | |
789 | strcpy(adev->gmc.umc_ras_if->name, "umc"); | |
790 | } | |
791 | umc_ih_info.head = umc_fs_info.head = *adev->gmc.umc_ras_if; | |
792 | ||
793 | r = amdgpu_ras_late_init(adev, adev->gmc.umc_ras_if, | |
794 | &umc_fs_info, &umc_ih_info); | |
145b03eb | 795 | if (r) |
2452e778 HZ |
796 | goto free; |
797 | ||
798 | if (amdgpu_ras_is_supported(adev, adev->gmc.umc_ras_if->block)) { | |
799 | r = amdgpu_irq_get(adev, &adev->gmc.ecc_irq, 0); | |
800 | if (r) | |
801 | goto umc_late_fini; | |
802 | } | |
803 | ||
804 | if (!adev->gmc.mmhub_ras_if) { | |
805 | adev->gmc.mmhub_ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL); | |
806 | if (!adev->gmc.mmhub_ras_if) | |
807 | return -ENOMEM; | |
808 | adev->gmc.mmhub_ras_if->block = AMDGPU_RAS_BLOCK__MMHUB; | |
809 | adev->gmc.mmhub_ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; | |
810 | adev->gmc.mmhub_ras_if->sub_block_index = 0; | |
811 | strcpy(adev->gmc.mmhub_ras_if->name, "mmhub"); | |
812 | } | |
813 | mmhub_ih_info.head = mmhub_fs_info.head = *adev->gmc.mmhub_ras_if; | |
814 | r = amdgpu_ras_late_init(adev, adev->gmc.mmhub_ras_if, | |
815 | &mmhub_fs_info, &mmhub_ih_info); | |
816 | if (r) | |
817 | goto mmhub_late_fini; | |
145b03eb | 818 | |
2452e778 HZ |
819 | return 0; |
820 | mmhub_late_fini: | |
821 | amdgpu_ras_late_fini(adev, adev->gmc.mmhub_ras_if, &mmhub_ih_info); | |
822 | umc_late_fini: | |
823 | amdgpu_ras_late_fini(adev, adev->gmc.umc_ras_if, &umc_ih_info); | |
824 | free: | |
825 | kfree(adev->gmc.umc_ras_if); | |
826 | kfree(adev->gmc.mmhub_ras_if); | |
145b03eb TZ |
827 | return r; |
828 | } | |
791c4769 | 829 | |
c713a461 EQ |
830 | static int gmc_v9_0_late_init(void *handle) |
831 | { | |
832 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
f49ea9f8 | 833 | bool r; |
c713a461 EQ |
834 | |
835 | if (!gmc_v9_0_keep_stolen_memory(adev)) | |
836 | amdgpu_bo_late_init(adev); | |
837 | ||
838 | r = gmc_v9_0_allocate_vm_inv_eng(adev); | |
839 | if (r) | |
840 | return r; | |
f49ea9f8 HZ |
841 | /* Check if ecc is available */ |
842 | if (!amdgpu_sriov_vf(adev)) { | |
843 | switch (adev->asic_type) { | |
844 | case CHIP_VEGA10: | |
845 | case CHIP_VEGA20: | |
846 | r = amdgpu_atomfirmware_mem_ecc_supported(adev); | |
847 | if (!r) { | |
848 | DRM_INFO("ECC is not present.\n"); | |
849 | if (adev->df_funcs->enable_ecc_force_par_wr_rmw) | |
850 | adev->df_funcs->enable_ecc_force_par_wr_rmw(adev, false); | |
851 | } else { | |
852 | DRM_INFO("ECC is active.\n"); | |
853 | } | |
4789c463 | 854 | |
f49ea9f8 HZ |
855 | r = amdgpu_atomfirmware_sram_ecc_supported(adev); |
856 | if (!r) { | |
857 | DRM_INFO("SRAM ECC is not present.\n"); | |
858 | } else { | |
859 | DRM_INFO("SRAM ECC is active.\n"); | |
860 | } | |
861 | break; | |
862 | default: | |
863 | break; | |
5ba4fa35 | 864 | } |
02bab923 DP |
865 | } |
866 | ||
791c4769 | 867 | r = gmc_v9_0_ecc_late_init(handle); |
868 | if (r) | |
869 | return r; | |
870 | ||
770d13b1 | 871 | return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); |
e60f8db5 AX |
872 | } |
873 | ||
874 | static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, | |
770d13b1 | 875 | struct amdgpu_gmc *mc) |
e60f8db5 | 876 | { |
eeb2487d | 877 | u64 base = 0; |
9d4f837a FM |
878 | |
879 | if (adev->asic_type == CHIP_ARCTURUS) | |
880 | base = mmhub_v9_4_get_fb_location(adev); | |
881 | else if (!amdgpu_sriov_vf(adev)) | |
882 | base = mmhub_v1_0_get_fb_location(adev); | |
883 | ||
6fdd68b1 AD |
884 | /* add the xgmi offset of the physical node */ |
885 | base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; | |
83afe835 | 886 | amdgpu_gmc_vram_location(adev, mc, base); |
961c75cf | 887 | amdgpu_gmc_gart_location(adev, mc); |
81c274c4 | 888 | amdgpu_gmc_agp_location(adev, mc); |
bc099ee9 | 889 | /* base offset of vram pages */ |
b6110c00 | 890 | adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev); |
6fdd68b1 AD |
891 | |
892 | /* XXX: add the xgmi offset of the physical node? */ | |
893 | adev->vm_manager.vram_base_offset += | |
894 | adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; | |
e60f8db5 AX |
895 | } |
896 | ||
897 | /** | |
898 | * gmc_v9_0_mc_init - initialize the memory controller driver params | |
899 | * | |
900 | * @adev: amdgpu_device pointer | |
901 | * | |
902 | * Look up the amount of vram, vram width, and decide how to place | |
903 | * vram and gart within the GPU's physical address space. | |
904 | * Returns 0 for success. | |
905 | */ | |
906 | static int gmc_v9_0_mc_init(struct amdgpu_device *adev) | |
907 | { | |
e60f8db5 | 908 | int chansize, numchan; |
d6895ad3 | 909 | int r; |
e60f8db5 | 910 | |
067e75b3 AD |
911 | if (amdgpu_sriov_vf(adev)) { |
912 | /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN, | |
913 | * and DF related registers is not readable, seems hardcord is the | |
914 | * only way to set the correct vram_width | |
915 | */ | |
916 | adev->gmc.vram_width = 2048; | |
917 | } else if (amdgpu_emu_mode != 1) { | |
3d918c0e | 918 | adev->gmc.vram_width = amdgpu_atomfirmware_get_vram_width(adev); |
067e75b3 AD |
919 | } |
920 | ||
770d13b1 | 921 | if (!adev->gmc.vram_width) { |
8d6a5230 | 922 | /* hbm memory channel size */ |
585b7f16 TSD |
923 | if (adev->flags & AMD_IS_APU) |
924 | chansize = 64; | |
925 | else | |
926 | chansize = 128; | |
8d6a5230 | 927 | |
070706c0 | 928 | numchan = adev->df_funcs->get_hbm_channel_number(adev); |
770d13b1 | 929 | adev->gmc.vram_width = numchan * chansize; |
e60f8db5 | 930 | } |
e60f8db5 | 931 | |
e60f8db5 | 932 | /* size in MB on si */ |
770d13b1 | 933 | adev->gmc.mc_vram_size = |
bebc0762 | 934 | adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; |
770d13b1 | 935 | adev->gmc.real_vram_size = adev->gmc.mc_vram_size; |
d6895ad3 CK |
936 | |
937 | if (!(adev->flags & AMD_IS_APU)) { | |
938 | r = amdgpu_device_resize_fb_bar(adev); | |
939 | if (r) | |
940 | return r; | |
941 | } | |
770d13b1 CK |
942 | adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); |
943 | adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); | |
e60f8db5 | 944 | |
156a81be CZ |
945 | #ifdef CONFIG_X86_64 |
946 | if (adev->flags & AMD_IS_APU) { | |
947 | adev->gmc.aper_base = gfxhub_v1_0_get_mc_fb_offset(adev); | |
948 | adev->gmc.aper_size = adev->gmc.real_vram_size; | |
949 | } | |
950 | #endif | |
e60f8db5 | 951 | /* In case the PCI BAR is larger than the actual amount of vram */ |
770d13b1 CK |
952 | adev->gmc.visible_vram_size = adev->gmc.aper_size; |
953 | if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) | |
954 | adev->gmc.visible_vram_size = adev->gmc.real_vram_size; | |
e60f8db5 | 955 | |
c3db7b5a AD |
956 | /* set the gart size */ |
957 | if (amdgpu_gart_size == -1) { | |
958 | switch (adev->asic_type) { | |
959 | case CHIP_VEGA10: /* all engines support GPUVM */ | |
273a14cd | 960 | case CHIP_VEGA12: /* all engines support GPUVM */ |
d96b428c | 961 | case CHIP_VEGA20: |
3de2ff5d | 962 | case CHIP_ARCTURUS: |
c3db7b5a | 963 | default: |
fe19b862 | 964 | adev->gmc.gart_size = 512ULL << 20; |
c3db7b5a AD |
965 | break; |
966 | case CHIP_RAVEN: /* DCE SG support */ | |
8787ee01 | 967 | case CHIP_RENOIR: |
770d13b1 | 968 | adev->gmc.gart_size = 1024ULL << 20; |
c3db7b5a AD |
969 | break; |
970 | } | |
971 | } else { | |
770d13b1 | 972 | adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; |
c3db7b5a AD |
973 | } |
974 | ||
770d13b1 | 975 | gmc_v9_0_vram_gtt_location(adev, &adev->gmc); |
e60f8db5 AX |
976 | |
977 | return 0; | |
978 | } | |
979 | ||
980 | static int gmc_v9_0_gart_init(struct amdgpu_device *adev) | |
981 | { | |
982 | int r; | |
983 | ||
1123b989 | 984 | if (adev->gart.bo) { |
e60f8db5 AX |
985 | WARN(1, "VEGA10 PCIE GART already initialized\n"); |
986 | return 0; | |
987 | } | |
988 | /* Initialize common gart structure */ | |
989 | r = amdgpu_gart_init(adev); | |
990 | if (r) | |
991 | return r; | |
992 | adev->gart.table_size = adev->gart.num_gpu_pages * 8; | |
7596ab68 | 993 | adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(MTYPE_UC) | |
e60f8db5 AX |
994 | AMDGPU_PTE_EXECUTABLE; |
995 | return amdgpu_gart_table_vram_alloc(adev); | |
996 | } | |
997 | ||
ebdef28e AD |
998 | static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev) |
999 | { | |
bfa3a9bb | 1000 | u32 d1vga_control; |
ebdef28e AD |
1001 | unsigned size; |
1002 | ||
6f752ec2 AG |
1003 | /* |
1004 | * TODO Remove once GART corruption is resolved | |
1005 | * Check related code in gmc_v9_0_sw_fini | |
1006 | * */ | |
cd2b5623 AD |
1007 | if (gmc_v9_0_keep_stolen_memory(adev)) |
1008 | return 9 * 1024 * 1024; | |
6f752ec2 | 1009 | |
bfa3a9bb | 1010 | d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); |
ebdef28e AD |
1011 | if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { |
1012 | size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */ | |
1013 | } else { | |
1014 | u32 viewport; | |
1015 | ||
1016 | switch (adev->asic_type) { | |
1017 | case CHIP_RAVEN: | |
8787ee01 | 1018 | case CHIP_RENOIR: |
ebdef28e AD |
1019 | viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); |
1020 | size = (REG_GET_FIELD(viewport, | |
1021 | HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * | |
1022 | REG_GET_FIELD(viewport, | |
1023 | HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * | |
1024 | 4); | |
1025 | break; | |
1026 | case CHIP_VEGA10: | |
1027 | case CHIP_VEGA12: | |
cd2b5623 | 1028 | case CHIP_VEGA20: |
ebdef28e AD |
1029 | default: |
1030 | viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE); | |
1031 | size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) * | |
1032 | REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) * | |
1033 | 4); | |
1034 | break; | |
1035 | } | |
1036 | } | |
1037 | /* return 0 if the pre-OS buffer uses up most of vram */ | |
1038 | if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) | |
1039 | return 0; | |
6f752ec2 | 1040 | |
ebdef28e AD |
1041 | return size; |
1042 | } | |
1043 | ||
e60f8db5 AX |
1044 | static int gmc_v9_0_sw_init(void *handle) |
1045 | { | |
1046 | int r; | |
e60f8db5 AX |
1047 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1048 | ||
0c8c0847 | 1049 | gfxhub_v1_0_init(adev); |
51cce480 LM |
1050 | if (adev->asic_type == CHIP_ARCTURUS) |
1051 | mmhub_v9_4_init(adev); | |
1052 | else | |
1053 | mmhub_v1_0_init(adev); | |
0c8c0847 | 1054 | |
770d13b1 | 1055 | spin_lock_init(&adev->gmc.invalidate_lock); |
e60f8db5 | 1056 | |
1e09b053 | 1057 | adev->gmc.vram_type = amdgpu_atomfirmware_get_vram_type(adev); |
fd66560b HZ |
1058 | switch (adev->asic_type) { |
1059 | case CHIP_RAVEN: | |
1daa2bfa LM |
1060 | adev->num_vmhubs = 2; |
1061 | ||
6a42fd6f | 1062 | if (adev->rev_id == 0x0 || adev->rev_id == 0x1) { |
f3368128 | 1063 | amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); |
6a42fd6f CK |
1064 | } else { |
1065 | /* vm_size is 128TB + 512GB for legacy 3-level page support */ | |
1066 | amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48); | |
770d13b1 | 1067 | adev->gmc.translate_further = |
6a42fd6f CK |
1068 | adev->vm_manager.num_level > 1; |
1069 | } | |
fd66560b HZ |
1070 | break; |
1071 | case CHIP_VEGA10: | |
273a14cd | 1072 | case CHIP_VEGA12: |
d96b428c | 1073 | case CHIP_VEGA20: |
8787ee01 | 1074 | case CHIP_RENOIR: |
1daa2bfa LM |
1075 | adev->num_vmhubs = 2; |
1076 | ||
8787ee01 | 1077 | |
36b32a68 ZJ |
1078 | /* |
1079 | * To fulfill 4-level page support, | |
1080 | * vm size is 256TB (48bit), maximum size of Vega10, | |
1081 | * block size 512 (9bit) | |
1082 | */ | |
cdba61da | 1083 | /* sriov restrict max_pfn below AMDGPU_GMC_HOLE */ |
1084 | if (amdgpu_sriov_vf(adev)) | |
1085 | amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 47); | |
1086 | else | |
1087 | amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); | |
fd66560b | 1088 | break; |
3de2ff5d | 1089 | case CHIP_ARCTURUS: |
c8a6e2a3 LM |
1090 | adev->num_vmhubs = 3; |
1091 | ||
3de2ff5d LM |
1092 | /* Keep the vm size same with Vega20 */ |
1093 | amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); | |
1094 | break; | |
fd66560b HZ |
1095 | default: |
1096 | break; | |
e60f8db5 AX |
1097 | } |
1098 | ||
1099 | /* This interrupt is VMC page fault.*/ | |
44a99b65 | 1100 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT, |
770d13b1 | 1101 | &adev->gmc.vm_fault); |
30da7bb1 CK |
1102 | if (r) |
1103 | return r; | |
1104 | ||
7d19b15f LM |
1105 | if (adev->asic_type == CHIP_ARCTURUS) { |
1106 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT, | |
1107 | &adev->gmc.vm_fault); | |
1108 | if (r) | |
1109 | return r; | |
1110 | } | |
1111 | ||
44a99b65 | 1112 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT, |
770d13b1 | 1113 | &adev->gmc.vm_fault); |
e60f8db5 AX |
1114 | |
1115 | if (r) | |
1116 | return r; | |
1117 | ||
791c4769 | 1118 | /* interrupt sent to DF. */ |
1119 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0, | |
1120 | &adev->gmc.ecc_irq); | |
1121 | if (r) | |
1122 | return r; | |
1123 | ||
e60f8db5 AX |
1124 | /* Set the internal MC address mask |
1125 | * This is the max address of the GPU's | |
1126 | * internal address space. | |
1127 | */ | |
770d13b1 | 1128 | adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ |
e60f8db5 | 1129 | |
244511f3 | 1130 | r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); |
e60f8db5 | 1131 | if (r) { |
e60f8db5 | 1132 | printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); |
244511f3 | 1133 | return r; |
e60f8db5 | 1134 | } |
244511f3 | 1135 | adev->need_swiotlb = drm_need_swiotlb(44); |
e60f8db5 | 1136 | |
47622ba0 | 1137 | if (adev->gmc.xgmi.supported) { |
bf0a60b7 AD |
1138 | r = gfxhub_v1_1_get_xgmi_info(adev); |
1139 | if (r) | |
1140 | return r; | |
1141 | } | |
1142 | ||
e60f8db5 AX |
1143 | r = gmc_v9_0_mc_init(adev); |
1144 | if (r) | |
1145 | return r; | |
1146 | ||
ebdef28e AD |
1147 | adev->gmc.stolen_size = gmc_v9_0_get_vbios_fb_size(adev); |
1148 | ||
e60f8db5 AX |
1149 | /* Memory manager */ |
1150 | r = amdgpu_bo_init(adev); | |
1151 | if (r) | |
1152 | return r; | |
1153 | ||
1154 | r = gmc_v9_0_gart_init(adev); | |
1155 | if (r) | |
1156 | return r; | |
1157 | ||
05ec3eda CK |
1158 | /* |
1159 | * number of VMs | |
1160 | * VMID 0 is reserved for System | |
1161 | * amdgpu graphics/compute will use VMIDs 1-7 | |
1162 | * amdkfd will use VMIDs 8-15 | |
1163 | */ | |
a2d15ed7 LM |
1164 | adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS; |
1165 | adev->vm_manager.id_mgr[AMDGPU_MMHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS; | |
c8a6e2a3 | 1166 | adev->vm_manager.id_mgr[AMDGPU_MMHUB_1].num_ids = AMDGPU_NUM_OF_VMIDS; |
05ec3eda | 1167 | |
05ec3eda CK |
1168 | amdgpu_vm_manager_init(adev); |
1169 | ||
1170 | return 0; | |
e60f8db5 AX |
1171 | } |
1172 | ||
e60f8db5 AX |
1173 | static int gmc_v9_0_sw_fini(void *handle) |
1174 | { | |
1175 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
994dcfaa | 1176 | void *stolen_vga_buf; |
e60f8db5 | 1177 | |
791c4769 | 1178 | if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC) && |
145b03eb TZ |
1179 | adev->gmc.umc_ras_if) { |
1180 | struct ras_common_if *ras_if = adev->gmc.umc_ras_if; | |
791c4769 | 1181 | struct ras_ih_if ih_info = { |
1182 | .head = *ras_if, | |
1183 | }; | |
1184 | ||
145b03eb | 1185 | /* remove fs first */ |
791c4769 | 1186 | amdgpu_ras_debugfs_remove(adev, ras_if); |
1187 | amdgpu_ras_sysfs_remove(adev, ras_if); | |
145b03eb | 1188 | /* remove the IH */ |
791c4769 | 1189 | amdgpu_ras_interrupt_remove_handler(adev, &ih_info); |
1190 | amdgpu_ras_feature_enable(adev, ras_if, 0); | |
1191 | kfree(ras_if); | |
1192 | } | |
1193 | ||
145b03eb TZ |
1194 | if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB) && |
1195 | adev->gmc.mmhub_ras_if) { | |
1196 | struct ras_common_if *ras_if = adev->gmc.mmhub_ras_if; | |
1197 | ||
1198 | /* remove fs and disable ras feature */ | |
1199 | amdgpu_ras_debugfs_remove(adev, ras_if); | |
1200 | amdgpu_ras_sysfs_remove(adev, ras_if); | |
1201 | amdgpu_ras_feature_enable(adev, ras_if, 0); | |
1202 | kfree(ras_if); | |
1203 | } | |
1204 | ||
f59548c8 | 1205 | amdgpu_gem_force_release(adev); |
05ec3eda | 1206 | amdgpu_vm_manager_fini(adev); |
6f752ec2 | 1207 | |
cd2b5623 | 1208 | if (gmc_v9_0_keep_stolen_memory(adev)) |
994dcfaa | 1209 | amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, &stolen_vga_buf); |
6f752ec2 | 1210 | |
a3d9103e | 1211 | amdgpu_gart_table_vram_free(adev); |
e60f8db5 | 1212 | amdgpu_bo_fini(adev); |
a3d9103e | 1213 | amdgpu_gart_fini(adev); |
e60f8db5 AX |
1214 | |
1215 | return 0; | |
1216 | } | |
1217 | ||
1218 | static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) | |
1219 | { | |
946a4d5b | 1220 | |
e60f8db5 AX |
1221 | switch (adev->asic_type) { |
1222 | case CHIP_VEGA10: | |
4cd4c5c0 | 1223 | if (amdgpu_sriov_vf(adev)) |
98cad2de TH |
1224 | break; |
1225 | /* fall through */ | |
d96b428c | 1226 | case CHIP_VEGA20: |
946a4d5b | 1227 | soc15_program_register_sequence(adev, |
5c583018 | 1228 | golden_settings_mmhub_1_0_0, |
c47b41a7 | 1229 | ARRAY_SIZE(golden_settings_mmhub_1_0_0)); |
946a4d5b | 1230 | soc15_program_register_sequence(adev, |
5c583018 | 1231 | golden_settings_athub_1_0_0, |
c47b41a7 | 1232 | ARRAY_SIZE(golden_settings_athub_1_0_0)); |
e60f8db5 | 1233 | break; |
273a14cd AD |
1234 | case CHIP_VEGA12: |
1235 | break; | |
e4f3abaa | 1236 | case CHIP_RAVEN: |
8787ee01 | 1237 | /* TODO for renoir */ |
946a4d5b | 1238 | soc15_program_register_sequence(adev, |
5c583018 | 1239 | golden_settings_athub_1_0_0, |
c47b41a7 | 1240 | ARRAY_SIZE(golden_settings_athub_1_0_0)); |
e4f3abaa | 1241 | break; |
e60f8db5 AX |
1242 | default: |
1243 | break; | |
1244 | } | |
1245 | } | |
1246 | ||
1247 | /** | |
1248 | * gmc_v9_0_gart_enable - gart enable | |
1249 | * | |
1250 | * @adev: amdgpu_device pointer | |
1251 | */ | |
1252 | static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) | |
1253 | { | |
3ff98548 | 1254 | int r, i; |
e60f8db5 AX |
1255 | bool value; |
1256 | u32 tmp; | |
1257 | ||
9c3f2b54 AD |
1258 | amdgpu_device_program_register_sequence(adev, |
1259 | golden_settings_vega10_hdp, | |
1260 | ARRAY_SIZE(golden_settings_vega10_hdp)); | |
e60f8db5 | 1261 | |
1123b989 | 1262 | if (adev->gart.bo == NULL) { |
e60f8db5 AX |
1263 | dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); |
1264 | return -EINVAL; | |
1265 | } | |
ce1b1b66 ML |
1266 | r = amdgpu_gart_table_vram_pin(adev); |
1267 | if (r) | |
1268 | return r; | |
e60f8db5 | 1269 | |
2fcd43ce HZ |
1270 | switch (adev->asic_type) { |
1271 | case CHIP_RAVEN: | |
8787ee01 | 1272 | /* TODO for renoir */ |
f8386b35 | 1273 | mmhub_v1_0_update_power_gating(adev, true); |
2fcd43ce HZ |
1274 | break; |
1275 | default: | |
1276 | break; | |
1277 | } | |
1278 | ||
e60f8db5 AX |
1279 | r = gfxhub_v1_0_gart_enable(adev); |
1280 | if (r) | |
1281 | return r; | |
1282 | ||
51cce480 LM |
1283 | if (adev->asic_type == CHIP_ARCTURUS) |
1284 | r = mmhub_v9_4_gart_enable(adev); | |
1285 | else | |
1286 | r = mmhub_v1_0_gart_enable(adev); | |
e60f8db5 AX |
1287 | if (r) |
1288 | return r; | |
1289 | ||
846347c9 | 1290 | WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1); |
e60f8db5 | 1291 | |
b9509c80 HR |
1292 | tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL); |
1293 | WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp); | |
e60f8db5 | 1294 | |
fe2b5323 TZ |
1295 | WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8)); |
1296 | WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40)); | |
1297 | ||
1d4e0a8c | 1298 | /* After HDP is initialized, flush HDP.*/ |
bebc0762 | 1299 | adev->nbio.funcs->hdp_flush(adev, NULL); |
1d4e0a8c | 1300 | |
e60f8db5 AX |
1301 | if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) |
1302 | value = false; | |
1303 | else | |
1304 | value = true; | |
1305 | ||
1306 | gfxhub_v1_0_set_fault_enable_default(adev, value); | |
51cce480 LM |
1307 | if (adev->asic_type == CHIP_ARCTURUS) |
1308 | mmhub_v9_4_set_fault_enable_default(adev, value); | |
1309 | else | |
1310 | mmhub_v1_0_set_fault_enable_default(adev, value); | |
3ff98548 OZ |
1311 | |
1312 | for (i = 0; i < adev->num_vmhubs; ++i) | |
1313 | gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0); | |
e60f8db5 AX |
1314 | |
1315 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", | |
770d13b1 | 1316 | (unsigned)(adev->gmc.gart_size >> 20), |
4e830fb1 | 1317 | (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); |
e60f8db5 AX |
1318 | adev->gart.ready = true; |
1319 | return 0; | |
1320 | } | |
1321 | ||
1322 | static int gmc_v9_0_hw_init(void *handle) | |
1323 | { | |
1324 | int r; | |
1325 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1326 | ||
1327 | /* The sequence of these two function calls matters.*/ | |
1328 | gmc_v9_0_init_golden_registers(adev); | |
1329 | ||
edca2d05 | 1330 | if (adev->mode_info.num_crtc) { |
edca2d05 | 1331 | /* Lockout access through VGA aperture*/ |
4d9c333a | 1332 | WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); |
edca2d05 AD |
1333 | |
1334 | /* disable VGA render */ | |
4d9c333a | 1335 | WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); |
edca2d05 AD |
1336 | } |
1337 | ||
e60f8db5 AX |
1338 | r = gmc_v9_0_gart_enable(adev); |
1339 | ||
1340 | return r; | |
1341 | } | |
1342 | ||
1343 | /** | |
1344 | * gmc_v9_0_gart_disable - gart disable | |
1345 | * | |
1346 | * @adev: amdgpu_device pointer | |
1347 | * | |
1348 | * This disables all VM page table. | |
1349 | */ | |
1350 | static void gmc_v9_0_gart_disable(struct amdgpu_device *adev) | |
1351 | { | |
1352 | gfxhub_v1_0_gart_disable(adev); | |
51cce480 LM |
1353 | if (adev->asic_type == CHIP_ARCTURUS) |
1354 | mmhub_v9_4_gart_disable(adev); | |
1355 | else | |
1356 | mmhub_v1_0_gart_disable(adev); | |
ce1b1b66 | 1357 | amdgpu_gart_table_vram_unpin(adev); |
e60f8db5 AX |
1358 | } |
1359 | ||
1360 | static int gmc_v9_0_hw_fini(void *handle) | |
1361 | { | |
1362 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1363 | ||
5dd696ae TH |
1364 | if (amdgpu_sriov_vf(adev)) { |
1365 | /* full access mode, so don't touch any GMC register */ | |
1366 | DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); | |
1367 | return 0; | |
1368 | } | |
1369 | ||
791c4769 | 1370 | amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); |
770d13b1 | 1371 | amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); |
e60f8db5 AX |
1372 | gmc_v9_0_gart_disable(adev); |
1373 | ||
1374 | return 0; | |
1375 | } | |
1376 | ||
1377 | static int gmc_v9_0_suspend(void *handle) | |
1378 | { | |
1379 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1380 | ||
f053cd47 | 1381 | return gmc_v9_0_hw_fini(adev); |
e60f8db5 AX |
1382 | } |
1383 | ||
1384 | static int gmc_v9_0_resume(void *handle) | |
1385 | { | |
1386 | int r; | |
1387 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1388 | ||
1389 | r = gmc_v9_0_hw_init(adev); | |
1390 | if (r) | |
1391 | return r; | |
1392 | ||
620f774f | 1393 | amdgpu_vmid_reset_all(adev); |
e60f8db5 | 1394 | |
32601d48 | 1395 | return 0; |
e60f8db5 AX |
1396 | } |
1397 | ||
1398 | static bool gmc_v9_0_is_idle(void *handle) | |
1399 | { | |
1400 | /* MC is always ready in GMC v9.*/ | |
1401 | return true; | |
1402 | } | |
1403 | ||
1404 | static int gmc_v9_0_wait_for_idle(void *handle) | |
1405 | { | |
1406 | /* There is no need to wait for MC idle in GMC v9.*/ | |
1407 | return 0; | |
1408 | } | |
1409 | ||
1410 | static int gmc_v9_0_soft_reset(void *handle) | |
1411 | { | |
1412 | /* XXX for emulation.*/ | |
1413 | return 0; | |
1414 | } | |
1415 | ||
1416 | static int gmc_v9_0_set_clockgating_state(void *handle, | |
1417 | enum amd_clockgating_state state) | |
1418 | { | |
d5583d4f HR |
1419 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1420 | ||
51cce480 | 1421 | if (adev->asic_type == CHIP_ARCTURUS) |
cb15e804 LM |
1422 | mmhub_v9_4_set_clockgating(adev, state); |
1423 | else | |
1424 | mmhub_v1_0_set_clockgating(adev, state); | |
bee7b51a LM |
1425 | |
1426 | athub_v1_0_set_clockgating(adev, state); | |
1427 | ||
1428 | return 0; | |
e60f8db5 AX |
1429 | } |
1430 | ||
13052be5 HR |
1431 | static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags) |
1432 | { | |
1433 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1434 | ||
51cce480 | 1435 | if (adev->asic_type == CHIP_ARCTURUS) |
cb15e804 LM |
1436 | mmhub_v9_4_get_clockgating(adev, flags); |
1437 | else | |
1438 | mmhub_v1_0_get_clockgating(adev, flags); | |
bee7b51a LM |
1439 | |
1440 | athub_v1_0_get_clockgating(adev, flags); | |
13052be5 HR |
1441 | } |
1442 | ||
e60f8db5 AX |
1443 | static int gmc_v9_0_set_powergating_state(void *handle, |
1444 | enum amd_powergating_state state) | |
1445 | { | |
1446 | return 0; | |
1447 | } | |
1448 | ||
1449 | const struct amd_ip_funcs gmc_v9_0_ip_funcs = { | |
1450 | .name = "gmc_v9_0", | |
1451 | .early_init = gmc_v9_0_early_init, | |
1452 | .late_init = gmc_v9_0_late_init, | |
1453 | .sw_init = gmc_v9_0_sw_init, | |
1454 | .sw_fini = gmc_v9_0_sw_fini, | |
1455 | .hw_init = gmc_v9_0_hw_init, | |
1456 | .hw_fini = gmc_v9_0_hw_fini, | |
1457 | .suspend = gmc_v9_0_suspend, | |
1458 | .resume = gmc_v9_0_resume, | |
1459 | .is_idle = gmc_v9_0_is_idle, | |
1460 | .wait_for_idle = gmc_v9_0_wait_for_idle, | |
1461 | .soft_reset = gmc_v9_0_soft_reset, | |
1462 | .set_clockgating_state = gmc_v9_0_set_clockgating_state, | |
1463 | .set_powergating_state = gmc_v9_0_set_powergating_state, | |
13052be5 | 1464 | .get_clockgating_state = gmc_v9_0_get_clockgating_state, |
e60f8db5 AX |
1465 | }; |
1466 | ||
1467 | const struct amdgpu_ip_block_version gmc_v9_0_ip_block = | |
1468 | { | |
1469 | .type = AMD_IP_BLOCK_TYPE_GMC, | |
1470 | .major = 9, | |
1471 | .minor = 0, | |
1472 | .rev = 0, | |
1473 | .funcs = &gmc_v9_0_ip_funcs, | |
1474 | }; |