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Merge tag 'mmc-v4.15-2' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / amdgpu / gmc_v9_0.c
CommitLineData
e60f8db5
AX		 1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include "amdgpu.h"
25#include "gmc_v9_0.h"
8d6a5230 26#include "amdgpu_atomfirmware.h"
e60f8db5
AX		 27
28#include "vega10/soc15ip.h"
29#include "vega10/HDP/hdp_4_0_offset.h"
30#include "vega10/HDP/hdp_4_0_sh_mask.h"
31#include "vega10/GC/gc_9_0_sh_mask.h"
edca2d05
AD		 32#include "vega10/DC/dce_12_0_offset.h"
33#include "vega10/DC/dce_12_0_sh_mask.h"
e60f8db5 34#include "vega10/vega10_enum.h"
5c583018
EQ		 35#include "vega10/MMHUB/mmhub_1_0_offset.h"
36#include "vega10/ATHUB/athub_1_0_offset.h"
e60f8db5
AX		 37
38#include "soc15_common.h"
39
40#include "nbio_v6_1.h"
aecbe64f 41#include "nbio_v7_0.h"
e60f8db5
AX		 42#include "gfxhub_v1_0.h"
43#include "mmhub_v1_0.h"
44
45#define mmDF_CS_AON0_DramBaseAddress0 0x0044
46#define mmDF_CS_AON0_DramBaseAddress0_BASE_IDX 0
47//DF_CS_AON0_DramBaseAddress0
48#define DF_CS_AON0_DramBaseAddress0__AddrRngVal__SHIFT 0x0
49#define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT 0x1
50#define DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT 0x4
51#define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT 0x8
52#define DF_CS_AON0_DramBaseAddress0__DramBaseAddr__SHIFT 0xc
53#define DF_CS_AON0_DramBaseAddress0__AddrRngVal_MASK 0x00000001L
54#define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK 0x00000002L
55#define DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK 0x000000F0L
56#define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK 0x00000700L
57#define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK 0xFFFFF000L
58
59/* XXX Move this macro to VEGA10 header file, which is like vid.h for VI.*/
60#define AMDGPU_NUM_OF_VMIDS 8
61
62static const u32 golden_settings_vega10_hdp[] =
63{
64 0xf64, 0x0fffffff, 0x00000000,
65 0xf65, 0x0fffffff, 0x00000000,
66 0xf66, 0x0fffffff, 0x00000000,
67 0xf67, 0x0fffffff, 0x00000000,
68 0xf68, 0x0fffffff, 0x00000000,
69 0xf6a, 0x0fffffff, 0x00000000,
70 0xf6b, 0x0fffffff, 0x00000000,
71 0xf6c, 0x0fffffff, 0x00000000,
72 0xf6d, 0x0fffffff, 0x00000000,
73 0xf6e, 0x0fffffff, 0x00000000,
74};
75
5c583018
EQ		 76static const u32 golden_settings_mmhub_1_0_0[] =
77{
78 SOC15_REG_OFFSET(MMHUB, 0, mmDAGB1_WRCLI2), 0x00000007, 0xfe5fe0fa,
79 SOC15_REG_OFFSET(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0), 0x00000030, 0x55555565
80};
81
82static const u32 golden_settings_athub_1_0_0[] =
83{
84 SOC15_REG_OFFSET(ATHUB, 0, mmRPB_ARB_CNTL), 0x0000ff00, 0x00000800,
85 SOC15_REG_OFFSET(ATHUB, 0, mmRPB_ARB_CNTL2), 0x00ff00ff, 0x00080008
86};
87
e60f8db5
AX		 88static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
89 struct amdgpu_irq_src *src,
90 unsigned type,
91 enum amdgpu_interrupt_state state)
92{
93 struct amdgpu_vmhub *hub;
ae6d1416 94 u32 tmp, reg, bits, i, j;
e60f8db5 95
11250164
CK		 96 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
97 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
98 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
99 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
100 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
101 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
102 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
103
e60f8db5
AX		 104 switch (state) {
105 case AMDGPU_IRQ_STATE_DISABLE:
ae6d1416
TSD		 106 for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) {
107 hub = &adev->vmhub[j];
108 for (i = 0; i < 16; i++) {
109 reg = hub->vm_context0_cntl + i;
110 tmp = RREG32(reg);
111 tmp &= ~bits;
112 WREG32(reg, tmp);
113 }
e60f8db5
AX		 114 }
115 break;
116 case AMDGPU_IRQ_STATE_ENABLE:
ae6d1416
TSD		 117 for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) {
118 hub = &adev->vmhub[j];
119 for (i = 0; i < 16; i++) {
120 reg = hub->vm_context0_cntl + i;
121 tmp = RREG32(reg);
122 tmp |= bits;
123 WREG32(reg, tmp);
124 }
e60f8db5 125 }
e60f8db5
AX		 126 default:
127 break;
128 }
129
130 return 0;
131}
132
133static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
134 struct amdgpu_irq_src *source,
135 struct amdgpu_iv_entry *entry)
136{
5a9b8e8a 137 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vm_id_src];
4d6cbde3 138 uint32_t status = 0;
e60f8db5
AX		 139 u64 addr;
140
141 addr = (u64)entry->src_data[0] << 12;
142 addr |= ((u64)entry->src_data[1] & 0xf) << 44;
143
79a0c465 144 if (!amdgpu_sriov_vf(adev)) {
5a9b8e8a
CK		 145 status = RREG32(hub->vm_l2_pro_fault_status);
146 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
4d6cbde3 147 }
e60f8db5 148
4d6cbde3
FK		 149 if (printk_ratelimit()) {
150 dev_err(adev->dev,
151 "[%s] VMC page fault (src_id:%u ring:%u vm_id:%u pas_id:%u)\n",
152 entry->vm_id_src ? "mmhub" : "gfxhub",
153 entry->src_id, entry->ring_id, entry->vm_id,
154 entry->pas_id);
155 dev_err(adev->dev, " at page 0x%016llx from %d\n",
156 addr, entry->client_id);
157 if (!amdgpu_sriov_vf(adev))
158 dev_err(adev->dev,
159 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
160 status);
79a0c465 161 }
e60f8db5
AX		 162
163 return 0;
164}
165
166static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = {
167 .set = gmc_v9_0_vm_fault_interrupt_state,
168 .process = gmc_v9_0_process_interrupt,
169};
170
171static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev)
172{
173 adev->mc.vm_fault.num_types = 1;
174 adev->mc.vm_fault.funcs = &gmc_v9_0_irq_funcs;
175}
176
03f89feb
CK		 177static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vm_id)
178{
179 u32 req = 0;
180
181 /* invalidate using legacy mode on vm_id*/
182 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
183 PER_VMID_INVALIDATE_REQ, 1 << vm_id);
184 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, 0);
185 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
186 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
187 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
188 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
189 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
190 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
191 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
192
193 return req;
194}
195
e60f8db5
AX		 196/*
197 * GART
198 * VMID 0 is the physical GPU addresses as used by the kernel.
199 * VMIDs 1-15 are used for userspace clients and are handled
200 * by the amdgpu vm/hsa code.
201 */
202
203/**
204 * gmc_v9_0_gart_flush_gpu_tlb - gart tlb flush callback
205 *
206 * @adev: amdgpu_device pointer
207 * @vmid: vm instance to flush
208 *
209 * Flush the TLB for the requested page table.
210 */
211static void gmc_v9_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
212 uint32_t vmid)
213{
214 /* Use register 17 for GART */
215 const unsigned eng = 17;
216 unsigned i, j;
217
218 /* flush hdp cache */
aecbe64f
CZ		 219 if (adev->flags & AMD_IS_APU)
220 nbio_v7_0_hdp_flush(adev);
221 else
222 nbio_v6_1_hdp_flush(adev);
e60f8db5
AX		 223
224 spin_lock(&adev->mc.invalidate_lock);
225
226 for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
227 struct amdgpu_vmhub *hub = &adev->vmhub[i];
03f89feb 228 u32 tmp = gmc_v9_0_get_invalidate_req(vmid);
e60f8db5 229
c7a7266b 230 WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);
e60f8db5
AX		 231
232 /* Busy wait for ACK.*/
233 for (j = 0; j < 100; j++) {
c7a7266b 234 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
e60f8db5
AX		 235 tmp &= 1 << vmid;
236 if (tmp)
237 break;
238 cpu_relax();
239 }
240 if (j < 100)
241 continue;
242
243 /* Wait for ACK with a delay.*/
244 for (j = 0; j < adev->usec_timeout; j++) {
c7a7266b 245 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
e60f8db5
AX		 246 tmp &= 1 << vmid;
247 if (tmp)
248 break;
249 udelay(1);
250 }
251 if (j < adev->usec_timeout)
252 continue;
253
254 DRM_ERROR("Timeout waiting for VM flush ACK!\n");
255 }
256
257 spin_unlock(&adev->mc.invalidate_lock);
258}
259
260/**
261 * gmc_v9_0_gart_set_pte_pde - update the page tables using MMIO
262 *
263 * @adev: amdgpu_device pointer
264 * @cpu_pt_addr: cpu address of the page table
265 * @gpu_page_idx: entry in the page table to update
266 * @addr: dst addr to write into pte/pde
267 * @flags: access flags
268 *
269 * Update the page tables using the CPU.
270 */
271static int gmc_v9_0_gart_set_pte_pde(struct amdgpu_device *adev,
272 void *cpu_pt_addr,
273 uint32_t gpu_page_idx,
274 uint64_t addr,
275 uint64_t flags)
276{
277 void __iomem *ptr = (void *)cpu_pt_addr;
278 uint64_t value;
279
280 /*
281 * PTE format on VEGA 10:
282 * 63:59 reserved
283 * 58:57 mtype
284 * 56 F
285 * 55 L
286 * 54 P
287 * 53 SW
288 * 52 T
289 * 50:48 reserved
290 * 47:12 4k physical page base address
291 * 11:7 fragment
292 * 6 write
293 * 5 read
294 * 4 exe
295 * 3 Z
296 * 2 snooped
297 * 1 system
298 * 0 valid
299 *
300 * PDE format on VEGA 10:
301 * 63:59 block fragment size
302 * 58:55 reserved
303 * 54 P
304 * 53:48 reserved
305 * 47:6 physical base address of PD or PTE
306 * 5:3 reserved
307 * 2 C
308 * 1 system
309 * 0 valid
310 */
311
312 /*
313 * The following is for PTE only. GART does not have PDEs.
314 */
315 value = addr & 0x0000FFFFFFFFF000ULL;
316 value |= flags;
317 writeq(value, ptr + (gpu_page_idx * 8));
318 return 0;
319}
320
321static uint64_t gmc_v9_0_get_vm_pte_flags(struct amdgpu_device *adev,
322 uint32_t flags)
323
324{
325 uint64_t pte_flag = 0;
326
327 if (flags & AMDGPU_VM_PAGE_EXECUTABLE)
328 pte_flag |= AMDGPU_PTE_EXECUTABLE;
329 if (flags & AMDGPU_VM_PAGE_READABLE)
330 pte_flag |= AMDGPU_PTE_READABLE;
331 if (flags & AMDGPU_VM_PAGE_WRITEABLE)
332 pte_flag |= AMDGPU_PTE_WRITEABLE;
333
334 switch (flags & AMDGPU_VM_MTYPE_MASK) {
335 case AMDGPU_VM_MTYPE_DEFAULT:
336 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
337 break;
338 case AMDGPU_VM_MTYPE_NC:
339 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
340 break;
341 case AMDGPU_VM_MTYPE_WC:
342 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_WC);
343 break;
344 case AMDGPU_VM_MTYPE_CC:
345 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_CC);
346 break;
347 case AMDGPU_VM_MTYPE_UC:
348 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_UC);
349 break;
350 default:
351 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
352 break;
353 }
354
355 if (flags & AMDGPU_VM_PAGE_PRT)
356 pte_flag |= AMDGPU_PTE_PRT;
357
358 return pte_flag;
359}
360
b1166325 361static u64 gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, u64 addr)
e60f8db5 362{
b1166325
CK		 363 addr = adev->vm_manager.vram_base_offset + addr - adev->mc.vram_start;
364 BUG_ON(addr & 0xFFFF00000000003FULL);
365 return addr;
e60f8db5
AX		 366}
367
f75e237c
CK		 368static const struct amdgpu_gart_funcs gmc_v9_0_gart_funcs = {
369 .flush_gpu_tlb = gmc_v9_0_gart_flush_gpu_tlb,
370 .set_pte_pde = gmc_v9_0_gart_set_pte_pde,
03f89feb 371 .get_invalidate_req = gmc_v9_0_get_invalidate_req,
b1166325
CK		 372 .get_vm_pte_flags = gmc_v9_0_get_vm_pte_flags,
373 .get_vm_pde = gmc_v9_0_get_vm_pde
e60f8db5
AX		 374};
375
f75e237c 376static void gmc_v9_0_set_gart_funcs(struct amdgpu_device *adev)
e60f8db5 377{
f75e237c
CK		 378 if (adev->gart.gart_funcs == NULL)
379 adev->gart.gart_funcs = &gmc_v9_0_gart_funcs;
e60f8db5
AX		 380}
381
382static int gmc_v9_0_early_init(void *handle)
383{
384 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
385
386 gmc_v9_0_set_gart_funcs(adev);
e60f8db5
AX		 387 gmc_v9_0_set_irq_funcs(adev);
388
389 return 0;
390}
391
392static int gmc_v9_0_late_init(void *handle)
393{
394 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
c5066129 395 /*
396 * The latest engine allocation on gfx9 is:
397 * Engine 0, 1: idle
398 * Engine 2, 3: firmware
399 * Engine 4~13: amdgpu ring, subject to change when ring number changes
400 * Engine 14~15: idle
401 * Engine 16: kfd tlb invalidation
402 * Engine 17: Gart flushes
403 */
404 unsigned vm_inv_eng[AMDGPU_MAX_VMHUBS] = { 4, 4 };
4789c463
CK		 405 unsigned i;
406
407 for(i = 0; i < adev->num_rings; ++i) {
408 struct amdgpu_ring *ring = adev->rings[i];
409 unsigned vmhub = ring->funcs->vmhub;
410
411 ring->vm_inv_eng = vm_inv_eng[vmhub]++;
775f55f1
TSD		 412 dev_info(adev->dev, "ring %u(%s) uses VM inv eng %u on hub %u\n",
413 ring->idx, ring->name, ring->vm_inv_eng,
414 ring->funcs->vmhub);
4789c463
CK		 415 }
416
c5066129 417 /* Engine 16 is used for KFD and 17 for GART flushes */
4789c463 418 for(i = 0; i < AMDGPU_MAX_VMHUBS; ++i)
c5066129 419 BUG_ON(vm_inv_eng[i] > 16);
4789c463 420
e60f8db5
AX		 421 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
422}
423
424static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
425 struct amdgpu_mc *mc)
426{
eeb2487d
ML		 427 u64 base = 0;
428 if (!amdgpu_sriov_vf(adev))
429 base = mmhub_v1_0_get_fb_location(adev);
e60f8db5 430 amdgpu_vram_location(adev, &adev->mc, base);
6f02a696 431 amdgpu_gart_location(adev, mc);
bc099ee9
CZ		 432 /* base offset of vram pages */
433 if (adev->flags & AMD_IS_APU)
434 adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev);
435 else
436 adev->vm_manager.vram_base_offset = 0;
e60f8db5
AX		 437}
438
439/**
440 * gmc_v9_0_mc_init - initialize the memory controller driver params
441 *
442 * @adev: amdgpu_device pointer
443 *
444 * Look up the amount of vram, vram width, and decide how to place
445 * vram and gart within the GPU's physical address space.
446 * Returns 0 for success.
447 */
448static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
449{
450 u32 tmp;
451 int chansize, numchan;
452
8d6a5230
AD		 453 adev->mc.vram_width = amdgpu_atomfirmware_get_vram_width(adev);
454 if (!adev->mc.vram_width) {
455 /* hbm memory channel size */
456 chansize = 128;
457
458 tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0);
459 tmp &= DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK;
460 tmp >>= DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
461 switch (tmp) {
462 case 0:
463 default:
464 numchan = 1;
465 break;
466 case 1:
467 numchan = 2;
468 break;
469 case 2:
470 numchan = 0;
471 break;
472 case 3:
473 numchan = 4;
474 break;
475 case 4:
476 numchan = 0;
477 break;
478 case 5:
479 numchan = 8;
480 break;
481 case 6:
482 numchan = 0;
483 break;
484 case 7:
485 numchan = 16;
486 break;
487 case 8:
488 numchan = 2;
489 break;
490 }
491 adev->mc.vram_width = numchan * chansize;
e60f8db5 492 }
e60f8db5
AX		 493
494 /* Could aper size report 0 ? */
495 adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
496 adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
497 /* size in MB on si */
498 adev->mc.mc_vram_size =
aecbe64f
CZ		 499 ((adev->flags & AMD_IS_APU) ? nbio_v7_0_get_memsize(adev) :
500 nbio_v6_1_get_memsize(adev)) * 1024ULL * 1024ULL;
e60f8db5
AX		 501 adev->mc.real_vram_size = adev->mc.mc_vram_size;
502 adev->mc.visible_vram_size = adev->mc.aper_size;
503
504 /* In case the PCI BAR is larger than the actual amount of vram */
505 if (adev->mc.visible_vram_size > adev->mc.real_vram_size)
506 adev->mc.visible_vram_size = adev->mc.real_vram_size;
507
c3db7b5a
AD		 508 /* set the gart size */
509 if (amdgpu_gart_size == -1) {
510 switch (adev->asic_type) {
511 case CHIP_VEGA10: /* all engines support GPUVM */
512 default:
513 adev->mc.gart_size = 256ULL << 20;
514 break;
515 case CHIP_RAVEN: /* DCE SG support */
516 adev->mc.gart_size = 1024ULL << 20;
517 break;
518 }
519 } else {
520 adev->mc.gart_size = (u64)amdgpu_gart_size << 20;
521 }
522
e60f8db5
AX		 523 gmc_v9_0_vram_gtt_location(adev, &adev->mc);
524
525 return 0;
526}
527
528static int gmc_v9_0_gart_init(struct amdgpu_device *adev)
529{
530 int r;
531
532 if (adev->gart.robj) {
533 WARN(1, "VEGA10 PCIE GART already initialized\n");
534 return 0;
535 }
536 /* Initialize common gart structure */
537 r = amdgpu_gart_init(adev);
538 if (r)
539 return r;
540 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
541 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE(MTYPE_UC) |
542 AMDGPU_PTE_EXECUTABLE;
543 return amdgpu_gart_table_vram_alloc(adev);
544}
545
e60f8db5
AX		 546static int gmc_v9_0_sw_init(void *handle)
547{
548 int r;
549 int dma_bits;
550 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
551
0c8c0847 552 gfxhub_v1_0_init(adev);
77f6c763 553 mmhub_v1_0_init(adev);
0c8c0847 554
e60f8db5
AX		 555 spin_lock_init(&adev->mc.invalidate_lock);
556
fd66560b
HZ		 557 switch (adev->asic_type) {
558 case CHIP_RAVEN:
e60f8db5 559 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
fd66560b
HZ		 560 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
561 adev->vm_manager.vm_size = 1U << 18;
562 adev->vm_manager.block_size = 9;
563 adev->vm_manager.num_level = 3;
d07f14be 564 amdgpu_vm_set_fragment_size(adev, 9);
fd66560b 565 } else {
d07f14be
RH		 566 /* vm_size is 64GB for legacy 2-level page support */
567 amdgpu_vm_adjust_size(adev, 64, 9);
fd66560b
HZ		 568 adev->vm_manager.num_level = 1;
569 }
570 break;
571 case CHIP_VEGA10:
e60f8db5
AX		 572 /* XXX Don't know how to get VRAM type yet. */
573 adev->mc.vram_type = AMDGPU_VRAM_TYPE_HBM;
36b32a68
ZJ		 574 /*
575 * To fulfill 4-level page support,
576 * vm size is 256TB (48bit), maximum size of Vega10,
577 * block size 512 (9bit)
578 */
579 adev->vm_manager.vm_size = 1U << 18;
580 adev->vm_manager.block_size = 9;
fd66560b 581 adev->vm_manager.num_level = 3;
d07f14be 582 amdgpu_vm_set_fragment_size(adev, 9);
fd66560b
HZ		 583 break;
584 default:
585 break;
e60f8db5
AX		 586 }
587
e618d306 588 DRM_INFO("vm size is %llu GB, block size is %u-bit,fragment size is %u-bit\n",
fd66560b 589 adev->vm_manager.vm_size,
e618d306
RH		 590 adev->vm_manager.block_size,
591 adev->vm_manager.fragment_size);
fd66560b 592
e60f8db5
AX		 593 /* This interrupt is VMC page fault.*/
594 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VMC, 0,
595 &adev->mc.vm_fault);
d7c434d3
FK		 596 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_UTCL2, 0,
597 &adev->mc.vm_fault);
e60f8db5
AX		 598
599 if (r)
600 return r;
601
36b32a68 602 adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
e60f8db5
AX		 603
604 /* Set the internal MC address mask
605 * This is the max address of the GPU's
606 * internal address space.
607 */
608 adev->mc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
609
916910ad
HR		 610 /*
611 * It needs to reserve 8M stolen memory for vega10
612 * TODO: Figure out how to avoid that...
613 */
614 adev->mc.stolen_size = 8 * 1024 * 1024;
615
e60f8db5
AX		 616 /* set DMA mask + need_dma32 flags.
617 * PCIE - can handle 44-bits.
618 * IGP - can handle 44-bits
619 * PCI - dma32 for legacy pci gart, 44 bits on vega10
620 */
621 adev->need_dma32 = false;
622 dma_bits = adev->need_dma32 ? 32 : 44;
623 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
624 if (r) {
625 adev->need_dma32 = true;
626 dma_bits = 32;
627 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
628 }
629 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
630 if (r) {
631 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
632 printk(KERN_WARNING "amdgpu: No coherent DMA available.\n");
633 }
634
635 r = gmc_v9_0_mc_init(adev);
636 if (r)
637 return r;
638
639 /* Memory manager */
640 r = amdgpu_bo_init(adev);
641 if (r)
642 return r;
643
644 r = gmc_v9_0_gart_init(adev);
645 if (r)
646 return r;
647
05ec3eda
CK		 648 /*
649 * number of VMs
650 * VMID 0 is reserved for System
651 * amdgpu graphics/compute will use VMIDs 1-7
652 * amdkfd will use VMIDs 8-15
653 */
654 adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids = AMDGPU_NUM_OF_VMIDS;
655 adev->vm_manager.id_mgr[AMDGPU_MMHUB].num_ids = AMDGPU_NUM_OF_VMIDS;
656
05ec3eda
CK		 657 amdgpu_vm_manager_init(adev);
658
659 return 0;
e60f8db5
AX		 660}
661
662/**
663 * gmc_v8_0_gart_fini - vm fini callback
664 *
665 * @adev: amdgpu_device pointer
666 *
667 * Tears down the driver GART/VM setup (CIK).
668 */
669static void gmc_v9_0_gart_fini(struct amdgpu_device *adev)
670{
671 amdgpu_gart_table_vram_free(adev);
672 amdgpu_gart_fini(adev);
673}
674
675static int gmc_v9_0_sw_fini(void *handle)
676{
677 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
678
05ec3eda 679 amdgpu_vm_manager_fini(adev);
e60f8db5
AX		 680 gmc_v9_0_gart_fini(adev);
681 amdgpu_gem_force_release(adev);
682 amdgpu_bo_fini(adev);
683
684 return 0;
685}
686
687static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
688{
689 switch (adev->asic_type) {
690 case CHIP_VEGA10:
5c583018
EQ		 691 amdgpu_program_register_sequence(adev,
692 golden_settings_mmhub_1_0_0,
693 (const u32)ARRAY_SIZE(golden_settings_mmhub_1_0_0));
694 amdgpu_program_register_sequence(adev,
695 golden_settings_athub_1_0_0,
696 (const u32)ARRAY_SIZE(golden_settings_athub_1_0_0));
e60f8db5 697 break;
e4f3abaa 698 case CHIP_RAVEN:
5c583018
EQ		 699 amdgpu_program_register_sequence(adev,
700 golden_settings_athub_1_0_0,
701 (const u32)ARRAY_SIZE(golden_settings_athub_1_0_0));
e4f3abaa 702 break;
e60f8db5
AX		 703 default:
704 break;
705 }
706}
707
708/**
709 * gmc_v9_0_gart_enable - gart enable
710 *
711 * @adev: amdgpu_device pointer
712 */
713static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
714{
715 int r;
716 bool value;
717 u32 tmp;
718
719 amdgpu_program_register_sequence(adev,
720 golden_settings_vega10_hdp,
721 (const u32)ARRAY_SIZE(golden_settings_vega10_hdp));
722
723 if (adev->gart.robj == NULL) {
724 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
725 return -EINVAL;
726 }
727 r = amdgpu_gart_table_vram_pin(adev);
728 if (r)
729 return r;
730
2fcd43ce
HZ		 731 switch (adev->asic_type) {
732 case CHIP_RAVEN:
733 mmhub_v1_0_initialize_power_gating(adev);
f8386b35 734 mmhub_v1_0_update_power_gating(adev, true);
2fcd43ce
HZ		 735 break;
736 default:
737 break;
738 }
739
e60f8db5
AX		 740 r = gfxhub_v1_0_gart_enable(adev);
741 if (r)
742 return r;
743
744 r = mmhub_v1_0_gart_enable(adev);
745 if (r)
746 return r;
747
846347c9 748 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
e60f8db5 749
b9509c80
HR		 750 tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL);
751 WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);
e60f8db5 752
1d4e0a8c
ML		 753 /* After HDP is initialized, flush HDP.*/
754 if (adev->flags & AMD_IS_APU)
755 nbio_v7_0_hdp_flush(adev);
756 else
757 nbio_v6_1_hdp_flush(adev);
758
e60f8db5
AX		 759 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
760 value = false;
761 else
762 value = true;
763
764 gfxhub_v1_0_set_fault_enable_default(adev, value);
765 mmhub_v1_0_set_fault_enable_default(adev, value);
e60f8db5
AX		 766 gmc_v9_0_gart_flush_gpu_tlb(adev, 0);
767
768 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
6f02a696 769 (unsigned)(adev->mc.gart_size >> 20),
e60f8db5
AX		 770 (unsigned long long)adev->gart.table_addr);
771 adev->gart.ready = true;
772 return 0;
773}
774
775static int gmc_v9_0_hw_init(void *handle)
776{
777 int r;
778 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
779
780 /* The sequence of these two function calls matters.*/
781 gmc_v9_0_init_golden_registers(adev);
782
edca2d05 783 if (adev->mode_info.num_crtc) {
edca2d05 784 /* Lockout access through VGA aperture*/
4d9c333a 785 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
edca2d05
AD		 786
787 /* disable VGA render */
4d9c333a 788 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
edca2d05
AD		 789 }
790
e60f8db5
AX		 791 r = gmc_v9_0_gart_enable(adev);
792
793 return r;
794}
795
796/**
797 * gmc_v9_0_gart_disable - gart disable
798 *
799 * @adev: amdgpu_device pointer
800 *
801 * This disables all VM page table.
802 */
803static void gmc_v9_0_gart_disable(struct amdgpu_device *adev)
804{
805 gfxhub_v1_0_gart_disable(adev);
806 mmhub_v1_0_gart_disable(adev);
807 amdgpu_gart_table_vram_unpin(adev);
808}
809
810static int gmc_v9_0_hw_fini(void *handle)
811{
812 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
813
5dd696ae
TH		 814 if (amdgpu_sriov_vf(adev)) {
815 /* full access mode, so don't touch any GMC register */
816 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
817 return 0;
818 }
819
e60f8db5
AX		 820 amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
821 gmc_v9_0_gart_disable(adev);
822
823 return 0;
824}
825
826static int gmc_v9_0_suspend(void *handle)
827{
828 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
829
f053cd47 830 return gmc_v9_0_hw_fini(adev);
e60f8db5
AX		 831}
832
833static int gmc_v9_0_resume(void *handle)
834{
835 int r;
836 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
837
838 r = gmc_v9_0_hw_init(adev);
839 if (r)
840 return r;
841
32601d48 842 amdgpu_vm_reset_all_ids(adev);
e60f8db5 843
32601d48 844 return 0;
e60f8db5
AX		 845}
846
847static bool gmc_v9_0_is_idle(void *handle)
848{
849 /* MC is always ready in GMC v9.*/
850 return true;
851}
852
853static int gmc_v9_0_wait_for_idle(void *handle)
854{
855 /* There is no need to wait for MC idle in GMC v9.*/
856 return 0;
857}
858
859static int gmc_v9_0_soft_reset(void *handle)
860{
861 /* XXX for emulation.*/
862 return 0;
863}
864
865static int gmc_v9_0_set_clockgating_state(void *handle,
866 enum amd_clockgating_state state)
867{
d5583d4f
HR		 868 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
869
870 return mmhub_v1_0_set_clockgating(adev, state);
e60f8db5
AX		 871}
872
13052be5
HR		 873static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags)
874{
875 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
876
877 mmhub_v1_0_get_clockgating(adev, flags);
878}
879
e60f8db5
AX		 880static int gmc_v9_0_set_powergating_state(void *handle,
881 enum amd_powergating_state state)
882{
883 return 0;
884}
885
886const struct amd_ip_funcs gmc_v9_0_ip_funcs = {
887 .name = "gmc_v9_0",
888 .early_init = gmc_v9_0_early_init,
889 .late_init = gmc_v9_0_late_init,
890 .sw_init = gmc_v9_0_sw_init,
891 .sw_fini = gmc_v9_0_sw_fini,
892 .hw_init = gmc_v9_0_hw_init,
893 .hw_fini = gmc_v9_0_hw_fini,
894 .suspend = gmc_v9_0_suspend,
895 .resume = gmc_v9_0_resume,
896 .is_idle = gmc_v9_0_is_idle,
897 .wait_for_idle = gmc_v9_0_wait_for_idle,
898 .soft_reset = gmc_v9_0_soft_reset,
899 .set_clockgating_state = gmc_v9_0_set_clockgating_state,
900 .set_powergating_state = gmc_v9_0_set_powergating_state,
13052be5 901 .get_clockgating_state = gmc_v9_0_get_clockgating_state,
e60f8db5
AX		 902};
903
904const struct amdgpu_ip_block_version gmc_v9_0_ip_block =
905{
906 .type = AMD_IP_BLOCK_TYPE_GMC,
907 .major = 9,
908 .minor = 0,
909 .rev = 0,
910 .funcs = &gmc_v9_0_ip_funcs,
911};
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