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e60f8db5 AX |
1 | /* |
2 | * Copyright 2016 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | */ | |
f867723b | 23 | |
e60f8db5 | 24 | #include <linux/firmware.h> |
f867723b SR |
25 | #include <linux/pci.h> |
26 | ||
fd5fd480 | 27 | #include <drm/drm_cache.h> |
f867723b | 28 | |
e60f8db5 AX |
29 | #include "amdgpu.h" |
30 | #include "gmc_v9_0.h" | |
8d6a5230 | 31 | #include "amdgpu_atomfirmware.h" |
2cddc50e | 32 | #include "amdgpu_gem.h" |
e60f8db5 | 33 | |
75199b8c FX |
34 | #include "hdp/hdp_4_0_offset.h" |
35 | #include "hdp/hdp_4_0_sh_mask.h" | |
cde5c34f | 36 | #include "gc/gc_9_0_sh_mask.h" |
135d4b10 FX |
37 | #include "dce/dce_12_0_offset.h" |
38 | #include "dce/dce_12_0_sh_mask.h" | |
fb960bd2 | 39 | #include "vega10_enum.h" |
65417d9f | 40 | #include "mmhub/mmhub_1_0_offset.h" |
6ce68225 | 41 | #include "athub/athub_1_0_offset.h" |
250b4228 | 42 | #include "oss/osssys_4_0_offset.h" |
e60f8db5 | 43 | |
946a4d5b | 44 | #include "soc15.h" |
e60f8db5 | 45 | #include "soc15_common.h" |
90c7a935 | 46 | #include "umc/umc_6_0_sh_mask.h" |
e60f8db5 | 47 | |
e60f8db5 AX |
48 | #include "gfxhub_v1_0.h" |
49 | #include "mmhub_v1_0.h" | |
bf0a60b7 | 50 | #include "gfxhub_v1_1.h" |
51cce480 | 51 | #include "mmhub_v9_4.h" |
5b6b35aa | 52 | #include "umc_v6_1.h" |
e60f8db5 | 53 | |
44a99b65 AG |
54 | #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" |
55 | ||
791c4769 | 56 | #include "amdgpu_ras.h" |
57 | ||
ebdef28e AD |
58 | /* add these here since we already include dce12 headers and these are for DCN */ |
59 | #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d | |
60 | #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 | |
61 | #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 | |
62 | #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 | |
63 | #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL | |
64 | #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L | |
65 | ||
e60f8db5 AX |
66 | /* XXX Move this macro to VEGA10 header file, which is like vid.h for VI.*/ |
67 | #define AMDGPU_NUM_OF_VMIDS 8 | |
68 | ||
69 | static const u32 golden_settings_vega10_hdp[] = | |
70 | { | |
71 | 0xf64, 0x0fffffff, 0x00000000, | |
72 | 0xf65, 0x0fffffff, 0x00000000, | |
73 | 0xf66, 0x0fffffff, 0x00000000, | |
74 | 0xf67, 0x0fffffff, 0x00000000, | |
75 | 0xf68, 0x0fffffff, 0x00000000, | |
76 | 0xf6a, 0x0fffffff, 0x00000000, | |
77 | 0xf6b, 0x0fffffff, 0x00000000, | |
78 | 0xf6c, 0x0fffffff, 0x00000000, | |
79 | 0xf6d, 0x0fffffff, 0x00000000, | |
80 | 0xf6e, 0x0fffffff, 0x00000000, | |
81 | }; | |
82 | ||
946a4d5b | 83 | static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] = |
5c583018 | 84 | { |
946a4d5b SL |
85 | SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa), |
86 | SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565) | |
5c583018 EQ |
87 | }; |
88 | ||
946a4d5b | 89 | static const struct soc15_reg_golden golden_settings_athub_1_0_0[] = |
5c583018 | 90 | { |
946a4d5b SL |
91 | SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800), |
92 | SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008) | |
5c583018 EQ |
93 | }; |
94 | ||
791c4769 | 95 | static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = { |
96 | (0x000143c0 + 0x00000000), | |
97 | (0x000143c0 + 0x00000800), | |
98 | (0x000143c0 + 0x00001000), | |
99 | (0x000143c0 + 0x00001800), | |
100 | (0x000543c0 + 0x00000000), | |
101 | (0x000543c0 + 0x00000800), | |
102 | (0x000543c0 + 0x00001000), | |
103 | (0x000543c0 + 0x00001800), | |
104 | (0x000943c0 + 0x00000000), | |
105 | (0x000943c0 + 0x00000800), | |
106 | (0x000943c0 + 0x00001000), | |
107 | (0x000943c0 + 0x00001800), | |
108 | (0x000d43c0 + 0x00000000), | |
109 | (0x000d43c0 + 0x00000800), | |
110 | (0x000d43c0 + 0x00001000), | |
111 | (0x000d43c0 + 0x00001800), | |
112 | (0x001143c0 + 0x00000000), | |
113 | (0x001143c0 + 0x00000800), | |
114 | (0x001143c0 + 0x00001000), | |
115 | (0x001143c0 + 0x00001800), | |
116 | (0x001543c0 + 0x00000000), | |
117 | (0x001543c0 + 0x00000800), | |
118 | (0x001543c0 + 0x00001000), | |
119 | (0x001543c0 + 0x00001800), | |
120 | (0x001943c0 + 0x00000000), | |
121 | (0x001943c0 + 0x00000800), | |
122 | (0x001943c0 + 0x00001000), | |
123 | (0x001943c0 + 0x00001800), | |
124 | (0x001d43c0 + 0x00000000), | |
125 | (0x001d43c0 + 0x00000800), | |
126 | (0x001d43c0 + 0x00001000), | |
127 | (0x001d43c0 + 0x00001800), | |
02bab923 DP |
128 | }; |
129 | ||
791c4769 | 130 | static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = { |
131 | (0x000143e0 + 0x00000000), | |
132 | (0x000143e0 + 0x00000800), | |
133 | (0x000143e0 + 0x00001000), | |
134 | (0x000143e0 + 0x00001800), | |
135 | (0x000543e0 + 0x00000000), | |
136 | (0x000543e0 + 0x00000800), | |
137 | (0x000543e0 + 0x00001000), | |
138 | (0x000543e0 + 0x00001800), | |
139 | (0x000943e0 + 0x00000000), | |
140 | (0x000943e0 + 0x00000800), | |
141 | (0x000943e0 + 0x00001000), | |
142 | (0x000943e0 + 0x00001800), | |
143 | (0x000d43e0 + 0x00000000), | |
144 | (0x000d43e0 + 0x00000800), | |
145 | (0x000d43e0 + 0x00001000), | |
146 | (0x000d43e0 + 0x00001800), | |
147 | (0x001143e0 + 0x00000000), | |
148 | (0x001143e0 + 0x00000800), | |
149 | (0x001143e0 + 0x00001000), | |
150 | (0x001143e0 + 0x00001800), | |
151 | (0x001543e0 + 0x00000000), | |
152 | (0x001543e0 + 0x00000800), | |
153 | (0x001543e0 + 0x00001000), | |
154 | (0x001543e0 + 0x00001800), | |
155 | (0x001943e0 + 0x00000000), | |
156 | (0x001943e0 + 0x00000800), | |
157 | (0x001943e0 + 0x00001000), | |
158 | (0x001943e0 + 0x00001800), | |
159 | (0x001d43e0 + 0x00000000), | |
160 | (0x001d43e0 + 0x00000800), | |
161 | (0x001d43e0 + 0x00001000), | |
162 | (0x001d43e0 + 0x00001800), | |
02bab923 DP |
163 | }; |
164 | ||
791c4769 | 165 | static const uint32_t ecc_umc_mcumc_status_addrs[] = { |
166 | (0x000143c2 + 0x00000000), | |
167 | (0x000143c2 + 0x00000800), | |
168 | (0x000143c2 + 0x00001000), | |
169 | (0x000143c2 + 0x00001800), | |
170 | (0x000543c2 + 0x00000000), | |
171 | (0x000543c2 + 0x00000800), | |
172 | (0x000543c2 + 0x00001000), | |
173 | (0x000543c2 + 0x00001800), | |
174 | (0x000943c2 + 0x00000000), | |
175 | (0x000943c2 + 0x00000800), | |
176 | (0x000943c2 + 0x00001000), | |
177 | (0x000943c2 + 0x00001800), | |
178 | (0x000d43c2 + 0x00000000), | |
179 | (0x000d43c2 + 0x00000800), | |
180 | (0x000d43c2 + 0x00001000), | |
181 | (0x000d43c2 + 0x00001800), | |
182 | (0x001143c2 + 0x00000000), | |
183 | (0x001143c2 + 0x00000800), | |
184 | (0x001143c2 + 0x00001000), | |
185 | (0x001143c2 + 0x00001800), | |
186 | (0x001543c2 + 0x00000000), | |
187 | (0x001543c2 + 0x00000800), | |
188 | (0x001543c2 + 0x00001000), | |
189 | (0x001543c2 + 0x00001800), | |
190 | (0x001943c2 + 0x00000000), | |
191 | (0x001943c2 + 0x00000800), | |
192 | (0x001943c2 + 0x00001000), | |
193 | (0x001943c2 + 0x00001800), | |
194 | (0x001d43c2 + 0x00000000), | |
195 | (0x001d43c2 + 0x00000800), | |
196 | (0x001d43c2 + 0x00001000), | |
197 | (0x001d43c2 + 0x00001800), | |
02bab923 DP |
198 | }; |
199 | ||
791c4769 | 200 | static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev, |
201 | struct amdgpu_irq_src *src, | |
202 | unsigned type, | |
203 | enum amdgpu_interrupt_state state) | |
204 | { | |
205 | u32 bits, i, tmp, reg; | |
206 | ||
207 | bits = 0x7f; | |
208 | ||
209 | switch (state) { | |
210 | case AMDGPU_IRQ_STATE_DISABLE: | |
211 | for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { | |
212 | reg = ecc_umc_mcumc_ctrl_addrs[i]; | |
213 | tmp = RREG32(reg); | |
214 | tmp &= ~bits; | |
215 | WREG32(reg, tmp); | |
216 | } | |
217 | for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { | |
218 | reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; | |
219 | tmp = RREG32(reg); | |
220 | tmp &= ~bits; | |
221 | WREG32(reg, tmp); | |
222 | } | |
223 | break; | |
224 | case AMDGPU_IRQ_STATE_ENABLE: | |
225 | for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { | |
226 | reg = ecc_umc_mcumc_ctrl_addrs[i]; | |
227 | tmp = RREG32(reg); | |
228 | tmp |= bits; | |
229 | WREG32(reg, tmp); | |
230 | } | |
231 | for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { | |
232 | reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; | |
233 | tmp = RREG32(reg); | |
234 | tmp |= bits; | |
235 | WREG32(reg, tmp); | |
236 | } | |
237 | break; | |
238 | default: | |
239 | break; | |
240 | } | |
241 | ||
242 | return 0; | |
243 | } | |
244 | ||
245 | static int gmc_v9_0_process_ras_data_cb(struct amdgpu_device *adev, | |
81e02619 | 246 | struct ras_err_data *err_data, |
791c4769 | 247 | struct amdgpu_iv_entry *entry) |
248 | { | |
9b54d201 | 249 | kgd2kfd_set_sram_ecc_flag(adev->kfd.dev); |
045c0216 | 250 | if (adev->umc.funcs->query_ras_error_count) |
81e02619 | 251 | adev->umc.funcs->query_ras_error_count(adev, err_data); |
791c4769 | 252 | amdgpu_ras_reset_gpu(adev, 0); |
253 | return AMDGPU_RAS_UE; | |
254 | } | |
255 | ||
256 | static int gmc_v9_0_process_ecc_irq(struct amdgpu_device *adev, | |
257 | struct amdgpu_irq_src *source, | |
258 | struct amdgpu_iv_entry *entry) | |
259 | { | |
14cfde84 | 260 | struct ras_common_if *ras_if = adev->gmc.ras_if; |
791c4769 | 261 | struct ras_dispatch_if ih_data = { |
791c4769 | 262 | .entry = entry, |
263 | }; | |
14cfde84 | 264 | |
265 | if (!ras_if) | |
266 | return 0; | |
267 | ||
268 | ih_data.head = *ras_if; | |
269 | ||
791c4769 | 270 | amdgpu_ras_interrupt_dispatch(adev, &ih_data); |
271 | return 0; | |
272 | } | |
273 | ||
e60f8db5 AX |
274 | static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, |
275 | struct amdgpu_irq_src *src, | |
276 | unsigned type, | |
277 | enum amdgpu_interrupt_state state) | |
278 | { | |
279 | struct amdgpu_vmhub *hub; | |
ae6d1416 | 280 | u32 tmp, reg, bits, i, j; |
e60f8db5 | 281 | |
11250164 CK |
282 | bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | |
283 | VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | | |
284 | VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | | |
285 | VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | | |
286 | VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | | |
287 | VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | | |
288 | VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; | |
289 | ||
e60f8db5 AX |
290 | switch (state) { |
291 | case AMDGPU_IRQ_STATE_DISABLE: | |
1daa2bfa | 292 | for (j = 0; j < adev->num_vmhubs; j++) { |
ae6d1416 TSD |
293 | hub = &adev->vmhub[j]; |
294 | for (i = 0; i < 16; i++) { | |
295 | reg = hub->vm_context0_cntl + i; | |
296 | tmp = RREG32(reg); | |
297 | tmp &= ~bits; | |
298 | WREG32(reg, tmp); | |
299 | } | |
e60f8db5 AX |
300 | } |
301 | break; | |
302 | case AMDGPU_IRQ_STATE_ENABLE: | |
1daa2bfa | 303 | for (j = 0; j < adev->num_vmhubs; j++) { |
ae6d1416 TSD |
304 | hub = &adev->vmhub[j]; |
305 | for (i = 0; i < 16; i++) { | |
306 | reg = hub->vm_context0_cntl + i; | |
307 | tmp = RREG32(reg); | |
308 | tmp |= bits; | |
309 | WREG32(reg, tmp); | |
310 | } | |
e60f8db5 | 311 | } |
e60f8db5 AX |
312 | default: |
313 | break; | |
314 | } | |
315 | ||
316 | return 0; | |
317 | } | |
318 | ||
319 | static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, | |
320 | struct amdgpu_irq_src *source, | |
321 | struct amdgpu_iv_entry *entry) | |
322 | { | |
51c60898 | 323 | struct amdgpu_vmhub *hub; |
c468f9e2 | 324 | bool retry_fault = !!(entry->src_data[1] & 0x80); |
4d6cbde3 | 325 | uint32_t status = 0; |
e60f8db5 | 326 | u64 addr; |
51c60898 | 327 | char hub_name[10]; |
e60f8db5 AX |
328 | |
329 | addr = (u64)entry->src_data[0] << 12; | |
330 | addr |= ((u64)entry->src_data[1] & 0xf) << 44; | |
331 | ||
c1a8abd9 CK |
332 | if (retry_fault && amdgpu_gmc_filter_faults(adev, addr, entry->pasid, |
333 | entry->timestamp)) | |
22666cc1 CK |
334 | return 1; /* This also prevents sending it to KFD */ |
335 | ||
51c60898 LM |
336 | if (entry->client_id == SOC15_IH_CLIENTID_VMC) { |
337 | snprintf(hub_name, sizeof(hub_name), "mmhub0"); | |
338 | hub = &adev->vmhub[AMDGPU_MMHUB_0]; | |
339 | } else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) { | |
340 | snprintf(hub_name, sizeof(hub_name), "mmhub1"); | |
341 | hub = &adev->vmhub[AMDGPU_MMHUB_1]; | |
342 | } else { | |
343 | snprintf(hub_name, sizeof(hub_name), "gfxhub0"); | |
344 | hub = &adev->vmhub[AMDGPU_GFXHUB_0]; | |
345 | } | |
346 | ||
c1a8abd9 | 347 | /* If it's the first fault for this address, process it normally */ |
79a0c465 | 348 | if (!amdgpu_sriov_vf(adev)) { |
5a9b8e8a CK |
349 | status = RREG32(hub->vm_l2_pro_fault_status); |
350 | WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); | |
4d6cbde3 | 351 | } |
e60f8db5 | 352 | |
4d6cbde3 | 353 | if (printk_ratelimit()) { |
05794eff | 354 | struct amdgpu_task_info task_info; |
efaa9646 | 355 | |
05794eff | 356 | memset(&task_info, 0, sizeof(struct amdgpu_task_info)); |
efaa9646 AG |
357 | amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); |
358 | ||
4d6cbde3 | 359 | dev_err(adev->dev, |
c468f9e2 CK |
360 | "[%s] %s page fault (src_id:%u ring:%u vmid:%u " |
361 | "pasid:%u, for process %s pid %d thread %s pid %d)\n", | |
51c60898 | 362 | hub_name, retry_fault ? "retry" : "no-retry", |
c4f46f22 | 363 | entry->src_id, entry->ring_id, entry->vmid, |
efaa9646 AG |
364 | entry->pasid, task_info.process_name, task_info.tgid, |
365 | task_info.task_name, task_info.pid); | |
5ddd4a9a | 366 | dev_err(adev->dev, " in page starting at address 0x%016llx from client %d\n", |
4d6cbde3 | 367 | addr, entry->client_id); |
5ddd4a9a | 368 | if (!amdgpu_sriov_vf(adev)) { |
4d6cbde3 FK |
369 | dev_err(adev->dev, |
370 | "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", | |
371 | status); | |
5ddd4a9a YZ |
372 | dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", |
373 | REG_GET_FIELD(status, | |
374 | VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); | |
375 | dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", | |
376 | REG_GET_FIELD(status, | |
377 | VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); | |
378 | dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", | |
379 | REG_GET_FIELD(status, | |
380 | VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); | |
381 | dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", | |
382 | REG_GET_FIELD(status, | |
383 | VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); | |
384 | ||
385 | } | |
79a0c465 | 386 | } |
e60f8db5 AX |
387 | |
388 | return 0; | |
389 | } | |
390 | ||
391 | static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = { | |
392 | .set = gmc_v9_0_vm_fault_interrupt_state, | |
393 | .process = gmc_v9_0_process_interrupt, | |
394 | }; | |
395 | ||
791c4769 | 396 | |
397 | static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = { | |
398 | .set = gmc_v9_0_ecc_interrupt_state, | |
399 | .process = gmc_v9_0_process_ecc_irq, | |
400 | }; | |
401 | ||
e60f8db5 AX |
402 | static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev) |
403 | { | |
770d13b1 CK |
404 | adev->gmc.vm_fault.num_types = 1; |
405 | adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs; | |
791c4769 | 406 | |
407 | adev->gmc.ecc_irq.num_types = 1; | |
408 | adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs; | |
e60f8db5 AX |
409 | } |
410 | ||
2a79d868 YZ |
411 | static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid, |
412 | uint32_t flush_type) | |
03f89feb CK |
413 | { |
414 | u32 req = 0; | |
415 | ||
03f89feb | 416 | req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, |
c4f46f22 | 417 | PER_VMID_INVALIDATE_REQ, 1 << vmid); |
2a79d868 | 418 | req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); |
03f89feb CK |
419 | req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); |
420 | req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); | |
421 | req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); | |
422 | req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); | |
423 | req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); | |
424 | req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, | |
425 | CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); | |
426 | ||
427 | return req; | |
428 | } | |
429 | ||
e60f8db5 AX |
430 | /* |
431 | * GART | |
432 | * VMID 0 is the physical GPU addresses as used by the kernel. | |
433 | * VMIDs 1-15 are used for userspace clients and are handled | |
434 | * by the amdgpu vm/hsa code. | |
435 | */ | |
436 | ||
437 | /** | |
2a79d868 | 438 | * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type |
e60f8db5 AX |
439 | * |
440 | * @adev: amdgpu_device pointer | |
441 | * @vmid: vm instance to flush | |
2a79d868 | 442 | * @flush_type: the flush type |
e60f8db5 | 443 | * |
2a79d868 | 444 | * Flush the TLB for the requested page table using certain type. |
e60f8db5 | 445 | */ |
132f34e4 | 446 | static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, |
2a79d868 | 447 | uint32_t vmid, uint32_t flush_type) |
e60f8db5 | 448 | { |
e60f8db5 AX |
449 | const unsigned eng = 17; |
450 | unsigned i, j; | |
e60f8db5 | 451 | |
1daa2bfa | 452 | for (i = 0; i < adev->num_vmhubs; ++i) { |
e60f8db5 | 453 | struct amdgpu_vmhub *hub = &adev->vmhub[i]; |
2a79d868 | 454 | u32 tmp = gmc_v9_0_get_invalidate_req(vmid, flush_type); |
e60f8db5 | 455 | |
82d1a1b1 CG |
456 | /* This is necessary for a HW workaround under SRIOV as well |
457 | * as GFXOFF under bare metal | |
458 | */ | |
459 | if (adev->gfx.kiq.ring.sched.ready && | |
460 | (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) && | |
461 | !adev->in_gpu_reset) { | |
af5fe1e9 CK |
462 | uint32_t req = hub->vm_inv_eng0_req + eng; |
463 | uint32_t ack = hub->vm_inv_eng0_ack + eng; | |
464 | ||
465 | amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, tmp, | |
466 | 1 << vmid); | |
467 | continue; | |
fc0faf04 | 468 | } |
3890d111 ED |
469 | |
470 | spin_lock(&adev->gmc.invalidate_lock); | |
c7a7266b | 471 | WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp); |
e60f8db5 | 472 | for (j = 0; j < adev->usec_timeout; j++) { |
c7a7266b | 473 | tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng); |
396557b0 | 474 | if (tmp & (1 << vmid)) |
e60f8db5 AX |
475 | break; |
476 | udelay(1); | |
477 | } | |
3890d111 | 478 | spin_unlock(&adev->gmc.invalidate_lock); |
396557b0 CK |
479 | if (j < adev->usec_timeout) |
480 | continue; | |
481 | ||
e60f8db5 AX |
482 | DRM_ERROR("Timeout waiting for VM flush ACK!\n"); |
483 | } | |
e60f8db5 AX |
484 | } |
485 | ||
9096d6e5 | 486 | static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, |
c633c00b | 487 | unsigned vmid, uint64_t pd_addr) |
9096d6e5 | 488 | { |
250b4228 CK |
489 | struct amdgpu_device *adev = ring->adev; |
490 | struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub]; | |
2a79d868 | 491 | uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0); |
9096d6e5 CK |
492 | unsigned eng = ring->vm_inv_eng; |
493 | ||
9096d6e5 CK |
494 | amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid), |
495 | lower_32_bits(pd_addr)); | |
496 | ||
497 | amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid), | |
498 | upper_32_bits(pd_addr)); | |
499 | ||
f8bc9037 AD |
500 | amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + eng, |
501 | hub->vm_inv_eng0_ack + eng, | |
502 | req, 1 << vmid); | |
f732b6b3 | 503 | |
9096d6e5 CK |
504 | return pd_addr; |
505 | } | |
506 | ||
c633c00b CK |
507 | static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, |
508 | unsigned pasid) | |
509 | { | |
510 | struct amdgpu_device *adev = ring->adev; | |
511 | uint32_t reg; | |
512 | ||
f2d66571 LM |
513 | /* Do nothing because there's no lut register for mmhub1. */ |
514 | if (ring->funcs->vmhub == AMDGPU_MMHUB_1) | |
515 | return; | |
516 | ||
a2d15ed7 | 517 | if (ring->funcs->vmhub == AMDGPU_GFXHUB_0) |
c633c00b CK |
518 | reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; |
519 | else | |
520 | reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; | |
521 | ||
522 | amdgpu_ring_emit_wreg(ring, reg, pasid); | |
523 | } | |
524 | ||
6490bd76 YZ |
525 | /* |
526 | * PTE format on VEGA 10: | |
527 | * 63:59 reserved | |
528 | * 58:57 mtype | |
529 | * 56 F | |
530 | * 55 L | |
531 | * 54 P | |
532 | * 53 SW | |
533 | * 52 T | |
534 | * 50:48 reserved | |
535 | * 47:12 4k physical page base address | |
536 | * 11:7 fragment | |
537 | * 6 write | |
538 | * 5 read | |
539 | * 4 exe | |
540 | * 3 Z | |
541 | * 2 snooped | |
542 | * 1 system | |
543 | * 0 valid | |
e60f8db5 | 544 | * |
6490bd76 YZ |
545 | * PDE format on VEGA 10: |
546 | * 63:59 block fragment size | |
547 | * 58:55 reserved | |
548 | * 54 P | |
549 | * 53:48 reserved | |
550 | * 47:6 physical base address of PD or PTE | |
551 | * 5:3 reserved | |
552 | * 2 C | |
553 | * 1 system | |
554 | * 0 valid | |
e60f8db5 | 555 | */ |
e60f8db5 AX |
556 | |
557 | static uint64_t gmc_v9_0_get_vm_pte_flags(struct amdgpu_device *adev, | |
558 | uint32_t flags) | |
559 | ||
560 | { | |
561 | uint64_t pte_flag = 0; | |
562 | ||
563 | if (flags & AMDGPU_VM_PAGE_EXECUTABLE) | |
564 | pte_flag |= AMDGPU_PTE_EXECUTABLE; | |
565 | if (flags & AMDGPU_VM_PAGE_READABLE) | |
566 | pte_flag |= AMDGPU_PTE_READABLE; | |
567 | if (flags & AMDGPU_VM_PAGE_WRITEABLE) | |
568 | pte_flag |= AMDGPU_PTE_WRITEABLE; | |
569 | ||
570 | switch (flags & AMDGPU_VM_MTYPE_MASK) { | |
571 | case AMDGPU_VM_MTYPE_DEFAULT: | |
7596ab68 | 572 | pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); |
e60f8db5 AX |
573 | break; |
574 | case AMDGPU_VM_MTYPE_NC: | |
7596ab68 | 575 | pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); |
e60f8db5 AX |
576 | break; |
577 | case AMDGPU_VM_MTYPE_WC: | |
7596ab68 | 578 | pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_WC); |
e60f8db5 AX |
579 | break; |
580 | case AMDGPU_VM_MTYPE_CC: | |
7596ab68 | 581 | pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_CC); |
e60f8db5 AX |
582 | break; |
583 | case AMDGPU_VM_MTYPE_UC: | |
7596ab68 | 584 | pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_UC); |
e60f8db5 AX |
585 | break; |
586 | default: | |
7596ab68 | 587 | pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); |
e60f8db5 AX |
588 | break; |
589 | } | |
590 | ||
591 | if (flags & AMDGPU_VM_PAGE_PRT) | |
592 | pte_flag |= AMDGPU_PTE_PRT; | |
593 | ||
594 | return pte_flag; | |
595 | } | |
596 | ||
3de676d8 CK |
597 | static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level, |
598 | uint64_t *addr, uint64_t *flags) | |
e60f8db5 | 599 | { |
bbc9fb10 | 600 | if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) |
3de676d8 | 601 | *addr = adev->vm_manager.vram_base_offset + *addr - |
770d13b1 | 602 | adev->gmc.vram_start; |
3de676d8 | 603 | BUG_ON(*addr & 0xFFFF00000000003FULL); |
6a42fd6f | 604 | |
770d13b1 | 605 | if (!adev->gmc.translate_further) |
6a42fd6f CK |
606 | return; |
607 | ||
608 | if (level == AMDGPU_VM_PDB1) { | |
609 | /* Set the block fragment size */ | |
610 | if (!(*flags & AMDGPU_PDE_PTE)) | |
611 | *flags |= AMDGPU_PDE_BFS(0x9); | |
612 | ||
613 | } else if (level == AMDGPU_VM_PDB0) { | |
614 | if (*flags & AMDGPU_PDE_PTE) | |
615 | *flags &= ~AMDGPU_PDE_PTE; | |
616 | else | |
617 | *flags |= AMDGPU_PTE_TF; | |
618 | } | |
e60f8db5 AX |
619 | } |
620 | ||
132f34e4 CK |
621 | static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = { |
622 | .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb, | |
9096d6e5 | 623 | .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb, |
c633c00b | 624 | .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping, |
b1166325 CK |
625 | .get_vm_pte_flags = gmc_v9_0_get_vm_pte_flags, |
626 | .get_vm_pde = gmc_v9_0_get_vm_pde | |
e60f8db5 AX |
627 | }; |
628 | ||
132f34e4 | 629 | static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev) |
e60f8db5 | 630 | { |
f54b30d7 | 631 | adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs; |
e60f8db5 AX |
632 | } |
633 | ||
5b6b35aa HZ |
634 | static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev) |
635 | { | |
636 | switch (adev->asic_type) { | |
637 | case CHIP_VEGA20: | |
045c0216 TZ |
638 | adev->umc.max_ras_err_cnt_per_query = |
639 | UMC_V6_1_UMC_INSTANCE_NUM * UMC_V6_1_CHANNEL_INSTANCE_NUM; | |
640 | adev->umc.funcs = &umc_v6_1_funcs; | |
5b6b35aa HZ |
641 | break; |
642 | default: | |
643 | break; | |
644 | } | |
645 | } | |
646 | ||
e60f8db5 AX |
647 | static int gmc_v9_0_early_init(void *handle) |
648 | { | |
649 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
650 | ||
132f34e4 | 651 | gmc_v9_0_set_gmc_funcs(adev); |
e60f8db5 | 652 | gmc_v9_0_set_irq_funcs(adev); |
5b6b35aa | 653 | gmc_v9_0_set_umc_funcs(adev); |
e60f8db5 | 654 | |
770d13b1 CK |
655 | adev->gmc.shared_aperture_start = 0x2000000000000000ULL; |
656 | adev->gmc.shared_aperture_end = | |
657 | adev->gmc.shared_aperture_start + (4ULL << 30) - 1; | |
bfa8eea2 | 658 | adev->gmc.private_aperture_start = 0x1000000000000000ULL; |
770d13b1 CK |
659 | adev->gmc.private_aperture_end = |
660 | adev->gmc.private_aperture_start + (4ULL << 30) - 1; | |
a7ea6548 | 661 | |
e60f8db5 AX |
662 | return 0; |
663 | } | |
664 | ||
cd2b5623 AD |
665 | static bool gmc_v9_0_keep_stolen_memory(struct amdgpu_device *adev) |
666 | { | |
667 | ||
668 | /* | |
669 | * TODO: | |
670 | * Currently there is a bug where some memory client outside | |
671 | * of the driver writes to first 8M of VRAM on S3 resume, | |
672 | * this overrides GART which by default gets placed in first 8M and | |
673 | * causes VM_FAULTS once GTT is accessed. | |
674 | * Keep the stolen memory reservation until the while this is not solved. | |
675 | * Also check code in gmc_v9_0_get_vbios_fb_size and gmc_v9_0_late_init | |
676 | */ | |
677 | switch (adev->asic_type) { | |
6abc0c8f | 678 | case CHIP_VEGA10: |
cd2b5623 | 679 | case CHIP_RAVEN: |
bfa3a9bb | 680 | case CHIP_ARCTURUS: |
02122753 | 681 | return true; |
cd2b5623 AD |
682 | case CHIP_VEGA12: |
683 | case CHIP_VEGA20: | |
684 | default: | |
6abc0c8f | 685 | return false; |
cd2b5623 AD |
686 | } |
687 | } | |
688 | ||
c713a461 | 689 | static int gmc_v9_0_allocate_vm_inv_eng(struct amdgpu_device *adev) |
e60f8db5 | 690 | { |
c713a461 EQ |
691 | struct amdgpu_ring *ring; |
692 | unsigned vm_inv_engs[AMDGPU_MAX_VMHUBS] = | |
c8a6e2a3 LM |
693 | {GFXHUB_FREE_VM_INV_ENGS_BITMAP, MMHUB_FREE_VM_INV_ENGS_BITMAP, |
694 | GFXHUB_FREE_VM_INV_ENGS_BITMAP}; | |
4789c463 | 695 | unsigned i; |
c713a461 | 696 | unsigned vmhub, inv_eng; |
4789c463 | 697 | |
c713a461 EQ |
698 | for (i = 0; i < adev->num_rings; ++i) { |
699 | ring = adev->rings[i]; | |
700 | vmhub = ring->funcs->vmhub; | |
6f752ec2 | 701 | |
c713a461 EQ |
702 | inv_eng = ffs(vm_inv_engs[vmhub]); |
703 | if (!inv_eng) { | |
704 | dev_err(adev->dev, "no VM inv eng for ring %s\n", | |
705 | ring->name); | |
706 | return -EINVAL; | |
707 | } | |
708 | ||
709 | ring->vm_inv_eng = inv_eng - 1; | |
72464382 | 710 | vm_inv_engs[vmhub] &= ~(1 << ring->vm_inv_eng); |
4789c463 | 711 | |
6e82c6e0 CK |
712 | dev_info(adev->dev, "ring %s uses VM inv eng %u on hub %u\n", |
713 | ring->name, ring->vm_inv_eng, ring->funcs->vmhub); | |
4789c463 CK |
714 | } |
715 | ||
c713a461 EQ |
716 | return 0; |
717 | } | |
718 | ||
791c4769 | 719 | static int gmc_v9_0_ecc_late_init(void *handle) |
c713a461 EQ |
720 | { |
721 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
791c4769 | 722 | struct ras_common_if **ras_if = &adev->gmc.ras_if; |
723 | struct ras_ih_if ih_info = { | |
724 | .cb = gmc_v9_0_process_ras_data_cb, | |
725 | }; | |
726 | struct ras_fs_if fs_info = { | |
727 | .sysfs_name = "umc_err_count", | |
728 | .debugfs_name = "umc_err_inject", | |
729 | }; | |
730 | struct ras_common_if ras_block = { | |
731 | .block = AMDGPU_RAS_BLOCK__UMC, | |
732 | .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, | |
733 | .sub_block_index = 0, | |
734 | .name = "umc", | |
735 | }; | |
c713a461 EQ |
736 | int r; |
737 | ||
791c4769 | 738 | if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) { |
53d65054 | 739 | amdgpu_ras_feature_enable_on_boot(adev, &ras_block, 0); |
791c4769 | 740 | return 0; |
741 | } | |
5b6b35aa | 742 | |
acbbee01 | 743 | /* handle resume path. */ |
6121366b | 744 | if (*ras_if) { |
745 | /* resend ras TA enable cmd during resume. | |
746 | * prepare to handle failure. | |
747 | */ | |
748 | ih_info.head = **ras_if; | |
749 | r = amdgpu_ras_feature_enable_on_boot(adev, *ras_if, 1); | |
750 | if (r) { | |
751 | if (r == -EAGAIN) { | |
752 | /* request a gpu reset. will run again. */ | |
753 | amdgpu_ras_request_reset_on_boot(adev, | |
754 | AMDGPU_RAS_BLOCK__UMC); | |
755 | return 0; | |
756 | } | |
757 | /* fail to enable ras, cleanup all. */ | |
758 | goto irq; | |
759 | } | |
760 | /* enable successfully. continue. */ | |
acbbee01 | 761 | goto resume; |
6121366b | 762 | } |
791c4769 | 763 | |
764 | *ras_if = kmalloc(sizeof(**ras_if), GFP_KERNEL); | |
765 | if (!*ras_if) | |
766 | return -ENOMEM; | |
767 | ||
768 | **ras_if = ras_block; | |
769 | ||
53d65054 | 770 | r = amdgpu_ras_feature_enable_on_boot(adev, *ras_if, 1); |
36810fdb | 771 | if (r) { |
772 | if (r == -EAGAIN) { | |
773 | amdgpu_ras_request_reset_on_boot(adev, | |
774 | AMDGPU_RAS_BLOCK__UMC); | |
775 | r = 0; | |
776 | } | |
791c4769 | 777 | goto feature; |
36810fdb | 778 | } |
791c4769 | 779 | |
780 | ih_info.head = **ras_if; | |
781 | fs_info.head = **ras_if; | |
782 | ||
783 | r = amdgpu_ras_interrupt_add_handler(adev, &ih_info); | |
784 | if (r) | |
785 | goto interrupt; | |
786 | ||
450f30ea | 787 | amdgpu_ras_debugfs_create(adev, &fs_info); |
791c4769 | 788 | |
789 | r = amdgpu_ras_sysfs_create(adev, &fs_info); | |
790 | if (r) | |
791 | goto sysfs; | |
acbbee01 | 792 | resume: |
791c4769 | 793 | r = amdgpu_irq_get(adev, &adev->gmc.ecc_irq, 0); |
794 | if (r) | |
795 | goto irq; | |
796 | ||
797 | return 0; | |
798 | irq: | |
799 | amdgpu_ras_sysfs_remove(adev, *ras_if); | |
800 | sysfs: | |
801 | amdgpu_ras_debugfs_remove(adev, *ras_if); | |
791c4769 | 802 | amdgpu_ras_interrupt_remove_handler(adev, &ih_info); |
803 | interrupt: | |
804 | amdgpu_ras_feature_enable(adev, *ras_if, 0); | |
805 | feature: | |
806 | kfree(*ras_if); | |
807 | *ras_if = NULL; | |
36810fdb | 808 | return r; |
791c4769 | 809 | } |
810 | ||
811 | ||
c713a461 EQ |
812 | static int gmc_v9_0_late_init(void *handle) |
813 | { | |
814 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
f49ea9f8 | 815 | bool r; |
c713a461 EQ |
816 | |
817 | if (!gmc_v9_0_keep_stolen_memory(adev)) | |
818 | amdgpu_bo_late_init(adev); | |
819 | ||
820 | r = gmc_v9_0_allocate_vm_inv_eng(adev); | |
821 | if (r) | |
822 | return r; | |
f49ea9f8 HZ |
823 | /* Check if ecc is available */ |
824 | if (!amdgpu_sriov_vf(adev)) { | |
825 | switch (adev->asic_type) { | |
826 | case CHIP_VEGA10: | |
827 | case CHIP_VEGA20: | |
828 | r = amdgpu_atomfirmware_mem_ecc_supported(adev); | |
829 | if (!r) { | |
830 | DRM_INFO("ECC is not present.\n"); | |
831 | if (adev->df_funcs->enable_ecc_force_par_wr_rmw) | |
832 | adev->df_funcs->enable_ecc_force_par_wr_rmw(adev, false); | |
833 | } else { | |
834 | DRM_INFO("ECC is active.\n"); | |
835 | } | |
4789c463 | 836 | |
f49ea9f8 HZ |
837 | r = amdgpu_atomfirmware_sram_ecc_supported(adev); |
838 | if (!r) { | |
839 | DRM_INFO("SRAM ECC is not present.\n"); | |
840 | } else { | |
841 | DRM_INFO("SRAM ECC is active.\n"); | |
842 | } | |
843 | break; | |
844 | default: | |
845 | break; | |
5ba4fa35 | 846 | } |
02bab923 DP |
847 | } |
848 | ||
791c4769 | 849 | r = gmc_v9_0_ecc_late_init(handle); |
850 | if (r) | |
851 | return r; | |
852 | ||
770d13b1 | 853 | return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); |
e60f8db5 AX |
854 | } |
855 | ||
856 | static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, | |
770d13b1 | 857 | struct amdgpu_gmc *mc) |
e60f8db5 | 858 | { |
eeb2487d | 859 | u64 base = 0; |
51cce480 LM |
860 | if (!amdgpu_sriov_vf(adev)) { |
861 | if (adev->asic_type == CHIP_ARCTURUS) | |
862 | base = mmhub_v9_4_get_fb_location(adev); | |
863 | else | |
864 | base = mmhub_v1_0_get_fb_location(adev); | |
865 | } | |
6fdd68b1 AD |
866 | /* add the xgmi offset of the physical node */ |
867 | base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; | |
83afe835 | 868 | amdgpu_gmc_vram_location(adev, mc, base); |
961c75cf | 869 | amdgpu_gmc_gart_location(adev, mc); |
c3e1b43c CK |
870 | if (!amdgpu_sriov_vf(adev)) |
871 | amdgpu_gmc_agp_location(adev, mc); | |
bc099ee9 | 872 | /* base offset of vram pages */ |
b6110c00 | 873 | adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev); |
6fdd68b1 AD |
874 | |
875 | /* XXX: add the xgmi offset of the physical node? */ | |
876 | adev->vm_manager.vram_base_offset += | |
877 | adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; | |
e60f8db5 AX |
878 | } |
879 | ||
880 | /** | |
881 | * gmc_v9_0_mc_init - initialize the memory controller driver params | |
882 | * | |
883 | * @adev: amdgpu_device pointer | |
884 | * | |
885 | * Look up the amount of vram, vram width, and decide how to place | |
886 | * vram and gart within the GPU's physical address space. | |
887 | * Returns 0 for success. | |
888 | */ | |
889 | static int gmc_v9_0_mc_init(struct amdgpu_device *adev) | |
890 | { | |
e60f8db5 | 891 | int chansize, numchan; |
d6895ad3 | 892 | int r; |
e60f8db5 | 893 | |
067e75b3 AD |
894 | if (amdgpu_sriov_vf(adev)) { |
895 | /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN, | |
896 | * and DF related registers is not readable, seems hardcord is the | |
897 | * only way to set the correct vram_width | |
898 | */ | |
899 | adev->gmc.vram_width = 2048; | |
900 | } else if (amdgpu_emu_mode != 1) { | |
3d918c0e | 901 | adev->gmc.vram_width = amdgpu_atomfirmware_get_vram_width(adev); |
067e75b3 AD |
902 | } |
903 | ||
770d13b1 | 904 | if (!adev->gmc.vram_width) { |
8d6a5230 | 905 | /* hbm memory channel size */ |
585b7f16 TSD |
906 | if (adev->flags & AMD_IS_APU) |
907 | chansize = 64; | |
908 | else | |
909 | chansize = 128; | |
8d6a5230 | 910 | |
070706c0 | 911 | numchan = adev->df_funcs->get_hbm_channel_number(adev); |
770d13b1 | 912 | adev->gmc.vram_width = numchan * chansize; |
e60f8db5 | 913 | } |
e60f8db5 | 914 | |
e60f8db5 | 915 | /* size in MB on si */ |
770d13b1 | 916 | adev->gmc.mc_vram_size = |
bf383fb6 | 917 | adev->nbio_funcs->get_memsize(adev) * 1024ULL * 1024ULL; |
770d13b1 | 918 | adev->gmc.real_vram_size = adev->gmc.mc_vram_size; |
d6895ad3 CK |
919 | |
920 | if (!(adev->flags & AMD_IS_APU)) { | |
921 | r = amdgpu_device_resize_fb_bar(adev); | |
922 | if (r) | |
923 | return r; | |
924 | } | |
770d13b1 CK |
925 | adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); |
926 | adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); | |
e60f8db5 | 927 | |
156a81be CZ |
928 | #ifdef CONFIG_X86_64 |
929 | if (adev->flags & AMD_IS_APU) { | |
930 | adev->gmc.aper_base = gfxhub_v1_0_get_mc_fb_offset(adev); | |
931 | adev->gmc.aper_size = adev->gmc.real_vram_size; | |
932 | } | |
933 | #endif | |
e60f8db5 | 934 | /* In case the PCI BAR is larger than the actual amount of vram */ |
770d13b1 CK |
935 | adev->gmc.visible_vram_size = adev->gmc.aper_size; |
936 | if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) | |
937 | adev->gmc.visible_vram_size = adev->gmc.real_vram_size; | |
e60f8db5 | 938 | |
c3db7b5a AD |
939 | /* set the gart size */ |
940 | if (amdgpu_gart_size == -1) { | |
941 | switch (adev->asic_type) { | |
942 | case CHIP_VEGA10: /* all engines support GPUVM */ | |
273a14cd | 943 | case CHIP_VEGA12: /* all engines support GPUVM */ |
d96b428c | 944 | case CHIP_VEGA20: |
3de2ff5d | 945 | case CHIP_ARCTURUS: |
c3db7b5a | 946 | default: |
fe19b862 | 947 | adev->gmc.gart_size = 512ULL << 20; |
c3db7b5a AD |
948 | break; |
949 | case CHIP_RAVEN: /* DCE SG support */ | |
770d13b1 | 950 | adev->gmc.gart_size = 1024ULL << 20; |
c3db7b5a AD |
951 | break; |
952 | } | |
953 | } else { | |
770d13b1 | 954 | adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; |
c3db7b5a AD |
955 | } |
956 | ||
770d13b1 | 957 | gmc_v9_0_vram_gtt_location(adev, &adev->gmc); |
e60f8db5 AX |
958 | |
959 | return 0; | |
960 | } | |
961 | ||
962 | static int gmc_v9_0_gart_init(struct amdgpu_device *adev) | |
963 | { | |
964 | int r; | |
965 | ||
1123b989 | 966 | if (adev->gart.bo) { |
e60f8db5 AX |
967 | WARN(1, "VEGA10 PCIE GART already initialized\n"); |
968 | return 0; | |
969 | } | |
970 | /* Initialize common gart structure */ | |
971 | r = amdgpu_gart_init(adev); | |
972 | if (r) | |
973 | return r; | |
974 | adev->gart.table_size = adev->gart.num_gpu_pages * 8; | |
7596ab68 | 975 | adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(MTYPE_UC) | |
e60f8db5 AX |
976 | AMDGPU_PTE_EXECUTABLE; |
977 | return amdgpu_gart_table_vram_alloc(adev); | |
978 | } | |
979 | ||
ebdef28e AD |
980 | static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev) |
981 | { | |
bfa3a9bb | 982 | u32 d1vga_control; |
ebdef28e AD |
983 | unsigned size; |
984 | ||
6f752ec2 AG |
985 | /* |
986 | * TODO Remove once GART corruption is resolved | |
987 | * Check related code in gmc_v9_0_sw_fini | |
988 | * */ | |
cd2b5623 AD |
989 | if (gmc_v9_0_keep_stolen_memory(adev)) |
990 | return 9 * 1024 * 1024; | |
6f752ec2 | 991 | |
bfa3a9bb | 992 | d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); |
ebdef28e AD |
993 | if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { |
994 | size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */ | |
995 | } else { | |
996 | u32 viewport; | |
997 | ||
998 | switch (adev->asic_type) { | |
999 | case CHIP_RAVEN: | |
1000 | viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); | |
1001 | size = (REG_GET_FIELD(viewport, | |
1002 | HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * | |
1003 | REG_GET_FIELD(viewport, | |
1004 | HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * | |
1005 | 4); | |
1006 | break; | |
1007 | case CHIP_VEGA10: | |
1008 | case CHIP_VEGA12: | |
cd2b5623 | 1009 | case CHIP_VEGA20: |
ebdef28e AD |
1010 | default: |
1011 | viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE); | |
1012 | size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) * | |
1013 | REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) * | |
1014 | 4); | |
1015 | break; | |
1016 | } | |
1017 | } | |
1018 | /* return 0 if the pre-OS buffer uses up most of vram */ | |
1019 | if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) | |
1020 | return 0; | |
6f752ec2 | 1021 | |
ebdef28e AD |
1022 | return size; |
1023 | } | |
1024 | ||
e60f8db5 AX |
1025 | static int gmc_v9_0_sw_init(void *handle) |
1026 | { | |
1027 | int r; | |
1028 | int dma_bits; | |
1029 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1030 | ||
0c8c0847 | 1031 | gfxhub_v1_0_init(adev); |
51cce480 LM |
1032 | if (adev->asic_type == CHIP_ARCTURUS) |
1033 | mmhub_v9_4_init(adev); | |
1034 | else | |
1035 | mmhub_v1_0_init(adev); | |
0c8c0847 | 1036 | |
770d13b1 | 1037 | spin_lock_init(&adev->gmc.invalidate_lock); |
e60f8db5 | 1038 | |
1e09b053 | 1039 | adev->gmc.vram_type = amdgpu_atomfirmware_get_vram_type(adev); |
fd66560b HZ |
1040 | switch (adev->asic_type) { |
1041 | case CHIP_RAVEN: | |
1daa2bfa LM |
1042 | adev->num_vmhubs = 2; |
1043 | ||
6a42fd6f | 1044 | if (adev->rev_id == 0x0 || adev->rev_id == 0x1) { |
f3368128 | 1045 | amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); |
6a42fd6f CK |
1046 | } else { |
1047 | /* vm_size is 128TB + 512GB for legacy 3-level page support */ | |
1048 | amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48); | |
770d13b1 | 1049 | adev->gmc.translate_further = |
6a42fd6f CK |
1050 | adev->vm_manager.num_level > 1; |
1051 | } | |
fd66560b HZ |
1052 | break; |
1053 | case CHIP_VEGA10: | |
273a14cd | 1054 | case CHIP_VEGA12: |
d96b428c | 1055 | case CHIP_VEGA20: |
1daa2bfa LM |
1056 | adev->num_vmhubs = 2; |
1057 | ||
36b32a68 ZJ |
1058 | /* |
1059 | * To fulfill 4-level page support, | |
1060 | * vm size is 256TB (48bit), maximum size of Vega10, | |
1061 | * block size 512 (9bit) | |
1062 | */ | |
cdba61da | 1063 | /* sriov restrict max_pfn below AMDGPU_GMC_HOLE */ |
1064 | if (amdgpu_sriov_vf(adev)) | |
1065 | amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 47); | |
1066 | else | |
1067 | amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); | |
fd66560b | 1068 | break; |
3de2ff5d | 1069 | case CHIP_ARCTURUS: |
c8a6e2a3 LM |
1070 | adev->num_vmhubs = 3; |
1071 | ||
3de2ff5d LM |
1072 | /* Keep the vm size same with Vega20 */ |
1073 | amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); | |
1074 | break; | |
fd66560b HZ |
1075 | default: |
1076 | break; | |
e60f8db5 AX |
1077 | } |
1078 | ||
1079 | /* This interrupt is VMC page fault.*/ | |
44a99b65 | 1080 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT, |
770d13b1 | 1081 | &adev->gmc.vm_fault); |
30da7bb1 CK |
1082 | if (r) |
1083 | return r; | |
1084 | ||
7d19b15f LM |
1085 | if (adev->asic_type == CHIP_ARCTURUS) { |
1086 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT, | |
1087 | &adev->gmc.vm_fault); | |
1088 | if (r) | |
1089 | return r; | |
1090 | } | |
1091 | ||
44a99b65 | 1092 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT, |
770d13b1 | 1093 | &adev->gmc.vm_fault); |
e60f8db5 AX |
1094 | |
1095 | if (r) | |
1096 | return r; | |
1097 | ||
791c4769 | 1098 | /* interrupt sent to DF. */ |
1099 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0, | |
1100 | &adev->gmc.ecc_irq); | |
1101 | if (r) | |
1102 | return r; | |
1103 | ||
e60f8db5 AX |
1104 | /* Set the internal MC address mask |
1105 | * This is the max address of the GPU's | |
1106 | * internal address space. | |
1107 | */ | |
770d13b1 | 1108 | adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ |
e60f8db5 AX |
1109 | |
1110 | /* set DMA mask + need_dma32 flags. | |
1111 | * PCIE - can handle 44-bits. | |
1112 | * IGP - can handle 44-bits | |
1113 | * PCI - dma32 for legacy pci gart, 44 bits on vega10 | |
1114 | */ | |
1115 | adev->need_dma32 = false; | |
1116 | dma_bits = adev->need_dma32 ? 32 : 44; | |
1117 | r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); | |
1118 | if (r) { | |
1119 | adev->need_dma32 = true; | |
1120 | dma_bits = 32; | |
1121 | printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); | |
1122 | } | |
1123 | r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); | |
1124 | if (r) { | |
1125 | pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32)); | |
1126 | printk(KERN_WARNING "amdgpu: No coherent DMA available.\n"); | |
1127 | } | |
913b2cb7 | 1128 | adev->need_swiotlb = drm_need_swiotlb(dma_bits); |
e60f8db5 | 1129 | |
47622ba0 | 1130 | if (adev->gmc.xgmi.supported) { |
bf0a60b7 AD |
1131 | r = gfxhub_v1_1_get_xgmi_info(adev); |
1132 | if (r) | |
1133 | return r; | |
1134 | } | |
1135 | ||
e60f8db5 AX |
1136 | r = gmc_v9_0_mc_init(adev); |
1137 | if (r) | |
1138 | return r; | |
1139 | ||
ebdef28e AD |
1140 | adev->gmc.stolen_size = gmc_v9_0_get_vbios_fb_size(adev); |
1141 | ||
e60f8db5 AX |
1142 | /* Memory manager */ |
1143 | r = amdgpu_bo_init(adev); | |
1144 | if (r) | |
1145 | return r; | |
1146 | ||
1147 | r = gmc_v9_0_gart_init(adev); | |
1148 | if (r) | |
1149 | return r; | |
1150 | ||
05ec3eda CK |
1151 | /* |
1152 | * number of VMs | |
1153 | * VMID 0 is reserved for System | |
1154 | * amdgpu graphics/compute will use VMIDs 1-7 | |
1155 | * amdkfd will use VMIDs 8-15 | |
1156 | */ | |
a2d15ed7 LM |
1157 | adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS; |
1158 | adev->vm_manager.id_mgr[AMDGPU_MMHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS; | |
c8a6e2a3 | 1159 | adev->vm_manager.id_mgr[AMDGPU_MMHUB_1].num_ids = AMDGPU_NUM_OF_VMIDS; |
05ec3eda | 1160 | |
05ec3eda CK |
1161 | amdgpu_vm_manager_init(adev); |
1162 | ||
1163 | return 0; | |
e60f8db5 AX |
1164 | } |
1165 | ||
e60f8db5 AX |
1166 | static int gmc_v9_0_sw_fini(void *handle) |
1167 | { | |
1168 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1169 | ||
791c4769 | 1170 | if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC) && |
1171 | adev->gmc.ras_if) { | |
1172 | struct ras_common_if *ras_if = adev->gmc.ras_if; | |
1173 | struct ras_ih_if ih_info = { | |
1174 | .head = *ras_if, | |
1175 | }; | |
1176 | ||
1177 | /*remove fs first*/ | |
1178 | amdgpu_ras_debugfs_remove(adev, ras_if); | |
1179 | amdgpu_ras_sysfs_remove(adev, ras_if); | |
1180 | /*remove the IH*/ | |
1181 | amdgpu_ras_interrupt_remove_handler(adev, &ih_info); | |
1182 | amdgpu_ras_feature_enable(adev, ras_if, 0); | |
1183 | kfree(ras_if); | |
1184 | } | |
1185 | ||
f59548c8 | 1186 | amdgpu_gem_force_release(adev); |
05ec3eda | 1187 | amdgpu_vm_manager_fini(adev); |
6f752ec2 | 1188 | |
cd2b5623 AD |
1189 | if (gmc_v9_0_keep_stolen_memory(adev)) |
1190 | amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, NULL); | |
6f752ec2 | 1191 | |
a3d9103e | 1192 | amdgpu_gart_table_vram_free(adev); |
e60f8db5 | 1193 | amdgpu_bo_fini(adev); |
a3d9103e | 1194 | amdgpu_gart_fini(adev); |
e60f8db5 AX |
1195 | |
1196 | return 0; | |
1197 | } | |
1198 | ||
1199 | static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) | |
1200 | { | |
946a4d5b | 1201 | |
e60f8db5 AX |
1202 | switch (adev->asic_type) { |
1203 | case CHIP_VEGA10: | |
98cad2de TH |
1204 | if (amdgpu_virt_support_skip_setting(adev)) |
1205 | break; | |
1206 | /* fall through */ | |
d96b428c | 1207 | case CHIP_VEGA20: |
946a4d5b | 1208 | soc15_program_register_sequence(adev, |
5c583018 | 1209 | golden_settings_mmhub_1_0_0, |
c47b41a7 | 1210 | ARRAY_SIZE(golden_settings_mmhub_1_0_0)); |
946a4d5b | 1211 | soc15_program_register_sequence(adev, |
5c583018 | 1212 | golden_settings_athub_1_0_0, |
c47b41a7 | 1213 | ARRAY_SIZE(golden_settings_athub_1_0_0)); |
e60f8db5 | 1214 | break; |
273a14cd AD |
1215 | case CHIP_VEGA12: |
1216 | break; | |
e4f3abaa | 1217 | case CHIP_RAVEN: |
946a4d5b | 1218 | soc15_program_register_sequence(adev, |
5c583018 | 1219 | golden_settings_athub_1_0_0, |
c47b41a7 | 1220 | ARRAY_SIZE(golden_settings_athub_1_0_0)); |
e4f3abaa | 1221 | break; |
e60f8db5 AX |
1222 | default: |
1223 | break; | |
1224 | } | |
1225 | } | |
1226 | ||
1227 | /** | |
1228 | * gmc_v9_0_gart_enable - gart enable | |
1229 | * | |
1230 | * @adev: amdgpu_device pointer | |
1231 | */ | |
1232 | static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) | |
1233 | { | |
1234 | int r; | |
1235 | bool value; | |
1236 | u32 tmp; | |
1237 | ||
9c3f2b54 AD |
1238 | amdgpu_device_program_register_sequence(adev, |
1239 | golden_settings_vega10_hdp, | |
1240 | ARRAY_SIZE(golden_settings_vega10_hdp)); | |
e60f8db5 | 1241 | |
1123b989 | 1242 | if (adev->gart.bo == NULL) { |
e60f8db5 AX |
1243 | dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); |
1244 | return -EINVAL; | |
1245 | } | |
ce1b1b66 ML |
1246 | r = amdgpu_gart_table_vram_pin(adev); |
1247 | if (r) | |
1248 | return r; | |
e60f8db5 | 1249 | |
2fcd43ce HZ |
1250 | switch (adev->asic_type) { |
1251 | case CHIP_RAVEN: | |
f8386b35 | 1252 | mmhub_v1_0_update_power_gating(adev, true); |
2fcd43ce HZ |
1253 | break; |
1254 | default: | |
1255 | break; | |
1256 | } | |
1257 | ||
e60f8db5 AX |
1258 | r = gfxhub_v1_0_gart_enable(adev); |
1259 | if (r) | |
1260 | return r; | |
1261 | ||
51cce480 LM |
1262 | if (adev->asic_type == CHIP_ARCTURUS) |
1263 | r = mmhub_v9_4_gart_enable(adev); | |
1264 | else | |
1265 | r = mmhub_v1_0_gart_enable(adev); | |
e60f8db5 AX |
1266 | if (r) |
1267 | return r; | |
1268 | ||
846347c9 | 1269 | WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1); |
e60f8db5 | 1270 | |
b9509c80 HR |
1271 | tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL); |
1272 | WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp); | |
e60f8db5 | 1273 | |
fe2b5323 TZ |
1274 | WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8)); |
1275 | WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40)); | |
1276 | ||
1d4e0a8c | 1277 | /* After HDP is initialized, flush HDP.*/ |
69882565 | 1278 | adev->nbio_funcs->hdp_flush(adev, NULL); |
1d4e0a8c | 1279 | |
e60f8db5 AX |
1280 | if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) |
1281 | value = false; | |
1282 | else | |
1283 | value = true; | |
1284 | ||
1285 | gfxhub_v1_0_set_fault_enable_default(adev, value); | |
51cce480 LM |
1286 | if (adev->asic_type == CHIP_ARCTURUS) |
1287 | mmhub_v9_4_set_fault_enable_default(adev, value); | |
1288 | else | |
1289 | mmhub_v1_0_set_fault_enable_default(adev, value); | |
2a79d868 | 1290 | gmc_v9_0_flush_gpu_tlb(adev, 0, 0); |
e60f8db5 AX |
1291 | |
1292 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", | |
770d13b1 | 1293 | (unsigned)(adev->gmc.gart_size >> 20), |
4e830fb1 | 1294 | (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); |
e60f8db5 AX |
1295 | adev->gart.ready = true; |
1296 | return 0; | |
1297 | } | |
1298 | ||
1299 | static int gmc_v9_0_hw_init(void *handle) | |
1300 | { | |
1301 | int r; | |
1302 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1303 | ||
1304 | /* The sequence of these two function calls matters.*/ | |
1305 | gmc_v9_0_init_golden_registers(adev); | |
1306 | ||
edca2d05 | 1307 | if (adev->mode_info.num_crtc) { |
edca2d05 | 1308 | /* Lockout access through VGA aperture*/ |
4d9c333a | 1309 | WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); |
edca2d05 AD |
1310 | |
1311 | /* disable VGA render */ | |
4d9c333a | 1312 | WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); |
edca2d05 AD |
1313 | } |
1314 | ||
e60f8db5 AX |
1315 | r = gmc_v9_0_gart_enable(adev); |
1316 | ||
1317 | return r; | |
1318 | } | |
1319 | ||
1320 | /** | |
1321 | * gmc_v9_0_gart_disable - gart disable | |
1322 | * | |
1323 | * @adev: amdgpu_device pointer | |
1324 | * | |
1325 | * This disables all VM page table. | |
1326 | */ | |
1327 | static void gmc_v9_0_gart_disable(struct amdgpu_device *adev) | |
1328 | { | |
1329 | gfxhub_v1_0_gart_disable(adev); | |
51cce480 LM |
1330 | if (adev->asic_type == CHIP_ARCTURUS) |
1331 | mmhub_v9_4_gart_disable(adev); | |
1332 | else | |
1333 | mmhub_v1_0_gart_disable(adev); | |
ce1b1b66 | 1334 | amdgpu_gart_table_vram_unpin(adev); |
e60f8db5 AX |
1335 | } |
1336 | ||
1337 | static int gmc_v9_0_hw_fini(void *handle) | |
1338 | { | |
1339 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1340 | ||
5dd696ae TH |
1341 | if (amdgpu_sriov_vf(adev)) { |
1342 | /* full access mode, so don't touch any GMC register */ | |
1343 | DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); | |
1344 | return 0; | |
1345 | } | |
1346 | ||
791c4769 | 1347 | amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); |
770d13b1 | 1348 | amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); |
e60f8db5 AX |
1349 | gmc_v9_0_gart_disable(adev); |
1350 | ||
1351 | return 0; | |
1352 | } | |
1353 | ||
1354 | static int gmc_v9_0_suspend(void *handle) | |
1355 | { | |
1356 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1357 | ||
f053cd47 | 1358 | return gmc_v9_0_hw_fini(adev); |
e60f8db5 AX |
1359 | } |
1360 | ||
1361 | static int gmc_v9_0_resume(void *handle) | |
1362 | { | |
1363 | int r; | |
1364 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1365 | ||
1366 | r = gmc_v9_0_hw_init(adev); | |
1367 | if (r) | |
1368 | return r; | |
1369 | ||
620f774f | 1370 | amdgpu_vmid_reset_all(adev); |
e60f8db5 | 1371 | |
32601d48 | 1372 | return 0; |
e60f8db5 AX |
1373 | } |
1374 | ||
1375 | static bool gmc_v9_0_is_idle(void *handle) | |
1376 | { | |
1377 | /* MC is always ready in GMC v9.*/ | |
1378 | return true; | |
1379 | } | |
1380 | ||
1381 | static int gmc_v9_0_wait_for_idle(void *handle) | |
1382 | { | |
1383 | /* There is no need to wait for MC idle in GMC v9.*/ | |
1384 | return 0; | |
1385 | } | |
1386 | ||
1387 | static int gmc_v9_0_soft_reset(void *handle) | |
1388 | { | |
1389 | /* XXX for emulation.*/ | |
1390 | return 0; | |
1391 | } | |
1392 | ||
1393 | static int gmc_v9_0_set_clockgating_state(void *handle, | |
1394 | enum amd_clockgating_state state) | |
1395 | { | |
d5583d4f HR |
1396 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1397 | ||
51cce480 LM |
1398 | if (adev->asic_type == CHIP_ARCTURUS) |
1399 | return 0; | |
1400 | ||
d5583d4f | 1401 | return mmhub_v1_0_set_clockgating(adev, state); |
e60f8db5 AX |
1402 | } |
1403 | ||
13052be5 HR |
1404 | static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags) |
1405 | { | |
1406 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1407 | ||
51cce480 LM |
1408 | if (adev->asic_type == CHIP_ARCTURUS) |
1409 | return; | |
1410 | ||
13052be5 HR |
1411 | mmhub_v1_0_get_clockgating(adev, flags); |
1412 | } | |
1413 | ||
e60f8db5 AX |
1414 | static int gmc_v9_0_set_powergating_state(void *handle, |
1415 | enum amd_powergating_state state) | |
1416 | { | |
1417 | return 0; | |
1418 | } | |
1419 | ||
1420 | const struct amd_ip_funcs gmc_v9_0_ip_funcs = { | |
1421 | .name = "gmc_v9_0", | |
1422 | .early_init = gmc_v9_0_early_init, | |
1423 | .late_init = gmc_v9_0_late_init, | |
1424 | .sw_init = gmc_v9_0_sw_init, | |
1425 | .sw_fini = gmc_v9_0_sw_fini, | |
1426 | .hw_init = gmc_v9_0_hw_init, | |
1427 | .hw_fini = gmc_v9_0_hw_fini, | |
1428 | .suspend = gmc_v9_0_suspend, | |
1429 | .resume = gmc_v9_0_resume, | |
1430 | .is_idle = gmc_v9_0_is_idle, | |
1431 | .wait_for_idle = gmc_v9_0_wait_for_idle, | |
1432 | .soft_reset = gmc_v9_0_soft_reset, | |
1433 | .set_clockgating_state = gmc_v9_0_set_clockgating_state, | |
1434 | .set_powergating_state = gmc_v9_0_set_powergating_state, | |
13052be5 | 1435 | .get_clockgating_state = gmc_v9_0_get_clockgating_state, |
e60f8db5 AX |
1436 | }; |
1437 | ||
1438 | const struct amdgpu_ip_block_version gmc_v9_0_ip_block = | |
1439 | { | |
1440 | .type = AMD_IP_BLOCK_TYPE_GMC, | |
1441 | .major = 9, | |
1442 | .minor = 0, | |
1443 | .rev = 0, | |
1444 | .funcs = &gmc_v9_0_ip_funcs, | |
1445 | }; |