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[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / amd / amdgpu / gmc_v9_0.c
CommitLineData
e60f8db5
AX		 1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
fd5fd480 24#include <drm/drm_cache.h>
e60f8db5
AX		 25#include "amdgpu.h"
26#include "gmc_v9_0.h"
8d6a5230 27#include "amdgpu_atomfirmware.h"
e60f8db5 28
75199b8c
FX		 29#include "hdp/hdp_4_0_offset.h"
30#include "hdp/hdp_4_0_sh_mask.h"
cde5c34f 31#include "gc/gc_9_0_sh_mask.h"
135d4b10
FX		 32#include "dce/dce_12_0_offset.h"
33#include "dce/dce_12_0_sh_mask.h"
fb960bd2 34#include "vega10_enum.h"
65417d9f 35#include "mmhub/mmhub_1_0_offset.h"
6ce68225 36#include "athub/athub_1_0_offset.h"
e60f8db5 37
946a4d5b 38#include "soc15.h"
e60f8db5 39#include "soc15_common.h"
90c7a935 40#include "umc/umc_6_0_sh_mask.h"
e60f8db5 41
e60f8db5
AX		 42#include "gfxhub_v1_0.h"
43#include "mmhub_v1_0.h"
44
45#define mmDF_CS_AON0_DramBaseAddress0 0x0044
46#define mmDF_CS_AON0_DramBaseAddress0_BASE_IDX 0
47//DF_CS_AON0_DramBaseAddress0
48#define DF_CS_AON0_DramBaseAddress0__AddrRngVal__SHIFT 0x0
49#define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT 0x1
50#define DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT 0x4
51#define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT 0x8
52#define DF_CS_AON0_DramBaseAddress0__DramBaseAddr__SHIFT 0xc
53#define DF_CS_AON0_DramBaseAddress0__AddrRngVal_MASK 0x00000001L
54#define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK 0x00000002L
55#define DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK 0x000000F0L
56#define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK 0x00000700L
57#define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK 0xFFFFF000L
58
59/* XXX Move this macro to VEGA10 header file, which is like vid.h for VI.*/
60#define AMDGPU_NUM_OF_VMIDS 8
61
62static const u32 golden_settings_vega10_hdp[] =
63{
64 0xf64, 0x0fffffff, 0x00000000,
65 0xf65, 0x0fffffff, 0x00000000,
66 0xf66, 0x0fffffff, 0x00000000,
67 0xf67, 0x0fffffff, 0x00000000,
68 0xf68, 0x0fffffff, 0x00000000,
69 0xf6a, 0x0fffffff, 0x00000000,
70 0xf6b, 0x0fffffff, 0x00000000,
71 0xf6c, 0x0fffffff, 0x00000000,
72 0xf6d, 0x0fffffff, 0x00000000,
73 0xf6e, 0x0fffffff, 0x00000000,
74};
75
946a4d5b 76static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] =
5c583018 77{
946a4d5b
SL		 78 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa),
79 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565)
5c583018
EQ		 80};
81
946a4d5b 82static const struct soc15_reg_golden golden_settings_athub_1_0_0[] =
5c583018 83{
946a4d5b
SL		 84 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800),
85 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008)
5c583018
EQ		 86};
87
02bab923
DP		 88/* Ecc related register addresses, (BASE + reg offset) */
89/* Universal Memory Controller caps (may be fused). */
90/* UMCCH:UmcLocalCap */
91#define UMCLOCALCAPS_ADDR0 (0x00014306 + 0x00000000)
92#define UMCLOCALCAPS_ADDR1 (0x00014306 + 0x00000800)
93#define UMCLOCALCAPS_ADDR2 (0x00014306 + 0x00001000)
94#define UMCLOCALCAPS_ADDR3 (0x00014306 + 0x00001800)
95#define UMCLOCALCAPS_ADDR4 (0x00054306 + 0x00000000)
96#define UMCLOCALCAPS_ADDR5 (0x00054306 + 0x00000800)
97#define UMCLOCALCAPS_ADDR6 (0x00054306 + 0x00001000)
98#define UMCLOCALCAPS_ADDR7 (0x00054306 + 0x00001800)
99#define UMCLOCALCAPS_ADDR8 (0x00094306 + 0x00000000)
100#define UMCLOCALCAPS_ADDR9 (0x00094306 + 0x00000800)
101#define UMCLOCALCAPS_ADDR10 (0x00094306 + 0x00001000)
102#define UMCLOCALCAPS_ADDR11 (0x00094306 + 0x00001800)
103#define UMCLOCALCAPS_ADDR12 (0x000d4306 + 0x00000000)
104#define UMCLOCALCAPS_ADDR13 (0x000d4306 + 0x00000800)
105#define UMCLOCALCAPS_ADDR14 (0x000d4306 + 0x00001000)
106#define UMCLOCALCAPS_ADDR15 (0x000d4306 + 0x00001800)
107
108/* Universal Memory Controller Channel config. */
109/* UMCCH:UMC_CONFIG */
110#define UMCCH_UMC_CONFIG_ADDR0 (0x00014040 + 0x00000000)
111#define UMCCH_UMC_CONFIG_ADDR1 (0x00014040 + 0x00000800)
112#define UMCCH_UMC_CONFIG_ADDR2 (0x00014040 + 0x00001000)
113#define UMCCH_UMC_CONFIG_ADDR3 (0x00014040 + 0x00001800)
114#define UMCCH_UMC_CONFIG_ADDR4 (0x00054040 + 0x00000000)
115#define UMCCH_UMC_CONFIG_ADDR5 (0x00054040 + 0x00000800)
116#define UMCCH_UMC_CONFIG_ADDR6 (0x00054040 + 0x00001000)
117#define UMCCH_UMC_CONFIG_ADDR7 (0x00054040 + 0x00001800)
118#define UMCCH_UMC_CONFIG_ADDR8 (0x00094040 + 0x00000000)
119#define UMCCH_UMC_CONFIG_ADDR9 (0x00094040 + 0x00000800)
120#define UMCCH_UMC_CONFIG_ADDR10 (0x00094040 + 0x00001000)
121#define UMCCH_UMC_CONFIG_ADDR11 (0x00094040 + 0x00001800)
122#define UMCCH_UMC_CONFIG_ADDR12 (0x000d4040 + 0x00000000)
123#define UMCCH_UMC_CONFIG_ADDR13 (0x000d4040 + 0x00000800)
124#define UMCCH_UMC_CONFIG_ADDR14 (0x000d4040 + 0x00001000)
125#define UMCCH_UMC_CONFIG_ADDR15 (0x000d4040 + 0x00001800)
126
127/* Universal Memory Controller Channel Ecc config. */
128/* UMCCH:EccCtrl */
129#define UMCCH_ECCCTRL_ADDR0 (0x00014053 + 0x00000000)
130#define UMCCH_ECCCTRL_ADDR1 (0x00014053 + 0x00000800)
131#define UMCCH_ECCCTRL_ADDR2 (0x00014053 + 0x00001000)
132#define UMCCH_ECCCTRL_ADDR3 (0x00014053 + 0x00001800)
133#define UMCCH_ECCCTRL_ADDR4 (0x00054053 + 0x00000000)
134#define UMCCH_ECCCTRL_ADDR5 (0x00054053 + 0x00000800)
135#define UMCCH_ECCCTRL_ADDR6 (0x00054053 + 0x00001000)
136#define UMCCH_ECCCTRL_ADDR7 (0x00054053 + 0x00001800)
137#define UMCCH_ECCCTRL_ADDR8 (0x00094053 + 0x00000000)
138#define UMCCH_ECCCTRL_ADDR9 (0x00094053 + 0x00000800)
139#define UMCCH_ECCCTRL_ADDR10 (0x00094053 + 0x00001000)
140#define UMCCH_ECCCTRL_ADDR11 (0x00094053 + 0x00001800)
141#define UMCCH_ECCCTRL_ADDR12 (0x000d4053 + 0x00000000)
142#define UMCCH_ECCCTRL_ADDR13 (0x000d4053 + 0x00000800)
143#define UMCCH_ECCCTRL_ADDR14 (0x000d4053 + 0x00001000)
144#define UMCCH_ECCCTRL_ADDR15 (0x000d4053 + 0x00001800)
145
146static const uint32_t ecc_umclocalcap_addrs[] = {
147 UMCLOCALCAPS_ADDR0,
148 UMCLOCALCAPS_ADDR1,
149 UMCLOCALCAPS_ADDR2,
150 UMCLOCALCAPS_ADDR3,
151 UMCLOCALCAPS_ADDR4,
152 UMCLOCALCAPS_ADDR5,
153 UMCLOCALCAPS_ADDR6,
154 UMCLOCALCAPS_ADDR7,
155 UMCLOCALCAPS_ADDR8,
156 UMCLOCALCAPS_ADDR9,
157 UMCLOCALCAPS_ADDR10,
158 UMCLOCALCAPS_ADDR11,
159 UMCLOCALCAPS_ADDR12,
160 UMCLOCALCAPS_ADDR13,
161 UMCLOCALCAPS_ADDR14,
162 UMCLOCALCAPS_ADDR15,
163};
164
165static const uint32_t ecc_umcch_umc_config_addrs[] = {
166 UMCCH_UMC_CONFIG_ADDR0,
167 UMCCH_UMC_CONFIG_ADDR1,
168 UMCCH_UMC_CONFIG_ADDR2,
169 UMCCH_UMC_CONFIG_ADDR3,
170 UMCCH_UMC_CONFIG_ADDR4,
171 UMCCH_UMC_CONFIG_ADDR5,
172 UMCCH_UMC_CONFIG_ADDR6,
173 UMCCH_UMC_CONFIG_ADDR7,
174 UMCCH_UMC_CONFIG_ADDR8,
175 UMCCH_UMC_CONFIG_ADDR9,
176 UMCCH_UMC_CONFIG_ADDR10,
177 UMCCH_UMC_CONFIG_ADDR11,
178 UMCCH_UMC_CONFIG_ADDR12,
179 UMCCH_UMC_CONFIG_ADDR13,
180 UMCCH_UMC_CONFIG_ADDR14,
181 UMCCH_UMC_CONFIG_ADDR15,
182};
183
184static const uint32_t ecc_umcch_eccctrl_addrs[] = {
185 UMCCH_ECCCTRL_ADDR0,
186 UMCCH_ECCCTRL_ADDR1,
187 UMCCH_ECCCTRL_ADDR2,
188 UMCCH_ECCCTRL_ADDR3,
189 UMCCH_ECCCTRL_ADDR4,
190 UMCCH_ECCCTRL_ADDR5,
191 UMCCH_ECCCTRL_ADDR6,
192 UMCCH_ECCCTRL_ADDR7,
193 UMCCH_ECCCTRL_ADDR8,
194 UMCCH_ECCCTRL_ADDR9,
195 UMCCH_ECCCTRL_ADDR10,
196 UMCCH_ECCCTRL_ADDR11,
197 UMCCH_ECCCTRL_ADDR12,
198 UMCCH_ECCCTRL_ADDR13,
199 UMCCH_ECCCTRL_ADDR14,
200 UMCCH_ECCCTRL_ADDR15,
201};
202
e60f8db5
AX		 203static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
204 struct amdgpu_irq_src *src,
205 unsigned type,
206 enum amdgpu_interrupt_state state)
207{
208 struct amdgpu_vmhub *hub;
ae6d1416 209 u32 tmp, reg, bits, i, j;
e60f8db5 210
11250164
CK		 211 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
212 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
213 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
214 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
215 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
216 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
217 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
218
e60f8db5
AX		 219 switch (state) {
220 case AMDGPU_IRQ_STATE_DISABLE:
ae6d1416
TSD		 221 for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) {
222 hub = &adev->vmhub[j];
223 for (i = 0; i < 16; i++) {
224 reg = hub->vm_context0_cntl + i;
225 tmp = RREG32(reg);
226 tmp &= ~bits;
227 WREG32(reg, tmp);
228 }
e60f8db5
AX		 229 }
230 break;
231 case AMDGPU_IRQ_STATE_ENABLE:
ae6d1416
TSD		 232 for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) {
233 hub = &adev->vmhub[j];
234 for (i = 0; i < 16; i++) {
235 reg = hub->vm_context0_cntl + i;
236 tmp = RREG32(reg);
237 tmp |= bits;
238 WREG32(reg, tmp);
239 }
e60f8db5 240 }
e60f8db5
AX		 241 default:
242 break;
243 }
244
245 return 0;
246}
247
248static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
249 struct amdgpu_irq_src *source,
250 struct amdgpu_iv_entry *entry)
251{
c4f46f22 252 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src];
4d6cbde3 253 uint32_t status = 0;
e60f8db5
AX		 254 u64 addr;
255
256 addr = (u64)entry->src_data[0] << 12;
257 addr |= ((u64)entry->src_data[1] & 0xf) << 44;
258
79a0c465 259 if (!amdgpu_sriov_vf(adev)) {
5a9b8e8a
CK		 260 status = RREG32(hub->vm_l2_pro_fault_status);
261 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
4d6cbde3 262 }
e60f8db5 263
4d6cbde3
FK		 264 if (printk_ratelimit()) {
265 dev_err(adev->dev,
3816e42f 266 "[%s] VMC page fault (src_id:%u ring:%u vmid:%u pasid:%u)\n",
c4f46f22
CK		 267 entry->vmid_src ? "mmhub" : "gfxhub",
268 entry->src_id, entry->ring_id, entry->vmid,
3816e42f 269 entry->pasid);
4d6cbde3
FK		 270 dev_err(adev->dev, " at page 0x%016llx from %d\n",
271 addr, entry->client_id);
272 if (!amdgpu_sriov_vf(adev))
273 dev_err(adev->dev,
274 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
275 status);
79a0c465 276 }
e60f8db5
AX		 277
278 return 0;
279}
280
281static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = {
282 .set = gmc_v9_0_vm_fault_interrupt_state,
283 .process = gmc_v9_0_process_interrupt,
284};
285
286static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev)
287{
770d13b1
CK		 288 adev->gmc.vm_fault.num_types = 1;
289 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs;
e60f8db5
AX		 290}
291
c4f46f22 292static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid)
03f89feb
CK		 293{
294 u32 req = 0;
295
c4f46f22 296 /* invalidate using legacy mode on vmid*/
03f89feb 297 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
c4f46f22 298 PER_VMID_INVALIDATE_REQ, 1 << vmid);
03f89feb
CK		 299 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, 0);
300 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
301 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
302 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
303 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
304 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
305 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
306 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
307
308 return req;
309}
310
e60f8db5
AX		 311/*
312 * GART
313 * VMID 0 is the physical GPU addresses as used by the kernel.
314 * VMIDs 1-15 are used for userspace clients and are handled
315 * by the amdgpu vm/hsa code.
316 */
317
318/**
132f34e4 319 * gmc_v9_0_flush_gpu_tlb - gart tlb flush callback
e60f8db5
AX		 320 *
321 * @adev: amdgpu_device pointer
322 * @vmid: vm instance to flush
323 *
324 * Flush the TLB for the requested page table.
325 */
132f34e4 326static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev,
e60f8db5
AX		 327 uint32_t vmid)
328{
329 /* Use register 17 for GART */
330 const unsigned eng = 17;
331 unsigned i, j;
332
770d13b1 333 spin_lock(&adev->gmc.invalidate_lock);
e60f8db5
AX		 334
335 for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
336 struct amdgpu_vmhub *hub = &adev->vmhub[i];
03f89feb 337 u32 tmp = gmc_v9_0_get_invalidate_req(vmid);
e60f8db5 338
c7a7266b 339 WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);
e60f8db5
AX		 340
341 /* Busy wait for ACK.*/
342 for (j = 0; j < 100; j++) {
c7a7266b 343 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
e60f8db5
AX		 344 tmp &= 1 << vmid;
345 if (tmp)
346 break;
347 cpu_relax();
348 }
349 if (j < 100)
350 continue;
351
352 /* Wait for ACK with a delay.*/
353 for (j = 0; j < adev->usec_timeout; j++) {
c7a7266b 354 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
e60f8db5
AX		 355 tmp &= 1 << vmid;
356 if (tmp)
357 break;
358 udelay(1);
359 }
360 if (j < adev->usec_timeout)
361 continue;
362
363 DRM_ERROR("Timeout waiting for VM flush ACK!\n");
364 }
365
770d13b1 366 spin_unlock(&adev->gmc.invalidate_lock);
e60f8db5
AX		 367}
368
369/**
132f34e4 370 * gmc_v9_0_set_pte_pde - update the page tables using MMIO
e60f8db5
AX		 371 *
372 * @adev: amdgpu_device pointer
373 * @cpu_pt_addr: cpu address of the page table
374 * @gpu_page_idx: entry in the page table to update
375 * @addr: dst addr to write into pte/pde
376 * @flags: access flags
377 *
378 * Update the page tables using the CPU.
379 */
132f34e4
CK		 380static int gmc_v9_0_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr,
381 uint32_t gpu_page_idx, uint64_t addr,
382 uint64_t flags)
e60f8db5
AX		 383{
384 void __iomem *ptr = (void *)cpu_pt_addr;
385 uint64_t value;
386
387 /*
388 * PTE format on VEGA 10:
389 * 63:59 reserved
390 * 58:57 mtype
391 * 56 F
392 * 55 L
393 * 54 P
394 * 53 SW
395 * 52 T
396 * 50:48 reserved
397 * 47:12 4k physical page base address
398 * 11:7 fragment
399 * 6 write
400 * 5 read
401 * 4 exe
402 * 3 Z
403 * 2 snooped
404 * 1 system
405 * 0 valid
406 *
407 * PDE format on VEGA 10:
408 * 63:59 block fragment size
409 * 58:55 reserved
410 * 54 P
411 * 53:48 reserved
412 * 47:6 physical base address of PD or PTE
413 * 5:3 reserved
414 * 2 C
415 * 1 system
416 * 0 valid
417 */
418
419 /*
420 * The following is for PTE only. GART does not have PDEs.
421 */
422 value = addr & 0x0000FFFFFFFFF000ULL;
423 value |= flags;
424 writeq(value, ptr + (gpu_page_idx * 8));
425 return 0;
426}
427
428static uint64_t gmc_v9_0_get_vm_pte_flags(struct amdgpu_device *adev,
429 uint32_t flags)
430
431{
432 uint64_t pte_flag = 0;
433
434 if (flags & AMDGPU_VM_PAGE_EXECUTABLE)
435 pte_flag |= AMDGPU_PTE_EXECUTABLE;
436 if (flags & AMDGPU_VM_PAGE_READABLE)
437 pte_flag |= AMDGPU_PTE_READABLE;
438 if (flags & AMDGPU_VM_PAGE_WRITEABLE)
439 pte_flag |= AMDGPU_PTE_WRITEABLE;
440
441 switch (flags & AMDGPU_VM_MTYPE_MASK) {
442 case AMDGPU_VM_MTYPE_DEFAULT:
443 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
444 break;
445 case AMDGPU_VM_MTYPE_NC:
446 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
447 break;
448 case AMDGPU_VM_MTYPE_WC:
449 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_WC);
450 break;
451 case AMDGPU_VM_MTYPE_CC:
452 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_CC);
453 break;
454 case AMDGPU_VM_MTYPE_UC:
455 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_UC);
456 break;
457 default:
458 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
459 break;
460 }
461
462 if (flags & AMDGPU_VM_PAGE_PRT)
463 pte_flag |= AMDGPU_PTE_PRT;
464
465 return pte_flag;
466}
467
3de676d8
CK		 468static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
469 uint64_t *addr, uint64_t *flags)
e60f8db5 470{
3de676d8
CK		 471 if (!(*flags & AMDGPU_PDE_PTE))
472 *addr = adev->vm_manager.vram_base_offset + *addr -
770d13b1 473 adev->gmc.vram_start;
3de676d8 474 BUG_ON(*addr & 0xFFFF00000000003FULL);
6a42fd6f 475
770d13b1 476 if (!adev->gmc.translate_further)
6a42fd6f
CK		 477 return;
478
479 if (level == AMDGPU_VM_PDB1) {
480 /* Set the block fragment size */
481 if (!(*flags & AMDGPU_PDE_PTE))
482 *flags |= AMDGPU_PDE_BFS(0x9);
483
484 } else if (level == AMDGPU_VM_PDB0) {
485 if (*flags & AMDGPU_PDE_PTE)
486 *flags &= ~AMDGPU_PDE_PTE;
487 else
488 *flags |= AMDGPU_PTE_TF;
489 }
e60f8db5
AX		 490}
491
132f34e4
CK		 492static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = {
493 .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb,
494 .set_pte_pde = gmc_v9_0_set_pte_pde,
03f89feb 495 .get_invalidate_req = gmc_v9_0_get_invalidate_req,
b1166325
CK		 496 .get_vm_pte_flags = gmc_v9_0_get_vm_pte_flags,
497 .get_vm_pde = gmc_v9_0_get_vm_pde
e60f8db5
AX		 498};
499
132f34e4 500static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev)
e60f8db5 501{
132f34e4
CK		 502 if (adev->gmc.gmc_funcs == NULL)
503 adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs;
e60f8db5
AX		 504}
505
506static int gmc_v9_0_early_init(void *handle)
507{
508 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
509
132f34e4 510 gmc_v9_0_set_gmc_funcs(adev);
e60f8db5
AX		 511 gmc_v9_0_set_irq_funcs(adev);
512
770d13b1
CK		 513 adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
514 adev->gmc.shared_aperture_end =
515 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
516 adev->gmc.private_aperture_start =
517 adev->gmc.shared_aperture_end + 1;
518 adev->gmc.private_aperture_end =
519 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
a7ea6548 520
e60f8db5
AX		 521 return 0;
522}
523
02bab923
DP		 524static int gmc_v9_0_ecc_available(struct amdgpu_device *adev)
525{
526 uint32_t reg_val;
527 uint32_t reg_addr;
528 uint32_t field_val;
529 size_t i;
530 uint32_t fv2;
531 size_t lost_sheep;
532
533 DRM_DEBUG("ecc: gmc_v9_0_ecc_available()\n");
534
535 lost_sheep = 0;
536 for (i = 0; i < ARRAY_SIZE(ecc_umclocalcap_addrs); ++i) {
537 reg_addr = ecc_umclocalcap_addrs[i];
538 DRM_DEBUG("ecc: "
539 "UMCCH_UmcLocalCap[%zu]: reg_addr: 0x%08x\n",
540 i, reg_addr);
541 reg_val = RREG32(reg_addr);
542 field_val = REG_GET_FIELD(reg_val, UMCCH0_0_UmcLocalCap,
543 EccDis);
544 DRM_DEBUG("ecc: "
545 "reg_val: 0x%08x, "
546 "EccDis: 0x%08x, ",
547 reg_val, field_val);
548 if (field_val) {
549 DRM_ERROR("ecc: UmcLocalCap:EccDis is set.\n");
550 ++lost_sheep;
551 }
552 }
553
554 for (i = 0; i < ARRAY_SIZE(ecc_umcch_umc_config_addrs); ++i) {
555 reg_addr = ecc_umcch_umc_config_addrs[i];
556 DRM_DEBUG("ecc: "
557 "UMCCH0_0_UMC_CONFIG[%zu]: reg_addr: 0x%08x",
558 i, reg_addr);
559 reg_val = RREG32(reg_addr);
560 field_val = REG_GET_FIELD(reg_val, UMCCH0_0_UMC_CONFIG,
561 DramReady);
562 DRM_DEBUG("ecc: "
563 "reg_val: 0x%08x, "
564 "DramReady: 0x%08x\n",
565 reg_val, field_val);
566
567 if (!field_val) {
568 DRM_ERROR("ecc: UMC_CONFIG:DramReady is not set.\n");
569 ++lost_sheep;
570 }
571 }
572
573 for (i = 0; i < ARRAY_SIZE(ecc_umcch_eccctrl_addrs); ++i) {
574 reg_addr = ecc_umcch_eccctrl_addrs[i];
575 DRM_DEBUG("ecc: "
576 "UMCCH_EccCtrl[%zu]: reg_addr: 0x%08x, ",
577 i, reg_addr);
578 reg_val = RREG32(reg_addr);
579 field_val = REG_GET_FIELD(reg_val, UMCCH0_0_EccCtrl,
580 WrEccEn);
581 fv2 = REG_GET_FIELD(reg_val, UMCCH0_0_EccCtrl,
582 RdEccEn);
583 DRM_DEBUG("ecc: "
584 "reg_val: 0x%08x, "
585 "WrEccEn: 0x%08x, "
586 "RdEccEn: 0x%08x\n",
587 reg_val, field_val, fv2);
588
589 if (!field_val) {
5a16008f 590 DRM_DEBUG("ecc: WrEccEn is not set\n");
02bab923
DP		 591 ++lost_sheep;
592 }
593 if (!fv2) {
5a16008f 594 DRM_DEBUG("ecc: RdEccEn is not set\n");
02bab923
DP		 595 ++lost_sheep;
596 }
597 }
598
599 DRM_DEBUG("ecc: lost_sheep: %zu\n", lost_sheep);
600 return lost_sheep == 0;
601}
602
e60f8db5
AX		 603static int gmc_v9_0_late_init(void *handle)
604{
605 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
c5066129 606 /*
607 * The latest engine allocation on gfx9 is:
608 * Engine 0, 1: idle
609 * Engine 2, 3: firmware
610 * Engine 4~13: amdgpu ring, subject to change when ring number changes
611 * Engine 14~15: idle
612 * Engine 16: kfd tlb invalidation
613 * Engine 17: Gart flushes
614 */
615 unsigned vm_inv_eng[AMDGPU_MAX_VMHUBS] = { 4, 4 };
4789c463 616 unsigned i;
02bab923 617 int r;
4789c463
CK		 618
619 for(i = 0; i < adev->num_rings; ++i) {
620 struct amdgpu_ring *ring = adev->rings[i];
621 unsigned vmhub = ring->funcs->vmhub;
622
623 ring->vm_inv_eng = vm_inv_eng[vmhub]++;
775f55f1
TSD		 624 dev_info(adev->dev, "ring %u(%s) uses VM inv eng %u on hub %u\n",
625 ring->idx, ring->name, ring->vm_inv_eng,
626 ring->funcs->vmhub);
4789c463
CK		 627 }
628
c5066129 629 /* Engine 16 is used for KFD and 17 for GART flushes */
4789c463 630 for(i = 0; i < AMDGPU_MAX_VMHUBS; ++i)
c5066129 631 BUG_ON(vm_inv_eng[i] > 16);
4789c463 632
5ba4fa35
AD		 633 if (adev->asic_type == CHIP_VEGA10) {
634 r = gmc_v9_0_ecc_available(adev);
635 if (r == 1) {
636 DRM_INFO("ECC is active.\n");
637 } else if (r == 0) {
638 DRM_INFO("ECC is not present.\n");
639 } else {
640 DRM_ERROR("gmc_v9_0_ecc_available() failed. r: %d\n", r);
641 return r;
642 }
02bab923
DP		 643 }
644
770d13b1 645 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
e60f8db5
AX		 646}
647
648static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
770d13b1 649 struct amdgpu_gmc *mc)
e60f8db5 650{
eeb2487d
ML		 651 u64 base = 0;
652 if (!amdgpu_sriov_vf(adev))
653 base = mmhub_v1_0_get_fb_location(adev);
770d13b1 654 amdgpu_device_vram_location(adev, &adev->gmc, base);
2543e28a 655 amdgpu_device_gart_location(adev, mc);
bc099ee9
CZ		 656 /* base offset of vram pages */
657 if (adev->flags & AMD_IS_APU)
658 adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev);
659 else
660 adev->vm_manager.vram_base_offset = 0;
e60f8db5
AX		 661}
662
663/**
664 * gmc_v9_0_mc_init - initialize the memory controller driver params
665 *
666 * @adev: amdgpu_device pointer
667 *
668 * Look up the amount of vram, vram width, and decide how to place
669 * vram and gart within the GPU's physical address space.
670 * Returns 0 for success.
671 */
672static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
673{
674 u32 tmp;
675 int chansize, numchan;
d6895ad3 676 int r;
e60f8db5 677
770d13b1
CK		 678 adev->gmc.vram_width = amdgpu_atomfirmware_get_vram_width(adev);
679 if (!adev->gmc.vram_width) {
8d6a5230
AD		 680 /* hbm memory channel size */
681 chansize = 128;
682
683 tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0);
684 tmp &= DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK;
685 tmp >>= DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
686 switch (tmp) {
687 case 0:
688 default:
689 numchan = 1;
690 break;
691 case 1:
692 numchan = 2;
693 break;
694 case 2:
695 numchan = 0;
696 break;
697 case 3:
698 numchan = 4;
699 break;
700 case 4:
701 numchan = 0;
702 break;
703 case 5:
704 numchan = 8;
705 break;
706 case 6:
707 numchan = 0;
708 break;
709 case 7:
710 numchan = 16;
711 break;
712 case 8:
713 numchan = 2;
714 break;
715 }
770d13b1 716 adev->gmc.vram_width = numchan * chansize;
e60f8db5 717 }
e60f8db5 718
e60f8db5 719 /* size in MB on si */
770d13b1 720 adev->gmc.mc_vram_size =
bf383fb6 721 adev->nbio_funcs->get_memsize(adev) * 1024ULL * 1024ULL;
770d13b1 722 adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
d6895ad3
CK		 723
724 if (!(adev->flags & AMD_IS_APU)) {
725 r = amdgpu_device_resize_fb_bar(adev);
726 if (r)
727 return r;
728 }
770d13b1
CK		 729 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
730 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
e60f8db5
AX		 731
732 /* In case the PCI BAR is larger than the actual amount of vram */
770d13b1
CK		 733 adev->gmc.visible_vram_size = adev->gmc.aper_size;
734 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
735 adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
e60f8db5 736
c3db7b5a
AD		 737 /* set the gart size */
738 if (amdgpu_gart_size == -1) {
739 switch (adev->asic_type) {
740 case CHIP_VEGA10: /* all engines support GPUVM */
741 default:
770d13b1 742 adev->gmc.gart_size = 256ULL << 20;
c3db7b5a
AD		 743 break;
744 case CHIP_RAVEN: /* DCE SG support */
770d13b1 745 adev->gmc.gart_size = 1024ULL << 20;
c3db7b5a
AD		 746 break;
747 }
748 } else {
770d13b1 749 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
c3db7b5a
AD		 750 }
751
770d13b1 752 gmc_v9_0_vram_gtt_location(adev, &adev->gmc);
e60f8db5
AX		 753
754 return 0;
755}
756
757static int gmc_v9_0_gart_init(struct amdgpu_device *adev)
758{
759 int r;
760
761 if (adev->gart.robj) {
762 WARN(1, "VEGA10 PCIE GART already initialized\n");
763 return 0;
764 }
765 /* Initialize common gart structure */
766 r = amdgpu_gart_init(adev);
767 if (r)
768 return r;
769 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
770 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE(MTYPE_UC) |
771 AMDGPU_PTE_EXECUTABLE;
772 return amdgpu_gart_table_vram_alloc(adev);
773}
774
e60f8db5
AX		 775static int gmc_v9_0_sw_init(void *handle)
776{
777 int r;
778 int dma_bits;
779 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
780
0c8c0847 781 gfxhub_v1_0_init(adev);
77f6c763 782 mmhub_v1_0_init(adev);
0c8c0847 783
770d13b1 784 spin_lock_init(&adev->gmc.invalidate_lock);
e60f8db5 785
fd66560b
HZ		 786 switch (adev->asic_type) {
787 case CHIP_RAVEN:
770d13b1 788 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
6a42fd6f 789 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
f3368128 790 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
6a42fd6f
CK		 791 } else {
792 /* vm_size is 128TB + 512GB for legacy 3-level page support */
793 amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48);
770d13b1 794 adev->gmc.translate_further =
6a42fd6f
CK		 795 adev->vm_manager.num_level > 1;
796 }
fd66560b
HZ		 797 break;
798 case CHIP_VEGA10:
e60f8db5 799 /* XXX Don't know how to get VRAM type yet. */
770d13b1 800 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM;
36b32a68
ZJ		 801 /*
802 * To fulfill 4-level page support,
803 * vm size is 256TB (48bit), maximum size of Vega10,
804 * block size 512 (9bit)
805 */
f3368128 806 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
fd66560b
HZ		 807 break;
808 default:
809 break;
e60f8db5
AX		 810 }
811
812 /* This interrupt is VMC page fault.*/
813 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VMC, 0,
770d13b1 814 &adev->gmc.vm_fault);
d7c434d3 815 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_UTCL2, 0,
770d13b1 816 &adev->gmc.vm_fault);
e60f8db5
AX		 817
818 if (r)
819 return r;
820
e60f8db5
AX		 821 /* Set the internal MC address mask
822 * This is the max address of the GPU's
823 * internal address space.
824 */
770d13b1 825 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
e60f8db5 826
916910ad
HR		 827 /*
828 * It needs to reserve 8M stolen memory for vega10
829 * TODO: Figure out how to avoid that...
830 */
770d13b1 831 adev->gmc.stolen_size = 8 * 1024 * 1024;
916910ad 832
e60f8db5
AX		 833 /* set DMA mask + need_dma32 flags.
834 * PCIE - can handle 44-bits.
835 * IGP - can handle 44-bits
836 * PCI - dma32 for legacy pci gart, 44 bits on vega10
837 */
838 adev->need_dma32 = false;
839 dma_bits = adev->need_dma32 ? 32 : 44;
840 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
841 if (r) {
842 adev->need_dma32 = true;
843 dma_bits = 32;
844 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
845 }
846 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
847 if (r) {
848 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
849 printk(KERN_WARNING "amdgpu: No coherent DMA available.\n");
850 }
fd5fd480 851 adev->need_swiotlb = drm_get_max_iomem() > ((u64)1 << dma_bits);
e60f8db5
AX		 852
853 r = gmc_v9_0_mc_init(adev);
854 if (r)
855 return r;
856
857 /* Memory manager */
858 r = amdgpu_bo_init(adev);
859 if (r)
860 return r;
861
862 r = gmc_v9_0_gart_init(adev);
863 if (r)
864 return r;
865
05ec3eda
CK		 866 /*
867 * number of VMs
868 * VMID 0 is reserved for System
869 * amdgpu graphics/compute will use VMIDs 1-7
870 * amdkfd will use VMIDs 8-15
871 */
872 adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids = AMDGPU_NUM_OF_VMIDS;
873 adev->vm_manager.id_mgr[AMDGPU_MMHUB].num_ids = AMDGPU_NUM_OF_VMIDS;
874
05ec3eda
CK		 875 amdgpu_vm_manager_init(adev);
876
877 return 0;
e60f8db5
AX		 878}
879
880/**
c79ee7d8 881 * gmc_v9_0_gart_fini - vm fini callback
e60f8db5
AX		 882 *
883 * @adev: amdgpu_device pointer
884 *
885 * Tears down the driver GART/VM setup (CIK).
886 */
887static void gmc_v9_0_gart_fini(struct amdgpu_device *adev)
888{
889 amdgpu_gart_table_vram_free(adev);
890 amdgpu_gart_fini(adev);
891}
892
893static int gmc_v9_0_sw_fini(void *handle)
894{
895 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
896
f59548c8 897 amdgpu_gem_force_release(adev);
05ec3eda 898 amdgpu_vm_manager_fini(adev);
e60f8db5 899 gmc_v9_0_gart_fini(adev);
e60f8db5
AX		 900 amdgpu_bo_fini(adev);
901
902 return 0;
903}
904
905static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
906{
946a4d5b 907
e60f8db5
AX		 908 switch (adev->asic_type) {
909 case CHIP_VEGA10:
946a4d5b 910 soc15_program_register_sequence(adev,
5c583018 911 golden_settings_mmhub_1_0_0,
c47b41a7 912 ARRAY_SIZE(golden_settings_mmhub_1_0_0));
946a4d5b 913 soc15_program_register_sequence(adev,
5c583018 914 golden_settings_athub_1_0_0,
c47b41a7 915 ARRAY_SIZE(golden_settings_athub_1_0_0));
e60f8db5 916 break;
e4f3abaa 917 case CHIP_RAVEN:
946a4d5b 918 soc15_program_register_sequence(adev,
5c583018 919 golden_settings_athub_1_0_0,
c47b41a7 920 ARRAY_SIZE(golden_settings_athub_1_0_0));
e4f3abaa 921 break;
e60f8db5
AX		 922 default:
923 break;
924 }
925}
926
927/**
928 * gmc_v9_0_gart_enable - gart enable
929 *
930 * @adev: amdgpu_device pointer
931 */
932static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
933{
934 int r;
935 bool value;
936 u32 tmp;
937
9c3f2b54
AD		 938 amdgpu_device_program_register_sequence(adev,
939 golden_settings_vega10_hdp,
940 ARRAY_SIZE(golden_settings_vega10_hdp));
e60f8db5
AX		 941
942 if (adev->gart.robj == NULL) {
943 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
944 return -EINVAL;
945 }
ce1b1b66
ML		 946 r = amdgpu_gart_table_vram_pin(adev);
947 if (r)
948 return r;
e60f8db5 949
2fcd43ce
HZ		 950 switch (adev->asic_type) {
951 case CHIP_RAVEN:
952 mmhub_v1_0_initialize_power_gating(adev);
f8386b35 953 mmhub_v1_0_update_power_gating(adev, true);
2fcd43ce
HZ		 954 break;
955 default:
956 break;
957 }
958
e60f8db5
AX		 959 r = gfxhub_v1_0_gart_enable(adev);
960 if (r)
961 return r;
962
963 r = mmhub_v1_0_gart_enable(adev);
964 if (r)
965 return r;
966
846347c9 967 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
e60f8db5 968
b9509c80
HR		 969 tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL);
970 WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);
e60f8db5 971
1d4e0a8c 972 /* After HDP is initialized, flush HDP.*/
bf383fb6 973 adev->nbio_funcs->hdp_flush(adev);
1d4e0a8c 974
e60f8db5
AX		 975 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
976 value = false;
977 else
978 value = true;
979
980 gfxhub_v1_0_set_fault_enable_default(adev, value);
981 mmhub_v1_0_set_fault_enable_default(adev, value);
132f34e4 982 gmc_v9_0_flush_gpu_tlb(adev, 0);
e60f8db5
AX		 983
984 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
770d13b1 985 (unsigned)(adev->gmc.gart_size >> 20),
e60f8db5
AX		 986 (unsigned long long)adev->gart.table_addr);
987 adev->gart.ready = true;
988 return 0;
989}
990
991static int gmc_v9_0_hw_init(void *handle)
992{
993 int r;
994 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
995
996 /* The sequence of these two function calls matters.*/
997 gmc_v9_0_init_golden_registers(adev);
998
edca2d05 999 if (adev->mode_info.num_crtc) {
edca2d05 1000 /* Lockout access through VGA aperture*/
4d9c333a 1001 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
edca2d05
AD		 1002
1003 /* disable VGA render */
4d9c333a 1004 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
edca2d05
AD		 1005 }
1006
e60f8db5
AX		 1007 r = gmc_v9_0_gart_enable(adev);
1008
1009 return r;
1010}
1011
1012/**
1013 * gmc_v9_0_gart_disable - gart disable
1014 *
1015 * @adev: amdgpu_device pointer
1016 *
1017 * This disables all VM page table.
1018 */
1019static void gmc_v9_0_gart_disable(struct amdgpu_device *adev)
1020{
1021 gfxhub_v1_0_gart_disable(adev);
1022 mmhub_v1_0_gart_disable(adev);
ce1b1b66 1023 amdgpu_gart_table_vram_unpin(adev);
e60f8db5
AX		 1024}
1025
1026static int gmc_v9_0_hw_fini(void *handle)
1027{
1028 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1029
5dd696ae
TH		 1030 if (amdgpu_sriov_vf(adev)) {
1031 /* full access mode, so don't touch any GMC register */
1032 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
1033 return 0;
1034 }
1035
770d13b1 1036 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
e60f8db5
AX		 1037 gmc_v9_0_gart_disable(adev);
1038
1039 return 0;
1040}
1041
1042static int gmc_v9_0_suspend(void *handle)
1043{
1044 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1045
f053cd47 1046 return gmc_v9_0_hw_fini(adev);
e60f8db5
AX		 1047}
1048
1049static int gmc_v9_0_resume(void *handle)
1050{
1051 int r;
1052 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1053
1054 r = gmc_v9_0_hw_init(adev);
1055 if (r)
1056 return r;
1057
620f774f 1058 amdgpu_vmid_reset_all(adev);
e60f8db5 1059
32601d48 1060 return 0;
e60f8db5
AX		 1061}
1062
1063static bool gmc_v9_0_is_idle(void *handle)
1064{
1065 /* MC is always ready in GMC v9.*/
1066 return true;
1067}
1068
1069static int gmc_v9_0_wait_for_idle(void *handle)
1070{
1071 /* There is no need to wait for MC idle in GMC v9.*/
1072 return 0;
1073}
1074
1075static int gmc_v9_0_soft_reset(void *handle)
1076{
1077 /* XXX for emulation.*/
1078 return 0;
1079}
1080
1081static int gmc_v9_0_set_clockgating_state(void *handle,
1082 enum amd_clockgating_state state)
1083{
d5583d4f
HR		 1084 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1085
1086 return mmhub_v1_0_set_clockgating(adev, state);
e60f8db5
AX		 1087}
1088
13052be5
HR		 1089static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags)
1090{
1091 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1092
1093 mmhub_v1_0_get_clockgating(adev, flags);
1094}
1095
e60f8db5
AX		 1096static int gmc_v9_0_set_powergating_state(void *handle,
1097 enum amd_powergating_state state)
1098{
1099 return 0;
1100}
1101
1102const struct amd_ip_funcs gmc_v9_0_ip_funcs = {
1103 .name = "gmc_v9_0",
1104 .early_init = gmc_v9_0_early_init,
1105 .late_init = gmc_v9_0_late_init,
1106 .sw_init = gmc_v9_0_sw_init,
1107 .sw_fini = gmc_v9_0_sw_fini,
1108 .hw_init = gmc_v9_0_hw_init,
1109 .hw_fini = gmc_v9_0_hw_fini,
1110 .suspend = gmc_v9_0_suspend,
1111 .resume = gmc_v9_0_resume,
1112 .is_idle = gmc_v9_0_is_idle,
1113 .wait_for_idle = gmc_v9_0_wait_for_idle,
1114 .soft_reset = gmc_v9_0_soft_reset,
1115 .set_clockgating_state = gmc_v9_0_set_clockgating_state,
1116 .set_powergating_state = gmc_v9_0_set_powergating_state,
13052be5 1117 .get_clockgating_state = gmc_v9_0_get_clockgating_state,
e60f8db5
AX		 1118};
1119
1120const struct amdgpu_ip_block_version gmc_v9_0_ip_block =
1121{
1122 .type = AMD_IP_BLOCK_TYPE_GMC,
1123 .major = 9,
1124 .minor = 0,
1125 .rev = 0,
1126 .funcs = &gmc_v9_0_ip_funcs,
1127};
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