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drm/amd/amdgpu: if visible VRAM allocation fail, fall back to invisible try again
[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / amd / amdgpu / gmc_v9_0.c
CommitLineData
e60f8db5
AX		 1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include "amdgpu.h"
25#include "gmc_v9_0.h"
8d6a5230 26#include "amdgpu_atomfirmware.h"
e60f8db5
AX		 27
28#include "vega10/soc15ip.h"
29#include "vega10/HDP/hdp_4_0_offset.h"
30#include "vega10/HDP/hdp_4_0_sh_mask.h"
31#include "vega10/GC/gc_9_0_sh_mask.h"
edca2d05
AD		 32#include "vega10/DC/dce_12_0_offset.h"
33#include "vega10/DC/dce_12_0_sh_mask.h"
e60f8db5 34#include "vega10/vega10_enum.h"
5c583018
EQ		 35#include "vega10/MMHUB/mmhub_1_0_offset.h"
36#include "vega10/ATHUB/athub_1_0_offset.h"
e60f8db5
AX		 37
38#include "soc15_common.h"
39
40#include "nbio_v6_1.h"
aecbe64f 41#include "nbio_v7_0.h"
e60f8db5
AX		 42#include "gfxhub_v1_0.h"
43#include "mmhub_v1_0.h"
44
45#define mmDF_CS_AON0_DramBaseAddress0 0x0044
46#define mmDF_CS_AON0_DramBaseAddress0_BASE_IDX 0
47//DF_CS_AON0_DramBaseAddress0
48#define DF_CS_AON0_DramBaseAddress0__AddrRngVal__SHIFT 0x0
49#define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT 0x1
50#define DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT 0x4
51#define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT 0x8
52#define DF_CS_AON0_DramBaseAddress0__DramBaseAddr__SHIFT 0xc
53#define DF_CS_AON0_DramBaseAddress0__AddrRngVal_MASK 0x00000001L
54#define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK 0x00000002L
55#define DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK 0x000000F0L
56#define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK 0x00000700L
57#define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK 0xFFFFF000L
58
59/* XXX Move this macro to VEGA10 header file, which is like vid.h for VI.*/
60#define AMDGPU_NUM_OF_VMIDS 8
61
62static const u32 golden_settings_vega10_hdp[] =
63{
64 0xf64, 0x0fffffff, 0x00000000,
65 0xf65, 0x0fffffff, 0x00000000,
66 0xf66, 0x0fffffff, 0x00000000,
67 0xf67, 0x0fffffff, 0x00000000,
68 0xf68, 0x0fffffff, 0x00000000,
69 0xf6a, 0x0fffffff, 0x00000000,
70 0xf6b, 0x0fffffff, 0x00000000,
71 0xf6c, 0x0fffffff, 0x00000000,
72 0xf6d, 0x0fffffff, 0x00000000,
73 0xf6e, 0x0fffffff, 0x00000000,
74};
75
5c583018
EQ		 76static const u32 golden_settings_mmhub_1_0_0[] =
77{
78 SOC15_REG_OFFSET(MMHUB, 0, mmDAGB1_WRCLI2), 0x00000007, 0xfe5fe0fa,
79 SOC15_REG_OFFSET(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0), 0x00000030, 0x55555565
80};
81
82static const u32 golden_settings_athub_1_0_0[] =
83{
84 SOC15_REG_OFFSET(ATHUB, 0, mmRPB_ARB_CNTL), 0x0000ff00, 0x00000800,
85 SOC15_REG_OFFSET(ATHUB, 0, mmRPB_ARB_CNTL2), 0x00ff00ff, 0x00080008
86};
87
e60f8db5
AX		 88static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
89 struct amdgpu_irq_src *src,
90 unsigned type,
91 enum amdgpu_interrupt_state state)
92{
93 struct amdgpu_vmhub *hub;
ae6d1416 94 u32 tmp, reg, bits, i, j;
e60f8db5 95
11250164
CK		 96 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
97 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
98 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
99 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
100 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
101 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
102 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
103
e60f8db5
AX		 104 switch (state) {
105 case AMDGPU_IRQ_STATE_DISABLE:
ae6d1416
TSD		 106 for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) {
107 hub = &adev->vmhub[j];
108 for (i = 0; i < 16; i++) {
109 reg = hub->vm_context0_cntl + i;
110 tmp = RREG32(reg);
111 tmp &= ~bits;
112 WREG32(reg, tmp);
113 }
e60f8db5
AX		 114 }
115 break;
116 case AMDGPU_IRQ_STATE_ENABLE:
ae6d1416
TSD		 117 for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) {
118 hub = &adev->vmhub[j];
119 for (i = 0; i < 16; i++) {
120 reg = hub->vm_context0_cntl + i;
121 tmp = RREG32(reg);
122 tmp |= bits;
123 WREG32(reg, tmp);
124 }
e60f8db5 125 }
e60f8db5
AX		 126 default:
127 break;
128 }
129
130 return 0;
131}
132
133static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
134 struct amdgpu_irq_src *source,
135 struct amdgpu_iv_entry *entry)
136{
5a9b8e8a 137 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vm_id_src];
4d6cbde3 138 uint32_t status = 0;
e60f8db5
AX		 139 u64 addr;
140
141 addr = (u64)entry->src_data[0] << 12;
142 addr |= ((u64)entry->src_data[1] & 0xf) << 44;
143
79a0c465 144 if (!amdgpu_sriov_vf(adev)) {
5a9b8e8a
CK		 145 status = RREG32(hub->vm_l2_pro_fault_status);
146 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
4d6cbde3 147 }
e60f8db5 148
4d6cbde3
FK		 149 if (printk_ratelimit()) {
150 dev_err(adev->dev,
151 "[%s] VMC page fault (src_id:%u ring:%u vm_id:%u pas_id:%u)\n",
152 entry->vm_id_src ? "mmhub" : "gfxhub",
153 entry->src_id, entry->ring_id, entry->vm_id,
154 entry->pas_id);
155 dev_err(adev->dev, " at page 0x%016llx from %d\n",
156 addr, entry->client_id);
157 if (!amdgpu_sriov_vf(adev))
158 dev_err(adev->dev,
159 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
160 status);
79a0c465 161 }
e60f8db5
AX		 162
163 return 0;
164}
165
166static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = {
167 .set = gmc_v9_0_vm_fault_interrupt_state,
168 .process = gmc_v9_0_process_interrupt,
169};
170
171static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev)
172{
173 adev->mc.vm_fault.num_types = 1;
174 adev->mc.vm_fault.funcs = &gmc_v9_0_irq_funcs;
175}
176
03f89feb
CK		 177static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vm_id)
178{
179 u32 req = 0;
180
181 /* invalidate using legacy mode on vm_id*/
182 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
183 PER_VMID_INVALIDATE_REQ, 1 << vm_id);
184 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, 0);
185 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
186 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
187 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
188 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
189 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
190 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
191 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
192
193 return req;
194}
195
e60f8db5
AX		 196/*
197 * GART
198 * VMID 0 is the physical GPU addresses as used by the kernel.
199 * VMIDs 1-15 are used for userspace clients and are handled
200 * by the amdgpu vm/hsa code.
201 */
202
203/**
204 * gmc_v9_0_gart_flush_gpu_tlb - gart tlb flush callback
205 *
206 * @adev: amdgpu_device pointer
207 * @vmid: vm instance to flush
208 *
209 * Flush the TLB for the requested page table.
210 */
211static void gmc_v9_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
212 uint32_t vmid)
213{
214 /* Use register 17 for GART */
215 const unsigned eng = 17;
216 unsigned i, j;
217
218 /* flush hdp cache */
aecbe64f
CZ		 219 if (adev->flags & AMD_IS_APU)
220 nbio_v7_0_hdp_flush(adev);
221 else
222 nbio_v6_1_hdp_flush(adev);
e60f8db5
AX		 223
224 spin_lock(&adev->mc.invalidate_lock);
225
226 for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
227 struct amdgpu_vmhub *hub = &adev->vmhub[i];
03f89feb 228 u32 tmp = gmc_v9_0_get_invalidate_req(vmid);
e60f8db5 229
c7a7266b 230 WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);
e60f8db5
AX		 231
232 /* Busy wait for ACK.*/
233 for (j = 0; j < 100; j++) {
c7a7266b 234 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
e60f8db5
AX		 235 tmp &= 1 << vmid;
236 if (tmp)
237 break;
238 cpu_relax();
239 }
240 if (j < 100)
241 continue;
242
243 /* Wait for ACK with a delay.*/
244 for (j = 0; j < adev->usec_timeout; j++) {
c7a7266b 245 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
e60f8db5
AX		 246 tmp &= 1 << vmid;
247 if (tmp)
248 break;
249 udelay(1);
250 }
251 if (j < adev->usec_timeout)
252 continue;
253
254 DRM_ERROR("Timeout waiting for VM flush ACK!\n");
255 }
256
257 spin_unlock(&adev->mc.invalidate_lock);
258}
259
260/**
261 * gmc_v9_0_gart_set_pte_pde - update the page tables using MMIO
262 *
263 * @adev: amdgpu_device pointer
264 * @cpu_pt_addr: cpu address of the page table
265 * @gpu_page_idx: entry in the page table to update
266 * @addr: dst addr to write into pte/pde
267 * @flags: access flags
268 *
269 * Update the page tables using the CPU.
270 */
271static int gmc_v9_0_gart_set_pte_pde(struct amdgpu_device *adev,
272 void *cpu_pt_addr,
273 uint32_t gpu_page_idx,
274 uint64_t addr,
275 uint64_t flags)
276{
277 void __iomem *ptr = (void *)cpu_pt_addr;
278 uint64_t value;
279
280 /*
281 * PTE format on VEGA 10:
282 * 63:59 reserved
283 * 58:57 mtype
284 * 56 F
285 * 55 L
286 * 54 P
287 * 53 SW
288 * 52 T
289 * 50:48 reserved
290 * 47:12 4k physical page base address
291 * 11:7 fragment
292 * 6 write
293 * 5 read
294 * 4 exe
295 * 3 Z
296 * 2 snooped
297 * 1 system
298 * 0 valid
299 *
300 * PDE format on VEGA 10:
301 * 63:59 block fragment size
302 * 58:55 reserved
303 * 54 P
304 * 53:48 reserved
305 * 47:6 physical base address of PD or PTE
306 * 5:3 reserved
307 * 2 C
308 * 1 system
309 * 0 valid
310 */
311
312 /*
313 * The following is for PTE only. GART does not have PDEs.
314 */
315 value = addr & 0x0000FFFFFFFFF000ULL;
316 value |= flags;
317 writeq(value, ptr + (gpu_page_idx * 8));
318 return 0;
319}
320
321static uint64_t gmc_v9_0_get_vm_pte_flags(struct amdgpu_device *adev,
322 uint32_t flags)
323
324{
325 uint64_t pte_flag = 0;
326
327 if (flags & AMDGPU_VM_PAGE_EXECUTABLE)
328 pte_flag |= AMDGPU_PTE_EXECUTABLE;
329 if (flags & AMDGPU_VM_PAGE_READABLE)
330 pte_flag |= AMDGPU_PTE_READABLE;
331 if (flags & AMDGPU_VM_PAGE_WRITEABLE)
332 pte_flag |= AMDGPU_PTE_WRITEABLE;
333
334 switch (flags & AMDGPU_VM_MTYPE_MASK) {
335 case AMDGPU_VM_MTYPE_DEFAULT:
336 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
337 break;
338 case AMDGPU_VM_MTYPE_NC:
339 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
340 break;
341 case AMDGPU_VM_MTYPE_WC:
342 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_WC);
343 break;
344 case AMDGPU_VM_MTYPE_CC:
345 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_CC);
346 break;
347 case AMDGPU_VM_MTYPE_UC:
348 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_UC);
349 break;
350 default:
351 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
352 break;
353 }
354
355 if (flags & AMDGPU_VM_PAGE_PRT)
356 pte_flag |= AMDGPU_PTE_PRT;
357
358 return pte_flag;
359}
360
b1166325 361static u64 gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, u64 addr)
e60f8db5 362{
b1166325
CK		 363 addr = adev->vm_manager.vram_base_offset + addr - adev->mc.vram_start;
364 BUG_ON(addr & 0xFFFF00000000003FULL);
365 return addr;
e60f8db5
AX		 366}
367
f75e237c
CK		 368static const struct amdgpu_gart_funcs gmc_v9_0_gart_funcs = {
369 .flush_gpu_tlb = gmc_v9_0_gart_flush_gpu_tlb,
370 .set_pte_pde = gmc_v9_0_gart_set_pte_pde,
03f89feb 371 .get_invalidate_req = gmc_v9_0_get_invalidate_req,
b1166325
CK		 372 .get_vm_pte_flags = gmc_v9_0_get_vm_pte_flags,
373 .get_vm_pde = gmc_v9_0_get_vm_pde
e60f8db5
AX		 374};
375
f75e237c 376static void gmc_v9_0_set_gart_funcs(struct amdgpu_device *adev)
e60f8db5 377{
f75e237c
CK		 378 if (adev->gart.gart_funcs == NULL)
379 adev->gart.gart_funcs = &gmc_v9_0_gart_funcs;
e60f8db5
AX		 380}
381
382static int gmc_v9_0_early_init(void *handle)
383{
384 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
385
386 gmc_v9_0_set_gart_funcs(adev);
e60f8db5
AX		 387 gmc_v9_0_set_irq_funcs(adev);
388
389 return 0;
390}
391
392static int gmc_v9_0_late_init(void *handle)
393{
394 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
43b9176f 395 unsigned vm_inv_eng[AMDGPU_MAX_VMHUBS] = { 3, 3 };
4789c463
CK		 396 unsigned i;
397
398 for(i = 0; i < adev->num_rings; ++i) {
399 struct amdgpu_ring *ring = adev->rings[i];
400 unsigned vmhub = ring->funcs->vmhub;
401
402 ring->vm_inv_eng = vm_inv_eng[vmhub]++;
775f55f1
TSD		 403 dev_info(adev->dev, "ring %u(%s) uses VM inv eng %u on hub %u\n",
404 ring->idx, ring->name, ring->vm_inv_eng,
405 ring->funcs->vmhub);
4789c463
CK		 406 }
407
408 /* Engine 17 is used for GART flushes */
409 for(i = 0; i < AMDGPU_MAX_VMHUBS; ++i)
410 BUG_ON(vm_inv_eng[i] > 17);
411
e60f8db5
AX		 412 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
413}
414
415static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
416 struct amdgpu_mc *mc)
417{
eeb2487d
ML		 418 u64 base = 0;
419 if (!amdgpu_sriov_vf(adev))
420 base = mmhub_v1_0_get_fb_location(adev);
e60f8db5 421 amdgpu_vram_location(adev, &adev->mc, base);
6f02a696 422 amdgpu_gart_location(adev, mc);
bc099ee9
CZ		 423 /* base offset of vram pages */
424 if (adev->flags & AMD_IS_APU)
425 adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev);
426 else
427 adev->vm_manager.vram_base_offset = 0;
e60f8db5
AX		 428}
429
430/**
431 * gmc_v9_0_mc_init - initialize the memory controller driver params
432 *
433 * @adev: amdgpu_device pointer
434 *
435 * Look up the amount of vram, vram width, and decide how to place
436 * vram and gart within the GPU's physical address space.
437 * Returns 0 for success.
438 */
439static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
440{
441 u32 tmp;
442 int chansize, numchan;
443
8d6a5230
AD		 444 adev->mc.vram_width = amdgpu_atomfirmware_get_vram_width(adev);
445 if (!adev->mc.vram_width) {
446 /* hbm memory channel size */
447 chansize = 128;
448
449 tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0);
450 tmp &= DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK;
451 tmp >>= DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
452 switch (tmp) {
453 case 0:
454 default:
455 numchan = 1;
456 break;
457 case 1:
458 numchan = 2;
459 break;
460 case 2:
461 numchan = 0;
462 break;
463 case 3:
464 numchan = 4;
465 break;
466 case 4:
467 numchan = 0;
468 break;
469 case 5:
470 numchan = 8;
471 break;
472 case 6:
473 numchan = 0;
474 break;
475 case 7:
476 numchan = 16;
477 break;
478 case 8:
479 numchan = 2;
480 break;
481 }
482 adev->mc.vram_width = numchan * chansize;
e60f8db5 483 }
e60f8db5
AX		 484
485 /* Could aper size report 0 ? */
486 adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
487 adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
488 /* size in MB on si */
489 adev->mc.mc_vram_size =
aecbe64f
CZ		 490 ((adev->flags & AMD_IS_APU) ? nbio_v7_0_get_memsize(adev) :
491 nbio_v6_1_get_memsize(adev)) * 1024ULL * 1024ULL;
e60f8db5
AX		 492 adev->mc.real_vram_size = adev->mc.mc_vram_size;
493 adev->mc.visible_vram_size = adev->mc.aper_size;
494
495 /* In case the PCI BAR is larger than the actual amount of vram */
496 if (adev->mc.visible_vram_size > adev->mc.real_vram_size)
497 adev->mc.visible_vram_size = adev->mc.real_vram_size;
498
c3db7b5a
AD		 499 /* set the gart size */
500 if (amdgpu_gart_size == -1) {
501 switch (adev->asic_type) {
502 case CHIP_VEGA10: /* all engines support GPUVM */
503 default:
504 adev->mc.gart_size = 256ULL << 20;
505 break;
506 case CHIP_RAVEN: /* DCE SG support */
507 adev->mc.gart_size = 1024ULL << 20;
508 break;
509 }
510 } else {
511 adev->mc.gart_size = (u64)amdgpu_gart_size << 20;
512 }
513
e60f8db5
AX		 514 gmc_v9_0_vram_gtt_location(adev, &adev->mc);
515
516 return 0;
517}
518
519static int gmc_v9_0_gart_init(struct amdgpu_device *adev)
520{
521 int r;
522
523 if (adev->gart.robj) {
524 WARN(1, "VEGA10 PCIE GART already initialized\n");
525 return 0;
526 }
527 /* Initialize common gart structure */
528 r = amdgpu_gart_init(adev);
529 if (r)
530 return r;
531 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
532 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE(MTYPE_UC) |
533 AMDGPU_PTE_EXECUTABLE;
534 return amdgpu_gart_table_vram_alloc(adev);
535}
536
e60f8db5
AX		 537static int gmc_v9_0_sw_init(void *handle)
538{
539 int r;
540 int dma_bits;
541 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
542
0c8c0847 543 gfxhub_v1_0_init(adev);
77f6c763 544 mmhub_v1_0_init(adev);
0c8c0847 545
e60f8db5
AX		 546 spin_lock_init(&adev->mc.invalidate_lock);
547
fd66560b
HZ		 548 switch (adev->asic_type) {
549 case CHIP_RAVEN:
e60f8db5 550 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
fd66560b
HZ		 551 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
552 adev->vm_manager.vm_size = 1U << 18;
553 adev->vm_manager.block_size = 9;
554 adev->vm_manager.num_level = 3;
d07f14be 555 amdgpu_vm_set_fragment_size(adev, 9);
fd66560b 556 } else {
d07f14be
RH		 557 /* vm_size is 64GB for legacy 2-level page support */
558 amdgpu_vm_adjust_size(adev, 64, 9);
fd66560b
HZ		 559 adev->vm_manager.num_level = 1;
560 }
561 break;
562 case CHIP_VEGA10:
e60f8db5
AX		 563 /* XXX Don't know how to get VRAM type yet. */
564 adev->mc.vram_type = AMDGPU_VRAM_TYPE_HBM;
36b32a68
ZJ		 565 /*
566 * To fulfill 4-level page support,
567 * vm size is 256TB (48bit), maximum size of Vega10,
568 * block size 512 (9bit)
569 */
570 adev->vm_manager.vm_size = 1U << 18;
571 adev->vm_manager.block_size = 9;
fd66560b 572 adev->vm_manager.num_level = 3;
d07f14be 573 amdgpu_vm_set_fragment_size(adev, 9);
fd66560b
HZ		 574 break;
575 default:
576 break;
e60f8db5
AX		 577 }
578
e618d306 579 DRM_INFO("vm size is %llu GB, block size is %u-bit,fragment size is %u-bit\n",
fd66560b 580 adev->vm_manager.vm_size,
e618d306
RH		 581 adev->vm_manager.block_size,
582 adev->vm_manager.fragment_size);
fd66560b 583
e60f8db5
AX		 584 /* This interrupt is VMC page fault.*/
585 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VMC, 0,
586 &adev->mc.vm_fault);
d7c434d3
FK		 587 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_UTCL2, 0,
588 &adev->mc.vm_fault);
e60f8db5
AX		 589
590 if (r)
591 return r;
592
36b32a68 593 adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
e60f8db5
AX		 594
595 /* Set the internal MC address mask
596 * This is the max address of the GPU's
597 * internal address space.
598 */
599 adev->mc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
600
916910ad
HR		 601 /*
602 * It needs to reserve 8M stolen memory for vega10
603 * TODO: Figure out how to avoid that...
604 */
605 adev->mc.stolen_size = 8 * 1024 * 1024;
606
e60f8db5
AX		 607 /* set DMA mask + need_dma32 flags.
608 * PCIE - can handle 44-bits.
609 * IGP - can handle 44-bits
610 * PCI - dma32 for legacy pci gart, 44 bits on vega10
611 */
612 adev->need_dma32 = false;
613 dma_bits = adev->need_dma32 ? 32 : 44;
614 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
615 if (r) {
616 adev->need_dma32 = true;
617 dma_bits = 32;
618 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
619 }
620 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
621 if (r) {
622 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
623 printk(KERN_WARNING "amdgpu: No coherent DMA available.\n");
624 }
625
626 r = gmc_v9_0_mc_init(adev);
627 if (r)
628 return r;
629
630 /* Memory manager */
631 r = amdgpu_bo_init(adev);
632 if (r)
633 return r;
634
635 r = gmc_v9_0_gart_init(adev);
636 if (r)
637 return r;
638
05ec3eda
CK		 639 /*
640 * number of VMs
641 * VMID 0 is reserved for System
642 * amdgpu graphics/compute will use VMIDs 1-7
643 * amdkfd will use VMIDs 8-15
644 */
645 adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids = AMDGPU_NUM_OF_VMIDS;
646 adev->vm_manager.id_mgr[AMDGPU_MMHUB].num_ids = AMDGPU_NUM_OF_VMIDS;
647
05ec3eda
CK		 648 amdgpu_vm_manager_init(adev);
649
650 return 0;
e60f8db5
AX		 651}
652
653/**
654 * gmc_v8_0_gart_fini - vm fini callback
655 *
656 * @adev: amdgpu_device pointer
657 *
658 * Tears down the driver GART/VM setup (CIK).
659 */
660static void gmc_v9_0_gart_fini(struct amdgpu_device *adev)
661{
662 amdgpu_gart_table_vram_free(adev);
663 amdgpu_gart_fini(adev);
664}
665
666static int gmc_v9_0_sw_fini(void *handle)
667{
668 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
669
05ec3eda 670 amdgpu_vm_manager_fini(adev);
e60f8db5
AX		 671 gmc_v9_0_gart_fini(adev);
672 amdgpu_gem_force_release(adev);
673 amdgpu_bo_fini(adev);
674
675 return 0;
676}
677
678static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
679{
680 switch (adev->asic_type) {
681 case CHIP_VEGA10:
5c583018
EQ		 682 amdgpu_program_register_sequence(adev,
683 golden_settings_mmhub_1_0_0,
684 (const u32)ARRAY_SIZE(golden_settings_mmhub_1_0_0));
685 amdgpu_program_register_sequence(adev,
686 golden_settings_athub_1_0_0,
687 (const u32)ARRAY_SIZE(golden_settings_athub_1_0_0));
e60f8db5 688 break;
e4f3abaa 689 case CHIP_RAVEN:
5c583018
EQ		 690 amdgpu_program_register_sequence(adev,
691 golden_settings_athub_1_0_0,
692 (const u32)ARRAY_SIZE(golden_settings_athub_1_0_0));
e4f3abaa 693 break;
e60f8db5
AX		 694 default:
695 break;
696 }
697}
698
699/**
700 * gmc_v9_0_gart_enable - gart enable
701 *
702 * @adev: amdgpu_device pointer
703 */
704static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
705{
706 int r;
707 bool value;
708 u32 tmp;
709
710 amdgpu_program_register_sequence(adev,
711 golden_settings_vega10_hdp,
712 (const u32)ARRAY_SIZE(golden_settings_vega10_hdp));
713
714 if (adev->gart.robj == NULL) {
715 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
716 return -EINVAL;
717 }
718 r = amdgpu_gart_table_vram_pin(adev);
719 if (r)
720 return r;
721
2fcd43ce
HZ		 722 switch (adev->asic_type) {
723 case CHIP_RAVEN:
724 mmhub_v1_0_initialize_power_gating(adev);
f8386b35 725 mmhub_v1_0_update_power_gating(adev, true);
2fcd43ce
HZ		 726 break;
727 default:
728 break;
729 }
730
e60f8db5
AX		 731 r = gfxhub_v1_0_gart_enable(adev);
732 if (r)
733 return r;
734
735 r = mmhub_v1_0_gart_enable(adev);
736 if (r)
737 return r;
738
846347c9 739 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
e60f8db5 740
b9509c80
HR		 741 tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL);
742 WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);
e60f8db5 743
1d4e0a8c
ML		 744 /* After HDP is initialized, flush HDP.*/
745 if (adev->flags & AMD_IS_APU)
746 nbio_v7_0_hdp_flush(adev);
747 else
748 nbio_v6_1_hdp_flush(adev);
749
e60f8db5
AX		 750 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
751 value = false;
752 else
753 value = true;
754
755 gfxhub_v1_0_set_fault_enable_default(adev, value);
756 mmhub_v1_0_set_fault_enable_default(adev, value);
e60f8db5
AX		 757 gmc_v9_0_gart_flush_gpu_tlb(adev, 0);
758
759 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
6f02a696 760 (unsigned)(adev->mc.gart_size >> 20),
e60f8db5
AX		 761 (unsigned long long)adev->gart.table_addr);
762 adev->gart.ready = true;
763 return 0;
764}
765
766static int gmc_v9_0_hw_init(void *handle)
767{
768 int r;
769 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
770
771 /* The sequence of these two function calls matters.*/
772 gmc_v9_0_init_golden_registers(adev);
773
edca2d05 774 if (adev->mode_info.num_crtc) {
edca2d05 775 /* Lockout access through VGA aperture*/
4d9c333a 776 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
edca2d05
AD		 777
778 /* disable VGA render */
4d9c333a 779 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
edca2d05
AD		 780 }
781
e60f8db5
AX		 782 r = gmc_v9_0_gart_enable(adev);
783
784 return r;
785}
786
787/**
788 * gmc_v9_0_gart_disable - gart disable
789 *
790 * @adev: amdgpu_device pointer
791 *
792 * This disables all VM page table.
793 */
794static void gmc_v9_0_gart_disable(struct amdgpu_device *adev)
795{
796 gfxhub_v1_0_gart_disable(adev);
797 mmhub_v1_0_gart_disable(adev);
798 amdgpu_gart_table_vram_unpin(adev);
799}
800
801static int gmc_v9_0_hw_fini(void *handle)
802{
803 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
804
5dd696ae
TH		 805 if (amdgpu_sriov_vf(adev)) {
806 /* full access mode, so don't touch any GMC register */
807 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
808 return 0;
809 }
810
e60f8db5
AX		 811 amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
812 gmc_v9_0_gart_disable(adev);
813
814 return 0;
815}
816
817static int gmc_v9_0_suspend(void *handle)
818{
819 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
820
f053cd47 821 return gmc_v9_0_hw_fini(adev);
e60f8db5
AX		 822}
823
824static int gmc_v9_0_resume(void *handle)
825{
826 int r;
827 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
828
829 r = gmc_v9_0_hw_init(adev);
830 if (r)
831 return r;
832
32601d48 833 amdgpu_vm_reset_all_ids(adev);
e60f8db5 834
32601d48 835 return 0;
e60f8db5
AX		 836}
837
838static bool gmc_v9_0_is_idle(void *handle)
839{
840 /* MC is always ready in GMC v9.*/
841 return true;
842}
843
844static int gmc_v9_0_wait_for_idle(void *handle)
845{
846 /* There is no need to wait for MC idle in GMC v9.*/
847 return 0;
848}
849
850static int gmc_v9_0_soft_reset(void *handle)
851{
852 /* XXX for emulation.*/
853 return 0;
854}
855
856static int gmc_v9_0_set_clockgating_state(void *handle,
857 enum amd_clockgating_state state)
858{
d5583d4f
HR		 859 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
860
861 return mmhub_v1_0_set_clockgating(adev, state);
e60f8db5
AX		 862}
863
13052be5
HR		 864static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags)
865{
866 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
867
868 mmhub_v1_0_get_clockgating(adev, flags);
869}
870
e60f8db5
AX		 871static int gmc_v9_0_set_powergating_state(void *handle,
872 enum amd_powergating_state state)
873{
874 return 0;
875}
876
877const struct amd_ip_funcs gmc_v9_0_ip_funcs = {
878 .name = "gmc_v9_0",
879 .early_init = gmc_v9_0_early_init,
880 .late_init = gmc_v9_0_late_init,
881 .sw_init = gmc_v9_0_sw_init,
882 .sw_fini = gmc_v9_0_sw_fini,
883 .hw_init = gmc_v9_0_hw_init,
884 .hw_fini = gmc_v9_0_hw_fini,
885 .suspend = gmc_v9_0_suspend,
886 .resume = gmc_v9_0_resume,
887 .is_idle = gmc_v9_0_is_idle,
888 .wait_for_idle = gmc_v9_0_wait_for_idle,
889 .soft_reset = gmc_v9_0_soft_reset,
890 .set_clockgating_state = gmc_v9_0_set_clockgating_state,
891 .set_powergating_state = gmc_v9_0_set_powergating_state,
13052be5 892 .get_clockgating_state = gmc_v9_0_get_clockgating_state,
e60f8db5
AX		 893};
894
895const struct amdgpu_ip_block_version gmc_v9_0_ip_block =
896{
897 .type = AMD_IP_BLOCK_TYPE_GMC,
898 .major = 9,
899 .minor = 0,
900 .rev = 0,
901 .funcs = &gmc_v9_0_ip_funcs,
902};
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