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drm/amdkfd: Remove unnecessary register setting when invalidating tlb in kfd
[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / amd / amdgpu / gmc_v9_0.c
CommitLineData
e60f8db5
AX		 1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
fd5fd480 24#include <drm/drm_cache.h>
e60f8db5
AX		 25#include "amdgpu.h"
26#include "gmc_v9_0.h"
8d6a5230 27#include "amdgpu_atomfirmware.h"
2cddc50e 28#include "amdgpu_gem.h"
e60f8db5 29
75199b8c
FX		 30#include "hdp/hdp_4_0_offset.h"
31#include "hdp/hdp_4_0_sh_mask.h"
cde5c34f 32#include "gc/gc_9_0_sh_mask.h"
135d4b10
FX		 33#include "dce/dce_12_0_offset.h"
34#include "dce/dce_12_0_sh_mask.h"
fb960bd2 35#include "vega10_enum.h"
65417d9f 36#include "mmhub/mmhub_1_0_offset.h"
6ce68225 37#include "athub/athub_1_0_offset.h"
250b4228 38#include "oss/osssys_4_0_offset.h"
e60f8db5 39
946a4d5b 40#include "soc15.h"
e60f8db5 41#include "soc15_common.h"
90c7a935 42#include "umc/umc_6_0_sh_mask.h"
e60f8db5 43
e60f8db5
AX		 44#include "gfxhub_v1_0.h"
45#include "mmhub_v1_0.h"
bf0a60b7 46#include "gfxhub_v1_1.h"
e60f8db5 47
44a99b65
AG		 48#include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
49
ebdef28e
AD		 50/* add these here since we already include dce12 headers and these are for DCN */
51#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d
52#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
53#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0
54#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10
55#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL
56#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L
57
e60f8db5
AX		 58/* XXX Move this macro to VEGA10 header file, which is like vid.h for VI.*/
59#define AMDGPU_NUM_OF_VMIDS 8
60
61static const u32 golden_settings_vega10_hdp[] =
62{
63 0xf64, 0x0fffffff, 0x00000000,
64 0xf65, 0x0fffffff, 0x00000000,
65 0xf66, 0x0fffffff, 0x00000000,
66 0xf67, 0x0fffffff, 0x00000000,
67 0xf68, 0x0fffffff, 0x00000000,
68 0xf6a, 0x0fffffff, 0x00000000,
69 0xf6b, 0x0fffffff, 0x00000000,
70 0xf6c, 0x0fffffff, 0x00000000,
71 0xf6d, 0x0fffffff, 0x00000000,
72 0xf6e, 0x0fffffff, 0x00000000,
73};
74
946a4d5b 75static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] =
5c583018 76{
946a4d5b
SL		 77 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa),
78 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565)
5c583018
EQ		 79};
80
946a4d5b 81static const struct soc15_reg_golden golden_settings_athub_1_0_0[] =
5c583018 82{
946a4d5b
SL		 83 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800),
84 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008)
5c583018
EQ		 85};
86
02bab923
DP		 87/* Ecc related register addresses, (BASE + reg offset) */
88/* Universal Memory Controller caps (may be fused). */
89/* UMCCH:UmcLocalCap */
90#define UMCLOCALCAPS_ADDR0 (0x00014306 + 0x00000000)
91#define UMCLOCALCAPS_ADDR1 (0x00014306 + 0x00000800)
92#define UMCLOCALCAPS_ADDR2 (0x00014306 + 0x00001000)
93#define UMCLOCALCAPS_ADDR3 (0x00014306 + 0x00001800)
94#define UMCLOCALCAPS_ADDR4 (0x00054306 + 0x00000000)
95#define UMCLOCALCAPS_ADDR5 (0x00054306 + 0x00000800)
96#define UMCLOCALCAPS_ADDR6 (0x00054306 + 0x00001000)
97#define UMCLOCALCAPS_ADDR7 (0x00054306 + 0x00001800)
98#define UMCLOCALCAPS_ADDR8 (0x00094306 + 0x00000000)
99#define UMCLOCALCAPS_ADDR9 (0x00094306 + 0x00000800)
100#define UMCLOCALCAPS_ADDR10 (0x00094306 + 0x00001000)
101#define UMCLOCALCAPS_ADDR11 (0x00094306 + 0x00001800)
102#define UMCLOCALCAPS_ADDR12 (0x000d4306 + 0x00000000)
103#define UMCLOCALCAPS_ADDR13 (0x000d4306 + 0x00000800)
104#define UMCLOCALCAPS_ADDR14 (0x000d4306 + 0x00001000)
105#define UMCLOCALCAPS_ADDR15 (0x000d4306 + 0x00001800)
106
107/* Universal Memory Controller Channel config. */
108/* UMCCH:UMC_CONFIG */
109#define UMCCH_UMC_CONFIG_ADDR0 (0x00014040 + 0x00000000)
110#define UMCCH_UMC_CONFIG_ADDR1 (0x00014040 + 0x00000800)
111#define UMCCH_UMC_CONFIG_ADDR2 (0x00014040 + 0x00001000)
112#define UMCCH_UMC_CONFIG_ADDR3 (0x00014040 + 0x00001800)
113#define UMCCH_UMC_CONFIG_ADDR4 (0x00054040 + 0x00000000)
114#define UMCCH_UMC_CONFIG_ADDR5 (0x00054040 + 0x00000800)
115#define UMCCH_UMC_CONFIG_ADDR6 (0x00054040 + 0x00001000)
116#define UMCCH_UMC_CONFIG_ADDR7 (0x00054040 + 0x00001800)
117#define UMCCH_UMC_CONFIG_ADDR8 (0x00094040 + 0x00000000)
118#define UMCCH_UMC_CONFIG_ADDR9 (0x00094040 + 0x00000800)
119#define UMCCH_UMC_CONFIG_ADDR10 (0x00094040 + 0x00001000)
120#define UMCCH_UMC_CONFIG_ADDR11 (0x00094040 + 0x00001800)
121#define UMCCH_UMC_CONFIG_ADDR12 (0x000d4040 + 0x00000000)
122#define UMCCH_UMC_CONFIG_ADDR13 (0x000d4040 + 0x00000800)
123#define UMCCH_UMC_CONFIG_ADDR14 (0x000d4040 + 0x00001000)
124#define UMCCH_UMC_CONFIG_ADDR15 (0x000d4040 + 0x00001800)
125
126/* Universal Memory Controller Channel Ecc config. */
127/* UMCCH:EccCtrl */
128#define UMCCH_ECCCTRL_ADDR0 (0x00014053 + 0x00000000)
129#define UMCCH_ECCCTRL_ADDR1 (0x00014053 + 0x00000800)
130#define UMCCH_ECCCTRL_ADDR2 (0x00014053 + 0x00001000)
131#define UMCCH_ECCCTRL_ADDR3 (0x00014053 + 0x00001800)
132#define UMCCH_ECCCTRL_ADDR4 (0x00054053 + 0x00000000)
133#define UMCCH_ECCCTRL_ADDR5 (0x00054053 + 0x00000800)
134#define UMCCH_ECCCTRL_ADDR6 (0x00054053 + 0x00001000)
135#define UMCCH_ECCCTRL_ADDR7 (0x00054053 + 0x00001800)
136#define UMCCH_ECCCTRL_ADDR8 (0x00094053 + 0x00000000)
137#define UMCCH_ECCCTRL_ADDR9 (0x00094053 + 0x00000800)
138#define UMCCH_ECCCTRL_ADDR10 (0x00094053 + 0x00001000)
139#define UMCCH_ECCCTRL_ADDR11 (0x00094053 + 0x00001800)
140#define UMCCH_ECCCTRL_ADDR12 (0x000d4053 + 0x00000000)
141#define UMCCH_ECCCTRL_ADDR13 (0x000d4053 + 0x00000800)
142#define UMCCH_ECCCTRL_ADDR14 (0x000d4053 + 0x00001000)
143#define UMCCH_ECCCTRL_ADDR15 (0x000d4053 + 0x00001800)
144
145static const uint32_t ecc_umclocalcap_addrs[] = {
146 UMCLOCALCAPS_ADDR0,
147 UMCLOCALCAPS_ADDR1,
148 UMCLOCALCAPS_ADDR2,
149 UMCLOCALCAPS_ADDR3,
150 UMCLOCALCAPS_ADDR4,
151 UMCLOCALCAPS_ADDR5,
152 UMCLOCALCAPS_ADDR6,
153 UMCLOCALCAPS_ADDR7,
154 UMCLOCALCAPS_ADDR8,
155 UMCLOCALCAPS_ADDR9,
156 UMCLOCALCAPS_ADDR10,
157 UMCLOCALCAPS_ADDR11,
158 UMCLOCALCAPS_ADDR12,
159 UMCLOCALCAPS_ADDR13,
160 UMCLOCALCAPS_ADDR14,
161 UMCLOCALCAPS_ADDR15,
162};
163
164static const uint32_t ecc_umcch_umc_config_addrs[] = {
165 UMCCH_UMC_CONFIG_ADDR0,
166 UMCCH_UMC_CONFIG_ADDR1,
167 UMCCH_UMC_CONFIG_ADDR2,
168 UMCCH_UMC_CONFIG_ADDR3,
169 UMCCH_UMC_CONFIG_ADDR4,
170 UMCCH_UMC_CONFIG_ADDR5,
171 UMCCH_UMC_CONFIG_ADDR6,
172 UMCCH_UMC_CONFIG_ADDR7,
173 UMCCH_UMC_CONFIG_ADDR8,
174 UMCCH_UMC_CONFIG_ADDR9,
175 UMCCH_UMC_CONFIG_ADDR10,
176 UMCCH_UMC_CONFIG_ADDR11,
177 UMCCH_UMC_CONFIG_ADDR12,
178 UMCCH_UMC_CONFIG_ADDR13,
179 UMCCH_UMC_CONFIG_ADDR14,
180 UMCCH_UMC_CONFIG_ADDR15,
181};
182
183static const uint32_t ecc_umcch_eccctrl_addrs[] = {
184 UMCCH_ECCCTRL_ADDR0,
185 UMCCH_ECCCTRL_ADDR1,
186 UMCCH_ECCCTRL_ADDR2,
187 UMCCH_ECCCTRL_ADDR3,
188 UMCCH_ECCCTRL_ADDR4,
189 UMCCH_ECCCTRL_ADDR5,
190 UMCCH_ECCCTRL_ADDR6,
191 UMCCH_ECCCTRL_ADDR7,
192 UMCCH_ECCCTRL_ADDR8,
193 UMCCH_ECCCTRL_ADDR9,
194 UMCCH_ECCCTRL_ADDR10,
195 UMCCH_ECCCTRL_ADDR11,
196 UMCCH_ECCCTRL_ADDR12,
197 UMCCH_ECCCTRL_ADDR13,
198 UMCCH_ECCCTRL_ADDR14,
199 UMCCH_ECCCTRL_ADDR15,
200};
201
e60f8db5
AX		 202static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
203 struct amdgpu_irq_src *src,
204 unsigned type,
205 enum amdgpu_interrupt_state state)
206{
207 struct amdgpu_vmhub *hub;
ae6d1416 208 u32 tmp, reg, bits, i, j;
e60f8db5 209
11250164
CK		 210 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
211 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
212 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
213 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
214 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
215 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
216 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
217
e60f8db5
AX		 218 switch (state) {
219 case AMDGPU_IRQ_STATE_DISABLE:
ae6d1416
TSD		 220 for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) {
221 hub = &adev->vmhub[j];
222 for (i = 0; i < 16; i++) {
223 reg = hub->vm_context0_cntl + i;
224 tmp = RREG32(reg);
225 tmp &= ~bits;
226 WREG32(reg, tmp);
227 }
e60f8db5
AX		 228 }
229 break;
230 case AMDGPU_IRQ_STATE_ENABLE:
ae6d1416
TSD		 231 for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) {
232 hub = &adev->vmhub[j];
233 for (i = 0; i < 16; i++) {
234 reg = hub->vm_context0_cntl + i;
235 tmp = RREG32(reg);
236 tmp |= bits;
237 WREG32(reg, tmp);
238 }
e60f8db5 239 }
e60f8db5
AX		 240 default:
241 break;
242 }
243
244 return 0;
245}
246
247static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
248 struct amdgpu_irq_src *source,
249 struct amdgpu_iv_entry *entry)
250{
c4f46f22 251 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src];
4d6cbde3 252 uint32_t status = 0;
e60f8db5
AX		 253 u64 addr;
254
255 addr = (u64)entry->src_data[0] << 12;
256 addr |= ((u64)entry->src_data[1] & 0xf) << 44;
257
79a0c465 258 if (!amdgpu_sriov_vf(adev)) {
5a9b8e8a
CK		 259 status = RREG32(hub->vm_l2_pro_fault_status);
260 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
4d6cbde3 261 }
e60f8db5 262
4d6cbde3 263 if (printk_ratelimit()) {
efaa9646
AG		 264 struct amdgpu_task_info task_info = { 0 };
265
266 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
267
4d6cbde3 268 dev_err(adev->dev,
0c79c0bb 269 "[%s] VMC page fault (src_id:%u ring:%u vmid:%u pasid:%u, for process %s pid %d thread %s pid %d)\n",
c4f46f22
CK		 270 entry->vmid_src ? "mmhub" : "gfxhub",
271 entry->src_id, entry->ring_id, entry->vmid,
efaa9646
AG		 272 entry->pasid, task_info.process_name, task_info.tgid,
273 task_info.task_name, task_info.pid);
7d0aa376 274 dev_err(adev->dev, " in page starting at address 0x%016llx from %d\n",
4d6cbde3
FK		 275 addr, entry->client_id);
276 if (!amdgpu_sriov_vf(adev))
277 dev_err(adev->dev,
278 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
279 status);
79a0c465 280 }
e60f8db5
AX		 281
282 return 0;
283}
284
285static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = {
286 .set = gmc_v9_0_vm_fault_interrupt_state,
287 .process = gmc_v9_0_process_interrupt,
288};
289
290static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev)
291{
770d13b1
CK		 292 adev->gmc.vm_fault.num_types = 1;
293 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs;
e60f8db5
AX		 294}
295
c4f46f22 296static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid)
03f89feb
CK		 297{
298 u32 req = 0;
299
c4f46f22 300 /* invalidate using legacy mode on vmid*/
03f89feb 301 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
c4f46f22 302 PER_VMID_INVALIDATE_REQ, 1 << vmid);
03f89feb
CK		 303 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, 0);
304 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
305 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
306 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
307 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
308 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
309 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
310 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
311
312 return req;
313}
314
1849e737 315static signed long amdgpu_kiq_reg_write_reg_wait(struct amdgpu_device *adev,
3890d111
ED		 316 uint32_t reg0, uint32_t reg1,
317 uint32_t ref, uint32_t mask)
318{
319 signed long r, cnt = 0;
320 unsigned long flags;
321 uint32_t seq;
322 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
323 struct amdgpu_ring *ring = &kiq->ring;
324
3890d111
ED		 325 spin_lock_irqsave(&kiq->ring_lock, flags);
326
327 amdgpu_ring_alloc(ring, 32);
328 amdgpu_ring_emit_reg_write_reg_wait(ring, reg0, reg1,
329 ref, mask);
330 amdgpu_fence_emit_polling(ring, &seq);
331 amdgpu_ring_commit(ring);
332 spin_unlock_irqrestore(&kiq->ring_lock, flags);
333
334 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
335
ae74da3e
ED		 336 /* don't wait anymore for IRQ context */
337 if (r < 1 && in_interrupt())
3890d111
ED		 338 goto failed_kiq;
339
340 might_sleep();
341
342 while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
343 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
344 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
345 }
346
347 if (cnt > MAX_KIQ_REG_TRY)
348 goto failed_kiq;
349
350 return 0;
351
352failed_kiq:
353 pr_err("failed to invalidate tlb with kiq\n");
354 return r;
355}
356
e60f8db5
AX		 357/*
358 * GART
359 * VMID 0 is the physical GPU addresses as used by the kernel.
360 * VMIDs 1-15 are used for userspace clients and are handled
361 * by the amdgpu vm/hsa code.
362 */
363
364/**
132f34e4 365 * gmc_v9_0_flush_gpu_tlb - gart tlb flush callback
e60f8db5
AX		 366 *
367 * @adev: amdgpu_device pointer
368 * @vmid: vm instance to flush
369 *
370 * Flush the TLB for the requested page table.
371 */
132f34e4 372static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev,
e60f8db5
AX		 373 uint32_t vmid)
374{
375 /* Use register 17 for GART */
376 const unsigned eng = 17;
377 unsigned i, j;
3890d111 378 int r;
e60f8db5
AX		 379
380 for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
381 struct amdgpu_vmhub *hub = &adev->vmhub[i];
03f89feb 382 u32 tmp = gmc_v9_0_get_invalidate_req(vmid);
e60f8db5 383
fc0faf04 384 if (adev->gfx.kiq.ring.ready &&
ae74da3e
ED		 385 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) &&
386 !adev->in_gpu_reset) {
fc0faf04
ED		 387 r = amdgpu_kiq_reg_write_reg_wait(adev, hub->vm_inv_eng0_req + eng,
388 hub->vm_inv_eng0_ack + eng, tmp, 1 << vmid);
389 if (!r)
390 continue;
391 }
3890d111
ED		 392
393 spin_lock(&adev->gmc.invalidate_lock);
394
c7a7266b 395 WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);
e60f8db5
AX		 396
397 /* Busy wait for ACK.*/
398 for (j = 0; j < 100; j++) {
c7a7266b 399 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
e60f8db5
AX		 400 tmp &= 1 << vmid;
401 if (tmp)
402 break;
403 cpu_relax();
404 }
3890d111
ED		 405 if (j < 100) {
406 spin_unlock(&adev->gmc.invalidate_lock);
e60f8db5 407 continue;
3890d111 408 }
e60f8db5
AX		 409
410 /* Wait for ACK with a delay.*/
411 for (j = 0; j < adev->usec_timeout; j++) {
c7a7266b 412 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
e60f8db5
AX		 413 tmp &= 1 << vmid;
414 if (tmp)
415 break;
416 udelay(1);
417 }
3890d111
ED		 418 if (j < adev->usec_timeout) {
419 spin_unlock(&adev->gmc.invalidate_lock);
e60f8db5 420 continue;
3890d111
ED		 421 }
422 spin_unlock(&adev->gmc.invalidate_lock);
e60f8db5
AX		 423 DRM_ERROR("Timeout waiting for VM flush ACK!\n");
424 }
e60f8db5
AX		 425}
426
9096d6e5 427static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
c633c00b 428 unsigned vmid, uint64_t pd_addr)
9096d6e5 429{
250b4228
CK		 430 struct amdgpu_device *adev = ring->adev;
431 struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub];
9096d6e5 432 uint32_t req = gmc_v9_0_get_invalidate_req(vmid);
9096d6e5
CK		 433 unsigned eng = ring->vm_inv_eng;
434
9096d6e5
CK		 435 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid),
436 lower_32_bits(pd_addr));
437
438 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid),
439 upper_32_bits(pd_addr));
440
f8bc9037
AD		 441 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + eng,
442 hub->vm_inv_eng0_ack + eng,
443 req, 1 << vmid);
f732b6b3 444
9096d6e5
CK		 445 return pd_addr;
446}
447
c633c00b
CK		 448static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
449 unsigned pasid)
450{
451 struct amdgpu_device *adev = ring->adev;
452 uint32_t reg;
453
454 if (ring->funcs->vmhub == AMDGPU_GFXHUB)
455 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
456 else
457 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
458
459 amdgpu_ring_emit_wreg(ring, reg, pasid);
460}
461
e60f8db5 462/**
132f34e4 463 * gmc_v9_0_set_pte_pde - update the page tables using MMIO
e60f8db5
AX		 464 *
465 * @adev: amdgpu_device pointer
466 * @cpu_pt_addr: cpu address of the page table
467 * @gpu_page_idx: entry in the page table to update
468 * @addr: dst addr to write into pte/pde
469 * @flags: access flags
470 *
471 * Update the page tables using the CPU.
472 */
132f34e4
CK		 473static int gmc_v9_0_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr,
474 uint32_t gpu_page_idx, uint64_t addr,
475 uint64_t flags)
e60f8db5
AX		 476{
477 void __iomem *ptr = (void *)cpu_pt_addr;
478 uint64_t value;
479
480 /*
481 * PTE format on VEGA 10:
482 * 63:59 reserved
483 * 58:57 mtype
484 * 56 F
485 * 55 L
486 * 54 P
487 * 53 SW
488 * 52 T
489 * 50:48 reserved
490 * 47:12 4k physical page base address
491 * 11:7 fragment
492 * 6 write
493 * 5 read
494 * 4 exe
495 * 3 Z
496 * 2 snooped
497 * 1 system
498 * 0 valid
499 *
500 * PDE format on VEGA 10:
501 * 63:59 block fragment size
502 * 58:55 reserved
503 * 54 P
504 * 53:48 reserved
505 * 47:6 physical base address of PD or PTE
506 * 5:3 reserved
507 * 2 C
508 * 1 system
509 * 0 valid
510 */
511
512 /*
513 * The following is for PTE only. GART does not have PDEs.
514 */
515 value = addr & 0x0000FFFFFFFFF000ULL;
516 value |= flags;
517 writeq(value, ptr + (gpu_page_idx * 8));
518 return 0;
519}
520
521static uint64_t gmc_v9_0_get_vm_pte_flags(struct amdgpu_device *adev,
522 uint32_t flags)
523
524{
525 uint64_t pte_flag = 0;
526
527 if (flags & AMDGPU_VM_PAGE_EXECUTABLE)
528 pte_flag |= AMDGPU_PTE_EXECUTABLE;
529 if (flags & AMDGPU_VM_PAGE_READABLE)
530 pte_flag |= AMDGPU_PTE_READABLE;
531 if (flags & AMDGPU_VM_PAGE_WRITEABLE)
532 pte_flag |= AMDGPU_PTE_WRITEABLE;
533
534 switch (flags & AMDGPU_VM_MTYPE_MASK) {
535 case AMDGPU_VM_MTYPE_DEFAULT:
536 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
537 break;
538 case AMDGPU_VM_MTYPE_NC:
539 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
540 break;
541 case AMDGPU_VM_MTYPE_WC:
542 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_WC);
543 break;
544 case AMDGPU_VM_MTYPE_CC:
545 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_CC);
546 break;
547 case AMDGPU_VM_MTYPE_UC:
548 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_UC);
549 break;
550 default:
551 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
552 break;
553 }
554
555 if (flags & AMDGPU_VM_PAGE_PRT)
556 pte_flag |= AMDGPU_PTE_PRT;
557
558 return pte_flag;
559}
560
3de676d8
CK		 561static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
562 uint64_t *addr, uint64_t *flags)
e60f8db5 563{
bbc9fb10 564 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
3de676d8 565 *addr = adev->vm_manager.vram_base_offset + *addr -
770d13b1 566 adev->gmc.vram_start;
3de676d8 567 BUG_ON(*addr & 0xFFFF00000000003FULL);
6a42fd6f 568
770d13b1 569 if (!adev->gmc.translate_further)
6a42fd6f
CK		 570 return;
571
572 if (level == AMDGPU_VM_PDB1) {
573 /* Set the block fragment size */
574 if (!(*flags & AMDGPU_PDE_PTE))
575 *flags |= AMDGPU_PDE_BFS(0x9);
576
577 } else if (level == AMDGPU_VM_PDB0) {
578 if (*flags & AMDGPU_PDE_PTE)
579 *flags &= ~AMDGPU_PDE_PTE;
580 else
581 *flags |= AMDGPU_PTE_TF;
582 }
e60f8db5
AX		 583}
584
132f34e4
CK		 585static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = {
586 .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb,
9096d6e5 587 .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb,
c633c00b 588 .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping,
132f34e4 589 .set_pte_pde = gmc_v9_0_set_pte_pde,
b1166325
CK		 590 .get_vm_pte_flags = gmc_v9_0_get_vm_pte_flags,
591 .get_vm_pde = gmc_v9_0_get_vm_pde
e60f8db5
AX		 592};
593
132f34e4 594static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev)
e60f8db5 595{
f54b30d7 596 adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs;
e60f8db5
AX		 597}
598
599static int gmc_v9_0_early_init(void *handle)
600{
601 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
602
132f34e4 603 gmc_v9_0_set_gmc_funcs(adev);
e60f8db5
AX		 604 gmc_v9_0_set_irq_funcs(adev);
605
770d13b1
CK		 606 adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
607 adev->gmc.shared_aperture_end =
608 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
bfa8eea2 609 adev->gmc.private_aperture_start = 0x1000000000000000ULL;
770d13b1
CK		 610 adev->gmc.private_aperture_end =
611 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
a7ea6548 612
e60f8db5
AX		 613 return 0;
614}
615
02bab923
DP		 616static int gmc_v9_0_ecc_available(struct amdgpu_device *adev)
617{
618 uint32_t reg_val;
619 uint32_t reg_addr;
620 uint32_t field_val;
621 size_t i;
622 uint32_t fv2;
623 size_t lost_sheep;
624
625 DRM_DEBUG("ecc: gmc_v9_0_ecc_available()\n");
626
627 lost_sheep = 0;
628 for (i = 0; i < ARRAY_SIZE(ecc_umclocalcap_addrs); ++i) {
629 reg_addr = ecc_umclocalcap_addrs[i];
630 DRM_DEBUG("ecc: "
631 "UMCCH_UmcLocalCap[%zu]: reg_addr: 0x%08x\n",
632 i, reg_addr);
633 reg_val = RREG32(reg_addr);
634 field_val = REG_GET_FIELD(reg_val, UMCCH0_0_UmcLocalCap,
635 EccDis);
636 DRM_DEBUG("ecc: "
637 "reg_val: 0x%08x, "
638 "EccDis: 0x%08x, ",
639 reg_val, field_val);
640 if (field_val) {
641 DRM_ERROR("ecc: UmcLocalCap:EccDis is set.\n");
642 ++lost_sheep;
643 }
644 }
645
646 for (i = 0; i < ARRAY_SIZE(ecc_umcch_umc_config_addrs); ++i) {
647 reg_addr = ecc_umcch_umc_config_addrs[i];
648 DRM_DEBUG("ecc: "
649 "UMCCH0_0_UMC_CONFIG[%zu]: reg_addr: 0x%08x",
650 i, reg_addr);
651 reg_val = RREG32(reg_addr);
652 field_val = REG_GET_FIELD(reg_val, UMCCH0_0_UMC_CONFIG,
653 DramReady);
654 DRM_DEBUG("ecc: "
655 "reg_val: 0x%08x, "
656 "DramReady: 0x%08x\n",
657 reg_val, field_val);
658
659 if (!field_val) {
660 DRM_ERROR("ecc: UMC_CONFIG:DramReady is not set.\n");
661 ++lost_sheep;
662 }
663 }
664
665 for (i = 0; i < ARRAY_SIZE(ecc_umcch_eccctrl_addrs); ++i) {
666 reg_addr = ecc_umcch_eccctrl_addrs[i];
667 DRM_DEBUG("ecc: "
668 "UMCCH_EccCtrl[%zu]: reg_addr: 0x%08x, ",
669 i, reg_addr);
670 reg_val = RREG32(reg_addr);
671 field_val = REG_GET_FIELD(reg_val, UMCCH0_0_EccCtrl,
672 WrEccEn);
673 fv2 = REG_GET_FIELD(reg_val, UMCCH0_0_EccCtrl,
674 RdEccEn);
675 DRM_DEBUG("ecc: "
676 "reg_val: 0x%08x, "
677 "WrEccEn: 0x%08x, "
678 "RdEccEn: 0x%08x\n",
679 reg_val, field_val, fv2);
680
681 if (!field_val) {
5a16008f 682 DRM_DEBUG("ecc: WrEccEn is not set\n");
02bab923
DP		 683 ++lost_sheep;
684 }
685 if (!fv2) {
5a16008f 686 DRM_DEBUG("ecc: RdEccEn is not set\n");
02bab923
DP		 687 ++lost_sheep;
688 }
689 }
690
691 DRM_DEBUG("ecc: lost_sheep: %zu\n", lost_sheep);
692 return lost_sheep == 0;
693}
694
cd2b5623
AD		 695static bool gmc_v9_0_keep_stolen_memory(struct amdgpu_device *adev)
696{
697
698 /*
699 * TODO:
700 * Currently there is a bug where some memory client outside
701 * of the driver writes to first 8M of VRAM on S3 resume,
702 * this overrides GART which by default gets placed in first 8M and
703 * causes VM_FAULTS once GTT is accessed.
704 * Keep the stolen memory reservation until the while this is not solved.
705 * Also check code in gmc_v9_0_get_vbios_fb_size and gmc_v9_0_late_init
706 */
707 switch (adev->asic_type) {
6abc0c8f
AD		 708 case CHIP_VEGA10:
709 return true;
cd2b5623 710 case CHIP_RAVEN:
cd2b5623
AD		 711 case CHIP_VEGA12:
712 case CHIP_VEGA20:
713 default:
6abc0c8f 714 return false;
cd2b5623
AD		 715 }
716}
717
e60f8db5
AX		 718static int gmc_v9_0_late_init(void *handle)
719{
720 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
c5066129 721 /*
722 * The latest engine allocation on gfx9 is:
723 * Engine 0, 1: idle
724 * Engine 2, 3: firmware
725 * Engine 4~13: amdgpu ring, subject to change when ring number changes
726 * Engine 14~15: idle
727 * Engine 16: kfd tlb invalidation
728 * Engine 17: Gart flushes
729 */
730 unsigned vm_inv_eng[AMDGPU_MAX_VMHUBS] = { 4, 4 };
4789c463 731 unsigned i;
02bab923 732 int r;
4789c463 733
cd2b5623
AD		 734 if (!gmc_v9_0_keep_stolen_memory(adev))
735 amdgpu_bo_late_init(adev);
6f752ec2 736
4789c463
CK		 737 for(i = 0; i < adev->num_rings; ++i) {
738 struct amdgpu_ring *ring = adev->rings[i];
739 unsigned vmhub = ring->funcs->vmhub;
740
741 ring->vm_inv_eng = vm_inv_eng[vmhub]++;
775f55f1
TSD		 742 dev_info(adev->dev, "ring %u(%s) uses VM inv eng %u on hub %u\n",
743 ring->idx, ring->name, ring->vm_inv_eng,
744 ring->funcs->vmhub);
4789c463
CK		 745 }
746
c5066129 747 /* Engine 16 is used for KFD and 17 for GART flushes */
4789c463 748 for(i = 0; i < AMDGPU_MAX_VMHUBS; ++i)
c5066129 749 BUG_ON(vm_inv_eng[i] > 16);
4789c463 750
7b6cbae2 751 if (adev->asic_type == CHIP_VEGA10 && !amdgpu_sriov_vf(adev)) {
5ba4fa35
AD		 752 r = gmc_v9_0_ecc_available(adev);
753 if (r == 1) {
754 DRM_INFO("ECC is active.\n");
755 } else if (r == 0) {
756 DRM_INFO("ECC is not present.\n");
e1d1a772 757 adev->df_funcs->enable_ecc_force_par_wr_rmw(adev, false);
5ba4fa35
AD		 758 } else {
759 DRM_ERROR("gmc_v9_0_ecc_available() failed. r: %d\n", r);
760 return r;
761 }
02bab923
DP		 762 }
763
770d13b1 764 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
e60f8db5
AX		 765}
766
767static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
770d13b1 768 struct amdgpu_gmc *mc)
e60f8db5 769{
eeb2487d
ML		 770 u64 base = 0;
771 if (!amdgpu_sriov_vf(adev))
772 base = mmhub_v1_0_get_fb_location(adev);
6fdd68b1
AD		 773 /* add the xgmi offset of the physical node */
774 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
961c75cf
CK		 775 amdgpu_gmc_vram_location(adev, &adev->gmc, base);
776 amdgpu_gmc_gart_location(adev, mc);
c3e1b43c
CK		 777 if (!amdgpu_sriov_vf(adev))
778 amdgpu_gmc_agp_location(adev, mc);
bc099ee9 779 /* base offset of vram pages */
b6110c00 780 adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev);
6fdd68b1
AD		 781
782 /* XXX: add the xgmi offset of the physical node? */
783 adev->vm_manager.vram_base_offset +=
784 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
e60f8db5
AX		 785}
786
787/**
788 * gmc_v9_0_mc_init - initialize the memory controller driver params
789 *
790 * @adev: amdgpu_device pointer
791 *
792 * Look up the amount of vram, vram width, and decide how to place
793 * vram and gart within the GPU's physical address space.
794 * Returns 0 for success.
795 */
796static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
797{
e60f8db5 798 int chansize, numchan;
d6895ad3 799 int r;
e60f8db5 800
3d918c0e
SL		 801 if (amdgpu_emu_mode != 1)
802 adev->gmc.vram_width = amdgpu_atomfirmware_get_vram_width(adev);
770d13b1 803 if (!adev->gmc.vram_width) {
8d6a5230 804 /* hbm memory channel size */
585b7f16
TSD		 805 if (adev->flags & AMD_IS_APU)
806 chansize = 64;
807 else
808 chansize = 128;
8d6a5230 809
070706c0 810 numchan = adev->df_funcs->get_hbm_channel_number(adev);
770d13b1 811 adev->gmc.vram_width = numchan * chansize;
e60f8db5 812 }
e60f8db5 813
e60f8db5 814 /* size in MB on si */
770d13b1 815 adev->gmc.mc_vram_size =
bf383fb6 816 adev->nbio_funcs->get_memsize(adev) * 1024ULL * 1024ULL;
770d13b1 817 adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
d6895ad3
CK		 818
819 if (!(adev->flags & AMD_IS_APU)) {
820 r = amdgpu_device_resize_fb_bar(adev);
821 if (r)
822 return r;
823 }
770d13b1
CK		 824 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
825 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
e60f8db5 826
156a81be
CZ		 827#ifdef CONFIG_X86_64
828 if (adev->flags & AMD_IS_APU) {
829 adev->gmc.aper_base = gfxhub_v1_0_get_mc_fb_offset(adev);
830 adev->gmc.aper_size = adev->gmc.real_vram_size;
831 }
832#endif
e60f8db5 833 /* In case the PCI BAR is larger than the actual amount of vram */
770d13b1
CK		 834 adev->gmc.visible_vram_size = adev->gmc.aper_size;
835 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
836 adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
e60f8db5 837
c3db7b5a
AD		 838 /* set the gart size */
839 if (amdgpu_gart_size == -1) {
840 switch (adev->asic_type) {
841 case CHIP_VEGA10: /* all engines support GPUVM */
273a14cd 842 case CHIP_VEGA12: /* all engines support GPUVM */
d96b428c 843 case CHIP_VEGA20:
c3db7b5a 844 default:
fe19b862 845 adev->gmc.gart_size = 512ULL << 20;
c3db7b5a
AD		 846 break;
847 case CHIP_RAVEN: /* DCE SG support */
770d13b1 848 adev->gmc.gart_size = 1024ULL << 20;
c3db7b5a
AD		 849 break;
850 }
851 } else {
770d13b1 852 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
c3db7b5a
AD		 853 }
854
770d13b1 855 gmc_v9_0_vram_gtt_location(adev, &adev->gmc);
e60f8db5
AX		 856
857 return 0;
858}
859
860static int gmc_v9_0_gart_init(struct amdgpu_device *adev)
861{
862 int r;
863
1123b989 864 if (adev->gart.bo) {
e60f8db5
AX		 865 WARN(1, "VEGA10 PCIE GART already initialized\n");
866 return 0;
867 }
868 /* Initialize common gart structure */
869 r = amdgpu_gart_init(adev);
870 if (r)
871 return r;
872 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
873 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE(MTYPE_UC) |
874 AMDGPU_PTE_EXECUTABLE;
875 return amdgpu_gart_table_vram_alloc(adev);
876}
877
ebdef28e
AD		 878static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev)
879{
ebdef28e 880 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
ebdef28e
AD		 881 unsigned size;
882
6f752ec2
AG		 883 /*
884 * TODO Remove once GART corruption is resolved
885 * Check related code in gmc_v9_0_sw_fini
886 * */
cd2b5623
AD		 887 if (gmc_v9_0_keep_stolen_memory(adev))
888 return 9 * 1024 * 1024;
6f752ec2 889
ebdef28e
AD		 890 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
891 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */
892 } else {
893 u32 viewport;
894
895 switch (adev->asic_type) {
896 case CHIP_RAVEN:
897 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
898 size = (REG_GET_FIELD(viewport,
899 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
900 REG_GET_FIELD(viewport,
901 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) *
902 4);
903 break;
904 case CHIP_VEGA10:
905 case CHIP_VEGA12:
cd2b5623 906 case CHIP_VEGA20:
ebdef28e
AD		 907 default:
908 viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE);
909 size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
910 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) *
911 4);
912 break;
913 }
914 }
915 /* return 0 if the pre-OS buffer uses up most of vram */
916 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024))
917 return 0;
6f752ec2 918
ebdef28e
AD		 919 return size;
920}
921
e60f8db5
AX		 922static int gmc_v9_0_sw_init(void *handle)
923{
924 int r;
925 int dma_bits;
926 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
927
0c8c0847 928 gfxhub_v1_0_init(adev);
77f6c763 929 mmhub_v1_0_init(adev);
0c8c0847 930
770d13b1 931 spin_lock_init(&adev->gmc.invalidate_lock);
e60f8db5 932
1e09b053 933 adev->gmc.vram_type = amdgpu_atomfirmware_get_vram_type(adev);
fd66560b
HZ		 934 switch (adev->asic_type) {
935 case CHIP_RAVEN:
6a42fd6f 936 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
f3368128 937 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
6a42fd6f
CK		 938 } else {
939 /* vm_size is 128TB + 512GB for legacy 3-level page support */
940 amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48);
770d13b1 941 adev->gmc.translate_further =
6a42fd6f
CK		 942 adev->vm_manager.num_level > 1;
943 }
fd66560b
HZ		 944 break;
945 case CHIP_VEGA10:
273a14cd 946 case CHIP_VEGA12:
d96b428c 947 case CHIP_VEGA20:
36b32a68
ZJ		 948 /*
949 * To fulfill 4-level page support,
950 * vm size is 256TB (48bit), maximum size of Vega10,
951 * block size 512 (9bit)
952 */
f3368128 953 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
fd66560b
HZ		 954 break;
955 default:
956 break;
e60f8db5
AX		 957 }
958
959 /* This interrupt is VMC page fault.*/
44a99b65 960 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT,
770d13b1 961 &adev->gmc.vm_fault);
44a99b65 962 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT,
770d13b1 963 &adev->gmc.vm_fault);
e60f8db5
AX		 964
965 if (r)
966 return r;
967
e60f8db5
AX		 968 /* Set the internal MC address mask
969 * This is the max address of the GPU's
970 * internal address space.
971 */
770d13b1 972 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
e60f8db5
AX		 973
974 /* set DMA mask + need_dma32 flags.
975 * PCIE - can handle 44-bits.
976 * IGP - can handle 44-bits
977 * PCI - dma32 for legacy pci gart, 44 bits on vega10
978 */
979 adev->need_dma32 = false;
980 dma_bits = adev->need_dma32 ? 32 : 44;
981 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
982 if (r) {
983 adev->need_dma32 = true;
984 dma_bits = 32;
985 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
986 }
987 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
988 if (r) {
989 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
990 printk(KERN_WARNING "amdgpu: No coherent DMA available.\n");
991 }
fd5fd480 992 adev->need_swiotlb = drm_get_max_iomem() > ((u64)1 << dma_bits);
e60f8db5 993
bf0a60b7
AD		 994 if (adev->asic_type == CHIP_VEGA20) {
995 r = gfxhub_v1_1_get_xgmi_info(adev);
996 if (r)
997 return r;
998 }
999
e60f8db5
AX		 1000 r = gmc_v9_0_mc_init(adev);
1001 if (r)
1002 return r;
1003
ebdef28e
AD		 1004 adev->gmc.stolen_size = gmc_v9_0_get_vbios_fb_size(adev);
1005
e60f8db5
AX		 1006 /* Memory manager */
1007 r = amdgpu_bo_init(adev);
1008 if (r)
1009 return r;
1010
1011 r = gmc_v9_0_gart_init(adev);
1012 if (r)
1013 return r;
1014
05ec3eda
CK		 1015 /*
1016 * number of VMs
1017 * VMID 0 is reserved for System
1018 * amdgpu graphics/compute will use VMIDs 1-7
1019 * amdkfd will use VMIDs 8-15
1020 */
1021 adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids = AMDGPU_NUM_OF_VMIDS;
1022 adev->vm_manager.id_mgr[AMDGPU_MMHUB].num_ids = AMDGPU_NUM_OF_VMIDS;
1023
05ec3eda
CK		 1024 amdgpu_vm_manager_init(adev);
1025
1026 return 0;
e60f8db5
AX		 1027}
1028
e60f8db5
AX		 1029static int gmc_v9_0_sw_fini(void *handle)
1030{
1031 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1032
f59548c8 1033 amdgpu_gem_force_release(adev);
05ec3eda 1034 amdgpu_vm_manager_fini(adev);
6f752ec2 1035
cd2b5623
AD		 1036 if (gmc_v9_0_keep_stolen_memory(adev))
1037 amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, NULL);
6f752ec2 1038
a3d9103e 1039 amdgpu_gart_table_vram_free(adev);
e60f8db5 1040 amdgpu_bo_fini(adev);
a3d9103e 1041 amdgpu_gart_fini(adev);
e60f8db5
AX		 1042
1043 return 0;
1044}
1045
1046static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
1047{
946a4d5b 1048
e60f8db5
AX		 1049 switch (adev->asic_type) {
1050 case CHIP_VEGA10:
d96b428c 1051 case CHIP_VEGA20:
946a4d5b 1052 soc15_program_register_sequence(adev,
5c583018 1053 golden_settings_mmhub_1_0_0,
c47b41a7 1054 ARRAY_SIZE(golden_settings_mmhub_1_0_0));
946a4d5b 1055 soc15_program_register_sequence(adev,
5c583018 1056 golden_settings_athub_1_0_0,
c47b41a7 1057 ARRAY_SIZE(golden_settings_athub_1_0_0));
e60f8db5 1058 break;
273a14cd
AD		 1059 case CHIP_VEGA12:
1060 break;
e4f3abaa 1061 case CHIP_RAVEN:
946a4d5b 1062 soc15_program_register_sequence(adev,
5c583018 1063 golden_settings_athub_1_0_0,
c47b41a7 1064 ARRAY_SIZE(golden_settings_athub_1_0_0));
e4f3abaa 1065 break;
e60f8db5
AX		 1066 default:
1067 break;
1068 }
1069}
1070
1071/**
1072 * gmc_v9_0_gart_enable - gart enable
1073 *
1074 * @adev: amdgpu_device pointer
1075 */
1076static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
1077{
1078 int r;
1079 bool value;
1080 u32 tmp;
1081
9c3f2b54
AD		 1082 amdgpu_device_program_register_sequence(adev,
1083 golden_settings_vega10_hdp,
1084 ARRAY_SIZE(golden_settings_vega10_hdp));
e60f8db5 1085
1123b989 1086 if (adev->gart.bo == NULL) {
e60f8db5
AX		 1087 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
1088 return -EINVAL;
1089 }
ce1b1b66
ML		 1090 r = amdgpu_gart_table_vram_pin(adev);
1091 if (r)
1092 return r;
e60f8db5 1093
2fcd43ce
HZ		 1094 switch (adev->asic_type) {
1095 case CHIP_RAVEN:
f8386b35 1096 mmhub_v1_0_update_power_gating(adev, true);
2fcd43ce
HZ		 1097 break;
1098 default:
1099 break;
1100 }
1101
e60f8db5
AX		 1102 r = gfxhub_v1_0_gart_enable(adev);
1103 if (r)
1104 return r;
1105
1106 r = mmhub_v1_0_gart_enable(adev);
1107 if (r)
1108 return r;
1109
846347c9 1110 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
e60f8db5 1111
b9509c80
HR		 1112 tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL);
1113 WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);
e60f8db5 1114
1d4e0a8c 1115 /* After HDP is initialized, flush HDP.*/
69882565 1116 adev->nbio_funcs->hdp_flush(adev, NULL);
1d4e0a8c 1117
e60f8db5
AX		 1118 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
1119 value = false;
1120 else
1121 value = true;
1122
1123 gfxhub_v1_0_set_fault_enable_default(adev, value);
1124 mmhub_v1_0_set_fault_enable_default(adev, value);
132f34e4 1125 gmc_v9_0_flush_gpu_tlb(adev, 0);
e60f8db5
AX		 1126
1127 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
770d13b1 1128 (unsigned)(adev->gmc.gart_size >> 20),
4e830fb1 1129 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
e60f8db5
AX		 1130 adev->gart.ready = true;
1131 return 0;
1132}
1133
1134static int gmc_v9_0_hw_init(void *handle)
1135{
1136 int r;
1137 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1138
1139 /* The sequence of these two function calls matters.*/
1140 gmc_v9_0_init_golden_registers(adev);
1141
edca2d05 1142 if (adev->mode_info.num_crtc) {
edca2d05 1143 /* Lockout access through VGA aperture*/
4d9c333a 1144 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
edca2d05
AD		 1145
1146 /* disable VGA render */
4d9c333a 1147 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
edca2d05
AD		 1148 }
1149
e60f8db5
AX		 1150 r = gmc_v9_0_gart_enable(adev);
1151
1152 return r;
1153}
1154
1155/**
1156 * gmc_v9_0_gart_disable - gart disable
1157 *
1158 * @adev: amdgpu_device pointer
1159 *
1160 * This disables all VM page table.
1161 */
1162static void gmc_v9_0_gart_disable(struct amdgpu_device *adev)
1163{
1164 gfxhub_v1_0_gart_disable(adev);
1165 mmhub_v1_0_gart_disable(adev);
ce1b1b66 1166 amdgpu_gart_table_vram_unpin(adev);
e60f8db5
AX		 1167}
1168
1169static int gmc_v9_0_hw_fini(void *handle)
1170{
1171 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1172
5dd696ae
TH		 1173 if (amdgpu_sriov_vf(adev)) {
1174 /* full access mode, so don't touch any GMC register */
1175 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
1176 return 0;
1177 }
1178
770d13b1 1179 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
e60f8db5
AX		 1180 gmc_v9_0_gart_disable(adev);
1181
1182 return 0;
1183}
1184
1185static int gmc_v9_0_suspend(void *handle)
1186{
1187 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1188
f053cd47 1189 return gmc_v9_0_hw_fini(adev);
e60f8db5
AX		 1190}
1191
1192static int gmc_v9_0_resume(void *handle)
1193{
1194 int r;
1195 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1196
1197 r = gmc_v9_0_hw_init(adev);
1198 if (r)
1199 return r;
1200
620f774f 1201 amdgpu_vmid_reset_all(adev);
e60f8db5 1202
32601d48 1203 return 0;
e60f8db5
AX		 1204}
1205
1206static bool gmc_v9_0_is_idle(void *handle)
1207{
1208 /* MC is always ready in GMC v9.*/
1209 return true;
1210}
1211
1212static int gmc_v9_0_wait_for_idle(void *handle)
1213{
1214 /* There is no need to wait for MC idle in GMC v9.*/
1215 return 0;
1216}
1217
1218static int gmc_v9_0_soft_reset(void *handle)
1219{
1220 /* XXX for emulation.*/
1221 return 0;
1222}
1223
1224static int gmc_v9_0_set_clockgating_state(void *handle,
1225 enum amd_clockgating_state state)
1226{
d5583d4f
HR		 1227 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1228
1229 return mmhub_v1_0_set_clockgating(adev, state);
e60f8db5
AX		 1230}
1231
13052be5
HR		 1232static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags)
1233{
1234 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1235
1236 mmhub_v1_0_get_clockgating(adev, flags);
1237}
1238
e60f8db5
AX		 1239static int gmc_v9_0_set_powergating_state(void *handle,
1240 enum amd_powergating_state state)
1241{
1242 return 0;
1243}
1244
1245const struct amd_ip_funcs gmc_v9_0_ip_funcs = {
1246 .name = "gmc_v9_0",
1247 .early_init = gmc_v9_0_early_init,
1248 .late_init = gmc_v9_0_late_init,
1249 .sw_init = gmc_v9_0_sw_init,
1250 .sw_fini = gmc_v9_0_sw_fini,
1251 .hw_init = gmc_v9_0_hw_init,
1252 .hw_fini = gmc_v9_0_hw_fini,
1253 .suspend = gmc_v9_0_suspend,
1254 .resume = gmc_v9_0_resume,
1255 .is_idle = gmc_v9_0_is_idle,
1256 .wait_for_idle = gmc_v9_0_wait_for_idle,
1257 .soft_reset = gmc_v9_0_soft_reset,
1258 .set_clockgating_state = gmc_v9_0_set_clockgating_state,
1259 .set_powergating_state = gmc_v9_0_set_powergating_state,
13052be5 1260 .get_clockgating_state = gmc_v9_0_get_clockgating_state,
e60f8db5
AX		 1261};
1262
1263const struct amdgpu_ip_block_version gmc_v9_0_ip_block =
1264{
1265 .type = AMD_IP_BLOCK_TYPE_GMC,
1266 .major = 9,
1267 .minor = 0,
1268 .rev = 0,
1269 .funcs = &gmc_v9_0_ip_funcs,
1270};
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