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e60f8db5 AX |
1 | /* |
2 | * Copyright 2016 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | */ | |
f867723b | 23 | |
e60f8db5 | 24 | #include <linux/firmware.h> |
f867723b SR |
25 | #include <linux/pci.h> |
26 | ||
fd5fd480 | 27 | #include <drm/drm_cache.h> |
f867723b | 28 | |
e60f8db5 AX |
29 | #include "amdgpu.h" |
30 | #include "gmc_v9_0.h" | |
8d6a5230 | 31 | #include "amdgpu_atomfirmware.h" |
2cddc50e | 32 | #include "amdgpu_gem.h" |
e60f8db5 | 33 | |
75199b8c FX |
34 | #include "hdp/hdp_4_0_offset.h" |
35 | #include "hdp/hdp_4_0_sh_mask.h" | |
cde5c34f | 36 | #include "gc/gc_9_0_sh_mask.h" |
135d4b10 FX |
37 | #include "dce/dce_12_0_offset.h" |
38 | #include "dce/dce_12_0_sh_mask.h" | |
fb960bd2 | 39 | #include "vega10_enum.h" |
65417d9f | 40 | #include "mmhub/mmhub_1_0_offset.h" |
6ce68225 | 41 | #include "athub/athub_1_0_offset.h" |
250b4228 | 42 | #include "oss/osssys_4_0_offset.h" |
e60f8db5 | 43 | |
946a4d5b | 44 | #include "soc15.h" |
e60f8db5 | 45 | #include "soc15_common.h" |
90c7a935 | 46 | #include "umc/umc_6_0_sh_mask.h" |
e60f8db5 | 47 | |
e60f8db5 AX |
48 | #include "gfxhub_v1_0.h" |
49 | #include "mmhub_v1_0.h" | |
bee7b51a | 50 | #include "athub_v1_0.h" |
bf0a60b7 | 51 | #include "gfxhub_v1_1.h" |
51cce480 | 52 | #include "mmhub_v9_4.h" |
5b6b35aa | 53 | #include "umc_v6_1.h" |
e60f8db5 | 54 | |
44a99b65 AG |
55 | #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" |
56 | ||
791c4769 | 57 | #include "amdgpu_ras.h" |
029fbd43 | 58 | #include "amdgpu_xgmi.h" |
791c4769 | 59 | |
ebdef28e AD |
60 | /* add these here since we already include dce12 headers and these are for DCN */ |
61 | #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d | |
62 | #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 | |
63 | #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 | |
64 | #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 | |
65 | #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL | |
66 | #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L | |
67 | ||
e60f8db5 AX |
68 | /* XXX Move this macro to VEGA10 header file, which is like vid.h for VI.*/ |
69 | #define AMDGPU_NUM_OF_VMIDS 8 | |
70 | ||
71 | static const u32 golden_settings_vega10_hdp[] = | |
72 | { | |
73 | 0xf64, 0x0fffffff, 0x00000000, | |
74 | 0xf65, 0x0fffffff, 0x00000000, | |
75 | 0xf66, 0x0fffffff, 0x00000000, | |
76 | 0xf67, 0x0fffffff, 0x00000000, | |
77 | 0xf68, 0x0fffffff, 0x00000000, | |
78 | 0xf6a, 0x0fffffff, 0x00000000, | |
79 | 0xf6b, 0x0fffffff, 0x00000000, | |
80 | 0xf6c, 0x0fffffff, 0x00000000, | |
81 | 0xf6d, 0x0fffffff, 0x00000000, | |
82 | 0xf6e, 0x0fffffff, 0x00000000, | |
83 | }; | |
84 | ||
946a4d5b | 85 | static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] = |
5c583018 | 86 | { |
946a4d5b SL |
87 | SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa), |
88 | SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565) | |
5c583018 EQ |
89 | }; |
90 | ||
946a4d5b | 91 | static const struct soc15_reg_golden golden_settings_athub_1_0_0[] = |
5c583018 | 92 | { |
946a4d5b SL |
93 | SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800), |
94 | SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008) | |
5c583018 EQ |
95 | }; |
96 | ||
791c4769 | 97 | static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = { |
98 | (0x000143c0 + 0x00000000), | |
99 | (0x000143c0 + 0x00000800), | |
100 | (0x000143c0 + 0x00001000), | |
101 | (0x000143c0 + 0x00001800), | |
102 | (0x000543c0 + 0x00000000), | |
103 | (0x000543c0 + 0x00000800), | |
104 | (0x000543c0 + 0x00001000), | |
105 | (0x000543c0 + 0x00001800), | |
106 | (0x000943c0 + 0x00000000), | |
107 | (0x000943c0 + 0x00000800), | |
108 | (0x000943c0 + 0x00001000), | |
109 | (0x000943c0 + 0x00001800), | |
110 | (0x000d43c0 + 0x00000000), | |
111 | (0x000d43c0 + 0x00000800), | |
112 | (0x000d43c0 + 0x00001000), | |
113 | (0x000d43c0 + 0x00001800), | |
114 | (0x001143c0 + 0x00000000), | |
115 | (0x001143c0 + 0x00000800), | |
116 | (0x001143c0 + 0x00001000), | |
117 | (0x001143c0 + 0x00001800), | |
118 | (0x001543c0 + 0x00000000), | |
119 | (0x001543c0 + 0x00000800), | |
120 | (0x001543c0 + 0x00001000), | |
121 | (0x001543c0 + 0x00001800), | |
122 | (0x001943c0 + 0x00000000), | |
123 | (0x001943c0 + 0x00000800), | |
124 | (0x001943c0 + 0x00001000), | |
125 | (0x001943c0 + 0x00001800), | |
126 | (0x001d43c0 + 0x00000000), | |
127 | (0x001d43c0 + 0x00000800), | |
128 | (0x001d43c0 + 0x00001000), | |
129 | (0x001d43c0 + 0x00001800), | |
02bab923 DP |
130 | }; |
131 | ||
791c4769 | 132 | static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = { |
133 | (0x000143e0 + 0x00000000), | |
134 | (0x000143e0 + 0x00000800), | |
135 | (0x000143e0 + 0x00001000), | |
136 | (0x000143e0 + 0x00001800), | |
137 | (0x000543e0 + 0x00000000), | |
138 | (0x000543e0 + 0x00000800), | |
139 | (0x000543e0 + 0x00001000), | |
140 | (0x000543e0 + 0x00001800), | |
141 | (0x000943e0 + 0x00000000), | |
142 | (0x000943e0 + 0x00000800), | |
143 | (0x000943e0 + 0x00001000), | |
144 | (0x000943e0 + 0x00001800), | |
145 | (0x000d43e0 + 0x00000000), | |
146 | (0x000d43e0 + 0x00000800), | |
147 | (0x000d43e0 + 0x00001000), | |
148 | (0x000d43e0 + 0x00001800), | |
149 | (0x001143e0 + 0x00000000), | |
150 | (0x001143e0 + 0x00000800), | |
151 | (0x001143e0 + 0x00001000), | |
152 | (0x001143e0 + 0x00001800), | |
153 | (0x001543e0 + 0x00000000), | |
154 | (0x001543e0 + 0x00000800), | |
155 | (0x001543e0 + 0x00001000), | |
156 | (0x001543e0 + 0x00001800), | |
157 | (0x001943e0 + 0x00000000), | |
158 | (0x001943e0 + 0x00000800), | |
159 | (0x001943e0 + 0x00001000), | |
160 | (0x001943e0 + 0x00001800), | |
161 | (0x001d43e0 + 0x00000000), | |
162 | (0x001d43e0 + 0x00000800), | |
163 | (0x001d43e0 + 0x00001000), | |
164 | (0x001d43e0 + 0x00001800), | |
02bab923 DP |
165 | }; |
166 | ||
791c4769 | 167 | static const uint32_t ecc_umc_mcumc_status_addrs[] = { |
168 | (0x000143c2 + 0x00000000), | |
169 | (0x000143c2 + 0x00000800), | |
170 | (0x000143c2 + 0x00001000), | |
171 | (0x000143c2 + 0x00001800), | |
172 | (0x000543c2 + 0x00000000), | |
173 | (0x000543c2 + 0x00000800), | |
174 | (0x000543c2 + 0x00001000), | |
175 | (0x000543c2 + 0x00001800), | |
176 | (0x000943c2 + 0x00000000), | |
177 | (0x000943c2 + 0x00000800), | |
178 | (0x000943c2 + 0x00001000), | |
179 | (0x000943c2 + 0x00001800), | |
180 | (0x000d43c2 + 0x00000000), | |
181 | (0x000d43c2 + 0x00000800), | |
182 | (0x000d43c2 + 0x00001000), | |
183 | (0x000d43c2 + 0x00001800), | |
184 | (0x001143c2 + 0x00000000), | |
185 | (0x001143c2 + 0x00000800), | |
186 | (0x001143c2 + 0x00001000), | |
187 | (0x001143c2 + 0x00001800), | |
188 | (0x001543c2 + 0x00000000), | |
189 | (0x001543c2 + 0x00000800), | |
190 | (0x001543c2 + 0x00001000), | |
191 | (0x001543c2 + 0x00001800), | |
192 | (0x001943c2 + 0x00000000), | |
193 | (0x001943c2 + 0x00000800), | |
194 | (0x001943c2 + 0x00001000), | |
195 | (0x001943c2 + 0x00001800), | |
196 | (0x001d43c2 + 0x00000000), | |
197 | (0x001d43c2 + 0x00000800), | |
198 | (0x001d43c2 + 0x00001000), | |
199 | (0x001d43c2 + 0x00001800), | |
02bab923 DP |
200 | }; |
201 | ||
791c4769 | 202 | static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev, |
203 | struct amdgpu_irq_src *src, | |
204 | unsigned type, | |
205 | enum amdgpu_interrupt_state state) | |
206 | { | |
207 | u32 bits, i, tmp, reg; | |
208 | ||
209 | bits = 0x7f; | |
210 | ||
211 | switch (state) { | |
212 | case AMDGPU_IRQ_STATE_DISABLE: | |
213 | for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { | |
214 | reg = ecc_umc_mcumc_ctrl_addrs[i]; | |
215 | tmp = RREG32(reg); | |
216 | tmp &= ~bits; | |
217 | WREG32(reg, tmp); | |
218 | } | |
219 | for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { | |
220 | reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; | |
221 | tmp = RREG32(reg); | |
222 | tmp &= ~bits; | |
223 | WREG32(reg, tmp); | |
224 | } | |
225 | break; | |
226 | case AMDGPU_IRQ_STATE_ENABLE: | |
227 | for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { | |
228 | reg = ecc_umc_mcumc_ctrl_addrs[i]; | |
229 | tmp = RREG32(reg); | |
230 | tmp |= bits; | |
231 | WREG32(reg, tmp); | |
232 | } | |
233 | for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { | |
234 | reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; | |
235 | tmp = RREG32(reg); | |
236 | tmp |= bits; | |
237 | WREG32(reg, tmp); | |
238 | } | |
239 | break; | |
240 | default: | |
241 | break; | |
242 | } | |
243 | ||
244 | return 0; | |
245 | } | |
246 | ||
247 | static int gmc_v9_0_process_ras_data_cb(struct amdgpu_device *adev, | |
81e02619 | 248 | struct ras_err_data *err_data, |
791c4769 | 249 | struct amdgpu_iv_entry *entry) |
250 | { | |
87d2b92f TZ |
251 | if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) |
252 | return AMDGPU_RAS_SUCCESS; | |
253 | ||
254 | kgd2kfd_set_sram_ecc_flag(adev->kfd.dev); | |
255 | if (adev->umc.funcs && | |
256 | adev->umc.funcs->query_ras_error_count) | |
257 | adev->umc.funcs->query_ras_error_count(adev, err_data); | |
258 | ||
259 | if (adev->umc.funcs && | |
260 | adev->umc.funcs->query_ras_error_address && | |
261 | adev->umc.max_ras_err_cnt_per_query) { | |
262 | err_data->err_addr = | |
263 | kcalloc(adev->umc.max_ras_err_cnt_per_query, | |
264 | sizeof(struct eeprom_table_record), GFP_KERNEL); | |
265 | /* still call query_ras_error_address to clear error status | |
266 | * even NOMEM error is encountered | |
267 | */ | |
268 | if(!err_data->err_addr) | |
269 | DRM_WARN("Failed to alloc memory for umc error address record!\n"); | |
270 | ||
7c6e68c7 AG |
271 | /* umc query_ras_error_address is also responsible for clearing |
272 | * error status | |
273 | */ | |
87d2b92f TZ |
274 | adev->umc.funcs->query_ras_error_address(adev, err_data); |
275 | } | |
276 | ||
277 | /* only uncorrectable error needs gpu reset */ | |
278 | if (err_data->ue_count) { | |
279 | if (err_data->err_addr_cnt && | |
280 | amdgpu_ras_add_bad_pages(adev, err_data->err_addr, | |
281 | err_data->err_addr_cnt)) | |
282 | DRM_WARN("Failed to add ras bad page!\n"); | |
91ba68f8 | 283 | |
87d2b92f | 284 | amdgpu_ras_reset_gpu(adev, 0); |
7c6e68c7 | 285 | } |
91ba68f8 | 286 | |
87d2b92f | 287 | kfree(err_data->err_addr); |
bd2280da | 288 | return AMDGPU_RAS_SUCCESS; |
791c4769 | 289 | } |
290 | ||
291 | static int gmc_v9_0_process_ecc_irq(struct amdgpu_device *adev, | |
292 | struct amdgpu_irq_src *source, | |
293 | struct amdgpu_iv_entry *entry) | |
294 | { | |
145b03eb | 295 | struct ras_common_if *ras_if = adev->gmc.umc_ras_if; |
791c4769 | 296 | struct ras_dispatch_if ih_data = { |
791c4769 | 297 | .entry = entry, |
298 | }; | |
14cfde84 | 299 | |
300 | if (!ras_if) | |
301 | return 0; | |
302 | ||
303 | ih_data.head = *ras_if; | |
304 | ||
791c4769 | 305 | amdgpu_ras_interrupt_dispatch(adev, &ih_data); |
306 | return 0; | |
307 | } | |
308 | ||
e60f8db5 AX |
309 | static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, |
310 | struct amdgpu_irq_src *src, | |
311 | unsigned type, | |
312 | enum amdgpu_interrupt_state state) | |
313 | { | |
314 | struct amdgpu_vmhub *hub; | |
ae6d1416 | 315 | u32 tmp, reg, bits, i, j; |
e60f8db5 | 316 | |
11250164 CK |
317 | bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | |
318 | VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | | |
319 | VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | | |
320 | VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | | |
321 | VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | | |
322 | VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | | |
323 | VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; | |
324 | ||
e60f8db5 AX |
325 | switch (state) { |
326 | case AMDGPU_IRQ_STATE_DISABLE: | |
1daa2bfa | 327 | for (j = 0; j < adev->num_vmhubs; j++) { |
ae6d1416 TSD |
328 | hub = &adev->vmhub[j]; |
329 | for (i = 0; i < 16; i++) { | |
330 | reg = hub->vm_context0_cntl + i; | |
331 | tmp = RREG32(reg); | |
332 | tmp &= ~bits; | |
333 | WREG32(reg, tmp); | |
334 | } | |
e60f8db5 AX |
335 | } |
336 | break; | |
337 | case AMDGPU_IRQ_STATE_ENABLE: | |
1daa2bfa | 338 | for (j = 0; j < adev->num_vmhubs; j++) { |
ae6d1416 TSD |
339 | hub = &adev->vmhub[j]; |
340 | for (i = 0; i < 16; i++) { | |
341 | reg = hub->vm_context0_cntl + i; | |
342 | tmp = RREG32(reg); | |
343 | tmp |= bits; | |
344 | WREG32(reg, tmp); | |
345 | } | |
e60f8db5 | 346 | } |
e60f8db5 AX |
347 | default: |
348 | break; | |
349 | } | |
350 | ||
351 | return 0; | |
352 | } | |
353 | ||
354 | static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, | |
355 | struct amdgpu_irq_src *source, | |
356 | struct amdgpu_iv_entry *entry) | |
357 | { | |
51c60898 | 358 | struct amdgpu_vmhub *hub; |
c468f9e2 | 359 | bool retry_fault = !!(entry->src_data[1] & 0x80); |
4d6cbde3 | 360 | uint32_t status = 0; |
e60f8db5 | 361 | u64 addr; |
51c60898 | 362 | char hub_name[10]; |
e60f8db5 AX |
363 | |
364 | addr = (u64)entry->src_data[0] << 12; | |
365 | addr |= ((u64)entry->src_data[1] & 0xf) << 44; | |
366 | ||
c1a8abd9 CK |
367 | if (retry_fault && amdgpu_gmc_filter_faults(adev, addr, entry->pasid, |
368 | entry->timestamp)) | |
22666cc1 CK |
369 | return 1; /* This also prevents sending it to KFD */ |
370 | ||
51c60898 LM |
371 | if (entry->client_id == SOC15_IH_CLIENTID_VMC) { |
372 | snprintf(hub_name, sizeof(hub_name), "mmhub0"); | |
373 | hub = &adev->vmhub[AMDGPU_MMHUB_0]; | |
374 | } else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) { | |
375 | snprintf(hub_name, sizeof(hub_name), "mmhub1"); | |
376 | hub = &adev->vmhub[AMDGPU_MMHUB_1]; | |
377 | } else { | |
378 | snprintf(hub_name, sizeof(hub_name), "gfxhub0"); | |
379 | hub = &adev->vmhub[AMDGPU_GFXHUB_0]; | |
380 | } | |
381 | ||
c1a8abd9 | 382 | /* If it's the first fault for this address, process it normally */ |
ec671737 CK |
383 | if (retry_fault && !in_interrupt() && |
384 | amdgpu_vm_handle_fault(adev, entry->pasid, addr)) | |
385 | return 1; /* This also prevents sending it to KFD */ | |
386 | ||
79a0c465 | 387 | if (!amdgpu_sriov_vf(adev)) { |
53499173 XY |
388 | /* |
389 | * Issue a dummy read to wait for the status register to | |
390 | * be updated to avoid reading an incorrect value due to | |
391 | * the new fast GRBM interface. | |
392 | */ | |
393 | if (entry->vmid_src == AMDGPU_GFXHUB_0) | |
394 | RREG32(hub->vm_l2_pro_fault_status); | |
395 | ||
5a9b8e8a CK |
396 | status = RREG32(hub->vm_l2_pro_fault_status); |
397 | WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); | |
4d6cbde3 | 398 | } |
e60f8db5 | 399 | |
4d6cbde3 | 400 | if (printk_ratelimit()) { |
05794eff | 401 | struct amdgpu_task_info task_info; |
efaa9646 | 402 | |
05794eff | 403 | memset(&task_info, 0, sizeof(struct amdgpu_task_info)); |
efaa9646 AG |
404 | amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); |
405 | ||
4d6cbde3 | 406 | dev_err(adev->dev, |
c468f9e2 CK |
407 | "[%s] %s page fault (src_id:%u ring:%u vmid:%u " |
408 | "pasid:%u, for process %s pid %d thread %s pid %d)\n", | |
51c60898 | 409 | hub_name, retry_fault ? "retry" : "no-retry", |
c4f46f22 | 410 | entry->src_id, entry->ring_id, entry->vmid, |
efaa9646 AG |
411 | entry->pasid, task_info.process_name, task_info.tgid, |
412 | task_info.task_name, task_info.pid); | |
5ddd4a9a | 413 | dev_err(adev->dev, " in page starting at address 0x%016llx from client %d\n", |
4d6cbde3 | 414 | addr, entry->client_id); |
5ddd4a9a | 415 | if (!amdgpu_sriov_vf(adev)) { |
4d6cbde3 FK |
416 | dev_err(adev->dev, |
417 | "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", | |
418 | status); | |
5ddd4a9a YZ |
419 | dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", |
420 | REG_GET_FIELD(status, | |
421 | VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); | |
422 | dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", | |
423 | REG_GET_FIELD(status, | |
424 | VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); | |
425 | dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", | |
426 | REG_GET_FIELD(status, | |
427 | VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); | |
428 | dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", | |
429 | REG_GET_FIELD(status, | |
430 | VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); | |
4e0ae5e2 YZ |
431 | dev_err(adev->dev, "\t RW: 0x%lx\n", |
432 | REG_GET_FIELD(status, | |
433 | VM_L2_PROTECTION_FAULT_STATUS, RW)); | |
5ddd4a9a YZ |
434 | |
435 | } | |
79a0c465 | 436 | } |
e60f8db5 AX |
437 | |
438 | return 0; | |
439 | } | |
440 | ||
441 | static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = { | |
442 | .set = gmc_v9_0_vm_fault_interrupt_state, | |
443 | .process = gmc_v9_0_process_interrupt, | |
444 | }; | |
445 | ||
791c4769 | 446 | |
447 | static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = { | |
448 | .set = gmc_v9_0_ecc_interrupt_state, | |
449 | .process = gmc_v9_0_process_ecc_irq, | |
450 | }; | |
451 | ||
e60f8db5 AX |
452 | static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev) |
453 | { | |
770d13b1 CK |
454 | adev->gmc.vm_fault.num_types = 1; |
455 | adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs; | |
791c4769 | 456 | |
457 | adev->gmc.ecc_irq.num_types = 1; | |
458 | adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs; | |
e60f8db5 AX |
459 | } |
460 | ||
2a79d868 YZ |
461 | static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid, |
462 | uint32_t flush_type) | |
03f89feb CK |
463 | { |
464 | u32 req = 0; | |
465 | ||
03f89feb | 466 | req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, |
c4f46f22 | 467 | PER_VMID_INVALIDATE_REQ, 1 << vmid); |
2a79d868 | 468 | req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); |
03f89feb CK |
469 | req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); |
470 | req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); | |
471 | req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); | |
472 | req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); | |
473 | req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); | |
474 | req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, | |
475 | CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); | |
476 | ||
477 | return req; | |
478 | } | |
479 | ||
e60f8db5 AX |
480 | /* |
481 | * GART | |
482 | * VMID 0 is the physical GPU addresses as used by the kernel. | |
483 | * VMIDs 1-15 are used for userspace clients and are handled | |
484 | * by the amdgpu vm/hsa code. | |
485 | */ | |
486 | ||
487 | /** | |
2a79d868 | 488 | * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type |
e60f8db5 AX |
489 | * |
490 | * @adev: amdgpu_device pointer | |
491 | * @vmid: vm instance to flush | |
2a79d868 | 492 | * @flush_type: the flush type |
e60f8db5 | 493 | * |
2a79d868 | 494 | * Flush the TLB for the requested page table using certain type. |
e60f8db5 | 495 | */ |
3ff98548 OZ |
496 | static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, |
497 | uint32_t vmhub, uint32_t flush_type) | |
e60f8db5 | 498 | { |
e60f8db5 | 499 | const unsigned eng = 17; |
3ff98548 OZ |
500 | u32 j, tmp; |
501 | struct amdgpu_vmhub *hub; | |
e60f8db5 | 502 | |
3ff98548 | 503 | BUG_ON(vmhub >= adev->num_vmhubs); |
e60f8db5 | 504 | |
3ff98548 OZ |
505 | hub = &adev->vmhub[vmhub]; |
506 | tmp = gmc_v9_0_get_invalidate_req(vmid, flush_type); | |
3890d111 | 507 | |
3ff98548 OZ |
508 | /* This is necessary for a HW workaround under SRIOV as well |
509 | * as GFXOFF under bare metal | |
510 | */ | |
511 | if (adev->gfx.kiq.ring.sched.ready && | |
512 | (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) && | |
513 | !adev->in_gpu_reset) { | |
514 | uint32_t req = hub->vm_inv_eng0_req + eng; | |
515 | uint32_t ack = hub->vm_inv_eng0_ack + eng; | |
516 | ||
517 | amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, tmp, | |
518 | 1 << vmid); | |
519 | return; | |
520 | } | |
396557b0 | 521 | |
3ff98548 OZ |
522 | spin_lock(&adev->gmc.invalidate_lock); |
523 | WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp); | |
53499173 XY |
524 | |
525 | /* | |
526 | * Issue a dummy read to wait for the ACK register to be cleared | |
527 | * to avoid a false ACK due to the new fast GRBM interface. | |
528 | */ | |
529 | if (vmhub == AMDGPU_GFXHUB_0) | |
530 | RREG32_NO_KIQ(hub->vm_inv_eng0_req + eng); | |
531 | ||
3ff98548 OZ |
532 | for (j = 0; j < adev->usec_timeout; j++) { |
533 | tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng); | |
534 | if (tmp & (1 << vmid)) | |
535 | break; | |
536 | udelay(1); | |
e60f8db5 | 537 | } |
3ff98548 OZ |
538 | spin_unlock(&adev->gmc.invalidate_lock); |
539 | if (j < adev->usec_timeout) | |
540 | return; | |
541 | ||
542 | DRM_ERROR("Timeout waiting for VM flush ACK!\n"); | |
e60f8db5 AX |
543 | } |
544 | ||
9096d6e5 | 545 | static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, |
c633c00b | 546 | unsigned vmid, uint64_t pd_addr) |
9096d6e5 | 547 | { |
250b4228 CK |
548 | struct amdgpu_device *adev = ring->adev; |
549 | struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub]; | |
2a79d868 | 550 | uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0); |
9096d6e5 CK |
551 | unsigned eng = ring->vm_inv_eng; |
552 | ||
9096d6e5 CK |
553 | amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid), |
554 | lower_32_bits(pd_addr)); | |
555 | ||
556 | amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid), | |
557 | upper_32_bits(pd_addr)); | |
558 | ||
f8bc9037 AD |
559 | amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + eng, |
560 | hub->vm_inv_eng0_ack + eng, | |
561 | req, 1 << vmid); | |
f732b6b3 | 562 | |
9096d6e5 CK |
563 | return pd_addr; |
564 | } | |
565 | ||
c633c00b CK |
566 | static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, |
567 | unsigned pasid) | |
568 | { | |
569 | struct amdgpu_device *adev = ring->adev; | |
570 | uint32_t reg; | |
571 | ||
f2d66571 LM |
572 | /* Do nothing because there's no lut register for mmhub1. */ |
573 | if (ring->funcs->vmhub == AMDGPU_MMHUB_1) | |
574 | return; | |
575 | ||
a2d15ed7 | 576 | if (ring->funcs->vmhub == AMDGPU_GFXHUB_0) |
c633c00b CK |
577 | reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; |
578 | else | |
579 | reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; | |
580 | ||
581 | amdgpu_ring_emit_wreg(ring, reg, pasid); | |
582 | } | |
583 | ||
6490bd76 YZ |
584 | /* |
585 | * PTE format on VEGA 10: | |
586 | * 63:59 reserved | |
587 | * 58:57 mtype | |
588 | * 56 F | |
589 | * 55 L | |
590 | * 54 P | |
591 | * 53 SW | |
592 | * 52 T | |
593 | * 50:48 reserved | |
594 | * 47:12 4k physical page base address | |
595 | * 11:7 fragment | |
596 | * 6 write | |
597 | * 5 read | |
598 | * 4 exe | |
599 | * 3 Z | |
600 | * 2 snooped | |
601 | * 1 system | |
602 | * 0 valid | |
e60f8db5 | 603 | * |
6490bd76 YZ |
604 | * PDE format on VEGA 10: |
605 | * 63:59 block fragment size | |
606 | * 58:55 reserved | |
607 | * 54 P | |
608 | * 53:48 reserved | |
609 | * 47:6 physical base address of PD or PTE | |
610 | * 5:3 reserved | |
611 | * 2 C | |
612 | * 1 system | |
613 | * 0 valid | |
e60f8db5 | 614 | */ |
e60f8db5 | 615 | |
71776b6d | 616 | static uint64_t gmc_v9_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) |
e60f8db5 AX |
617 | |
618 | { | |
71776b6d | 619 | switch (flags) { |
e60f8db5 | 620 | case AMDGPU_VM_MTYPE_DEFAULT: |
71776b6d | 621 | return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); |
e60f8db5 | 622 | case AMDGPU_VM_MTYPE_NC: |
71776b6d | 623 | return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); |
e60f8db5 | 624 | case AMDGPU_VM_MTYPE_WC: |
71776b6d | 625 | return AMDGPU_PTE_MTYPE_VG10(MTYPE_WC); |
093e48c0 | 626 | case AMDGPU_VM_MTYPE_RW: |
71776b6d | 627 | return AMDGPU_PTE_MTYPE_VG10(MTYPE_RW); |
e60f8db5 | 628 | case AMDGPU_VM_MTYPE_CC: |
71776b6d | 629 | return AMDGPU_PTE_MTYPE_VG10(MTYPE_CC); |
e60f8db5 | 630 | case AMDGPU_VM_MTYPE_UC: |
71776b6d | 631 | return AMDGPU_PTE_MTYPE_VG10(MTYPE_UC); |
e60f8db5 | 632 | default: |
71776b6d | 633 | return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); |
e60f8db5 | 634 | } |
e60f8db5 AX |
635 | } |
636 | ||
3de676d8 CK |
637 | static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level, |
638 | uint64_t *addr, uint64_t *flags) | |
e60f8db5 | 639 | { |
bbc9fb10 | 640 | if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) |
3de676d8 | 641 | *addr = adev->vm_manager.vram_base_offset + *addr - |
770d13b1 | 642 | adev->gmc.vram_start; |
3de676d8 | 643 | BUG_ON(*addr & 0xFFFF00000000003FULL); |
6a42fd6f | 644 | |
770d13b1 | 645 | if (!adev->gmc.translate_further) |
6a42fd6f CK |
646 | return; |
647 | ||
648 | if (level == AMDGPU_VM_PDB1) { | |
649 | /* Set the block fragment size */ | |
650 | if (!(*flags & AMDGPU_PDE_PTE)) | |
651 | *flags |= AMDGPU_PDE_BFS(0x9); | |
652 | ||
653 | } else if (level == AMDGPU_VM_PDB0) { | |
654 | if (*flags & AMDGPU_PDE_PTE) | |
655 | *flags &= ~AMDGPU_PDE_PTE; | |
656 | else | |
657 | *flags |= AMDGPU_PTE_TF; | |
658 | } | |
e60f8db5 AX |
659 | } |
660 | ||
cbfae36c CK |
661 | static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev, |
662 | struct amdgpu_bo_va_mapping *mapping, | |
663 | uint64_t *flags) | |
664 | { | |
665 | *flags &= ~AMDGPU_PTE_EXECUTABLE; | |
666 | *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; | |
667 | ||
668 | *flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK; | |
669 | *flags |= mapping->flags & AMDGPU_PTE_MTYPE_VG10_MASK; | |
670 | ||
671 | if (mapping->flags & AMDGPU_PTE_PRT) { | |
672 | *flags |= AMDGPU_PTE_PRT; | |
673 | *flags &= ~AMDGPU_PTE_VALID; | |
674 | } | |
675 | ||
676 | if (adev->asic_type == CHIP_ARCTURUS && | |
677 | !(*flags & AMDGPU_PTE_SYSTEM) && | |
678 | mapping->bo_va->is_xgmi) | |
679 | *flags |= AMDGPU_PTE_SNOOPED; | |
680 | } | |
681 | ||
132f34e4 CK |
682 | static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = { |
683 | .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb, | |
9096d6e5 | 684 | .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb, |
c633c00b | 685 | .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping, |
71776b6d | 686 | .map_mtype = gmc_v9_0_map_mtype, |
cbfae36c CK |
687 | .get_vm_pde = gmc_v9_0_get_vm_pde, |
688 | .get_vm_pte = gmc_v9_0_get_vm_pte | |
e60f8db5 AX |
689 | }; |
690 | ||
132f34e4 | 691 | static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev) |
e60f8db5 | 692 | { |
f54b30d7 | 693 | adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs; |
e60f8db5 AX |
694 | } |
695 | ||
5b6b35aa HZ |
696 | static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev) |
697 | { | |
698 | switch (adev->asic_type) { | |
699 | case CHIP_VEGA20: | |
3aacf4ea TZ |
700 | adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; |
701 | adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; | |
702 | adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; | |
703 | adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET; | |
704 | adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; | |
045c0216 | 705 | adev->umc.funcs = &umc_v6_1_funcs; |
5b6b35aa HZ |
706 | break; |
707 | default: | |
708 | break; | |
709 | } | |
710 | } | |
711 | ||
3d093da0 TZ |
712 | static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev) |
713 | { | |
714 | switch (adev->asic_type) { | |
715 | case CHIP_VEGA20: | |
716 | adev->mmhub_funcs = &mmhub_v1_0_funcs; | |
717 | break; | |
718 | default: | |
719 | break; | |
720 | } | |
721 | } | |
722 | ||
e60f8db5 AX |
723 | static int gmc_v9_0_early_init(void *handle) |
724 | { | |
725 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
726 | ||
132f34e4 | 727 | gmc_v9_0_set_gmc_funcs(adev); |
e60f8db5 | 728 | gmc_v9_0_set_irq_funcs(adev); |
5b6b35aa | 729 | gmc_v9_0_set_umc_funcs(adev); |
3d093da0 | 730 | gmc_v9_0_set_mmhub_funcs(adev); |
e60f8db5 | 731 | |
770d13b1 CK |
732 | adev->gmc.shared_aperture_start = 0x2000000000000000ULL; |
733 | adev->gmc.shared_aperture_end = | |
734 | adev->gmc.shared_aperture_start + (4ULL << 30) - 1; | |
bfa8eea2 | 735 | adev->gmc.private_aperture_start = 0x1000000000000000ULL; |
770d13b1 CK |
736 | adev->gmc.private_aperture_end = |
737 | adev->gmc.private_aperture_start + (4ULL << 30) - 1; | |
a7ea6548 | 738 | |
e60f8db5 AX |
739 | return 0; |
740 | } | |
741 | ||
cd2b5623 AD |
742 | static bool gmc_v9_0_keep_stolen_memory(struct amdgpu_device *adev) |
743 | { | |
744 | ||
745 | /* | |
746 | * TODO: | |
747 | * Currently there is a bug where some memory client outside | |
748 | * of the driver writes to first 8M of VRAM on S3 resume, | |
749 | * this overrides GART which by default gets placed in first 8M and | |
750 | * causes VM_FAULTS once GTT is accessed. | |
751 | * Keep the stolen memory reservation until the while this is not solved. | |
752 | * Also check code in gmc_v9_0_get_vbios_fb_size and gmc_v9_0_late_init | |
753 | */ | |
754 | switch (adev->asic_type) { | |
6abc0c8f | 755 | case CHIP_VEGA10: |
cd2b5623 | 756 | case CHIP_RAVEN: |
bfa3a9bb | 757 | case CHIP_ARCTURUS: |
8787ee01 | 758 | case CHIP_RENOIR: |
02122753 | 759 | return true; |
cd2b5623 AD |
760 | case CHIP_VEGA12: |
761 | case CHIP_VEGA20: | |
762 | default: | |
6abc0c8f | 763 | return false; |
cd2b5623 AD |
764 | } |
765 | } | |
766 | ||
c713a461 | 767 | static int gmc_v9_0_allocate_vm_inv_eng(struct amdgpu_device *adev) |
e60f8db5 | 768 | { |
c713a461 EQ |
769 | struct amdgpu_ring *ring; |
770 | unsigned vm_inv_engs[AMDGPU_MAX_VMHUBS] = | |
c8a6e2a3 LM |
771 | {GFXHUB_FREE_VM_INV_ENGS_BITMAP, MMHUB_FREE_VM_INV_ENGS_BITMAP, |
772 | GFXHUB_FREE_VM_INV_ENGS_BITMAP}; | |
4789c463 | 773 | unsigned i; |
c713a461 | 774 | unsigned vmhub, inv_eng; |
4789c463 | 775 | |
c713a461 EQ |
776 | for (i = 0; i < adev->num_rings; ++i) { |
777 | ring = adev->rings[i]; | |
778 | vmhub = ring->funcs->vmhub; | |
6f752ec2 | 779 | |
c713a461 EQ |
780 | inv_eng = ffs(vm_inv_engs[vmhub]); |
781 | if (!inv_eng) { | |
782 | dev_err(adev->dev, "no VM inv eng for ring %s\n", | |
783 | ring->name); | |
784 | return -EINVAL; | |
785 | } | |
786 | ||
787 | ring->vm_inv_eng = inv_eng - 1; | |
72464382 | 788 | vm_inv_engs[vmhub] &= ~(1 << ring->vm_inv_eng); |
4789c463 | 789 | |
6e82c6e0 CK |
790 | dev_info(adev->dev, "ring %s uses VM inv eng %u on hub %u\n", |
791 | ring->name, ring->vm_inv_eng, ring->funcs->vmhub); | |
4789c463 CK |
792 | } |
793 | ||
c713a461 EQ |
794 | return 0; |
795 | } | |
796 | ||
145b03eb TZ |
797 | static int gmc_v9_0_ecc_late_init(void *handle) |
798 | { | |
799 | int r; | |
2452e778 | 800 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
2452e778 HZ |
801 | struct ras_ih_if umc_ih_info = { |
802 | .cb = gmc_v9_0_process_ras_data_cb, | |
145b03eb | 803 | }; |
145b03eb | 804 | |
86edcc7d TZ |
805 | if (adev->umc.funcs && adev->umc.funcs->ras_late_init) { |
806 | r = adev->umc.funcs->ras_late_init(adev, &umc_ih_info); | |
807 | if (r) | |
808 | return r; | |
809 | } | |
2452e778 | 810 | |
4ce71be6 | 811 | if (adev->mmhub_funcs && adev->mmhub_funcs->ras_late_init) { |
dda79907 HZ |
812 | r = adev->mmhub_funcs->ras_late_init(adev); |
813 | if (r) | |
814 | return r; | |
2452e778 | 815 | } |
029fbd43 HZ |
816 | |
817 | return amdgpu_xgmi_ras_late_init(adev); | |
145b03eb | 818 | } |
791c4769 | 819 | |
c713a461 EQ |
820 | static int gmc_v9_0_late_init(void *handle) |
821 | { | |
822 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
c5b6e585 | 823 | int r; |
c713a461 EQ |
824 | |
825 | if (!gmc_v9_0_keep_stolen_memory(adev)) | |
826 | amdgpu_bo_late_init(adev); | |
827 | ||
828 | r = gmc_v9_0_allocate_vm_inv_eng(adev); | |
829 | if (r) | |
830 | return r; | |
f49ea9f8 HZ |
831 | /* Check if ecc is available */ |
832 | if (!amdgpu_sriov_vf(adev)) { | |
833 | switch (adev->asic_type) { | |
834 | case CHIP_VEGA10: | |
835 | case CHIP_VEGA20: | |
836 | r = amdgpu_atomfirmware_mem_ecc_supported(adev); | |
837 | if (!r) { | |
838 | DRM_INFO("ECC is not present.\n"); | |
839 | if (adev->df_funcs->enable_ecc_force_par_wr_rmw) | |
840 | adev->df_funcs->enable_ecc_force_par_wr_rmw(adev, false); | |
841 | } else { | |
842 | DRM_INFO("ECC is active.\n"); | |
843 | } | |
4789c463 | 844 | |
f49ea9f8 HZ |
845 | r = amdgpu_atomfirmware_sram_ecc_supported(adev); |
846 | if (!r) { | |
847 | DRM_INFO("SRAM ECC is not present.\n"); | |
848 | } else { | |
849 | DRM_INFO("SRAM ECC is active.\n"); | |
850 | } | |
851 | break; | |
852 | default: | |
853 | break; | |
5ba4fa35 | 854 | } |
02bab923 DP |
855 | } |
856 | ||
791c4769 | 857 | r = gmc_v9_0_ecc_late_init(handle); |
858 | if (r) | |
859 | return r; | |
860 | ||
770d13b1 | 861 | return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); |
e60f8db5 AX |
862 | } |
863 | ||
864 | static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, | |
770d13b1 | 865 | struct amdgpu_gmc *mc) |
e60f8db5 | 866 | { |
eeb2487d | 867 | u64 base = 0; |
9d4f837a FM |
868 | |
869 | if (adev->asic_type == CHIP_ARCTURUS) | |
870 | base = mmhub_v9_4_get_fb_location(adev); | |
871 | else if (!amdgpu_sriov_vf(adev)) | |
872 | base = mmhub_v1_0_get_fb_location(adev); | |
873 | ||
6fdd68b1 AD |
874 | /* add the xgmi offset of the physical node */ |
875 | base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; | |
83afe835 | 876 | amdgpu_gmc_vram_location(adev, mc, base); |
961c75cf | 877 | amdgpu_gmc_gart_location(adev, mc); |
81c274c4 | 878 | amdgpu_gmc_agp_location(adev, mc); |
bc099ee9 | 879 | /* base offset of vram pages */ |
b6110c00 | 880 | adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev); |
6fdd68b1 AD |
881 | |
882 | /* XXX: add the xgmi offset of the physical node? */ | |
883 | adev->vm_manager.vram_base_offset += | |
884 | adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; | |
e60f8db5 AX |
885 | } |
886 | ||
887 | /** | |
888 | * gmc_v9_0_mc_init - initialize the memory controller driver params | |
889 | * | |
890 | * @adev: amdgpu_device pointer | |
891 | * | |
892 | * Look up the amount of vram, vram width, and decide how to place | |
893 | * vram and gart within the GPU's physical address space. | |
894 | * Returns 0 for success. | |
895 | */ | |
896 | static int gmc_v9_0_mc_init(struct amdgpu_device *adev) | |
897 | { | |
e60f8db5 | 898 | int chansize, numchan; |
d6895ad3 | 899 | int r; |
e60f8db5 | 900 | |
067e75b3 AD |
901 | if (amdgpu_sriov_vf(adev)) { |
902 | /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN, | |
903 | * and DF related registers is not readable, seems hardcord is the | |
904 | * only way to set the correct vram_width | |
905 | */ | |
906 | adev->gmc.vram_width = 2048; | |
907 | } else if (amdgpu_emu_mode != 1) { | |
3d918c0e | 908 | adev->gmc.vram_width = amdgpu_atomfirmware_get_vram_width(adev); |
067e75b3 AD |
909 | } |
910 | ||
770d13b1 | 911 | if (!adev->gmc.vram_width) { |
8d6a5230 | 912 | /* hbm memory channel size */ |
585b7f16 TSD |
913 | if (adev->flags & AMD_IS_APU) |
914 | chansize = 64; | |
915 | else | |
916 | chansize = 128; | |
8d6a5230 | 917 | |
070706c0 | 918 | numchan = adev->df_funcs->get_hbm_channel_number(adev); |
770d13b1 | 919 | adev->gmc.vram_width = numchan * chansize; |
e60f8db5 | 920 | } |
e60f8db5 | 921 | |
e60f8db5 | 922 | /* size in MB on si */ |
770d13b1 | 923 | adev->gmc.mc_vram_size = |
bebc0762 | 924 | adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; |
770d13b1 | 925 | adev->gmc.real_vram_size = adev->gmc.mc_vram_size; |
d6895ad3 CK |
926 | |
927 | if (!(adev->flags & AMD_IS_APU)) { | |
928 | r = amdgpu_device_resize_fb_bar(adev); | |
929 | if (r) | |
930 | return r; | |
931 | } | |
770d13b1 CK |
932 | adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); |
933 | adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); | |
e60f8db5 | 934 | |
156a81be CZ |
935 | #ifdef CONFIG_X86_64 |
936 | if (adev->flags & AMD_IS_APU) { | |
937 | adev->gmc.aper_base = gfxhub_v1_0_get_mc_fb_offset(adev); | |
938 | adev->gmc.aper_size = adev->gmc.real_vram_size; | |
939 | } | |
940 | #endif | |
e60f8db5 | 941 | /* In case the PCI BAR is larger than the actual amount of vram */ |
770d13b1 CK |
942 | adev->gmc.visible_vram_size = adev->gmc.aper_size; |
943 | if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) | |
944 | adev->gmc.visible_vram_size = adev->gmc.real_vram_size; | |
e60f8db5 | 945 | |
c3db7b5a AD |
946 | /* set the gart size */ |
947 | if (amdgpu_gart_size == -1) { | |
948 | switch (adev->asic_type) { | |
949 | case CHIP_VEGA10: /* all engines support GPUVM */ | |
273a14cd | 950 | case CHIP_VEGA12: /* all engines support GPUVM */ |
d96b428c | 951 | case CHIP_VEGA20: |
3de2ff5d | 952 | case CHIP_ARCTURUS: |
c3db7b5a | 953 | default: |
fe19b862 | 954 | adev->gmc.gart_size = 512ULL << 20; |
c3db7b5a AD |
955 | break; |
956 | case CHIP_RAVEN: /* DCE SG support */ | |
8787ee01 | 957 | case CHIP_RENOIR: |
770d13b1 | 958 | adev->gmc.gart_size = 1024ULL << 20; |
c3db7b5a AD |
959 | break; |
960 | } | |
961 | } else { | |
770d13b1 | 962 | adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; |
c3db7b5a AD |
963 | } |
964 | ||
770d13b1 | 965 | gmc_v9_0_vram_gtt_location(adev, &adev->gmc); |
e60f8db5 AX |
966 | |
967 | return 0; | |
968 | } | |
969 | ||
970 | static int gmc_v9_0_gart_init(struct amdgpu_device *adev) | |
971 | { | |
972 | int r; | |
973 | ||
1123b989 | 974 | if (adev->gart.bo) { |
e60f8db5 AX |
975 | WARN(1, "VEGA10 PCIE GART already initialized\n"); |
976 | return 0; | |
977 | } | |
978 | /* Initialize common gart structure */ | |
979 | r = amdgpu_gart_init(adev); | |
980 | if (r) | |
981 | return r; | |
982 | adev->gart.table_size = adev->gart.num_gpu_pages * 8; | |
7596ab68 | 983 | adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(MTYPE_UC) | |
e60f8db5 AX |
984 | AMDGPU_PTE_EXECUTABLE; |
985 | return amdgpu_gart_table_vram_alloc(adev); | |
986 | } | |
987 | ||
ebdef28e AD |
988 | static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev) |
989 | { | |
bfa3a9bb | 990 | u32 d1vga_control; |
ebdef28e AD |
991 | unsigned size; |
992 | ||
6f752ec2 AG |
993 | /* |
994 | * TODO Remove once GART corruption is resolved | |
995 | * Check related code in gmc_v9_0_sw_fini | |
996 | * */ | |
cd2b5623 AD |
997 | if (gmc_v9_0_keep_stolen_memory(adev)) |
998 | return 9 * 1024 * 1024; | |
6f752ec2 | 999 | |
bfa3a9bb | 1000 | d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); |
ebdef28e AD |
1001 | if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { |
1002 | size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */ | |
1003 | } else { | |
1004 | u32 viewport; | |
1005 | ||
1006 | switch (adev->asic_type) { | |
1007 | case CHIP_RAVEN: | |
8787ee01 | 1008 | case CHIP_RENOIR: |
ebdef28e AD |
1009 | viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); |
1010 | size = (REG_GET_FIELD(viewport, | |
1011 | HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * | |
1012 | REG_GET_FIELD(viewport, | |
1013 | HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * | |
1014 | 4); | |
1015 | break; | |
1016 | case CHIP_VEGA10: | |
1017 | case CHIP_VEGA12: | |
cd2b5623 | 1018 | case CHIP_VEGA20: |
ebdef28e AD |
1019 | default: |
1020 | viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE); | |
1021 | size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) * | |
1022 | REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) * | |
1023 | 4); | |
1024 | break; | |
1025 | } | |
1026 | } | |
1027 | /* return 0 if the pre-OS buffer uses up most of vram */ | |
1028 | if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) | |
1029 | return 0; | |
6f752ec2 | 1030 | |
ebdef28e AD |
1031 | return size; |
1032 | } | |
1033 | ||
e60f8db5 AX |
1034 | static int gmc_v9_0_sw_init(void *handle) |
1035 | { | |
1036 | int r; | |
e60f8db5 AX |
1037 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1038 | ||
0c8c0847 | 1039 | gfxhub_v1_0_init(adev); |
51cce480 LM |
1040 | if (adev->asic_type == CHIP_ARCTURUS) |
1041 | mmhub_v9_4_init(adev); | |
1042 | else | |
1043 | mmhub_v1_0_init(adev); | |
0c8c0847 | 1044 | |
770d13b1 | 1045 | spin_lock_init(&adev->gmc.invalidate_lock); |
e60f8db5 | 1046 | |
1e09b053 | 1047 | adev->gmc.vram_type = amdgpu_atomfirmware_get_vram_type(adev); |
fd66560b HZ |
1048 | switch (adev->asic_type) { |
1049 | case CHIP_RAVEN: | |
1daa2bfa LM |
1050 | adev->num_vmhubs = 2; |
1051 | ||
6a42fd6f | 1052 | if (adev->rev_id == 0x0 || adev->rev_id == 0x1) { |
f3368128 | 1053 | amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); |
6a42fd6f CK |
1054 | } else { |
1055 | /* vm_size is 128TB + 512GB for legacy 3-level page support */ | |
1056 | amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48); | |
770d13b1 | 1057 | adev->gmc.translate_further = |
6a42fd6f CK |
1058 | adev->vm_manager.num_level > 1; |
1059 | } | |
fd66560b HZ |
1060 | break; |
1061 | case CHIP_VEGA10: | |
273a14cd | 1062 | case CHIP_VEGA12: |
d96b428c | 1063 | case CHIP_VEGA20: |
8787ee01 | 1064 | case CHIP_RENOIR: |
1daa2bfa LM |
1065 | adev->num_vmhubs = 2; |
1066 | ||
8787ee01 | 1067 | |
36b32a68 ZJ |
1068 | /* |
1069 | * To fulfill 4-level page support, | |
1070 | * vm size is 256TB (48bit), maximum size of Vega10, | |
1071 | * block size 512 (9bit) | |
1072 | */ | |
cdba61da | 1073 | /* sriov restrict max_pfn below AMDGPU_GMC_HOLE */ |
1074 | if (amdgpu_sriov_vf(adev)) | |
1075 | amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 47); | |
1076 | else | |
1077 | amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); | |
fd66560b | 1078 | break; |
3de2ff5d | 1079 | case CHIP_ARCTURUS: |
c8a6e2a3 LM |
1080 | adev->num_vmhubs = 3; |
1081 | ||
3de2ff5d LM |
1082 | /* Keep the vm size same with Vega20 */ |
1083 | amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); | |
1084 | break; | |
fd66560b HZ |
1085 | default: |
1086 | break; | |
e60f8db5 AX |
1087 | } |
1088 | ||
1089 | /* This interrupt is VMC page fault.*/ | |
44a99b65 | 1090 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT, |
770d13b1 | 1091 | &adev->gmc.vm_fault); |
30da7bb1 CK |
1092 | if (r) |
1093 | return r; | |
1094 | ||
7d19b15f LM |
1095 | if (adev->asic_type == CHIP_ARCTURUS) { |
1096 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT, | |
1097 | &adev->gmc.vm_fault); | |
1098 | if (r) | |
1099 | return r; | |
1100 | } | |
1101 | ||
44a99b65 | 1102 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT, |
770d13b1 | 1103 | &adev->gmc.vm_fault); |
e60f8db5 AX |
1104 | |
1105 | if (r) | |
1106 | return r; | |
1107 | ||
791c4769 | 1108 | /* interrupt sent to DF. */ |
1109 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0, | |
1110 | &adev->gmc.ecc_irq); | |
1111 | if (r) | |
1112 | return r; | |
1113 | ||
e60f8db5 AX |
1114 | /* Set the internal MC address mask |
1115 | * This is the max address of the GPU's | |
1116 | * internal address space. | |
1117 | */ | |
770d13b1 | 1118 | adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ |
e60f8db5 | 1119 | |
244511f3 | 1120 | r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); |
e60f8db5 | 1121 | if (r) { |
e60f8db5 | 1122 | printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); |
244511f3 | 1123 | return r; |
e60f8db5 | 1124 | } |
244511f3 | 1125 | adev->need_swiotlb = drm_need_swiotlb(44); |
e60f8db5 | 1126 | |
47622ba0 | 1127 | if (adev->gmc.xgmi.supported) { |
bf0a60b7 AD |
1128 | r = gfxhub_v1_1_get_xgmi_info(adev); |
1129 | if (r) | |
1130 | return r; | |
1131 | } | |
1132 | ||
e60f8db5 AX |
1133 | r = gmc_v9_0_mc_init(adev); |
1134 | if (r) | |
1135 | return r; | |
1136 | ||
ebdef28e AD |
1137 | adev->gmc.stolen_size = gmc_v9_0_get_vbios_fb_size(adev); |
1138 | ||
e60f8db5 AX |
1139 | /* Memory manager */ |
1140 | r = amdgpu_bo_init(adev); | |
1141 | if (r) | |
1142 | return r; | |
1143 | ||
1144 | r = gmc_v9_0_gart_init(adev); | |
1145 | if (r) | |
1146 | return r; | |
1147 | ||
05ec3eda CK |
1148 | /* |
1149 | * number of VMs | |
1150 | * VMID 0 is reserved for System | |
1151 | * amdgpu graphics/compute will use VMIDs 1-7 | |
1152 | * amdkfd will use VMIDs 8-15 | |
1153 | */ | |
a2d15ed7 LM |
1154 | adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS; |
1155 | adev->vm_manager.id_mgr[AMDGPU_MMHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS; | |
c8a6e2a3 | 1156 | adev->vm_manager.id_mgr[AMDGPU_MMHUB_1].num_ids = AMDGPU_NUM_OF_VMIDS; |
05ec3eda | 1157 | |
05ec3eda CK |
1158 | amdgpu_vm_manager_init(adev); |
1159 | ||
1160 | return 0; | |
e60f8db5 AX |
1161 | } |
1162 | ||
e60f8db5 AX |
1163 | static int gmc_v9_0_sw_fini(void *handle) |
1164 | { | |
1165 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
994dcfaa | 1166 | void *stolen_vga_buf; |
e60f8db5 | 1167 | |
791c4769 | 1168 | if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC) && |
145b03eb TZ |
1169 | adev->gmc.umc_ras_if) { |
1170 | struct ras_common_if *ras_if = adev->gmc.umc_ras_if; | |
791c4769 | 1171 | struct ras_ih_if ih_info = { |
1172 | .head = *ras_if, | |
1173 | }; | |
1174 | ||
145b03eb | 1175 | /* remove fs first */ |
791c4769 | 1176 | amdgpu_ras_debugfs_remove(adev, ras_if); |
1177 | amdgpu_ras_sysfs_remove(adev, ras_if); | |
145b03eb | 1178 | /* remove the IH */ |
791c4769 | 1179 | amdgpu_ras_interrupt_remove_handler(adev, &ih_info); |
1180 | amdgpu_ras_feature_enable(adev, ras_if, 0); | |
1181 | kfree(ras_if); | |
1182 | } | |
1183 | ||
145b03eb TZ |
1184 | if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB) && |
1185 | adev->gmc.mmhub_ras_if) { | |
1186 | struct ras_common_if *ras_if = adev->gmc.mmhub_ras_if; | |
1187 | ||
1188 | /* remove fs and disable ras feature */ | |
1189 | amdgpu_ras_debugfs_remove(adev, ras_if); | |
1190 | amdgpu_ras_sysfs_remove(adev, ras_if); | |
1191 | amdgpu_ras_feature_enable(adev, ras_if, 0); | |
1192 | kfree(ras_if); | |
1193 | } | |
1194 | ||
f59548c8 | 1195 | amdgpu_gem_force_release(adev); |
05ec3eda | 1196 | amdgpu_vm_manager_fini(adev); |
6f752ec2 | 1197 | |
cd2b5623 | 1198 | if (gmc_v9_0_keep_stolen_memory(adev)) |
994dcfaa | 1199 | amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, &stolen_vga_buf); |
6f752ec2 | 1200 | |
a3d9103e | 1201 | amdgpu_gart_table_vram_free(adev); |
e60f8db5 | 1202 | amdgpu_bo_fini(adev); |
a3d9103e | 1203 | amdgpu_gart_fini(adev); |
e60f8db5 AX |
1204 | |
1205 | return 0; | |
1206 | } | |
1207 | ||
1208 | static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) | |
1209 | { | |
946a4d5b | 1210 | |
e60f8db5 AX |
1211 | switch (adev->asic_type) { |
1212 | case CHIP_VEGA10: | |
4cd4c5c0 | 1213 | if (amdgpu_sriov_vf(adev)) |
98cad2de TH |
1214 | break; |
1215 | /* fall through */ | |
d96b428c | 1216 | case CHIP_VEGA20: |
946a4d5b | 1217 | soc15_program_register_sequence(adev, |
5c583018 | 1218 | golden_settings_mmhub_1_0_0, |
c47b41a7 | 1219 | ARRAY_SIZE(golden_settings_mmhub_1_0_0)); |
946a4d5b | 1220 | soc15_program_register_sequence(adev, |
5c583018 | 1221 | golden_settings_athub_1_0_0, |
c47b41a7 | 1222 | ARRAY_SIZE(golden_settings_athub_1_0_0)); |
e60f8db5 | 1223 | break; |
273a14cd AD |
1224 | case CHIP_VEGA12: |
1225 | break; | |
e4f3abaa | 1226 | case CHIP_RAVEN: |
8787ee01 | 1227 | /* TODO for renoir */ |
946a4d5b | 1228 | soc15_program_register_sequence(adev, |
5c583018 | 1229 | golden_settings_athub_1_0_0, |
c47b41a7 | 1230 | ARRAY_SIZE(golden_settings_athub_1_0_0)); |
e4f3abaa | 1231 | break; |
e60f8db5 AX |
1232 | default: |
1233 | break; | |
1234 | } | |
1235 | } | |
1236 | ||
1237 | /** | |
1238 | * gmc_v9_0_gart_enable - gart enable | |
1239 | * | |
1240 | * @adev: amdgpu_device pointer | |
1241 | */ | |
1242 | static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) | |
1243 | { | |
3ff98548 | 1244 | int r, i; |
e60f8db5 AX |
1245 | bool value; |
1246 | u32 tmp; | |
1247 | ||
9c3f2b54 AD |
1248 | amdgpu_device_program_register_sequence(adev, |
1249 | golden_settings_vega10_hdp, | |
1250 | ARRAY_SIZE(golden_settings_vega10_hdp)); | |
e60f8db5 | 1251 | |
1123b989 | 1252 | if (adev->gart.bo == NULL) { |
e60f8db5 AX |
1253 | dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); |
1254 | return -EINVAL; | |
1255 | } | |
ce1b1b66 ML |
1256 | r = amdgpu_gart_table_vram_pin(adev); |
1257 | if (r) | |
1258 | return r; | |
e60f8db5 | 1259 | |
2fcd43ce HZ |
1260 | switch (adev->asic_type) { |
1261 | case CHIP_RAVEN: | |
8787ee01 | 1262 | /* TODO for renoir */ |
f8386b35 | 1263 | mmhub_v1_0_update_power_gating(adev, true); |
2fcd43ce HZ |
1264 | break; |
1265 | default: | |
1266 | break; | |
1267 | } | |
1268 | ||
e60f8db5 AX |
1269 | r = gfxhub_v1_0_gart_enable(adev); |
1270 | if (r) | |
1271 | return r; | |
1272 | ||
51cce480 LM |
1273 | if (adev->asic_type == CHIP_ARCTURUS) |
1274 | r = mmhub_v9_4_gart_enable(adev); | |
1275 | else | |
1276 | r = mmhub_v1_0_gart_enable(adev); | |
e60f8db5 AX |
1277 | if (r) |
1278 | return r; | |
1279 | ||
846347c9 | 1280 | WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1); |
e60f8db5 | 1281 | |
b9509c80 HR |
1282 | tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL); |
1283 | WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp); | |
e60f8db5 | 1284 | |
fe2b5323 TZ |
1285 | WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8)); |
1286 | WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40)); | |
1287 | ||
1d4e0a8c | 1288 | /* After HDP is initialized, flush HDP.*/ |
bebc0762 | 1289 | adev->nbio.funcs->hdp_flush(adev, NULL); |
1d4e0a8c | 1290 | |
e60f8db5 AX |
1291 | if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) |
1292 | value = false; | |
1293 | else | |
1294 | value = true; | |
1295 | ||
1296 | gfxhub_v1_0_set_fault_enable_default(adev, value); | |
51cce480 LM |
1297 | if (adev->asic_type == CHIP_ARCTURUS) |
1298 | mmhub_v9_4_set_fault_enable_default(adev, value); | |
1299 | else | |
1300 | mmhub_v1_0_set_fault_enable_default(adev, value); | |
3ff98548 OZ |
1301 | |
1302 | for (i = 0; i < adev->num_vmhubs; ++i) | |
1303 | gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0); | |
e60f8db5 AX |
1304 | |
1305 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", | |
770d13b1 | 1306 | (unsigned)(adev->gmc.gart_size >> 20), |
4e830fb1 | 1307 | (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); |
e60f8db5 AX |
1308 | adev->gart.ready = true; |
1309 | return 0; | |
1310 | } | |
1311 | ||
1312 | static int gmc_v9_0_hw_init(void *handle) | |
1313 | { | |
1314 | int r; | |
1315 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1316 | ||
1317 | /* The sequence of these two function calls matters.*/ | |
1318 | gmc_v9_0_init_golden_registers(adev); | |
1319 | ||
edca2d05 | 1320 | if (adev->mode_info.num_crtc) { |
edca2d05 | 1321 | /* Lockout access through VGA aperture*/ |
4d9c333a | 1322 | WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); |
edca2d05 AD |
1323 | |
1324 | /* disable VGA render */ | |
4d9c333a | 1325 | WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); |
edca2d05 AD |
1326 | } |
1327 | ||
e60f8db5 AX |
1328 | r = gmc_v9_0_gart_enable(adev); |
1329 | ||
1330 | return r; | |
1331 | } | |
1332 | ||
1333 | /** | |
1334 | * gmc_v9_0_gart_disable - gart disable | |
1335 | * | |
1336 | * @adev: amdgpu_device pointer | |
1337 | * | |
1338 | * This disables all VM page table. | |
1339 | */ | |
1340 | static void gmc_v9_0_gart_disable(struct amdgpu_device *adev) | |
1341 | { | |
1342 | gfxhub_v1_0_gart_disable(adev); | |
51cce480 LM |
1343 | if (adev->asic_type == CHIP_ARCTURUS) |
1344 | mmhub_v9_4_gart_disable(adev); | |
1345 | else | |
1346 | mmhub_v1_0_gart_disable(adev); | |
ce1b1b66 | 1347 | amdgpu_gart_table_vram_unpin(adev); |
e60f8db5 AX |
1348 | } |
1349 | ||
1350 | static int gmc_v9_0_hw_fini(void *handle) | |
1351 | { | |
1352 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1353 | ||
5dd696ae TH |
1354 | if (amdgpu_sriov_vf(adev)) { |
1355 | /* full access mode, so don't touch any GMC register */ | |
1356 | DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); | |
1357 | return 0; | |
1358 | } | |
1359 | ||
791c4769 | 1360 | amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); |
770d13b1 | 1361 | amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); |
e60f8db5 AX |
1362 | gmc_v9_0_gart_disable(adev); |
1363 | ||
1364 | return 0; | |
1365 | } | |
1366 | ||
1367 | static int gmc_v9_0_suspend(void *handle) | |
1368 | { | |
1369 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1370 | ||
f053cd47 | 1371 | return gmc_v9_0_hw_fini(adev); |
e60f8db5 AX |
1372 | } |
1373 | ||
1374 | static int gmc_v9_0_resume(void *handle) | |
1375 | { | |
1376 | int r; | |
1377 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1378 | ||
1379 | r = gmc_v9_0_hw_init(adev); | |
1380 | if (r) | |
1381 | return r; | |
1382 | ||
620f774f | 1383 | amdgpu_vmid_reset_all(adev); |
e60f8db5 | 1384 | |
32601d48 | 1385 | return 0; |
e60f8db5 AX |
1386 | } |
1387 | ||
1388 | static bool gmc_v9_0_is_idle(void *handle) | |
1389 | { | |
1390 | /* MC is always ready in GMC v9.*/ | |
1391 | return true; | |
1392 | } | |
1393 | ||
1394 | static int gmc_v9_0_wait_for_idle(void *handle) | |
1395 | { | |
1396 | /* There is no need to wait for MC idle in GMC v9.*/ | |
1397 | return 0; | |
1398 | } | |
1399 | ||
1400 | static int gmc_v9_0_soft_reset(void *handle) | |
1401 | { | |
1402 | /* XXX for emulation.*/ | |
1403 | return 0; | |
1404 | } | |
1405 | ||
1406 | static int gmc_v9_0_set_clockgating_state(void *handle, | |
1407 | enum amd_clockgating_state state) | |
1408 | { | |
d5583d4f HR |
1409 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1410 | ||
51cce480 | 1411 | if (adev->asic_type == CHIP_ARCTURUS) |
cb15e804 LM |
1412 | mmhub_v9_4_set_clockgating(adev, state); |
1413 | else | |
1414 | mmhub_v1_0_set_clockgating(adev, state); | |
bee7b51a LM |
1415 | |
1416 | athub_v1_0_set_clockgating(adev, state); | |
1417 | ||
1418 | return 0; | |
e60f8db5 AX |
1419 | } |
1420 | ||
13052be5 HR |
1421 | static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags) |
1422 | { | |
1423 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1424 | ||
51cce480 | 1425 | if (adev->asic_type == CHIP_ARCTURUS) |
cb15e804 LM |
1426 | mmhub_v9_4_get_clockgating(adev, flags); |
1427 | else | |
1428 | mmhub_v1_0_get_clockgating(adev, flags); | |
bee7b51a LM |
1429 | |
1430 | athub_v1_0_get_clockgating(adev, flags); | |
13052be5 HR |
1431 | } |
1432 | ||
e60f8db5 AX |
1433 | static int gmc_v9_0_set_powergating_state(void *handle, |
1434 | enum amd_powergating_state state) | |
1435 | { | |
1436 | return 0; | |
1437 | } | |
1438 | ||
1439 | const struct amd_ip_funcs gmc_v9_0_ip_funcs = { | |
1440 | .name = "gmc_v9_0", | |
1441 | .early_init = gmc_v9_0_early_init, | |
1442 | .late_init = gmc_v9_0_late_init, | |
1443 | .sw_init = gmc_v9_0_sw_init, | |
1444 | .sw_fini = gmc_v9_0_sw_fini, | |
1445 | .hw_init = gmc_v9_0_hw_init, | |
1446 | .hw_fini = gmc_v9_0_hw_fini, | |
1447 | .suspend = gmc_v9_0_suspend, | |
1448 | .resume = gmc_v9_0_resume, | |
1449 | .is_idle = gmc_v9_0_is_idle, | |
1450 | .wait_for_idle = gmc_v9_0_wait_for_idle, | |
1451 | .soft_reset = gmc_v9_0_soft_reset, | |
1452 | .set_clockgating_state = gmc_v9_0_set_clockgating_state, | |
1453 | .set_powergating_state = gmc_v9_0_set_powergating_state, | |
13052be5 | 1454 | .get_clockgating_state = gmc_v9_0_get_clockgating_state, |
e60f8db5 AX |
1455 | }; |
1456 | ||
1457 | const struct amdgpu_ip_block_version gmc_v9_0_ip_block = | |
1458 | { | |
1459 | .type = AMD_IP_BLOCK_TYPE_GMC, | |
1460 | .major = 9, | |
1461 | .minor = 0, | |
1462 | .rev = 0, | |
1463 | .funcs = &gmc_v9_0_ip_funcs, | |
1464 | }; |