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drm/amdgpu: move setting the GART addr into TTM
[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / amd / amdgpu / gmc_v9_0.c
CommitLineData
e60f8db5
AX		 1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
fd5fd480 24#include <drm/drm_cache.h>
e60f8db5
AX		 25#include "amdgpu.h"
26#include "gmc_v9_0.h"
8d6a5230 27#include "amdgpu_atomfirmware.h"
2cddc50e 28#include "amdgpu_gem.h"
e60f8db5 29
75199b8c
FX		 30#include "hdp/hdp_4_0_offset.h"
31#include "hdp/hdp_4_0_sh_mask.h"
cde5c34f 32#include "gc/gc_9_0_sh_mask.h"
135d4b10
FX		 33#include "dce/dce_12_0_offset.h"
34#include "dce/dce_12_0_sh_mask.h"
fb960bd2 35#include "vega10_enum.h"
65417d9f 36#include "mmhub/mmhub_1_0_offset.h"
6ce68225 37#include "athub/athub_1_0_offset.h"
250b4228 38#include "oss/osssys_4_0_offset.h"
e60f8db5 39
946a4d5b 40#include "soc15.h"
e60f8db5 41#include "soc15_common.h"
90c7a935 42#include "umc/umc_6_0_sh_mask.h"
e60f8db5 43
e60f8db5
AX		 44#include "gfxhub_v1_0.h"
45#include "mmhub_v1_0.h"
46
44a99b65
AG		 47#include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
48
ebdef28e
AD		 49/* add these here since we already include dce12 headers and these are for DCN */
50#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d
51#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
52#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0
53#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10
54#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL
55#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L
56
e60f8db5
AX		 57/* XXX Move this macro to VEGA10 header file, which is like vid.h for VI.*/
58#define AMDGPU_NUM_OF_VMIDS 8
59
60static const u32 golden_settings_vega10_hdp[] =
61{
62 0xf64, 0x0fffffff, 0x00000000,
63 0xf65, 0x0fffffff, 0x00000000,
64 0xf66, 0x0fffffff, 0x00000000,
65 0xf67, 0x0fffffff, 0x00000000,
66 0xf68, 0x0fffffff, 0x00000000,
67 0xf6a, 0x0fffffff, 0x00000000,
68 0xf6b, 0x0fffffff, 0x00000000,
69 0xf6c, 0x0fffffff, 0x00000000,
70 0xf6d, 0x0fffffff, 0x00000000,
71 0xf6e, 0x0fffffff, 0x00000000,
72};
73
946a4d5b 74static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] =
5c583018 75{
946a4d5b
SL		 76 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa),
77 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565)
5c583018
EQ		 78};
79
946a4d5b 80static const struct soc15_reg_golden golden_settings_athub_1_0_0[] =
5c583018 81{
946a4d5b
SL		 82 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800),
83 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008)
5c583018
EQ		 84};
85
02bab923
DP		 86/* Ecc related register addresses, (BASE + reg offset) */
87/* Universal Memory Controller caps (may be fused). */
88/* UMCCH:UmcLocalCap */
89#define UMCLOCALCAPS_ADDR0 (0x00014306 + 0x00000000)
90#define UMCLOCALCAPS_ADDR1 (0x00014306 + 0x00000800)
91#define UMCLOCALCAPS_ADDR2 (0x00014306 + 0x00001000)
92#define UMCLOCALCAPS_ADDR3 (0x00014306 + 0x00001800)
93#define UMCLOCALCAPS_ADDR4 (0x00054306 + 0x00000000)
94#define UMCLOCALCAPS_ADDR5 (0x00054306 + 0x00000800)
95#define UMCLOCALCAPS_ADDR6 (0x00054306 + 0x00001000)
96#define UMCLOCALCAPS_ADDR7 (0x00054306 + 0x00001800)
97#define UMCLOCALCAPS_ADDR8 (0x00094306 + 0x00000000)
98#define UMCLOCALCAPS_ADDR9 (0x00094306 + 0x00000800)
99#define UMCLOCALCAPS_ADDR10 (0x00094306 + 0x00001000)
100#define UMCLOCALCAPS_ADDR11 (0x00094306 + 0x00001800)
101#define UMCLOCALCAPS_ADDR12 (0x000d4306 + 0x00000000)
102#define UMCLOCALCAPS_ADDR13 (0x000d4306 + 0x00000800)
103#define UMCLOCALCAPS_ADDR14 (0x000d4306 + 0x00001000)
104#define UMCLOCALCAPS_ADDR15 (0x000d4306 + 0x00001800)
105
106/* Universal Memory Controller Channel config. */
107/* UMCCH:UMC_CONFIG */
108#define UMCCH_UMC_CONFIG_ADDR0 (0x00014040 + 0x00000000)
109#define UMCCH_UMC_CONFIG_ADDR1 (0x00014040 + 0x00000800)
110#define UMCCH_UMC_CONFIG_ADDR2 (0x00014040 + 0x00001000)
111#define UMCCH_UMC_CONFIG_ADDR3 (0x00014040 + 0x00001800)
112#define UMCCH_UMC_CONFIG_ADDR4 (0x00054040 + 0x00000000)
113#define UMCCH_UMC_CONFIG_ADDR5 (0x00054040 + 0x00000800)
114#define UMCCH_UMC_CONFIG_ADDR6 (0x00054040 + 0x00001000)
115#define UMCCH_UMC_CONFIG_ADDR7 (0x00054040 + 0x00001800)
116#define UMCCH_UMC_CONFIG_ADDR8 (0x00094040 + 0x00000000)
117#define UMCCH_UMC_CONFIG_ADDR9 (0x00094040 + 0x00000800)
118#define UMCCH_UMC_CONFIG_ADDR10 (0x00094040 + 0x00001000)
119#define UMCCH_UMC_CONFIG_ADDR11 (0x00094040 + 0x00001800)
120#define UMCCH_UMC_CONFIG_ADDR12 (0x000d4040 + 0x00000000)
121#define UMCCH_UMC_CONFIG_ADDR13 (0x000d4040 + 0x00000800)
122#define UMCCH_UMC_CONFIG_ADDR14 (0x000d4040 + 0x00001000)
123#define UMCCH_UMC_CONFIG_ADDR15 (0x000d4040 + 0x00001800)
124
125/* Universal Memory Controller Channel Ecc config. */
126/* UMCCH:EccCtrl */
127#define UMCCH_ECCCTRL_ADDR0 (0x00014053 + 0x00000000)
128#define UMCCH_ECCCTRL_ADDR1 (0x00014053 + 0x00000800)
129#define UMCCH_ECCCTRL_ADDR2 (0x00014053 + 0x00001000)
130#define UMCCH_ECCCTRL_ADDR3 (0x00014053 + 0x00001800)
131#define UMCCH_ECCCTRL_ADDR4 (0x00054053 + 0x00000000)
132#define UMCCH_ECCCTRL_ADDR5 (0x00054053 + 0x00000800)
133#define UMCCH_ECCCTRL_ADDR6 (0x00054053 + 0x00001000)
134#define UMCCH_ECCCTRL_ADDR7 (0x00054053 + 0x00001800)
135#define UMCCH_ECCCTRL_ADDR8 (0x00094053 + 0x00000000)
136#define UMCCH_ECCCTRL_ADDR9 (0x00094053 + 0x00000800)
137#define UMCCH_ECCCTRL_ADDR10 (0x00094053 + 0x00001000)
138#define UMCCH_ECCCTRL_ADDR11 (0x00094053 + 0x00001800)
139#define UMCCH_ECCCTRL_ADDR12 (0x000d4053 + 0x00000000)
140#define UMCCH_ECCCTRL_ADDR13 (0x000d4053 + 0x00000800)
141#define UMCCH_ECCCTRL_ADDR14 (0x000d4053 + 0x00001000)
142#define UMCCH_ECCCTRL_ADDR15 (0x000d4053 + 0x00001800)
143
144static const uint32_t ecc_umclocalcap_addrs[] = {
145 UMCLOCALCAPS_ADDR0,
146 UMCLOCALCAPS_ADDR1,
147 UMCLOCALCAPS_ADDR2,
148 UMCLOCALCAPS_ADDR3,
149 UMCLOCALCAPS_ADDR4,
150 UMCLOCALCAPS_ADDR5,
151 UMCLOCALCAPS_ADDR6,
152 UMCLOCALCAPS_ADDR7,
153 UMCLOCALCAPS_ADDR8,
154 UMCLOCALCAPS_ADDR9,
155 UMCLOCALCAPS_ADDR10,
156 UMCLOCALCAPS_ADDR11,
157 UMCLOCALCAPS_ADDR12,
158 UMCLOCALCAPS_ADDR13,
159 UMCLOCALCAPS_ADDR14,
160 UMCLOCALCAPS_ADDR15,
161};
162
163static const uint32_t ecc_umcch_umc_config_addrs[] = {
164 UMCCH_UMC_CONFIG_ADDR0,
165 UMCCH_UMC_CONFIG_ADDR1,
166 UMCCH_UMC_CONFIG_ADDR2,
167 UMCCH_UMC_CONFIG_ADDR3,
168 UMCCH_UMC_CONFIG_ADDR4,
169 UMCCH_UMC_CONFIG_ADDR5,
170 UMCCH_UMC_CONFIG_ADDR6,
171 UMCCH_UMC_CONFIG_ADDR7,
172 UMCCH_UMC_CONFIG_ADDR8,
173 UMCCH_UMC_CONFIG_ADDR9,
174 UMCCH_UMC_CONFIG_ADDR10,
175 UMCCH_UMC_CONFIG_ADDR11,
176 UMCCH_UMC_CONFIG_ADDR12,
177 UMCCH_UMC_CONFIG_ADDR13,
178 UMCCH_UMC_CONFIG_ADDR14,
179 UMCCH_UMC_CONFIG_ADDR15,
180};
181
182static const uint32_t ecc_umcch_eccctrl_addrs[] = {
183 UMCCH_ECCCTRL_ADDR0,
184 UMCCH_ECCCTRL_ADDR1,
185 UMCCH_ECCCTRL_ADDR2,
186 UMCCH_ECCCTRL_ADDR3,
187 UMCCH_ECCCTRL_ADDR4,
188 UMCCH_ECCCTRL_ADDR5,
189 UMCCH_ECCCTRL_ADDR6,
190 UMCCH_ECCCTRL_ADDR7,
191 UMCCH_ECCCTRL_ADDR8,
192 UMCCH_ECCCTRL_ADDR9,
193 UMCCH_ECCCTRL_ADDR10,
194 UMCCH_ECCCTRL_ADDR11,
195 UMCCH_ECCCTRL_ADDR12,
196 UMCCH_ECCCTRL_ADDR13,
197 UMCCH_ECCCTRL_ADDR14,
198 UMCCH_ECCCTRL_ADDR15,
199};
200
e60f8db5
AX		 201static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
202 struct amdgpu_irq_src *src,
203 unsigned type,
204 enum amdgpu_interrupt_state state)
205{
206 struct amdgpu_vmhub *hub;
ae6d1416 207 u32 tmp, reg, bits, i, j;
e60f8db5 208
11250164
CK		 209 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
210 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
211 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
212 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
213 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
214 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
215 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
216
e60f8db5
AX		 217 switch (state) {
218 case AMDGPU_IRQ_STATE_DISABLE:
ae6d1416
TSD		 219 for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) {
220 hub = &adev->vmhub[j];
221 for (i = 0; i < 16; i++) {
222 reg = hub->vm_context0_cntl + i;
223 tmp = RREG32(reg);
224 tmp &= ~bits;
225 WREG32(reg, tmp);
226 }
e60f8db5
AX		 227 }
228 break;
229 case AMDGPU_IRQ_STATE_ENABLE:
ae6d1416
TSD		 230 for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) {
231 hub = &adev->vmhub[j];
232 for (i = 0; i < 16; i++) {
233 reg = hub->vm_context0_cntl + i;
234 tmp = RREG32(reg);
235 tmp |= bits;
236 WREG32(reg, tmp);
237 }
e60f8db5 238 }
e60f8db5
AX		 239 default:
240 break;
241 }
242
243 return 0;
244}
245
246static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
247 struct amdgpu_irq_src *source,
248 struct amdgpu_iv_entry *entry)
249{
c4f46f22 250 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src];
4d6cbde3 251 uint32_t status = 0;
e60f8db5
AX		 252 u64 addr;
253
254 addr = (u64)entry->src_data[0] << 12;
255 addr |= ((u64)entry->src_data[1] & 0xf) << 44;
256
79a0c465 257 if (!amdgpu_sriov_vf(adev)) {
5a9b8e8a
CK		 258 status = RREG32(hub->vm_l2_pro_fault_status);
259 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
4d6cbde3 260 }
e60f8db5 261
4d6cbde3 262 if (printk_ratelimit()) {
efaa9646
AG		 263 struct amdgpu_task_info task_info = { 0 };
264
265 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
266
4d6cbde3 267 dev_err(adev->dev,
efaa9646 268 "[%s] VMC page fault (src_id:%u ring:%u vmid:%u pasid:%u, for process %s pid %d thread %s pid %d\n)\n",
c4f46f22
CK		 269 entry->vmid_src ? "mmhub" : "gfxhub",
270 entry->src_id, entry->ring_id, entry->vmid,
efaa9646
AG		 271 entry->pasid, task_info.process_name, task_info.tgid,
272 task_info.task_name, task_info.pid);
6cdf4e87 273 dev_err(adev->dev, " at address 0x%016llx from %d\n",
4d6cbde3
FK		 274 addr, entry->client_id);
275 if (!amdgpu_sriov_vf(adev))
276 dev_err(adev->dev,
277 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
278 status);
79a0c465 279 }
e60f8db5
AX		 280
281 return 0;
282}
283
284static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = {
285 .set = gmc_v9_0_vm_fault_interrupt_state,
286 .process = gmc_v9_0_process_interrupt,
287};
288
289static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev)
290{
770d13b1
CK		 291 adev->gmc.vm_fault.num_types = 1;
292 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs;
e60f8db5
AX		 293}
294
c4f46f22 295static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid)
03f89feb
CK		 296{
297 u32 req = 0;
298
c4f46f22 299 /* invalidate using legacy mode on vmid*/
03f89feb 300 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
c4f46f22 301 PER_VMID_INVALIDATE_REQ, 1 << vmid);
03f89feb
CK		 302 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, 0);
303 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
304 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
305 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
306 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
307 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
308 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
309 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
310
311 return req;
312}
313
1849e737 314static signed long amdgpu_kiq_reg_write_reg_wait(struct amdgpu_device *adev,
3890d111
ED		 315 uint32_t reg0, uint32_t reg1,
316 uint32_t ref, uint32_t mask)
317{
318 signed long r, cnt = 0;
319 unsigned long flags;
320 uint32_t seq;
321 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
322 struct amdgpu_ring *ring = &kiq->ring;
323
3890d111
ED		 324 spin_lock_irqsave(&kiq->ring_lock, flags);
325
326 amdgpu_ring_alloc(ring, 32);
327 amdgpu_ring_emit_reg_write_reg_wait(ring, reg0, reg1,
328 ref, mask);
329 amdgpu_fence_emit_polling(ring, &seq);
330 amdgpu_ring_commit(ring);
331 spin_unlock_irqrestore(&kiq->ring_lock, flags);
332
333 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
334
ae74da3e
ED		 335 /* don't wait anymore for IRQ context */
336 if (r < 1 && in_interrupt())
3890d111
ED		 337 goto failed_kiq;
338
339 might_sleep();
340
341 while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
342 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
343 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
344 }
345
346 if (cnt > MAX_KIQ_REG_TRY)
347 goto failed_kiq;
348
349 return 0;
350
351failed_kiq:
352 pr_err("failed to invalidate tlb with kiq\n");
353 return r;
354}
355
e60f8db5
AX		 356/*
357 * GART
358 * VMID 0 is the physical GPU addresses as used by the kernel.
359 * VMIDs 1-15 are used for userspace clients and are handled
360 * by the amdgpu vm/hsa code.
361 */
362
363/**
132f34e4 364 * gmc_v9_0_flush_gpu_tlb - gart tlb flush callback
e60f8db5
AX		 365 *
366 * @adev: amdgpu_device pointer
367 * @vmid: vm instance to flush
368 *
369 * Flush the TLB for the requested page table.
370 */
132f34e4 371static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev,
e60f8db5
AX		 372 uint32_t vmid)
373{
374 /* Use register 17 for GART */
375 const unsigned eng = 17;
376 unsigned i, j;
3890d111 377 int r;
e60f8db5
AX		 378
379 for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
380 struct amdgpu_vmhub *hub = &adev->vmhub[i];
03f89feb 381 u32 tmp = gmc_v9_0_get_invalidate_req(vmid);
e60f8db5 382
fc0faf04 383 if (adev->gfx.kiq.ring.ready &&
ae74da3e
ED		 384 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) &&
385 !adev->in_gpu_reset) {
fc0faf04
ED		 386 r = amdgpu_kiq_reg_write_reg_wait(adev, hub->vm_inv_eng0_req + eng,
387 hub->vm_inv_eng0_ack + eng, tmp, 1 << vmid);
388 if (!r)
389 continue;
390 }
3890d111
ED		 391
392 spin_lock(&adev->gmc.invalidate_lock);
393
c7a7266b 394 WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);
e60f8db5
AX		 395
396 /* Busy wait for ACK.*/
397 for (j = 0; j < 100; j++) {
c7a7266b 398 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
e60f8db5
AX		 399 tmp &= 1 << vmid;
400 if (tmp)
401 break;
402 cpu_relax();
403 }
3890d111
ED		 404 if (j < 100) {
405 spin_unlock(&adev->gmc.invalidate_lock);
e60f8db5 406 continue;
3890d111 407 }
e60f8db5
AX		 408
409 /* Wait for ACK with a delay.*/
410 for (j = 0; j < adev->usec_timeout; j++) {
c7a7266b 411 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
e60f8db5
AX		 412 tmp &= 1 << vmid;
413 if (tmp)
414 break;
415 udelay(1);
416 }
3890d111
ED		 417 if (j < adev->usec_timeout) {
418 spin_unlock(&adev->gmc.invalidate_lock);
e60f8db5 419 continue;
3890d111
ED		 420 }
421 spin_unlock(&adev->gmc.invalidate_lock);
e60f8db5
AX		 422 DRM_ERROR("Timeout waiting for VM flush ACK!\n");
423 }
e60f8db5
AX		 424}
425
9096d6e5 426static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
c633c00b 427 unsigned vmid, uint64_t pd_addr)
9096d6e5 428{
250b4228
CK		 429 struct amdgpu_device *adev = ring->adev;
430 struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub];
9096d6e5
CK		 431 uint32_t req = gmc_v9_0_get_invalidate_req(vmid);
432 uint64_t flags = AMDGPU_PTE_VALID;
433 unsigned eng = ring->vm_inv_eng;
434
c633c00b 435 amdgpu_gmc_get_vm_pde(adev, -1, &pd_addr, &flags);
9096d6e5
CK		 436 pd_addr |= flags;
437
438 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid),
439 lower_32_bits(pd_addr));
440
441 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid),
442 upper_32_bits(pd_addr));
443
f8bc9037
AD		 444 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + eng,
445 hub->vm_inv_eng0_ack + eng,
446 req, 1 << vmid);
f732b6b3 447
9096d6e5
CK		 448 return pd_addr;
449}
450
c633c00b
CK		 451static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
452 unsigned pasid)
453{
454 struct amdgpu_device *adev = ring->adev;
455 uint32_t reg;
456
457 if (ring->funcs->vmhub == AMDGPU_GFXHUB)
458 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
459 else
460 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
461
462 amdgpu_ring_emit_wreg(ring, reg, pasid);
463}
464
e60f8db5 465/**
132f34e4 466 * gmc_v9_0_set_pte_pde - update the page tables using MMIO
e60f8db5
AX		 467 *
468 * @adev: amdgpu_device pointer
469 * @cpu_pt_addr: cpu address of the page table
470 * @gpu_page_idx: entry in the page table to update
471 * @addr: dst addr to write into pte/pde
472 * @flags: access flags
473 *
474 * Update the page tables using the CPU.
475 */
132f34e4
CK		 476static int gmc_v9_0_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr,
477 uint32_t gpu_page_idx, uint64_t addr,
478 uint64_t flags)
e60f8db5
AX		 479{
480 void __iomem *ptr = (void *)cpu_pt_addr;
481 uint64_t value;
482
483 /*
484 * PTE format on VEGA 10:
485 * 63:59 reserved
486 * 58:57 mtype
487 * 56 F
488 * 55 L
489 * 54 P
490 * 53 SW
491 * 52 T
492 * 50:48 reserved
493 * 47:12 4k physical page base address
494 * 11:7 fragment
495 * 6 write
496 * 5 read
497 * 4 exe
498 * 3 Z
499 * 2 snooped
500 * 1 system
501 * 0 valid
502 *
503 * PDE format on VEGA 10:
504 * 63:59 block fragment size
505 * 58:55 reserved
506 * 54 P
507 * 53:48 reserved
508 * 47:6 physical base address of PD or PTE
509 * 5:3 reserved
510 * 2 C
511 * 1 system
512 * 0 valid
513 */
514
515 /*
516 * The following is for PTE only. GART does not have PDEs.
517 */
518 value = addr & 0x0000FFFFFFFFF000ULL;
519 value |= flags;
520 writeq(value, ptr + (gpu_page_idx * 8));
521 return 0;
522}
523
524static uint64_t gmc_v9_0_get_vm_pte_flags(struct amdgpu_device *adev,
525 uint32_t flags)
526
527{
528 uint64_t pte_flag = 0;
529
530 if (flags & AMDGPU_VM_PAGE_EXECUTABLE)
531 pte_flag |= AMDGPU_PTE_EXECUTABLE;
532 if (flags & AMDGPU_VM_PAGE_READABLE)
533 pte_flag |= AMDGPU_PTE_READABLE;
534 if (flags & AMDGPU_VM_PAGE_WRITEABLE)
535 pte_flag |= AMDGPU_PTE_WRITEABLE;
536
537 switch (flags & AMDGPU_VM_MTYPE_MASK) {
538 case AMDGPU_VM_MTYPE_DEFAULT:
539 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
540 break;
541 case AMDGPU_VM_MTYPE_NC:
542 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
543 break;
544 case AMDGPU_VM_MTYPE_WC:
545 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_WC);
546 break;
547 case AMDGPU_VM_MTYPE_CC:
548 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_CC);
549 break;
550 case AMDGPU_VM_MTYPE_UC:
551 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_UC);
552 break;
553 default:
554 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
555 break;
556 }
557
558 if (flags & AMDGPU_VM_PAGE_PRT)
559 pte_flag |= AMDGPU_PTE_PRT;
560
561 return pte_flag;
562}
563
3de676d8
CK		 564static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
565 uint64_t *addr, uint64_t *flags)
e60f8db5 566{
3de676d8
CK		 567 if (!(*flags & AMDGPU_PDE_PTE))
568 *addr = adev->vm_manager.vram_base_offset + *addr -
770d13b1 569 adev->gmc.vram_start;
3de676d8 570 BUG_ON(*addr & 0xFFFF00000000003FULL);
6a42fd6f 571
770d13b1 572 if (!adev->gmc.translate_further)
6a42fd6f
CK		 573 return;
574
575 if (level == AMDGPU_VM_PDB1) {
576 /* Set the block fragment size */
577 if (!(*flags & AMDGPU_PDE_PTE))
578 *flags |= AMDGPU_PDE_BFS(0x9);
579
580 } else if (level == AMDGPU_VM_PDB0) {
581 if (*flags & AMDGPU_PDE_PTE)
582 *flags &= ~AMDGPU_PDE_PTE;
583 else
584 *flags |= AMDGPU_PTE_TF;
585 }
e60f8db5
AX		 586}
587
132f34e4
CK		 588static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = {
589 .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb,
9096d6e5 590 .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb,
c633c00b 591 .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping,
132f34e4 592 .set_pte_pde = gmc_v9_0_set_pte_pde,
b1166325
CK		 593 .get_vm_pte_flags = gmc_v9_0_get_vm_pte_flags,
594 .get_vm_pde = gmc_v9_0_get_vm_pde
e60f8db5
AX		 595};
596
132f34e4 597static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev)
e60f8db5 598{
132f34e4
CK		 599 if (adev->gmc.gmc_funcs == NULL)
600 adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs;
e60f8db5
AX		 601}
602
603static int gmc_v9_0_early_init(void *handle)
604{
605 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
606
132f34e4 607 gmc_v9_0_set_gmc_funcs(adev);
e60f8db5
AX		 608 gmc_v9_0_set_irq_funcs(adev);
609
770d13b1
CK		 610 adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
611 adev->gmc.shared_aperture_end =
612 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
bfa8eea2 613 adev->gmc.private_aperture_start = 0x1000000000000000ULL;
770d13b1
CK		 614 adev->gmc.private_aperture_end =
615 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
a7ea6548 616
e60f8db5
AX		 617 return 0;
618}
619
02bab923
DP		 620static int gmc_v9_0_ecc_available(struct amdgpu_device *adev)
621{
622 uint32_t reg_val;
623 uint32_t reg_addr;
624 uint32_t field_val;
625 size_t i;
626 uint32_t fv2;
627 size_t lost_sheep;
628
629 DRM_DEBUG("ecc: gmc_v9_0_ecc_available()\n");
630
631 lost_sheep = 0;
632 for (i = 0; i < ARRAY_SIZE(ecc_umclocalcap_addrs); ++i) {
633 reg_addr = ecc_umclocalcap_addrs[i];
634 DRM_DEBUG("ecc: "
635 "UMCCH_UmcLocalCap[%zu]: reg_addr: 0x%08x\n",
636 i, reg_addr);
637 reg_val = RREG32(reg_addr);
638 field_val = REG_GET_FIELD(reg_val, UMCCH0_0_UmcLocalCap,
639 EccDis);
640 DRM_DEBUG("ecc: "
641 "reg_val: 0x%08x, "
642 "EccDis: 0x%08x, ",
643 reg_val, field_val);
644 if (field_val) {
645 DRM_ERROR("ecc: UmcLocalCap:EccDis is set.\n");
646 ++lost_sheep;
647 }
648 }
649
650 for (i = 0; i < ARRAY_SIZE(ecc_umcch_umc_config_addrs); ++i) {
651 reg_addr = ecc_umcch_umc_config_addrs[i];
652 DRM_DEBUG("ecc: "
653 "UMCCH0_0_UMC_CONFIG[%zu]: reg_addr: 0x%08x",
654 i, reg_addr);
655 reg_val = RREG32(reg_addr);
656 field_val = REG_GET_FIELD(reg_val, UMCCH0_0_UMC_CONFIG,
657 DramReady);
658 DRM_DEBUG("ecc: "
659 "reg_val: 0x%08x, "
660 "DramReady: 0x%08x\n",
661 reg_val, field_val);
662
663 if (!field_val) {
664 DRM_ERROR("ecc: UMC_CONFIG:DramReady is not set.\n");
665 ++lost_sheep;
666 }
667 }
668
669 for (i = 0; i < ARRAY_SIZE(ecc_umcch_eccctrl_addrs); ++i) {
670 reg_addr = ecc_umcch_eccctrl_addrs[i];
671 DRM_DEBUG("ecc: "
672 "UMCCH_EccCtrl[%zu]: reg_addr: 0x%08x, ",
673 i, reg_addr);
674 reg_val = RREG32(reg_addr);
675 field_val = REG_GET_FIELD(reg_val, UMCCH0_0_EccCtrl,
676 WrEccEn);
677 fv2 = REG_GET_FIELD(reg_val, UMCCH0_0_EccCtrl,
678 RdEccEn);
679 DRM_DEBUG("ecc: "
680 "reg_val: 0x%08x, "
681 "WrEccEn: 0x%08x, "
682 "RdEccEn: 0x%08x\n",
683 reg_val, field_val, fv2);
684
685 if (!field_val) {
5a16008f 686 DRM_DEBUG("ecc: WrEccEn is not set\n");
02bab923
DP		 687 ++lost_sheep;
688 }
689 if (!fv2) {
5a16008f 690 DRM_DEBUG("ecc: RdEccEn is not set\n");
02bab923
DP		 691 ++lost_sheep;
692 }
693 }
694
695 DRM_DEBUG("ecc: lost_sheep: %zu\n", lost_sheep);
696 return lost_sheep == 0;
697}
698
e60f8db5
AX		 699static int gmc_v9_0_late_init(void *handle)
700{
701 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
c5066129 702 /*
703 * The latest engine allocation on gfx9 is:
704 * Engine 0, 1: idle
705 * Engine 2, 3: firmware
706 * Engine 4~13: amdgpu ring, subject to change when ring number changes
707 * Engine 14~15: idle
708 * Engine 16: kfd tlb invalidation
709 * Engine 17: Gart flushes
710 */
711 unsigned vm_inv_eng[AMDGPU_MAX_VMHUBS] = { 4, 4 };
4789c463 712 unsigned i;
02bab923 713 int r;
4789c463 714
6f752ec2
AG		 715 /*
716 * TODO - Uncomment once GART corruption issue is fixed.
717 */
718 /* amdgpu_bo_late_init(adev); */
719
4789c463
CK		 720 for(i = 0; i < adev->num_rings; ++i) {
721 struct amdgpu_ring *ring = adev->rings[i];
722 unsigned vmhub = ring->funcs->vmhub;
723
724 ring->vm_inv_eng = vm_inv_eng[vmhub]++;
775f55f1
TSD		 725 dev_info(adev->dev, "ring %u(%s) uses VM inv eng %u on hub %u\n",
726 ring->idx, ring->name, ring->vm_inv_eng,
727 ring->funcs->vmhub);
4789c463
CK		 728 }
729
c5066129 730 /* Engine 16 is used for KFD and 17 for GART flushes */
4789c463 731 for(i = 0; i < AMDGPU_MAX_VMHUBS; ++i)
c5066129 732 BUG_ON(vm_inv_eng[i] > 16);
4789c463 733
7b6cbae2 734 if (adev->asic_type == CHIP_VEGA10 && !amdgpu_sriov_vf(adev)) {
5ba4fa35
AD		 735 r = gmc_v9_0_ecc_available(adev);
736 if (r == 1) {
737 DRM_INFO("ECC is active.\n");
738 } else if (r == 0) {
739 DRM_INFO("ECC is not present.\n");
e1d1a772 740 adev->df_funcs->enable_ecc_force_par_wr_rmw(adev, false);
5ba4fa35
AD		 741 } else {
742 DRM_ERROR("gmc_v9_0_ecc_available() failed. r: %d\n", r);
743 return r;
744 }
02bab923
DP		 745 }
746
770d13b1 747 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
e60f8db5
AX		 748}
749
750static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
770d13b1 751 struct amdgpu_gmc *mc)
e60f8db5 752{
eeb2487d
ML		 753 u64 base = 0;
754 if (!amdgpu_sriov_vf(adev))
755 base = mmhub_v1_0_get_fb_location(adev);
770d13b1 756 amdgpu_device_vram_location(adev, &adev->gmc, base);
2543e28a 757 amdgpu_device_gart_location(adev, mc);
bc099ee9 758 /* base offset of vram pages */
b6110c00 759 adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev);
e60f8db5
AX		 760}
761
762/**
763 * gmc_v9_0_mc_init - initialize the memory controller driver params
764 *
765 * @adev: amdgpu_device pointer
766 *
767 * Look up the amount of vram, vram width, and decide how to place
768 * vram and gart within the GPU's physical address space.
769 * Returns 0 for success.
770 */
771static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
772{
e60f8db5 773 int chansize, numchan;
d6895ad3 774 int r;
e60f8db5 775
3d918c0e
SL		 776 if (amdgpu_emu_mode != 1)
777 adev->gmc.vram_width = amdgpu_atomfirmware_get_vram_width(adev);
770d13b1 778 if (!adev->gmc.vram_width) {
8d6a5230 779 /* hbm memory channel size */
585b7f16
TSD		 780 if (adev->flags & AMD_IS_APU)
781 chansize = 64;
782 else
783 chansize = 128;
8d6a5230 784
070706c0 785 numchan = adev->df_funcs->get_hbm_channel_number(adev);
770d13b1 786 adev->gmc.vram_width = numchan * chansize;
e60f8db5 787 }
e60f8db5 788
e60f8db5 789 /* size in MB on si */
770d13b1 790 adev->gmc.mc_vram_size =
bf383fb6 791 adev->nbio_funcs->get_memsize(adev) * 1024ULL * 1024ULL;
770d13b1 792 adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
d6895ad3
CK		 793
794 if (!(adev->flags & AMD_IS_APU)) {
795 r = amdgpu_device_resize_fb_bar(adev);
796 if (r)
797 return r;
798 }
770d13b1
CK		 799 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
800 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
e60f8db5 801
156a81be
CZ		 802#ifdef CONFIG_X86_64
803 if (adev->flags & AMD_IS_APU) {
804 adev->gmc.aper_base = gfxhub_v1_0_get_mc_fb_offset(adev);
805 adev->gmc.aper_size = adev->gmc.real_vram_size;
806 }
807#endif
e60f8db5 808 /* In case the PCI BAR is larger than the actual amount of vram */
770d13b1
CK		 809 adev->gmc.visible_vram_size = adev->gmc.aper_size;
810 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
811 adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
e60f8db5 812
c3db7b5a
AD		 813 /* set the gart size */
814 if (amdgpu_gart_size == -1) {
815 switch (adev->asic_type) {
816 case CHIP_VEGA10: /* all engines support GPUVM */
273a14cd 817 case CHIP_VEGA12: /* all engines support GPUVM */
d96b428c 818 case CHIP_VEGA20:
c3db7b5a 819 default:
fe19b862 820 adev->gmc.gart_size = 512ULL << 20;
c3db7b5a
AD		 821 break;
822 case CHIP_RAVEN: /* DCE SG support */
770d13b1 823 adev->gmc.gart_size = 1024ULL << 20;
c3db7b5a
AD		 824 break;
825 }
826 } else {
770d13b1 827 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
c3db7b5a
AD		 828 }
829
770d13b1 830 gmc_v9_0_vram_gtt_location(adev, &adev->gmc);
e60f8db5
AX		 831
832 return 0;
833}
834
835static int gmc_v9_0_gart_init(struct amdgpu_device *adev)
836{
837 int r;
838
839 if (adev->gart.robj) {
840 WARN(1, "VEGA10 PCIE GART already initialized\n");
841 return 0;
842 }
843 /* Initialize common gart structure */
844 r = amdgpu_gart_init(adev);
845 if (r)
846 return r;
847 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
848 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE(MTYPE_UC) |
849 AMDGPU_PTE_EXECUTABLE;
850 return amdgpu_gart_table_vram_alloc(adev);
851}
852
ebdef28e
AD		 853static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev)
854{
855#if 0
856 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
857#endif
858 unsigned size;
859
6f752ec2
AG		 860 /*
861 * TODO Remove once GART corruption is resolved
862 * Check related code in gmc_v9_0_sw_fini
863 * */
864 size = 9 * 1024 * 1024;
865
866#if 0
ebdef28e
AD		 867 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
868 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */
869 } else {
870 u32 viewport;
871
872 switch (adev->asic_type) {
873 case CHIP_RAVEN:
874 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
875 size = (REG_GET_FIELD(viewport,
876 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
877 REG_GET_FIELD(viewport,
878 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) *
879 4);
880 break;
881 case CHIP_VEGA10:
882 case CHIP_VEGA12:
883 default:
884 viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE);
885 size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
886 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) *
887 4);
888 break;
889 }
890 }
891 /* return 0 if the pre-OS buffer uses up most of vram */
892 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024))
893 return 0;
6f752ec2
AG		 894
895#endif
ebdef28e
AD		 896 return size;
897}
898
e60f8db5
AX		 899static int gmc_v9_0_sw_init(void *handle)
900{
901 int r;
902 int dma_bits;
903 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
904
0c8c0847 905 gfxhub_v1_0_init(adev);
77f6c763 906 mmhub_v1_0_init(adev);
0c8c0847 907
770d13b1 908 spin_lock_init(&adev->gmc.invalidate_lock);
e60f8db5 909
1e09b053 910 adev->gmc.vram_type = amdgpu_atomfirmware_get_vram_type(adev);
fd66560b
HZ		 911 switch (adev->asic_type) {
912 case CHIP_RAVEN:
6a42fd6f 913 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
f3368128 914 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
6a42fd6f
CK		 915 } else {
916 /* vm_size is 128TB + 512GB for legacy 3-level page support */
917 amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48);
770d13b1 918 adev->gmc.translate_further =
6a42fd6f
CK		 919 adev->vm_manager.num_level > 1;
920 }
fd66560b
HZ		 921 break;
922 case CHIP_VEGA10:
273a14cd 923 case CHIP_VEGA12:
d96b428c 924 case CHIP_VEGA20:
36b32a68
ZJ		 925 /*
926 * To fulfill 4-level page support,
927 * vm size is 256TB (48bit), maximum size of Vega10,
928 * block size 512 (9bit)
929 */
f3368128 930 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
fd66560b
HZ		 931 break;
932 default:
933 break;
e60f8db5
AX		 934 }
935
936 /* This interrupt is VMC page fault.*/
44a99b65 937 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT,
770d13b1 938 &adev->gmc.vm_fault);
44a99b65 939 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT,
770d13b1 940 &adev->gmc.vm_fault);
e60f8db5
AX		 941
942 if (r)
943 return r;
944
e60f8db5
AX		 945 /* Set the internal MC address mask
946 * This is the max address of the GPU's
947 * internal address space.
948 */
770d13b1 949 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
e60f8db5
AX		 950
951 /* set DMA mask + need_dma32 flags.
952 * PCIE - can handle 44-bits.
953 * IGP - can handle 44-bits
954 * PCI - dma32 for legacy pci gart, 44 bits on vega10
955 */
956 adev->need_dma32 = false;
957 dma_bits = adev->need_dma32 ? 32 : 44;
958 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
959 if (r) {
960 adev->need_dma32 = true;
961 dma_bits = 32;
962 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
963 }
964 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
965 if (r) {
966 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
967 printk(KERN_WARNING "amdgpu: No coherent DMA available.\n");
968 }
fd5fd480 969 adev->need_swiotlb = drm_get_max_iomem() > ((u64)1 << dma_bits);
e60f8db5
AX		 970
971 r = gmc_v9_0_mc_init(adev);
972 if (r)
973 return r;
974
ebdef28e
AD		 975 adev->gmc.stolen_size = gmc_v9_0_get_vbios_fb_size(adev);
976
e60f8db5
AX		 977 /* Memory manager */
978 r = amdgpu_bo_init(adev);
979 if (r)
980 return r;
981
982 r = gmc_v9_0_gart_init(adev);
983 if (r)
984 return r;
985
05ec3eda
CK		 986 /*
987 * number of VMs
988 * VMID 0 is reserved for System
989 * amdgpu graphics/compute will use VMIDs 1-7
990 * amdkfd will use VMIDs 8-15
991 */
992 adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids = AMDGPU_NUM_OF_VMIDS;
993 adev->vm_manager.id_mgr[AMDGPU_MMHUB].num_ids = AMDGPU_NUM_OF_VMIDS;
994
05ec3eda
CK		 995 amdgpu_vm_manager_init(adev);
996
997 return 0;
e60f8db5
AX		 998}
999
e60f8db5
AX		 1000static int gmc_v9_0_sw_fini(void *handle)
1001{
1002 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1003
f59548c8 1004 amdgpu_gem_force_release(adev);
05ec3eda 1005 amdgpu_vm_manager_fini(adev);
6f752ec2
AG		 1006
1007 /*
1008 * TODO:
1009 * Currently there is a bug where some memory client outside
1010 * of the driver writes to first 8M of VRAM on S3 resume,
1011 * this overrides GART which by default gets placed in first 8M and
1012 * causes VM_FAULTS once GTT is accessed.
1013 * Keep the stolen memory reservation until the while this is not solved.
1014 * Also check code in gmc_v9_0_get_vbios_fb_size and gmc_v9_0_late_init
1015 */
1016 amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, NULL);
1017
a3d9103e 1018 amdgpu_gart_table_vram_free(adev);
e60f8db5 1019 amdgpu_bo_fini(adev);
a3d9103e 1020 amdgpu_gart_fini(adev);
e60f8db5
AX		 1021
1022 return 0;
1023}
1024
1025static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
1026{
946a4d5b 1027
e60f8db5
AX		 1028 switch (adev->asic_type) {
1029 case CHIP_VEGA10:
d96b428c 1030 case CHIP_VEGA20:
946a4d5b 1031 soc15_program_register_sequence(adev,
5c583018 1032 golden_settings_mmhub_1_0_0,
c47b41a7 1033 ARRAY_SIZE(golden_settings_mmhub_1_0_0));
946a4d5b 1034 soc15_program_register_sequence(adev,
5c583018 1035 golden_settings_athub_1_0_0,
c47b41a7 1036 ARRAY_SIZE(golden_settings_athub_1_0_0));
e60f8db5 1037 break;
273a14cd
AD		 1038 case CHIP_VEGA12:
1039 break;
e4f3abaa 1040 case CHIP_RAVEN:
946a4d5b 1041 soc15_program_register_sequence(adev,
5c583018 1042 golden_settings_athub_1_0_0,
c47b41a7 1043 ARRAY_SIZE(golden_settings_athub_1_0_0));
e4f3abaa 1044 break;
e60f8db5
AX		 1045 default:
1046 break;
1047 }
1048}
1049
1050/**
1051 * gmc_v9_0_gart_enable - gart enable
1052 *
1053 * @adev: amdgpu_device pointer
1054 */
1055static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
1056{
1057 int r;
1058 bool value;
1059 u32 tmp;
1060
9c3f2b54
AD		 1061 amdgpu_device_program_register_sequence(adev,
1062 golden_settings_vega10_hdp,
1063 ARRAY_SIZE(golden_settings_vega10_hdp));
e60f8db5
AX		 1064
1065 if (adev->gart.robj == NULL) {
1066 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
1067 return -EINVAL;
1068 }
ce1b1b66
ML		 1069 r = amdgpu_gart_table_vram_pin(adev);
1070 if (r)
1071 return r;
e60f8db5 1072
2fcd43ce
HZ		 1073 switch (adev->asic_type) {
1074 case CHIP_RAVEN:
1075 mmhub_v1_0_initialize_power_gating(adev);
f8386b35 1076 mmhub_v1_0_update_power_gating(adev, true);
2fcd43ce
HZ		 1077 break;
1078 default:
1079 break;
1080 }
1081
e60f8db5
AX		 1082 r = gfxhub_v1_0_gart_enable(adev);
1083 if (r)
1084 return r;
1085
1086 r = mmhub_v1_0_gart_enable(adev);
1087 if (r)
1088 return r;
1089
846347c9 1090 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
e60f8db5 1091
b9509c80
HR		 1092 tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL);
1093 WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);
e60f8db5 1094
1d4e0a8c 1095 /* After HDP is initialized, flush HDP.*/
69882565 1096 adev->nbio_funcs->hdp_flush(adev, NULL);
1d4e0a8c 1097
e60f8db5
AX		 1098 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
1099 value = false;
1100 else
1101 value = true;
1102
1103 gfxhub_v1_0_set_fault_enable_default(adev, value);
1104 mmhub_v1_0_set_fault_enable_default(adev, value);
132f34e4 1105 gmc_v9_0_flush_gpu_tlb(adev, 0);
e60f8db5
AX		 1106
1107 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
770d13b1 1108 (unsigned)(adev->gmc.gart_size >> 20),
e60f8db5
AX		 1109 (unsigned long long)adev->gart.table_addr);
1110 adev->gart.ready = true;
1111 return 0;
1112}
1113
1114static int gmc_v9_0_hw_init(void *handle)
1115{
1116 int r;
1117 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1118
1119 /* The sequence of these two function calls matters.*/
1120 gmc_v9_0_init_golden_registers(adev);
1121
edca2d05 1122 if (adev->mode_info.num_crtc) {
edca2d05 1123 /* Lockout access through VGA aperture*/
4d9c333a 1124 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
edca2d05
AD		 1125
1126 /* disable VGA render */
4d9c333a 1127 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
edca2d05
AD		 1128 }
1129
e60f8db5
AX		 1130 r = gmc_v9_0_gart_enable(adev);
1131
1132 return r;
1133}
1134
1135/**
1136 * gmc_v9_0_gart_disable - gart disable
1137 *
1138 * @adev: amdgpu_device pointer
1139 *
1140 * This disables all VM page table.
1141 */
1142static void gmc_v9_0_gart_disable(struct amdgpu_device *adev)
1143{
1144 gfxhub_v1_0_gart_disable(adev);
1145 mmhub_v1_0_gart_disable(adev);
ce1b1b66 1146 amdgpu_gart_table_vram_unpin(adev);
e60f8db5
AX		 1147}
1148
1149static int gmc_v9_0_hw_fini(void *handle)
1150{
1151 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1152
5dd696ae
TH		 1153 if (amdgpu_sriov_vf(adev)) {
1154 /* full access mode, so don't touch any GMC register */
1155 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
1156 return 0;
1157 }
1158
770d13b1 1159 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
e60f8db5
AX		 1160 gmc_v9_0_gart_disable(adev);
1161
1162 return 0;
1163}
1164
1165static int gmc_v9_0_suspend(void *handle)
1166{
1167 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1168
f053cd47 1169 return gmc_v9_0_hw_fini(adev);
e60f8db5
AX		 1170}
1171
1172static int gmc_v9_0_resume(void *handle)
1173{
1174 int r;
1175 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1176
1177 r = gmc_v9_0_hw_init(adev);
1178 if (r)
1179 return r;
1180
620f774f 1181 amdgpu_vmid_reset_all(adev);
e60f8db5 1182
32601d48 1183 return 0;
e60f8db5
AX		 1184}
1185
1186static bool gmc_v9_0_is_idle(void *handle)
1187{
1188 /* MC is always ready in GMC v9.*/
1189 return true;
1190}
1191
1192static int gmc_v9_0_wait_for_idle(void *handle)
1193{
1194 /* There is no need to wait for MC idle in GMC v9.*/
1195 return 0;
1196}
1197
1198static int gmc_v9_0_soft_reset(void *handle)
1199{
1200 /* XXX for emulation.*/
1201 return 0;
1202}
1203
1204static int gmc_v9_0_set_clockgating_state(void *handle,
1205 enum amd_clockgating_state state)
1206{
d5583d4f
HR		 1207 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1208
1209 return mmhub_v1_0_set_clockgating(adev, state);
e60f8db5
AX		 1210}
1211
13052be5
HR		 1212static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags)
1213{
1214 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1215
1216 mmhub_v1_0_get_clockgating(adev, flags);
1217}
1218
e60f8db5
AX		 1219static int gmc_v9_0_set_powergating_state(void *handle,
1220 enum amd_powergating_state state)
1221{
1222 return 0;
1223}
1224
1225const struct amd_ip_funcs gmc_v9_0_ip_funcs = {
1226 .name = "gmc_v9_0",
1227 .early_init = gmc_v9_0_early_init,
1228 .late_init = gmc_v9_0_late_init,
1229 .sw_init = gmc_v9_0_sw_init,
1230 .sw_fini = gmc_v9_0_sw_fini,
1231 .hw_init = gmc_v9_0_hw_init,
1232 .hw_fini = gmc_v9_0_hw_fini,
1233 .suspend = gmc_v9_0_suspend,
1234 .resume = gmc_v9_0_resume,
1235 .is_idle = gmc_v9_0_is_idle,
1236 .wait_for_idle = gmc_v9_0_wait_for_idle,
1237 .soft_reset = gmc_v9_0_soft_reset,
1238 .set_clockgating_state = gmc_v9_0_set_clockgating_state,
1239 .set_powergating_state = gmc_v9_0_set_powergating_state,
13052be5 1240 .get_clockgating_state = gmc_v9_0_get_clockgating_state,
e60f8db5
AX		 1241};
1242
1243const struct amdgpu_ip_block_version gmc_v9_0_ip_block =
1244{
1245 .type = AMD_IP_BLOCK_TYPE_GMC,
1246 .major = 9,
1247 .minor = 0,
1248 .rev = 0,
1249 .funcs = &gmc_v9_0_ip_funcs,
1250};
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