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drm/amd/amdgpu: Change comp GFXv9 ring name to remove space
[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / amd / amdgpu / gmc_v9_0.c
CommitLineData
e60f8db5
AX		 1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include "amdgpu.h"
25#include "gmc_v9_0.h"
26
27#include "vega10/soc15ip.h"
28#include "vega10/HDP/hdp_4_0_offset.h"
29#include "vega10/HDP/hdp_4_0_sh_mask.h"
30#include "vega10/GC/gc_9_0_sh_mask.h"
31#include "vega10/vega10_enum.h"
32
33#include "soc15_common.h"
34
35#include "nbio_v6_1.h"
36#include "gfxhub_v1_0.h"
37#include "mmhub_v1_0.h"
38
39#define mmDF_CS_AON0_DramBaseAddress0 0x0044
40#define mmDF_CS_AON0_DramBaseAddress0_BASE_IDX 0
41//DF_CS_AON0_DramBaseAddress0
42#define DF_CS_AON0_DramBaseAddress0__AddrRngVal__SHIFT 0x0
43#define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT 0x1
44#define DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT 0x4
45#define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT 0x8
46#define DF_CS_AON0_DramBaseAddress0__DramBaseAddr__SHIFT 0xc
47#define DF_CS_AON0_DramBaseAddress0__AddrRngVal_MASK 0x00000001L
48#define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK 0x00000002L
49#define DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK 0x000000F0L
50#define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK 0x00000700L
51#define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK 0xFFFFF000L
52
53/* XXX Move this macro to VEGA10 header file, which is like vid.h for VI.*/
54#define AMDGPU_NUM_OF_VMIDS 8
55
56static const u32 golden_settings_vega10_hdp[] =
57{
58 0xf64, 0x0fffffff, 0x00000000,
59 0xf65, 0x0fffffff, 0x00000000,
60 0xf66, 0x0fffffff, 0x00000000,
61 0xf67, 0x0fffffff, 0x00000000,
62 0xf68, 0x0fffffff, 0x00000000,
63 0xf6a, 0x0fffffff, 0x00000000,
64 0xf6b, 0x0fffffff, 0x00000000,
65 0xf6c, 0x0fffffff, 0x00000000,
66 0xf6d, 0x0fffffff, 0x00000000,
67 0xf6e, 0x0fffffff, 0x00000000,
68};
69
70static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
71 struct amdgpu_irq_src *src,
72 unsigned type,
73 enum amdgpu_interrupt_state state)
74{
75 struct amdgpu_vmhub *hub;
76 u32 tmp, reg, bits, i;
77
11250164
CK		 78 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
79 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
80 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
81 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
82 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
83 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
84 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
85
e60f8db5
AX		 86 switch (state) {
87 case AMDGPU_IRQ_STATE_DISABLE:
88 /* MM HUB */
89 hub = &adev->vmhub[AMDGPU_MMHUB];
e60f8db5
AX		 90 for (i = 0; i< 16; i++) {
91 reg = hub->vm_context0_cntl + i;
92 tmp = RREG32(reg);
93 tmp &= ~bits;
94 WREG32(reg, tmp);
95 }
96
97 /* GFX HUB */
98 hub = &adev->vmhub[AMDGPU_GFXHUB];
e60f8db5
AX		 99 for (i = 0; i < 16; i++) {
100 reg = hub->vm_context0_cntl + i;
101 tmp = RREG32(reg);
102 tmp &= ~bits;
103 WREG32(reg, tmp);
104 }
105 break;
106 case AMDGPU_IRQ_STATE_ENABLE:
107 /* MM HUB */
108 hub = &adev->vmhub[AMDGPU_MMHUB];
e60f8db5
AX		 109 for (i = 0; i< 16; i++) {
110 reg = hub->vm_context0_cntl + i;
111 tmp = RREG32(reg);
112 tmp |= bits;
113 WREG32(reg, tmp);
114 }
115
116 /* GFX HUB */
117 hub = &adev->vmhub[AMDGPU_GFXHUB];
e60f8db5
AX		 118 for (i = 0; i < 16; i++) {
119 reg = hub->vm_context0_cntl + i;
120 tmp = RREG32(reg);
121 tmp |= bits;
122 WREG32(reg, tmp);
123 }
124 break;
125 default:
126 break;
127 }
128
129 return 0;
130}
131
132static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
133 struct amdgpu_irq_src *source,
134 struct amdgpu_iv_entry *entry)
135{
5a9b8e8a 136 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vm_id_src];
4d6cbde3 137 uint32_t status = 0;
e60f8db5
AX		 138 u64 addr;
139
140 addr = (u64)entry->src_data[0] << 12;
141 addr |= ((u64)entry->src_data[1] & 0xf) << 44;
142
79a0c465 143 if (!amdgpu_sriov_vf(adev)) {
5a9b8e8a
CK		 144 status = RREG32(hub->vm_l2_pro_fault_status);
145 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
4d6cbde3 146 }
e60f8db5 147
4d6cbde3
FK		 148 if (printk_ratelimit()) {
149 dev_err(adev->dev,
150 "[%s] VMC page fault (src_id:%u ring:%u vm_id:%u pas_id:%u)\n",
151 entry->vm_id_src ? "mmhub" : "gfxhub",
152 entry->src_id, entry->ring_id, entry->vm_id,
153 entry->pas_id);
154 dev_err(adev->dev, " at page 0x%016llx from %d\n",
155 addr, entry->client_id);
156 if (!amdgpu_sriov_vf(adev))
157 dev_err(adev->dev,
158 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
159 status);
79a0c465 160 }
e60f8db5
AX		 161
162 return 0;
163}
164
165static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = {
166 .set = gmc_v9_0_vm_fault_interrupt_state,
167 .process = gmc_v9_0_process_interrupt,
168};
169
170static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev)
171{
172 adev->mc.vm_fault.num_types = 1;
173 adev->mc.vm_fault.funcs = &gmc_v9_0_irq_funcs;
174}
175
03f89feb
CK		 176static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vm_id)
177{
178 u32 req = 0;
179
180 /* invalidate using legacy mode on vm_id*/
181 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
182 PER_VMID_INVALIDATE_REQ, 1 << vm_id);
183 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, 0);
184 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
185 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
186 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
187 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
188 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
189 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
190 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
191
192 return req;
193}
194
e60f8db5
AX		 195/*
196 * GART
197 * VMID 0 is the physical GPU addresses as used by the kernel.
198 * VMIDs 1-15 are used for userspace clients and are handled
199 * by the amdgpu vm/hsa code.
200 */
201
202/**
203 * gmc_v9_0_gart_flush_gpu_tlb - gart tlb flush callback
204 *
205 * @adev: amdgpu_device pointer
206 * @vmid: vm instance to flush
207 *
208 * Flush the TLB for the requested page table.
209 */
210static void gmc_v9_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
211 uint32_t vmid)
212{
213 /* Use register 17 for GART */
214 const unsigned eng = 17;
215 unsigned i, j;
216
217 /* flush hdp cache */
218 nbio_v6_1_hdp_flush(adev);
219
220 spin_lock(&adev->mc.invalidate_lock);
221
222 for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
223 struct amdgpu_vmhub *hub = &adev->vmhub[i];
03f89feb 224 u32 tmp = gmc_v9_0_get_invalidate_req(vmid);
e60f8db5 225
c7a7266b 226 WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);
e60f8db5
AX		 227
228 /* Busy wait for ACK.*/
229 for (j = 0; j < 100; j++) {
c7a7266b 230 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
e60f8db5
AX		 231 tmp &= 1 << vmid;
232 if (tmp)
233 break;
234 cpu_relax();
235 }
236 if (j < 100)
237 continue;
238
239 /* Wait for ACK with a delay.*/
240 for (j = 0; j < adev->usec_timeout; j++) {
c7a7266b 241 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
e60f8db5
AX		 242 tmp &= 1 << vmid;
243 if (tmp)
244 break;
245 udelay(1);
246 }
247 if (j < adev->usec_timeout)
248 continue;
249
250 DRM_ERROR("Timeout waiting for VM flush ACK!\n");
251 }
252
253 spin_unlock(&adev->mc.invalidate_lock);
254}
255
256/**
257 * gmc_v9_0_gart_set_pte_pde - update the page tables using MMIO
258 *
259 * @adev: amdgpu_device pointer
260 * @cpu_pt_addr: cpu address of the page table
261 * @gpu_page_idx: entry in the page table to update
262 * @addr: dst addr to write into pte/pde
263 * @flags: access flags
264 *
265 * Update the page tables using the CPU.
266 */
267static int gmc_v9_0_gart_set_pte_pde(struct amdgpu_device *adev,
268 void *cpu_pt_addr,
269 uint32_t gpu_page_idx,
270 uint64_t addr,
271 uint64_t flags)
272{
273 void __iomem *ptr = (void *)cpu_pt_addr;
274 uint64_t value;
275
276 /*
277 * PTE format on VEGA 10:
278 * 63:59 reserved
279 * 58:57 mtype
280 * 56 F
281 * 55 L
282 * 54 P
283 * 53 SW
284 * 52 T
285 * 50:48 reserved
286 * 47:12 4k physical page base address
287 * 11:7 fragment
288 * 6 write
289 * 5 read
290 * 4 exe
291 * 3 Z
292 * 2 snooped
293 * 1 system
294 * 0 valid
295 *
296 * PDE format on VEGA 10:
297 * 63:59 block fragment size
298 * 58:55 reserved
299 * 54 P
300 * 53:48 reserved
301 * 47:6 physical base address of PD or PTE
302 * 5:3 reserved
303 * 2 C
304 * 1 system
305 * 0 valid
306 */
307
308 /*
309 * The following is for PTE only. GART does not have PDEs.
310 */
311 value = addr & 0x0000FFFFFFFFF000ULL;
312 value |= flags;
313 writeq(value, ptr + (gpu_page_idx * 8));
314 return 0;
315}
316
317static uint64_t gmc_v9_0_get_vm_pte_flags(struct amdgpu_device *adev,
318 uint32_t flags)
319
320{
321 uint64_t pte_flag = 0;
322
323 if (flags & AMDGPU_VM_PAGE_EXECUTABLE)
324 pte_flag |= AMDGPU_PTE_EXECUTABLE;
325 if (flags & AMDGPU_VM_PAGE_READABLE)
326 pte_flag |= AMDGPU_PTE_READABLE;
327 if (flags & AMDGPU_VM_PAGE_WRITEABLE)
328 pte_flag |= AMDGPU_PTE_WRITEABLE;
329
330 switch (flags & AMDGPU_VM_MTYPE_MASK) {
331 case AMDGPU_VM_MTYPE_DEFAULT:
332 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
333 break;
334 case AMDGPU_VM_MTYPE_NC:
335 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
336 break;
337 case AMDGPU_VM_MTYPE_WC:
338 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_WC);
339 break;
340 case AMDGPU_VM_MTYPE_CC:
341 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_CC);
342 break;
343 case AMDGPU_VM_MTYPE_UC:
344 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_UC);
345 break;
346 default:
347 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
348 break;
349 }
350
351 if (flags & AMDGPU_VM_PAGE_PRT)
352 pte_flag |= AMDGPU_PTE_PRT;
353
354 return pte_flag;
355}
356
e60f8db5
AX		 357static u64 gmc_v9_0_adjust_mc_addr(struct amdgpu_device *adev, u64 mc_addr)
358{
359 return adev->vm_manager.vram_base_offset + mc_addr - adev->mc.vram_start;
360}
361
f75e237c
CK		 362static const struct amdgpu_gart_funcs gmc_v9_0_gart_funcs = {
363 .flush_gpu_tlb = gmc_v9_0_gart_flush_gpu_tlb,
364 .set_pte_pde = gmc_v9_0_gart_set_pte_pde,
365 .get_vm_pte_flags = gmc_v9_0_get_vm_pte_flags,
e60f8db5 366 .adjust_mc_addr = gmc_v9_0_adjust_mc_addr,
03f89feb 367 .get_invalidate_req = gmc_v9_0_get_invalidate_req,
e60f8db5
AX		 368};
369
f75e237c 370static void gmc_v9_0_set_gart_funcs(struct amdgpu_device *adev)
e60f8db5 371{
f75e237c
CK		 372 if (adev->gart.gart_funcs == NULL)
373 adev->gart.gart_funcs = &gmc_v9_0_gart_funcs;
e60f8db5
AX		 374}
375
376static int gmc_v9_0_early_init(void *handle)
377{
378 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
379
380 gmc_v9_0_set_gart_funcs(adev);
e60f8db5
AX		 381 gmc_v9_0_set_irq_funcs(adev);
382
383 return 0;
384}
385
386static int gmc_v9_0_late_init(void *handle)
387{
388 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4789c463
CK		 389 unsigned vm_inv_eng[AMDGPU_MAX_VMHUBS] = { 0 };
390 unsigned i;
391
392 for(i = 0; i < adev->num_rings; ++i) {
393 struct amdgpu_ring *ring = adev->rings[i];
394 unsigned vmhub = ring->funcs->vmhub;
395
396 ring->vm_inv_eng = vm_inv_eng[vmhub]++;
397 dev_info(adev->dev, "ring %u uses VM inv eng %u on hub %u\n",
398 ring->idx, ring->vm_inv_eng, ring->funcs->vmhub);
399 }
400
401 /* Engine 17 is used for GART flushes */
402 for(i = 0; i < AMDGPU_MAX_VMHUBS; ++i)
403 BUG_ON(vm_inv_eng[i] > 17);
404
e60f8db5
AX		 405 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
406}
407
408static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
409 struct amdgpu_mc *mc)
410{
eeb2487d
ML		 411 u64 base = 0;
412 if (!amdgpu_sriov_vf(adev))
413 base = mmhub_v1_0_get_fb_location(adev);
e60f8db5
AX		 414 amdgpu_vram_location(adev, &adev->mc, base);
415 adev->mc.gtt_base_align = 0;
416 amdgpu_gtt_location(adev, mc);
417}
418
419/**
420 * gmc_v9_0_mc_init - initialize the memory controller driver params
421 *
422 * @adev: amdgpu_device pointer
423 *
424 * Look up the amount of vram, vram width, and decide how to place
425 * vram and gart within the GPU's physical address space.
426 * Returns 0 for success.
427 */
428static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
429{
430 u32 tmp;
431 int chansize, numchan;
432
433 /* hbm memory channel size */
434 chansize = 128;
435
436 tmp = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_CS_AON0_DramBaseAddress0));
437 tmp &= DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK;
438 tmp >>= DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
439 switch (tmp) {
440 case 0:
441 default:
442 numchan = 1;
443 break;
444 case 1:
445 numchan = 2;
446 break;
447 case 2:
448 numchan = 0;
449 break;
450 case 3:
451 numchan = 4;
452 break;
453 case 4:
454 numchan = 0;
455 break;
456 case 5:
457 numchan = 8;
458 break;
459 case 6:
460 numchan = 0;
461 break;
462 case 7:
463 numchan = 16;
464 break;
465 case 8:
466 numchan = 2;
467 break;
468 }
469 adev->mc.vram_width = numchan * chansize;
470
471 /* Could aper size report 0 ? */
472 adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
473 adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
474 /* size in MB on si */
475 adev->mc.mc_vram_size =
476 nbio_v6_1_get_memsize(adev) * 1024ULL * 1024ULL;
477 adev->mc.real_vram_size = adev->mc.mc_vram_size;
478 adev->mc.visible_vram_size = adev->mc.aper_size;
479
480 /* In case the PCI BAR is larger than the actual amount of vram */
481 if (adev->mc.visible_vram_size > adev->mc.real_vram_size)
482 adev->mc.visible_vram_size = adev->mc.real_vram_size;
483
484 /* unless the user had overridden it, set the gart
485 * size equal to the 1024 or vram, whichever is larger.
486 */
487 if (amdgpu_gart_size == -1)
488 adev->mc.gtt_size = max((1024ULL << 20), adev->mc.mc_vram_size);
489 else
490 adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20;
491
492 gmc_v9_0_vram_gtt_location(adev, &adev->mc);
493
494 return 0;
495}
496
497static int gmc_v9_0_gart_init(struct amdgpu_device *adev)
498{
499 int r;
500
501 if (adev->gart.robj) {
502 WARN(1, "VEGA10 PCIE GART already initialized\n");
503 return 0;
504 }
505 /* Initialize common gart structure */
506 r = amdgpu_gart_init(adev);
507 if (r)
508 return r;
509 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
510 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE(MTYPE_UC) |
511 AMDGPU_PTE_EXECUTABLE;
512 return amdgpu_gart_table_vram_alloc(adev);
513}
514
515/*
516 * vm
517 * VMID 0 is the physical GPU addresses as used by the kernel.
518 * VMIDs 1-15 are used for userspace clients and are handled
519 * by the amdgpu vm/hsa code.
520 */
521/**
522 * gmc_v9_0_vm_init - vm init callback
523 *
524 * @adev: amdgpu_device pointer
525 *
526 * Inits vega10 specific vm parameters (number of VMs, base of vram for
527 * VMIDs 1-15) (vega10).
528 * Returns 0 for success.
529 */
530static int gmc_v9_0_vm_init(struct amdgpu_device *adev)
531{
532 /*
533 * number of VMs
534 * VMID 0 is reserved for System
535 * amdgpu graphics/compute will use VMIDs 1-7
536 * amdkfd will use VMIDs 8-15
537 */
7645670d
CK		 538 adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids = AMDGPU_NUM_OF_VMIDS;
539 adev->vm_manager.id_mgr[AMDGPU_MMHUB].num_ids = AMDGPU_NUM_OF_VMIDS;
bab4fee7
JZ		 540
541 /* TODO: fix num_level for APU when updating vm size and block size */
542 if (adev->flags & AMD_IS_APU)
543 adev->vm_manager.num_level = 1;
544 else
545 adev->vm_manager.num_level = 3;
e60f8db5
AX		 546 amdgpu_vm_manager_init(adev);
547
548 /* base offset of vram pages */
549 /*XXX This value is not zero for APU*/
550 adev->vm_manager.vram_base_offset = 0;
551
552 return 0;
553}
554
555/**
556 * gmc_v9_0_vm_fini - vm fini callback
557 *
558 * @adev: amdgpu_device pointer
559 *
560 * Tear down any asic specific VM setup.
561 */
562static void gmc_v9_0_vm_fini(struct amdgpu_device *adev)
563{
564 return;
565}
566
567static int gmc_v9_0_sw_init(void *handle)
568{
569 int r;
570 int dma_bits;
571 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
572
573 spin_lock_init(&adev->mc.invalidate_lock);
574
575 if (adev->flags & AMD_IS_APU) {
576 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
bab4fee7 577 amdgpu_vm_adjust_size(adev, 64);
e60f8db5
AX		 578 } else {
579 /* XXX Don't know how to get VRAM type yet. */
580 adev->mc.vram_type = AMDGPU_VRAM_TYPE_HBM;
36b32a68
ZJ		 581 /*
582 * To fulfill 4-level page support,
583 * vm size is 256TB (48bit), maximum size of Vega10,
584 * block size 512 (9bit)
585 */
586 adev->vm_manager.vm_size = 1U << 18;
587 adev->vm_manager.block_size = 9;
bab4fee7
JZ		 588 DRM_INFO("vm size is %llu GB, block size is %u-bit\n",
589 adev->vm_manager.vm_size,
590 adev->vm_manager.block_size);
e60f8db5
AX		 591 }
592
593 /* This interrupt is VMC page fault.*/
594 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VMC, 0,
595 &adev->mc.vm_fault);
d7c434d3
FK		 596 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_UTCL2, 0,
597 &adev->mc.vm_fault);
e60f8db5
AX		 598
599 if (r)
600 return r;
601
36b32a68 602 adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
e60f8db5
AX		 603
604 /* Set the internal MC address mask
605 * This is the max address of the GPU's
606 * internal address space.
607 */
608 adev->mc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
609
610 /* set DMA mask + need_dma32 flags.
611 * PCIE - can handle 44-bits.
612 * IGP - can handle 44-bits
613 * PCI - dma32 for legacy pci gart, 44 bits on vega10
614 */
615 adev->need_dma32 = false;
616 dma_bits = adev->need_dma32 ? 32 : 44;
617 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
618 if (r) {
619 adev->need_dma32 = true;
620 dma_bits = 32;
621 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
622 }
623 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
624 if (r) {
625 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
626 printk(KERN_WARNING "amdgpu: No coherent DMA available.\n");
627 }
628
629 r = gmc_v9_0_mc_init(adev);
630 if (r)
631 return r;
632
633 /* Memory manager */
634 r = amdgpu_bo_init(adev);
635 if (r)
636 return r;
637
638 r = gmc_v9_0_gart_init(adev);
639 if (r)
640 return r;
641
642 if (!adev->vm_manager.enabled) {
643 r = gmc_v9_0_vm_init(adev);
644 if (r) {
645 dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
646 return r;
647 }
648 adev->vm_manager.enabled = true;
649 }
650 return r;
651}
652
653/**
654 * gmc_v8_0_gart_fini - vm fini callback
655 *
656 * @adev: amdgpu_device pointer
657 *
658 * Tears down the driver GART/VM setup (CIK).
659 */
660static void gmc_v9_0_gart_fini(struct amdgpu_device *adev)
661{
662 amdgpu_gart_table_vram_free(adev);
663 amdgpu_gart_fini(adev);
664}
665
666static int gmc_v9_0_sw_fini(void *handle)
667{
668 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
669
670 if (adev->vm_manager.enabled) {
671 amdgpu_vm_manager_fini(adev);
672 gmc_v9_0_vm_fini(adev);
673 adev->vm_manager.enabled = false;
674 }
675 gmc_v9_0_gart_fini(adev);
676 amdgpu_gem_force_release(adev);
677 amdgpu_bo_fini(adev);
678
679 return 0;
680}
681
682static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
683{
684 switch (adev->asic_type) {
685 case CHIP_VEGA10:
686 break;
687 default:
688 break;
689 }
690}
691
692/**
693 * gmc_v9_0_gart_enable - gart enable
694 *
695 * @adev: amdgpu_device pointer
696 */
697static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
698{
699 int r;
700 bool value;
701 u32 tmp;
702
703 amdgpu_program_register_sequence(adev,
704 golden_settings_vega10_hdp,
705 (const u32)ARRAY_SIZE(golden_settings_vega10_hdp));
706
707 if (adev->gart.robj == NULL) {
708 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
709 return -EINVAL;
710 }
711 r = amdgpu_gart_table_vram_pin(adev);
712 if (r)
713 return r;
714
715 /* After HDP is initialized, flush HDP.*/
716 nbio_v6_1_hdp_flush(adev);
717
718 r = gfxhub_v1_0_gart_enable(adev);
719 if (r)
720 return r;
721
722 r = mmhub_v1_0_gart_enable(adev);
723 if (r)
724 return r;
725
726 tmp = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MISC_CNTL));
727 tmp |= HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK;
728 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MISC_CNTL), tmp);
729
730 tmp = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_HOST_PATH_CNTL));
731 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_HOST_PATH_CNTL), tmp);
732
733
734 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
735 value = false;
736 else
737 value = true;
738
739 gfxhub_v1_0_set_fault_enable_default(adev, value);
740 mmhub_v1_0_set_fault_enable_default(adev, value);
741
742 gmc_v9_0_gart_flush_gpu_tlb(adev, 0);
743
744 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
745 (unsigned)(adev->mc.gtt_size >> 20),
746 (unsigned long long)adev->gart.table_addr);
747 adev->gart.ready = true;
748 return 0;
749}
750
751static int gmc_v9_0_hw_init(void *handle)
752{
753 int r;
754 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
755
756 /* The sequence of these two function calls matters.*/
757 gmc_v9_0_init_golden_registers(adev);
758
759 r = gmc_v9_0_gart_enable(adev);
760
761 return r;
762}
763
764/**
765 * gmc_v9_0_gart_disable - gart disable
766 *
767 * @adev: amdgpu_device pointer
768 *
769 * This disables all VM page table.
770 */
771static void gmc_v9_0_gart_disable(struct amdgpu_device *adev)
772{
773 gfxhub_v1_0_gart_disable(adev);
774 mmhub_v1_0_gart_disable(adev);
775 amdgpu_gart_table_vram_unpin(adev);
776}
777
778static int gmc_v9_0_hw_fini(void *handle)
779{
780 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
781
782 amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
783 gmc_v9_0_gart_disable(adev);
784
785 return 0;
786}
787
788static int gmc_v9_0_suspend(void *handle)
789{
790 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
791
792 if (adev->vm_manager.enabled) {
793 gmc_v9_0_vm_fini(adev);
794 adev->vm_manager.enabled = false;
795 }
796 gmc_v9_0_hw_fini(adev);
797
798 return 0;
799}
800
801static int gmc_v9_0_resume(void *handle)
802{
803 int r;
804 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
805
806 r = gmc_v9_0_hw_init(adev);
807 if (r)
808 return r;
809
810 if (!adev->vm_manager.enabled) {
811 r = gmc_v9_0_vm_init(adev);
812 if (r) {
813 dev_err(adev->dev,
814 "vm manager initialization failed (%d).\n", r);
815 return r;
816 }
817 adev->vm_manager.enabled = true;
818 }
819
820 return r;
821}
822
823static bool gmc_v9_0_is_idle(void *handle)
824{
825 /* MC is always ready in GMC v9.*/
826 return true;
827}
828
829static int gmc_v9_0_wait_for_idle(void *handle)
830{
831 /* There is no need to wait for MC idle in GMC v9.*/
832 return 0;
833}
834
835static int gmc_v9_0_soft_reset(void *handle)
836{
837 /* XXX for emulation.*/
838 return 0;
839}
840
841static int gmc_v9_0_set_clockgating_state(void *handle,
842 enum amd_clockgating_state state)
843{
844 return 0;
845}
846
847static int gmc_v9_0_set_powergating_state(void *handle,
848 enum amd_powergating_state state)
849{
850 return 0;
851}
852
853const struct amd_ip_funcs gmc_v9_0_ip_funcs = {
854 .name = "gmc_v9_0",
855 .early_init = gmc_v9_0_early_init,
856 .late_init = gmc_v9_0_late_init,
857 .sw_init = gmc_v9_0_sw_init,
858 .sw_fini = gmc_v9_0_sw_fini,
859 .hw_init = gmc_v9_0_hw_init,
860 .hw_fini = gmc_v9_0_hw_fini,
861 .suspend = gmc_v9_0_suspend,
862 .resume = gmc_v9_0_resume,
863 .is_idle = gmc_v9_0_is_idle,
864 .wait_for_idle = gmc_v9_0_wait_for_idle,
865 .soft_reset = gmc_v9_0_soft_reset,
866 .set_clockgating_state = gmc_v9_0_set_clockgating_state,
867 .set_powergating_state = gmc_v9_0_set_powergating_state,
868};
869
870const struct amdgpu_ip_block_version gmc_v9_0_ip_block =
871{
872 .type = AMD_IP_BLOCK_TYPE_GMC,
873 .major = 9,
874 .minor = 0,
875 .rev = 0,
876 .funcs = &gmc_v9_0_ip_funcs,
877};
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