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drm/amdgpu/vcn1: add emit_reg_write_reg_wait ring callback
[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / amd / amdgpu / gmc_v9_0.c
CommitLineData
e60f8db5
AX		 1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
fd5fd480 24#include <drm/drm_cache.h>
e60f8db5
AX		 25#include "amdgpu.h"
26#include "gmc_v9_0.h"
8d6a5230 27#include "amdgpu_atomfirmware.h"
e60f8db5 28
75199b8c
FX		 29#include "hdp/hdp_4_0_offset.h"
30#include "hdp/hdp_4_0_sh_mask.h"
cde5c34f 31#include "gc/gc_9_0_sh_mask.h"
135d4b10
FX		 32#include "dce/dce_12_0_offset.h"
33#include "dce/dce_12_0_sh_mask.h"
fb960bd2 34#include "vega10_enum.h"
65417d9f 35#include "mmhub/mmhub_1_0_offset.h"
6ce68225 36#include "athub/athub_1_0_offset.h"
250b4228 37#include "oss/osssys_4_0_offset.h"
e60f8db5 38
946a4d5b 39#include "soc15.h"
e60f8db5 40#include "soc15_common.h"
90c7a935 41#include "umc/umc_6_0_sh_mask.h"
e60f8db5 42
e60f8db5
AX		 43#include "gfxhub_v1_0.h"
44#include "mmhub_v1_0.h"
45
46#define mmDF_CS_AON0_DramBaseAddress0 0x0044
47#define mmDF_CS_AON0_DramBaseAddress0_BASE_IDX 0
48//DF_CS_AON0_DramBaseAddress0
49#define DF_CS_AON0_DramBaseAddress0__AddrRngVal__SHIFT 0x0
50#define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT 0x1
51#define DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT 0x4
52#define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT 0x8
53#define DF_CS_AON0_DramBaseAddress0__DramBaseAddr__SHIFT 0xc
54#define DF_CS_AON0_DramBaseAddress0__AddrRngVal_MASK 0x00000001L
55#define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK 0x00000002L
56#define DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK 0x000000F0L
57#define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK 0x00000700L
58#define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK 0xFFFFF000L
59
60/* XXX Move this macro to VEGA10 header file, which is like vid.h for VI.*/
61#define AMDGPU_NUM_OF_VMIDS 8
62
63static const u32 golden_settings_vega10_hdp[] =
64{
65 0xf64, 0x0fffffff, 0x00000000,
66 0xf65, 0x0fffffff, 0x00000000,
67 0xf66, 0x0fffffff, 0x00000000,
68 0xf67, 0x0fffffff, 0x00000000,
69 0xf68, 0x0fffffff, 0x00000000,
70 0xf6a, 0x0fffffff, 0x00000000,
71 0xf6b, 0x0fffffff, 0x00000000,
72 0xf6c, 0x0fffffff, 0x00000000,
73 0xf6d, 0x0fffffff, 0x00000000,
74 0xf6e, 0x0fffffff, 0x00000000,
75};
76
946a4d5b 77static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] =
5c583018 78{
946a4d5b
SL		 79 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa),
80 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565)
5c583018
EQ		 81};
82
946a4d5b 83static const struct soc15_reg_golden golden_settings_athub_1_0_0[] =
5c583018 84{
946a4d5b
SL		 85 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800),
86 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008)
5c583018
EQ		 87};
88
02bab923
DP		 89/* Ecc related register addresses, (BASE + reg offset) */
90/* Universal Memory Controller caps (may be fused). */
91/* UMCCH:UmcLocalCap */
92#define UMCLOCALCAPS_ADDR0 (0x00014306 + 0x00000000)
93#define UMCLOCALCAPS_ADDR1 (0x00014306 + 0x00000800)
94#define UMCLOCALCAPS_ADDR2 (0x00014306 + 0x00001000)
95#define UMCLOCALCAPS_ADDR3 (0x00014306 + 0x00001800)
96#define UMCLOCALCAPS_ADDR4 (0x00054306 + 0x00000000)
97#define UMCLOCALCAPS_ADDR5 (0x00054306 + 0x00000800)
98#define UMCLOCALCAPS_ADDR6 (0x00054306 + 0x00001000)
99#define UMCLOCALCAPS_ADDR7 (0x00054306 + 0x00001800)
100#define UMCLOCALCAPS_ADDR8 (0x00094306 + 0x00000000)
101#define UMCLOCALCAPS_ADDR9 (0x00094306 + 0x00000800)
102#define UMCLOCALCAPS_ADDR10 (0x00094306 + 0x00001000)
103#define UMCLOCALCAPS_ADDR11 (0x00094306 + 0x00001800)
104#define UMCLOCALCAPS_ADDR12 (0x000d4306 + 0x00000000)
105#define UMCLOCALCAPS_ADDR13 (0x000d4306 + 0x00000800)
106#define UMCLOCALCAPS_ADDR14 (0x000d4306 + 0x00001000)
107#define UMCLOCALCAPS_ADDR15 (0x000d4306 + 0x00001800)
108
109/* Universal Memory Controller Channel config. */
110/* UMCCH:UMC_CONFIG */
111#define UMCCH_UMC_CONFIG_ADDR0 (0x00014040 + 0x00000000)
112#define UMCCH_UMC_CONFIG_ADDR1 (0x00014040 + 0x00000800)
113#define UMCCH_UMC_CONFIG_ADDR2 (0x00014040 + 0x00001000)
114#define UMCCH_UMC_CONFIG_ADDR3 (0x00014040 + 0x00001800)
115#define UMCCH_UMC_CONFIG_ADDR4 (0x00054040 + 0x00000000)
116#define UMCCH_UMC_CONFIG_ADDR5 (0x00054040 + 0x00000800)
117#define UMCCH_UMC_CONFIG_ADDR6 (0x00054040 + 0x00001000)
118#define UMCCH_UMC_CONFIG_ADDR7 (0x00054040 + 0x00001800)
119#define UMCCH_UMC_CONFIG_ADDR8 (0x00094040 + 0x00000000)
120#define UMCCH_UMC_CONFIG_ADDR9 (0x00094040 + 0x00000800)
121#define UMCCH_UMC_CONFIG_ADDR10 (0x00094040 + 0x00001000)
122#define UMCCH_UMC_CONFIG_ADDR11 (0x00094040 + 0x00001800)
123#define UMCCH_UMC_CONFIG_ADDR12 (0x000d4040 + 0x00000000)
124#define UMCCH_UMC_CONFIG_ADDR13 (0x000d4040 + 0x00000800)
125#define UMCCH_UMC_CONFIG_ADDR14 (0x000d4040 + 0x00001000)
126#define UMCCH_UMC_CONFIG_ADDR15 (0x000d4040 + 0x00001800)
127
128/* Universal Memory Controller Channel Ecc config. */
129/* UMCCH:EccCtrl */
130#define UMCCH_ECCCTRL_ADDR0 (0x00014053 + 0x00000000)
131#define UMCCH_ECCCTRL_ADDR1 (0x00014053 + 0x00000800)
132#define UMCCH_ECCCTRL_ADDR2 (0x00014053 + 0x00001000)
133#define UMCCH_ECCCTRL_ADDR3 (0x00014053 + 0x00001800)
134#define UMCCH_ECCCTRL_ADDR4 (0x00054053 + 0x00000000)
135#define UMCCH_ECCCTRL_ADDR5 (0x00054053 + 0x00000800)
136#define UMCCH_ECCCTRL_ADDR6 (0x00054053 + 0x00001000)
137#define UMCCH_ECCCTRL_ADDR7 (0x00054053 + 0x00001800)
138#define UMCCH_ECCCTRL_ADDR8 (0x00094053 + 0x00000000)
139#define UMCCH_ECCCTRL_ADDR9 (0x00094053 + 0x00000800)
140#define UMCCH_ECCCTRL_ADDR10 (0x00094053 + 0x00001000)
141#define UMCCH_ECCCTRL_ADDR11 (0x00094053 + 0x00001800)
142#define UMCCH_ECCCTRL_ADDR12 (0x000d4053 + 0x00000000)
143#define UMCCH_ECCCTRL_ADDR13 (0x000d4053 + 0x00000800)
144#define UMCCH_ECCCTRL_ADDR14 (0x000d4053 + 0x00001000)
145#define UMCCH_ECCCTRL_ADDR15 (0x000d4053 + 0x00001800)
146
147static const uint32_t ecc_umclocalcap_addrs[] = {
148 UMCLOCALCAPS_ADDR0,
149 UMCLOCALCAPS_ADDR1,
150 UMCLOCALCAPS_ADDR2,
151 UMCLOCALCAPS_ADDR3,
152 UMCLOCALCAPS_ADDR4,
153 UMCLOCALCAPS_ADDR5,
154 UMCLOCALCAPS_ADDR6,
155 UMCLOCALCAPS_ADDR7,
156 UMCLOCALCAPS_ADDR8,
157 UMCLOCALCAPS_ADDR9,
158 UMCLOCALCAPS_ADDR10,
159 UMCLOCALCAPS_ADDR11,
160 UMCLOCALCAPS_ADDR12,
161 UMCLOCALCAPS_ADDR13,
162 UMCLOCALCAPS_ADDR14,
163 UMCLOCALCAPS_ADDR15,
164};
165
166static const uint32_t ecc_umcch_umc_config_addrs[] = {
167 UMCCH_UMC_CONFIG_ADDR0,
168 UMCCH_UMC_CONFIG_ADDR1,
169 UMCCH_UMC_CONFIG_ADDR2,
170 UMCCH_UMC_CONFIG_ADDR3,
171 UMCCH_UMC_CONFIG_ADDR4,
172 UMCCH_UMC_CONFIG_ADDR5,
173 UMCCH_UMC_CONFIG_ADDR6,
174 UMCCH_UMC_CONFIG_ADDR7,
175 UMCCH_UMC_CONFIG_ADDR8,
176 UMCCH_UMC_CONFIG_ADDR9,
177 UMCCH_UMC_CONFIG_ADDR10,
178 UMCCH_UMC_CONFIG_ADDR11,
179 UMCCH_UMC_CONFIG_ADDR12,
180 UMCCH_UMC_CONFIG_ADDR13,
181 UMCCH_UMC_CONFIG_ADDR14,
182 UMCCH_UMC_CONFIG_ADDR15,
183};
184
185static const uint32_t ecc_umcch_eccctrl_addrs[] = {
186 UMCCH_ECCCTRL_ADDR0,
187 UMCCH_ECCCTRL_ADDR1,
188 UMCCH_ECCCTRL_ADDR2,
189 UMCCH_ECCCTRL_ADDR3,
190 UMCCH_ECCCTRL_ADDR4,
191 UMCCH_ECCCTRL_ADDR5,
192 UMCCH_ECCCTRL_ADDR6,
193 UMCCH_ECCCTRL_ADDR7,
194 UMCCH_ECCCTRL_ADDR8,
195 UMCCH_ECCCTRL_ADDR9,
196 UMCCH_ECCCTRL_ADDR10,
197 UMCCH_ECCCTRL_ADDR11,
198 UMCCH_ECCCTRL_ADDR12,
199 UMCCH_ECCCTRL_ADDR13,
200 UMCCH_ECCCTRL_ADDR14,
201 UMCCH_ECCCTRL_ADDR15,
202};
203
e60f8db5
AX		 204static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
205 struct amdgpu_irq_src *src,
206 unsigned type,
207 enum amdgpu_interrupt_state state)
208{
209 struct amdgpu_vmhub *hub;
ae6d1416 210 u32 tmp, reg, bits, i, j;
e60f8db5 211
11250164
CK		 212 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
213 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
214 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
215 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
216 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
217 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
218 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
219
e60f8db5
AX		 220 switch (state) {
221 case AMDGPU_IRQ_STATE_DISABLE:
ae6d1416
TSD		 222 for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) {
223 hub = &adev->vmhub[j];
224 for (i = 0; i < 16; i++) {
225 reg = hub->vm_context0_cntl + i;
226 tmp = RREG32(reg);
227 tmp &= ~bits;
228 WREG32(reg, tmp);
229 }
e60f8db5
AX		 230 }
231 break;
232 case AMDGPU_IRQ_STATE_ENABLE:
ae6d1416
TSD		 233 for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) {
234 hub = &adev->vmhub[j];
235 for (i = 0; i < 16; i++) {
236 reg = hub->vm_context0_cntl + i;
237 tmp = RREG32(reg);
238 tmp |= bits;
239 WREG32(reg, tmp);
240 }
e60f8db5 241 }
e60f8db5
AX		 242 default:
243 break;
244 }
245
246 return 0;
247}
248
249static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
250 struct amdgpu_irq_src *source,
251 struct amdgpu_iv_entry *entry)
252{
c4f46f22 253 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src];
4d6cbde3 254 uint32_t status = 0;
e60f8db5
AX		 255 u64 addr;
256
257 addr = (u64)entry->src_data[0] << 12;
258 addr |= ((u64)entry->src_data[1] & 0xf) << 44;
259
79a0c465 260 if (!amdgpu_sriov_vf(adev)) {
5a9b8e8a
CK		 261 status = RREG32(hub->vm_l2_pro_fault_status);
262 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
4d6cbde3 263 }
e60f8db5 264
4d6cbde3
FK		 265 if (printk_ratelimit()) {
266 dev_err(adev->dev,
3816e42f 267 "[%s] VMC page fault (src_id:%u ring:%u vmid:%u pasid:%u)\n",
c4f46f22
CK		 268 entry->vmid_src ? "mmhub" : "gfxhub",
269 entry->src_id, entry->ring_id, entry->vmid,
3816e42f 270 entry->pasid);
4d6cbde3
FK		 271 dev_err(adev->dev, " at page 0x%016llx from %d\n",
272 addr, entry->client_id);
273 if (!amdgpu_sriov_vf(adev))
274 dev_err(adev->dev,
275 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
276 status);
79a0c465 277 }
e60f8db5
AX		 278
279 return 0;
280}
281
282static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = {
283 .set = gmc_v9_0_vm_fault_interrupt_state,
284 .process = gmc_v9_0_process_interrupt,
285};
286
287static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev)
288{
770d13b1
CK		 289 adev->gmc.vm_fault.num_types = 1;
290 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs;
e60f8db5
AX		 291}
292
c4f46f22 293static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid)
03f89feb
CK		 294{
295 u32 req = 0;
296
c4f46f22 297 /* invalidate using legacy mode on vmid*/
03f89feb 298 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
c4f46f22 299 PER_VMID_INVALIDATE_REQ, 1 << vmid);
03f89feb
CK		 300 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, 0);
301 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
302 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
303 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
304 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
305 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
306 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
307 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
308
309 return req;
310}
311
e60f8db5
AX		 312/*
313 * GART
314 * VMID 0 is the physical GPU addresses as used by the kernel.
315 * VMIDs 1-15 are used for userspace clients and are handled
316 * by the amdgpu vm/hsa code.
317 */
318
319/**
132f34e4 320 * gmc_v9_0_flush_gpu_tlb - gart tlb flush callback
e60f8db5
AX		 321 *
322 * @adev: amdgpu_device pointer
323 * @vmid: vm instance to flush
324 *
325 * Flush the TLB for the requested page table.
326 */
132f34e4 327static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev,
e60f8db5
AX		 328 uint32_t vmid)
329{
330 /* Use register 17 for GART */
331 const unsigned eng = 17;
332 unsigned i, j;
333
770d13b1 334 spin_lock(&adev->gmc.invalidate_lock);
e60f8db5
AX		 335
336 for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
337 struct amdgpu_vmhub *hub = &adev->vmhub[i];
03f89feb 338 u32 tmp = gmc_v9_0_get_invalidate_req(vmid);
e60f8db5 339
c7a7266b 340 WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);
e60f8db5
AX		 341
342 /* Busy wait for ACK.*/
343 for (j = 0; j < 100; j++) {
c7a7266b 344 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
e60f8db5
AX		 345 tmp &= 1 << vmid;
346 if (tmp)
347 break;
348 cpu_relax();
349 }
350 if (j < 100)
351 continue;
352
353 /* Wait for ACK with a delay.*/
354 for (j = 0; j < adev->usec_timeout; j++) {
c7a7266b 355 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
e60f8db5
AX		 356 tmp &= 1 << vmid;
357 if (tmp)
358 break;
359 udelay(1);
360 }
361 if (j < adev->usec_timeout)
362 continue;
363
364 DRM_ERROR("Timeout waiting for VM flush ACK!\n");
365 }
366
770d13b1 367 spin_unlock(&adev->gmc.invalidate_lock);
e60f8db5
AX		 368}
369
9096d6e5 370static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
c633c00b 371 unsigned vmid, uint64_t pd_addr)
9096d6e5 372{
250b4228
CK		 373 struct amdgpu_device *adev = ring->adev;
374 struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub];
9096d6e5
CK		 375 uint32_t req = gmc_v9_0_get_invalidate_req(vmid);
376 uint64_t flags = AMDGPU_PTE_VALID;
377 unsigned eng = ring->vm_inv_eng;
378
c633c00b 379 amdgpu_gmc_get_vm_pde(adev, -1, &pd_addr, &flags);
9096d6e5
CK		 380 pd_addr |= flags;
381
382 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid),
383 lower_32_bits(pd_addr));
384
385 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid),
386 upper_32_bits(pd_addr));
387
388 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_req + eng, req);
389
f732b6b3
CK		 390 /* wait for the invalidate to complete */
391 amdgpu_ring_emit_reg_wait(ring, hub->vm_inv_eng0_ack + eng,
392 1 << vmid, 1 << vmid);
393
9096d6e5
CK		 394 return pd_addr;
395}
396
c633c00b
CK		 397static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
398 unsigned pasid)
399{
400 struct amdgpu_device *adev = ring->adev;
401 uint32_t reg;
402
403 if (ring->funcs->vmhub == AMDGPU_GFXHUB)
404 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
405 else
406 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
407
408 amdgpu_ring_emit_wreg(ring, reg, pasid);
409}
410
e60f8db5 411/**
132f34e4 412 * gmc_v9_0_set_pte_pde - update the page tables using MMIO
e60f8db5
AX		 413 *
414 * @adev: amdgpu_device pointer
415 * @cpu_pt_addr: cpu address of the page table
416 * @gpu_page_idx: entry in the page table to update
417 * @addr: dst addr to write into pte/pde
418 * @flags: access flags
419 *
420 * Update the page tables using the CPU.
421 */
132f34e4
CK		 422static int gmc_v9_0_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr,
423 uint32_t gpu_page_idx, uint64_t addr,
424 uint64_t flags)
e60f8db5
AX		 425{
426 void __iomem *ptr = (void *)cpu_pt_addr;
427 uint64_t value;
428
429 /*
430 * PTE format on VEGA 10:
431 * 63:59 reserved
432 * 58:57 mtype
433 * 56 F
434 * 55 L
435 * 54 P
436 * 53 SW
437 * 52 T
438 * 50:48 reserved
439 * 47:12 4k physical page base address
440 * 11:7 fragment
441 * 6 write
442 * 5 read
443 * 4 exe
444 * 3 Z
445 * 2 snooped
446 * 1 system
447 * 0 valid
448 *
449 * PDE format on VEGA 10:
450 * 63:59 block fragment size
451 * 58:55 reserved
452 * 54 P
453 * 53:48 reserved
454 * 47:6 physical base address of PD or PTE
455 * 5:3 reserved
456 * 2 C
457 * 1 system
458 * 0 valid
459 */
460
461 /*
462 * The following is for PTE only. GART does not have PDEs.
463 */
464 value = addr & 0x0000FFFFFFFFF000ULL;
465 value |= flags;
466 writeq(value, ptr + (gpu_page_idx * 8));
467 return 0;
468}
469
470static uint64_t gmc_v9_0_get_vm_pte_flags(struct amdgpu_device *adev,
471 uint32_t flags)
472
473{
474 uint64_t pte_flag = 0;
475
476 if (flags & AMDGPU_VM_PAGE_EXECUTABLE)
477 pte_flag |= AMDGPU_PTE_EXECUTABLE;
478 if (flags & AMDGPU_VM_PAGE_READABLE)
479 pte_flag |= AMDGPU_PTE_READABLE;
480 if (flags & AMDGPU_VM_PAGE_WRITEABLE)
481 pte_flag |= AMDGPU_PTE_WRITEABLE;
482
483 switch (flags & AMDGPU_VM_MTYPE_MASK) {
484 case AMDGPU_VM_MTYPE_DEFAULT:
485 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
486 break;
487 case AMDGPU_VM_MTYPE_NC:
488 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
489 break;
490 case AMDGPU_VM_MTYPE_WC:
491 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_WC);
492 break;
493 case AMDGPU_VM_MTYPE_CC:
494 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_CC);
495 break;
496 case AMDGPU_VM_MTYPE_UC:
497 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_UC);
498 break;
499 default:
500 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
501 break;
502 }
503
504 if (flags & AMDGPU_VM_PAGE_PRT)
505 pte_flag |= AMDGPU_PTE_PRT;
506
507 return pte_flag;
508}
509
3de676d8
CK		 510static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
511 uint64_t *addr, uint64_t *flags)
e60f8db5 512{
3de676d8
CK		 513 if (!(*flags & AMDGPU_PDE_PTE))
514 *addr = adev->vm_manager.vram_base_offset + *addr -
770d13b1 515 adev->gmc.vram_start;
3de676d8 516 BUG_ON(*addr & 0xFFFF00000000003FULL);
6a42fd6f 517
770d13b1 518 if (!adev->gmc.translate_further)
6a42fd6f
CK		 519 return;
520
521 if (level == AMDGPU_VM_PDB1) {
522 /* Set the block fragment size */
523 if (!(*flags & AMDGPU_PDE_PTE))
524 *flags |= AMDGPU_PDE_BFS(0x9);
525
526 } else if (level == AMDGPU_VM_PDB0) {
527 if (*flags & AMDGPU_PDE_PTE)
528 *flags &= ~AMDGPU_PDE_PTE;
529 else
530 *flags |= AMDGPU_PTE_TF;
531 }
e60f8db5
AX		 532}
533
132f34e4
CK		 534static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = {
535 .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb,
9096d6e5 536 .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb,
c633c00b 537 .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping,
132f34e4 538 .set_pte_pde = gmc_v9_0_set_pte_pde,
b1166325
CK		 539 .get_vm_pte_flags = gmc_v9_0_get_vm_pte_flags,
540 .get_vm_pde = gmc_v9_0_get_vm_pde
e60f8db5
AX		 541};
542
132f34e4 543static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev)
e60f8db5 544{
132f34e4
CK		 545 if (adev->gmc.gmc_funcs == NULL)
546 adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs;
e60f8db5
AX		 547}
548
549static int gmc_v9_0_early_init(void *handle)
550{
551 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
552
132f34e4 553 gmc_v9_0_set_gmc_funcs(adev);
e60f8db5
AX		 554 gmc_v9_0_set_irq_funcs(adev);
555
770d13b1
CK		 556 adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
557 adev->gmc.shared_aperture_end =
558 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
559 adev->gmc.private_aperture_start =
560 adev->gmc.shared_aperture_end + 1;
561 adev->gmc.private_aperture_end =
562 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
a7ea6548 563
e60f8db5
AX		 564 return 0;
565}
566
02bab923
DP		 567static int gmc_v9_0_ecc_available(struct amdgpu_device *adev)
568{
569 uint32_t reg_val;
570 uint32_t reg_addr;
571 uint32_t field_val;
572 size_t i;
573 uint32_t fv2;
574 size_t lost_sheep;
575
576 DRM_DEBUG("ecc: gmc_v9_0_ecc_available()\n");
577
578 lost_sheep = 0;
579 for (i = 0; i < ARRAY_SIZE(ecc_umclocalcap_addrs); ++i) {
580 reg_addr = ecc_umclocalcap_addrs[i];
581 DRM_DEBUG("ecc: "
582 "UMCCH_UmcLocalCap[%zu]: reg_addr: 0x%08x\n",
583 i, reg_addr);
584 reg_val = RREG32(reg_addr);
585 field_val = REG_GET_FIELD(reg_val, UMCCH0_0_UmcLocalCap,
586 EccDis);
587 DRM_DEBUG("ecc: "
588 "reg_val: 0x%08x, "
589 "EccDis: 0x%08x, ",
590 reg_val, field_val);
591 if (field_val) {
592 DRM_ERROR("ecc: UmcLocalCap:EccDis is set.\n");
593 ++lost_sheep;
594 }
595 }
596
597 for (i = 0; i < ARRAY_SIZE(ecc_umcch_umc_config_addrs); ++i) {
598 reg_addr = ecc_umcch_umc_config_addrs[i];
599 DRM_DEBUG("ecc: "
600 "UMCCH0_0_UMC_CONFIG[%zu]: reg_addr: 0x%08x",
601 i, reg_addr);
602 reg_val = RREG32(reg_addr);
603 field_val = REG_GET_FIELD(reg_val, UMCCH0_0_UMC_CONFIG,
604 DramReady);
605 DRM_DEBUG("ecc: "
606 "reg_val: 0x%08x, "
607 "DramReady: 0x%08x\n",
608 reg_val, field_val);
609
610 if (!field_val) {
611 DRM_ERROR("ecc: UMC_CONFIG:DramReady is not set.\n");
612 ++lost_sheep;
613 }
614 }
615
616 for (i = 0; i < ARRAY_SIZE(ecc_umcch_eccctrl_addrs); ++i) {
617 reg_addr = ecc_umcch_eccctrl_addrs[i];
618 DRM_DEBUG("ecc: "
619 "UMCCH_EccCtrl[%zu]: reg_addr: 0x%08x, ",
620 i, reg_addr);
621 reg_val = RREG32(reg_addr);
622 field_val = REG_GET_FIELD(reg_val, UMCCH0_0_EccCtrl,
623 WrEccEn);
624 fv2 = REG_GET_FIELD(reg_val, UMCCH0_0_EccCtrl,
625 RdEccEn);
626 DRM_DEBUG("ecc: "
627 "reg_val: 0x%08x, "
628 "WrEccEn: 0x%08x, "
629 "RdEccEn: 0x%08x\n",
630 reg_val, field_val, fv2);
631
632 if (!field_val) {
5a16008f 633 DRM_DEBUG("ecc: WrEccEn is not set\n");
02bab923
DP		 634 ++lost_sheep;
635 }
636 if (!fv2) {
5a16008f 637 DRM_DEBUG("ecc: RdEccEn is not set\n");
02bab923
DP		 638 ++lost_sheep;
639 }
640 }
641
642 DRM_DEBUG("ecc: lost_sheep: %zu\n", lost_sheep);
643 return lost_sheep == 0;
644}
645
e60f8db5
AX		 646static int gmc_v9_0_late_init(void *handle)
647{
648 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
c5066129 649 /*
650 * The latest engine allocation on gfx9 is:
651 * Engine 0, 1: idle
652 * Engine 2, 3: firmware
653 * Engine 4~13: amdgpu ring, subject to change when ring number changes
654 * Engine 14~15: idle
655 * Engine 16: kfd tlb invalidation
656 * Engine 17: Gart flushes
657 */
658 unsigned vm_inv_eng[AMDGPU_MAX_VMHUBS] = { 4, 4 };
4789c463 659 unsigned i;
02bab923 660 int r;
4789c463
CK		 661
662 for(i = 0; i < adev->num_rings; ++i) {
663 struct amdgpu_ring *ring = adev->rings[i];
664 unsigned vmhub = ring->funcs->vmhub;
665
666 ring->vm_inv_eng = vm_inv_eng[vmhub]++;
775f55f1
TSD		 667 dev_info(adev->dev, "ring %u(%s) uses VM inv eng %u on hub %u\n",
668 ring->idx, ring->name, ring->vm_inv_eng,
669 ring->funcs->vmhub);
4789c463
CK		 670 }
671
c5066129 672 /* Engine 16 is used for KFD and 17 for GART flushes */
4789c463 673 for(i = 0; i < AMDGPU_MAX_VMHUBS; ++i)
c5066129 674 BUG_ON(vm_inv_eng[i] > 16);
4789c463 675
7b6cbae2 676 if (adev->asic_type == CHIP_VEGA10 && !amdgpu_sriov_vf(adev)) {
5ba4fa35
AD		 677 r = gmc_v9_0_ecc_available(adev);
678 if (r == 1) {
679 DRM_INFO("ECC is active.\n");
680 } else if (r == 0) {
681 DRM_INFO("ECC is not present.\n");
682 } else {
683 DRM_ERROR("gmc_v9_0_ecc_available() failed. r: %d\n", r);
684 return r;
685 }
02bab923
DP		 686 }
687
770d13b1 688 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
e60f8db5
AX		 689}
690
691static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
770d13b1 692 struct amdgpu_gmc *mc)
e60f8db5 693{
eeb2487d
ML		 694 u64 base = 0;
695 if (!amdgpu_sriov_vf(adev))
696 base = mmhub_v1_0_get_fb_location(adev);
770d13b1 697 amdgpu_device_vram_location(adev, &adev->gmc, base);
2543e28a 698 amdgpu_device_gart_location(adev, mc);
bc099ee9
CZ		 699 /* base offset of vram pages */
700 if (adev->flags & AMD_IS_APU)
701 adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev);
702 else
703 adev->vm_manager.vram_base_offset = 0;
e60f8db5
AX		 704}
705
706/**
707 * gmc_v9_0_mc_init - initialize the memory controller driver params
708 *
709 * @adev: amdgpu_device pointer
710 *
711 * Look up the amount of vram, vram width, and decide how to place
712 * vram and gart within the GPU's physical address space.
713 * Returns 0 for success.
714 */
715static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
716{
e60f8db5 717 int chansize, numchan;
d6895ad3 718 int r;
e60f8db5 719
3d918c0e
SL		 720 if (amdgpu_emu_mode != 1)
721 adev->gmc.vram_width = amdgpu_atomfirmware_get_vram_width(adev);
770d13b1 722 if (!adev->gmc.vram_width) {
8d6a5230 723 /* hbm memory channel size */
585b7f16
TSD		 724 if (adev->flags & AMD_IS_APU)
725 chansize = 64;
726 else
727 chansize = 128;
8d6a5230 728
070706c0 729 numchan = adev->df_funcs->get_hbm_channel_number(adev);
770d13b1 730 adev->gmc.vram_width = numchan * chansize;
e60f8db5 731 }
e60f8db5 732
e60f8db5 733 /* size in MB on si */
770d13b1 734 adev->gmc.mc_vram_size =
bf383fb6 735 adev->nbio_funcs->get_memsize(adev) * 1024ULL * 1024ULL;
770d13b1 736 adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
d6895ad3
CK		 737
738 if (!(adev->flags & AMD_IS_APU)) {
739 r = amdgpu_device_resize_fb_bar(adev);
740 if (r)
741 return r;
742 }
770d13b1
CK		 743 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
744 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
e60f8db5 745
156a81be
CZ		 746#ifdef CONFIG_X86_64
747 if (adev->flags & AMD_IS_APU) {
748 adev->gmc.aper_base = gfxhub_v1_0_get_mc_fb_offset(adev);
749 adev->gmc.aper_size = adev->gmc.real_vram_size;
750 }
751#endif
e60f8db5 752 /* In case the PCI BAR is larger than the actual amount of vram */
770d13b1
CK		 753 adev->gmc.visible_vram_size = adev->gmc.aper_size;
754 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
755 adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
e60f8db5 756
c3db7b5a
AD		 757 /* set the gart size */
758 if (amdgpu_gart_size == -1) {
759 switch (adev->asic_type) {
760 case CHIP_VEGA10: /* all engines support GPUVM */
273a14cd 761 case CHIP_VEGA12: /* all engines support GPUVM */
c3db7b5a 762 default:
fe19b862 763 adev->gmc.gart_size = 512ULL << 20;
c3db7b5a
AD		 764 break;
765 case CHIP_RAVEN: /* DCE SG support */
770d13b1 766 adev->gmc.gart_size = 1024ULL << 20;
c3db7b5a
AD		 767 break;
768 }
769 } else {
770d13b1 770 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
c3db7b5a
AD		 771 }
772
770d13b1 773 gmc_v9_0_vram_gtt_location(adev, &adev->gmc);
e60f8db5
AX		 774
775 return 0;
776}
777
778static int gmc_v9_0_gart_init(struct amdgpu_device *adev)
779{
780 int r;
781
782 if (adev->gart.robj) {
783 WARN(1, "VEGA10 PCIE GART already initialized\n");
784 return 0;
785 }
786 /* Initialize common gart structure */
787 r = amdgpu_gart_init(adev);
788 if (r)
789 return r;
790 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
791 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE(MTYPE_UC) |
792 AMDGPU_PTE_EXECUTABLE;
793 return amdgpu_gart_table_vram_alloc(adev);
794}
795
e60f8db5
AX		 796static int gmc_v9_0_sw_init(void *handle)
797{
798 int r;
799 int dma_bits;
800 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
801
0c8c0847 802 gfxhub_v1_0_init(adev);
77f6c763 803 mmhub_v1_0_init(adev);
0c8c0847 804
770d13b1 805 spin_lock_init(&adev->gmc.invalidate_lock);
e60f8db5 806
1e09b053 807 adev->gmc.vram_type = amdgpu_atomfirmware_get_vram_type(adev);
fd66560b
HZ		 808 switch (adev->asic_type) {
809 case CHIP_RAVEN:
6a42fd6f 810 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
f3368128 811 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
6a42fd6f
CK		 812 } else {
813 /* vm_size is 128TB + 512GB for legacy 3-level page support */
814 amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48);
770d13b1 815 adev->gmc.translate_further =
6a42fd6f
CK		 816 adev->vm_manager.num_level > 1;
817 }
fd66560b
HZ		 818 break;
819 case CHIP_VEGA10:
273a14cd 820 case CHIP_VEGA12:
36b32a68
ZJ		 821 /*
822 * To fulfill 4-level page support,
823 * vm size is 256TB (48bit), maximum size of Vega10,
824 * block size 512 (9bit)
825 */
f3368128 826 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
fd66560b
HZ		 827 break;
828 default:
829 break;
e60f8db5
AX		 830 }
831
832 /* This interrupt is VMC page fault.*/
3760f76c 833 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, 0,
770d13b1 834 &adev->gmc.vm_fault);
3760f76c 835 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, 0,
770d13b1 836 &adev->gmc.vm_fault);
e60f8db5
AX		 837
838 if (r)
839 return r;
840
e60f8db5
AX		 841 /* Set the internal MC address mask
842 * This is the max address of the GPU's
843 * internal address space.
844 */
770d13b1 845 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
e60f8db5 846
916910ad
HR		 847 /*
848 * It needs to reserve 8M stolen memory for vega10
849 * TODO: Figure out how to avoid that...
850 */
770d13b1 851 adev->gmc.stolen_size = 8 * 1024 * 1024;
916910ad 852
e60f8db5
AX		 853 /* set DMA mask + need_dma32 flags.
854 * PCIE - can handle 44-bits.
855 * IGP - can handle 44-bits
856 * PCI - dma32 for legacy pci gart, 44 bits on vega10
857 */
858 adev->need_dma32 = false;
859 dma_bits = adev->need_dma32 ? 32 : 44;
860 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
861 if (r) {
862 adev->need_dma32 = true;
863 dma_bits = 32;
864 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
865 }
866 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
867 if (r) {
868 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
869 printk(KERN_WARNING "amdgpu: No coherent DMA available.\n");
870 }
fd5fd480 871 adev->need_swiotlb = drm_get_max_iomem() > ((u64)1 << dma_bits);
e60f8db5
AX		 872
873 r = gmc_v9_0_mc_init(adev);
874 if (r)
875 return r;
876
877 /* Memory manager */
878 r = amdgpu_bo_init(adev);
879 if (r)
880 return r;
881
882 r = gmc_v9_0_gart_init(adev);
883 if (r)
884 return r;
885
05ec3eda
CK		 886 /*
887 * number of VMs
888 * VMID 0 is reserved for System
889 * amdgpu graphics/compute will use VMIDs 1-7
890 * amdkfd will use VMIDs 8-15
891 */
892 adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids = AMDGPU_NUM_OF_VMIDS;
893 adev->vm_manager.id_mgr[AMDGPU_MMHUB].num_ids = AMDGPU_NUM_OF_VMIDS;
894
05ec3eda
CK		 895 amdgpu_vm_manager_init(adev);
896
897 return 0;
e60f8db5
AX		 898}
899
900/**
c79ee7d8 901 * gmc_v9_0_gart_fini - vm fini callback
e60f8db5
AX		 902 *
903 * @adev: amdgpu_device pointer
904 *
905 * Tears down the driver GART/VM setup (CIK).
906 */
907static void gmc_v9_0_gart_fini(struct amdgpu_device *adev)
908{
909 amdgpu_gart_table_vram_free(adev);
910 amdgpu_gart_fini(adev);
911}
912
913static int gmc_v9_0_sw_fini(void *handle)
914{
915 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
916
f59548c8 917 amdgpu_gem_force_release(adev);
05ec3eda 918 amdgpu_vm_manager_fini(adev);
e60f8db5 919 gmc_v9_0_gart_fini(adev);
e60f8db5
AX		 920 amdgpu_bo_fini(adev);
921
922 return 0;
923}
924
925static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
926{
946a4d5b 927
e60f8db5
AX		 928 switch (adev->asic_type) {
929 case CHIP_VEGA10:
946a4d5b 930 soc15_program_register_sequence(adev,
5c583018 931 golden_settings_mmhub_1_0_0,
c47b41a7 932 ARRAY_SIZE(golden_settings_mmhub_1_0_0));
946a4d5b 933 soc15_program_register_sequence(adev,
5c583018 934 golden_settings_athub_1_0_0,
c47b41a7 935 ARRAY_SIZE(golden_settings_athub_1_0_0));
e60f8db5 936 break;
273a14cd
AD		 937 case CHIP_VEGA12:
938 break;
e4f3abaa 939 case CHIP_RAVEN:
946a4d5b 940 soc15_program_register_sequence(adev,
5c583018 941 golden_settings_athub_1_0_0,
c47b41a7 942 ARRAY_SIZE(golden_settings_athub_1_0_0));
e4f3abaa 943 break;
e60f8db5
AX		 944 default:
945 break;
946 }
947}
948
949/**
950 * gmc_v9_0_gart_enable - gart enable
951 *
952 * @adev: amdgpu_device pointer
953 */
954static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
955{
956 int r;
957 bool value;
958 u32 tmp;
959
9c3f2b54
AD		 960 amdgpu_device_program_register_sequence(adev,
961 golden_settings_vega10_hdp,
962 ARRAY_SIZE(golden_settings_vega10_hdp));
e60f8db5
AX		 963
964 if (adev->gart.robj == NULL) {
965 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
966 return -EINVAL;
967 }
ce1b1b66
ML		 968 r = amdgpu_gart_table_vram_pin(adev);
969 if (r)
970 return r;
e60f8db5 971
2fcd43ce
HZ		 972 switch (adev->asic_type) {
973 case CHIP_RAVEN:
974 mmhub_v1_0_initialize_power_gating(adev);
f8386b35 975 mmhub_v1_0_update_power_gating(adev, true);
2fcd43ce
HZ		 976 break;
977 default:
978 break;
979 }
980
e60f8db5
AX		 981 r = gfxhub_v1_0_gart_enable(adev);
982 if (r)
983 return r;
984
985 r = mmhub_v1_0_gart_enable(adev);
986 if (r)
987 return r;
988
846347c9 989 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
e60f8db5 990
b9509c80
HR		 991 tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL);
992 WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);
e60f8db5 993
1d4e0a8c 994 /* After HDP is initialized, flush HDP.*/
69882565 995 adev->nbio_funcs->hdp_flush(adev, NULL);
1d4e0a8c 996
e60f8db5
AX		 997 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
998 value = false;
999 else
1000 value = true;
1001
1002 gfxhub_v1_0_set_fault_enable_default(adev, value);
1003 mmhub_v1_0_set_fault_enable_default(adev, value);
132f34e4 1004 gmc_v9_0_flush_gpu_tlb(adev, 0);
e60f8db5
AX		 1005
1006 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
770d13b1 1007 (unsigned)(adev->gmc.gart_size >> 20),
e60f8db5
AX		 1008 (unsigned long long)adev->gart.table_addr);
1009 adev->gart.ready = true;
1010 return 0;
1011}
1012
1013static int gmc_v9_0_hw_init(void *handle)
1014{
1015 int r;
1016 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1017
1018 /* The sequence of these two function calls matters.*/
1019 gmc_v9_0_init_golden_registers(adev);
1020
edca2d05 1021 if (adev->mode_info.num_crtc) {
edca2d05 1022 /* Lockout access through VGA aperture*/
4d9c333a 1023 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
edca2d05
AD		 1024
1025 /* disable VGA render */
4d9c333a 1026 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
edca2d05
AD		 1027 }
1028
e60f8db5
AX		 1029 r = gmc_v9_0_gart_enable(adev);
1030
1031 return r;
1032}
1033
1034/**
1035 * gmc_v9_0_gart_disable - gart disable
1036 *
1037 * @adev: amdgpu_device pointer
1038 *
1039 * This disables all VM page table.
1040 */
1041static void gmc_v9_0_gart_disable(struct amdgpu_device *adev)
1042{
1043 gfxhub_v1_0_gart_disable(adev);
1044 mmhub_v1_0_gart_disable(adev);
ce1b1b66 1045 amdgpu_gart_table_vram_unpin(adev);
e60f8db5
AX		 1046}
1047
1048static int gmc_v9_0_hw_fini(void *handle)
1049{
1050 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1051
5dd696ae
TH		 1052 if (amdgpu_sriov_vf(adev)) {
1053 /* full access mode, so don't touch any GMC register */
1054 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
1055 return 0;
1056 }
1057
770d13b1 1058 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
e60f8db5
AX		 1059 gmc_v9_0_gart_disable(adev);
1060
1061 return 0;
1062}
1063
1064static int gmc_v9_0_suspend(void *handle)
1065{
1066 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1067
f053cd47 1068 return gmc_v9_0_hw_fini(adev);
e60f8db5
AX		 1069}
1070
1071static int gmc_v9_0_resume(void *handle)
1072{
1073 int r;
1074 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1075
1076 r = gmc_v9_0_hw_init(adev);
1077 if (r)
1078 return r;
1079
620f774f 1080 amdgpu_vmid_reset_all(adev);
e60f8db5 1081
32601d48 1082 return 0;
e60f8db5
AX		 1083}
1084
1085static bool gmc_v9_0_is_idle(void *handle)
1086{
1087 /* MC is always ready in GMC v9.*/
1088 return true;
1089}
1090
1091static int gmc_v9_0_wait_for_idle(void *handle)
1092{
1093 /* There is no need to wait for MC idle in GMC v9.*/
1094 return 0;
1095}
1096
1097static int gmc_v9_0_soft_reset(void *handle)
1098{
1099 /* XXX for emulation.*/
1100 return 0;
1101}
1102
1103static int gmc_v9_0_set_clockgating_state(void *handle,
1104 enum amd_clockgating_state state)
1105{
d5583d4f
HR		 1106 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1107
1108 return mmhub_v1_0_set_clockgating(adev, state);
e60f8db5
AX		 1109}
1110
13052be5
HR		 1111static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags)
1112{
1113 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1114
1115 mmhub_v1_0_get_clockgating(adev, flags);
1116}
1117
e60f8db5
AX		 1118static int gmc_v9_0_set_powergating_state(void *handle,
1119 enum amd_powergating_state state)
1120{
1121 return 0;
1122}
1123
1124const struct amd_ip_funcs gmc_v9_0_ip_funcs = {
1125 .name = "gmc_v9_0",
1126 .early_init = gmc_v9_0_early_init,
1127 .late_init = gmc_v9_0_late_init,
1128 .sw_init = gmc_v9_0_sw_init,
1129 .sw_fini = gmc_v9_0_sw_fini,
1130 .hw_init = gmc_v9_0_hw_init,
1131 .hw_fini = gmc_v9_0_hw_fini,
1132 .suspend = gmc_v9_0_suspend,
1133 .resume = gmc_v9_0_resume,
1134 .is_idle = gmc_v9_0_is_idle,
1135 .wait_for_idle = gmc_v9_0_wait_for_idle,
1136 .soft_reset = gmc_v9_0_soft_reset,
1137 .set_clockgating_state = gmc_v9_0_set_clockgating_state,
1138 .set_powergating_state = gmc_v9_0_set_powergating_state,
13052be5 1139 .get_clockgating_state = gmc_v9_0_get_clockgating_state,
e60f8db5
AX		 1140};
1141
1142const struct amdgpu_ip_block_version gmc_v9_0_ip_block =
1143{
1144 .type = AMD_IP_BLOCK_TYPE_GMC,
1145 .major = 9,
1146 .minor = 0,
1147 .rev = 0,
1148 .funcs = &gmc_v9_0_ip_funcs,
1149};
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