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[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / amd / amdgpu / gmc_v9_0.c
CommitLineData
e60f8db5
AX		 1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include "amdgpu.h"
25#include "gmc_v9_0.h"
8d6a5230 26#include "amdgpu_atomfirmware.h"
e60f8db5
AX		 27
28#include "vega10/soc15ip.h"
29#include "vega10/HDP/hdp_4_0_offset.h"
30#include "vega10/HDP/hdp_4_0_sh_mask.h"
31#include "vega10/GC/gc_9_0_sh_mask.h"
edca2d05
AD		 32#include "vega10/DC/dce_12_0_offset.h"
33#include "vega10/DC/dce_12_0_sh_mask.h"
e60f8db5
AX		 34#include "vega10/vega10_enum.h"
35
36#include "soc15_common.h"
37
38#include "nbio_v6_1.h"
aecbe64f 39#include "nbio_v7_0.h"
e60f8db5
AX		 40#include "gfxhub_v1_0.h"
41#include "mmhub_v1_0.h"
42
43#define mmDF_CS_AON0_DramBaseAddress0 0x0044
44#define mmDF_CS_AON0_DramBaseAddress0_BASE_IDX 0
45//DF_CS_AON0_DramBaseAddress0
46#define DF_CS_AON0_DramBaseAddress0__AddrRngVal__SHIFT 0x0
47#define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT 0x1
48#define DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT 0x4
49#define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT 0x8
50#define DF_CS_AON0_DramBaseAddress0__DramBaseAddr__SHIFT 0xc
51#define DF_CS_AON0_DramBaseAddress0__AddrRngVal_MASK 0x00000001L
52#define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK 0x00000002L
53#define DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK 0x000000F0L
54#define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK 0x00000700L
55#define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK 0xFFFFF000L
56
57/* XXX Move this macro to VEGA10 header file, which is like vid.h for VI.*/
58#define AMDGPU_NUM_OF_VMIDS 8
59
60static const u32 golden_settings_vega10_hdp[] =
61{
62 0xf64, 0x0fffffff, 0x00000000,
63 0xf65, 0x0fffffff, 0x00000000,
64 0xf66, 0x0fffffff, 0x00000000,
65 0xf67, 0x0fffffff, 0x00000000,
66 0xf68, 0x0fffffff, 0x00000000,
67 0xf6a, 0x0fffffff, 0x00000000,
68 0xf6b, 0x0fffffff, 0x00000000,
69 0xf6c, 0x0fffffff, 0x00000000,
70 0xf6d, 0x0fffffff, 0x00000000,
71 0xf6e, 0x0fffffff, 0x00000000,
72};
73
74static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
75 struct amdgpu_irq_src *src,
76 unsigned type,
77 enum amdgpu_interrupt_state state)
78{
79 struct amdgpu_vmhub *hub;
ae6d1416 80 u32 tmp, reg, bits, i, j;
e60f8db5 81
11250164
CK		 82 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
83 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
84 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
85 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
86 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
87 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
88 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
89
e60f8db5
AX		 90 switch (state) {
91 case AMDGPU_IRQ_STATE_DISABLE:
ae6d1416
TSD		 92 for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) {
93 hub = &adev->vmhub[j];
94 for (i = 0; i < 16; i++) {
95 reg = hub->vm_context0_cntl + i;
96 tmp = RREG32(reg);
97 tmp &= ~bits;
98 WREG32(reg, tmp);
99 }
e60f8db5
AX		 100 }
101 break;
102 case AMDGPU_IRQ_STATE_ENABLE:
ae6d1416
TSD		 103 for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) {
104 hub = &adev->vmhub[j];
105 for (i = 0; i < 16; i++) {
106 reg = hub->vm_context0_cntl + i;
107 tmp = RREG32(reg);
108 tmp |= bits;
109 WREG32(reg, tmp);
110 }
e60f8db5 111 }
e60f8db5
AX		 112 default:
113 break;
114 }
115
116 return 0;
117}
118
119static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
120 struct amdgpu_irq_src *source,
121 struct amdgpu_iv_entry *entry)
122{
5a9b8e8a 123 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vm_id_src];
4d6cbde3 124 uint32_t status = 0;
e60f8db5
AX		 125 u64 addr;
126
127 addr = (u64)entry->src_data[0] << 12;
128 addr |= ((u64)entry->src_data[1] & 0xf) << 44;
129
79a0c465 130 if (!amdgpu_sriov_vf(adev)) {
5a9b8e8a
CK		 131 status = RREG32(hub->vm_l2_pro_fault_status);
132 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
4d6cbde3 133 }
e60f8db5 134
4d6cbde3
FK		 135 if (printk_ratelimit()) {
136 dev_err(adev->dev,
137 "[%s] VMC page fault (src_id:%u ring:%u vm_id:%u pas_id:%u)\n",
138 entry->vm_id_src ? "mmhub" : "gfxhub",
139 entry->src_id, entry->ring_id, entry->vm_id,
140 entry->pas_id);
141 dev_err(adev->dev, " at page 0x%016llx from %d\n",
142 addr, entry->client_id);
143 if (!amdgpu_sriov_vf(adev))
144 dev_err(adev->dev,
145 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
146 status);
79a0c465 147 }
e60f8db5
AX		 148
149 return 0;
150}
151
152static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = {
153 .set = gmc_v9_0_vm_fault_interrupt_state,
154 .process = gmc_v9_0_process_interrupt,
155};
156
157static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev)
158{
159 adev->mc.vm_fault.num_types = 1;
160 adev->mc.vm_fault.funcs = &gmc_v9_0_irq_funcs;
161}
162
03f89feb
CK		 163static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vm_id)
164{
165 u32 req = 0;
166
167 /* invalidate using legacy mode on vm_id*/
168 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
169 PER_VMID_INVALIDATE_REQ, 1 << vm_id);
170 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, 0);
171 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
172 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
173 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
174 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
175 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
176 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
177 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
178
179 return req;
180}
181
e60f8db5
AX		 182/*
183 * GART
184 * VMID 0 is the physical GPU addresses as used by the kernel.
185 * VMIDs 1-15 are used for userspace clients and are handled
186 * by the amdgpu vm/hsa code.
187 */
188
189/**
190 * gmc_v9_0_gart_flush_gpu_tlb - gart tlb flush callback
191 *
192 * @adev: amdgpu_device pointer
193 * @vmid: vm instance to flush
194 *
195 * Flush the TLB for the requested page table.
196 */
197static void gmc_v9_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
198 uint32_t vmid)
199{
200 /* Use register 17 for GART */
201 const unsigned eng = 17;
202 unsigned i, j;
203
204 /* flush hdp cache */
aecbe64f
CZ		 205 if (adev->flags & AMD_IS_APU)
206 nbio_v7_0_hdp_flush(adev);
207 else
208 nbio_v6_1_hdp_flush(adev);
e60f8db5
AX		 209
210 spin_lock(&adev->mc.invalidate_lock);
211
212 for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
213 struct amdgpu_vmhub *hub = &adev->vmhub[i];
03f89feb 214 u32 tmp = gmc_v9_0_get_invalidate_req(vmid);
e60f8db5 215
c7a7266b 216 WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);
e60f8db5
AX		 217
218 /* Busy wait for ACK.*/
219 for (j = 0; j < 100; j++) {
c7a7266b 220 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
e60f8db5
AX		 221 tmp &= 1 << vmid;
222 if (tmp)
223 break;
224 cpu_relax();
225 }
226 if (j < 100)
227 continue;
228
229 /* Wait for ACK with a delay.*/
230 for (j = 0; j < adev->usec_timeout; j++) {
c7a7266b 231 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
e60f8db5
AX		 232 tmp &= 1 << vmid;
233 if (tmp)
234 break;
235 udelay(1);
236 }
237 if (j < adev->usec_timeout)
238 continue;
239
240 DRM_ERROR("Timeout waiting for VM flush ACK!\n");
241 }
242
243 spin_unlock(&adev->mc.invalidate_lock);
244}
245
246/**
247 * gmc_v9_0_gart_set_pte_pde - update the page tables using MMIO
248 *
249 * @adev: amdgpu_device pointer
250 * @cpu_pt_addr: cpu address of the page table
251 * @gpu_page_idx: entry in the page table to update
252 * @addr: dst addr to write into pte/pde
253 * @flags: access flags
254 *
255 * Update the page tables using the CPU.
256 */
257static int gmc_v9_0_gart_set_pte_pde(struct amdgpu_device *adev,
258 void *cpu_pt_addr,
259 uint32_t gpu_page_idx,
260 uint64_t addr,
261 uint64_t flags)
262{
263 void __iomem *ptr = (void *)cpu_pt_addr;
264 uint64_t value;
265
266 /*
267 * PTE format on VEGA 10:
268 * 63:59 reserved
269 * 58:57 mtype
270 * 56 F
271 * 55 L
272 * 54 P
273 * 53 SW
274 * 52 T
275 * 50:48 reserved
276 * 47:12 4k physical page base address
277 * 11:7 fragment
278 * 6 write
279 * 5 read
280 * 4 exe
281 * 3 Z
282 * 2 snooped
283 * 1 system
284 * 0 valid
285 *
286 * PDE format on VEGA 10:
287 * 63:59 block fragment size
288 * 58:55 reserved
289 * 54 P
290 * 53:48 reserved
291 * 47:6 physical base address of PD or PTE
292 * 5:3 reserved
293 * 2 C
294 * 1 system
295 * 0 valid
296 */
297
298 /*
299 * The following is for PTE only. GART does not have PDEs.
300 */
301 value = addr & 0x0000FFFFFFFFF000ULL;
302 value |= flags;
303 writeq(value, ptr + (gpu_page_idx * 8));
304 return 0;
305}
306
307static uint64_t gmc_v9_0_get_vm_pte_flags(struct amdgpu_device *adev,
308 uint32_t flags)
309
310{
311 uint64_t pte_flag = 0;
312
313 if (flags & AMDGPU_VM_PAGE_EXECUTABLE)
314 pte_flag |= AMDGPU_PTE_EXECUTABLE;
315 if (flags & AMDGPU_VM_PAGE_READABLE)
316 pte_flag |= AMDGPU_PTE_READABLE;
317 if (flags & AMDGPU_VM_PAGE_WRITEABLE)
318 pte_flag |= AMDGPU_PTE_WRITEABLE;
319
320 switch (flags & AMDGPU_VM_MTYPE_MASK) {
321 case AMDGPU_VM_MTYPE_DEFAULT:
322 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
323 break;
324 case AMDGPU_VM_MTYPE_NC:
325 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
326 break;
327 case AMDGPU_VM_MTYPE_WC:
328 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_WC);
329 break;
330 case AMDGPU_VM_MTYPE_CC:
331 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_CC);
332 break;
333 case AMDGPU_VM_MTYPE_UC:
334 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_UC);
335 break;
336 default:
337 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
338 break;
339 }
340
341 if (flags & AMDGPU_VM_PAGE_PRT)
342 pte_flag |= AMDGPU_PTE_PRT;
343
344 return pte_flag;
345}
346
b1166325 347static u64 gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, u64 addr)
e60f8db5 348{
b1166325
CK		 349 addr = adev->vm_manager.vram_base_offset + addr - adev->mc.vram_start;
350 BUG_ON(addr & 0xFFFF00000000003FULL);
351 return addr;
e60f8db5
AX		 352}
353
f75e237c
CK		 354static const struct amdgpu_gart_funcs gmc_v9_0_gart_funcs = {
355 .flush_gpu_tlb = gmc_v9_0_gart_flush_gpu_tlb,
356 .set_pte_pde = gmc_v9_0_gart_set_pte_pde,
03f89feb 357 .get_invalidate_req = gmc_v9_0_get_invalidate_req,
b1166325
CK		 358 .get_vm_pte_flags = gmc_v9_0_get_vm_pte_flags,
359 .get_vm_pde = gmc_v9_0_get_vm_pde
e60f8db5
AX		 360};
361
f75e237c 362static void gmc_v9_0_set_gart_funcs(struct amdgpu_device *adev)
e60f8db5 363{
f75e237c
CK		 364 if (adev->gart.gart_funcs == NULL)
365 adev->gart.gart_funcs = &gmc_v9_0_gart_funcs;
e60f8db5
AX		 366}
367
368static int gmc_v9_0_early_init(void *handle)
369{
370 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
371
372 gmc_v9_0_set_gart_funcs(adev);
e60f8db5
AX		 373 gmc_v9_0_set_irq_funcs(adev);
374
375 return 0;
376}
377
378static int gmc_v9_0_late_init(void *handle)
379{
380 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
43b9176f 381 unsigned vm_inv_eng[AMDGPU_MAX_VMHUBS] = { 3, 3 };
4789c463
CK		 382 unsigned i;
383
384 for(i = 0; i < adev->num_rings; ++i) {
385 struct amdgpu_ring *ring = adev->rings[i];
386 unsigned vmhub = ring->funcs->vmhub;
387
388 ring->vm_inv_eng = vm_inv_eng[vmhub]++;
775f55f1
TSD		 389 dev_info(adev->dev, "ring %u(%s) uses VM inv eng %u on hub %u\n",
390 ring->idx, ring->name, ring->vm_inv_eng,
391 ring->funcs->vmhub);
4789c463
CK		 392 }
393
394 /* Engine 17 is used for GART flushes */
395 for(i = 0; i < AMDGPU_MAX_VMHUBS; ++i)
396 BUG_ON(vm_inv_eng[i] > 17);
397
e60f8db5
AX		 398 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
399}
400
401static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
402 struct amdgpu_mc *mc)
403{
eeb2487d
ML		 404 u64 base = 0;
405 if (!amdgpu_sriov_vf(adev))
406 base = mmhub_v1_0_get_fb_location(adev);
e60f8db5 407 amdgpu_vram_location(adev, &adev->mc, base);
6f02a696 408 amdgpu_gart_location(adev, mc);
bc099ee9
CZ		 409 /* base offset of vram pages */
410 if (adev->flags & AMD_IS_APU)
411 adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev);
412 else
413 adev->vm_manager.vram_base_offset = 0;
e60f8db5
AX		 414}
415
416/**
417 * gmc_v9_0_mc_init - initialize the memory controller driver params
418 *
419 * @adev: amdgpu_device pointer
420 *
421 * Look up the amount of vram, vram width, and decide how to place
422 * vram and gart within the GPU's physical address space.
423 * Returns 0 for success.
424 */
425static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
426{
427 u32 tmp;
428 int chansize, numchan;
429
8d6a5230
AD		 430 adev->mc.vram_width = amdgpu_atomfirmware_get_vram_width(adev);
431 if (!adev->mc.vram_width) {
432 /* hbm memory channel size */
433 chansize = 128;
434
435 tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0);
436 tmp &= DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK;
437 tmp >>= DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
438 switch (tmp) {
439 case 0:
440 default:
441 numchan = 1;
442 break;
443 case 1:
444 numchan = 2;
445 break;
446 case 2:
447 numchan = 0;
448 break;
449 case 3:
450 numchan = 4;
451 break;
452 case 4:
453 numchan = 0;
454 break;
455 case 5:
456 numchan = 8;
457 break;
458 case 6:
459 numchan = 0;
460 break;
461 case 7:
462 numchan = 16;
463 break;
464 case 8:
465 numchan = 2;
466 break;
467 }
468 adev->mc.vram_width = numchan * chansize;
e60f8db5 469 }
e60f8db5
AX		 470
471 /* Could aper size report 0 ? */
472 adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
473 adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
474 /* size in MB on si */
475 adev->mc.mc_vram_size =
aecbe64f
CZ		 476 ((adev->flags & AMD_IS_APU) ? nbio_v7_0_get_memsize(adev) :
477 nbio_v6_1_get_memsize(adev)) * 1024ULL * 1024ULL;
e60f8db5
AX		 478 adev->mc.real_vram_size = adev->mc.mc_vram_size;
479 adev->mc.visible_vram_size = adev->mc.aper_size;
480
481 /* In case the PCI BAR is larger than the actual amount of vram */
482 if (adev->mc.visible_vram_size > adev->mc.real_vram_size)
483 adev->mc.visible_vram_size = adev->mc.real_vram_size;
484
c3db7b5a
AD		 485 /* set the gart size */
486 if (amdgpu_gart_size == -1) {
487 switch (adev->asic_type) {
488 case CHIP_VEGA10: /* all engines support GPUVM */
489 default:
490 adev->mc.gart_size = 256ULL << 20;
491 break;
492 case CHIP_RAVEN: /* DCE SG support */
493 adev->mc.gart_size = 1024ULL << 20;
494 break;
495 }
496 } else {
497 adev->mc.gart_size = (u64)amdgpu_gart_size << 20;
498 }
499
e60f8db5
AX		 500 gmc_v9_0_vram_gtt_location(adev, &adev->mc);
501
502 return 0;
503}
504
505static int gmc_v9_0_gart_init(struct amdgpu_device *adev)
506{
507 int r;
508
509 if (adev->gart.robj) {
510 WARN(1, "VEGA10 PCIE GART already initialized\n");
511 return 0;
512 }
513 /* Initialize common gart structure */
514 r = amdgpu_gart_init(adev);
515 if (r)
516 return r;
517 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
518 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE(MTYPE_UC) |
519 AMDGPU_PTE_EXECUTABLE;
520 return amdgpu_gart_table_vram_alloc(adev);
521}
522
e60f8db5
AX		 523static int gmc_v9_0_sw_init(void *handle)
524{
525 int r;
526 int dma_bits;
527 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
528
0c8c0847 529 gfxhub_v1_0_init(adev);
77f6c763 530 mmhub_v1_0_init(adev);
0c8c0847 531
e60f8db5
AX		 532 spin_lock_init(&adev->mc.invalidate_lock);
533
fd66560b
HZ		 534 switch (adev->asic_type) {
535 case CHIP_RAVEN:
e60f8db5 536 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
fd66560b
HZ		 537 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
538 adev->vm_manager.vm_size = 1U << 18;
539 adev->vm_manager.block_size = 9;
540 adev->vm_manager.num_level = 3;
d07f14be 541 amdgpu_vm_set_fragment_size(adev, 9);
fd66560b 542 } else {
d07f14be
RH		 543 /* vm_size is 64GB for legacy 2-level page support */
544 amdgpu_vm_adjust_size(adev, 64, 9);
fd66560b
HZ		 545 adev->vm_manager.num_level = 1;
546 }
547 break;
548 case CHIP_VEGA10:
e60f8db5
AX		 549 /* XXX Don't know how to get VRAM type yet. */
550 adev->mc.vram_type = AMDGPU_VRAM_TYPE_HBM;
36b32a68
ZJ		 551 /*
552 * To fulfill 4-level page support,
553 * vm size is 256TB (48bit), maximum size of Vega10,
554 * block size 512 (9bit)
555 */
556 adev->vm_manager.vm_size = 1U << 18;
557 adev->vm_manager.block_size = 9;
fd66560b 558 adev->vm_manager.num_level = 3;
d07f14be 559 amdgpu_vm_set_fragment_size(adev, 9);
fd66560b
HZ		 560 break;
561 default:
562 break;
e60f8db5
AX		 563 }
564
e618d306 565 DRM_INFO("vm size is %llu GB, block size is %u-bit,fragment size is %u-bit\n",
fd66560b 566 adev->vm_manager.vm_size,
e618d306
RH		 567 adev->vm_manager.block_size,
568 adev->vm_manager.fragment_size);
fd66560b 569
e60f8db5
AX		 570 /* This interrupt is VMC page fault.*/
571 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VMC, 0,
572 &adev->mc.vm_fault);
d7c434d3
FK		 573 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_UTCL2, 0,
574 &adev->mc.vm_fault);
e60f8db5
AX		 575
576 if (r)
577 return r;
578
36b32a68 579 adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
e60f8db5
AX		 580
581 /* Set the internal MC address mask
582 * This is the max address of the GPU's
583 * internal address space.
584 */
585 adev->mc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
586
916910ad
HR		 587 /*
588 * It needs to reserve 8M stolen memory for vega10
589 * TODO: Figure out how to avoid that...
590 */
591 adev->mc.stolen_size = 8 * 1024 * 1024;
592
e60f8db5
AX		 593 /* set DMA mask + need_dma32 flags.
594 * PCIE - can handle 44-bits.
595 * IGP - can handle 44-bits
596 * PCI - dma32 for legacy pci gart, 44 bits on vega10
597 */
598 adev->need_dma32 = false;
599 dma_bits = adev->need_dma32 ? 32 : 44;
600 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
601 if (r) {
602 adev->need_dma32 = true;
603 dma_bits = 32;
604 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
605 }
606 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
607 if (r) {
608 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
609 printk(KERN_WARNING "amdgpu: No coherent DMA available.\n");
610 }
611
612 r = gmc_v9_0_mc_init(adev);
613 if (r)
614 return r;
615
616 /* Memory manager */
617 r = amdgpu_bo_init(adev);
618 if (r)
619 return r;
620
621 r = gmc_v9_0_gart_init(adev);
622 if (r)
623 return r;
624
05ec3eda
CK		 625 /*
626 * number of VMs
627 * VMID 0 is reserved for System
628 * amdgpu graphics/compute will use VMIDs 1-7
629 * amdkfd will use VMIDs 8-15
630 */
631 adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids = AMDGPU_NUM_OF_VMIDS;
632 adev->vm_manager.id_mgr[AMDGPU_MMHUB].num_ids = AMDGPU_NUM_OF_VMIDS;
633
05ec3eda
CK		 634 amdgpu_vm_manager_init(adev);
635
636 return 0;
e60f8db5
AX		 637}
638
639/**
640 * gmc_v8_0_gart_fini - vm fini callback
641 *
642 * @adev: amdgpu_device pointer
643 *
644 * Tears down the driver GART/VM setup (CIK).
645 */
646static void gmc_v9_0_gart_fini(struct amdgpu_device *adev)
647{
648 amdgpu_gart_table_vram_free(adev);
649 amdgpu_gart_fini(adev);
650}
651
652static int gmc_v9_0_sw_fini(void *handle)
653{
654 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
655
05ec3eda 656 amdgpu_vm_manager_fini(adev);
e60f8db5
AX		 657 gmc_v9_0_gart_fini(adev);
658 amdgpu_gem_force_release(adev);
659 amdgpu_bo_fini(adev);
660
661 return 0;
662}
663
664static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
665{
666 switch (adev->asic_type) {
667 case CHIP_VEGA10:
668 break;
e4f3abaa
CZ		 669 case CHIP_RAVEN:
670 break;
e60f8db5
AX		 671 default:
672 break;
673 }
674}
675
676/**
677 * gmc_v9_0_gart_enable - gart enable
678 *
679 * @adev: amdgpu_device pointer
680 */
681static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
682{
683 int r;
684 bool value;
685 u32 tmp;
686
687 amdgpu_program_register_sequence(adev,
688 golden_settings_vega10_hdp,
689 (const u32)ARRAY_SIZE(golden_settings_vega10_hdp));
690
691 if (adev->gart.robj == NULL) {
692 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
693 return -EINVAL;
694 }
695 r = amdgpu_gart_table_vram_pin(adev);
696 if (r)
697 return r;
698
2fcd43ce
HZ		 699 switch (adev->asic_type) {
700 case CHIP_RAVEN:
701 mmhub_v1_0_initialize_power_gating(adev);
f8386b35 702 mmhub_v1_0_update_power_gating(adev, true);
2fcd43ce
HZ		 703 break;
704 default:
705 break;
706 }
707
e60f8db5
AX		 708 r = gfxhub_v1_0_gart_enable(adev);
709 if (r)
710 return r;
711
712 r = mmhub_v1_0_gart_enable(adev);
713 if (r)
714 return r;
715
846347c9 716 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
e60f8db5 717
b9509c80
HR		 718 tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL);
719 WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);
e60f8db5 720
1d4e0a8c
ML		 721 /* After HDP is initialized, flush HDP.*/
722 if (adev->flags & AMD_IS_APU)
723 nbio_v7_0_hdp_flush(adev);
724 else
725 nbio_v6_1_hdp_flush(adev);
726
e60f8db5
AX		 727 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
728 value = false;
729 else
730 value = true;
731
732 gfxhub_v1_0_set_fault_enable_default(adev, value);
733 mmhub_v1_0_set_fault_enable_default(adev, value);
e60f8db5
AX		 734 gmc_v9_0_gart_flush_gpu_tlb(adev, 0);
735
736 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
6f02a696 737 (unsigned)(adev->mc.gart_size >> 20),
e60f8db5
AX		 738 (unsigned long long)adev->gart.table_addr);
739 adev->gart.ready = true;
740 return 0;
741}
742
743static int gmc_v9_0_hw_init(void *handle)
744{
745 int r;
746 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
747
748 /* The sequence of these two function calls matters.*/
749 gmc_v9_0_init_golden_registers(adev);
750
edca2d05 751 if (adev->mode_info.num_crtc) {
edca2d05 752 /* Lockout access through VGA aperture*/
4d9c333a 753 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
edca2d05
AD		 754
755 /* disable VGA render */
4d9c333a 756 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
edca2d05
AD		 757 }
758
e60f8db5
AX		 759 r = gmc_v9_0_gart_enable(adev);
760
761 return r;
762}
763
764/**
765 * gmc_v9_0_gart_disable - gart disable
766 *
767 * @adev: amdgpu_device pointer
768 *
769 * This disables all VM page table.
770 */
771static void gmc_v9_0_gart_disable(struct amdgpu_device *adev)
772{
773 gfxhub_v1_0_gart_disable(adev);
774 mmhub_v1_0_gart_disable(adev);
775 amdgpu_gart_table_vram_unpin(adev);
776}
777
778static int gmc_v9_0_hw_fini(void *handle)
779{
780 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
781
5dd696ae
TH		 782 if (amdgpu_sriov_vf(adev)) {
783 /* full access mode, so don't touch any GMC register */
784 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
785 return 0;
786 }
787
e60f8db5
AX		 788 amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
789 gmc_v9_0_gart_disable(adev);
790
791 return 0;
792}
793
794static int gmc_v9_0_suspend(void *handle)
795{
796 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
797
f053cd47 798 return gmc_v9_0_hw_fini(adev);
e60f8db5
AX		 799}
800
801static int gmc_v9_0_resume(void *handle)
802{
803 int r;
804 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
805
806 r = gmc_v9_0_hw_init(adev);
807 if (r)
808 return r;
809
32601d48 810 amdgpu_vm_reset_all_ids(adev);
e60f8db5 811
32601d48 812 return 0;
e60f8db5
AX		 813}
814
815static bool gmc_v9_0_is_idle(void *handle)
816{
817 /* MC is always ready in GMC v9.*/
818 return true;
819}
820
821static int gmc_v9_0_wait_for_idle(void *handle)
822{
823 /* There is no need to wait for MC idle in GMC v9.*/
824 return 0;
825}
826
827static int gmc_v9_0_soft_reset(void *handle)
828{
829 /* XXX for emulation.*/
830 return 0;
831}
832
833static int gmc_v9_0_set_clockgating_state(void *handle,
834 enum amd_clockgating_state state)
835{
d5583d4f
HR		 836 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
837
838 return mmhub_v1_0_set_clockgating(adev, state);
e60f8db5
AX		 839}
840
13052be5
HR		 841static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags)
842{
843 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
844
845 mmhub_v1_0_get_clockgating(adev, flags);
846}
847
e60f8db5
AX		 848static int gmc_v9_0_set_powergating_state(void *handle,
849 enum amd_powergating_state state)
850{
851 return 0;
852}
853
854const struct amd_ip_funcs gmc_v9_0_ip_funcs = {
855 .name = "gmc_v9_0",
856 .early_init = gmc_v9_0_early_init,
857 .late_init = gmc_v9_0_late_init,
858 .sw_init = gmc_v9_0_sw_init,
859 .sw_fini = gmc_v9_0_sw_fini,
860 .hw_init = gmc_v9_0_hw_init,
861 .hw_fini = gmc_v9_0_hw_fini,
862 .suspend = gmc_v9_0_suspend,
863 .resume = gmc_v9_0_resume,
864 .is_idle = gmc_v9_0_is_idle,
865 .wait_for_idle = gmc_v9_0_wait_for_idle,
866 .soft_reset = gmc_v9_0_soft_reset,
867 .set_clockgating_state = gmc_v9_0_set_clockgating_state,
868 .set_powergating_state = gmc_v9_0_set_powergating_state,
13052be5 869 .get_clockgating_state = gmc_v9_0_get_clockgating_state,
e60f8db5
AX		 870};
871
872const struct amdgpu_ip_block_version gmc_v9_0_ip_block =
873{
874 .type = AMD_IP_BLOCK_TYPE_GMC,
875 .major = 9,
876 .minor = 0,
877 .rev = 0,
878 .funcs = &gmc_v9_0_ip_funcs,
879};
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