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edc61147 HZ |
1 | /* |
2 | * Copyright 2019 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | */ | |
23 | ||
b23b2e9e AD |
24 | #include <linux/pci.h> |
25 | ||
edc61147 HZ |
26 | #include "amdgpu.h" |
27 | #include "amdgpu_ih.h" | |
28 | ||
29 | #include "oss/osssys_5_0_0_offset.h" | |
30 | #include "oss/osssys_5_0_0_sh_mask.h" | |
31 | ||
32 | #include "soc15_common.h" | |
33 | #include "navi10_ih.h" | |
34 | ||
022b6518 | 35 | #define MAX_REARM_RETRY 10 |
edc61147 HZ |
36 | |
37 | static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev); | |
38 | ||
39 | /** | |
40 | * navi10_ih_enable_interrupts - Enable the interrupt ring buffer | |
41 | * | |
42 | * @adev: amdgpu_device pointer | |
43 | * | |
44 | * Enable the interrupt ring buffer (NAVI10). | |
45 | */ | |
46 | static void navi10_ih_enable_interrupts(struct amdgpu_device *adev) | |
47 | { | |
48 | u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); | |
49 | ||
50 | ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); | |
51 | ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); | |
52 | WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); | |
53 | adev->irq.ih.enabled = true; | |
ab518012 AS |
54 | |
55 | if (adev->irq.ih1.ring_size) { | |
56 | ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); | |
57 | ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, | |
58 | RB_ENABLE, 1); | |
59 | WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); | |
60 | adev->irq.ih1.enabled = true; | |
61 | } | |
62 | ||
63 | if (adev->irq.ih2.ring_size) { | |
64 | ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); | |
65 | ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, | |
66 | RB_ENABLE, 1); | |
67 | WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); | |
68 | adev->irq.ih2.enabled = true; | |
69 | } | |
edc61147 HZ |
70 | } |
71 | ||
72 | /** | |
73 | * navi10_ih_disable_interrupts - Disable the interrupt ring buffer | |
74 | * | |
75 | * @adev: amdgpu_device pointer | |
76 | * | |
77 | * Disable the interrupt ring buffer (NAVI10). | |
78 | */ | |
79 | static void navi10_ih_disable_interrupts(struct amdgpu_device *adev) | |
80 | { | |
81 | u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); | |
82 | ||
83 | ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); | |
84 | ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); | |
85 | WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); | |
86 | /* set rptr, wptr to 0 */ | |
87 | WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); | |
88 | WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); | |
89 | adev->irq.ih.enabled = false; | |
90 | adev->irq.ih.rptr = 0; | |
ab518012 AS |
91 | |
92 | if (adev->irq.ih1.ring_size) { | |
93 | ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); | |
94 | ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, | |
95 | RB_ENABLE, 0); | |
96 | WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); | |
97 | /* set rptr, wptr to 0 */ | |
98 | WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); | |
99 | WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); | |
100 | adev->irq.ih1.enabled = false; | |
101 | adev->irq.ih1.rptr = 0; | |
102 | } | |
103 | ||
104 | if (adev->irq.ih2.ring_size) { | |
105 | ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); | |
106 | ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, | |
107 | RB_ENABLE, 0); | |
108 | WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); | |
109 | /* set rptr, wptr to 0 */ | |
110 | WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0); | |
111 | WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0); | |
112 | adev->irq.ih2.enabled = false; | |
113 | adev->irq.ih2.rptr = 0; | |
114 | } | |
115 | ||
edc61147 HZ |
116 | } |
117 | ||
118 | static uint32_t navi10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) | |
119 | { | |
120 | int rb_bufsz = order_base_2(ih->ring_size / 4); | |
121 | ||
122 | ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, | |
123 | MC_SPACE, ih->use_bus_addr ? 1 : 4); | |
124 | ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, | |
125 | WPTR_OVERFLOW_CLEAR, 1); | |
126 | ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, | |
127 | WPTR_OVERFLOW_ENABLE, 1); | |
128 | ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); | |
129 | /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register | |
130 | * value is written to memory | |
131 | */ | |
132 | ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, | |
133 | WPTR_WRITEBACK_ENABLE, 1); | |
134 | ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); | |
135 | ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); | |
136 | ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); | |
137 | ||
138 | return ih_rb_cntl; | |
139 | } | |
140 | ||
ab518012 AS |
141 | static uint32_t navi10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) |
142 | { | |
143 | u32 ih_doorbell_rtpr = 0; | |
144 | ||
145 | if (ih->use_doorbell) { | |
146 | ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, | |
147 | IH_DOORBELL_RPTR, OFFSET, | |
148 | ih->doorbell_index); | |
149 | ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, | |
150 | IH_DOORBELL_RPTR, | |
151 | ENABLE, 1); | |
152 | } else { | |
153 | ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, | |
154 | IH_DOORBELL_RPTR, | |
155 | ENABLE, 0); | |
156 | } | |
157 | return ih_doorbell_rtpr; | |
158 | } | |
159 | ||
edc61147 HZ |
160 | /** |
161 | * navi10_ih_irq_init - init and enable the interrupt ring | |
162 | * | |
163 | * @adev: amdgpu_device pointer | |
164 | * | |
165 | * Allocate a ring buffer for the interrupt controller, | |
166 | * enable the RLC, disable interrupts, enable the IH | |
167 | * ring buffer and enable it (NAVI). | |
168 | * Called at device load and reume. | |
169 | * Returns 0 for success, errors for failure. | |
170 | */ | |
171 | static int navi10_ih_irq_init(struct amdgpu_device *adev) | |
172 | { | |
173 | struct amdgpu_ih_ring *ih = &adev->irq.ih; | |
ab518012 | 174 | u32 ih_rb_cntl, ih_chicken; |
edc61147 HZ |
175 | u32 tmp; |
176 | ||
177 | /* disable irqs */ | |
178 | navi10_ih_disable_interrupts(adev); | |
179 | ||
bebc0762 | 180 | adev->nbio.funcs->ih_control(adev); |
edc61147 HZ |
181 | |
182 | /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ | |
183 | WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, ih->gpu_addr >> 8); | |
184 | WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (ih->gpu_addr >> 40) & 0xff); | |
185 | ||
186 | ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); | |
187 | ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl); | |
188 | ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, | |
189 | !!adev->irq.msi_enabled); | |
190 | ||
191 | if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)) { | |
192 | if (ih->use_bus_addr) { | |
193 | ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); | |
194 | ih_chicken = REG_SET_FIELD(ih_chicken, | |
195 | IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); | |
196 | WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); | |
197 | } | |
198 | } | |
199 | ||
200 | WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); | |
201 | ||
202 | /* set the writeback address whether it's enabled or not */ | |
203 | WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, | |
204 | lower_32_bits(ih->wptr_addr)); | |
205 | WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, | |
206 | upper_32_bits(ih->wptr_addr) & 0xFFFF); | |
207 | ||
208 | /* set rptr, wptr to 0 */ | |
209 | WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); | |
210 | WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); | |
211 | ||
ab518012 AS |
212 | WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR, |
213 | navi10_ih_doorbell_rptr(ih)); | |
edc61147 | 214 | |
bebc0762 | 215 | adev->nbio.funcs->ih_doorbell_range(adev, ih->use_doorbell, |
edc61147 HZ |
216 | ih->doorbell_index); |
217 | ||
ab518012 AS |
218 | ih = &adev->irq.ih1; |
219 | if (ih->ring_size) { | |
220 | WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING1, ih->gpu_addr >> 8); | |
221 | WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING1, | |
222 | (ih->gpu_addr >> 40) & 0xff); | |
223 | ||
224 | ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); | |
225 | ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl); | |
226 | ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, | |
227 | WPTR_OVERFLOW_ENABLE, 0); | |
228 | ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, | |
229 | RB_FULL_DRAIN_ENABLE, 1); | |
230 | WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); | |
231 | /* set rptr, wptr to 0 */ | |
232 | WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); | |
233 | WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); | |
234 | ||
235 | WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1, | |
236 | navi10_ih_doorbell_rptr(ih)); | |
237 | } | |
238 | ||
239 | ih = &adev->irq.ih2; | |
240 | if (ih->ring_size) { | |
241 | WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING2, ih->gpu_addr >> 8); | |
242 | WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING2, | |
243 | (ih->gpu_addr >> 40) & 0xff); | |
244 | ||
245 | ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); | |
246 | ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl); | |
247 | ||
248 | WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); | |
249 | /* set rptr, wptr to 0 */ | |
250 | WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0); | |
251 | WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0); | |
252 | ||
253 | WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2, | |
254 | navi10_ih_doorbell_rptr(ih)); | |
255 | } | |
256 | ||
257 | ||
edc61147 HZ |
258 | tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); |
259 | tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, | |
260 | CLIENT18_IS_STORM_CLIENT, 1); | |
261 | WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); | |
262 | ||
263 | tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); | |
264 | tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); | |
265 | WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); | |
266 | ||
267 | pci_set_master(adev->pdev); | |
268 | ||
269 | /* enable interrupts */ | |
270 | navi10_ih_enable_interrupts(adev); | |
271 | ||
7eca4006 | 272 | return 0; |
edc61147 HZ |
273 | } |
274 | ||
275 | /** | |
276 | * navi10_ih_irq_disable - disable interrupts | |
277 | * | |
278 | * @adev: amdgpu_device pointer | |
279 | * | |
280 | * Disable interrupts on the hw (NAVI10). | |
281 | */ | |
282 | static void navi10_ih_irq_disable(struct amdgpu_device *adev) | |
283 | { | |
284 | navi10_ih_disable_interrupts(adev); | |
285 | ||
286 | /* Wait and acknowledge irq */ | |
287 | mdelay(1); | |
288 | } | |
289 | ||
290 | /** | |
291 | * navi10_ih_get_wptr - get the IH ring buffer wptr | |
292 | * | |
293 | * @adev: amdgpu_device pointer | |
294 | * | |
295 | * Get the IH ring buffer wptr from either the register | |
296 | * or the writeback memory buffer (NAVI10). Also check for | |
297 | * ring buffer overflow and deal with it. | |
298 | * Returns the value of the wptr. | |
299 | */ | |
300 | static u32 navi10_ih_get_wptr(struct amdgpu_device *adev, | |
301 | struct amdgpu_ih_ring *ih) | |
302 | { | |
303 | u32 wptr, reg, tmp; | |
304 | ||
305 | wptr = le32_to_cpu(*ih->wptr_cpu); | |
306 | ||
307 | if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) | |
308 | goto out; | |
309 | ||
ab518012 AS |
310 | if (ih == &adev->irq.ih) |
311 | reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); | |
312 | else if (ih == &adev->irq.ih1) | |
313 | reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); | |
314 | else if (ih == &adev->irq.ih2) | |
315 | reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); | |
316 | else | |
317 | BUG(); | |
318 | ||
edc61147 HZ |
319 | wptr = RREG32_NO_KIQ(reg); |
320 | if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) | |
321 | goto out; | |
322 | wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); | |
323 | ||
324 | /* When a ring buffer overflow happen start parsing interrupt | |
325 | * from the last not overwritten vector (wptr + 32). Hopefully | |
326 | * this should allow us to catch up. | |
327 | */ | |
328 | tmp = (wptr + 32) & ih->ptr_mask; | |
329 | dev_warn(adev->dev, "IH ring buffer overflow " | |
330 | "(0x%08X, 0x%08X, 0x%08X)\n", | |
331 | wptr, ih->rptr, tmp); | |
332 | ih->rptr = tmp; | |
333 | ||
ab518012 AS |
334 | if (ih == &adev->irq.ih) |
335 | reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); | |
336 | else if (ih == &adev->irq.ih1) | |
337 | reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); | |
338 | else if (ih == &adev->irq.ih2) | |
339 | reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); | |
340 | else | |
341 | BUG(); | |
342 | ||
edc61147 HZ |
343 | tmp = RREG32_NO_KIQ(reg); |
344 | tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); | |
345 | WREG32_NO_KIQ(reg, tmp); | |
346 | out: | |
347 | return (wptr & ih->ptr_mask); | |
348 | } | |
349 | ||
350 | /** | |
351 | * navi10_ih_decode_iv - decode an interrupt vector | |
352 | * | |
353 | * @adev: amdgpu_device pointer | |
354 | * | |
355 | * Decodes the interrupt vector at the current rptr | |
356 | * position and also advance the position. | |
357 | */ | |
358 | static void navi10_ih_decode_iv(struct amdgpu_device *adev, | |
359 | struct amdgpu_ih_ring *ih, | |
360 | struct amdgpu_iv_entry *entry) | |
361 | { | |
362 | /* wptr/rptr are in bytes! */ | |
363 | u32 ring_index = ih->rptr >> 2; | |
364 | uint32_t dw[8]; | |
365 | ||
366 | dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); | |
367 | dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); | |
368 | dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); | |
369 | dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); | |
370 | dw[4] = le32_to_cpu(ih->ring[ring_index + 4]); | |
371 | dw[5] = le32_to_cpu(ih->ring[ring_index + 5]); | |
372 | dw[6] = le32_to_cpu(ih->ring[ring_index + 6]); | |
373 | dw[7] = le32_to_cpu(ih->ring[ring_index + 7]); | |
374 | ||
375 | entry->client_id = dw[0] & 0xff; | |
376 | entry->src_id = (dw[0] >> 8) & 0xff; | |
377 | entry->ring_id = (dw[0] >> 16) & 0xff; | |
378 | entry->vmid = (dw[0] >> 24) & 0xf; | |
379 | entry->vmid_src = (dw[0] >> 31); | |
380 | entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32); | |
381 | entry->timestamp_src = dw[2] >> 31; | |
382 | entry->pasid = dw[3] & 0xffff; | |
383 | entry->pasid_src = dw[3] >> 31; | |
384 | entry->src_data[0] = dw[4]; | |
385 | entry->src_data[1] = dw[5]; | |
386 | entry->src_data[2] = dw[6]; | |
387 | entry->src_data[3] = dw[7]; | |
388 | ||
389 | /* wptr/rptr are in bytes! */ | |
390 | ih->rptr += 32; | |
391 | } | |
392 | ||
022b6518 SD |
393 | /** |
394 | * navi10_ih_irq_rearm - rearm IRQ if lost | |
395 | * | |
396 | * @adev: amdgpu_device pointer | |
397 | * | |
398 | */ | |
399 | static void navi10_ih_irq_rearm(struct amdgpu_device *adev, | |
400 | struct amdgpu_ih_ring *ih) | |
401 | { | |
402 | uint32_t reg_rptr = 0; | |
403 | uint32_t v = 0; | |
404 | uint32_t i = 0; | |
405 | ||
406 | if (ih == &adev->irq.ih) | |
407 | reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); | |
408 | else if (ih == &adev->irq.ih1) | |
409 | reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); | |
410 | else if (ih == &adev->irq.ih2) | |
411 | reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); | |
412 | else | |
413 | return; | |
414 | ||
415 | /* Rearm IRQ / re-write doorbell if doorbell write is lost */ | |
416 | for (i = 0; i < MAX_REARM_RETRY; i++) { | |
417 | v = RREG32_NO_KIQ(reg_rptr); | |
418 | if ((v < ih->ring_size) && (v != ih->rptr)) | |
419 | WDOORBELL32(ih->doorbell_index, ih->rptr); | |
420 | else | |
421 | break; | |
422 | } | |
423 | } | |
424 | ||
edc61147 HZ |
425 | /** |
426 | * navi10_ih_set_rptr - set the IH ring buffer rptr | |
427 | * | |
428 | * @adev: amdgpu_device pointer | |
429 | * | |
430 | * Set the IH ring buffer rptr. | |
431 | */ | |
432 | static void navi10_ih_set_rptr(struct amdgpu_device *adev, | |
433 | struct amdgpu_ih_ring *ih) | |
434 | { | |
435 | if (ih->use_doorbell) { | |
436 | /* XXX check if swapping is necessary on BE */ | |
437 | *ih->rptr_cpu = ih->rptr; | |
438 | WDOORBELL32(ih->doorbell_index, ih->rptr); | |
022b6518 SD |
439 | |
440 | if (amdgpu_sriov_vf(adev)) | |
441 | navi10_ih_irq_rearm(adev, ih); | |
ab518012 | 442 | } else if (ih == &adev->irq.ih) { |
edc61147 | 443 | WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr); |
ab518012 AS |
444 | } else if (ih == &adev->irq.ih1) { |
445 | WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, ih->rptr); | |
446 | } else if (ih == &adev->irq.ih2) { | |
447 | WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, ih->rptr); | |
448 | } | |
449 | } | |
450 | ||
451 | /** | |
452 | * navi10_ih_self_irq - dispatch work for ring 1 and 2 | |
453 | * | |
454 | * @adev: amdgpu_device pointer | |
455 | * @source: irq source | |
456 | * @entry: IV with WPTR update | |
457 | * | |
458 | * Update the WPTR from the IV and schedule work to handle the entries. | |
459 | */ | |
460 | static int navi10_ih_self_irq(struct amdgpu_device *adev, | |
461 | struct amdgpu_irq_src *source, | |
462 | struct amdgpu_iv_entry *entry) | |
463 | { | |
464 | uint32_t wptr = cpu_to_le32(entry->src_data[0]); | |
465 | ||
466 | switch (entry->ring_id) { | |
467 | case 1: | |
468 | *adev->irq.ih1.wptr_cpu = wptr; | |
469 | schedule_work(&adev->irq.ih1_work); | |
470 | break; | |
471 | case 2: | |
472 | *adev->irq.ih2.wptr_cpu = wptr; | |
473 | schedule_work(&adev->irq.ih2_work); | |
474 | break; | |
475 | default: break; | |
476 | } | |
477 | return 0; | |
478 | } | |
479 | ||
480 | static const struct amdgpu_irq_src_funcs navi10_ih_self_irq_funcs = { | |
481 | .process = navi10_ih_self_irq, | |
482 | }; | |
483 | ||
484 | static void navi10_ih_set_self_irq_funcs(struct amdgpu_device *adev) | |
485 | { | |
486 | adev->irq.self_irq.num_types = 0; | |
487 | adev->irq.self_irq.funcs = &navi10_ih_self_irq_funcs; | |
edc61147 HZ |
488 | } |
489 | ||
490 | static int navi10_ih_early_init(void *handle) | |
491 | { | |
492 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
493 | ||
494 | navi10_ih_set_interrupt_funcs(adev); | |
ab518012 | 495 | navi10_ih_set_self_irq_funcs(adev); |
edc61147 HZ |
496 | return 0; |
497 | } | |
498 | ||
499 | static int navi10_ih_sw_init(void *handle) | |
500 | { | |
501 | int r; | |
502 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
503 | bool use_bus_addr; | |
504 | ||
ab518012 AS |
505 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, |
506 | &adev->irq.self_irq); | |
507 | ||
508 | if (r) | |
509 | return r; | |
510 | ||
edc61147 HZ |
511 | /* use gpu virtual address for ih ring |
512 | * until ih_checken is programmed to allow | |
513 | * use bus address for ih ring by psp bl */ | |
514 | use_bus_addr = | |
515 | (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) ? false : true; | |
516 | r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr); | |
517 | if (r) | |
518 | return r; | |
519 | ||
520 | adev->irq.ih.use_doorbell = true; | |
521 | adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; | |
522 | ||
ab518012 AS |
523 | r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true); |
524 | if (r) | |
525 | return r; | |
526 | ||
527 | adev->irq.ih1.use_doorbell = true; | |
528 | adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1; | |
529 | ||
530 | r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true); | |
531 | if (r) | |
532 | return r; | |
533 | ||
534 | adev->irq.ih2.use_doorbell = true; | |
535 | adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1; | |
536 | ||
edc61147 HZ |
537 | r = amdgpu_irq_init(adev); |
538 | ||
539 | return r; | |
540 | } | |
541 | ||
542 | static int navi10_ih_sw_fini(void *handle) | |
543 | { | |
544 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
545 | ||
546 | amdgpu_irq_fini(adev); | |
ab518012 AS |
547 | amdgpu_ih_ring_fini(adev, &adev->irq.ih2); |
548 | amdgpu_ih_ring_fini(adev, &adev->irq.ih1); | |
edc61147 HZ |
549 | amdgpu_ih_ring_fini(adev, &adev->irq.ih); |
550 | ||
551 | return 0; | |
552 | } | |
553 | ||
554 | static int navi10_ih_hw_init(void *handle) | |
555 | { | |
556 | int r; | |
557 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
558 | ||
559 | r = navi10_ih_irq_init(adev); | |
560 | if (r) | |
561 | return r; | |
562 | ||
563 | return 0; | |
564 | } | |
565 | ||
566 | static int navi10_ih_hw_fini(void *handle) | |
567 | { | |
568 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
569 | ||
570 | navi10_ih_irq_disable(adev); | |
571 | ||
572 | return 0; | |
573 | } | |
574 | ||
575 | static int navi10_ih_suspend(void *handle) | |
576 | { | |
577 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
578 | ||
579 | return navi10_ih_hw_fini(adev); | |
580 | } | |
581 | ||
582 | static int navi10_ih_resume(void *handle) | |
583 | { | |
584 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
585 | ||
586 | return navi10_ih_hw_init(adev); | |
587 | } | |
588 | ||
589 | static bool navi10_ih_is_idle(void *handle) | |
590 | { | |
591 | /* todo */ | |
592 | return true; | |
593 | } | |
594 | ||
595 | static int navi10_ih_wait_for_idle(void *handle) | |
596 | { | |
597 | /* todo */ | |
598 | return -ETIMEDOUT; | |
599 | } | |
600 | ||
601 | static int navi10_ih_soft_reset(void *handle) | |
602 | { | |
603 | /* todo */ | |
604 | return 0; | |
605 | } | |
606 | ||
607 | static void navi10_ih_update_clockgating_state(struct amdgpu_device *adev, | |
608 | bool enable) | |
609 | { | |
610 | uint32_t data, def, field_val; | |
611 | ||
612 | if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { | |
613 | def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL); | |
614 | field_val = enable ? 0 : 1; | |
615 | data = REG_SET_FIELD(data, IH_CLK_CTRL, | |
616 | DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); | |
617 | data = REG_SET_FIELD(data, IH_CLK_CTRL, | |
618 | OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); | |
619 | data = REG_SET_FIELD(data, IH_CLK_CTRL, | |
620 | LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); | |
621 | data = REG_SET_FIELD(data, IH_CLK_CTRL, | |
622 | DYN_CLK_SOFT_OVERRIDE, field_val); | |
623 | data = REG_SET_FIELD(data, IH_CLK_CTRL, | |
624 | REG_CLK_SOFT_OVERRIDE, field_val); | |
625 | if (def != data) | |
626 | WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data); | |
627 | } | |
628 | ||
629 | return; | |
630 | } | |
631 | ||
632 | static int navi10_ih_set_clockgating_state(void *handle, | |
633 | enum amd_clockgating_state state) | |
634 | { | |
635 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
636 | ||
637 | navi10_ih_update_clockgating_state(adev, | |
a9d4fe2f | 638 | state == AMD_CG_STATE_GATE); |
edc61147 HZ |
639 | return 0; |
640 | } | |
641 | ||
642 | static int navi10_ih_set_powergating_state(void *handle, | |
643 | enum amd_powergating_state state) | |
644 | { | |
645 | return 0; | |
646 | } | |
647 | ||
648 | static void navi10_ih_get_clockgating_state(void *handle, u32 *flags) | |
649 | { | |
650 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
651 | ||
652 | if (!RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL)) | |
653 | *flags |= AMD_CG_SUPPORT_IH_CG; | |
654 | ||
655 | return; | |
656 | } | |
657 | ||
658 | static const struct amd_ip_funcs navi10_ih_ip_funcs = { | |
659 | .name = "navi10_ih", | |
660 | .early_init = navi10_ih_early_init, | |
661 | .late_init = NULL, | |
662 | .sw_init = navi10_ih_sw_init, | |
663 | .sw_fini = navi10_ih_sw_fini, | |
664 | .hw_init = navi10_ih_hw_init, | |
665 | .hw_fini = navi10_ih_hw_fini, | |
666 | .suspend = navi10_ih_suspend, | |
667 | .resume = navi10_ih_resume, | |
668 | .is_idle = navi10_ih_is_idle, | |
669 | .wait_for_idle = navi10_ih_wait_for_idle, | |
670 | .soft_reset = navi10_ih_soft_reset, | |
671 | .set_clockgating_state = navi10_ih_set_clockgating_state, | |
672 | .set_powergating_state = navi10_ih_set_powergating_state, | |
673 | .get_clockgating_state = navi10_ih_get_clockgating_state, | |
674 | }; | |
675 | ||
676 | static const struct amdgpu_ih_funcs navi10_ih_funcs = { | |
677 | .get_wptr = navi10_ih_get_wptr, | |
678 | .decode_iv = navi10_ih_decode_iv, | |
679 | .set_rptr = navi10_ih_set_rptr | |
680 | }; | |
681 | ||
682 | static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev) | |
683 | { | |
684 | if (adev->irq.ih_funcs == NULL) | |
685 | adev->irq.ih_funcs = &navi10_ih_funcs; | |
686 | } | |
687 | ||
688 | const struct amdgpu_ip_block_version navi10_ih_ip_block = | |
689 | { | |
690 | .type = AMD_IP_BLOCK_TYPE_IH, | |
691 | .major = 5, | |
692 | .minor = 0, | |
693 | .rev = 0, | |
694 | .funcs = &navi10_ih_ip_funcs, | |
695 | }; |