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1 | /* |
2 | * Copyright 2016 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | */ | |
23 | ||
24 | #ifndef __NBIO_V6_1_H__ | |
25 | #define __NBIO_V6_1_H__ | |
26 | ||
27 | #include "soc15_common.h" | |
28 | ||
29 | extern struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg; | |
30 | extern struct nbio_pcie_index_data nbio_v6_1_pcie_index_data; | |
31 | int nbio_v6_1_init(struct amdgpu_device *adev); | |
32 | u32 nbio_v6_1_get_atombios_scratch_regs(struct amdgpu_device *adev, | |
33 | uint32_t idx); | |
34 | void nbio_v6_1_set_atombios_scratch_regs(struct amdgpu_device *adev, | |
35 | uint32_t idx, uint32_t val); | |
36 | void nbio_v6_1_mc_access_enable(struct amdgpu_device *adev, bool enable); | |
37 | void nbio_v6_1_hdp_flush(struct amdgpu_device *adev); | |
38 | u32 nbio_v6_1_get_memsize(struct amdgpu_device *adev); | |
39 | void nbio_v6_1_sdma_doorbell_range(struct amdgpu_device *adev, int instance, | |
40 | bool use_doorbell, int doorbell_index); | |
41 | void nbio_v6_1_enable_doorbell_aperture(struct amdgpu_device *adev, | |
42 | bool enable); | |
43 | void nbio_v6_1_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, | |
44 | bool enable); | |
45 | void nbio_v6_1_ih_doorbell_range(struct amdgpu_device *adev, | |
46 | bool use_doorbell, int doorbell_index); | |
47 | void nbio_v6_1_ih_control(struct amdgpu_device *adev); | |
48 | u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev); | |
49 | void nbio_v6_1_update_medium_grain_clock_gating(struct amdgpu_device *adev, bool enable); | |
50 | void nbio_v6_1_update_medium_grain_light_sleep(struct amdgpu_device *adev, bool enable); | |
e96487a6 | 51 | void nbio_v6_1_get_clockgating_state(struct amdgpu_device *adev, u32 *flags); |
1b922423 | 52 | void nbio_v6_1_detect_hw_virt(struct amdgpu_device *adev); |
c1d83da9 JZ |
53 | |
54 | #endif |