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drm/amdgpu: add VEGAM SDMA firmware support
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / amdgpu / sdma_v3_0.c
CommitLineData
aaa36a97
AD
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#include <linux/firmware.h>
25#include <drm/drmP.h>
26#include "amdgpu.h"
27#include "amdgpu_ucode.h"
28#include "amdgpu_trace.h"
29#include "vi.h"
30#include "vid.h"
31
32#include "oss/oss_3_0_d.h"
33#include "oss/oss_3_0_sh_mask.h"
34
35#include "gmc/gmc_8_1_d.h"
36#include "gmc/gmc_8_1_sh_mask.h"
37
38#include "gca/gfx_8_0_d.h"
74a5d165 39#include "gca/gfx_8_0_enum.h"
aaa36a97
AD
40#include "gca/gfx_8_0_sh_mask.h"
41
42#include "bif/bif_5_0_d.h"
43#include "bif/bif_5_0_sh_mask.h"
44
45#include "tonga_sdma_pkt_open.h"
46
47static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev);
48static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev);
49static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev);
50static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev);
51
c65444fe
JZ
52MODULE_FIRMWARE("amdgpu/tonga_sdma.bin");
53MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin");
54MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin");
55MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin");
1a5bbb66
DZ
56MODULE_FIRMWARE("amdgpu/fiji_sdma.bin");
57MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin");
bb16e3b6 58MODULE_FIRMWARE("amdgpu/stoney_sdma.bin");
2cc0c0b5
FC
59MODULE_FIRMWARE("amdgpu/polaris10_sdma.bin");
60MODULE_FIRMWARE("amdgpu/polaris10_sdma1.bin");
61MODULE_FIRMWARE("amdgpu/polaris11_sdma.bin");
62MODULE_FIRMWARE("amdgpu/polaris11_sdma1.bin");
c4642a47
JZ
63MODULE_FIRMWARE("amdgpu/polaris12_sdma.bin");
64MODULE_FIRMWARE("amdgpu/polaris12_sdma1.bin");
2267e262
LL
65MODULE_FIRMWARE("amdgpu/vegam_sdma.bin");
66MODULE_FIRMWARE("amdgpu/vegam_sdma1.bin");
2cea03de 67
aaa36a97
AD
68
69static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
70{
71 SDMA0_REGISTER_OFFSET,
72 SDMA1_REGISTER_OFFSET
73};
74
75static const u32 golden_settings_tonga_a11[] =
76{
77 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
78 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
79 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
80 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
81 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
82 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
83 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
84 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
85 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
86 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
87};
88
89static const u32 tonga_mgcg_cgcg_init[] =
90{
91 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
92 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
93};
94
1a5bbb66
DZ
95static const u32 golden_settings_fiji_a10[] =
96{
97 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
98 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
99 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
100 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
101 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
102 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
103 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
104 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
105};
106
107static const u32 fiji_mgcg_cgcg_init[] =
108{
109 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
110 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
111};
112
2cc0c0b5 113static const u32 golden_settings_polaris11_a11[] =
2cea03de
FC
114{
115 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
b9934878 116 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
2cea03de
FC
117 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
118 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
119 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
120 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
b9934878 121 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
2cea03de
FC
122 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
123 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
124 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
125};
126
2cc0c0b5 127static const u32 golden_settings_polaris10_a11[] =
2cea03de
FC
128{
129 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
130 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
131 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
132 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
133 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
134 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
135 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
136 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
137 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
138 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
139};
140
aaa36a97
AD
141static const u32 cz_golden_settings_a11[] =
142{
143 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
144 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
145 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
146 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
147 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
148 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
149 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
150 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
151 mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100,
152 mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800,
153 mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100,
154 mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100,
155};
156
157static const u32 cz_mgcg_cgcg_init[] =
158{
159 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
160 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
161};
162
bb16e3b6
SL
163static const u32 stoney_golden_settings_a11[] =
164{
165 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
166 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
167 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
168 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
169};
170
171static const u32 stoney_mgcg_cgcg_init[] =
172{
173 mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100,
174};
175
aaa36a97
AD
176/*
177 * sDMA - System DMA
178 * Starting with CIK, the GPU has new asynchronous
179 * DMA engines. These engines are used for compute
180 * and gfx. There are two DMA engines (SDMA0, SDMA1)
181 * and each one supports 1 ring buffer used for gfx
182 * and 2 queues used for compute.
183 *
184 * The programming model is very similar to the CP
185 * (ring buffer, IBs, etc.), but sDMA has it's own
186 * packet format that is different from the PM4 format
187 * used by the CP. sDMA supports copying data, writing
188 * embedded data, solid fills, and a number of other
189 * things. It also has support for tiling/detiling of
190 * buffers.
191 */
192
193static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev)
194{
195 switch (adev->asic_type) {
1a5bbb66 196 case CHIP_FIJI:
9c3f2b54
AD
197 amdgpu_device_program_register_sequence(adev,
198 fiji_mgcg_cgcg_init,
199 ARRAY_SIZE(fiji_mgcg_cgcg_init));
200 amdgpu_device_program_register_sequence(adev,
201 golden_settings_fiji_a10,
202 ARRAY_SIZE(golden_settings_fiji_a10));
1a5bbb66 203 break;
aaa36a97 204 case CHIP_TONGA:
9c3f2b54
AD
205 amdgpu_device_program_register_sequence(adev,
206 tonga_mgcg_cgcg_init,
207 ARRAY_SIZE(tonga_mgcg_cgcg_init));
208 amdgpu_device_program_register_sequence(adev,
209 golden_settings_tonga_a11,
210 ARRAY_SIZE(golden_settings_tonga_a11));
aaa36a97 211 break;
2cc0c0b5 212 case CHIP_POLARIS11:
c4642a47 213 case CHIP_POLARIS12:
9c3f2b54
AD
214 amdgpu_device_program_register_sequence(adev,
215 golden_settings_polaris11_a11,
216 ARRAY_SIZE(golden_settings_polaris11_a11));
2cea03de 217 break;
2cc0c0b5 218 case CHIP_POLARIS10:
9c3f2b54
AD
219 amdgpu_device_program_register_sequence(adev,
220 golden_settings_polaris10_a11,
221 ARRAY_SIZE(golden_settings_polaris10_a11));
2cea03de 222 break;
aaa36a97 223 case CHIP_CARRIZO:
9c3f2b54
AD
224 amdgpu_device_program_register_sequence(adev,
225 cz_mgcg_cgcg_init,
226 ARRAY_SIZE(cz_mgcg_cgcg_init));
227 amdgpu_device_program_register_sequence(adev,
228 cz_golden_settings_a11,
229 ARRAY_SIZE(cz_golden_settings_a11));
aaa36a97 230 break;
bb16e3b6 231 case CHIP_STONEY:
9c3f2b54
AD
232 amdgpu_device_program_register_sequence(adev,
233 stoney_mgcg_cgcg_init,
234 ARRAY_SIZE(stoney_mgcg_cgcg_init));
235 amdgpu_device_program_register_sequence(adev,
236 stoney_golden_settings_a11,
237 ARRAY_SIZE(stoney_golden_settings_a11));
bb16e3b6 238 break;
aaa36a97
AD
239 default:
240 break;
241 }
242}
243
14d83e78
ML
244static void sdma_v3_0_free_microcode(struct amdgpu_device *adev)
245{
246 int i;
247 for (i = 0; i < adev->sdma.num_instances; i++) {
248 release_firmware(adev->sdma.instance[i].fw);
249 adev->sdma.instance[i].fw = NULL;
250 }
251}
252
aaa36a97
AD
253/**
254 * sdma_v3_0_init_microcode - load ucode images from disk
255 *
256 * @adev: amdgpu_device pointer
257 *
258 * Use the firmware interface to load the ucode images into
259 * the driver (not loaded into hw).
260 * Returns 0 on success, error on failure.
261 */
262static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)
263{
264 const char *chip_name;
265 char fw_name[30];
c113ea1c 266 int err = 0, i;
aaa36a97
AD
267 struct amdgpu_firmware_info *info = NULL;
268 const struct common_firmware_header *header = NULL;
595fd013 269 const struct sdma_firmware_header_v1_0 *hdr;
aaa36a97
AD
270
271 DRM_DEBUG("\n");
272
273 switch (adev->asic_type) {
274 case CHIP_TONGA:
275 chip_name = "tonga";
276 break;
1a5bbb66
DZ
277 case CHIP_FIJI:
278 chip_name = "fiji";
279 break;
2cc0c0b5
FC
280 case CHIP_POLARIS10:
281 chip_name = "polaris10";
2cea03de 282 break;
2267e262
LL
283 case CHIP_POLARIS11:
284 chip_name = "polaris11";
285 break;
c4642a47
JZ
286 case CHIP_POLARIS12:
287 chip_name = "polaris12";
288 break;
2267e262
LL
289 case CHIP_VEGAM:
290 chip_name = "vegam";
291 break;
aaa36a97
AD
292 case CHIP_CARRIZO:
293 chip_name = "carrizo";
294 break;
bb16e3b6
SL
295 case CHIP_STONEY:
296 chip_name = "stoney";
297 break;
aaa36a97
AD
298 default: BUG();
299 }
300
c113ea1c 301 for (i = 0; i < adev->sdma.num_instances; i++) {
aaa36a97 302 if (i == 0)
c65444fe 303 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
aaa36a97 304 else
c65444fe 305 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
c113ea1c 306 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
aaa36a97
AD
307 if (err)
308 goto out;
c113ea1c 309 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
aaa36a97
AD
310 if (err)
311 goto out;
c113ea1c
AD
312 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
313 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
314 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
315 if (adev->sdma.instance[i].feature_version >= 20)
316 adev->sdma.instance[i].burst_nop = true;
aaa36a97 317
e635ee07 318 if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) {
aaa36a97
AD
319 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
320 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
c113ea1c 321 info->fw = adev->sdma.instance[i].fw;
aaa36a97
AD
322 header = (const struct common_firmware_header *)info->fw->data;
323 adev->firmware.fw_size +=
324 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
325 }
326 }
327out:
328 if (err) {
7ca85295 329 pr_err("sdma_v3_0: Failed to load firmware \"%s\"\n", fw_name);
c113ea1c
AD
330 for (i = 0; i < adev->sdma.num_instances; i++) {
331 release_firmware(adev->sdma.instance[i].fw);
332 adev->sdma.instance[i].fw = NULL;
aaa36a97
AD
333 }
334 }
335 return err;
336}
337
338/**
339 * sdma_v3_0_ring_get_rptr - get the current read pointer
340 *
341 * @ring: amdgpu ring pointer
342 *
343 * Get the current rptr from the hardware (VI+).
344 */
536fbf94 345static uint64_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
aaa36a97 346{
aaa36a97 347 /* XXX check if swapping is necessary on BE */
d912adef 348 return ring->adev->wb.wb[ring->rptr_offs] >> 2;
aaa36a97
AD
349}
350
351/**
352 * sdma_v3_0_ring_get_wptr - get the current write pointer
353 *
354 * @ring: amdgpu ring pointer
355 *
356 * Get the current wptr from the hardware (VI+).
357 */
536fbf94 358static uint64_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
aaa36a97
AD
359{
360 struct amdgpu_device *adev = ring->adev;
361 u32 wptr;
362
2ffe31de 363 if (ring->use_doorbell || ring->use_pollmem) {
aaa36a97
AD
364 /* XXX check if swapping is necessary on BE */
365 wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2;
366 } else {
c113ea1c 367 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
aaa36a97
AD
368
369 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
370 }
371
372 return wptr;
373}
374
375/**
376 * sdma_v3_0_ring_set_wptr - commit the write pointer
377 *
378 * @ring: amdgpu ring pointer
379 *
380 * Write the wptr back to the hardware (VI+).
381 */
382static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
383{
384 struct amdgpu_device *adev = ring->adev;
385
386 if (ring->use_doorbell) {
3e4b0bd9 387 u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs];
aaa36a97 388 /* XXX check if swapping is necessary on BE */
3e4b0bd9 389 WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2));
536fbf94 390 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr) << 2);
2ffe31de
PD
391 } else if (ring->use_pollmem) {
392 u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs];
393
394 WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2));
aaa36a97 395 } else {
c113ea1c 396 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
aaa36a97 397
536fbf94 398 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], lower_32_bits(ring->wptr) << 2);
aaa36a97
AD
399 }
400}
401
ac01db3d
JZ
402static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
403{
c113ea1c 404 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
ac01db3d
JZ
405 int i;
406
407 for (i = 0; i < count; i++)
408 if (sdma && sdma->burst_nop && (i == 0))
79887142 409 amdgpu_ring_write(ring, ring->funcs->nop |
ac01db3d
JZ
410 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
411 else
79887142 412 amdgpu_ring_write(ring, ring->funcs->nop);
ac01db3d
JZ
413}
414
aaa36a97
AD
415/**
416 * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine
417 *
418 * @ring: amdgpu ring pointer
419 * @ib: IB object to schedule
420 *
421 * Schedule an IB in the DMA ring (VI).
422 */
423static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
d88bf583 424 struct amdgpu_ib *ib,
c4f46f22 425 unsigned vmid, bool ctx_switch)
aaa36a97 426{
aaa36a97 427 /* IB packet must end on a 8 DW boundary */
536fbf94 428 sdma_v3_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8);
aaa36a97
AD
429
430 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
c4f46f22 431 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
aaa36a97
AD
432 /* base must be 32 byte aligned */
433 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
434 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
435 amdgpu_ring_write(ring, ib->length_dw);
436 amdgpu_ring_write(ring, 0);
437 amdgpu_ring_write(ring, 0);
438
439}
440
441/**
d2edb07b 442 * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
aaa36a97
AD
443 *
444 * @ring: amdgpu ring pointer
445 *
446 * Emit an hdp flush packet on the requested DMA ring.
447 */
d2edb07b 448static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
aaa36a97
AD
449{
450 u32 ref_and_mask = 0;
451
c113ea1c 452 if (ring == &ring->adev->sdma.instance[0].ring)
aaa36a97
AD
453 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
454 else
455 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
456
457 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
458 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
459 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
460 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
461 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
462 amdgpu_ring_write(ring, ref_and_mask); /* reference */
463 amdgpu_ring_write(ring, ref_and_mask); /* mask */
464 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
465 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
466}
467
468/**
469 * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring
470 *
471 * @ring: amdgpu ring pointer
472 * @fence: amdgpu fence object
473 *
474 * Add a DMA fence packet to the ring to write
475 * the fence seq number and DMA trap packet to generate
476 * an interrupt if needed (VI).
477 */
478static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
890ee23f 479 unsigned flags)
aaa36a97 480{
890ee23f 481 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
aaa36a97
AD
482 /* write the fence */
483 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
484 amdgpu_ring_write(ring, lower_32_bits(addr));
485 amdgpu_ring_write(ring, upper_32_bits(addr));
486 amdgpu_ring_write(ring, lower_32_bits(seq));
487
488 /* optionally write high bits as well */
890ee23f 489 if (write64bit) {
aaa36a97
AD
490 addr += 4;
491 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
492 amdgpu_ring_write(ring, lower_32_bits(addr));
493 amdgpu_ring_write(ring, upper_32_bits(addr));
494 amdgpu_ring_write(ring, upper_32_bits(seq));
495 }
496
497 /* generate an interrupt */
498 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
499 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
500}
501
aaa36a97
AD
502/**
503 * sdma_v3_0_gfx_stop - stop the gfx async dma engines
504 *
505 * @adev: amdgpu_device pointer
506 *
507 * Stop the gfx async dma ring buffers (VI).
508 */
509static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev)
510{
c113ea1c
AD
511 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
512 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
aaa36a97
AD
513 u32 rb_cntl, ib_cntl;
514 int i;
515
516 if ((adev->mman.buffer_funcs_ring == sdma0) ||
517 (adev->mman.buffer_funcs_ring == sdma1))
57adc4ce 518 amdgpu_ttm_set_buffer_funcs_status(adev, false);
aaa36a97 519
c113ea1c 520 for (i = 0; i < adev->sdma.num_instances; i++) {
aaa36a97
AD
521 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
522 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
523 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
524 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
525 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
526 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
527 }
528 sdma0->ready = false;
529 sdma1->ready = false;
530}
531
532/**
533 * sdma_v3_0_rlc_stop - stop the compute async dma engines
534 *
535 * @adev: amdgpu_device pointer
536 *
537 * Stop the compute async dma queues (VI).
538 */
539static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev)
540{
541 /* XXX todo */
542}
543
cd06bf68
BG
544/**
545 * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch
546 *
547 * @adev: amdgpu_device pointer
548 * @enable: enable/disable the DMA MEs context switch.
549 *
550 * Halt or unhalt the async dma engines context switch (VI).
551 */
552static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
553{
a667386c 554 u32 f32_cntl, phase_quantum = 0;
cd06bf68
BG
555 int i;
556
a667386c
FK
557 if (amdgpu_sdma_phase_quantum) {
558 unsigned value = amdgpu_sdma_phase_quantum;
559 unsigned unit = 0;
560
561 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
562 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
563 value = (value + 1) >> 1;
564 unit++;
565 }
566 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
567 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
568 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
569 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
570 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
571 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
572 WARN_ONCE(1,
573 "clamping sdma_phase_quantum to %uK clock cycles\n",
574 value << unit);
575 }
576 phase_quantum =
577 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
578 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
579 }
580
c113ea1c 581 for (i = 0; i < adev->sdma.num_instances; i++) {
cd06bf68 582 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
4048f0f0 583 if (enable) {
cd06bf68
BG
584 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
585 AUTO_CTXSW_ENABLE, 1);
4048f0f0 586 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
587 ATC_L1_ENABLE, 1);
a667386c
FK
588 if (amdgpu_sdma_phase_quantum) {
589 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i],
590 phase_quantum);
591 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i],
592 phase_quantum);
593 }
4048f0f0 594 } else {
cd06bf68
BG
595 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
596 AUTO_CTXSW_ENABLE, 0);
4048f0f0 597 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
598 ATC_L1_ENABLE, 1);
599 }
600
cd06bf68
BG
601 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
602 }
603}
604
aaa36a97
AD
605/**
606 * sdma_v3_0_enable - stop the async dma engines
607 *
608 * @adev: amdgpu_device pointer
609 * @enable: enable/disable the DMA MEs.
610 *
611 * Halt or unhalt the async dma engines (VI).
612 */
613static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable)
614{
615 u32 f32_cntl;
616 int i;
617
004e29cc 618 if (!enable) {
aaa36a97
AD
619 sdma_v3_0_gfx_stop(adev);
620 sdma_v3_0_rlc_stop(adev);
621 }
622
c113ea1c 623 for (i = 0; i < adev->sdma.num_instances; i++) {
aaa36a97
AD
624 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
625 if (enable)
626 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
627 else
628 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
629 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
630 }
631}
632
633/**
634 * sdma_v3_0_gfx_resume - setup and start the async dma engines
635 *
636 * @adev: amdgpu_device pointer
637 *
638 * Set up the gfx DMA ring buffers and enable them (VI).
639 * Returns 0 for success, error for failure.
640 */
641static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
642{
643 struct amdgpu_ring *ring;
e33dac39 644 u32 rb_cntl, ib_cntl, wptr_poll_cntl;
aaa36a97
AD
645 u32 rb_bufsz;
646 u32 wb_offset;
647 u32 doorbell;
e33dac39 648 u64 wptr_gpu_addr;
aaa36a97
AD
649 int i, j, r;
650
c113ea1c
AD
651 for (i = 0; i < adev->sdma.num_instances; i++) {
652 ring = &adev->sdma.instance[i].ring;
f6bd7942 653 amdgpu_ring_clear_ring(ring);
aaa36a97
AD
654 wb_offset = (ring->rptr_offs * 4);
655
656 mutex_lock(&adev->srbm_mutex);
657 for (j = 0; j < 16; j++) {
658 vi_srbm_select(adev, 0, 0, 0, j);
659 /* SDMA GFX */
660 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
661 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
662 }
663 vi_srbm_select(adev, 0, 0, 0, 0);
664 mutex_unlock(&adev->srbm_mutex);
665
c458fe94
AD
666 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
667 adev->gfx.config.gb_addr_config & 0x70);
668
aaa36a97
AD
669 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
670
671 /* Set ring buffer size in dwords */
672 rb_bufsz = order_base_2(ring->ring_size / 4);
673 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
674 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
675#ifdef __BIG_ENDIAN
676 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
677 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
678 RPTR_WRITEBACK_SWAP_ENABLE, 1);
679#endif
680 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
681
682 /* Initialize the ring buffer's read and write pointers */
78cb9083 683 ring->wptr = 0;
aaa36a97 684 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
78cb9083 685 sdma_v3_0_ring_set_wptr(ring);
d72f7c06
ML
686 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
687 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
aaa36a97
AD
688
689 /* set the wb address whether it's enabled or not */
690 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
691 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
692 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
693 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
694
695 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
696
697 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
698 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
699
aaa36a97
AD
700 doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]);
701
702 if (ring->use_doorbell) {
703 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL,
704 OFFSET, ring->doorbell_index);
705 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
706 } else {
707 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
708 }
709 WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell);
710
e33dac39
XY
711 /* setup the wptr shadow polling */
712 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
713
714 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO + sdma_offsets[i],
715 lower_32_bits(wptr_gpu_addr));
716 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i],
717 upper_32_bits(wptr_gpu_addr));
718 wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]);
4062119b
ED
719 if (ring->use_pollmem) {
720 /*wptr polling is not enogh fast, directly clean the wptr register */
721 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
2ffe31de
PD
722 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
723 SDMA0_GFX_RB_WPTR_POLL_CNTL,
724 ENABLE, 1);
4062119b 725 } else {
2ffe31de
PD
726 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
727 SDMA0_GFX_RB_WPTR_POLL_CNTL,
728 ENABLE, 0);
4062119b 729 }
e33dac39
XY
730 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i], wptr_poll_cntl);
731
aaa36a97
AD
732 /* enable DMA RB */
733 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
734 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
735
736 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
737 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
738#ifdef __BIG_ENDIAN
739 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
740#endif
741 /* enable DMA IBs */
742 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
743
744 ring->ready = true;
505dfe76 745 }
aaa36a97 746
505dfe76
ML
747 /* unhalt the MEs */
748 sdma_v3_0_enable(adev, true);
749 /* enable sdma ring preemption */
750 sdma_v3_0_ctx_switch_enable(adev, true);
751
752 for (i = 0; i < adev->sdma.num_instances; i++) {
753 ring = &adev->sdma.instance[i].ring;
aaa36a97
AD
754 r = amdgpu_ring_test_ring(ring);
755 if (r) {
756 ring->ready = false;
757 return r;
758 }
759
760 if (adev->mman.buffer_funcs_ring == ring)
57adc4ce 761 amdgpu_ttm_set_buffer_funcs_status(adev, true);
aaa36a97
AD
762 }
763
764 return 0;
765}
766
767/**
768 * sdma_v3_0_rlc_resume - setup and start the async dma engines
769 *
770 * @adev: amdgpu_device pointer
771 *
772 * Set up the compute DMA queues and enable them (VI).
773 * Returns 0 for success, error for failure.
774 */
775static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev)
776{
777 /* XXX todo */
778 return 0;
779}
780
781/**
782 * sdma_v3_0_load_microcode - load the sDMA ME ucode
783 *
784 * @adev: amdgpu_device pointer
785 *
786 * Loads the sDMA0/1 ucode.
787 * Returns 0 for success, -EINVAL if the ucode is not available.
788 */
789static int sdma_v3_0_load_microcode(struct amdgpu_device *adev)
790{
791 const struct sdma_firmware_header_v1_0 *hdr;
792 const __le32 *fw_data;
793 u32 fw_size;
794 int i, j;
795
aaa36a97
AD
796 /* halt the MEs */
797 sdma_v3_0_enable(adev, false);
798
c113ea1c
AD
799 for (i = 0; i < adev->sdma.num_instances; i++) {
800 if (!adev->sdma.instance[i].fw)
801 return -EINVAL;
802 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
aaa36a97
AD
803 amdgpu_ucode_print_sdma_hdr(&hdr->header);
804 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
aaa36a97 805 fw_data = (const __le32 *)
c113ea1c 806 (adev->sdma.instance[i].fw->data +
aaa36a97
AD
807 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
808 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
809 for (j = 0; j < fw_size; j++)
810 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
c113ea1c 811 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
aaa36a97
AD
812 }
813
814 return 0;
815}
816
817/**
818 * sdma_v3_0_start - setup and start the async dma engines
819 *
820 * @adev: amdgpu_device pointer
821 *
822 * Set up the DMA engines and enable them (VI).
823 * Returns 0 for success, error for failure.
824 */
825static int sdma_v3_0_start(struct amdgpu_device *adev)
826{
790d84fd 827 int r;
aaa36a97 828
790d84fd
RZ
829 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
830 r = sdma_v3_0_load_microcode(adev);
831 if (r)
832 return r;
aaa36a97
AD
833 }
834
8a1115ff 835 /* disable sdma engine before programing it */
505dfe76
ML
836 sdma_v3_0_ctx_switch_enable(adev, false);
837 sdma_v3_0_enable(adev, false);
aaa36a97
AD
838
839 /* start the gfx rings and rlc compute queues */
840 r = sdma_v3_0_gfx_resume(adev);
841 if (r)
842 return r;
843 r = sdma_v3_0_rlc_resume(adev);
844 if (r)
845 return r;
846
847 return 0;
848}
849
850/**
851 * sdma_v3_0_ring_test_ring - simple async dma engine test
852 *
853 * @ring: amdgpu_ring structure holding ring information
854 *
855 * Test the DMA engine by writing using it to write an
856 * value to memory. (VI).
857 * Returns 0 for success, error for failure.
858 */
859static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring)
860{
861 struct amdgpu_device *adev = ring->adev;
862 unsigned i;
863 unsigned index;
864 int r;
865 u32 tmp;
866 u64 gpu_addr;
867
131b4b36 868 r = amdgpu_device_wb_get(adev, &index);
aaa36a97
AD
869 if (r) {
870 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
871 return r;
872 }
873
874 gpu_addr = adev->wb.gpu_addr + (index * 4);
875 tmp = 0xCAFEDEAD;
876 adev->wb.wb[index] = cpu_to_le32(tmp);
877
a27de35c 878 r = amdgpu_ring_alloc(ring, 5);
aaa36a97
AD
879 if (r) {
880 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
131b4b36 881 amdgpu_device_wb_free(adev, index);
aaa36a97
AD
882 return r;
883 }
884
885 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
886 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
887 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
888 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
889 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
890 amdgpu_ring_write(ring, 0xDEADBEEF);
a27de35c 891 amdgpu_ring_commit(ring);
aaa36a97
AD
892
893 for (i = 0; i < adev->usec_timeout; i++) {
894 tmp = le32_to_cpu(adev->wb.wb[index]);
895 if (tmp == 0xDEADBEEF)
896 break;
897 DRM_UDELAY(1);
898 }
899
900 if (i < adev->usec_timeout) {
9953b72f 901 DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i);
aaa36a97
AD
902 } else {
903 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
904 ring->idx, tmp);
905 r = -EINVAL;
906 }
131b4b36 907 amdgpu_device_wb_free(adev, index);
aaa36a97
AD
908
909 return r;
910}
911
912/**
913 * sdma_v3_0_ring_test_ib - test an IB on the DMA engine
914 *
915 * @ring: amdgpu_ring structure holding ring information
916 *
917 * Test a simple IB in the DMA ring (VI).
918 * Returns 0 on success, error on failure.
919 */
bbec97aa 920static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
aaa36a97
AD
921{
922 struct amdgpu_device *adev = ring->adev;
923 struct amdgpu_ib ib;
f54d1867 924 struct dma_fence *f = NULL;
aaa36a97 925 unsigned index;
aaa36a97
AD
926 u32 tmp = 0;
927 u64 gpu_addr;
bbec97aa 928 long r;
aaa36a97 929
131b4b36 930 r = amdgpu_device_wb_get(adev, &index);
aaa36a97 931 if (r) {
bbec97aa 932 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
aaa36a97
AD
933 return r;
934 }
935
936 gpu_addr = adev->wb.gpu_addr + (index * 4);
937 tmp = 0xCAFEDEAD;
938 adev->wb.wb[index] = cpu_to_le32(tmp);
b203dd95 939 memset(&ib, 0, sizeof(ib));
b07c60c0 940 r = amdgpu_ib_get(adev, NULL, 256, &ib);
aaa36a97 941 if (r) {
bbec97aa 942 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
0011fdaa 943 goto err0;
aaa36a97
AD
944 }
945
946 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
947 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
948 ib.ptr[1] = lower_32_bits(gpu_addr);
949 ib.ptr[2] = upper_32_bits(gpu_addr);
950 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
951 ib.ptr[4] = 0xDEADBEEF;
952 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
953 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
954 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
955 ib.length_dw = 8;
956
50ddc75e 957 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
0011fdaa
CZ
958 if (r)
959 goto err1;
960
f54d1867 961 r = dma_fence_wait_timeout(f, false, timeout);
bbec97aa
CK
962 if (r == 0) {
963 DRM_ERROR("amdgpu: IB test timed out\n");
964 r = -ETIMEDOUT;
965 goto err1;
966 } else if (r < 0) {
967 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
0011fdaa 968 goto err1;
aaa36a97 969 }
6d44565d
CK
970 tmp = le32_to_cpu(adev->wb.wb[index]);
971 if (tmp == 0xDEADBEEF) {
9953b72f 972 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
bbec97aa 973 r = 0;
aaa36a97
AD
974 } else {
975 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
976 r = -EINVAL;
977 }
0011fdaa 978err1:
cc55c45d 979 amdgpu_ib_free(adev, &ib, NULL);
f54d1867 980 dma_fence_put(f);
0011fdaa 981err0:
131b4b36 982 amdgpu_device_wb_free(adev, index);
aaa36a97
AD
983 return r;
984}
985
986/**
987 * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART
988 *
989 * @ib: indirect buffer to fill with commands
990 * @pe: addr of the page entry
991 * @src: src addr to copy from
992 * @count: number of page entries to update
993 *
994 * Update PTEs by copying them from the GART using sDMA (CIK).
995 */
996static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib,
997 uint64_t pe, uint64_t src,
998 unsigned count)
999{
96105e53
CK
1000 unsigned bytes = count * 8;
1001
1002 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1003 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1004 ib->ptr[ib->length_dw++] = bytes;
1005 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1006 ib->ptr[ib->length_dw++] = lower_32_bits(src);
1007 ib->ptr[ib->length_dw++] = upper_32_bits(src);
1008 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1009 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
aaa36a97
AD
1010}
1011
1012/**
1013 * sdma_v3_0_vm_write_pte - update PTEs by writing them manually
1014 *
1015 * @ib: indirect buffer to fill with commands
1016 * @pe: addr of the page entry
de9ea7bd 1017 * @value: dst addr to write into pe
aaa36a97
AD
1018 * @count: number of page entries to update
1019 * @incr: increase next addr by incr bytes
aaa36a97
AD
1020 *
1021 * Update PTEs by writing them manually using sDMA (CIK).
1022 */
de9ea7bd
CK
1023static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1024 uint64_t value, unsigned count,
1025 uint32_t incr)
aaa36a97 1026{
de9ea7bd
CK
1027 unsigned ndw = count * 2;
1028
1029 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
6bf3f9c3 1030 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
de9ea7bd
CK
1031 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1032 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1033 ib->ptr[ib->length_dw++] = ndw;
4bc07289 1034 for (; ndw > 0; ndw -= 2) {
de9ea7bd
CK
1035 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1036 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1037 value += incr;
aaa36a97
AD
1038 }
1039}
1040
1041/**
1042 * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA
1043 *
1044 * @ib: indirect buffer to fill with commands
1045 * @pe: addr of the page entry
1046 * @addr: dst addr to write into pe
1047 * @count: number of page entries to update
1048 * @incr: increase next addr by incr bytes
1049 * @flags: access flags
1050 *
1051 * Update the page tables using sDMA (CIK).
1052 */
96105e53 1053static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
aaa36a97 1054 uint64_t addr, unsigned count,
6b777607 1055 uint32_t incr, uint64_t flags)
aaa36a97 1056{
96105e53
CK
1057 /* for physically contiguous pages (vram) */
1058 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
1059 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1060 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
b9be700e
JZ
1061 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1062 ib->ptr[ib->length_dw++] = upper_32_bits(flags);
96105e53
CK
1063 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1064 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1065 ib->ptr[ib->length_dw++] = incr; /* increment size */
1066 ib->ptr[ib->length_dw++] = 0;
1067 ib->ptr[ib->length_dw++] = count; /* number of entries */
aaa36a97
AD
1068}
1069
1070/**
9e5d5309 1071 * sdma_v3_0_ring_pad_ib - pad the IB to the required number of dw
aaa36a97
AD
1072 *
1073 * @ib: indirect buffer to fill with padding
1074 *
1075 */
9e5d5309 1076static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
aaa36a97 1077{
9e5d5309 1078 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
ac01db3d
JZ
1079 u32 pad_count;
1080 int i;
1081
1082 pad_count = (8 - (ib->length_dw & 0x7)) % 8;
1083 for (i = 0; i < pad_count; i++)
1084 if (sdma && sdma->burst_nop && (i == 0))
1085 ib->ptr[ib->length_dw++] =
1086 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1087 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1088 else
1089 ib->ptr[ib->length_dw++] =
1090 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
aaa36a97
AD
1091}
1092
1093/**
00b7c4ff 1094 * sdma_v3_0_ring_emit_pipeline_sync - sync the pipeline
aaa36a97
AD
1095 *
1096 * @ring: amdgpu_ring pointer
aaa36a97 1097 *
00b7c4ff 1098 * Make sure all previous operations are completed (CIK).
aaa36a97 1099 */
00b7c4ff 1100static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
aaa36a97 1101{
5c55db83
CZ
1102 uint32_t seq = ring->fence_drv.sync_seq;
1103 uint64_t addr = ring->fence_drv.gpu_addr;
1104
1105 /* wait for idle */
1106 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1107 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1108 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1109 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1110 amdgpu_ring_write(ring, addr & 0xfffffffc);
1111 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1112 amdgpu_ring_write(ring, seq); /* reference */
4a8e06f7 1113 amdgpu_ring_write(ring, 0xffffffff); /* mask */
5c55db83
CZ
1114 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1115 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
00b7c4ff 1116}
5c55db83 1117
00b7c4ff
CK
1118/**
1119 * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA
1120 *
1121 * @ring: amdgpu_ring pointer
1122 * @vm: amdgpu_vm pointer
1123 *
1124 * Update the page table base and flush the VM TLB
1125 * using sDMA (VI).
1126 */
1127static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
c633c00b 1128 unsigned vmid, uint64_t pd_addr)
00b7c4ff 1129{
c633c00b 1130 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
aaa36a97
AD
1131
1132 /* wait for flush */
1133 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1134 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1135 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
1136 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
1137 amdgpu_ring_write(ring, 0);
1138 amdgpu_ring_write(ring, 0); /* reference */
1139 amdgpu_ring_write(ring, 0); /* mask */
1140 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1141 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
1142}
1143
3d31d4cb
CK
1144static void sdma_v3_0_ring_emit_wreg(struct amdgpu_ring *ring,
1145 uint32_t reg, uint32_t val)
1146{
1147 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1148 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1149 amdgpu_ring_write(ring, reg);
1150 amdgpu_ring_write(ring, val);
1151}
1152
5fc3aeeb 1153static int sdma_v3_0_early_init(void *handle)
aaa36a97 1154{
5fc3aeeb 1155 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1156
c113ea1c 1157 switch (adev->asic_type) {
bb16e3b6
SL
1158 case CHIP_STONEY:
1159 adev->sdma.num_instances = 1;
1160 break;
c113ea1c
AD
1161 default:
1162 adev->sdma.num_instances = SDMA_MAX_INSTANCE;
1163 break;
1164 }
1165
aaa36a97
AD
1166 sdma_v3_0_set_ring_funcs(adev);
1167 sdma_v3_0_set_buffer_funcs(adev);
1168 sdma_v3_0_set_vm_pte_funcs(adev);
1169 sdma_v3_0_set_irq_funcs(adev);
1170
1171 return 0;
1172}
1173
5fc3aeeb 1174static int sdma_v3_0_sw_init(void *handle)
aaa36a97
AD
1175{
1176 struct amdgpu_ring *ring;
c113ea1c 1177 int r, i;
5fc3aeeb 1178 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD
1179
1180 /* SDMA trap event */
d766e6a3
AD
1181 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 224,
1182 &adev->sdma.trap_irq);
aaa36a97
AD
1183 if (r)
1184 return r;
1185
1186 /* SDMA Privileged inst */
d766e6a3
AD
1187 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 241,
1188 &adev->sdma.illegal_inst_irq);
aaa36a97
AD
1189 if (r)
1190 return r;
1191
1192 /* SDMA Privileged inst */
d766e6a3
AD
1193 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 247,
1194 &adev->sdma.illegal_inst_irq);
aaa36a97
AD
1195 if (r)
1196 return r;
1197
1198 r = sdma_v3_0_init_microcode(adev);
1199 if (r) {
1200 DRM_ERROR("Failed to load sdma firmware!\n");
1201 return r;
1202 }
1203
c113ea1c
AD
1204 for (i = 0; i < adev->sdma.num_instances; i++) {
1205 ring = &adev->sdma.instance[i].ring;
1206 ring->ring_obj = NULL;
2ffe31de
PD
1207 if (!amdgpu_sriov_vf(adev)) {
1208 ring->use_doorbell = true;
1209 ring->doorbell_index = (i == 0) ?
1210 AMDGPU_DOORBELL_sDMA_ENGINE0 : AMDGPU_DOORBELL_sDMA_ENGINE1;
1211 } else {
1212 ring->use_pollmem = true;
1213 }
c113ea1c
AD
1214
1215 sprintf(ring->name, "sdma%d", i);
b38d99c4 1216 r = amdgpu_ring_init(adev, ring, 1024,
c113ea1c
AD
1217 &adev->sdma.trap_irq,
1218 (i == 0) ?
21cd942e
CK
1219 AMDGPU_SDMA_IRQ_TRAP0 :
1220 AMDGPU_SDMA_IRQ_TRAP1);
c113ea1c
AD
1221 if (r)
1222 return r;
1223 }
aaa36a97
AD
1224
1225 return r;
1226}
1227
5fc3aeeb 1228static int sdma_v3_0_sw_fini(void *handle)
aaa36a97 1229{
5fc3aeeb 1230 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
c113ea1c 1231 int i;
5fc3aeeb 1232
c113ea1c
AD
1233 for (i = 0; i < adev->sdma.num_instances; i++)
1234 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
aaa36a97 1235
14d83e78 1236 sdma_v3_0_free_microcode(adev);
aaa36a97
AD
1237 return 0;
1238}
1239
5fc3aeeb 1240static int sdma_v3_0_hw_init(void *handle)
aaa36a97
AD
1241{
1242 int r;
5fc3aeeb 1243 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD
1244
1245 sdma_v3_0_init_golden_registers(adev);
1246
1247 r = sdma_v3_0_start(adev);
1248 if (r)
1249 return r;
1250
1251 return r;
1252}
1253
5fc3aeeb 1254static int sdma_v3_0_hw_fini(void *handle)
aaa36a97 1255{
5fc3aeeb 1256 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1257
cd06bf68 1258 sdma_v3_0_ctx_switch_enable(adev, false);
aaa36a97
AD
1259 sdma_v3_0_enable(adev, false);
1260
1261 return 0;
1262}
1263
5fc3aeeb 1264static int sdma_v3_0_suspend(void *handle)
aaa36a97 1265{
5fc3aeeb 1266 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD
1267
1268 return sdma_v3_0_hw_fini(adev);
1269}
1270
5fc3aeeb 1271static int sdma_v3_0_resume(void *handle)
aaa36a97 1272{
5fc3aeeb 1273 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD
1274
1275 return sdma_v3_0_hw_init(adev);
1276}
1277
5fc3aeeb 1278static bool sdma_v3_0_is_idle(void *handle)
aaa36a97 1279{
5fc3aeeb 1280 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD
1281 u32 tmp = RREG32(mmSRBM_STATUS2);
1282
1283 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1284 SRBM_STATUS2__SDMA1_BUSY_MASK))
1285 return false;
1286
1287 return true;
1288}
1289
5fc3aeeb 1290static int sdma_v3_0_wait_for_idle(void *handle)
aaa36a97
AD
1291{
1292 unsigned i;
1293 u32 tmp;
5fc3aeeb 1294 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD
1295
1296 for (i = 0; i < adev->usec_timeout; i++) {
1297 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1298 SRBM_STATUS2__SDMA1_BUSY_MASK);
1299
1300 if (!tmp)
1301 return 0;
1302 udelay(1);
1303 }
1304 return -ETIMEDOUT;
1305}
1306
da146d3b 1307static bool sdma_v3_0_check_soft_reset(void *handle)
aaa36a97 1308{
5fc3aeeb 1309 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
e702a680 1310 u32 srbm_soft_reset = 0;
aaa36a97
AD
1311 u32 tmp = RREG32(mmSRBM_STATUS2);
1312
e702a680
CZ
1313 if ((tmp & SRBM_STATUS2__SDMA_BUSY_MASK) ||
1314 (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK)) {
aaa36a97 1315 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
aaa36a97
AD
1316 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1317 }
1318
e702a680 1319 if (srbm_soft_reset) {
e702a680 1320 adev->sdma.srbm_soft_reset = srbm_soft_reset;
da146d3b 1321 return true;
e702a680 1322 } else {
e702a680 1323 adev->sdma.srbm_soft_reset = 0;
da146d3b 1324 return false;
e702a680 1325 }
e702a680
CZ
1326}
1327
1328static int sdma_v3_0_pre_soft_reset(void *handle)
1329{
1330 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1331 u32 srbm_soft_reset = 0;
1332
da146d3b 1333 if (!adev->sdma.srbm_soft_reset)
e702a680
CZ
1334 return 0;
1335
1336 srbm_soft_reset = adev->sdma.srbm_soft_reset;
1337
1338 if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) ||
1339 REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) {
1340 sdma_v3_0_ctx_switch_enable(adev, false);
1341 sdma_v3_0_enable(adev, false);
1342 }
1343
1344 return 0;
1345}
1346
1347static int sdma_v3_0_post_soft_reset(void *handle)
1348{
1349 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1350 u32 srbm_soft_reset = 0;
1351
da146d3b 1352 if (!adev->sdma.srbm_soft_reset)
e702a680
CZ
1353 return 0;
1354
1355 srbm_soft_reset = adev->sdma.srbm_soft_reset;
1356
1357 if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) ||
1358 REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) {
1359 sdma_v3_0_gfx_resume(adev);
1360 sdma_v3_0_rlc_resume(adev);
1361 }
1362
1363 return 0;
1364}
1365
1366static int sdma_v3_0_soft_reset(void *handle)
1367{
1368 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1369 u32 srbm_soft_reset = 0;
1370 u32 tmp;
1371
da146d3b 1372 if (!adev->sdma.srbm_soft_reset)
e702a680
CZ
1373 return 0;
1374
1375 srbm_soft_reset = adev->sdma.srbm_soft_reset;
1376
aaa36a97 1377 if (srbm_soft_reset) {
aaa36a97
AD
1378 tmp = RREG32(mmSRBM_SOFT_RESET);
1379 tmp |= srbm_soft_reset;
1380 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1381 WREG32(mmSRBM_SOFT_RESET, tmp);
1382 tmp = RREG32(mmSRBM_SOFT_RESET);
1383
1384 udelay(50);
1385
1386 tmp &= ~srbm_soft_reset;
1387 WREG32(mmSRBM_SOFT_RESET, tmp);
1388 tmp = RREG32(mmSRBM_SOFT_RESET);
1389
1390 /* Wait a little for things to settle down */
1391 udelay(50);
aaa36a97
AD
1392 }
1393
1394 return 0;
1395}
1396
1397static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev,
1398 struct amdgpu_irq_src *source,
1399 unsigned type,
1400 enum amdgpu_interrupt_state state)
1401{
1402 u32 sdma_cntl;
1403
1404 switch (type) {
1405 case AMDGPU_SDMA_IRQ_TRAP0:
1406 switch (state) {
1407 case AMDGPU_IRQ_STATE_DISABLE:
1408 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1409 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1410 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1411 break;
1412 case AMDGPU_IRQ_STATE_ENABLE:
1413 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1414 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1415 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1416 break;
1417 default:
1418 break;
1419 }
1420 break;
1421 case AMDGPU_SDMA_IRQ_TRAP1:
1422 switch (state) {
1423 case AMDGPU_IRQ_STATE_DISABLE:
1424 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1425 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1426 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1427 break;
1428 case AMDGPU_IRQ_STATE_ENABLE:
1429 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1430 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1431 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1432 break;
1433 default:
1434 break;
1435 }
1436 break;
1437 default:
1438 break;
1439 }
1440 return 0;
1441}
1442
1443static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev,
1444 struct amdgpu_irq_src *source,
1445 struct amdgpu_iv_entry *entry)
1446{
1447 u8 instance_id, queue_id;
1448
1449 instance_id = (entry->ring_id & 0x3) >> 0;
1450 queue_id = (entry->ring_id & 0xc) >> 2;
1451 DRM_DEBUG("IH: SDMA trap\n");
1452 switch (instance_id) {
1453 case 0:
1454 switch (queue_id) {
1455 case 0:
c113ea1c 1456 amdgpu_fence_process(&adev->sdma.instance[0].ring);
aaa36a97
AD
1457 break;
1458 case 1:
1459 /* XXX compute */
1460 break;
1461 case 2:
1462 /* XXX compute */
1463 break;
1464 }
1465 break;
1466 case 1:
1467 switch (queue_id) {
1468 case 0:
c113ea1c 1469 amdgpu_fence_process(&adev->sdma.instance[1].ring);
aaa36a97
AD
1470 break;
1471 case 1:
1472 /* XXX compute */
1473 break;
1474 case 2:
1475 /* XXX compute */
1476 break;
1477 }
1478 break;
1479 }
1480 return 0;
1481}
1482
1483static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1484 struct amdgpu_irq_src *source,
1485 struct amdgpu_iv_entry *entry)
1486{
1487 DRM_ERROR("Illegal instruction in SDMA command stream\n");
1488 schedule_work(&adev->reset_work);
1489 return 0;
1490}
1491
ce22362b 1492static void sdma_v3_0_update_sdma_medium_grain_clock_gating(
3c997d24
EH
1493 struct amdgpu_device *adev,
1494 bool enable)
1495{
1496 uint32_t temp, data;
ce22362b 1497 int i;
3c997d24 1498
e08d53cb 1499 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
ce22362b
AD
1500 for (i = 0; i < adev->sdma.num_instances; i++) {
1501 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
1502 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1503 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1504 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1505 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1506 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1507 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1508 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1509 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1510 if (data != temp)
1511 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
1512 }
3c997d24 1513 } else {
ce22362b
AD
1514 for (i = 0; i < adev->sdma.num_instances; i++) {
1515 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
1516 data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
3c997d24
EH
1517 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1518 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1519 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1520 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1521 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1522 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1523 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK;
1524
ce22362b
AD
1525 if (data != temp)
1526 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
1527 }
3c997d24
EH
1528 }
1529}
1530
ce22362b 1531static void sdma_v3_0_update_sdma_medium_grain_light_sleep(
3c997d24
EH
1532 struct amdgpu_device *adev,
1533 bool enable)
1534{
1535 uint32_t temp, data;
ce22362b 1536 int i;
3c997d24 1537
e08d53cb 1538 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
ce22362b
AD
1539 for (i = 0; i < adev->sdma.num_instances; i++) {
1540 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
1541 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
3c997d24 1542
ce22362b
AD
1543 if (temp != data)
1544 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
1545 }
3c997d24 1546 } else {
ce22362b
AD
1547 for (i = 0; i < adev->sdma.num_instances; i++) {
1548 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
1549 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
3c997d24 1550
ce22362b
AD
1551 if (temp != data)
1552 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
1553 }
3c997d24
EH
1554 }
1555}
1556
5fc3aeeb 1557static int sdma_v3_0_set_clockgating_state(void *handle,
1558 enum amd_clockgating_state state)
aaa36a97 1559{
3c997d24
EH
1560 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1561
ce137c04
ML
1562 if (amdgpu_sriov_vf(adev))
1563 return 0;
1564
3c997d24
EH
1565 switch (adev->asic_type) {
1566 case CHIP_FIJI:
ce22362b
AD
1567 case CHIP_CARRIZO:
1568 case CHIP_STONEY:
1569 sdma_v3_0_update_sdma_medium_grain_clock_gating(adev,
7e913664 1570 state == AMD_CG_STATE_GATE);
ce22362b 1571 sdma_v3_0_update_sdma_medium_grain_light_sleep(adev,
7e913664 1572 state == AMD_CG_STATE_GATE);
3c997d24
EH
1573 break;
1574 default:
1575 break;
1576 }
aaa36a97
AD
1577 return 0;
1578}
1579
5fc3aeeb 1580static int sdma_v3_0_set_powergating_state(void *handle,
1581 enum amd_powergating_state state)
aaa36a97
AD
1582{
1583 return 0;
1584}
1585
41c360f6
HR
1586static void sdma_v3_0_get_clockgating_state(void *handle, u32 *flags)
1587{
1588 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1589 int data;
1590
ce137c04
ML
1591 if (amdgpu_sriov_vf(adev))
1592 *flags = 0;
1593
41c360f6
HR
1594 /* AMD_CG_SUPPORT_SDMA_MGCG */
1595 data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[0]);
1596 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK))
1597 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1598
1599 /* AMD_CG_SUPPORT_SDMA_LS */
1600 data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[0]);
1601 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1602 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1603}
1604
a1255107 1605static const struct amd_ip_funcs sdma_v3_0_ip_funcs = {
88a907d6 1606 .name = "sdma_v3_0",
aaa36a97
AD
1607 .early_init = sdma_v3_0_early_init,
1608 .late_init = NULL,
1609 .sw_init = sdma_v3_0_sw_init,
1610 .sw_fini = sdma_v3_0_sw_fini,
1611 .hw_init = sdma_v3_0_hw_init,
1612 .hw_fini = sdma_v3_0_hw_fini,
1613 .suspend = sdma_v3_0_suspend,
1614 .resume = sdma_v3_0_resume,
1615 .is_idle = sdma_v3_0_is_idle,
1616 .wait_for_idle = sdma_v3_0_wait_for_idle,
e702a680
CZ
1617 .check_soft_reset = sdma_v3_0_check_soft_reset,
1618 .pre_soft_reset = sdma_v3_0_pre_soft_reset,
1619 .post_soft_reset = sdma_v3_0_post_soft_reset,
aaa36a97 1620 .soft_reset = sdma_v3_0_soft_reset,
aaa36a97
AD
1621 .set_clockgating_state = sdma_v3_0_set_clockgating_state,
1622 .set_powergating_state = sdma_v3_0_set_powergating_state,
41c360f6 1623 .get_clockgating_state = sdma_v3_0_get_clockgating_state,
aaa36a97
AD
1624};
1625
aaa36a97 1626static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
21cd942e 1627 .type = AMDGPU_RING_TYPE_SDMA,
79887142
CK
1628 .align_mask = 0xf,
1629 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
536fbf94 1630 .support_64bit_ptrs = false,
aaa36a97
AD
1631 .get_rptr = sdma_v3_0_ring_get_rptr,
1632 .get_wptr = sdma_v3_0_ring_get_wptr,
1633 .set_wptr = sdma_v3_0_ring_set_wptr,
e12f3d7a
CK
1634 .emit_frame_size =
1635 6 + /* sdma_v3_0_ring_emit_hdp_flush */
2ee150cd 1636 3 + /* hdp invalidate */
e12f3d7a 1637 6 + /* sdma_v3_0_ring_emit_pipeline_sync */
49135593 1638 VI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* sdma_v3_0_ring_emit_vm_flush */
e12f3d7a
CK
1639 10 + 10 + 10, /* sdma_v3_0_ring_emit_fence x3 for user fence, vm fence */
1640 .emit_ib_size = 7 + 6, /* sdma_v3_0_ring_emit_ib */
aaa36a97
AD
1641 .emit_ib = sdma_v3_0_ring_emit_ib,
1642 .emit_fence = sdma_v3_0_ring_emit_fence,
00b7c4ff 1643 .emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync,
aaa36a97 1644 .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush,
d2edb07b 1645 .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush,
aaa36a97
AD
1646 .test_ring = sdma_v3_0_ring_test_ring,
1647 .test_ib = sdma_v3_0_ring_test_ib,
ac01db3d 1648 .insert_nop = sdma_v3_0_ring_insert_nop,
9e5d5309 1649 .pad_ib = sdma_v3_0_ring_pad_ib,
3d31d4cb 1650 .emit_wreg = sdma_v3_0_ring_emit_wreg,
aaa36a97
AD
1651};
1652
1653static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev)
1654{
c113ea1c
AD
1655 int i;
1656
1657 for (i = 0; i < adev->sdma.num_instances; i++)
1658 adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs;
aaa36a97
AD
1659}
1660
1661static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = {
1662 .set = sdma_v3_0_set_trap_irq_state,
1663 .process = sdma_v3_0_process_trap_irq,
1664};
1665
1666static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = {
1667 .process = sdma_v3_0_process_illegal_inst_irq,
1668};
1669
1670static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev)
1671{
c113ea1c
AD
1672 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1673 adev->sdma.trap_irq.funcs = &sdma_v3_0_trap_irq_funcs;
1674 adev->sdma.illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs;
aaa36a97
AD
1675}
1676
1677/**
1678 * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine
1679 *
1680 * @ring: amdgpu_ring structure holding ring information
1681 * @src_offset: src GPU address
1682 * @dst_offset: dst GPU address
1683 * @byte_count: number of bytes to xfer
1684 *
1685 * Copy GPU buffers using the DMA engine (VI).
1686 * Used by the amdgpu ttm implementation to move pages if
1687 * registered as the asic copy callback.
1688 */
c7ae72c0 1689static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib,
aaa36a97
AD
1690 uint64_t src_offset,
1691 uint64_t dst_offset,
1692 uint32_t byte_count)
1693{
c7ae72c0
CZ
1694 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1695 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1696 ib->ptr[ib->length_dw++] = byte_count;
1697 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1698 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1699 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1700 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1701 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
aaa36a97
AD
1702}
1703
1704/**
1705 * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine
1706 *
1707 * @ring: amdgpu_ring structure holding ring information
1708 * @src_data: value to write to buffer
1709 * @dst_offset: dst GPU address
1710 * @byte_count: number of bytes to xfer
1711 *
1712 * Fill GPU buffers using the DMA engine (VI).
1713 */
6e7a3840 1714static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib,
aaa36a97
AD
1715 uint32_t src_data,
1716 uint64_t dst_offset,
1717 uint32_t byte_count)
1718{
6e7a3840
CZ
1719 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1720 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1721 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1722 ib->ptr[ib->length_dw++] = src_data;
1723 ib->ptr[ib->length_dw++] = byte_count;
aaa36a97
AD
1724}
1725
1726static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = {
dfe5c2b7 1727 .copy_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */
aaa36a97
AD
1728 .copy_num_dw = 7,
1729 .emit_copy_buffer = sdma_v3_0_emit_copy_buffer,
1730
dfe5c2b7 1731 .fill_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */
aaa36a97
AD
1732 .fill_num_dw = 5,
1733 .emit_fill_buffer = sdma_v3_0_emit_fill_buffer,
1734};
1735
1736static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev)
1737{
1738 if (adev->mman.buffer_funcs == NULL) {
1739 adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs;
c113ea1c 1740 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
aaa36a97
AD
1741 }
1742}
1743
1744static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = {
e6d92197 1745 .copy_pte_num_dw = 7,
aaa36a97 1746 .copy_pte = sdma_v3_0_vm_copy_pte,
e6d92197 1747
aaa36a97
AD
1748 .write_pte = sdma_v3_0_vm_write_pte,
1749 .set_pte_pde = sdma_v3_0_vm_set_pte_pde,
aaa36a97
AD
1750};
1751
1752static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1753{
2d55e45a
CK
1754 unsigned i;
1755
aaa36a97
AD
1756 if (adev->vm_manager.vm_pte_funcs == NULL) {
1757 adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs;
2d55e45a
CK
1758 for (i = 0; i < adev->sdma.num_instances; i++)
1759 adev->vm_manager.vm_pte_rings[i] =
1760 &adev->sdma.instance[i].ring;
1761
1762 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
aaa36a97
AD
1763 }
1764}
a1255107
AD
1765
1766const struct amdgpu_ip_block_version sdma_v3_0_ip_block =
1767{
1768 .type = AMD_IP_BLOCK_TYPE_SDMA,
1769 .major = 3,
1770 .minor = 0,
1771 .rev = 0,
1772 .funcs = &sdma_v3_0_ip_funcs,
1773};
1774
1775const struct amdgpu_ip_block_version sdma_v3_1_ip_block =
1776{
1777 .type = AMD_IP_BLOCK_TYPE_SDMA,
1778 .major = 3,
1779 .minor = 1,
1780 .rev = 0,
1781 .funcs = &sdma_v3_0_ip_funcs,
1782};