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aaa36a97 AD |
1 | /* |
2 | * Copyright 2014 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Alex Deucher | |
23 | */ | |
24 | #include <linux/firmware.h> | |
25 | #include <drm/drmP.h> | |
26 | #include "amdgpu.h" | |
27 | #include "amdgpu_ucode.h" | |
28 | #include "amdgpu_trace.h" | |
29 | #include "vi.h" | |
30 | #include "vid.h" | |
31 | ||
32 | #include "oss/oss_3_0_d.h" | |
33 | #include "oss/oss_3_0_sh_mask.h" | |
34 | ||
35 | #include "gmc/gmc_8_1_d.h" | |
36 | #include "gmc/gmc_8_1_sh_mask.h" | |
37 | ||
38 | #include "gca/gfx_8_0_d.h" | |
74a5d165 | 39 | #include "gca/gfx_8_0_enum.h" |
aaa36a97 AD |
40 | #include "gca/gfx_8_0_sh_mask.h" |
41 | ||
42 | #include "bif/bif_5_0_d.h" | |
43 | #include "bif/bif_5_0_sh_mask.h" | |
44 | ||
45 | #include "tonga_sdma_pkt_open.h" | |
46 | ||
47 | static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev); | |
48 | static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev); | |
49 | static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev); | |
50 | static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev); | |
51 | ||
c65444fe JZ |
52 | MODULE_FIRMWARE("amdgpu/tonga_sdma.bin"); |
53 | MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin"); | |
54 | MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin"); | |
55 | MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin"); | |
1a5bbb66 DZ |
56 | MODULE_FIRMWARE("amdgpu/fiji_sdma.bin"); |
57 | MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin"); | |
bb16e3b6 | 58 | MODULE_FIRMWARE("amdgpu/stoney_sdma.bin"); |
2cc0c0b5 FC |
59 | MODULE_FIRMWARE("amdgpu/polaris10_sdma.bin"); |
60 | MODULE_FIRMWARE("amdgpu/polaris10_sdma1.bin"); | |
61 | MODULE_FIRMWARE("amdgpu/polaris11_sdma.bin"); | |
62 | MODULE_FIRMWARE("amdgpu/polaris11_sdma1.bin"); | |
2cea03de | 63 | |
aaa36a97 AD |
64 | |
65 | static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = | |
66 | { | |
67 | SDMA0_REGISTER_OFFSET, | |
68 | SDMA1_REGISTER_OFFSET | |
69 | }; | |
70 | ||
71 | static const u32 golden_settings_tonga_a11[] = | |
72 | { | |
73 | mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, | |
74 | mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, | |
75 | mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, | |
76 | mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, | |
77 | mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, | |
78 | mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, | |
79 | mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, | |
80 | mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, | |
81 | mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, | |
82 | mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, | |
83 | }; | |
84 | ||
85 | static const u32 tonga_mgcg_cgcg_init[] = | |
86 | { | |
87 | mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, | |
88 | mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 | |
89 | }; | |
90 | ||
1a5bbb66 DZ |
91 | static const u32 golden_settings_fiji_a10[] = |
92 | { | |
93 | mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, | |
94 | mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, | |
95 | mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, | |
96 | mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, | |
97 | mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, | |
98 | mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, | |
99 | mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, | |
100 | mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, | |
101 | }; | |
102 | ||
103 | static const u32 fiji_mgcg_cgcg_init[] = | |
104 | { | |
105 | mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, | |
106 | mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 | |
107 | }; | |
108 | ||
2cc0c0b5 | 109 | static const u32 golden_settings_polaris11_a11[] = |
2cea03de FC |
110 | { |
111 | mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, | |
112 | mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, | |
113 | mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, | |
114 | mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, | |
115 | mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, | |
116 | mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, | |
117 | mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, | |
118 | mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, | |
119 | }; | |
120 | ||
2cc0c0b5 | 121 | static const u32 golden_settings_polaris10_a11[] = |
2cea03de FC |
122 | { |
123 | mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, | |
124 | mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, | |
125 | mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, | |
126 | mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, | |
127 | mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, | |
128 | mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, | |
129 | mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, | |
130 | mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, | |
131 | mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, | |
132 | mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, | |
133 | }; | |
134 | ||
aaa36a97 AD |
135 | static const u32 cz_golden_settings_a11[] = |
136 | { | |
137 | mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, | |
138 | mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, | |
139 | mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100, | |
140 | mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800, | |
141 | mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100, | |
142 | mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100, | |
143 | mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, | |
144 | mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, | |
145 | mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100, | |
146 | mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800, | |
147 | mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100, | |
148 | mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100, | |
149 | }; | |
150 | ||
151 | static const u32 cz_mgcg_cgcg_init[] = | |
152 | { | |
153 | mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, | |
154 | mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 | |
155 | }; | |
156 | ||
bb16e3b6 SL |
157 | static const u32 stoney_golden_settings_a11[] = |
158 | { | |
159 | mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100, | |
160 | mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800, | |
161 | mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100, | |
162 | mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100, | |
163 | }; | |
164 | ||
165 | static const u32 stoney_mgcg_cgcg_init[] = | |
166 | { | |
167 | mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100, | |
168 | }; | |
169 | ||
aaa36a97 AD |
170 | /* |
171 | * sDMA - System DMA | |
172 | * Starting with CIK, the GPU has new asynchronous | |
173 | * DMA engines. These engines are used for compute | |
174 | * and gfx. There are two DMA engines (SDMA0, SDMA1) | |
175 | * and each one supports 1 ring buffer used for gfx | |
176 | * and 2 queues used for compute. | |
177 | * | |
178 | * The programming model is very similar to the CP | |
179 | * (ring buffer, IBs, etc.), but sDMA has it's own | |
180 | * packet format that is different from the PM4 format | |
181 | * used by the CP. sDMA supports copying data, writing | |
182 | * embedded data, solid fills, and a number of other | |
183 | * things. It also has support for tiling/detiling of | |
184 | * buffers. | |
185 | */ | |
186 | ||
187 | static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev) | |
188 | { | |
189 | switch (adev->asic_type) { | |
1a5bbb66 DZ |
190 | case CHIP_FIJI: |
191 | amdgpu_program_register_sequence(adev, | |
192 | fiji_mgcg_cgcg_init, | |
193 | (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init)); | |
194 | amdgpu_program_register_sequence(adev, | |
195 | golden_settings_fiji_a10, | |
196 | (const u32)ARRAY_SIZE(golden_settings_fiji_a10)); | |
197 | break; | |
aaa36a97 AD |
198 | case CHIP_TONGA: |
199 | amdgpu_program_register_sequence(adev, | |
200 | tonga_mgcg_cgcg_init, | |
201 | (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); | |
202 | amdgpu_program_register_sequence(adev, | |
203 | golden_settings_tonga_a11, | |
204 | (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); | |
205 | break; | |
2cc0c0b5 | 206 | case CHIP_POLARIS11: |
2cea03de | 207 | amdgpu_program_register_sequence(adev, |
2cc0c0b5 FC |
208 | golden_settings_polaris11_a11, |
209 | (const u32)ARRAY_SIZE(golden_settings_polaris11_a11)); | |
2cea03de | 210 | break; |
2cc0c0b5 | 211 | case CHIP_POLARIS10: |
2cea03de | 212 | amdgpu_program_register_sequence(adev, |
2cc0c0b5 FC |
213 | golden_settings_polaris10_a11, |
214 | (const u32)ARRAY_SIZE(golden_settings_polaris10_a11)); | |
2cea03de | 215 | break; |
aaa36a97 AD |
216 | case CHIP_CARRIZO: |
217 | amdgpu_program_register_sequence(adev, | |
218 | cz_mgcg_cgcg_init, | |
219 | (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); | |
220 | amdgpu_program_register_sequence(adev, | |
221 | cz_golden_settings_a11, | |
222 | (const u32)ARRAY_SIZE(cz_golden_settings_a11)); | |
223 | break; | |
bb16e3b6 SL |
224 | case CHIP_STONEY: |
225 | amdgpu_program_register_sequence(adev, | |
226 | stoney_mgcg_cgcg_init, | |
227 | (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init)); | |
228 | amdgpu_program_register_sequence(adev, | |
229 | stoney_golden_settings_a11, | |
230 | (const u32)ARRAY_SIZE(stoney_golden_settings_a11)); | |
231 | break; | |
aaa36a97 AD |
232 | default: |
233 | break; | |
234 | } | |
235 | } | |
236 | ||
237 | /** | |
238 | * sdma_v3_0_init_microcode - load ucode images from disk | |
239 | * | |
240 | * @adev: amdgpu_device pointer | |
241 | * | |
242 | * Use the firmware interface to load the ucode images into | |
243 | * the driver (not loaded into hw). | |
244 | * Returns 0 on success, error on failure. | |
245 | */ | |
246 | static int sdma_v3_0_init_microcode(struct amdgpu_device *adev) | |
247 | { | |
248 | const char *chip_name; | |
249 | char fw_name[30]; | |
c113ea1c | 250 | int err = 0, i; |
aaa36a97 AD |
251 | struct amdgpu_firmware_info *info = NULL; |
252 | const struct common_firmware_header *header = NULL; | |
595fd013 | 253 | const struct sdma_firmware_header_v1_0 *hdr; |
aaa36a97 AD |
254 | |
255 | DRM_DEBUG("\n"); | |
256 | ||
257 | switch (adev->asic_type) { | |
258 | case CHIP_TONGA: | |
259 | chip_name = "tonga"; | |
260 | break; | |
1a5bbb66 DZ |
261 | case CHIP_FIJI: |
262 | chip_name = "fiji"; | |
263 | break; | |
2cc0c0b5 FC |
264 | case CHIP_POLARIS11: |
265 | chip_name = "polaris11"; | |
2cea03de | 266 | break; |
2cc0c0b5 FC |
267 | case CHIP_POLARIS10: |
268 | chip_name = "polaris10"; | |
2cea03de | 269 | break; |
aaa36a97 AD |
270 | case CHIP_CARRIZO: |
271 | chip_name = "carrizo"; | |
272 | break; | |
bb16e3b6 SL |
273 | case CHIP_STONEY: |
274 | chip_name = "stoney"; | |
275 | break; | |
aaa36a97 AD |
276 | default: BUG(); |
277 | } | |
278 | ||
c113ea1c | 279 | for (i = 0; i < adev->sdma.num_instances; i++) { |
aaa36a97 | 280 | if (i == 0) |
c65444fe | 281 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); |
aaa36a97 | 282 | else |
c65444fe | 283 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); |
c113ea1c | 284 | err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); |
aaa36a97 AD |
285 | if (err) |
286 | goto out; | |
c113ea1c | 287 | err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); |
aaa36a97 AD |
288 | if (err) |
289 | goto out; | |
c113ea1c AD |
290 | hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; |
291 | adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); | |
292 | adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); | |
293 | if (adev->sdma.instance[i].feature_version >= 20) | |
294 | adev->sdma.instance[i].burst_nop = true; | |
aaa36a97 AD |
295 | |
296 | if (adev->firmware.smu_load) { | |
297 | info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; | |
298 | info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; | |
c113ea1c | 299 | info->fw = adev->sdma.instance[i].fw; |
aaa36a97 AD |
300 | header = (const struct common_firmware_header *)info->fw->data; |
301 | adev->firmware.fw_size += | |
302 | ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); | |
303 | } | |
304 | } | |
305 | out: | |
306 | if (err) { | |
307 | printk(KERN_ERR | |
308 | "sdma_v3_0: Failed to load firmware \"%s\"\n", | |
309 | fw_name); | |
c113ea1c AD |
310 | for (i = 0; i < adev->sdma.num_instances; i++) { |
311 | release_firmware(adev->sdma.instance[i].fw); | |
312 | adev->sdma.instance[i].fw = NULL; | |
aaa36a97 AD |
313 | } |
314 | } | |
315 | return err; | |
316 | } | |
317 | ||
318 | /** | |
319 | * sdma_v3_0_ring_get_rptr - get the current read pointer | |
320 | * | |
321 | * @ring: amdgpu ring pointer | |
322 | * | |
323 | * Get the current rptr from the hardware (VI+). | |
324 | */ | |
325 | static uint32_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring) | |
326 | { | |
327 | u32 rptr; | |
328 | ||
329 | /* XXX check if swapping is necessary on BE */ | |
330 | rptr = ring->adev->wb.wb[ring->rptr_offs] >> 2; | |
331 | ||
332 | return rptr; | |
333 | } | |
334 | ||
335 | /** | |
336 | * sdma_v3_0_ring_get_wptr - get the current write pointer | |
337 | * | |
338 | * @ring: amdgpu ring pointer | |
339 | * | |
340 | * Get the current wptr from the hardware (VI+). | |
341 | */ | |
342 | static uint32_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring) | |
343 | { | |
344 | struct amdgpu_device *adev = ring->adev; | |
345 | u32 wptr; | |
346 | ||
347 | if (ring->use_doorbell) { | |
348 | /* XXX check if swapping is necessary on BE */ | |
349 | wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2; | |
350 | } else { | |
c113ea1c | 351 | int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1; |
aaa36a97 AD |
352 | |
353 | wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2; | |
354 | } | |
355 | ||
356 | return wptr; | |
357 | } | |
358 | ||
359 | /** | |
360 | * sdma_v3_0_ring_set_wptr - commit the write pointer | |
361 | * | |
362 | * @ring: amdgpu ring pointer | |
363 | * | |
364 | * Write the wptr back to the hardware (VI+). | |
365 | */ | |
366 | static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring) | |
367 | { | |
368 | struct amdgpu_device *adev = ring->adev; | |
369 | ||
370 | if (ring->use_doorbell) { | |
371 | /* XXX check if swapping is necessary on BE */ | |
372 | adev->wb.wb[ring->wptr_offs] = ring->wptr << 2; | |
373 | WDOORBELL32(ring->doorbell_index, ring->wptr << 2); | |
374 | } else { | |
c113ea1c | 375 | int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1; |
aaa36a97 AD |
376 | |
377 | WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2); | |
378 | } | |
379 | } | |
380 | ||
ac01db3d JZ |
381 | static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) |
382 | { | |
c113ea1c | 383 | struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); |
ac01db3d JZ |
384 | int i; |
385 | ||
386 | for (i = 0; i < count; i++) | |
387 | if (sdma && sdma->burst_nop && (i == 0)) | |
388 | amdgpu_ring_write(ring, ring->nop | | |
389 | SDMA_PKT_NOP_HEADER_COUNT(count - 1)); | |
390 | else | |
391 | amdgpu_ring_write(ring, ring->nop); | |
392 | } | |
393 | ||
aaa36a97 AD |
394 | /** |
395 | * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine | |
396 | * | |
397 | * @ring: amdgpu ring pointer | |
398 | * @ib: IB object to schedule | |
399 | * | |
400 | * Schedule an IB in the DMA ring (VI). | |
401 | */ | |
402 | static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring, | |
f153d286 | 403 | struct amdgpu_ib *ib, bool ctx_switch) |
aaa36a97 | 404 | { |
4ff37a83 | 405 | u32 vmid = ib->vm_id & 0xf; |
aaa36a97 AD |
406 | u32 next_rptr = ring->wptr + 5; |
407 | ||
aaa36a97 AD |
408 | while ((next_rptr & 7) != 2) |
409 | next_rptr++; | |
410 | next_rptr += 6; | |
411 | ||
412 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | | |
413 | SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); | |
414 | amdgpu_ring_write(ring, lower_32_bits(ring->next_rptr_gpu_addr) & 0xfffffffc); | |
415 | amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr)); | |
416 | amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); | |
417 | amdgpu_ring_write(ring, next_rptr); | |
418 | ||
aaa36a97 | 419 | /* IB packet must end on a 8 DW boundary */ |
ac01db3d | 420 | sdma_v3_0_ring_insert_nop(ring, (10 - (ring->wptr & 7)) % 8); |
aaa36a97 AD |
421 | |
422 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | | |
423 | SDMA_PKT_INDIRECT_HEADER_VMID(vmid)); | |
424 | /* base must be 32 byte aligned */ | |
425 | amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); | |
426 | amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); | |
427 | amdgpu_ring_write(ring, ib->length_dw); | |
428 | amdgpu_ring_write(ring, 0); | |
429 | amdgpu_ring_write(ring, 0); | |
430 | ||
431 | } | |
432 | ||
433 | /** | |
d2edb07b | 434 | * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring |
aaa36a97 AD |
435 | * |
436 | * @ring: amdgpu ring pointer | |
437 | * | |
438 | * Emit an hdp flush packet on the requested DMA ring. | |
439 | */ | |
d2edb07b | 440 | static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) |
aaa36a97 AD |
441 | { |
442 | u32 ref_and_mask = 0; | |
443 | ||
c113ea1c | 444 | if (ring == &ring->adev->sdma.instance[0].ring) |
aaa36a97 AD |
445 | ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); |
446 | else | |
447 | ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); | |
448 | ||
449 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | | |
450 | SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | | |
451 | SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ | |
452 | amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); | |
453 | amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2); | |
454 | amdgpu_ring_write(ring, ref_and_mask); /* reference */ | |
455 | amdgpu_ring_write(ring, ref_and_mask); /* mask */ | |
456 | amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | | |
457 | SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ | |
458 | } | |
459 | ||
cc958e67 CZ |
460 | static void sdma_v3_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) |
461 | { | |
462 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | | |
463 | SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); | |
464 | amdgpu_ring_write(ring, mmHDP_DEBUG0); | |
465 | amdgpu_ring_write(ring, 1); | |
466 | } | |
467 | ||
aaa36a97 AD |
468 | /** |
469 | * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring | |
470 | * | |
471 | * @ring: amdgpu ring pointer | |
472 | * @fence: amdgpu fence object | |
473 | * | |
474 | * Add a DMA fence packet to the ring to write | |
475 | * the fence seq number and DMA trap packet to generate | |
476 | * an interrupt if needed (VI). | |
477 | */ | |
478 | static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, | |
890ee23f | 479 | unsigned flags) |
aaa36a97 | 480 | { |
890ee23f | 481 | bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; |
aaa36a97 AD |
482 | /* write the fence */ |
483 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); | |
484 | amdgpu_ring_write(ring, lower_32_bits(addr)); | |
485 | amdgpu_ring_write(ring, upper_32_bits(addr)); | |
486 | amdgpu_ring_write(ring, lower_32_bits(seq)); | |
487 | ||
488 | /* optionally write high bits as well */ | |
890ee23f | 489 | if (write64bit) { |
aaa36a97 AD |
490 | addr += 4; |
491 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); | |
492 | amdgpu_ring_write(ring, lower_32_bits(addr)); | |
493 | amdgpu_ring_write(ring, upper_32_bits(addr)); | |
494 | amdgpu_ring_write(ring, upper_32_bits(seq)); | |
495 | } | |
496 | ||
497 | /* generate an interrupt */ | |
498 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); | |
499 | amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); | |
500 | } | |
501 | ||
03ccf481 ML |
502 | unsigned init_cond_exec(struct amdgpu_ring *ring) |
503 | { | |
504 | unsigned ret; | |
505 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE)); | |
506 | amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); | |
507 | amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); | |
508 | amdgpu_ring_write(ring, 1); | |
509 | ret = ring->wptr;/* this is the offset we need patch later */ | |
510 | amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */ | |
511 | return ret; | |
512 | } | |
513 | ||
514 | void patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) | |
515 | { | |
516 | unsigned cur; | |
517 | BUG_ON(ring->ring[offset] != 0x55aa55aa); | |
518 | ||
519 | cur = ring->wptr - 1; | |
520 | if (likely(cur > offset)) | |
521 | ring->ring[offset] = cur - offset; | |
522 | else | |
523 | ring->ring[offset] = (ring->ring_size>>2) - offset + cur; | |
524 | } | |
525 | ||
526 | ||
aaa36a97 AD |
527 | /** |
528 | * sdma_v3_0_gfx_stop - stop the gfx async dma engines | |
529 | * | |
530 | * @adev: amdgpu_device pointer | |
531 | * | |
532 | * Stop the gfx async dma ring buffers (VI). | |
533 | */ | |
534 | static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev) | |
535 | { | |
c113ea1c AD |
536 | struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; |
537 | struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; | |
aaa36a97 AD |
538 | u32 rb_cntl, ib_cntl; |
539 | int i; | |
540 | ||
541 | if ((adev->mman.buffer_funcs_ring == sdma0) || | |
542 | (adev->mman.buffer_funcs_ring == sdma1)) | |
543 | amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size); | |
544 | ||
c113ea1c | 545 | for (i = 0; i < adev->sdma.num_instances; i++) { |
aaa36a97 AD |
546 | rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); |
547 | rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); | |
548 | WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); | |
549 | ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); | |
550 | ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); | |
551 | WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); | |
552 | } | |
553 | sdma0->ready = false; | |
554 | sdma1->ready = false; | |
555 | } | |
556 | ||
557 | /** | |
558 | * sdma_v3_0_rlc_stop - stop the compute async dma engines | |
559 | * | |
560 | * @adev: amdgpu_device pointer | |
561 | * | |
562 | * Stop the compute async dma queues (VI). | |
563 | */ | |
564 | static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev) | |
565 | { | |
566 | /* XXX todo */ | |
567 | } | |
568 | ||
cd06bf68 BG |
569 | /** |
570 | * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch | |
571 | * | |
572 | * @adev: amdgpu_device pointer | |
573 | * @enable: enable/disable the DMA MEs context switch. | |
574 | * | |
575 | * Halt or unhalt the async dma engines context switch (VI). | |
576 | */ | |
577 | static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) | |
578 | { | |
579 | u32 f32_cntl; | |
580 | int i; | |
581 | ||
c113ea1c | 582 | for (i = 0; i < adev->sdma.num_instances; i++) { |
cd06bf68 BG |
583 | f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); |
584 | if (enable) | |
585 | f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, | |
586 | AUTO_CTXSW_ENABLE, 1); | |
587 | else | |
588 | f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, | |
589 | AUTO_CTXSW_ENABLE, 0); | |
590 | WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl); | |
591 | } | |
592 | } | |
593 | ||
aaa36a97 AD |
594 | /** |
595 | * sdma_v3_0_enable - stop the async dma engines | |
596 | * | |
597 | * @adev: amdgpu_device pointer | |
598 | * @enable: enable/disable the DMA MEs. | |
599 | * | |
600 | * Halt or unhalt the async dma engines (VI). | |
601 | */ | |
602 | static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable) | |
603 | { | |
604 | u32 f32_cntl; | |
605 | int i; | |
606 | ||
607 | if (enable == false) { | |
608 | sdma_v3_0_gfx_stop(adev); | |
609 | sdma_v3_0_rlc_stop(adev); | |
610 | } | |
611 | ||
c113ea1c | 612 | for (i = 0; i < adev->sdma.num_instances; i++) { |
aaa36a97 AD |
613 | f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); |
614 | if (enable) | |
615 | f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0); | |
616 | else | |
617 | f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); | |
618 | WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl); | |
619 | } | |
620 | } | |
621 | ||
622 | /** | |
623 | * sdma_v3_0_gfx_resume - setup and start the async dma engines | |
624 | * | |
625 | * @adev: amdgpu_device pointer | |
626 | * | |
627 | * Set up the gfx DMA ring buffers and enable them (VI). | |
628 | * Returns 0 for success, error for failure. | |
629 | */ | |
630 | static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev) | |
631 | { | |
632 | struct amdgpu_ring *ring; | |
633 | u32 rb_cntl, ib_cntl; | |
634 | u32 rb_bufsz; | |
635 | u32 wb_offset; | |
636 | u32 doorbell; | |
637 | int i, j, r; | |
638 | ||
c113ea1c AD |
639 | for (i = 0; i < adev->sdma.num_instances; i++) { |
640 | ring = &adev->sdma.instance[i].ring; | |
aaa36a97 AD |
641 | wb_offset = (ring->rptr_offs * 4); |
642 | ||
643 | mutex_lock(&adev->srbm_mutex); | |
644 | for (j = 0; j < 16; j++) { | |
645 | vi_srbm_select(adev, 0, 0, 0, j); | |
646 | /* SDMA GFX */ | |
647 | WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0); | |
648 | WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0); | |
649 | } | |
650 | vi_srbm_select(adev, 0, 0, 0, 0); | |
651 | mutex_unlock(&adev->srbm_mutex); | |
652 | ||
c458fe94 AD |
653 | WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i], |
654 | adev->gfx.config.gb_addr_config & 0x70); | |
655 | ||
aaa36a97 AD |
656 | WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); |
657 | ||
658 | /* Set ring buffer size in dwords */ | |
659 | rb_bufsz = order_base_2(ring->ring_size / 4); | |
660 | rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); | |
661 | rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); | |
662 | #ifdef __BIG_ENDIAN | |
663 | rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); | |
664 | rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, | |
665 | RPTR_WRITEBACK_SWAP_ENABLE, 1); | |
666 | #endif | |
667 | WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); | |
668 | ||
669 | /* Initialize the ring buffer's read and write pointers */ | |
670 | WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); | |
671 | WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); | |
672 | ||
673 | /* set the wb address whether it's enabled or not */ | |
674 | WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], | |
675 | upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); | |
676 | WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], | |
677 | lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); | |
678 | ||
679 | rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); | |
680 | ||
681 | WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); | |
682 | WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); | |
683 | ||
684 | ring->wptr = 0; | |
685 | WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2); | |
686 | ||
687 | doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]); | |
688 | ||
689 | if (ring->use_doorbell) { | |
690 | doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, | |
691 | OFFSET, ring->doorbell_index); | |
692 | doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); | |
693 | } else { | |
694 | doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); | |
695 | } | |
696 | WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell); | |
697 | ||
698 | /* enable DMA RB */ | |
699 | rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); | |
700 | WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); | |
701 | ||
702 | ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); | |
703 | ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); | |
704 | #ifdef __BIG_ENDIAN | |
705 | ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); | |
706 | #endif | |
707 | /* enable DMA IBs */ | |
708 | WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); | |
709 | ||
710 | ring->ready = true; | |
711 | ||
712 | r = amdgpu_ring_test_ring(ring); | |
713 | if (r) { | |
714 | ring->ready = false; | |
715 | return r; | |
716 | } | |
717 | ||
718 | if (adev->mman.buffer_funcs_ring == ring) | |
719 | amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size); | |
720 | } | |
721 | ||
722 | return 0; | |
723 | } | |
724 | ||
725 | /** | |
726 | * sdma_v3_0_rlc_resume - setup and start the async dma engines | |
727 | * | |
728 | * @adev: amdgpu_device pointer | |
729 | * | |
730 | * Set up the compute DMA queues and enable them (VI). | |
731 | * Returns 0 for success, error for failure. | |
732 | */ | |
733 | static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev) | |
734 | { | |
735 | /* XXX todo */ | |
736 | return 0; | |
737 | } | |
738 | ||
739 | /** | |
740 | * sdma_v3_0_load_microcode - load the sDMA ME ucode | |
741 | * | |
742 | * @adev: amdgpu_device pointer | |
743 | * | |
744 | * Loads the sDMA0/1 ucode. | |
745 | * Returns 0 for success, -EINVAL if the ucode is not available. | |
746 | */ | |
747 | static int sdma_v3_0_load_microcode(struct amdgpu_device *adev) | |
748 | { | |
749 | const struct sdma_firmware_header_v1_0 *hdr; | |
750 | const __le32 *fw_data; | |
751 | u32 fw_size; | |
752 | int i, j; | |
753 | ||
aaa36a97 AD |
754 | /* halt the MEs */ |
755 | sdma_v3_0_enable(adev, false); | |
756 | ||
c113ea1c AD |
757 | for (i = 0; i < adev->sdma.num_instances; i++) { |
758 | if (!adev->sdma.instance[i].fw) | |
759 | return -EINVAL; | |
760 | hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; | |
aaa36a97 AD |
761 | amdgpu_ucode_print_sdma_hdr(&hdr->header); |
762 | fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; | |
aaa36a97 | 763 | fw_data = (const __le32 *) |
c113ea1c | 764 | (adev->sdma.instance[i].fw->data + |
aaa36a97 AD |
765 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); |
766 | WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0); | |
767 | for (j = 0; j < fw_size; j++) | |
768 | WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++)); | |
c113ea1c | 769 | WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version); |
aaa36a97 AD |
770 | } |
771 | ||
772 | return 0; | |
773 | } | |
774 | ||
775 | /** | |
776 | * sdma_v3_0_start - setup and start the async dma engines | |
777 | * | |
778 | * @adev: amdgpu_device pointer | |
779 | * | |
780 | * Set up the DMA engines and enable them (VI). | |
781 | * Returns 0 for success, error for failure. | |
782 | */ | |
783 | static int sdma_v3_0_start(struct amdgpu_device *adev) | |
784 | { | |
c113ea1c | 785 | int r, i; |
aaa36a97 | 786 | |
e61710c5 | 787 | if (!adev->pp_enabled) { |
ba5c2a87 RZ |
788 | if (!adev->firmware.smu_load) { |
789 | r = sdma_v3_0_load_microcode(adev); | |
c113ea1c | 790 | if (r) |
ba5c2a87 RZ |
791 | return r; |
792 | } else { | |
793 | for (i = 0; i < adev->sdma.num_instances; i++) { | |
794 | r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, | |
795 | (i == 0) ? | |
796 | AMDGPU_UCODE_ID_SDMA0 : | |
797 | AMDGPU_UCODE_ID_SDMA1); | |
798 | if (r) | |
799 | return -EINVAL; | |
800 | } | |
c113ea1c | 801 | } |
aaa36a97 AD |
802 | } |
803 | ||
804 | /* unhalt the MEs */ | |
805 | sdma_v3_0_enable(adev, true); | |
cd06bf68 BG |
806 | /* enable sdma ring preemption */ |
807 | sdma_v3_0_ctx_switch_enable(adev, true); | |
aaa36a97 AD |
808 | |
809 | /* start the gfx rings and rlc compute queues */ | |
810 | r = sdma_v3_0_gfx_resume(adev); | |
811 | if (r) | |
812 | return r; | |
813 | r = sdma_v3_0_rlc_resume(adev); | |
814 | if (r) | |
815 | return r; | |
816 | ||
817 | return 0; | |
818 | } | |
819 | ||
820 | /** | |
821 | * sdma_v3_0_ring_test_ring - simple async dma engine test | |
822 | * | |
823 | * @ring: amdgpu_ring structure holding ring information | |
824 | * | |
825 | * Test the DMA engine by writing using it to write an | |
826 | * value to memory. (VI). | |
827 | * Returns 0 for success, error for failure. | |
828 | */ | |
829 | static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring) | |
830 | { | |
831 | struct amdgpu_device *adev = ring->adev; | |
832 | unsigned i; | |
833 | unsigned index; | |
834 | int r; | |
835 | u32 tmp; | |
836 | u64 gpu_addr; | |
837 | ||
838 | r = amdgpu_wb_get(adev, &index); | |
839 | if (r) { | |
840 | dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); | |
841 | return r; | |
842 | } | |
843 | ||
844 | gpu_addr = adev->wb.gpu_addr + (index * 4); | |
845 | tmp = 0xCAFEDEAD; | |
846 | adev->wb.wb[index] = cpu_to_le32(tmp); | |
847 | ||
a27de35c | 848 | r = amdgpu_ring_alloc(ring, 5); |
aaa36a97 AD |
849 | if (r) { |
850 | DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); | |
851 | amdgpu_wb_free(adev, index); | |
852 | return r; | |
853 | } | |
854 | ||
855 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | | |
856 | SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); | |
857 | amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); | |
858 | amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); | |
859 | amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); | |
860 | amdgpu_ring_write(ring, 0xDEADBEEF); | |
a27de35c | 861 | amdgpu_ring_commit(ring); |
aaa36a97 AD |
862 | |
863 | for (i = 0; i < adev->usec_timeout; i++) { | |
864 | tmp = le32_to_cpu(adev->wb.wb[index]); | |
865 | if (tmp == 0xDEADBEEF) | |
866 | break; | |
867 | DRM_UDELAY(1); | |
868 | } | |
869 | ||
870 | if (i < adev->usec_timeout) { | |
871 | DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); | |
872 | } else { | |
873 | DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", | |
874 | ring->idx, tmp); | |
875 | r = -EINVAL; | |
876 | } | |
877 | amdgpu_wb_free(adev, index); | |
878 | ||
879 | return r; | |
880 | } | |
881 | ||
882 | /** | |
883 | * sdma_v3_0_ring_test_ib - test an IB on the DMA engine | |
884 | * | |
885 | * @ring: amdgpu_ring structure holding ring information | |
886 | * | |
887 | * Test a simple IB in the DMA ring (VI). | |
888 | * Returns 0 on success, error on failure. | |
889 | */ | |
890 | static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring) | |
891 | { | |
892 | struct amdgpu_device *adev = ring->adev; | |
893 | struct amdgpu_ib ib; | |
1763552e | 894 | struct fence *f = NULL; |
aaa36a97 AD |
895 | unsigned i; |
896 | unsigned index; | |
897 | int r; | |
898 | u32 tmp = 0; | |
899 | u64 gpu_addr; | |
900 | ||
901 | r = amdgpu_wb_get(adev, &index); | |
902 | if (r) { | |
903 | dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); | |
904 | return r; | |
905 | } | |
906 | ||
907 | gpu_addr = adev->wb.gpu_addr + (index * 4); | |
908 | tmp = 0xCAFEDEAD; | |
909 | adev->wb.wb[index] = cpu_to_le32(tmp); | |
b203dd95 | 910 | memset(&ib, 0, sizeof(ib)); |
b07c60c0 | 911 | r = amdgpu_ib_get(adev, NULL, 256, &ib); |
aaa36a97 | 912 | if (r) { |
aaa36a97 | 913 | DRM_ERROR("amdgpu: failed to get ib (%d).\n", r); |
0011fdaa | 914 | goto err0; |
aaa36a97 AD |
915 | } |
916 | ||
917 | ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | | |
918 | SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); | |
919 | ib.ptr[1] = lower_32_bits(gpu_addr); | |
920 | ib.ptr[2] = upper_32_bits(gpu_addr); | |
921 | ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1); | |
922 | ib.ptr[4] = 0xDEADBEEF; | |
923 | ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); | |
924 | ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); | |
925 | ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); | |
926 | ib.length_dw = 8; | |
927 | ||
c5637837 | 928 | r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f); |
0011fdaa CZ |
929 | if (r) |
930 | goto err1; | |
931 | ||
1763552e | 932 | r = fence_wait(f, false); |
aaa36a97 | 933 | if (r) { |
aaa36a97 | 934 | DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); |
0011fdaa | 935 | goto err1; |
aaa36a97 AD |
936 | } |
937 | for (i = 0; i < adev->usec_timeout; i++) { | |
938 | tmp = le32_to_cpu(adev->wb.wb[index]); | |
939 | if (tmp == 0xDEADBEEF) | |
940 | break; | |
941 | DRM_UDELAY(1); | |
942 | } | |
943 | if (i < adev->usec_timeout) { | |
944 | DRM_INFO("ib test on ring %d succeeded in %u usecs\n", | |
0011fdaa CZ |
945 | ring->idx, i); |
946 | goto err1; | |
aaa36a97 AD |
947 | } else { |
948 | DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); | |
949 | r = -EINVAL; | |
950 | } | |
0011fdaa | 951 | err1: |
281b4223 | 952 | fence_put(f); |
cc55c45d | 953 | amdgpu_ib_free(adev, &ib, NULL); |
73cfa5f5 | 954 | fence_put(f); |
0011fdaa | 955 | err0: |
aaa36a97 AD |
956 | amdgpu_wb_free(adev, index); |
957 | return r; | |
958 | } | |
959 | ||
960 | /** | |
961 | * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART | |
962 | * | |
963 | * @ib: indirect buffer to fill with commands | |
964 | * @pe: addr of the page entry | |
965 | * @src: src addr to copy from | |
966 | * @count: number of page entries to update | |
967 | * | |
968 | * Update PTEs by copying them from the GART using sDMA (CIK). | |
969 | */ | |
970 | static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib, | |
971 | uint64_t pe, uint64_t src, | |
972 | unsigned count) | |
973 | { | |
974 | while (count) { | |
975 | unsigned bytes = count * 8; | |
976 | if (bytes > 0x1FFFF8) | |
977 | bytes = 0x1FFFF8; | |
978 | ||
979 | ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | | |
980 | SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); | |
981 | ib->ptr[ib->length_dw++] = bytes; | |
982 | ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ | |
983 | ib->ptr[ib->length_dw++] = lower_32_bits(src); | |
984 | ib->ptr[ib->length_dw++] = upper_32_bits(src); | |
985 | ib->ptr[ib->length_dw++] = lower_32_bits(pe); | |
986 | ib->ptr[ib->length_dw++] = upper_32_bits(pe); | |
987 | ||
988 | pe += bytes; | |
989 | src += bytes; | |
990 | count -= bytes / 8; | |
991 | } | |
992 | } | |
993 | ||
994 | /** | |
995 | * sdma_v3_0_vm_write_pte - update PTEs by writing them manually | |
996 | * | |
997 | * @ib: indirect buffer to fill with commands | |
998 | * @pe: addr of the page entry | |
999 | * @addr: dst addr to write into pe | |
1000 | * @count: number of page entries to update | |
1001 | * @incr: increase next addr by incr bytes | |
1002 | * @flags: access flags | |
1003 | * | |
1004 | * Update PTEs by writing them manually using sDMA (CIK). | |
1005 | */ | |
1006 | static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, | |
b07c9d2a | 1007 | const dma_addr_t *pages_addr, uint64_t pe, |
aaa36a97 AD |
1008 | uint64_t addr, unsigned count, |
1009 | uint32_t incr, uint32_t flags) | |
1010 | { | |
1011 | uint64_t value; | |
1012 | unsigned ndw; | |
1013 | ||
1014 | while (count) { | |
1015 | ndw = count * 2; | |
1016 | if (ndw > 0xFFFFE) | |
1017 | ndw = 0xFFFFE; | |
1018 | ||
1019 | /* for non-physically contiguous pages (system) */ | |
1020 | ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | | |
1021 | SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); | |
1022 | ib->ptr[ib->length_dw++] = pe; | |
1023 | ib->ptr[ib->length_dw++] = upper_32_bits(pe); | |
1024 | ib->ptr[ib->length_dw++] = ndw; | |
1025 | for (; ndw > 0; ndw -= 2, --count, pe += 8) { | |
b07c9d2a | 1026 | value = amdgpu_vm_map_gart(pages_addr, addr); |
aaa36a97 AD |
1027 | addr += incr; |
1028 | value |= flags; | |
1029 | ib->ptr[ib->length_dw++] = value; | |
1030 | ib->ptr[ib->length_dw++] = upper_32_bits(value); | |
1031 | } | |
1032 | } | |
1033 | } | |
1034 | ||
1035 | /** | |
1036 | * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA | |
1037 | * | |
1038 | * @ib: indirect buffer to fill with commands | |
1039 | * @pe: addr of the page entry | |
1040 | * @addr: dst addr to write into pe | |
1041 | * @count: number of page entries to update | |
1042 | * @incr: increase next addr by incr bytes | |
1043 | * @flags: access flags | |
1044 | * | |
1045 | * Update the page tables using sDMA (CIK). | |
1046 | */ | |
1047 | static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib, | |
1048 | uint64_t pe, | |
1049 | uint64_t addr, unsigned count, | |
1050 | uint32_t incr, uint32_t flags) | |
1051 | { | |
1052 | uint64_t value; | |
1053 | unsigned ndw; | |
1054 | ||
1055 | while (count) { | |
1056 | ndw = count; | |
1057 | if (ndw > 0x7FFFF) | |
1058 | ndw = 0x7FFFF; | |
1059 | ||
1060 | if (flags & AMDGPU_PTE_VALID) | |
1061 | value = addr; | |
1062 | else | |
1063 | value = 0; | |
1064 | ||
1065 | /* for physically contiguous pages (vram) */ | |
1066 | ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE); | |
1067 | ib->ptr[ib->length_dw++] = pe; /* dst addr */ | |
1068 | ib->ptr[ib->length_dw++] = upper_32_bits(pe); | |
1069 | ib->ptr[ib->length_dw++] = flags; /* mask */ | |
1070 | ib->ptr[ib->length_dw++] = 0; | |
1071 | ib->ptr[ib->length_dw++] = value; /* value */ | |
1072 | ib->ptr[ib->length_dw++] = upper_32_bits(value); | |
1073 | ib->ptr[ib->length_dw++] = incr; /* increment size */ | |
1074 | ib->ptr[ib->length_dw++] = 0; | |
1075 | ib->ptr[ib->length_dw++] = ndw; /* number of entries */ | |
1076 | ||
1077 | pe += ndw * 8; | |
1078 | addr += ndw * incr; | |
1079 | count -= ndw; | |
1080 | } | |
1081 | } | |
1082 | ||
1083 | /** | |
9e5d5309 | 1084 | * sdma_v3_0_ring_pad_ib - pad the IB to the required number of dw |
aaa36a97 AD |
1085 | * |
1086 | * @ib: indirect buffer to fill with padding | |
1087 | * | |
1088 | */ | |
9e5d5309 | 1089 | static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) |
aaa36a97 | 1090 | { |
9e5d5309 | 1091 | struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); |
ac01db3d JZ |
1092 | u32 pad_count; |
1093 | int i; | |
1094 | ||
1095 | pad_count = (8 - (ib->length_dw & 0x7)) % 8; | |
1096 | for (i = 0; i < pad_count; i++) | |
1097 | if (sdma && sdma->burst_nop && (i == 0)) | |
1098 | ib->ptr[ib->length_dw++] = | |
1099 | SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | | |
1100 | SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); | |
1101 | else | |
1102 | ib->ptr[ib->length_dw++] = | |
1103 | SDMA_PKT_HEADER_OP(SDMA_OP_NOP); | |
aaa36a97 AD |
1104 | } |
1105 | ||
1106 | /** | |
00b7c4ff | 1107 | * sdma_v3_0_ring_emit_pipeline_sync - sync the pipeline |
aaa36a97 AD |
1108 | * |
1109 | * @ring: amdgpu_ring pointer | |
aaa36a97 | 1110 | * |
00b7c4ff | 1111 | * Make sure all previous operations are completed (CIK). |
aaa36a97 | 1112 | */ |
00b7c4ff | 1113 | static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) |
aaa36a97 | 1114 | { |
5c55db83 CZ |
1115 | uint32_t seq = ring->fence_drv.sync_seq; |
1116 | uint64_t addr = ring->fence_drv.gpu_addr; | |
1117 | ||
1118 | /* wait for idle */ | |
1119 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | | |
1120 | SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | | |
1121 | SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ | |
1122 | SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); | |
1123 | amdgpu_ring_write(ring, addr & 0xfffffffc); | |
1124 | amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); | |
1125 | amdgpu_ring_write(ring, seq); /* reference */ | |
1126 | amdgpu_ring_write(ring, 0xfffffff); /* mask */ | |
1127 | amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | | |
1128 | SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ | |
00b7c4ff | 1129 | } |
5c55db83 | 1130 | |
00b7c4ff CK |
1131 | /** |
1132 | * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA | |
1133 | * | |
1134 | * @ring: amdgpu_ring pointer | |
1135 | * @vm: amdgpu_vm pointer | |
1136 | * | |
1137 | * Update the page table base and flush the VM TLB | |
1138 | * using sDMA (VI). | |
1139 | */ | |
1140 | static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring, | |
1141 | unsigned vm_id, uint64_t pd_addr) | |
1142 | { | |
aaa36a97 AD |
1143 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | |
1144 | SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); | |
1145 | if (vm_id < 8) { | |
1146 | amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id)); | |
1147 | } else { | |
1148 | amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8)); | |
1149 | } | |
1150 | amdgpu_ring_write(ring, pd_addr >> 12); | |
1151 | ||
aaa36a97 AD |
1152 | /* flush TLB */ |
1153 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | | |
1154 | SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); | |
1155 | amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); | |
1156 | amdgpu_ring_write(ring, 1 << vm_id); | |
1157 | ||
1158 | /* wait for flush */ | |
1159 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | | |
1160 | SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | | |
1161 | SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */ | |
1162 | amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2); | |
1163 | amdgpu_ring_write(ring, 0); | |
1164 | amdgpu_ring_write(ring, 0); /* reference */ | |
1165 | amdgpu_ring_write(ring, 0); /* mask */ | |
1166 | amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | | |
1167 | SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ | |
1168 | } | |
1169 | ||
5fc3aeeb | 1170 | static int sdma_v3_0_early_init(void *handle) |
aaa36a97 | 1171 | { |
5fc3aeeb | 1172 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1173 | ||
c113ea1c | 1174 | switch (adev->asic_type) { |
bb16e3b6 SL |
1175 | case CHIP_STONEY: |
1176 | adev->sdma.num_instances = 1; | |
1177 | break; | |
c113ea1c AD |
1178 | default: |
1179 | adev->sdma.num_instances = SDMA_MAX_INSTANCE; | |
1180 | break; | |
1181 | } | |
1182 | ||
aaa36a97 AD |
1183 | sdma_v3_0_set_ring_funcs(adev); |
1184 | sdma_v3_0_set_buffer_funcs(adev); | |
1185 | sdma_v3_0_set_vm_pte_funcs(adev); | |
1186 | sdma_v3_0_set_irq_funcs(adev); | |
1187 | ||
1188 | return 0; | |
1189 | } | |
1190 | ||
5fc3aeeb | 1191 | static int sdma_v3_0_sw_init(void *handle) |
aaa36a97 AD |
1192 | { |
1193 | struct amdgpu_ring *ring; | |
c113ea1c | 1194 | int r, i; |
5fc3aeeb | 1195 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
aaa36a97 AD |
1196 | |
1197 | /* SDMA trap event */ | |
c113ea1c | 1198 | r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq); |
aaa36a97 AD |
1199 | if (r) |
1200 | return r; | |
1201 | ||
1202 | /* SDMA Privileged inst */ | |
c113ea1c | 1203 | r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq); |
aaa36a97 AD |
1204 | if (r) |
1205 | return r; | |
1206 | ||
1207 | /* SDMA Privileged inst */ | |
c113ea1c | 1208 | r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq); |
aaa36a97 AD |
1209 | if (r) |
1210 | return r; | |
1211 | ||
1212 | r = sdma_v3_0_init_microcode(adev); | |
1213 | if (r) { | |
1214 | DRM_ERROR("Failed to load sdma firmware!\n"); | |
1215 | return r; | |
1216 | } | |
1217 | ||
c113ea1c AD |
1218 | for (i = 0; i < adev->sdma.num_instances; i++) { |
1219 | ring = &adev->sdma.instance[i].ring; | |
1220 | ring->ring_obj = NULL; | |
1221 | ring->use_doorbell = true; | |
1222 | ring->doorbell_index = (i == 0) ? | |
1223 | AMDGPU_DOORBELL_sDMA_ENGINE0 : AMDGPU_DOORBELL_sDMA_ENGINE1; | |
1224 | ||
1225 | sprintf(ring->name, "sdma%d", i); | |
b38d99c4 | 1226 | r = amdgpu_ring_init(adev, ring, 1024, |
c113ea1c AD |
1227 | SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf, |
1228 | &adev->sdma.trap_irq, | |
1229 | (i == 0) ? | |
1230 | AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1, | |
1231 | AMDGPU_RING_TYPE_SDMA); | |
1232 | if (r) | |
1233 | return r; | |
1234 | } | |
aaa36a97 AD |
1235 | |
1236 | return r; | |
1237 | } | |
1238 | ||
5fc3aeeb | 1239 | static int sdma_v3_0_sw_fini(void *handle) |
aaa36a97 | 1240 | { |
5fc3aeeb | 1241 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
c113ea1c | 1242 | int i; |
5fc3aeeb | 1243 | |
c113ea1c AD |
1244 | for (i = 0; i < adev->sdma.num_instances; i++) |
1245 | amdgpu_ring_fini(&adev->sdma.instance[i].ring); | |
aaa36a97 AD |
1246 | |
1247 | return 0; | |
1248 | } | |
1249 | ||
5fc3aeeb | 1250 | static int sdma_v3_0_hw_init(void *handle) |
aaa36a97 AD |
1251 | { |
1252 | int r; | |
5fc3aeeb | 1253 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
aaa36a97 AD |
1254 | |
1255 | sdma_v3_0_init_golden_registers(adev); | |
1256 | ||
1257 | r = sdma_v3_0_start(adev); | |
1258 | if (r) | |
1259 | return r; | |
1260 | ||
1261 | return r; | |
1262 | } | |
1263 | ||
5fc3aeeb | 1264 | static int sdma_v3_0_hw_fini(void *handle) |
aaa36a97 | 1265 | { |
5fc3aeeb | 1266 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1267 | ||
cd06bf68 | 1268 | sdma_v3_0_ctx_switch_enable(adev, false); |
aaa36a97 AD |
1269 | sdma_v3_0_enable(adev, false); |
1270 | ||
1271 | return 0; | |
1272 | } | |
1273 | ||
5fc3aeeb | 1274 | static int sdma_v3_0_suspend(void *handle) |
aaa36a97 | 1275 | { |
5fc3aeeb | 1276 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
aaa36a97 AD |
1277 | |
1278 | return sdma_v3_0_hw_fini(adev); | |
1279 | } | |
1280 | ||
5fc3aeeb | 1281 | static int sdma_v3_0_resume(void *handle) |
aaa36a97 | 1282 | { |
5fc3aeeb | 1283 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
aaa36a97 AD |
1284 | |
1285 | return sdma_v3_0_hw_init(adev); | |
1286 | } | |
1287 | ||
5fc3aeeb | 1288 | static bool sdma_v3_0_is_idle(void *handle) |
aaa36a97 | 1289 | { |
5fc3aeeb | 1290 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
aaa36a97 AD |
1291 | u32 tmp = RREG32(mmSRBM_STATUS2); |
1292 | ||
1293 | if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK | | |
1294 | SRBM_STATUS2__SDMA1_BUSY_MASK)) | |
1295 | return false; | |
1296 | ||
1297 | return true; | |
1298 | } | |
1299 | ||
5fc3aeeb | 1300 | static int sdma_v3_0_wait_for_idle(void *handle) |
aaa36a97 AD |
1301 | { |
1302 | unsigned i; | |
1303 | u32 tmp; | |
5fc3aeeb | 1304 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
aaa36a97 AD |
1305 | |
1306 | for (i = 0; i < adev->usec_timeout; i++) { | |
1307 | tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | | |
1308 | SRBM_STATUS2__SDMA1_BUSY_MASK); | |
1309 | ||
1310 | if (!tmp) | |
1311 | return 0; | |
1312 | udelay(1); | |
1313 | } | |
1314 | return -ETIMEDOUT; | |
1315 | } | |
1316 | ||
5fc3aeeb | 1317 | static int sdma_v3_0_soft_reset(void *handle) |
aaa36a97 AD |
1318 | { |
1319 | u32 srbm_soft_reset = 0; | |
5fc3aeeb | 1320 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
aaa36a97 AD |
1321 | u32 tmp = RREG32(mmSRBM_STATUS2); |
1322 | ||
1323 | if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) { | |
1324 | /* sdma0 */ | |
1325 | tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); | |
1326 | tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0); | |
1327 | WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); | |
1328 | srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK; | |
1329 | } | |
1330 | if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) { | |
1331 | /* sdma1 */ | |
1332 | tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); | |
1333 | tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0); | |
1334 | WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); | |
1335 | srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK; | |
1336 | } | |
1337 | ||
1338 | if (srbm_soft_reset) { | |
aaa36a97 AD |
1339 | tmp = RREG32(mmSRBM_SOFT_RESET); |
1340 | tmp |= srbm_soft_reset; | |
1341 | dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); | |
1342 | WREG32(mmSRBM_SOFT_RESET, tmp); | |
1343 | tmp = RREG32(mmSRBM_SOFT_RESET); | |
1344 | ||
1345 | udelay(50); | |
1346 | ||
1347 | tmp &= ~srbm_soft_reset; | |
1348 | WREG32(mmSRBM_SOFT_RESET, tmp); | |
1349 | tmp = RREG32(mmSRBM_SOFT_RESET); | |
1350 | ||
1351 | /* Wait a little for things to settle down */ | |
1352 | udelay(50); | |
aaa36a97 AD |
1353 | } |
1354 | ||
1355 | return 0; | |
1356 | } | |
1357 | ||
1358 | static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev, | |
1359 | struct amdgpu_irq_src *source, | |
1360 | unsigned type, | |
1361 | enum amdgpu_interrupt_state state) | |
1362 | { | |
1363 | u32 sdma_cntl; | |
1364 | ||
1365 | switch (type) { | |
1366 | case AMDGPU_SDMA_IRQ_TRAP0: | |
1367 | switch (state) { | |
1368 | case AMDGPU_IRQ_STATE_DISABLE: | |
1369 | sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); | |
1370 | sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); | |
1371 | WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); | |
1372 | break; | |
1373 | case AMDGPU_IRQ_STATE_ENABLE: | |
1374 | sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); | |
1375 | sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); | |
1376 | WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); | |
1377 | break; | |
1378 | default: | |
1379 | break; | |
1380 | } | |
1381 | break; | |
1382 | case AMDGPU_SDMA_IRQ_TRAP1: | |
1383 | switch (state) { | |
1384 | case AMDGPU_IRQ_STATE_DISABLE: | |
1385 | sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); | |
1386 | sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); | |
1387 | WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); | |
1388 | break; | |
1389 | case AMDGPU_IRQ_STATE_ENABLE: | |
1390 | sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); | |
1391 | sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); | |
1392 | WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); | |
1393 | break; | |
1394 | default: | |
1395 | break; | |
1396 | } | |
1397 | break; | |
1398 | default: | |
1399 | break; | |
1400 | } | |
1401 | return 0; | |
1402 | } | |
1403 | ||
1404 | static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev, | |
1405 | struct amdgpu_irq_src *source, | |
1406 | struct amdgpu_iv_entry *entry) | |
1407 | { | |
1408 | u8 instance_id, queue_id; | |
1409 | ||
1410 | instance_id = (entry->ring_id & 0x3) >> 0; | |
1411 | queue_id = (entry->ring_id & 0xc) >> 2; | |
1412 | DRM_DEBUG("IH: SDMA trap\n"); | |
1413 | switch (instance_id) { | |
1414 | case 0: | |
1415 | switch (queue_id) { | |
1416 | case 0: | |
c113ea1c | 1417 | amdgpu_fence_process(&adev->sdma.instance[0].ring); |
aaa36a97 AD |
1418 | break; |
1419 | case 1: | |
1420 | /* XXX compute */ | |
1421 | break; | |
1422 | case 2: | |
1423 | /* XXX compute */ | |
1424 | break; | |
1425 | } | |
1426 | break; | |
1427 | case 1: | |
1428 | switch (queue_id) { | |
1429 | case 0: | |
c113ea1c | 1430 | amdgpu_fence_process(&adev->sdma.instance[1].ring); |
aaa36a97 AD |
1431 | break; |
1432 | case 1: | |
1433 | /* XXX compute */ | |
1434 | break; | |
1435 | case 2: | |
1436 | /* XXX compute */ | |
1437 | break; | |
1438 | } | |
1439 | break; | |
1440 | } | |
1441 | return 0; | |
1442 | } | |
1443 | ||
1444 | static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev, | |
1445 | struct amdgpu_irq_src *source, | |
1446 | struct amdgpu_iv_entry *entry) | |
1447 | { | |
1448 | DRM_ERROR("Illegal instruction in SDMA command stream\n"); | |
1449 | schedule_work(&adev->reset_work); | |
1450 | return 0; | |
1451 | } | |
1452 | ||
ce22362b | 1453 | static void sdma_v3_0_update_sdma_medium_grain_clock_gating( |
3c997d24 EH |
1454 | struct amdgpu_device *adev, |
1455 | bool enable) | |
1456 | { | |
1457 | uint32_t temp, data; | |
ce22362b | 1458 | int i; |
3c997d24 | 1459 | |
e08d53cb | 1460 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { |
ce22362b AD |
1461 | for (i = 0; i < adev->sdma.num_instances; i++) { |
1462 | temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]); | |
1463 | data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | | |
1464 | SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | | |
1465 | SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | | |
1466 | SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | | |
1467 | SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | | |
1468 | SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | | |
1469 | SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | | |
1470 | SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); | |
1471 | if (data != temp) | |
1472 | WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data); | |
1473 | } | |
3c997d24 | 1474 | } else { |
ce22362b AD |
1475 | for (i = 0; i < adev->sdma.num_instances; i++) { |
1476 | temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]); | |
1477 | data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | | |
3c997d24 EH |
1478 | SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | |
1479 | SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | | |
1480 | SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | | |
1481 | SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | | |
1482 | SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | | |
1483 | SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | | |
1484 | SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK; | |
1485 | ||
ce22362b AD |
1486 | if (data != temp) |
1487 | WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data); | |
1488 | } | |
3c997d24 EH |
1489 | } |
1490 | } | |
1491 | ||
ce22362b | 1492 | static void sdma_v3_0_update_sdma_medium_grain_light_sleep( |
3c997d24 EH |
1493 | struct amdgpu_device *adev, |
1494 | bool enable) | |
1495 | { | |
1496 | uint32_t temp, data; | |
ce22362b | 1497 | int i; |
3c997d24 | 1498 | |
e08d53cb | 1499 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { |
ce22362b AD |
1500 | for (i = 0; i < adev->sdma.num_instances; i++) { |
1501 | temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]); | |
1502 | data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; | |
3c997d24 | 1503 | |
ce22362b AD |
1504 | if (temp != data) |
1505 | WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data); | |
1506 | } | |
3c997d24 | 1507 | } else { |
ce22362b AD |
1508 | for (i = 0; i < adev->sdma.num_instances; i++) { |
1509 | temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]); | |
1510 | data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; | |
3c997d24 | 1511 | |
ce22362b AD |
1512 | if (temp != data) |
1513 | WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data); | |
1514 | } | |
3c997d24 EH |
1515 | } |
1516 | } | |
1517 | ||
5fc3aeeb | 1518 | static int sdma_v3_0_set_clockgating_state(void *handle, |
1519 | enum amd_clockgating_state state) | |
aaa36a97 | 1520 | { |
3c997d24 EH |
1521 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1522 | ||
1523 | switch (adev->asic_type) { | |
1524 | case CHIP_FIJI: | |
ce22362b AD |
1525 | case CHIP_CARRIZO: |
1526 | case CHIP_STONEY: | |
1527 | sdma_v3_0_update_sdma_medium_grain_clock_gating(adev, | |
3c997d24 | 1528 | state == AMD_CG_STATE_GATE ? true : false); |
ce22362b | 1529 | sdma_v3_0_update_sdma_medium_grain_light_sleep(adev, |
3c997d24 EH |
1530 | state == AMD_CG_STATE_GATE ? true : false); |
1531 | break; | |
1532 | default: | |
1533 | break; | |
1534 | } | |
aaa36a97 AD |
1535 | return 0; |
1536 | } | |
1537 | ||
5fc3aeeb | 1538 | static int sdma_v3_0_set_powergating_state(void *handle, |
1539 | enum amd_powergating_state state) | |
aaa36a97 AD |
1540 | { |
1541 | return 0; | |
1542 | } | |
1543 | ||
5fc3aeeb | 1544 | const struct amd_ip_funcs sdma_v3_0_ip_funcs = { |
88a907d6 | 1545 | .name = "sdma_v3_0", |
aaa36a97 AD |
1546 | .early_init = sdma_v3_0_early_init, |
1547 | .late_init = NULL, | |
1548 | .sw_init = sdma_v3_0_sw_init, | |
1549 | .sw_fini = sdma_v3_0_sw_fini, | |
1550 | .hw_init = sdma_v3_0_hw_init, | |
1551 | .hw_fini = sdma_v3_0_hw_fini, | |
1552 | .suspend = sdma_v3_0_suspend, | |
1553 | .resume = sdma_v3_0_resume, | |
1554 | .is_idle = sdma_v3_0_is_idle, | |
1555 | .wait_for_idle = sdma_v3_0_wait_for_idle, | |
1556 | .soft_reset = sdma_v3_0_soft_reset, | |
aaa36a97 AD |
1557 | .set_clockgating_state = sdma_v3_0_set_clockgating_state, |
1558 | .set_powergating_state = sdma_v3_0_set_powergating_state, | |
1559 | }; | |
1560 | ||
aaa36a97 AD |
1561 | static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = { |
1562 | .get_rptr = sdma_v3_0_ring_get_rptr, | |
1563 | .get_wptr = sdma_v3_0_ring_get_wptr, | |
1564 | .set_wptr = sdma_v3_0_ring_set_wptr, | |
1565 | .parse_cs = NULL, | |
1566 | .emit_ib = sdma_v3_0_ring_emit_ib, | |
1567 | .emit_fence = sdma_v3_0_ring_emit_fence, | |
00b7c4ff | 1568 | .emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync, |
aaa36a97 | 1569 | .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush, |
d2edb07b | 1570 | .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush, |
cc958e67 | 1571 | .emit_hdp_invalidate = sdma_v3_0_ring_emit_hdp_invalidate, |
aaa36a97 AD |
1572 | .test_ring = sdma_v3_0_ring_test_ring, |
1573 | .test_ib = sdma_v3_0_ring_test_ib, | |
ac01db3d | 1574 | .insert_nop = sdma_v3_0_ring_insert_nop, |
9e5d5309 | 1575 | .pad_ib = sdma_v3_0_ring_pad_ib, |
aaa36a97 AD |
1576 | }; |
1577 | ||
1578 | static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev) | |
1579 | { | |
c113ea1c AD |
1580 | int i; |
1581 | ||
1582 | for (i = 0; i < adev->sdma.num_instances; i++) | |
1583 | adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs; | |
aaa36a97 AD |
1584 | } |
1585 | ||
1586 | static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = { | |
1587 | .set = sdma_v3_0_set_trap_irq_state, | |
1588 | .process = sdma_v3_0_process_trap_irq, | |
1589 | }; | |
1590 | ||
1591 | static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = { | |
1592 | .process = sdma_v3_0_process_illegal_inst_irq, | |
1593 | }; | |
1594 | ||
1595 | static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev) | |
1596 | { | |
c113ea1c AD |
1597 | adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; |
1598 | adev->sdma.trap_irq.funcs = &sdma_v3_0_trap_irq_funcs; | |
1599 | adev->sdma.illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs; | |
aaa36a97 AD |
1600 | } |
1601 | ||
1602 | /** | |
1603 | * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine | |
1604 | * | |
1605 | * @ring: amdgpu_ring structure holding ring information | |
1606 | * @src_offset: src GPU address | |
1607 | * @dst_offset: dst GPU address | |
1608 | * @byte_count: number of bytes to xfer | |
1609 | * | |
1610 | * Copy GPU buffers using the DMA engine (VI). | |
1611 | * Used by the amdgpu ttm implementation to move pages if | |
1612 | * registered as the asic copy callback. | |
1613 | */ | |
c7ae72c0 | 1614 | static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib, |
aaa36a97 AD |
1615 | uint64_t src_offset, |
1616 | uint64_t dst_offset, | |
1617 | uint32_t byte_count) | |
1618 | { | |
c7ae72c0 CZ |
1619 | ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | |
1620 | SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); | |
1621 | ib->ptr[ib->length_dw++] = byte_count; | |
1622 | ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ | |
1623 | ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); | |
1624 | ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); | |
1625 | ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); | |
1626 | ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); | |
aaa36a97 AD |
1627 | } |
1628 | ||
1629 | /** | |
1630 | * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine | |
1631 | * | |
1632 | * @ring: amdgpu_ring structure holding ring information | |
1633 | * @src_data: value to write to buffer | |
1634 | * @dst_offset: dst GPU address | |
1635 | * @byte_count: number of bytes to xfer | |
1636 | * | |
1637 | * Fill GPU buffers using the DMA engine (VI). | |
1638 | */ | |
6e7a3840 | 1639 | static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib, |
aaa36a97 AD |
1640 | uint32_t src_data, |
1641 | uint64_t dst_offset, | |
1642 | uint32_t byte_count) | |
1643 | { | |
6e7a3840 CZ |
1644 | ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); |
1645 | ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); | |
1646 | ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); | |
1647 | ib->ptr[ib->length_dw++] = src_data; | |
1648 | ib->ptr[ib->length_dw++] = byte_count; | |
aaa36a97 AD |
1649 | } |
1650 | ||
1651 | static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = { | |
1652 | .copy_max_bytes = 0x1fffff, | |
1653 | .copy_num_dw = 7, | |
1654 | .emit_copy_buffer = sdma_v3_0_emit_copy_buffer, | |
1655 | ||
1656 | .fill_max_bytes = 0x1fffff, | |
1657 | .fill_num_dw = 5, | |
1658 | .emit_fill_buffer = sdma_v3_0_emit_fill_buffer, | |
1659 | }; | |
1660 | ||
1661 | static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev) | |
1662 | { | |
1663 | if (adev->mman.buffer_funcs == NULL) { | |
1664 | adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs; | |
c113ea1c | 1665 | adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; |
aaa36a97 AD |
1666 | } |
1667 | } | |
1668 | ||
1669 | static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = { | |
1670 | .copy_pte = sdma_v3_0_vm_copy_pte, | |
1671 | .write_pte = sdma_v3_0_vm_write_pte, | |
1672 | .set_pte_pde = sdma_v3_0_vm_set_pte_pde, | |
aaa36a97 AD |
1673 | }; |
1674 | ||
1675 | static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev) | |
1676 | { | |
2d55e45a CK |
1677 | unsigned i; |
1678 | ||
aaa36a97 AD |
1679 | if (adev->vm_manager.vm_pte_funcs == NULL) { |
1680 | adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs; | |
2d55e45a CK |
1681 | for (i = 0; i < adev->sdma.num_instances; i++) |
1682 | adev->vm_manager.vm_pte_rings[i] = | |
1683 | &adev->sdma.instance[i].ring; | |
1684 | ||
1685 | adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances; | |
aaa36a97 AD |
1686 | } |
1687 | } |