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aaa36a97 AD |
1 | /* |
2 | * Copyright 2014 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Alex Deucher | |
23 | */ | |
24 | #include <linux/firmware.h> | |
25 | #include <drm/drmP.h> | |
26 | #include "amdgpu.h" | |
27 | #include "amdgpu_ucode.h" | |
28 | #include "amdgpu_trace.h" | |
29 | #include "vi.h" | |
30 | #include "vid.h" | |
31 | ||
32 | #include "oss/oss_3_0_d.h" | |
33 | #include "oss/oss_3_0_sh_mask.h" | |
34 | ||
35 | #include "gmc/gmc_8_1_d.h" | |
36 | #include "gmc/gmc_8_1_sh_mask.h" | |
37 | ||
38 | #include "gca/gfx_8_0_d.h" | |
74a5d165 | 39 | #include "gca/gfx_8_0_enum.h" |
aaa36a97 AD |
40 | #include "gca/gfx_8_0_sh_mask.h" |
41 | ||
42 | #include "bif/bif_5_0_d.h" | |
43 | #include "bif/bif_5_0_sh_mask.h" | |
44 | ||
45 | #include "tonga_sdma_pkt_open.h" | |
46 | ||
47 | static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev); | |
48 | static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev); | |
49 | static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev); | |
50 | static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev); | |
51 | ||
c65444fe JZ |
52 | MODULE_FIRMWARE("amdgpu/tonga_sdma.bin"); |
53 | MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin"); | |
54 | MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin"); | |
55 | MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin"); | |
1a5bbb66 DZ |
56 | MODULE_FIRMWARE("amdgpu/fiji_sdma.bin"); |
57 | MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin"); | |
bb16e3b6 | 58 | MODULE_FIRMWARE("amdgpu/stoney_sdma.bin"); |
2cc0c0b5 FC |
59 | MODULE_FIRMWARE("amdgpu/polaris10_sdma.bin"); |
60 | MODULE_FIRMWARE("amdgpu/polaris10_sdma1.bin"); | |
61 | MODULE_FIRMWARE("amdgpu/polaris11_sdma.bin"); | |
62 | MODULE_FIRMWARE("amdgpu/polaris11_sdma1.bin"); | |
2cea03de | 63 | |
aaa36a97 AD |
64 | |
65 | static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = | |
66 | { | |
67 | SDMA0_REGISTER_OFFSET, | |
68 | SDMA1_REGISTER_OFFSET | |
69 | }; | |
70 | ||
71 | static const u32 golden_settings_tonga_a11[] = | |
72 | { | |
73 | mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, | |
74 | mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, | |
75 | mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, | |
76 | mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, | |
77 | mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, | |
78 | mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, | |
79 | mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, | |
80 | mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, | |
81 | mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, | |
82 | mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, | |
83 | }; | |
84 | ||
85 | static const u32 tonga_mgcg_cgcg_init[] = | |
86 | { | |
87 | mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, | |
88 | mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 | |
89 | }; | |
90 | ||
1a5bbb66 DZ |
91 | static const u32 golden_settings_fiji_a10[] = |
92 | { | |
93 | mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, | |
94 | mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, | |
95 | mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, | |
96 | mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, | |
97 | mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, | |
98 | mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, | |
99 | mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, | |
100 | mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, | |
101 | }; | |
102 | ||
103 | static const u32 fiji_mgcg_cgcg_init[] = | |
104 | { | |
105 | mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, | |
106 | mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 | |
107 | }; | |
108 | ||
2cc0c0b5 | 109 | static const u32 golden_settings_polaris11_a11[] = |
2cea03de FC |
110 | { |
111 | mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, | |
b9934878 | 112 | mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, |
2cea03de FC |
113 | mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, |
114 | mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, | |
115 | mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, | |
116 | mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, | |
b9934878 | 117 | mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, |
2cea03de FC |
118 | mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, |
119 | mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, | |
120 | mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, | |
121 | }; | |
122 | ||
2cc0c0b5 | 123 | static const u32 golden_settings_polaris10_a11[] = |
2cea03de FC |
124 | { |
125 | mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, | |
126 | mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, | |
127 | mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, | |
128 | mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, | |
129 | mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, | |
130 | mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, | |
131 | mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, | |
132 | mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, | |
133 | mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, | |
134 | mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, | |
135 | }; | |
136 | ||
aaa36a97 AD |
137 | static const u32 cz_golden_settings_a11[] = |
138 | { | |
139 | mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, | |
140 | mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, | |
141 | mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100, | |
142 | mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800, | |
143 | mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100, | |
144 | mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100, | |
145 | mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, | |
146 | mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, | |
147 | mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100, | |
148 | mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800, | |
149 | mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100, | |
150 | mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100, | |
151 | }; | |
152 | ||
153 | static const u32 cz_mgcg_cgcg_init[] = | |
154 | { | |
155 | mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, | |
156 | mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 | |
157 | }; | |
158 | ||
bb16e3b6 SL |
159 | static const u32 stoney_golden_settings_a11[] = |
160 | { | |
161 | mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100, | |
162 | mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800, | |
163 | mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100, | |
164 | mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100, | |
165 | }; | |
166 | ||
167 | static const u32 stoney_mgcg_cgcg_init[] = | |
168 | { | |
169 | mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100, | |
170 | }; | |
171 | ||
aaa36a97 AD |
172 | /* |
173 | * sDMA - System DMA | |
174 | * Starting with CIK, the GPU has new asynchronous | |
175 | * DMA engines. These engines are used for compute | |
176 | * and gfx. There are two DMA engines (SDMA0, SDMA1) | |
177 | * and each one supports 1 ring buffer used for gfx | |
178 | * and 2 queues used for compute. | |
179 | * | |
180 | * The programming model is very similar to the CP | |
181 | * (ring buffer, IBs, etc.), but sDMA has it's own | |
182 | * packet format that is different from the PM4 format | |
183 | * used by the CP. sDMA supports copying data, writing | |
184 | * embedded data, solid fills, and a number of other | |
185 | * things. It also has support for tiling/detiling of | |
186 | * buffers. | |
187 | */ | |
188 | ||
189 | static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev) | |
190 | { | |
191 | switch (adev->asic_type) { | |
1a5bbb66 DZ |
192 | case CHIP_FIJI: |
193 | amdgpu_program_register_sequence(adev, | |
194 | fiji_mgcg_cgcg_init, | |
195 | (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init)); | |
196 | amdgpu_program_register_sequence(adev, | |
197 | golden_settings_fiji_a10, | |
198 | (const u32)ARRAY_SIZE(golden_settings_fiji_a10)); | |
199 | break; | |
aaa36a97 AD |
200 | case CHIP_TONGA: |
201 | amdgpu_program_register_sequence(adev, | |
202 | tonga_mgcg_cgcg_init, | |
203 | (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); | |
204 | amdgpu_program_register_sequence(adev, | |
205 | golden_settings_tonga_a11, | |
206 | (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); | |
207 | break; | |
2cc0c0b5 | 208 | case CHIP_POLARIS11: |
2cea03de | 209 | amdgpu_program_register_sequence(adev, |
2cc0c0b5 FC |
210 | golden_settings_polaris11_a11, |
211 | (const u32)ARRAY_SIZE(golden_settings_polaris11_a11)); | |
2cea03de | 212 | break; |
2cc0c0b5 | 213 | case CHIP_POLARIS10: |
2cea03de | 214 | amdgpu_program_register_sequence(adev, |
2cc0c0b5 FC |
215 | golden_settings_polaris10_a11, |
216 | (const u32)ARRAY_SIZE(golden_settings_polaris10_a11)); | |
2cea03de | 217 | break; |
aaa36a97 AD |
218 | case CHIP_CARRIZO: |
219 | amdgpu_program_register_sequence(adev, | |
220 | cz_mgcg_cgcg_init, | |
221 | (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); | |
222 | amdgpu_program_register_sequence(adev, | |
223 | cz_golden_settings_a11, | |
224 | (const u32)ARRAY_SIZE(cz_golden_settings_a11)); | |
225 | break; | |
bb16e3b6 SL |
226 | case CHIP_STONEY: |
227 | amdgpu_program_register_sequence(adev, | |
228 | stoney_mgcg_cgcg_init, | |
229 | (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init)); | |
230 | amdgpu_program_register_sequence(adev, | |
231 | stoney_golden_settings_a11, | |
232 | (const u32)ARRAY_SIZE(stoney_golden_settings_a11)); | |
233 | break; | |
aaa36a97 AD |
234 | default: |
235 | break; | |
236 | } | |
237 | } | |
238 | ||
239 | /** | |
240 | * sdma_v3_0_init_microcode - load ucode images from disk | |
241 | * | |
242 | * @adev: amdgpu_device pointer | |
243 | * | |
244 | * Use the firmware interface to load the ucode images into | |
245 | * the driver (not loaded into hw). | |
246 | * Returns 0 on success, error on failure. | |
247 | */ | |
248 | static int sdma_v3_0_init_microcode(struct amdgpu_device *adev) | |
249 | { | |
250 | const char *chip_name; | |
251 | char fw_name[30]; | |
c113ea1c | 252 | int err = 0, i; |
aaa36a97 AD |
253 | struct amdgpu_firmware_info *info = NULL; |
254 | const struct common_firmware_header *header = NULL; | |
595fd013 | 255 | const struct sdma_firmware_header_v1_0 *hdr; |
aaa36a97 AD |
256 | |
257 | DRM_DEBUG("\n"); | |
258 | ||
259 | switch (adev->asic_type) { | |
260 | case CHIP_TONGA: | |
261 | chip_name = "tonga"; | |
262 | break; | |
1a5bbb66 DZ |
263 | case CHIP_FIJI: |
264 | chip_name = "fiji"; | |
265 | break; | |
2cc0c0b5 FC |
266 | case CHIP_POLARIS11: |
267 | chip_name = "polaris11"; | |
2cea03de | 268 | break; |
2cc0c0b5 FC |
269 | case CHIP_POLARIS10: |
270 | chip_name = "polaris10"; | |
2cea03de | 271 | break; |
aaa36a97 AD |
272 | case CHIP_CARRIZO: |
273 | chip_name = "carrizo"; | |
274 | break; | |
bb16e3b6 SL |
275 | case CHIP_STONEY: |
276 | chip_name = "stoney"; | |
277 | break; | |
aaa36a97 AD |
278 | default: BUG(); |
279 | } | |
280 | ||
c113ea1c | 281 | for (i = 0; i < adev->sdma.num_instances; i++) { |
aaa36a97 | 282 | if (i == 0) |
c65444fe | 283 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); |
aaa36a97 | 284 | else |
c65444fe | 285 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); |
c113ea1c | 286 | err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); |
aaa36a97 AD |
287 | if (err) |
288 | goto out; | |
c113ea1c | 289 | err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); |
aaa36a97 AD |
290 | if (err) |
291 | goto out; | |
c113ea1c AD |
292 | hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; |
293 | adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); | |
294 | adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); | |
295 | if (adev->sdma.instance[i].feature_version >= 20) | |
296 | adev->sdma.instance[i].burst_nop = true; | |
aaa36a97 AD |
297 | |
298 | if (adev->firmware.smu_load) { | |
299 | info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; | |
300 | info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; | |
c113ea1c | 301 | info->fw = adev->sdma.instance[i].fw; |
aaa36a97 AD |
302 | header = (const struct common_firmware_header *)info->fw->data; |
303 | adev->firmware.fw_size += | |
304 | ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); | |
305 | } | |
306 | } | |
307 | out: | |
308 | if (err) { | |
309 | printk(KERN_ERR | |
310 | "sdma_v3_0: Failed to load firmware \"%s\"\n", | |
311 | fw_name); | |
c113ea1c AD |
312 | for (i = 0; i < adev->sdma.num_instances; i++) { |
313 | release_firmware(adev->sdma.instance[i].fw); | |
314 | adev->sdma.instance[i].fw = NULL; | |
aaa36a97 AD |
315 | } |
316 | } | |
317 | return err; | |
318 | } | |
319 | ||
320 | /** | |
321 | * sdma_v3_0_ring_get_rptr - get the current read pointer | |
322 | * | |
323 | * @ring: amdgpu ring pointer | |
324 | * | |
325 | * Get the current rptr from the hardware (VI+). | |
326 | */ | |
327 | static uint32_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring) | |
328 | { | |
329 | u32 rptr; | |
330 | ||
331 | /* XXX check if swapping is necessary on BE */ | |
332 | rptr = ring->adev->wb.wb[ring->rptr_offs] >> 2; | |
333 | ||
334 | return rptr; | |
335 | } | |
336 | ||
337 | /** | |
338 | * sdma_v3_0_ring_get_wptr - get the current write pointer | |
339 | * | |
340 | * @ring: amdgpu ring pointer | |
341 | * | |
342 | * Get the current wptr from the hardware (VI+). | |
343 | */ | |
344 | static uint32_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring) | |
345 | { | |
346 | struct amdgpu_device *adev = ring->adev; | |
347 | u32 wptr; | |
348 | ||
349 | if (ring->use_doorbell) { | |
350 | /* XXX check if swapping is necessary on BE */ | |
351 | wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2; | |
352 | } else { | |
c113ea1c | 353 | int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1; |
aaa36a97 AD |
354 | |
355 | wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2; | |
356 | } | |
357 | ||
358 | return wptr; | |
359 | } | |
360 | ||
361 | /** | |
362 | * sdma_v3_0_ring_set_wptr - commit the write pointer | |
363 | * | |
364 | * @ring: amdgpu ring pointer | |
365 | * | |
366 | * Write the wptr back to the hardware (VI+). | |
367 | */ | |
368 | static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring) | |
369 | { | |
370 | struct amdgpu_device *adev = ring->adev; | |
371 | ||
372 | if (ring->use_doorbell) { | |
373 | /* XXX check if swapping is necessary on BE */ | |
374 | adev->wb.wb[ring->wptr_offs] = ring->wptr << 2; | |
375 | WDOORBELL32(ring->doorbell_index, ring->wptr << 2); | |
376 | } else { | |
c113ea1c | 377 | int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1; |
aaa36a97 AD |
378 | |
379 | WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2); | |
380 | } | |
381 | } | |
382 | ||
ac01db3d JZ |
383 | static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) |
384 | { | |
c113ea1c | 385 | struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); |
ac01db3d JZ |
386 | int i; |
387 | ||
388 | for (i = 0; i < count; i++) | |
389 | if (sdma && sdma->burst_nop && (i == 0)) | |
390 | amdgpu_ring_write(ring, ring->nop | | |
391 | SDMA_PKT_NOP_HEADER_COUNT(count - 1)); | |
392 | else | |
393 | amdgpu_ring_write(ring, ring->nop); | |
394 | } | |
395 | ||
aaa36a97 AD |
396 | /** |
397 | * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine | |
398 | * | |
399 | * @ring: amdgpu ring pointer | |
400 | * @ib: IB object to schedule | |
401 | * | |
402 | * Schedule an IB in the DMA ring (VI). | |
403 | */ | |
404 | static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring, | |
d88bf583 CK |
405 | struct amdgpu_ib *ib, |
406 | unsigned vm_id, bool ctx_switch) | |
aaa36a97 | 407 | { |
d88bf583 | 408 | u32 vmid = vm_id & 0xf; |
aaa36a97 AD |
409 | u32 next_rptr = ring->wptr + 5; |
410 | ||
aaa36a97 AD |
411 | while ((next_rptr & 7) != 2) |
412 | next_rptr++; | |
413 | next_rptr += 6; | |
414 | ||
415 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | | |
416 | SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); | |
417 | amdgpu_ring_write(ring, lower_32_bits(ring->next_rptr_gpu_addr) & 0xfffffffc); | |
418 | amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr)); | |
419 | amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); | |
420 | amdgpu_ring_write(ring, next_rptr); | |
421 | ||
aaa36a97 | 422 | /* IB packet must end on a 8 DW boundary */ |
ac01db3d | 423 | sdma_v3_0_ring_insert_nop(ring, (10 - (ring->wptr & 7)) % 8); |
aaa36a97 AD |
424 | |
425 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | | |
426 | SDMA_PKT_INDIRECT_HEADER_VMID(vmid)); | |
427 | /* base must be 32 byte aligned */ | |
428 | amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); | |
429 | amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); | |
430 | amdgpu_ring_write(ring, ib->length_dw); | |
431 | amdgpu_ring_write(ring, 0); | |
432 | amdgpu_ring_write(ring, 0); | |
433 | ||
434 | } | |
435 | ||
436 | /** | |
d2edb07b | 437 | * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring |
aaa36a97 AD |
438 | * |
439 | * @ring: amdgpu ring pointer | |
440 | * | |
441 | * Emit an hdp flush packet on the requested DMA ring. | |
442 | */ | |
d2edb07b | 443 | static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) |
aaa36a97 AD |
444 | { |
445 | u32 ref_and_mask = 0; | |
446 | ||
c113ea1c | 447 | if (ring == &ring->adev->sdma.instance[0].ring) |
aaa36a97 AD |
448 | ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); |
449 | else | |
450 | ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); | |
451 | ||
452 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | | |
453 | SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | | |
454 | SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ | |
455 | amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); | |
456 | amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2); | |
457 | amdgpu_ring_write(ring, ref_and_mask); /* reference */ | |
458 | amdgpu_ring_write(ring, ref_and_mask); /* mask */ | |
459 | amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | | |
460 | SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ | |
461 | } | |
462 | ||
cc958e67 CZ |
463 | static void sdma_v3_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) |
464 | { | |
465 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | | |
466 | SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); | |
467 | amdgpu_ring_write(ring, mmHDP_DEBUG0); | |
468 | amdgpu_ring_write(ring, 1); | |
469 | } | |
470 | ||
aaa36a97 AD |
471 | /** |
472 | * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring | |
473 | * | |
474 | * @ring: amdgpu ring pointer | |
475 | * @fence: amdgpu fence object | |
476 | * | |
477 | * Add a DMA fence packet to the ring to write | |
478 | * the fence seq number and DMA trap packet to generate | |
479 | * an interrupt if needed (VI). | |
480 | */ | |
481 | static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, | |
890ee23f | 482 | unsigned flags) |
aaa36a97 | 483 | { |
890ee23f | 484 | bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; |
aaa36a97 AD |
485 | /* write the fence */ |
486 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); | |
487 | amdgpu_ring_write(ring, lower_32_bits(addr)); | |
488 | amdgpu_ring_write(ring, upper_32_bits(addr)); | |
489 | amdgpu_ring_write(ring, lower_32_bits(seq)); | |
490 | ||
491 | /* optionally write high bits as well */ | |
890ee23f | 492 | if (write64bit) { |
aaa36a97 AD |
493 | addr += 4; |
494 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); | |
495 | amdgpu_ring_write(ring, lower_32_bits(addr)); | |
496 | amdgpu_ring_write(ring, upper_32_bits(addr)); | |
497 | amdgpu_ring_write(ring, upper_32_bits(seq)); | |
498 | } | |
499 | ||
500 | /* generate an interrupt */ | |
501 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); | |
502 | amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); | |
503 | } | |
504 | ||
03ccf481 ML |
505 | unsigned init_cond_exec(struct amdgpu_ring *ring) |
506 | { | |
507 | unsigned ret; | |
508 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE)); | |
509 | amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); | |
510 | amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); | |
511 | amdgpu_ring_write(ring, 1); | |
512 | ret = ring->wptr;/* this is the offset we need patch later */ | |
513 | amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */ | |
514 | return ret; | |
515 | } | |
516 | ||
517 | void patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) | |
518 | { | |
519 | unsigned cur; | |
520 | BUG_ON(ring->ring[offset] != 0x55aa55aa); | |
521 | ||
522 | cur = ring->wptr - 1; | |
523 | if (likely(cur > offset)) | |
524 | ring->ring[offset] = cur - offset; | |
525 | else | |
526 | ring->ring[offset] = (ring->ring_size>>2) - offset + cur; | |
527 | } | |
528 | ||
529 | ||
aaa36a97 AD |
530 | /** |
531 | * sdma_v3_0_gfx_stop - stop the gfx async dma engines | |
532 | * | |
533 | * @adev: amdgpu_device pointer | |
534 | * | |
535 | * Stop the gfx async dma ring buffers (VI). | |
536 | */ | |
537 | static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev) | |
538 | { | |
c113ea1c AD |
539 | struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; |
540 | struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; | |
aaa36a97 AD |
541 | u32 rb_cntl, ib_cntl; |
542 | int i; | |
543 | ||
544 | if ((adev->mman.buffer_funcs_ring == sdma0) || | |
545 | (adev->mman.buffer_funcs_ring == sdma1)) | |
546 | amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size); | |
547 | ||
c113ea1c | 548 | for (i = 0; i < adev->sdma.num_instances; i++) { |
aaa36a97 AD |
549 | rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); |
550 | rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); | |
551 | WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); | |
552 | ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); | |
553 | ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); | |
554 | WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); | |
555 | } | |
556 | sdma0->ready = false; | |
557 | sdma1->ready = false; | |
558 | } | |
559 | ||
560 | /** | |
561 | * sdma_v3_0_rlc_stop - stop the compute async dma engines | |
562 | * | |
563 | * @adev: amdgpu_device pointer | |
564 | * | |
565 | * Stop the compute async dma queues (VI). | |
566 | */ | |
567 | static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev) | |
568 | { | |
569 | /* XXX todo */ | |
570 | } | |
571 | ||
cd06bf68 BG |
572 | /** |
573 | * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch | |
574 | * | |
575 | * @adev: amdgpu_device pointer | |
576 | * @enable: enable/disable the DMA MEs context switch. | |
577 | * | |
578 | * Halt or unhalt the async dma engines context switch (VI). | |
579 | */ | |
580 | static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) | |
581 | { | |
582 | u32 f32_cntl; | |
583 | int i; | |
584 | ||
c113ea1c | 585 | for (i = 0; i < adev->sdma.num_instances; i++) { |
cd06bf68 BG |
586 | f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); |
587 | if (enable) | |
588 | f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, | |
589 | AUTO_CTXSW_ENABLE, 1); | |
590 | else | |
591 | f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, | |
592 | AUTO_CTXSW_ENABLE, 0); | |
593 | WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl); | |
594 | } | |
595 | } | |
596 | ||
aaa36a97 AD |
597 | /** |
598 | * sdma_v3_0_enable - stop the async dma engines | |
599 | * | |
600 | * @adev: amdgpu_device pointer | |
601 | * @enable: enable/disable the DMA MEs. | |
602 | * | |
603 | * Halt or unhalt the async dma engines (VI). | |
604 | */ | |
605 | static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable) | |
606 | { | |
607 | u32 f32_cntl; | |
608 | int i; | |
609 | ||
610 | if (enable == false) { | |
611 | sdma_v3_0_gfx_stop(adev); | |
612 | sdma_v3_0_rlc_stop(adev); | |
613 | } | |
614 | ||
c113ea1c | 615 | for (i = 0; i < adev->sdma.num_instances; i++) { |
aaa36a97 AD |
616 | f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); |
617 | if (enable) | |
618 | f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0); | |
619 | else | |
620 | f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); | |
621 | WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl); | |
622 | } | |
623 | } | |
624 | ||
625 | /** | |
626 | * sdma_v3_0_gfx_resume - setup and start the async dma engines | |
627 | * | |
628 | * @adev: amdgpu_device pointer | |
629 | * | |
630 | * Set up the gfx DMA ring buffers and enable them (VI). | |
631 | * Returns 0 for success, error for failure. | |
632 | */ | |
633 | static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev) | |
634 | { | |
635 | struct amdgpu_ring *ring; | |
636 | u32 rb_cntl, ib_cntl; | |
637 | u32 rb_bufsz; | |
638 | u32 wb_offset; | |
639 | u32 doorbell; | |
640 | int i, j, r; | |
641 | ||
c113ea1c AD |
642 | for (i = 0; i < adev->sdma.num_instances; i++) { |
643 | ring = &adev->sdma.instance[i].ring; | |
aaa36a97 AD |
644 | wb_offset = (ring->rptr_offs * 4); |
645 | ||
646 | mutex_lock(&adev->srbm_mutex); | |
647 | for (j = 0; j < 16; j++) { | |
648 | vi_srbm_select(adev, 0, 0, 0, j); | |
649 | /* SDMA GFX */ | |
650 | WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0); | |
651 | WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0); | |
652 | } | |
653 | vi_srbm_select(adev, 0, 0, 0, 0); | |
654 | mutex_unlock(&adev->srbm_mutex); | |
655 | ||
c458fe94 AD |
656 | WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i], |
657 | adev->gfx.config.gb_addr_config & 0x70); | |
658 | ||
aaa36a97 AD |
659 | WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); |
660 | ||
661 | /* Set ring buffer size in dwords */ | |
662 | rb_bufsz = order_base_2(ring->ring_size / 4); | |
663 | rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); | |
664 | rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); | |
665 | #ifdef __BIG_ENDIAN | |
666 | rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); | |
667 | rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, | |
668 | RPTR_WRITEBACK_SWAP_ENABLE, 1); | |
669 | #endif | |
670 | WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); | |
671 | ||
672 | /* Initialize the ring buffer's read and write pointers */ | |
673 | WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); | |
674 | WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); | |
d72f7c06 ML |
675 | WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); |
676 | WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0); | |
aaa36a97 AD |
677 | |
678 | /* set the wb address whether it's enabled or not */ | |
679 | WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], | |
680 | upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); | |
681 | WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], | |
682 | lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); | |
683 | ||
684 | rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); | |
685 | ||
686 | WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); | |
687 | WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); | |
688 | ||
689 | ring->wptr = 0; | |
690 | WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2); | |
691 | ||
692 | doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]); | |
693 | ||
694 | if (ring->use_doorbell) { | |
695 | doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, | |
696 | OFFSET, ring->doorbell_index); | |
697 | doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); | |
698 | } else { | |
699 | doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); | |
700 | } | |
701 | WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell); | |
702 | ||
703 | /* enable DMA RB */ | |
704 | rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); | |
705 | WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); | |
706 | ||
707 | ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); | |
708 | ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); | |
709 | #ifdef __BIG_ENDIAN | |
710 | ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); | |
711 | #endif | |
712 | /* enable DMA IBs */ | |
713 | WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); | |
714 | ||
715 | ring->ready = true; | |
716 | ||
717 | r = amdgpu_ring_test_ring(ring); | |
718 | if (r) { | |
719 | ring->ready = false; | |
720 | return r; | |
721 | } | |
722 | ||
723 | if (adev->mman.buffer_funcs_ring == ring) | |
724 | amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size); | |
725 | } | |
726 | ||
727 | return 0; | |
728 | } | |
729 | ||
730 | /** | |
731 | * sdma_v3_0_rlc_resume - setup and start the async dma engines | |
732 | * | |
733 | * @adev: amdgpu_device pointer | |
734 | * | |
735 | * Set up the compute DMA queues and enable them (VI). | |
736 | * Returns 0 for success, error for failure. | |
737 | */ | |
738 | static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev) | |
739 | { | |
740 | /* XXX todo */ | |
741 | return 0; | |
742 | } | |
743 | ||
744 | /** | |
745 | * sdma_v3_0_load_microcode - load the sDMA ME ucode | |
746 | * | |
747 | * @adev: amdgpu_device pointer | |
748 | * | |
749 | * Loads the sDMA0/1 ucode. | |
750 | * Returns 0 for success, -EINVAL if the ucode is not available. | |
751 | */ | |
752 | static int sdma_v3_0_load_microcode(struct amdgpu_device *adev) | |
753 | { | |
754 | const struct sdma_firmware_header_v1_0 *hdr; | |
755 | const __le32 *fw_data; | |
756 | u32 fw_size; | |
757 | int i, j; | |
758 | ||
aaa36a97 AD |
759 | /* halt the MEs */ |
760 | sdma_v3_0_enable(adev, false); | |
761 | ||
c113ea1c AD |
762 | for (i = 0; i < adev->sdma.num_instances; i++) { |
763 | if (!adev->sdma.instance[i].fw) | |
764 | return -EINVAL; | |
765 | hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; | |
aaa36a97 AD |
766 | amdgpu_ucode_print_sdma_hdr(&hdr->header); |
767 | fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; | |
aaa36a97 | 768 | fw_data = (const __le32 *) |
c113ea1c | 769 | (adev->sdma.instance[i].fw->data + |
aaa36a97 AD |
770 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); |
771 | WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0); | |
772 | for (j = 0; j < fw_size; j++) | |
773 | WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++)); | |
c113ea1c | 774 | WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version); |
aaa36a97 AD |
775 | } |
776 | ||
777 | return 0; | |
778 | } | |
779 | ||
780 | /** | |
781 | * sdma_v3_0_start - setup and start the async dma engines | |
782 | * | |
783 | * @adev: amdgpu_device pointer | |
784 | * | |
785 | * Set up the DMA engines and enable them (VI). | |
786 | * Returns 0 for success, error for failure. | |
787 | */ | |
788 | static int sdma_v3_0_start(struct amdgpu_device *adev) | |
789 | { | |
c113ea1c | 790 | int r, i; |
aaa36a97 | 791 | |
e61710c5 | 792 | if (!adev->pp_enabled) { |
ba5c2a87 RZ |
793 | if (!adev->firmware.smu_load) { |
794 | r = sdma_v3_0_load_microcode(adev); | |
c113ea1c | 795 | if (r) |
ba5c2a87 RZ |
796 | return r; |
797 | } else { | |
798 | for (i = 0; i < adev->sdma.num_instances; i++) { | |
799 | r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, | |
800 | (i == 0) ? | |
801 | AMDGPU_UCODE_ID_SDMA0 : | |
802 | AMDGPU_UCODE_ID_SDMA1); | |
803 | if (r) | |
804 | return -EINVAL; | |
805 | } | |
c113ea1c | 806 | } |
aaa36a97 AD |
807 | } |
808 | ||
809 | /* unhalt the MEs */ | |
810 | sdma_v3_0_enable(adev, true); | |
cd06bf68 BG |
811 | /* enable sdma ring preemption */ |
812 | sdma_v3_0_ctx_switch_enable(adev, true); | |
aaa36a97 AD |
813 | |
814 | /* start the gfx rings and rlc compute queues */ | |
815 | r = sdma_v3_0_gfx_resume(adev); | |
816 | if (r) | |
817 | return r; | |
818 | r = sdma_v3_0_rlc_resume(adev); | |
819 | if (r) | |
820 | return r; | |
821 | ||
822 | return 0; | |
823 | } | |
824 | ||
825 | /** | |
826 | * sdma_v3_0_ring_test_ring - simple async dma engine test | |
827 | * | |
828 | * @ring: amdgpu_ring structure holding ring information | |
829 | * | |
830 | * Test the DMA engine by writing using it to write an | |
831 | * value to memory. (VI). | |
832 | * Returns 0 for success, error for failure. | |
833 | */ | |
834 | static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring) | |
835 | { | |
836 | struct amdgpu_device *adev = ring->adev; | |
837 | unsigned i; | |
838 | unsigned index; | |
839 | int r; | |
840 | u32 tmp; | |
841 | u64 gpu_addr; | |
842 | ||
843 | r = amdgpu_wb_get(adev, &index); | |
844 | if (r) { | |
845 | dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); | |
846 | return r; | |
847 | } | |
848 | ||
849 | gpu_addr = adev->wb.gpu_addr + (index * 4); | |
850 | tmp = 0xCAFEDEAD; | |
851 | adev->wb.wb[index] = cpu_to_le32(tmp); | |
852 | ||
a27de35c | 853 | r = amdgpu_ring_alloc(ring, 5); |
aaa36a97 AD |
854 | if (r) { |
855 | DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); | |
856 | amdgpu_wb_free(adev, index); | |
857 | return r; | |
858 | } | |
859 | ||
860 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | | |
861 | SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); | |
862 | amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); | |
863 | amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); | |
864 | amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); | |
865 | amdgpu_ring_write(ring, 0xDEADBEEF); | |
a27de35c | 866 | amdgpu_ring_commit(ring); |
aaa36a97 AD |
867 | |
868 | for (i = 0; i < adev->usec_timeout; i++) { | |
869 | tmp = le32_to_cpu(adev->wb.wb[index]); | |
870 | if (tmp == 0xDEADBEEF) | |
871 | break; | |
872 | DRM_UDELAY(1); | |
873 | } | |
874 | ||
875 | if (i < adev->usec_timeout) { | |
876 | DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); | |
877 | } else { | |
878 | DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", | |
879 | ring->idx, tmp); | |
880 | r = -EINVAL; | |
881 | } | |
882 | amdgpu_wb_free(adev, index); | |
883 | ||
884 | return r; | |
885 | } | |
886 | ||
887 | /** | |
888 | * sdma_v3_0_ring_test_ib - test an IB on the DMA engine | |
889 | * | |
890 | * @ring: amdgpu_ring structure holding ring information | |
891 | * | |
892 | * Test a simple IB in the DMA ring (VI). | |
893 | * Returns 0 on success, error on failure. | |
894 | */ | |
895 | static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring) | |
896 | { | |
897 | struct amdgpu_device *adev = ring->adev; | |
898 | struct amdgpu_ib ib; | |
1763552e | 899 | struct fence *f = NULL; |
aaa36a97 AD |
900 | unsigned i; |
901 | unsigned index; | |
902 | int r; | |
903 | u32 tmp = 0; | |
904 | u64 gpu_addr; | |
905 | ||
906 | r = amdgpu_wb_get(adev, &index); | |
907 | if (r) { | |
908 | dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); | |
909 | return r; | |
910 | } | |
911 | ||
912 | gpu_addr = adev->wb.gpu_addr + (index * 4); | |
913 | tmp = 0xCAFEDEAD; | |
914 | adev->wb.wb[index] = cpu_to_le32(tmp); | |
b203dd95 | 915 | memset(&ib, 0, sizeof(ib)); |
b07c60c0 | 916 | r = amdgpu_ib_get(adev, NULL, 256, &ib); |
aaa36a97 | 917 | if (r) { |
aaa36a97 | 918 | DRM_ERROR("amdgpu: failed to get ib (%d).\n", r); |
0011fdaa | 919 | goto err0; |
aaa36a97 AD |
920 | } |
921 | ||
922 | ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | | |
923 | SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); | |
924 | ib.ptr[1] = lower_32_bits(gpu_addr); | |
925 | ib.ptr[2] = upper_32_bits(gpu_addr); | |
926 | ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1); | |
927 | ib.ptr[4] = 0xDEADBEEF; | |
928 | ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); | |
929 | ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); | |
930 | ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); | |
931 | ib.length_dw = 8; | |
932 | ||
c5637837 | 933 | r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f); |
0011fdaa CZ |
934 | if (r) |
935 | goto err1; | |
936 | ||
1763552e | 937 | r = fence_wait(f, false); |
aaa36a97 | 938 | if (r) { |
aaa36a97 | 939 | DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); |
0011fdaa | 940 | goto err1; |
aaa36a97 AD |
941 | } |
942 | for (i = 0; i < adev->usec_timeout; i++) { | |
943 | tmp = le32_to_cpu(adev->wb.wb[index]); | |
944 | if (tmp == 0xDEADBEEF) | |
945 | break; | |
946 | DRM_UDELAY(1); | |
947 | } | |
948 | if (i < adev->usec_timeout) { | |
949 | DRM_INFO("ib test on ring %d succeeded in %u usecs\n", | |
0011fdaa CZ |
950 | ring->idx, i); |
951 | goto err1; | |
aaa36a97 AD |
952 | } else { |
953 | DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); | |
954 | r = -EINVAL; | |
955 | } | |
0011fdaa | 956 | err1: |
281b4223 | 957 | fence_put(f); |
cc55c45d | 958 | amdgpu_ib_free(adev, &ib, NULL); |
73cfa5f5 | 959 | fence_put(f); |
0011fdaa | 960 | err0: |
aaa36a97 AD |
961 | amdgpu_wb_free(adev, index); |
962 | return r; | |
963 | } | |
964 | ||
965 | /** | |
966 | * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART | |
967 | * | |
968 | * @ib: indirect buffer to fill with commands | |
969 | * @pe: addr of the page entry | |
970 | * @src: src addr to copy from | |
971 | * @count: number of page entries to update | |
972 | * | |
973 | * Update PTEs by copying them from the GART using sDMA (CIK). | |
974 | */ | |
975 | static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib, | |
976 | uint64_t pe, uint64_t src, | |
977 | unsigned count) | |
978 | { | |
979 | while (count) { | |
980 | unsigned bytes = count * 8; | |
981 | if (bytes > 0x1FFFF8) | |
982 | bytes = 0x1FFFF8; | |
983 | ||
984 | ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | | |
985 | SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); | |
986 | ib->ptr[ib->length_dw++] = bytes; | |
987 | ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ | |
988 | ib->ptr[ib->length_dw++] = lower_32_bits(src); | |
989 | ib->ptr[ib->length_dw++] = upper_32_bits(src); | |
990 | ib->ptr[ib->length_dw++] = lower_32_bits(pe); | |
991 | ib->ptr[ib->length_dw++] = upper_32_bits(pe); | |
992 | ||
993 | pe += bytes; | |
994 | src += bytes; | |
995 | count -= bytes / 8; | |
996 | } | |
997 | } | |
998 | ||
999 | /** | |
1000 | * sdma_v3_0_vm_write_pte - update PTEs by writing them manually | |
1001 | * | |
1002 | * @ib: indirect buffer to fill with commands | |
1003 | * @pe: addr of the page entry | |
1004 | * @addr: dst addr to write into pe | |
1005 | * @count: number of page entries to update | |
1006 | * @incr: increase next addr by incr bytes | |
1007 | * @flags: access flags | |
1008 | * | |
1009 | * Update PTEs by writing them manually using sDMA (CIK). | |
1010 | */ | |
1011 | static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, | |
b07c9d2a | 1012 | const dma_addr_t *pages_addr, uint64_t pe, |
aaa36a97 AD |
1013 | uint64_t addr, unsigned count, |
1014 | uint32_t incr, uint32_t flags) | |
1015 | { | |
1016 | uint64_t value; | |
1017 | unsigned ndw; | |
1018 | ||
1019 | while (count) { | |
1020 | ndw = count * 2; | |
1021 | if (ndw > 0xFFFFE) | |
1022 | ndw = 0xFFFFE; | |
1023 | ||
1024 | /* for non-physically contiguous pages (system) */ | |
1025 | ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | | |
1026 | SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); | |
1027 | ib->ptr[ib->length_dw++] = pe; | |
1028 | ib->ptr[ib->length_dw++] = upper_32_bits(pe); | |
1029 | ib->ptr[ib->length_dw++] = ndw; | |
1030 | for (; ndw > 0; ndw -= 2, --count, pe += 8) { | |
b07c9d2a | 1031 | value = amdgpu_vm_map_gart(pages_addr, addr); |
aaa36a97 AD |
1032 | addr += incr; |
1033 | value |= flags; | |
1034 | ib->ptr[ib->length_dw++] = value; | |
1035 | ib->ptr[ib->length_dw++] = upper_32_bits(value); | |
1036 | } | |
1037 | } | |
1038 | } | |
1039 | ||
1040 | /** | |
1041 | * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA | |
1042 | * | |
1043 | * @ib: indirect buffer to fill with commands | |
1044 | * @pe: addr of the page entry | |
1045 | * @addr: dst addr to write into pe | |
1046 | * @count: number of page entries to update | |
1047 | * @incr: increase next addr by incr bytes | |
1048 | * @flags: access flags | |
1049 | * | |
1050 | * Update the page tables using sDMA (CIK). | |
1051 | */ | |
1052 | static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib, | |
1053 | uint64_t pe, | |
1054 | uint64_t addr, unsigned count, | |
1055 | uint32_t incr, uint32_t flags) | |
1056 | { | |
1057 | uint64_t value; | |
1058 | unsigned ndw; | |
1059 | ||
1060 | while (count) { | |
1061 | ndw = count; | |
1062 | if (ndw > 0x7FFFF) | |
1063 | ndw = 0x7FFFF; | |
1064 | ||
1065 | if (flags & AMDGPU_PTE_VALID) | |
1066 | value = addr; | |
1067 | else | |
1068 | value = 0; | |
1069 | ||
1070 | /* for physically contiguous pages (vram) */ | |
1071 | ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE); | |
1072 | ib->ptr[ib->length_dw++] = pe; /* dst addr */ | |
1073 | ib->ptr[ib->length_dw++] = upper_32_bits(pe); | |
1074 | ib->ptr[ib->length_dw++] = flags; /* mask */ | |
1075 | ib->ptr[ib->length_dw++] = 0; | |
1076 | ib->ptr[ib->length_dw++] = value; /* value */ | |
1077 | ib->ptr[ib->length_dw++] = upper_32_bits(value); | |
1078 | ib->ptr[ib->length_dw++] = incr; /* increment size */ | |
1079 | ib->ptr[ib->length_dw++] = 0; | |
1080 | ib->ptr[ib->length_dw++] = ndw; /* number of entries */ | |
1081 | ||
1082 | pe += ndw * 8; | |
1083 | addr += ndw * incr; | |
1084 | count -= ndw; | |
1085 | } | |
1086 | } | |
1087 | ||
1088 | /** | |
9e5d5309 | 1089 | * sdma_v3_0_ring_pad_ib - pad the IB to the required number of dw |
aaa36a97 AD |
1090 | * |
1091 | * @ib: indirect buffer to fill with padding | |
1092 | * | |
1093 | */ | |
9e5d5309 | 1094 | static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) |
aaa36a97 | 1095 | { |
9e5d5309 | 1096 | struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); |
ac01db3d JZ |
1097 | u32 pad_count; |
1098 | int i; | |
1099 | ||
1100 | pad_count = (8 - (ib->length_dw & 0x7)) % 8; | |
1101 | for (i = 0; i < pad_count; i++) | |
1102 | if (sdma && sdma->burst_nop && (i == 0)) | |
1103 | ib->ptr[ib->length_dw++] = | |
1104 | SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | | |
1105 | SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); | |
1106 | else | |
1107 | ib->ptr[ib->length_dw++] = | |
1108 | SDMA_PKT_HEADER_OP(SDMA_OP_NOP); | |
aaa36a97 AD |
1109 | } |
1110 | ||
1111 | /** | |
00b7c4ff | 1112 | * sdma_v3_0_ring_emit_pipeline_sync - sync the pipeline |
aaa36a97 AD |
1113 | * |
1114 | * @ring: amdgpu_ring pointer | |
aaa36a97 | 1115 | * |
00b7c4ff | 1116 | * Make sure all previous operations are completed (CIK). |
aaa36a97 | 1117 | */ |
00b7c4ff | 1118 | static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) |
aaa36a97 | 1119 | { |
5c55db83 CZ |
1120 | uint32_t seq = ring->fence_drv.sync_seq; |
1121 | uint64_t addr = ring->fence_drv.gpu_addr; | |
1122 | ||
1123 | /* wait for idle */ | |
1124 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | | |
1125 | SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | | |
1126 | SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ | |
1127 | SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); | |
1128 | amdgpu_ring_write(ring, addr & 0xfffffffc); | |
1129 | amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); | |
1130 | amdgpu_ring_write(ring, seq); /* reference */ | |
1131 | amdgpu_ring_write(ring, 0xfffffff); /* mask */ | |
1132 | amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | | |
1133 | SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ | |
00b7c4ff | 1134 | } |
5c55db83 | 1135 | |
00b7c4ff CK |
1136 | /** |
1137 | * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA | |
1138 | * | |
1139 | * @ring: amdgpu_ring pointer | |
1140 | * @vm: amdgpu_vm pointer | |
1141 | * | |
1142 | * Update the page table base and flush the VM TLB | |
1143 | * using sDMA (VI). | |
1144 | */ | |
1145 | static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring, | |
1146 | unsigned vm_id, uint64_t pd_addr) | |
1147 | { | |
aaa36a97 AD |
1148 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | |
1149 | SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); | |
1150 | if (vm_id < 8) { | |
1151 | amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id)); | |
1152 | } else { | |
1153 | amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8)); | |
1154 | } | |
1155 | amdgpu_ring_write(ring, pd_addr >> 12); | |
1156 | ||
aaa36a97 AD |
1157 | /* flush TLB */ |
1158 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | | |
1159 | SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); | |
1160 | amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); | |
1161 | amdgpu_ring_write(ring, 1 << vm_id); | |
1162 | ||
1163 | /* wait for flush */ | |
1164 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | | |
1165 | SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | | |
1166 | SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */ | |
1167 | amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2); | |
1168 | amdgpu_ring_write(ring, 0); | |
1169 | amdgpu_ring_write(ring, 0); /* reference */ | |
1170 | amdgpu_ring_write(ring, 0); /* mask */ | |
1171 | amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | | |
1172 | SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ | |
1173 | } | |
1174 | ||
5fc3aeeb | 1175 | static int sdma_v3_0_early_init(void *handle) |
aaa36a97 | 1176 | { |
5fc3aeeb | 1177 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1178 | ||
c113ea1c | 1179 | switch (adev->asic_type) { |
bb16e3b6 SL |
1180 | case CHIP_STONEY: |
1181 | adev->sdma.num_instances = 1; | |
1182 | break; | |
c113ea1c AD |
1183 | default: |
1184 | adev->sdma.num_instances = SDMA_MAX_INSTANCE; | |
1185 | break; | |
1186 | } | |
1187 | ||
aaa36a97 AD |
1188 | sdma_v3_0_set_ring_funcs(adev); |
1189 | sdma_v3_0_set_buffer_funcs(adev); | |
1190 | sdma_v3_0_set_vm_pte_funcs(adev); | |
1191 | sdma_v3_0_set_irq_funcs(adev); | |
1192 | ||
1193 | return 0; | |
1194 | } | |
1195 | ||
5fc3aeeb | 1196 | static int sdma_v3_0_sw_init(void *handle) |
aaa36a97 AD |
1197 | { |
1198 | struct amdgpu_ring *ring; | |
c113ea1c | 1199 | int r, i; |
5fc3aeeb | 1200 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
aaa36a97 AD |
1201 | |
1202 | /* SDMA trap event */ | |
c113ea1c | 1203 | r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq); |
aaa36a97 AD |
1204 | if (r) |
1205 | return r; | |
1206 | ||
1207 | /* SDMA Privileged inst */ | |
c113ea1c | 1208 | r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq); |
aaa36a97 AD |
1209 | if (r) |
1210 | return r; | |
1211 | ||
1212 | /* SDMA Privileged inst */ | |
c113ea1c | 1213 | r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq); |
aaa36a97 AD |
1214 | if (r) |
1215 | return r; | |
1216 | ||
1217 | r = sdma_v3_0_init_microcode(adev); | |
1218 | if (r) { | |
1219 | DRM_ERROR("Failed to load sdma firmware!\n"); | |
1220 | return r; | |
1221 | } | |
1222 | ||
c113ea1c AD |
1223 | for (i = 0; i < adev->sdma.num_instances; i++) { |
1224 | ring = &adev->sdma.instance[i].ring; | |
1225 | ring->ring_obj = NULL; | |
1226 | ring->use_doorbell = true; | |
1227 | ring->doorbell_index = (i == 0) ? | |
1228 | AMDGPU_DOORBELL_sDMA_ENGINE0 : AMDGPU_DOORBELL_sDMA_ENGINE1; | |
1229 | ||
1230 | sprintf(ring->name, "sdma%d", i); | |
b38d99c4 | 1231 | r = amdgpu_ring_init(adev, ring, 1024, |
c113ea1c AD |
1232 | SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf, |
1233 | &adev->sdma.trap_irq, | |
1234 | (i == 0) ? | |
1235 | AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1, | |
1236 | AMDGPU_RING_TYPE_SDMA); | |
1237 | if (r) | |
1238 | return r; | |
1239 | } | |
aaa36a97 AD |
1240 | |
1241 | return r; | |
1242 | } | |
1243 | ||
5fc3aeeb | 1244 | static int sdma_v3_0_sw_fini(void *handle) |
aaa36a97 | 1245 | { |
5fc3aeeb | 1246 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
c113ea1c | 1247 | int i; |
5fc3aeeb | 1248 | |
c113ea1c AD |
1249 | for (i = 0; i < adev->sdma.num_instances; i++) |
1250 | amdgpu_ring_fini(&adev->sdma.instance[i].ring); | |
aaa36a97 AD |
1251 | |
1252 | return 0; | |
1253 | } | |
1254 | ||
5fc3aeeb | 1255 | static int sdma_v3_0_hw_init(void *handle) |
aaa36a97 AD |
1256 | { |
1257 | int r; | |
5fc3aeeb | 1258 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
aaa36a97 AD |
1259 | |
1260 | sdma_v3_0_init_golden_registers(adev); | |
1261 | ||
1262 | r = sdma_v3_0_start(adev); | |
1263 | if (r) | |
1264 | return r; | |
1265 | ||
1266 | return r; | |
1267 | } | |
1268 | ||
5fc3aeeb | 1269 | static int sdma_v3_0_hw_fini(void *handle) |
aaa36a97 | 1270 | { |
5fc3aeeb | 1271 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1272 | ||
cd06bf68 | 1273 | sdma_v3_0_ctx_switch_enable(adev, false); |
aaa36a97 AD |
1274 | sdma_v3_0_enable(adev, false); |
1275 | ||
1276 | return 0; | |
1277 | } | |
1278 | ||
5fc3aeeb | 1279 | static int sdma_v3_0_suspend(void *handle) |
aaa36a97 | 1280 | { |
5fc3aeeb | 1281 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
aaa36a97 AD |
1282 | |
1283 | return sdma_v3_0_hw_fini(adev); | |
1284 | } | |
1285 | ||
5fc3aeeb | 1286 | static int sdma_v3_0_resume(void *handle) |
aaa36a97 | 1287 | { |
5fc3aeeb | 1288 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
aaa36a97 AD |
1289 | |
1290 | return sdma_v3_0_hw_init(adev); | |
1291 | } | |
1292 | ||
5fc3aeeb | 1293 | static bool sdma_v3_0_is_idle(void *handle) |
aaa36a97 | 1294 | { |
5fc3aeeb | 1295 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
aaa36a97 AD |
1296 | u32 tmp = RREG32(mmSRBM_STATUS2); |
1297 | ||
1298 | if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK | | |
1299 | SRBM_STATUS2__SDMA1_BUSY_MASK)) | |
1300 | return false; | |
1301 | ||
1302 | return true; | |
1303 | } | |
1304 | ||
5fc3aeeb | 1305 | static int sdma_v3_0_wait_for_idle(void *handle) |
aaa36a97 AD |
1306 | { |
1307 | unsigned i; | |
1308 | u32 tmp; | |
5fc3aeeb | 1309 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
aaa36a97 AD |
1310 | |
1311 | for (i = 0; i < adev->usec_timeout; i++) { | |
1312 | tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | | |
1313 | SRBM_STATUS2__SDMA1_BUSY_MASK); | |
1314 | ||
1315 | if (!tmp) | |
1316 | return 0; | |
1317 | udelay(1); | |
1318 | } | |
1319 | return -ETIMEDOUT; | |
1320 | } | |
1321 | ||
5fc3aeeb | 1322 | static int sdma_v3_0_soft_reset(void *handle) |
aaa36a97 AD |
1323 | { |
1324 | u32 srbm_soft_reset = 0; | |
5fc3aeeb | 1325 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
aaa36a97 AD |
1326 | u32 tmp = RREG32(mmSRBM_STATUS2); |
1327 | ||
1328 | if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) { | |
1329 | /* sdma0 */ | |
1330 | tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); | |
1331 | tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0); | |
1332 | WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); | |
1333 | srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK; | |
1334 | } | |
1335 | if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) { | |
1336 | /* sdma1 */ | |
1337 | tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); | |
1338 | tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0); | |
1339 | WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); | |
1340 | srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK; | |
1341 | } | |
1342 | ||
1343 | if (srbm_soft_reset) { | |
aaa36a97 AD |
1344 | tmp = RREG32(mmSRBM_SOFT_RESET); |
1345 | tmp |= srbm_soft_reset; | |
1346 | dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); | |
1347 | WREG32(mmSRBM_SOFT_RESET, tmp); | |
1348 | tmp = RREG32(mmSRBM_SOFT_RESET); | |
1349 | ||
1350 | udelay(50); | |
1351 | ||
1352 | tmp &= ~srbm_soft_reset; | |
1353 | WREG32(mmSRBM_SOFT_RESET, tmp); | |
1354 | tmp = RREG32(mmSRBM_SOFT_RESET); | |
1355 | ||
1356 | /* Wait a little for things to settle down */ | |
1357 | udelay(50); | |
aaa36a97 AD |
1358 | } |
1359 | ||
1360 | return 0; | |
1361 | } | |
1362 | ||
1363 | static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev, | |
1364 | struct amdgpu_irq_src *source, | |
1365 | unsigned type, | |
1366 | enum amdgpu_interrupt_state state) | |
1367 | { | |
1368 | u32 sdma_cntl; | |
1369 | ||
1370 | switch (type) { | |
1371 | case AMDGPU_SDMA_IRQ_TRAP0: | |
1372 | switch (state) { | |
1373 | case AMDGPU_IRQ_STATE_DISABLE: | |
1374 | sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); | |
1375 | sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); | |
1376 | WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); | |
1377 | break; | |
1378 | case AMDGPU_IRQ_STATE_ENABLE: | |
1379 | sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); | |
1380 | sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); | |
1381 | WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); | |
1382 | break; | |
1383 | default: | |
1384 | break; | |
1385 | } | |
1386 | break; | |
1387 | case AMDGPU_SDMA_IRQ_TRAP1: | |
1388 | switch (state) { | |
1389 | case AMDGPU_IRQ_STATE_DISABLE: | |
1390 | sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); | |
1391 | sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); | |
1392 | WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); | |
1393 | break; | |
1394 | case AMDGPU_IRQ_STATE_ENABLE: | |
1395 | sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); | |
1396 | sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); | |
1397 | WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); | |
1398 | break; | |
1399 | default: | |
1400 | break; | |
1401 | } | |
1402 | break; | |
1403 | default: | |
1404 | break; | |
1405 | } | |
1406 | return 0; | |
1407 | } | |
1408 | ||
1409 | static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev, | |
1410 | struct amdgpu_irq_src *source, | |
1411 | struct amdgpu_iv_entry *entry) | |
1412 | { | |
1413 | u8 instance_id, queue_id; | |
1414 | ||
1415 | instance_id = (entry->ring_id & 0x3) >> 0; | |
1416 | queue_id = (entry->ring_id & 0xc) >> 2; | |
1417 | DRM_DEBUG("IH: SDMA trap\n"); | |
1418 | switch (instance_id) { | |
1419 | case 0: | |
1420 | switch (queue_id) { | |
1421 | case 0: | |
c113ea1c | 1422 | amdgpu_fence_process(&adev->sdma.instance[0].ring); |
aaa36a97 AD |
1423 | break; |
1424 | case 1: | |
1425 | /* XXX compute */ | |
1426 | break; | |
1427 | case 2: | |
1428 | /* XXX compute */ | |
1429 | break; | |
1430 | } | |
1431 | break; | |
1432 | case 1: | |
1433 | switch (queue_id) { | |
1434 | case 0: | |
c113ea1c | 1435 | amdgpu_fence_process(&adev->sdma.instance[1].ring); |
aaa36a97 AD |
1436 | break; |
1437 | case 1: | |
1438 | /* XXX compute */ | |
1439 | break; | |
1440 | case 2: | |
1441 | /* XXX compute */ | |
1442 | break; | |
1443 | } | |
1444 | break; | |
1445 | } | |
1446 | return 0; | |
1447 | } | |
1448 | ||
1449 | static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev, | |
1450 | struct amdgpu_irq_src *source, | |
1451 | struct amdgpu_iv_entry *entry) | |
1452 | { | |
1453 | DRM_ERROR("Illegal instruction in SDMA command stream\n"); | |
1454 | schedule_work(&adev->reset_work); | |
1455 | return 0; | |
1456 | } | |
1457 | ||
ce22362b | 1458 | static void sdma_v3_0_update_sdma_medium_grain_clock_gating( |
3c997d24 EH |
1459 | struct amdgpu_device *adev, |
1460 | bool enable) | |
1461 | { | |
1462 | uint32_t temp, data; | |
ce22362b | 1463 | int i; |
3c997d24 | 1464 | |
e08d53cb | 1465 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { |
ce22362b AD |
1466 | for (i = 0; i < adev->sdma.num_instances; i++) { |
1467 | temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]); | |
1468 | data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | | |
1469 | SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | | |
1470 | SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | | |
1471 | SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | | |
1472 | SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | | |
1473 | SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | | |
1474 | SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | | |
1475 | SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); | |
1476 | if (data != temp) | |
1477 | WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data); | |
1478 | } | |
3c997d24 | 1479 | } else { |
ce22362b AD |
1480 | for (i = 0; i < adev->sdma.num_instances; i++) { |
1481 | temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]); | |
1482 | data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | | |
3c997d24 EH |
1483 | SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | |
1484 | SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | | |
1485 | SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | | |
1486 | SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | | |
1487 | SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | | |
1488 | SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | | |
1489 | SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK; | |
1490 | ||
ce22362b AD |
1491 | if (data != temp) |
1492 | WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data); | |
1493 | } | |
3c997d24 EH |
1494 | } |
1495 | } | |
1496 | ||
ce22362b | 1497 | static void sdma_v3_0_update_sdma_medium_grain_light_sleep( |
3c997d24 EH |
1498 | struct amdgpu_device *adev, |
1499 | bool enable) | |
1500 | { | |
1501 | uint32_t temp, data; | |
ce22362b | 1502 | int i; |
3c997d24 | 1503 | |
e08d53cb | 1504 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { |
ce22362b AD |
1505 | for (i = 0; i < adev->sdma.num_instances; i++) { |
1506 | temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]); | |
1507 | data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; | |
3c997d24 | 1508 | |
ce22362b AD |
1509 | if (temp != data) |
1510 | WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data); | |
1511 | } | |
3c997d24 | 1512 | } else { |
ce22362b AD |
1513 | for (i = 0; i < adev->sdma.num_instances; i++) { |
1514 | temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]); | |
1515 | data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; | |
3c997d24 | 1516 | |
ce22362b AD |
1517 | if (temp != data) |
1518 | WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data); | |
1519 | } | |
3c997d24 EH |
1520 | } |
1521 | } | |
1522 | ||
5fc3aeeb | 1523 | static int sdma_v3_0_set_clockgating_state(void *handle, |
1524 | enum amd_clockgating_state state) | |
aaa36a97 | 1525 | { |
3c997d24 EH |
1526 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1527 | ||
1528 | switch (adev->asic_type) { | |
1529 | case CHIP_FIJI: | |
ce22362b AD |
1530 | case CHIP_CARRIZO: |
1531 | case CHIP_STONEY: | |
1532 | sdma_v3_0_update_sdma_medium_grain_clock_gating(adev, | |
3c997d24 | 1533 | state == AMD_CG_STATE_GATE ? true : false); |
ce22362b | 1534 | sdma_v3_0_update_sdma_medium_grain_light_sleep(adev, |
3c997d24 EH |
1535 | state == AMD_CG_STATE_GATE ? true : false); |
1536 | break; | |
1537 | default: | |
1538 | break; | |
1539 | } | |
aaa36a97 AD |
1540 | return 0; |
1541 | } | |
1542 | ||
5fc3aeeb | 1543 | static int sdma_v3_0_set_powergating_state(void *handle, |
1544 | enum amd_powergating_state state) | |
aaa36a97 AD |
1545 | { |
1546 | return 0; | |
1547 | } | |
1548 | ||
5fc3aeeb | 1549 | const struct amd_ip_funcs sdma_v3_0_ip_funcs = { |
88a907d6 | 1550 | .name = "sdma_v3_0", |
aaa36a97 AD |
1551 | .early_init = sdma_v3_0_early_init, |
1552 | .late_init = NULL, | |
1553 | .sw_init = sdma_v3_0_sw_init, | |
1554 | .sw_fini = sdma_v3_0_sw_fini, | |
1555 | .hw_init = sdma_v3_0_hw_init, | |
1556 | .hw_fini = sdma_v3_0_hw_fini, | |
1557 | .suspend = sdma_v3_0_suspend, | |
1558 | .resume = sdma_v3_0_resume, | |
1559 | .is_idle = sdma_v3_0_is_idle, | |
1560 | .wait_for_idle = sdma_v3_0_wait_for_idle, | |
1561 | .soft_reset = sdma_v3_0_soft_reset, | |
aaa36a97 AD |
1562 | .set_clockgating_state = sdma_v3_0_set_clockgating_state, |
1563 | .set_powergating_state = sdma_v3_0_set_powergating_state, | |
1564 | }; | |
1565 | ||
aaa36a97 AD |
1566 | static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = { |
1567 | .get_rptr = sdma_v3_0_ring_get_rptr, | |
1568 | .get_wptr = sdma_v3_0_ring_get_wptr, | |
1569 | .set_wptr = sdma_v3_0_ring_set_wptr, | |
1570 | .parse_cs = NULL, | |
1571 | .emit_ib = sdma_v3_0_ring_emit_ib, | |
1572 | .emit_fence = sdma_v3_0_ring_emit_fence, | |
00b7c4ff | 1573 | .emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync, |
aaa36a97 | 1574 | .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush, |
d2edb07b | 1575 | .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush, |
cc958e67 | 1576 | .emit_hdp_invalidate = sdma_v3_0_ring_emit_hdp_invalidate, |
aaa36a97 AD |
1577 | .test_ring = sdma_v3_0_ring_test_ring, |
1578 | .test_ib = sdma_v3_0_ring_test_ib, | |
ac01db3d | 1579 | .insert_nop = sdma_v3_0_ring_insert_nop, |
9e5d5309 | 1580 | .pad_ib = sdma_v3_0_ring_pad_ib, |
aaa36a97 AD |
1581 | }; |
1582 | ||
1583 | static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev) | |
1584 | { | |
c113ea1c AD |
1585 | int i; |
1586 | ||
1587 | for (i = 0; i < adev->sdma.num_instances; i++) | |
1588 | adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs; | |
aaa36a97 AD |
1589 | } |
1590 | ||
1591 | static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = { | |
1592 | .set = sdma_v3_0_set_trap_irq_state, | |
1593 | .process = sdma_v3_0_process_trap_irq, | |
1594 | }; | |
1595 | ||
1596 | static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = { | |
1597 | .process = sdma_v3_0_process_illegal_inst_irq, | |
1598 | }; | |
1599 | ||
1600 | static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev) | |
1601 | { | |
c113ea1c AD |
1602 | adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; |
1603 | adev->sdma.trap_irq.funcs = &sdma_v3_0_trap_irq_funcs; | |
1604 | adev->sdma.illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs; | |
aaa36a97 AD |
1605 | } |
1606 | ||
1607 | /** | |
1608 | * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine | |
1609 | * | |
1610 | * @ring: amdgpu_ring structure holding ring information | |
1611 | * @src_offset: src GPU address | |
1612 | * @dst_offset: dst GPU address | |
1613 | * @byte_count: number of bytes to xfer | |
1614 | * | |
1615 | * Copy GPU buffers using the DMA engine (VI). | |
1616 | * Used by the amdgpu ttm implementation to move pages if | |
1617 | * registered as the asic copy callback. | |
1618 | */ | |
c7ae72c0 | 1619 | static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib, |
aaa36a97 AD |
1620 | uint64_t src_offset, |
1621 | uint64_t dst_offset, | |
1622 | uint32_t byte_count) | |
1623 | { | |
c7ae72c0 CZ |
1624 | ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | |
1625 | SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); | |
1626 | ib->ptr[ib->length_dw++] = byte_count; | |
1627 | ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ | |
1628 | ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); | |
1629 | ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); | |
1630 | ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); | |
1631 | ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); | |
aaa36a97 AD |
1632 | } |
1633 | ||
1634 | /** | |
1635 | * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine | |
1636 | * | |
1637 | * @ring: amdgpu_ring structure holding ring information | |
1638 | * @src_data: value to write to buffer | |
1639 | * @dst_offset: dst GPU address | |
1640 | * @byte_count: number of bytes to xfer | |
1641 | * | |
1642 | * Fill GPU buffers using the DMA engine (VI). | |
1643 | */ | |
6e7a3840 | 1644 | static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib, |
aaa36a97 AD |
1645 | uint32_t src_data, |
1646 | uint64_t dst_offset, | |
1647 | uint32_t byte_count) | |
1648 | { | |
6e7a3840 CZ |
1649 | ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); |
1650 | ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); | |
1651 | ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); | |
1652 | ib->ptr[ib->length_dw++] = src_data; | |
1653 | ib->ptr[ib->length_dw++] = byte_count; | |
aaa36a97 AD |
1654 | } |
1655 | ||
1656 | static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = { | |
1657 | .copy_max_bytes = 0x1fffff, | |
1658 | .copy_num_dw = 7, | |
1659 | .emit_copy_buffer = sdma_v3_0_emit_copy_buffer, | |
1660 | ||
1661 | .fill_max_bytes = 0x1fffff, | |
1662 | .fill_num_dw = 5, | |
1663 | .emit_fill_buffer = sdma_v3_0_emit_fill_buffer, | |
1664 | }; | |
1665 | ||
1666 | static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev) | |
1667 | { | |
1668 | if (adev->mman.buffer_funcs == NULL) { | |
1669 | adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs; | |
c113ea1c | 1670 | adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; |
aaa36a97 AD |
1671 | } |
1672 | } | |
1673 | ||
1674 | static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = { | |
1675 | .copy_pte = sdma_v3_0_vm_copy_pte, | |
1676 | .write_pte = sdma_v3_0_vm_write_pte, | |
1677 | .set_pte_pde = sdma_v3_0_vm_set_pte_pde, | |
aaa36a97 AD |
1678 | }; |
1679 | ||
1680 | static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev) | |
1681 | { | |
2d55e45a CK |
1682 | unsigned i; |
1683 | ||
aaa36a97 AD |
1684 | if (adev->vm_manager.vm_pte_funcs == NULL) { |
1685 | adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs; | |
2d55e45a CK |
1686 | for (i = 0; i < adev->sdma.num_instances; i++) |
1687 | adev->vm_manager.vm_pte_rings[i] = | |
1688 | &adev->sdma.instance[i].ring; | |
1689 | ||
1690 | adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances; | |
aaa36a97 AD |
1691 | } |
1692 | } |