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drm/amdgpu: update golden setting for pitcairn
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / amd / amdgpu / si.c
CommitLineData
62a37553
KW		 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/firmware.h>
25#include <linux/slab.h>
26#include <linux/module.h>
27#include "drmP.h"
28#include "amdgpu.h"
29#include "amdgpu_atombios.h"
30#include "amdgpu_ih.h"
31#include "amdgpu_uvd.h"
32#include "amdgpu_vce.h"
33#include "atom.h"
34#include "amdgpu_powerplay.h"
35#include "si/sid.h"
36#include "si_ih.h"
37#include "gfx_v6_0.h"
38#include "gmc_v6_0.h"
39#include "si_dma.h"
40#include "dce_v6_0.h"
41#include "si.h"
2120df47 42#include "dce_virtual.h"
62a37553
KW		 43
44static const u32 tahiti_golden_registers[] =
45{
7c0a705e 46 0x17bc, 0x00000030, 0x00000011,
62a37553
KW		 47 0x2684, 0x00010000, 0x00018208,
48 0x260c, 0xffffffff, 0x00000000,
49 0x260d, 0xf00fffff, 0x00000400,
50 0x260e, 0x0002021c, 0x00020200,
51 0x031e, 0x00000080, 0x00000000,
7c0a705e
FC		 52 0x340c, 0x000000c0, 0x00800040,
53 0x360c, 0x000000c0, 0x00800040,
62a37553
KW		 54 0x16ec, 0x000000f0, 0x00000070,
55 0x16f0, 0x00200000, 0x50100000,
56 0x1c0c, 0x31000311, 0x00000011,
57 0x09df, 0x00000003, 0x000007ff,
58 0x0903, 0x000007ff, 0x00000000,
59 0x2285, 0xf000001f, 0x00000007,
60 0x22c9, 0xffffffff, 0x00ffffff,
61 0x22c4, 0x0000ff0f, 0x00000000,
62 0xa293, 0x07ffffff, 0x4e000000,
63 0xa0d4, 0x3f3f3fff, 0x2a00126a,
7c0a705e 64 0x000c, 0xffffffff, 0x0040,
62a37553
KW		 65 0x000d, 0x00000040, 0x00004040,
66 0x2440, 0x07ffffff, 0x03000000,
67 0x23a2, 0x01ff1f3f, 0x00000000,
68 0x23a1, 0x01ff1f3f, 0x00000000,
69 0x2418, 0x0000007f, 0x00000020,
70 0x2542, 0x00010000, 0x00010000,
71 0x2b05, 0x00000200, 0x000002fb,
72 0x2b04, 0xffffffff, 0x0000543b,
73 0x2b03, 0xffffffff, 0xa9210876,
74 0x2234, 0xffffffff, 0x000fff40,
75 0x2235, 0x0000001f, 0x00000010,
76 0x0504, 0x20000000, 0x20fffed8,
7c0a705e
FC		 77 0x0570, 0x000c0fc0, 0x000c0400,
78 0x052c, 0x0fffffff, 0xffffffff,
79 0x052d, 0x0fffffff, 0x0fffffff,
80 0x052e, 0x0fffffff, 0x0fffffff,
81 0x052f, 0x0fffffff, 0x0fffffff
62a37553
KW		 82};
83
84static const u32 tahiti_golden_registers2[] =
85{
86 0x0319, 0x00000001, 0x00000001
87};
88
89static const u32 tahiti_golden_rlc_registers[] =
90{
7c0a705e 91 0x263e, 0xffffffff, 0x12011003,
62a37553
KW		 92 0x3109, 0xffffffff, 0x00601005,
93 0x311f, 0xffffffff, 0x10104040,
94 0x3122, 0xffffffff, 0x0100000a,
95 0x30c5, 0xffffffff, 0x00000800,
96 0x30c3, 0xffffffff, 0x800000f4,
7c0a705e 97 0x3d2a, 0x00000008, 0x00000000
62a37553
KW		 98};
99
100static const u32 pitcairn_golden_registers[] =
101{
1245a694 102 0x17bc, 0x00000030, 0x00000011,
62a37553
KW		 103 0x2684, 0x00010000, 0x00018208,
104 0x260c, 0xffffffff, 0x00000000,
105 0x260d, 0xf00fffff, 0x00000400,
106 0x260e, 0x0002021c, 0x00020200,
107 0x031e, 0x00000080, 0x00000000,
108 0x340c, 0x000300c0, 0x00800040,
109 0x360c, 0x000300c0, 0x00800040,
110 0x16ec, 0x000000f0, 0x00000070,
111 0x16f0, 0x00200000, 0x50100000,
112 0x1c0c, 0x31000311, 0x00000011,
113 0x0ab9, 0x00073ffe, 0x000022a2,
114 0x0903, 0x000007ff, 0x00000000,
115 0x2285, 0xf000001f, 0x00000007,
116 0x22c9, 0xffffffff, 0x00ffffff,
117 0x22c4, 0x0000ff0f, 0x00000000,
118 0xa293, 0x07ffffff, 0x4e000000,
119 0xa0d4, 0x3f3f3fff, 0x2a00126a,
1245a694 120 0x000c, 0xffffffff, 0x0040,
62a37553
KW		 121 0x000d, 0x00000040, 0x00004040,
122 0x2440, 0x07ffffff, 0x03000000,
123 0x2418, 0x0000007f, 0x00000020,
124 0x2542, 0x00010000, 0x00010000,
125 0x2b05, 0x000003ff, 0x000000f7,
126 0x2b04, 0xffffffff, 0x00000000,
127 0x2b03, 0xffffffff, 0x32761054,
128 0x2235, 0x0000001f, 0x00000010,
1245a694
FC		 129 0x0570, 0x000c0fc0, 0x000c0400,
130 0x052c, 0x0fffffff, 0xffffffff,
131 0x052d, 0x0fffffff, 0x0fffffff,
132 0x052e, 0x0fffffff, 0x0fffffff,
133 0x052f, 0x0fffffff, 0x0fffffff
62a37553
KW		 134};
135
136static const u32 pitcairn_golden_rlc_registers[] =
137{
1245a694 138 0x263e, 0xffffffff, 0x12011003,
62a37553
KW		 139 0x3109, 0xffffffff, 0x00601004,
140 0x311f, 0xffffffff, 0x10102020,
141 0x3122, 0xffffffff, 0x01000020,
142 0x30c5, 0xffffffff, 0x00000800,
143 0x30c3, 0xffffffff, 0x800000a4
144};
145
146static const u32 verde_pg_init[] =
147{
148 0xd4f, 0xffffffff, 0x40000,
149 0xd4e, 0xffffffff, 0x200010ff,
150 0xd4f, 0xffffffff, 0x0,
151 0xd4f, 0xffffffff, 0x0,
152 0xd4f, 0xffffffff, 0x0,
153 0xd4f, 0xffffffff, 0x0,
154 0xd4f, 0xffffffff, 0x0,
155 0xd4f, 0xffffffff, 0x7007,
156 0xd4e, 0xffffffff, 0x300010ff,
157 0xd4f, 0xffffffff, 0x0,
158 0xd4f, 0xffffffff, 0x0,
159 0xd4f, 0xffffffff, 0x0,
160 0xd4f, 0xffffffff, 0x0,
161 0xd4f, 0xffffffff, 0x0,
162 0xd4f, 0xffffffff, 0x400000,
163 0xd4e, 0xffffffff, 0x100010ff,
164 0xd4f, 0xffffffff, 0x0,
165 0xd4f, 0xffffffff, 0x0,
166 0xd4f, 0xffffffff, 0x0,
167 0xd4f, 0xffffffff, 0x0,
168 0xd4f, 0xffffffff, 0x0,
169 0xd4f, 0xffffffff, 0x120200,
170 0xd4e, 0xffffffff, 0x500010ff,
171 0xd4f, 0xffffffff, 0x0,
172 0xd4f, 0xffffffff, 0x0,
173 0xd4f, 0xffffffff, 0x0,
174 0xd4f, 0xffffffff, 0x0,
175 0xd4f, 0xffffffff, 0x0,
176 0xd4f, 0xffffffff, 0x1e1e16,
177 0xd4e, 0xffffffff, 0x600010ff,
178 0xd4f, 0xffffffff, 0x0,
179 0xd4f, 0xffffffff, 0x0,
180 0xd4f, 0xffffffff, 0x0,
181 0xd4f, 0xffffffff, 0x0,
182 0xd4f, 0xffffffff, 0x0,
183 0xd4f, 0xffffffff, 0x171f1e,
184 0xd4e, 0xffffffff, 0x700010ff,
185 0xd4f, 0xffffffff, 0x0,
186 0xd4f, 0xffffffff, 0x0,
187 0xd4f, 0xffffffff, 0x0,
188 0xd4f, 0xffffffff, 0x0,
189 0xd4f, 0xffffffff, 0x0,
190 0xd4f, 0xffffffff, 0x0,
191 0xd4e, 0xffffffff, 0x9ff,
192 0xd40, 0xffffffff, 0x0,
193 0xd41, 0xffffffff, 0x10000800,
194 0xd41, 0xffffffff, 0xf,
195 0xd41, 0xffffffff, 0xf,
196 0xd40, 0xffffffff, 0x4,
197 0xd41, 0xffffffff, 0x1000051e,
198 0xd41, 0xffffffff, 0xffff,
199 0xd41, 0xffffffff, 0xffff,
200 0xd40, 0xffffffff, 0x8,
201 0xd41, 0xffffffff, 0x80500,
202 0xd40, 0xffffffff, 0x12,
203 0xd41, 0xffffffff, 0x9050c,
204 0xd40, 0xffffffff, 0x1d,
205 0xd41, 0xffffffff, 0xb052c,
206 0xd40, 0xffffffff, 0x2a,
207 0xd41, 0xffffffff, 0x1053e,
208 0xd40, 0xffffffff, 0x2d,
209 0xd41, 0xffffffff, 0x10546,
210 0xd40, 0xffffffff, 0x30,
211 0xd41, 0xffffffff, 0xa054e,
212 0xd40, 0xffffffff, 0x3c,
213 0xd41, 0xffffffff, 0x1055f,
214 0xd40, 0xffffffff, 0x3f,
215 0xd41, 0xffffffff, 0x10567,
216 0xd40, 0xffffffff, 0x42,
217 0xd41, 0xffffffff, 0x1056f,
218 0xd40, 0xffffffff, 0x45,
219 0xd41, 0xffffffff, 0x10572,
220 0xd40, 0xffffffff, 0x48,
221 0xd41, 0xffffffff, 0x20575,
222 0xd40, 0xffffffff, 0x4c,
223 0xd41, 0xffffffff, 0x190801,
224 0xd40, 0xffffffff, 0x67,
225 0xd41, 0xffffffff, 0x1082a,
226 0xd40, 0xffffffff, 0x6a,
227 0xd41, 0xffffffff, 0x1b082d,
228 0xd40, 0xffffffff, 0x87,
229 0xd41, 0xffffffff, 0x310851,
230 0xd40, 0xffffffff, 0xba,
231 0xd41, 0xffffffff, 0x891,
232 0xd40, 0xffffffff, 0xbc,
233 0xd41, 0xffffffff, 0x893,
234 0xd40, 0xffffffff, 0xbe,
235 0xd41, 0xffffffff, 0x20895,
236 0xd40, 0xffffffff, 0xc2,
237 0xd41, 0xffffffff, 0x20899,
238 0xd40, 0xffffffff, 0xc6,
239 0xd41, 0xffffffff, 0x2089d,
240 0xd40, 0xffffffff, 0xca,
241 0xd41, 0xffffffff, 0x8a1,
242 0xd40, 0xffffffff, 0xcc,
243 0xd41, 0xffffffff, 0x8a3,
244 0xd40, 0xffffffff, 0xce,
245 0xd41, 0xffffffff, 0x308a5,
246 0xd40, 0xffffffff, 0xd3,
247 0xd41, 0xffffffff, 0x6d08cd,
248 0xd40, 0xffffffff, 0x142,
249 0xd41, 0xffffffff, 0x2000095a,
250 0xd41, 0xffffffff, 0x1,
251 0xd40, 0xffffffff, 0x144,
252 0xd41, 0xffffffff, 0x301f095b,
253 0xd40, 0xffffffff, 0x165,
254 0xd41, 0xffffffff, 0xc094d,
255 0xd40, 0xffffffff, 0x173,
256 0xd41, 0xffffffff, 0xf096d,
257 0xd40, 0xffffffff, 0x184,
258 0xd41, 0xffffffff, 0x15097f,
259 0xd40, 0xffffffff, 0x19b,
260 0xd41, 0xffffffff, 0xc0998,
261 0xd40, 0xffffffff, 0x1a9,
262 0xd41, 0xffffffff, 0x409a7,
263 0xd40, 0xffffffff, 0x1af,
264 0xd41, 0xffffffff, 0xcdc,
265 0xd40, 0xffffffff, 0x1b1,
266 0xd41, 0xffffffff, 0x800,
267 0xd42, 0xffffffff, 0x6c9b2000,
268 0xd44, 0xfc00, 0x2000,
269 0xd51, 0xffffffff, 0xfc0,
270 0xa35, 0x00000100, 0x100
271};
272
273static const u32 verde_golden_rlc_registers[] =
274{
275 0x3109, 0xffffffff, 0x033f1005,
276 0x311f, 0xffffffff, 0x10808020,
277 0x3122, 0xffffffff, 0x00800008,
278 0x30c5, 0xffffffff, 0x00001000,
279 0x30c3, 0xffffffff, 0x80010014
280};
281
282static const u32 verde_golden_registers[] =
283{
284 0x2684, 0x00010000, 0x00018208,
285 0x260c, 0xffffffff, 0x00000000,
286 0x260d, 0xf00fffff, 0x00000400,
287 0x260e, 0x0002021c, 0x00020200,
288 0x031e, 0x00000080, 0x00000000,
289 0x340c, 0x000300c0, 0x00800040,
290 0x340c, 0x000300c0, 0x00800040,
291 0x360c, 0x000300c0, 0x00800040,
292 0x360c, 0x000300c0, 0x00800040,
293 0x16ec, 0x000000f0, 0x00000070,
294 0x16f0, 0x00200000, 0x50100000,
295
296 0x1c0c, 0x31000311, 0x00000011,
297 0x0ab9, 0x00073ffe, 0x000022a2,
298 0x0ab9, 0x00073ffe, 0x000022a2,
299 0x0ab9, 0x00073ffe, 0x000022a2,
300 0x0903, 0x000007ff, 0x00000000,
301 0x0903, 0x000007ff, 0x00000000,
302 0x0903, 0x000007ff, 0x00000000,
303 0x2285, 0xf000001f, 0x00000007,
304 0x2285, 0xf000001f, 0x00000007,
305 0x2285, 0xf000001f, 0x00000007,
306 0x2285, 0xffffffff, 0x00ffffff,
307 0x22c4, 0x0000ff0f, 0x00000000,
308
309 0xa293, 0x07ffffff, 0x4e000000,
310 0xa0d4, 0x3f3f3fff, 0x0000124a,
311 0xa0d4, 0x3f3f3fff, 0x0000124a,
312 0xa0d4, 0x3f3f3fff, 0x0000124a,
313 0x000c, 0x000000ff, 0x0040,
314 0x000d, 0x00000040, 0x00004040,
315 0x2440, 0x07ffffff, 0x03000000,
316 0x2440, 0x07ffffff, 0x03000000,
317 0x23a2, 0x01ff1f3f, 0x00000000,
318 0x23a3, 0x01ff1f3f, 0x00000000,
319 0x23a2, 0x01ff1f3f, 0x00000000,
320 0x23a1, 0x01ff1f3f, 0x00000000,
321 0x23a1, 0x01ff1f3f, 0x00000000,
322
323 0x23a1, 0x01ff1f3f, 0x00000000,
324 0x2418, 0x0000007f, 0x00000020,
325 0x2542, 0x00010000, 0x00010000,
326 0x2b01, 0x000003ff, 0x00000003,
327 0x2b05, 0x000003ff, 0x00000003,
328 0x2b05, 0x000003ff, 0x00000003,
329 0x2b04, 0xffffffff, 0x00000000,
330 0x2b04, 0xffffffff, 0x00000000,
331 0x2b04, 0xffffffff, 0x00000000,
332 0x2b03, 0xffffffff, 0x00001032,
333 0x2b03, 0xffffffff, 0x00001032,
334 0x2b03, 0xffffffff, 0x00001032,
335 0x2235, 0x0000001f, 0x00000010,
336 0x2235, 0x0000001f, 0x00000010,
337 0x2235, 0x0000001f, 0x00000010,
338 0x0570, 0x000c0fc0, 0x000c0400
339};
340
341static const u32 oland_golden_registers[] =
342{
343 0x2684, 0x00010000, 0x00018208,
344 0x260c, 0xffffffff, 0x00000000,
345 0x260d, 0xf00fffff, 0x00000400,
346 0x260e, 0x0002021c, 0x00020200,
347 0x031e, 0x00000080, 0x00000000,
348 0x340c, 0x000300c0, 0x00800040,
349 0x360c, 0x000300c0, 0x00800040,
350 0x16ec, 0x000000f0, 0x00000070,
351 0x16f9, 0x00200000, 0x50100000,
352 0x1c0c, 0x31000311, 0x00000011,
353 0x0ab9, 0x00073ffe, 0x000022a2,
354 0x0903, 0x000007ff, 0x00000000,
355 0x2285, 0xf000001f, 0x00000007,
356 0x22c9, 0xffffffff, 0x00ffffff,
357 0x22c4, 0x0000ff0f, 0x00000000,
358 0xa293, 0x07ffffff, 0x4e000000,
359 0xa0d4, 0x3f3f3fff, 0x00000082,
360 0x000c, 0x000000ff, 0x0040,
361 0x000d, 0x00000040, 0x00004040,
362 0x2440, 0x07ffffff, 0x03000000,
363 0x2418, 0x0000007f, 0x00000020,
364 0x2542, 0x00010000, 0x00010000,
365 0x2b05, 0x000003ff, 0x000000f3,
366 0x2b04, 0xffffffff, 0x00000000,
367 0x2b03, 0xffffffff, 0x00003210,
368 0x2235, 0x0000001f, 0x00000010,
369 0x0570, 0x000c0fc0, 0x000c0400
370};
371
372static const u32 oland_golden_rlc_registers[] =
373{
374 0x3109, 0xffffffff, 0x00601005,
375 0x311f, 0xffffffff, 0x10104040,
376 0x3122, 0xffffffff, 0x0100000a,
377 0x30c5, 0xffffffff, 0x00000800,
378 0x30c3, 0xffffffff, 0x800000f4
379};
380
381static const u32 hainan_golden_registers[] =
382{
383 0x2684, 0x00010000, 0x00018208,
384 0x260c, 0xffffffff, 0x00000000,
385 0x260d, 0xf00fffff, 0x00000400,
386 0x260e, 0x0002021c, 0x00020200,
387 0x4595, 0xff000fff, 0x00000100,
388 0x340c, 0x000300c0, 0x00800040,
389 0x3630, 0xff000fff, 0x00000100,
390 0x360c, 0x000300c0, 0x00800040,
391 0x0ab9, 0x00073ffe, 0x000022a2,
392 0x0903, 0x000007ff, 0x00000000,
393 0x2285, 0xf000001f, 0x00000007,
394 0x22c9, 0xffffffff, 0x00ffffff,
395 0x22c4, 0x0000ff0f, 0x00000000,
396 0xa393, 0x07ffffff, 0x4e000000,
397 0xa0d4, 0x3f3f3fff, 0x00000000,
398 0x000c, 0x000000ff, 0x0040,
399 0x000d, 0x00000040, 0x00004040,
400 0x2440, 0x03e00000, 0x03600000,
401 0x2418, 0x0000007f, 0x00000020,
402 0x2542, 0x00010000, 0x00010000,
403 0x2b05, 0x000003ff, 0x000000f1,
404 0x2b04, 0xffffffff, 0x00000000,
405 0x2b03, 0xffffffff, 0x00003210,
406 0x2235, 0x0000001f, 0x00000010,
407 0x0570, 0x000c0fc0, 0x000c0400
408};
409
410static const u32 hainan_golden_registers2[] =
411{
412 0x263e, 0xffffffff, 0x02010001
413};
414
415static const u32 tahiti_mgcg_cgcg_init[] =
416{
417 0x3100, 0xffffffff, 0xfffffffc,
418 0x200b, 0xffffffff, 0xe0000000,
419 0x2698, 0xffffffff, 0x00000100,
420 0x24a9, 0xffffffff, 0x00000100,
421 0x3059, 0xffffffff, 0x00000100,
422 0x25dd, 0xffffffff, 0x00000100,
423 0x2261, 0xffffffff, 0x06000100,
424 0x2286, 0xffffffff, 0x00000100,
425 0x24a8, 0xffffffff, 0x00000100,
426 0x30e0, 0xffffffff, 0x00000100,
427 0x22ca, 0xffffffff, 0x00000100,
428 0x2451, 0xffffffff, 0x00000100,
429 0x2362, 0xffffffff, 0x00000100,
430 0x2363, 0xffffffff, 0x00000100,
431 0x240c, 0xffffffff, 0x00000100,
432 0x240d, 0xffffffff, 0x00000100,
433 0x240e, 0xffffffff, 0x00000100,
434 0x240f, 0xffffffff, 0x00000100,
435 0x2b60, 0xffffffff, 0x00000100,
436 0x2b15, 0xffffffff, 0x00000100,
437 0x225f, 0xffffffff, 0x06000100,
438 0x261a, 0xffffffff, 0x00000100,
439 0x2544, 0xffffffff, 0x00000100,
440 0x2bc1, 0xffffffff, 0x00000100,
441 0x2b81, 0xffffffff, 0x00000100,
442 0x2527, 0xffffffff, 0x00000100,
443 0x200b, 0xffffffff, 0xe0000000,
444 0x2458, 0xffffffff, 0x00010000,
445 0x2459, 0xffffffff, 0x00030002,
446 0x245a, 0xffffffff, 0x00040007,
447 0x245b, 0xffffffff, 0x00060005,
448 0x245c, 0xffffffff, 0x00090008,
449 0x245d, 0xffffffff, 0x00020001,
450 0x245e, 0xffffffff, 0x00040003,
451 0x245f, 0xffffffff, 0x00000007,
452 0x2460, 0xffffffff, 0x00060005,
453 0x2461, 0xffffffff, 0x00090008,
454 0x2462, 0xffffffff, 0x00030002,
455 0x2463, 0xffffffff, 0x00050004,
456 0x2464, 0xffffffff, 0x00000008,
457 0x2465, 0xffffffff, 0x00070006,
458 0x2466, 0xffffffff, 0x000a0009,
459 0x2467, 0xffffffff, 0x00040003,
460 0x2468, 0xffffffff, 0x00060005,
461 0x2469, 0xffffffff, 0x00000009,
462 0x246a, 0xffffffff, 0x00080007,
463 0x246b, 0xffffffff, 0x000b000a,
464 0x246c, 0xffffffff, 0x00050004,
465 0x246d, 0xffffffff, 0x00070006,
466 0x246e, 0xffffffff, 0x0008000b,
467 0x246f, 0xffffffff, 0x000a0009,
468 0x2470, 0xffffffff, 0x000d000c,
469 0x2471, 0xffffffff, 0x00060005,
470 0x2472, 0xffffffff, 0x00080007,
471 0x2473, 0xffffffff, 0x0000000b,
472 0x2474, 0xffffffff, 0x000a0009,
473 0x2475, 0xffffffff, 0x000d000c,
474 0x2476, 0xffffffff, 0x00070006,
475 0x2477, 0xffffffff, 0x00090008,
476 0x2478, 0xffffffff, 0x0000000c,
477 0x2479, 0xffffffff, 0x000b000a,
478 0x247a, 0xffffffff, 0x000e000d,
479 0x247b, 0xffffffff, 0x00080007,
480 0x247c, 0xffffffff, 0x000a0009,
481 0x247d, 0xffffffff, 0x0000000d,
482 0x247e, 0xffffffff, 0x000c000b,
483 0x247f, 0xffffffff, 0x000f000e,
484 0x2480, 0xffffffff, 0x00090008,
485 0x2481, 0xffffffff, 0x000b000a,
486 0x2482, 0xffffffff, 0x000c000f,
487 0x2483, 0xffffffff, 0x000e000d,
488 0x2484, 0xffffffff, 0x00110010,
489 0x2485, 0xffffffff, 0x000a0009,
490 0x2486, 0xffffffff, 0x000c000b,
491 0x2487, 0xffffffff, 0x0000000f,
492 0x2488, 0xffffffff, 0x000e000d,
493 0x2489, 0xffffffff, 0x00110010,
494 0x248a, 0xffffffff, 0x000b000a,
495 0x248b, 0xffffffff, 0x000d000c,
496 0x248c, 0xffffffff, 0x00000010,
497 0x248d, 0xffffffff, 0x000f000e,
498 0x248e, 0xffffffff, 0x00120011,
499 0x248f, 0xffffffff, 0x000c000b,
500 0x2490, 0xffffffff, 0x000e000d,
501 0x2491, 0xffffffff, 0x00000011,
502 0x2492, 0xffffffff, 0x0010000f,
503 0x2493, 0xffffffff, 0x00130012,
504 0x2494, 0xffffffff, 0x000d000c,
505 0x2495, 0xffffffff, 0x000f000e,
506 0x2496, 0xffffffff, 0x00100013,
507 0x2497, 0xffffffff, 0x00120011,
508 0x2498, 0xffffffff, 0x00150014,
509 0x2499, 0xffffffff, 0x000e000d,
510 0x249a, 0xffffffff, 0x0010000f,
511 0x249b, 0xffffffff, 0x00000013,
512 0x249c, 0xffffffff, 0x00120011,
513 0x249d, 0xffffffff, 0x00150014,
514 0x249e, 0xffffffff, 0x000f000e,
515 0x249f, 0xffffffff, 0x00110010,
516 0x24a0, 0xffffffff, 0x00000014,
517 0x24a1, 0xffffffff, 0x00130012,
518 0x24a2, 0xffffffff, 0x00160015,
519 0x24a3, 0xffffffff, 0x0010000f,
520 0x24a4, 0xffffffff, 0x00120011,
521 0x24a5, 0xffffffff, 0x00000015,
522 0x24a6, 0xffffffff, 0x00140013,
523 0x24a7, 0xffffffff, 0x00170016,
524 0x2454, 0xffffffff, 0x96940200,
525 0x21c2, 0xffffffff, 0x00900100,
526 0x311e, 0xffffffff, 0x00000080,
527 0x3101, 0xffffffff, 0x0020003f,
7c0a705e
FC		 528 0x000c, 0xffffffff, 0x0000001c,
529 0x000d, 0x000f0000, 0x000f0000,
530 0x0583, 0xffffffff, 0x00000100,
531 0x0409, 0xffffffff, 0x00000100,
532 0x040b, 0x00000101, 0x00000000,
533 0x082a, 0xffffffff, 0x00000104,
534 0x0993, 0x000c0000, 0x000c0000,
535 0x0992, 0x000c0000, 0x000c0000,
62a37553
KW		 536 0x1579, 0xff000fff, 0x00000100,
537 0x157a, 0x00000001, 0x00000001,
7c0a705e
FC		 538 0x0bd4, 0x00000001, 0x00000001,
539 0x0c33, 0xc0000fff, 0x00000104,
62a37553
KW		 540 0x3079, 0x00000001, 0x00000001,
541 0x3430, 0xfffffff0, 0x00000100,
542 0x3630, 0xfffffff0, 0x00000100
543};
544static const u32 pitcairn_mgcg_cgcg_init[] =
545{
546 0x3100, 0xffffffff, 0xfffffffc,
547 0x200b, 0xffffffff, 0xe0000000,
548 0x2698, 0xffffffff, 0x00000100,
549 0x24a9, 0xffffffff, 0x00000100,
550 0x3059, 0xffffffff, 0x00000100,
551 0x25dd, 0xffffffff, 0x00000100,
552 0x2261, 0xffffffff, 0x06000100,
553 0x2286, 0xffffffff, 0x00000100,
554 0x24a8, 0xffffffff, 0x00000100,
555 0x30e0, 0xffffffff, 0x00000100,
556 0x22ca, 0xffffffff, 0x00000100,
557 0x2451, 0xffffffff, 0x00000100,
558 0x2362, 0xffffffff, 0x00000100,
559 0x2363, 0xffffffff, 0x00000100,
560 0x240c, 0xffffffff, 0x00000100,
561 0x240d, 0xffffffff, 0x00000100,
562 0x240e, 0xffffffff, 0x00000100,
563 0x240f, 0xffffffff, 0x00000100,
564 0x2b60, 0xffffffff, 0x00000100,
565 0x2b15, 0xffffffff, 0x00000100,
566 0x225f, 0xffffffff, 0x06000100,
567 0x261a, 0xffffffff, 0x00000100,
568 0x2544, 0xffffffff, 0x00000100,
569 0x2bc1, 0xffffffff, 0x00000100,
570 0x2b81, 0xffffffff, 0x00000100,
571 0x2527, 0xffffffff, 0x00000100,
572 0x200b, 0xffffffff, 0xe0000000,
573 0x2458, 0xffffffff, 0x00010000,
574 0x2459, 0xffffffff, 0x00030002,
575 0x245a, 0xffffffff, 0x00040007,
576 0x245b, 0xffffffff, 0x00060005,
577 0x245c, 0xffffffff, 0x00090008,
578 0x245d, 0xffffffff, 0x00020001,
579 0x245e, 0xffffffff, 0x00040003,
580 0x245f, 0xffffffff, 0x00000007,
581 0x2460, 0xffffffff, 0x00060005,
582 0x2461, 0xffffffff, 0x00090008,
583 0x2462, 0xffffffff, 0x00030002,
584 0x2463, 0xffffffff, 0x00050004,
585 0x2464, 0xffffffff, 0x00000008,
586 0x2465, 0xffffffff, 0x00070006,
587 0x2466, 0xffffffff, 0x000a0009,
588 0x2467, 0xffffffff, 0x00040003,
589 0x2468, 0xffffffff, 0x00060005,
590 0x2469, 0xffffffff, 0x00000009,
591 0x246a, 0xffffffff, 0x00080007,
592 0x246b, 0xffffffff, 0x000b000a,
593 0x246c, 0xffffffff, 0x00050004,
594 0x246d, 0xffffffff, 0x00070006,
595 0x246e, 0xffffffff, 0x0008000b,
596 0x246f, 0xffffffff, 0x000a0009,
597 0x2470, 0xffffffff, 0x000d000c,
598 0x2480, 0xffffffff, 0x00090008,
599 0x2481, 0xffffffff, 0x000b000a,
600 0x2482, 0xffffffff, 0x000c000f,
601 0x2483, 0xffffffff, 0x000e000d,
602 0x2484, 0xffffffff, 0x00110010,
603 0x2485, 0xffffffff, 0x000a0009,
604 0x2486, 0xffffffff, 0x000c000b,
605 0x2487, 0xffffffff, 0x0000000f,
606 0x2488, 0xffffffff, 0x000e000d,
607 0x2489, 0xffffffff, 0x00110010,
608 0x248a, 0xffffffff, 0x000b000a,
609 0x248b, 0xffffffff, 0x000d000c,
610 0x248c, 0xffffffff, 0x00000010,
611 0x248d, 0xffffffff, 0x000f000e,
612 0x248e, 0xffffffff, 0x00120011,
613 0x248f, 0xffffffff, 0x000c000b,
614 0x2490, 0xffffffff, 0x000e000d,
615 0x2491, 0xffffffff, 0x00000011,
616 0x2492, 0xffffffff, 0x0010000f,
617 0x2493, 0xffffffff, 0x00130012,
618 0x2494, 0xffffffff, 0x000d000c,
619 0x2495, 0xffffffff, 0x000f000e,
620 0x2496, 0xffffffff, 0x00100013,
621 0x2497, 0xffffffff, 0x00120011,
622 0x2498, 0xffffffff, 0x00150014,
623 0x2454, 0xffffffff, 0x96940200,
624 0x21c2, 0xffffffff, 0x00900100,
625 0x311e, 0xffffffff, 0x00000080,
626 0x3101, 0xffffffff, 0x0020003f,
1245a694
FC		 627 0x000c, 0xffffffff, 0x0000001c,
628 0x000d, 0x000f0000, 0x000f0000,
629 0x0583, 0xffffffff, 0x00000100,
630 0x0409, 0xffffffff, 0x00000100,
631 0x040b, 0x00000101, 0x00000000,
632 0x082a, 0xffffffff, 0x00000104,
62a37553
KW		 633 0x1579, 0xff000fff, 0x00000100,
634 0x157a, 0x00000001, 0x00000001,
1245a694
FC		 635 0x0bd4, 0x00000001, 0x00000001,
636 0x0c33, 0xc0000fff, 0x00000104,
62a37553
KW		 637 0x3079, 0x00000001, 0x00000001,
638 0x3430, 0xfffffff0, 0x00000100,
639 0x3630, 0xfffffff0, 0x00000100
640};
641static const u32 verde_mgcg_cgcg_init[] =
642{
643 0x3100, 0xffffffff, 0xfffffffc,
644 0x200b, 0xffffffff, 0xe0000000,
645 0x2698, 0xffffffff, 0x00000100,
646 0x24a9, 0xffffffff, 0x00000100,
647 0x3059, 0xffffffff, 0x00000100,
648 0x25dd, 0xffffffff, 0x00000100,
649 0x2261, 0xffffffff, 0x06000100,
650 0x2286, 0xffffffff, 0x00000100,
651 0x24a8, 0xffffffff, 0x00000100,
652 0x30e0, 0xffffffff, 0x00000100,
653 0x22ca, 0xffffffff, 0x00000100,
654 0x2451, 0xffffffff, 0x00000100,
655 0x2362, 0xffffffff, 0x00000100,
656 0x2363, 0xffffffff, 0x00000100,
657 0x240c, 0xffffffff, 0x00000100,
658 0x240d, 0xffffffff, 0x00000100,
659 0x240e, 0xffffffff, 0x00000100,
660 0x240f, 0xffffffff, 0x00000100,
661 0x2b60, 0xffffffff, 0x00000100,
662 0x2b15, 0xffffffff, 0x00000100,
663 0x225f, 0xffffffff, 0x06000100,
664 0x261a, 0xffffffff, 0x00000100,
665 0x2544, 0xffffffff, 0x00000100,
666 0x2bc1, 0xffffffff, 0x00000100,
667 0x2b81, 0xffffffff, 0x00000100,
668 0x2527, 0xffffffff, 0x00000100,
669 0x200b, 0xffffffff, 0xe0000000,
670 0x2458, 0xffffffff, 0x00010000,
671 0x2459, 0xffffffff, 0x00030002,
672 0x245a, 0xffffffff, 0x00040007,
673 0x245b, 0xffffffff, 0x00060005,
674 0x245c, 0xffffffff, 0x00090008,
675 0x245d, 0xffffffff, 0x00020001,
676 0x245e, 0xffffffff, 0x00040003,
677 0x245f, 0xffffffff, 0x00000007,
678 0x2460, 0xffffffff, 0x00060005,
679 0x2461, 0xffffffff, 0x00090008,
680 0x2462, 0xffffffff, 0x00030002,
681 0x2463, 0xffffffff, 0x00050004,
682 0x2464, 0xffffffff, 0x00000008,
683 0x2465, 0xffffffff, 0x00070006,
684 0x2466, 0xffffffff, 0x000a0009,
685 0x2467, 0xffffffff, 0x00040003,
686 0x2468, 0xffffffff, 0x00060005,
687 0x2469, 0xffffffff, 0x00000009,
688 0x246a, 0xffffffff, 0x00080007,
689 0x246b, 0xffffffff, 0x000b000a,
690 0x246c, 0xffffffff, 0x00050004,
691 0x246d, 0xffffffff, 0x00070006,
692 0x246e, 0xffffffff, 0x0008000b,
693 0x246f, 0xffffffff, 0x000a0009,
694 0x2470, 0xffffffff, 0x000d000c,
695 0x2480, 0xffffffff, 0x00090008,
696 0x2481, 0xffffffff, 0x000b000a,
697 0x2482, 0xffffffff, 0x000c000f,
698 0x2483, 0xffffffff, 0x000e000d,
699 0x2484, 0xffffffff, 0x00110010,
700 0x2485, 0xffffffff, 0x000a0009,
701 0x2486, 0xffffffff, 0x000c000b,
702 0x2487, 0xffffffff, 0x0000000f,
703 0x2488, 0xffffffff, 0x000e000d,
704 0x2489, 0xffffffff, 0x00110010,
705 0x248a, 0xffffffff, 0x000b000a,
706 0x248b, 0xffffffff, 0x000d000c,
707 0x248c, 0xffffffff, 0x00000010,
708 0x248d, 0xffffffff, 0x000f000e,
709 0x248e, 0xffffffff, 0x00120011,
710 0x248f, 0xffffffff, 0x000c000b,
711 0x2490, 0xffffffff, 0x000e000d,
712 0x2491, 0xffffffff, 0x00000011,
713 0x2492, 0xffffffff, 0x0010000f,
714 0x2493, 0xffffffff, 0x00130012,
715 0x2494, 0xffffffff, 0x000d000c,
716 0x2495, 0xffffffff, 0x000f000e,
717 0x2496, 0xffffffff, 0x00100013,
718 0x2497, 0xffffffff, 0x00120011,
719 0x2498, 0xffffffff, 0x00150014,
720 0x2454, 0xffffffff, 0x96940200,
721 0x21c2, 0xffffffff, 0x00900100,
722 0x311e, 0xffffffff, 0x00000080,
723 0x3101, 0xffffffff, 0x0020003f,
724 0xc, 0xffffffff, 0x0000001c,
725 0xd, 0x000f0000, 0x000f0000,
726 0x583, 0xffffffff, 0x00000100,
727 0x409, 0xffffffff, 0x00000100,
728 0x40b, 0x00000101, 0x00000000,
729 0x82a, 0xffffffff, 0x00000104,
730 0x993, 0x000c0000, 0x000c0000,
731 0x992, 0x000c0000, 0x000c0000,
732 0x1579, 0xff000fff, 0x00000100,
733 0x157a, 0x00000001, 0x00000001,
734 0xbd4, 0x00000001, 0x00000001,
735 0xc33, 0xc0000fff, 0x00000104,
736 0x3079, 0x00000001, 0x00000001,
737 0x3430, 0xfffffff0, 0x00000100,
738 0x3630, 0xfffffff0, 0x00000100
739};
740static const u32 oland_mgcg_cgcg_init[] =
741{
742 0x3100, 0xffffffff, 0xfffffffc,
743 0x200b, 0xffffffff, 0xe0000000,
744 0x2698, 0xffffffff, 0x00000100,
745 0x24a9, 0xffffffff, 0x00000100,
746 0x3059, 0xffffffff, 0x00000100,
747 0x25dd, 0xffffffff, 0x00000100,
748 0x2261, 0xffffffff, 0x06000100,
749 0x2286, 0xffffffff, 0x00000100,
750 0x24a8, 0xffffffff, 0x00000100,
751 0x30e0, 0xffffffff, 0x00000100,
752 0x22ca, 0xffffffff, 0x00000100,
753 0x2451, 0xffffffff, 0x00000100,
754 0x2362, 0xffffffff, 0x00000100,
755 0x2363, 0xffffffff, 0x00000100,
756 0x240c, 0xffffffff, 0x00000100,
757 0x240d, 0xffffffff, 0x00000100,
758 0x240e, 0xffffffff, 0x00000100,
759 0x240f, 0xffffffff, 0x00000100,
760 0x2b60, 0xffffffff, 0x00000100,
761 0x2b15, 0xffffffff, 0x00000100,
762 0x225f, 0xffffffff, 0x06000100,
763 0x261a, 0xffffffff, 0x00000100,
764 0x2544, 0xffffffff, 0x00000100,
765 0x2bc1, 0xffffffff, 0x00000100,
766 0x2b81, 0xffffffff, 0x00000100,
767 0x2527, 0xffffffff, 0x00000100,
768 0x200b, 0xffffffff, 0xe0000000,
769 0x2458, 0xffffffff, 0x00010000,
770 0x2459, 0xffffffff, 0x00030002,
771 0x245a, 0xffffffff, 0x00040007,
772 0x245b, 0xffffffff, 0x00060005,
773 0x245c, 0xffffffff, 0x00090008,
774 0x245d, 0xffffffff, 0x00020001,
775 0x245e, 0xffffffff, 0x00040003,
776 0x245f, 0xffffffff, 0x00000007,
777 0x2460, 0xffffffff, 0x00060005,
778 0x2461, 0xffffffff, 0x00090008,
779 0x2462, 0xffffffff, 0x00030002,
780 0x2463, 0xffffffff, 0x00050004,
781 0x2464, 0xffffffff, 0x00000008,
782 0x2465, 0xffffffff, 0x00070006,
783 0x2466, 0xffffffff, 0x000a0009,
784 0x2467, 0xffffffff, 0x00040003,
785 0x2468, 0xffffffff, 0x00060005,
786 0x2469, 0xffffffff, 0x00000009,
787 0x246a, 0xffffffff, 0x00080007,
788 0x246b, 0xffffffff, 0x000b000a,
789 0x246c, 0xffffffff, 0x00050004,
790 0x246d, 0xffffffff, 0x00070006,
791 0x246e, 0xffffffff, 0x0008000b,
792 0x246f, 0xffffffff, 0x000a0009,
793 0x2470, 0xffffffff, 0x000d000c,
794 0x2471, 0xffffffff, 0x00060005,
795 0x2472, 0xffffffff, 0x00080007,
796 0x2473, 0xffffffff, 0x0000000b,
797 0x2474, 0xffffffff, 0x000a0009,
798 0x2475, 0xffffffff, 0x000d000c,
799 0x2454, 0xffffffff, 0x96940200,
800 0x21c2, 0xffffffff, 0x00900100,
801 0x311e, 0xffffffff, 0x00000080,
802 0x3101, 0xffffffff, 0x0020003f,
803 0xc, 0xffffffff, 0x0000001c,
804 0xd, 0x000f0000, 0x000f0000,
805 0x583, 0xffffffff, 0x00000100,
806 0x409, 0xffffffff, 0x00000100,
807 0x40b, 0x00000101, 0x00000000,
808 0x82a, 0xffffffff, 0x00000104,
809 0x993, 0x000c0000, 0x000c0000,
810 0x992, 0x000c0000, 0x000c0000,
811 0x1579, 0xff000fff, 0x00000100,
812 0x157a, 0x00000001, 0x00000001,
813 0xbd4, 0x00000001, 0x00000001,
814 0xc33, 0xc0000fff, 0x00000104,
815 0x3079, 0x00000001, 0x00000001,
816 0x3430, 0xfffffff0, 0x00000100,
817 0x3630, 0xfffffff0, 0x00000100
818};
819static const u32 hainan_mgcg_cgcg_init[] =
820{
821 0x3100, 0xffffffff, 0xfffffffc,
822 0x200b, 0xffffffff, 0xe0000000,
823 0x2698, 0xffffffff, 0x00000100,
824 0x24a9, 0xffffffff, 0x00000100,
825 0x3059, 0xffffffff, 0x00000100,
826 0x25dd, 0xffffffff, 0x00000100,
827 0x2261, 0xffffffff, 0x06000100,
828 0x2286, 0xffffffff, 0x00000100,
829 0x24a8, 0xffffffff, 0x00000100,
830 0x30e0, 0xffffffff, 0x00000100,
831 0x22ca, 0xffffffff, 0x00000100,
832 0x2451, 0xffffffff, 0x00000100,
833 0x2362, 0xffffffff, 0x00000100,
834 0x2363, 0xffffffff, 0x00000100,
835 0x240c, 0xffffffff, 0x00000100,
836 0x240d, 0xffffffff, 0x00000100,
837 0x240e, 0xffffffff, 0x00000100,
838 0x240f, 0xffffffff, 0x00000100,
839 0x2b60, 0xffffffff, 0x00000100,
840 0x2b15, 0xffffffff, 0x00000100,
841 0x225f, 0xffffffff, 0x06000100,
842 0x261a, 0xffffffff, 0x00000100,
843 0x2544, 0xffffffff, 0x00000100,
844 0x2bc1, 0xffffffff, 0x00000100,
845 0x2b81, 0xffffffff, 0x00000100,
846 0x2527, 0xffffffff, 0x00000100,
847 0x200b, 0xffffffff, 0xe0000000,
848 0x2458, 0xffffffff, 0x00010000,
849 0x2459, 0xffffffff, 0x00030002,
850 0x245a, 0xffffffff, 0x00040007,
851 0x245b, 0xffffffff, 0x00060005,
852 0x245c, 0xffffffff, 0x00090008,
853 0x245d, 0xffffffff, 0x00020001,
854 0x245e, 0xffffffff, 0x00040003,
855 0x245f, 0xffffffff, 0x00000007,
856 0x2460, 0xffffffff, 0x00060005,
857 0x2461, 0xffffffff, 0x00090008,
858 0x2462, 0xffffffff, 0x00030002,
859 0x2463, 0xffffffff, 0x00050004,
860 0x2464, 0xffffffff, 0x00000008,
861 0x2465, 0xffffffff, 0x00070006,
862 0x2466, 0xffffffff, 0x000a0009,
863 0x2467, 0xffffffff, 0x00040003,
864 0x2468, 0xffffffff, 0x00060005,
865 0x2469, 0xffffffff, 0x00000009,
866 0x246a, 0xffffffff, 0x00080007,
867 0x246b, 0xffffffff, 0x000b000a,
868 0x246c, 0xffffffff, 0x00050004,
869 0x246d, 0xffffffff, 0x00070006,
870 0x246e, 0xffffffff, 0x0008000b,
871 0x246f, 0xffffffff, 0x000a0009,
872 0x2470, 0xffffffff, 0x000d000c,
873 0x2471, 0xffffffff, 0x00060005,
874 0x2472, 0xffffffff, 0x00080007,
875 0x2473, 0xffffffff, 0x0000000b,
876 0x2474, 0xffffffff, 0x000a0009,
877 0x2475, 0xffffffff, 0x000d000c,
878 0x2454, 0xffffffff, 0x96940200,
879 0x21c2, 0xffffffff, 0x00900100,
880 0x311e, 0xffffffff, 0x00000080,
881 0x3101, 0xffffffff, 0x0020003f,
882 0xc, 0xffffffff, 0x0000001c,
883 0xd, 0x000f0000, 0x000f0000,
884 0x583, 0xffffffff, 0x00000100,
885 0x409, 0xffffffff, 0x00000100,
886 0x82a, 0xffffffff, 0x00000104,
887 0x993, 0x000c0000, 0x000c0000,
888 0x992, 0x000c0000, 0x000c0000,
889 0xbd4, 0x00000001, 0x00000001,
890 0xc33, 0xc0000fff, 0x00000104,
891 0x3079, 0x00000001, 0x00000001,
892 0x3430, 0xfffffff0, 0x00000100,
893 0x3630, 0xfffffff0, 0x00000100
894};
895
896static u32 si_pcie_rreg(struct amdgpu_device *adev, u32 reg)
897{
898 unsigned long flags;
899 u32 r;
900
901 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
902 WREG32(AMDGPU_PCIE_INDEX, reg);
903 (void)RREG32(AMDGPU_PCIE_INDEX);
904 r = RREG32(AMDGPU_PCIE_DATA);
905 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
906 return r;
907}
908
909static void si_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
910{
911 unsigned long flags;
912
913 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
914 WREG32(AMDGPU_PCIE_INDEX, reg);
915 (void)RREG32(AMDGPU_PCIE_INDEX);
916 WREG32(AMDGPU_PCIE_DATA, v);
917 (void)RREG32(AMDGPU_PCIE_DATA);
918 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
919}
920
d1936cc2 921static u32 si_pciep_rreg(struct amdgpu_device *adev, u32 reg)
36b9a952
HR		 922{
923 unsigned long flags;
924 u32 r;
925
926 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
927 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
928 (void)RREG32(PCIE_PORT_INDEX);
929 r = RREG32(PCIE_PORT_DATA);
930 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
931 return r;
932}
933
d1936cc2 934static void si_pciep_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
36b9a952
HR		 935{
936 unsigned long flags;
937
938 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
939 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
940 (void)RREG32(PCIE_PORT_INDEX);
941 WREG32(PCIE_PORT_DATA, (v));
942 (void)RREG32(PCIE_PORT_DATA);
943 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
944}
945
62a37553
KW		 946static u32 si_smc_rreg(struct amdgpu_device *adev, u32 reg)
947{
948 unsigned long flags;
949 u32 r;
950
951 spin_lock_irqsave(&adev->smc_idx_lock, flags);
952 WREG32(SMC_IND_INDEX_0, (reg));
953 r = RREG32(SMC_IND_DATA_0);
954 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
955 return r;
956}
957
958static void si_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
959{
960 unsigned long flags;
961
962 spin_lock_irqsave(&adev->smc_idx_lock, flags);
963 WREG32(SMC_IND_INDEX_0, (reg));
964 WREG32(SMC_IND_DATA_0, (v));
965 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
966}
967
62a37553
KW		 968static struct amdgpu_allowed_register_entry si_allowed_read_registers[] = {
969 {GRBM_STATUS, false},
970 {GB_ADDR_CONFIG, false},
971 {MC_ARB_RAMCFG, false},
972 {GB_TILE_MODE0, false},
973 {GB_TILE_MODE1, false},
974 {GB_TILE_MODE2, false},
975 {GB_TILE_MODE3, false},
976 {GB_TILE_MODE4, false},
977 {GB_TILE_MODE5, false},
978 {GB_TILE_MODE6, false},
979 {GB_TILE_MODE7, false},
980 {GB_TILE_MODE8, false},
981 {GB_TILE_MODE9, false},
982 {GB_TILE_MODE10, false},
983 {GB_TILE_MODE11, false},
984 {GB_TILE_MODE12, false},
985 {GB_TILE_MODE13, false},
986 {GB_TILE_MODE14, false},
987 {GB_TILE_MODE15, false},
988 {GB_TILE_MODE16, false},
989 {GB_TILE_MODE17, false},
990 {GB_TILE_MODE18, false},
991 {GB_TILE_MODE19, false},
992 {GB_TILE_MODE20, false},
993 {GB_TILE_MODE21, false},
994 {GB_TILE_MODE22, false},
995 {GB_TILE_MODE23, false},
996 {GB_TILE_MODE24, false},
997 {GB_TILE_MODE25, false},
998 {GB_TILE_MODE26, false},
999 {GB_TILE_MODE27, false},
1000 {GB_TILE_MODE28, false},
1001 {GB_TILE_MODE29, false},
1002 {GB_TILE_MODE30, false},
1003 {GB_TILE_MODE31, false},
1004 {CC_RB_BACKEND_DISABLE, false, true},
1005 {GC_USER_RB_BACKEND_DISABLE, false, true},
1006 {PA_SC_RASTER_CONFIG, false, true},
1007};
1008
1009static uint32_t si_read_indexed_register(struct amdgpu_device *adev,
1010 u32 se_num, u32 sh_num,
1011 u32 reg_offset)
1012{
1013 uint32_t val;
1014
1015 mutex_lock(&adev->grbm_idx_mutex);
1016 if (se_num != 0xffffffff || sh_num != 0xffffffff)
1017 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
1018
1019 val = RREG32(reg_offset);
1020
1021 if (se_num != 0xffffffff || sh_num != 0xffffffff)
1022 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1023 mutex_unlock(&adev->grbm_idx_mutex);
1024 return val;
1025}
1026
1027static int si_read_register(struct amdgpu_device *adev, u32 se_num,
1028 u32 sh_num, u32 reg_offset, u32 *value)
1029{
1030 uint32_t i;
1031
1032 *value = 0;
1033 for (i = 0; i < ARRAY_SIZE(si_allowed_read_registers); i++) {
1034 if (reg_offset != si_allowed_read_registers[i].reg_offset)
1035 continue;
1036
1037 if (!si_allowed_read_registers[i].untouched)
1038 *value = si_allowed_read_registers[i].grbm_indexed ?
1039 si_read_indexed_register(adev, se_num,
1040 sh_num, reg_offset) :
1041 RREG32(reg_offset);
1042 return 0;
1043 }
1044 return -EINVAL;
1045}
1046
1047static bool si_read_disabled_bios(struct amdgpu_device *adev)
1048{
1049 u32 bus_cntl;
1050 u32 d1vga_control = 0;
1051 u32 d2vga_control = 0;
1052 u32 vga_render_control = 0;
1053 u32 rom_cntl;
1054 bool r;
1055
1056 bus_cntl = RREG32(R600_BUS_CNTL);
1057 if (adev->mode_info.num_crtc) {
1058 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
1059 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
1060 vga_render_control = RREG32(VGA_RENDER_CONTROL);
1061 }
1062 rom_cntl = RREG32(R600_ROM_CNTL);
1063
1064 /* enable the rom */
1065 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
1066 if (adev->mode_info.num_crtc) {
1067 /* Disable VGA mode */
1068 WREG32(AVIVO_D1VGA_CONTROL,
1069 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
1070 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
1071 WREG32(AVIVO_D2VGA_CONTROL,
1072 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
1073 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
1074 WREG32(VGA_RENDER_CONTROL,
1075 (vga_render_control & C_000300_VGA_VSTATUS_CNTL));
1076 }
1077 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
1078
1079 r = amdgpu_read_bios(adev);
1080
1081 /* restore regs */
1082 WREG32(R600_BUS_CNTL, bus_cntl);
1083 if (adev->mode_info.num_crtc) {
1084 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
1085 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
1086 WREG32(VGA_RENDER_CONTROL, vga_render_control);
1087 }
1088 WREG32(R600_ROM_CNTL, rom_cntl);
1089 return r;
1090}
1091
1092//xxx: not implemented
1093static int si_asic_reset(struct amdgpu_device *adev)
1094{
1095 return 0;
1096}
1097
1098static void si_vga_set_state(struct amdgpu_device *adev, bool state)
1099{
1100 uint32_t temp;
1101
1102 temp = RREG32(CONFIG_CNTL);
1103 if (state == false) {
1104 temp &= ~(1<<0);
1105 temp |= (1<<1);
1106 } else {
1107 temp &= ~(1<<1);
1108 }
1109 WREG32(CONFIG_CNTL, temp);
1110}
1111
1112static u32 si_get_xclk(struct amdgpu_device *adev)
1113{
1114 u32 reference_clock = adev->clock.spll.reference_freq;
1115 u32 tmp;
1116
1117 tmp = RREG32(CG_CLKPIN_CNTL_2);
1118 if (tmp & MUX_TCLK_TO_XCLK)
1119 return TCLK;
1120
1121 tmp = RREG32(CG_CLKPIN_CNTL);
1122 if (tmp & XTALIN_DIVIDE)
1123 return reference_clock / 4;
1124
1125 return reference_clock;
1126}
1919696e 1127
62a37553
KW		 1128//xxx:not implemented
1129static int si_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
1130{
1131 return 0;
1132}
1133
4e99a44e
ML		 1134static void si_detect_hw_virtualization(struct amdgpu_device *adev)
1135{
1136 if (is_virtual_machine()) /* passthrough mode */
1137 adev->virtualization.virtual_caps |= AMDGPU_PASSTHROUGH_MODE;
1138}
1139
62a37553
KW		 1140static const struct amdgpu_asic_funcs si_asic_funcs =
1141{
1142 .read_disabled_bios = &si_read_disabled_bios,
4e99a44e 1143 .detect_hw_virtualization = si_detect_hw_virtualization,
62a37553
KW		 1144 .read_register = &si_read_register,
1145 .reset = &si_asic_reset,
1146 .set_vga_state = &si_vga_set_state,
1147 .get_xclk = &si_get_xclk,
1148 .set_uvd_clocks = &si_set_uvd_clocks,
1149 .set_vce_clocks = NULL,
62a37553
KW		 1150};
1151
1152static uint32_t si_get_rev_id(struct amdgpu_device *adev)
1153{
1154 return (RREG32(CC_DRM_ID_STRAPS) & CC_DRM_ID_STRAPS__ATI_REV_ID_MASK)
1155 >> CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT;
1156}
1157
1158static int si_common_early_init(void *handle)
1159{
1160 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1161
1162 adev->smc_rreg = &si_smc_rreg;
1163 adev->smc_wreg = &si_smc_wreg;
1164 adev->pcie_rreg = &si_pcie_rreg;
1165 adev->pcie_wreg = &si_pcie_wreg;
36b9a952
HR		 1166 adev->pciep_rreg = &si_pciep_rreg;
1167 adev->pciep_wreg = &si_pciep_wreg;
62a37553
KW		 1168 adev->uvd_ctx_rreg = NULL;
1169 adev->uvd_ctx_wreg = NULL;
1170 adev->didt_rreg = NULL;
1171 adev->didt_wreg = NULL;
1172
1173 adev->asic_funcs = &si_asic_funcs;
1174
1175 adev->rev_id = si_get_rev_id(adev);
1176 adev->external_rev_id = 0xFF;
1177 switch (adev->asic_type) {
1178 case CHIP_TAHITI:
1179 adev->cg_flags =
1180 AMD_CG_SUPPORT_GFX_MGCG |
1181 AMD_CG_SUPPORT_GFX_MGLS |
1182 /*AMD_CG_SUPPORT_GFX_CGCG |*/
1183 AMD_CG_SUPPORT_GFX_CGLS |
1184 AMD_CG_SUPPORT_GFX_CGTS |
1185 AMD_CG_SUPPORT_GFX_CP_LS |
1186 AMD_CG_SUPPORT_MC_MGCG |
1187 AMD_CG_SUPPORT_SDMA_MGCG |
1188 AMD_CG_SUPPORT_BIF_LS |
1189 AMD_CG_SUPPORT_VCE_MGCG |
1190 AMD_CG_SUPPORT_UVD_MGCG |
1191 AMD_CG_SUPPORT_HDP_LS |
1192 AMD_CG_SUPPORT_HDP_MGCG;
1193 adev->pg_flags = 0;
7c0a705e
FC		 1194 adev->external_rev_id = (adev->rev_id == 0) ? 1 :
1195 (adev->rev_id == 1) ? 5 : 6;
62a37553
KW		 1196 break;
1197 case CHIP_PITCAIRN:
1198 adev->cg_flags =
1199 AMD_CG_SUPPORT_GFX_MGCG |
1200 AMD_CG_SUPPORT_GFX_MGLS |
1201 /*AMD_CG_SUPPORT_GFX_CGCG |*/
1202 AMD_CG_SUPPORT_GFX_CGLS |
1203 AMD_CG_SUPPORT_GFX_CGTS |
1204 AMD_CG_SUPPORT_GFX_CP_LS |
1205 AMD_CG_SUPPORT_GFX_RLC_LS |
1206 AMD_CG_SUPPORT_MC_LS |
1207 AMD_CG_SUPPORT_MC_MGCG |
1208 AMD_CG_SUPPORT_SDMA_MGCG |
1209 AMD_CG_SUPPORT_BIF_LS |
1210 AMD_CG_SUPPORT_VCE_MGCG |
1211 AMD_CG_SUPPORT_UVD_MGCG |
1212 AMD_CG_SUPPORT_HDP_LS |
1213 AMD_CG_SUPPORT_HDP_MGCG;
1214 adev->pg_flags = 0;
1215 break;
1216
1217 case CHIP_VERDE:
1218 adev->cg_flags =
1219 AMD_CG_SUPPORT_GFX_MGCG |
1220 AMD_CG_SUPPORT_GFX_MGLS |
1221 AMD_CG_SUPPORT_GFX_CGLS |
1222 AMD_CG_SUPPORT_GFX_CGTS |
1223 AMD_CG_SUPPORT_GFX_CGTS_LS |
1224 AMD_CG_SUPPORT_GFX_CP_LS |
1225 AMD_CG_SUPPORT_MC_LS |
1226 AMD_CG_SUPPORT_MC_MGCG |
1227 AMD_CG_SUPPORT_SDMA_MGCG |
1228 AMD_CG_SUPPORT_SDMA_LS |
1229 AMD_CG_SUPPORT_BIF_LS |
1230 AMD_CG_SUPPORT_VCE_MGCG |
1231 AMD_CG_SUPPORT_UVD_MGCG |
1232 AMD_CG_SUPPORT_HDP_LS |
1233 AMD_CG_SUPPORT_HDP_MGCG;
1234 adev->pg_flags = 0;
1235 //???
1236 adev->external_rev_id = adev->rev_id + 0x14;
1237 break;
1238 case CHIP_OLAND:
1239 adev->cg_flags =
1240 AMD_CG_SUPPORT_GFX_MGCG |
1241 AMD_CG_SUPPORT_GFX_MGLS |
1242 /*AMD_CG_SUPPORT_GFX_CGCG |*/
1243 AMD_CG_SUPPORT_GFX_CGLS |
1244 AMD_CG_SUPPORT_GFX_CGTS |
1245 AMD_CG_SUPPORT_GFX_CP_LS |
1246 AMD_CG_SUPPORT_GFX_RLC_LS |
1247 AMD_CG_SUPPORT_MC_LS |
1248 AMD_CG_SUPPORT_MC_MGCG |
1249 AMD_CG_SUPPORT_SDMA_MGCG |
1250 AMD_CG_SUPPORT_BIF_LS |
1251 AMD_CG_SUPPORT_UVD_MGCG |
1252 AMD_CG_SUPPORT_HDP_LS |
1253 AMD_CG_SUPPORT_HDP_MGCG;
1254 adev->pg_flags = 0;
1255 break;
1256 case CHIP_HAINAN:
1257 adev->cg_flags =
1258 AMD_CG_SUPPORT_GFX_MGCG |
1259 AMD_CG_SUPPORT_GFX_MGLS |
1260 /*AMD_CG_SUPPORT_GFX_CGCG |*/
1261 AMD_CG_SUPPORT_GFX_CGLS |
1262 AMD_CG_SUPPORT_GFX_CGTS |
1263 AMD_CG_SUPPORT_GFX_CP_LS |
1264 AMD_CG_SUPPORT_GFX_RLC_LS |
1265 AMD_CG_SUPPORT_MC_LS |
1266 AMD_CG_SUPPORT_MC_MGCG |
1267 AMD_CG_SUPPORT_SDMA_MGCG |
1268 AMD_CG_SUPPORT_BIF_LS |
1269 AMD_CG_SUPPORT_HDP_LS |
1270 AMD_CG_SUPPORT_HDP_MGCG;
1271 adev->pg_flags = 0;
1272 break;
1273
1274 default:
1275 return -EINVAL;
1276 }
1277
1278 return 0;
1279}
1280
1281static int si_common_sw_init(void *handle)
1282{
1283 return 0;
1284}
1285
1286static int si_common_sw_fini(void *handle)
1287{
1288 return 0;
1289}
1290
1291
1292static void si_init_golden_registers(struct amdgpu_device *adev)
1293{
1294 switch (adev->asic_type) {
1295 case CHIP_TAHITI:
1296 amdgpu_program_register_sequence(adev,
1297 tahiti_golden_registers,
1298 (const u32)ARRAY_SIZE(tahiti_golden_registers));
1299 amdgpu_program_register_sequence(adev,
1300 tahiti_golden_rlc_registers,
1301 (const u32)ARRAY_SIZE(tahiti_golden_rlc_registers));
1302 amdgpu_program_register_sequence(adev,
1303 tahiti_mgcg_cgcg_init,
1304 (const u32)ARRAY_SIZE(tahiti_mgcg_cgcg_init));
1305 amdgpu_program_register_sequence(adev,
1306 tahiti_golden_registers2,
1307 (const u32)ARRAY_SIZE(tahiti_golden_registers2));
1308 break;
1309 case CHIP_PITCAIRN:
1310 amdgpu_program_register_sequence(adev,
1311 pitcairn_golden_registers,
1312 (const u32)ARRAY_SIZE(pitcairn_golden_registers));
1313 amdgpu_program_register_sequence(adev,
1314 pitcairn_golden_rlc_registers,
1315 (const u32)ARRAY_SIZE(pitcairn_golden_rlc_registers));
1316 amdgpu_program_register_sequence(adev,
1317 pitcairn_mgcg_cgcg_init,
1318 (const u32)ARRAY_SIZE(pitcairn_mgcg_cgcg_init));
1319 case CHIP_VERDE:
1320 amdgpu_program_register_sequence(adev,
1321 verde_golden_registers,
1322 (const u32)ARRAY_SIZE(verde_golden_registers));
1323 amdgpu_program_register_sequence(adev,
1324 verde_golden_rlc_registers,
1325 (const u32)ARRAY_SIZE(verde_golden_rlc_registers));
1326 amdgpu_program_register_sequence(adev,
1327 verde_mgcg_cgcg_init,
1328 (const u32)ARRAY_SIZE(verde_mgcg_cgcg_init));
1329 amdgpu_program_register_sequence(adev,
1330 verde_pg_init,
1331 (const u32)ARRAY_SIZE(verde_pg_init));
1332 break;
1333 case CHIP_OLAND:
1334 amdgpu_program_register_sequence(adev,
1335 oland_golden_registers,
1336 (const u32)ARRAY_SIZE(oland_golden_registers));
1337 amdgpu_program_register_sequence(adev,
1338 oland_golden_rlc_registers,
1339 (const u32)ARRAY_SIZE(oland_golden_rlc_registers));
1340 amdgpu_program_register_sequence(adev,
1341 oland_mgcg_cgcg_init,
1342 (const u32)ARRAY_SIZE(oland_mgcg_cgcg_init));
1343 case CHIP_HAINAN:
1344 amdgpu_program_register_sequence(adev,
1345 hainan_golden_registers,
1346 (const u32)ARRAY_SIZE(hainan_golden_registers));
1347 amdgpu_program_register_sequence(adev,
1348 hainan_golden_registers2,
1349 (const u32)ARRAY_SIZE(hainan_golden_registers2));
1350 amdgpu_program_register_sequence(adev,
1351 hainan_mgcg_cgcg_init,
1352 (const u32)ARRAY_SIZE(hainan_mgcg_cgcg_init));
1353 break;
1354
1355
1356 default:
1357 BUG();
1358 }
1359}
1360
62a37553
KW		 1361static void si_pcie_gen3_enable(struct amdgpu_device *adev)
1362{
1363 struct pci_dev *root = adev->pdev->bus->self;
1364 int bridge_pos, gpu_pos;
1365 u32 speed_cntl, mask, current_data_rate;
1366 int ret, i;
1367 u16 tmp16;
1368
1369 if (pci_is_root_bus(adev->pdev->bus))
1370 return;
1371
1372 if (amdgpu_pcie_gen2 == 0)
1373 return;
1374
1375 if (adev->flags & AMD_IS_APU)
1376 return;
1377
1378 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
1379 if (ret != 0)
1380 return;
1381
1382 if (!(mask & (DRM_PCIE_SPEED_50 | DRM_PCIE_SPEED_80)))
1383 return;
1384
36b9a952 1385 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
62a37553
KW		 1386 current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >>
1387 LC_CURRENT_DATA_RATE_SHIFT;
1388 if (mask & DRM_PCIE_SPEED_80) {
1389 if (current_data_rate == 2) {
1390 DRM_INFO("PCIE gen 3 link speeds already enabled\n");
1391 return;
1392 }
1393 DRM_INFO("enabling PCIE gen 3 link speeds, disable with amdgpu.pcie_gen2=0\n");
1394 } else if (mask & DRM_PCIE_SPEED_50) {
1395 if (current_data_rate == 1) {
1396 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
1397 return;
1398 }
1399 DRM_INFO("enabling PCIE gen 2 link speeds, disable with amdgpu.pcie_gen2=0\n");
1400 }
1401
1402 bridge_pos = pci_pcie_cap(root);
1403 if (!bridge_pos)
1404 return;
1405
1406 gpu_pos = pci_pcie_cap(adev->pdev);
1407 if (!gpu_pos)
1408 return;
1409
1410 if (mask & DRM_PCIE_SPEED_80) {
1411 if (current_data_rate != 2) {
1412 u16 bridge_cfg, gpu_cfg;
1413 u16 bridge_cfg2, gpu_cfg2;
1414 u32 max_lw, current_lw, tmp;
1415
1416 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
1417 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
1418
1419 tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;
1420 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
1421
1422 tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;
1423 pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
1424
1425 tmp = RREG32_PCIE(PCIE_LC_STATUS1);
1426 max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT;
1427 current_lw = (tmp & LC_OPERATING_LINK_WIDTH_MASK) >> LC_OPERATING_LINK_WIDTH_SHIFT;
1428
1429 if (current_lw < max_lw) {
36b9a952 1430 tmp = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
62a37553
KW		 1431 if (tmp & LC_RENEGOTIATION_SUPPORT) {
1432 tmp &= ~(LC_LINK_WIDTH_MASK | LC_UPCONFIGURE_DIS);
1433 tmp |= (max_lw << LC_LINK_WIDTH_SHIFT);
1434 tmp |= LC_UPCONFIGURE_SUPPORT | LC_RENEGOTIATE_EN | LC_RECONFIG_NOW;
36b9a952 1435 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, tmp);
62a37553
KW		 1436 }
1437 }
1438
1439 for (i = 0; i < 10; i++) {
1440 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16);
1441 if (tmp16 & PCI_EXP_DEVSTA_TRPND)
1442 break;
1443
1444 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
1445 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
1446
1447 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2);
1448 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2);
1449
36b9a952 1450 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
62a37553 1451 tmp |= LC_SET_QUIESCE;
36b9a952 1452 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
62a37553 1453
36b9a952 1454 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
62a37553 1455 tmp |= LC_REDO_EQ;
36b9a952 1456 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
62a37553
KW		 1457
1458 mdelay(100);
1459
1460 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16);
1461 tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
1462 tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);
1463 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
1464
1465 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16);
1466 tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
1467 tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);
1468 pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
1469
1470 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
1471 tmp16 &= ~((1 << 4) | (7 << 9));
1472 tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9)));
1473 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
1474
1475 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
1476 tmp16 &= ~((1 << 4) | (7 << 9));
1477 tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));
1478 pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
1479
36b9a952 1480 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
62a37553 1481 tmp &= ~LC_SET_QUIESCE;
36b9a952 1482 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
62a37553
KW		 1483 }
1484 }
1485 }
1486
1487 speed_cntl |= LC_FORCE_EN_SW_SPEED_CHANGE | LC_FORCE_DIS_HW_SPEED_CHANGE;
1488 speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE;
36b9a952 1489 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
62a37553
KW		 1490
1491 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
1492 tmp16 &= ~0xf;
1493 if (mask & DRM_PCIE_SPEED_80)
1494 tmp16 |= 3;
1495 else if (mask & DRM_PCIE_SPEED_50)
1496 tmp16 |= 2;
1497 else
1498 tmp16 |= 1;
1499 pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
1500
36b9a952 1501 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
62a37553 1502 speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE;
36b9a952 1503 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
62a37553
KW		 1504
1505 for (i = 0; i < adev->usec_timeout; i++) {
36b9a952 1506 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
62a37553
KW		 1507 if ((speed_cntl & LC_INITIATE_LINK_SPEED_CHANGE) == 0)
1508 break;
1509 udelay(1);
1510 }
1511}
1512
1513static inline u32 si_pif_phy0_rreg(struct amdgpu_device *adev, u32 reg)
1514{
1515 unsigned long flags;
1516 u32 r;
1517
1518 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
1519 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
1520 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
1521 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1522 return r;
1523}
1524
1525static inline void si_pif_phy0_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
1526{
1527 unsigned long flags;
1528
1529 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
1530 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
1531 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
1532 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1533}
1534
1535static inline u32 si_pif_phy1_rreg(struct amdgpu_device *adev, u32 reg)
1536{
1537 unsigned long flags;
1538 u32 r;
1539
1540 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
1541 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
1542 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
1543 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1544 return r;
1545}
1546
1547static inline void si_pif_phy1_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
1548{
1549 unsigned long flags;
1550
1551 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
1552 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
1553 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
1554 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1555}
1556static void si_program_aspm(struct amdgpu_device *adev)
1557{
1558 u32 data, orig;
1559 bool disable_l0s = false, disable_l1 = false, disable_plloff_in_l1 = false;
1560 bool disable_clkreq = false;
1561
1562 if (amdgpu_aspm == 0)
1563 return;
1564
1565 if (adev->flags & AMD_IS_APU)
1566 return;
36b9a952 1567 orig = data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);
62a37553
KW		 1568 data &= ~LC_XMIT_N_FTS_MASK;
1569 data |= LC_XMIT_N_FTS(0x24) | LC_XMIT_N_FTS_OVERRIDE_EN;
1570 if (orig != data)
36b9a952 1571 WREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL, data);
62a37553 1572
36b9a952 1573 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL3);
62a37553
KW		 1574 data |= LC_GO_TO_RECOVERY;
1575 if (orig != data)
36b9a952 1576 WREG32_PCIE_PORT(PCIE_LC_CNTL3, data);
62a37553
KW		 1577
1578 orig = data = RREG32_PCIE(PCIE_P_CNTL);
1579 data |= P_IGNORE_EDB_ERR;
1580 if (orig != data)
1581 WREG32_PCIE(PCIE_P_CNTL, data);
1582
36b9a952 1583 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);
62a37553
KW		 1584 data &= ~(LC_L0S_INACTIVITY_MASK | LC_L1_INACTIVITY_MASK);
1585 data |= LC_PMI_TO_L1_DIS;
1586 if (!disable_l0s)
1587 data |= LC_L0S_INACTIVITY(7);
1588
1589 if (!disable_l1) {
1590 data |= LC_L1_INACTIVITY(7);
1591 data &= ~LC_PMI_TO_L1_DIS;
1592 if (orig != data)
36b9a952 1593 WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
62a37553
KW		 1594
1595 if (!disable_plloff_in_l1) {
1596 bool clk_req_support;
1597
1598 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_0);
1599 data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);
1600 data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);
1601 if (orig != data)
1602 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_0, data);
1603
1604 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_1);
1605 data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);
1606 data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);
1607 if (orig != data)
1608 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_1, data);
1609
1610 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_0);
1611 data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);
1612 data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);
1613 if (orig != data)
1614 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_0, data);
1615
1616 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_1);
1617 data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);
1618 data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);
1619 if (orig != data)
1620 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_1, data);
1621
1622 if ((adev->family != CHIP_OLAND) && (adev->family != CHIP_HAINAN)) {
1623 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_0);
1624 data &= ~PLL_RAMP_UP_TIME_0_MASK;
1625 if (orig != data)
1626 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_0, data);
1627
1628 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_1);
1629 data &= ~PLL_RAMP_UP_TIME_1_MASK;
1630 if (orig != data)
1631 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_1, data);
1632
1633 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_2);
1634 data &= ~PLL_RAMP_UP_TIME_2_MASK;
1635 if (orig != data)
1636 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_2, data);
1637
1638 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_3);
1639 data &= ~PLL_RAMP_UP_TIME_3_MASK;
1640 if (orig != data)
1641 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_3, data);
1642
1643 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_0);
1644 data &= ~PLL_RAMP_UP_TIME_0_MASK;
1645 if (orig != data)
1646 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_0, data);
1647
1648 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_1);
1649 data &= ~PLL_RAMP_UP_TIME_1_MASK;
1650 if (orig != data)
1651 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_1, data);
1652
1653 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_2);
1654 data &= ~PLL_RAMP_UP_TIME_2_MASK;
1655 if (orig != data)
1656 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_2, data);
1657
1658 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_3);
1659 data &= ~PLL_RAMP_UP_TIME_3_MASK;
1660 if (orig != data)
1661 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_3, data);
1662 }
36b9a952 1663 orig = data = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
62a37553
KW		 1664 data &= ~LC_DYN_LANES_PWR_STATE_MASK;
1665 data |= LC_DYN_LANES_PWR_STATE(3);
1666 if (orig != data)
36b9a952 1667 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, data);
62a37553
KW		 1668
1669 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_CNTL);
1670 data &= ~LS2_EXIT_TIME_MASK;
1671 if ((adev->family == CHIP_OLAND) || (adev->family == CHIP_HAINAN))
1672 data |= LS2_EXIT_TIME(5);
1673 if (orig != data)
1674 si_pif_phy0_wreg(adev,PB0_PIF_CNTL, data);
1675
1676 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_CNTL);
1677 data &= ~LS2_EXIT_TIME_MASK;
1678 if ((adev->family == CHIP_OLAND) || (adev->family == CHIP_HAINAN))
1679 data |= LS2_EXIT_TIME(5);
1680 if (orig != data)
1681 si_pif_phy1_wreg(adev,PB1_PIF_CNTL, data);
1682
1683 if (!disable_clkreq &&
1684 !pci_is_root_bus(adev->pdev->bus)) {
1685 struct pci_dev *root = adev->pdev->bus->self;
1686 u32 lnkcap;
1687
1688 clk_req_support = false;
1689 pcie_capability_read_dword(root, PCI_EXP_LNKCAP, &lnkcap);
1690 if (lnkcap & PCI_EXP_LNKCAP_CLKPM)
1691 clk_req_support = true;
1692 } else {
1693 clk_req_support = false;
1694 }
1695
1696 if (clk_req_support) {
36b9a952 1697 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL2);
62a37553
KW		 1698 data |= LC_ALLOW_PDWN_IN_L1 | LC_ALLOW_PDWN_IN_L23;
1699 if (orig != data)
36b9a952 1700 WREG32_PCIE_PORT(PCIE_LC_CNTL2, data);
62a37553
KW		 1701
1702 orig = data = RREG32(THM_CLK_CNTL);
1703 data &= ~(CMON_CLK_SEL_MASK | TMON_CLK_SEL_MASK);
1704 data |= CMON_CLK_SEL(1) | TMON_CLK_SEL(1);
1705 if (orig != data)
1706 WREG32(THM_CLK_CNTL, data);
1707
1708 orig = data = RREG32(MISC_CLK_CNTL);
1709 data &= ~(DEEP_SLEEP_CLK_SEL_MASK | ZCLK_SEL_MASK);
1710 data |= DEEP_SLEEP_CLK_SEL(1) | ZCLK_SEL(1);
1711 if (orig != data)
1712 WREG32(MISC_CLK_CNTL, data);
1713
1714 orig = data = RREG32(CG_CLKPIN_CNTL);
1715 data &= ~BCLK_AS_XCLK;
1716 if (orig != data)
1717 WREG32(CG_CLKPIN_CNTL, data);
1718
1719 orig = data = RREG32(CG_CLKPIN_CNTL_2);
1720 data &= ~FORCE_BIF_REFCLK_EN;
1721 if (orig != data)
1722 WREG32(CG_CLKPIN_CNTL_2, data);
1723
1724 orig = data = RREG32(MPLL_BYPASSCLK_SEL);
1725 data &= ~MPLL_CLKOUT_SEL_MASK;
1726 data |= MPLL_CLKOUT_SEL(4);
1727 if (orig != data)
1728 WREG32(MPLL_BYPASSCLK_SEL, data);
1729
1730 orig = data = RREG32(SPLL_CNTL_MODE);
1731 data &= ~SPLL_REFCLK_SEL_MASK;
1732 if (orig != data)
1733 WREG32(SPLL_CNTL_MODE, data);
1734 }
1735 }
1736 } else {
1737 if (orig != data)
36b9a952 1738 WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
62a37553
KW		 1739 }
1740
1741 orig = data = RREG32_PCIE(PCIE_CNTL2);
1742 data |= SLV_MEM_LS_EN | MST_MEM_LS_EN | REPLAY_MEM_LS_EN;
1743 if (orig != data)
1744 WREG32_PCIE(PCIE_CNTL2, data);
1745
1746 if (!disable_l0s) {
36b9a952 1747 data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);
62a37553
KW		 1748 if((data & LC_N_FTS_MASK) == LC_N_FTS_MASK) {
1749 data = RREG32_PCIE(PCIE_LC_STATUS1);
1750 if ((data & LC_REVERSE_XMIT) && (data & LC_REVERSE_RCVR)) {
36b9a952 1751 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);
62a37553
KW		 1752 data &= ~LC_L0S_INACTIVITY_MASK;
1753 if (orig != data)
36b9a952 1754 WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
62a37553
KW		 1755 }
1756 }
1757 }
1758}
1759
1760static void si_fix_pci_max_read_req_size(struct amdgpu_device *adev)
1761{
1762 int readrq;
1763 u16 v;
1764
1765 readrq = pcie_get_readrq(adev->pdev);
1766 v = ffs(readrq) - 8;
1767 if ((v == 0) || (v == 6) || (v == 7))
1768 pcie_set_readrq(adev->pdev, 512);
1769}
1770
1771static int si_common_hw_init(void *handle)
1772{
1773 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1774
1775 si_fix_pci_max_read_req_size(adev);
1776 si_init_golden_registers(adev);
1777 si_pcie_gen3_enable(adev);
1778 si_program_aspm(adev);
1779
1780 return 0;
1781}
1782
1783static int si_common_hw_fini(void *handle)
1784{
1785 return 0;
1786}
1787
1788static int si_common_suspend(void *handle)
1789{
1790 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1791
1792 return si_common_hw_fini(adev);
1793}
1794
1795static int si_common_resume(void *handle)
1796{
1797 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1798
1799 return si_common_hw_init(adev);
1800}
1801
1802static bool si_common_is_idle(void *handle)
1803{
1804 return true;
1805}
1806
1807static int si_common_wait_for_idle(void *handle)
1808{
1809 return 0;
1810}
1811
1812static int si_common_soft_reset(void *handle)
1813{
1814 return 0;
1815}
1816
1817static int si_common_set_clockgating_state(void *handle,
1818 enum amd_clockgating_state state)
1819{
1820 return 0;
1821}
1822
1823static int si_common_set_powergating_state(void *handle,
1824 enum amd_powergating_state state)
1825{
1826 return 0;
1827}
1828
a1255107 1829static const struct amd_ip_funcs si_common_ip_funcs = {
62a37553
KW		 1830 .name = "si_common",
1831 .early_init = si_common_early_init,
1832 .late_init = NULL,
1833 .sw_init = si_common_sw_init,
1834 .sw_fini = si_common_sw_fini,
1835 .hw_init = si_common_hw_init,
1836 .hw_fini = si_common_hw_fini,
1837 .suspend = si_common_suspend,
1838 .resume = si_common_resume,
1839 .is_idle = si_common_is_idle,
1840 .wait_for_idle = si_common_wait_for_idle,
1841 .soft_reset = si_common_soft_reset,
1842 .set_clockgating_state = si_common_set_clockgating_state,
1843 .set_powergating_state = si_common_set_powergating_state,
1844};
1845
a1255107 1846static const struct amdgpu_ip_block_version si_common_ip_block =
62a37553 1847{
a1255107
AD		 1848 .type = AMD_IP_BLOCK_TYPE_COMMON,
1849 .major = 1,
1850 .minor = 0,
1851 .rev = 0,
1852 .funcs = &si_common_ip_funcs,
2120df47
AD		 1853};
1854
62a37553
KW		 1855int si_set_ip_blocks(struct amdgpu_device *adev)
1856{
1857 switch (adev->asic_type) {
1858 case CHIP_VERDE:
1859 case CHIP_TAHITI:
1860 case CHIP_PITCAIRN:
a1255107
AD		 1861 amdgpu_ip_block_add(adev, &si_common_ip_block);
1862 amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block);
1863 amdgpu_ip_block_add(adev, &si_ih_ip_block);
1864 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1865 if (adev->enable_virtual_display)
1866 amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1867 else
1868 amdgpu_ip_block_add(adev, &dce_v6_0_ip_block);
1869 amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block);
1870 amdgpu_ip_block_add(adev, &si_dma_ip_block);
1871 /* amdgpu_ip_block_add(adev, &uvd_v3_1_ip_block); */
1872 /* amdgpu_ip_block_add(adev, &vce_v1_0_ip_block); */
1873 break;
62a37553 1874 case CHIP_OLAND:
a1255107
AD		 1875 amdgpu_ip_block_add(adev, &si_common_ip_block);
1876 amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block);
1877 amdgpu_ip_block_add(adev, &si_ih_ip_block);
1878 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1879 if (adev->enable_virtual_display)
1880 amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1881 else
1882 amdgpu_ip_block_add(adev, &dce_v6_4_ip_block);
1883 amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block);
1884 amdgpu_ip_block_add(adev, &si_dma_ip_block);
1885 /* amdgpu_ip_block_add(adev, &uvd_v3_1_ip_block); */
1886 /* amdgpu_ip_block_add(adev, &vce_v1_0_ip_block); */
62a37553
KW		 1887 break;
1888 case CHIP_HAINAN:
a1255107
AD		 1889 amdgpu_ip_block_add(adev, &si_common_ip_block);
1890 amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block);
1891 amdgpu_ip_block_add(adev, &si_ih_ip_block);
1892 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1893 if (adev->enable_virtual_display)
1894 amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1895 amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block);
1896 amdgpu_ip_block_add(adev, &si_dma_ip_block);
62a37553
KW		 1897 break;
1898 default:
1899 BUG();
1900 }
1901 return 0;
1902}
1903
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