]>
Commit | Line | Data |
---|---|---|
30d1574f KW |
1 | /* |
2 | * Copyright 2015 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Alex Deucher | |
23 | */ | |
24 | #include <drm/drmP.h> | |
25 | #include "amdgpu.h" | |
26 | #include "amdgpu_trace.h" | |
4fef88bd | 27 | #include "si.h" |
689957b1 | 28 | #include "sid.h" |
30d1574f KW |
29 | |
30 | const u32 sdma_offsets[SDMA_MAX_INSTANCE] = | |
31 | { | |
32 | DMA0_REGISTER_OFFSET, | |
33 | DMA1_REGISTER_OFFSET | |
34 | }; | |
35 | ||
36 | static void si_dma_set_ring_funcs(struct amdgpu_device *adev); | |
37 | static void si_dma_set_buffer_funcs(struct amdgpu_device *adev); | |
38 | static void si_dma_set_vm_pte_funcs(struct amdgpu_device *adev); | |
39 | static void si_dma_set_irq_funcs(struct amdgpu_device *adev); | |
40 | ||
536fbf94 | 41 | static uint64_t si_dma_ring_get_rptr(struct amdgpu_ring *ring) |
30d1574f | 42 | { |
cb5df31b | 43 | return ring->adev->wb.wb[ring->rptr_offs>>2]; |
30d1574f KW |
44 | } |
45 | ||
536fbf94 | 46 | static uint64_t si_dma_ring_get_wptr(struct amdgpu_ring *ring) |
30d1574f | 47 | { |
30d1574f KW |
48 | struct amdgpu_device *adev = ring->adev; |
49 | u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1; | |
50 | ||
51 | return (RREG32(DMA_RB_WPTR + sdma_offsets[me]) & 0x3fffc) >> 2; | |
52 | } | |
53 | ||
54 | static void si_dma_ring_set_wptr(struct amdgpu_ring *ring) | |
55 | { | |
56 | struct amdgpu_device *adev = ring->adev; | |
57 | u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1; | |
58 | ||
536fbf94 KW |
59 | WREG32(DMA_RB_WPTR + sdma_offsets[me], |
60 | (lower_32_bits(ring->wptr) << 2) & 0x3fffc); | |
30d1574f KW |
61 | } |
62 | ||
63 | static void si_dma_ring_emit_ib(struct amdgpu_ring *ring, | |
64 | struct amdgpu_ib *ib, | |
c4f46f22 | 65 | unsigned vmid, bool ctx_switch) |
30d1574f KW |
66 | { |
67 | /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring. | |
68 | * Pad as necessary with NOPs. | |
69 | */ | |
536fbf94 | 70 | while ((lower_32_bits(ring->wptr) & 7) != 5) |
30d1574f | 71 | amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0)); |
c4f46f22 | 72 | amdgpu_ring_write(ring, DMA_IB_PACKET(DMA_PACKET_INDIRECT_BUFFER, vmid, 0)); |
30d1574f KW |
73 | amdgpu_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); |
74 | amdgpu_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); | |
75 | ||
76 | } | |
77 | ||
30d1574f KW |
78 | /** |
79 | * si_dma_ring_emit_fence - emit a fence on the DMA ring | |
80 | * | |
81 | * @ring: amdgpu ring pointer | |
82 | * @fence: amdgpu fence object | |
83 | * | |
84 | * Add a DMA fence packet to the ring to write | |
85 | * the fence seq number and DMA trap packet to generate | |
86 | * an interrupt if needed (VI). | |
87 | */ | |
88 | static void si_dma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, | |
89 | unsigned flags) | |
90 | { | |
91 | ||
92 | bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; | |
93 | /* write the fence */ | |
94 | amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0, 0)); | |
95 | amdgpu_ring_write(ring, addr & 0xfffffffc); | |
96 | amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xff)); | |
97 | amdgpu_ring_write(ring, seq); | |
98 | /* optionally write high bits as well */ | |
99 | if (write64bit) { | |
100 | addr += 4; | |
101 | amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0, 0)); | |
102 | amdgpu_ring_write(ring, addr & 0xfffffffc); | |
103 | amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xff)); | |
104 | amdgpu_ring_write(ring, upper_32_bits(seq)); | |
105 | } | |
106 | /* generate an interrupt */ | |
107 | amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0, 0)); | |
108 | } | |
109 | ||
110 | static void si_dma_stop(struct amdgpu_device *adev) | |
111 | { | |
112 | struct amdgpu_ring *ring; | |
113 | u32 rb_cntl; | |
114 | unsigned i; | |
115 | ||
116 | for (i = 0; i < adev->sdma.num_instances; i++) { | |
117 | ring = &adev->sdma.instance[i].ring; | |
118 | /* dma0 */ | |
119 | rb_cntl = RREG32(DMA_RB_CNTL + sdma_offsets[i]); | |
120 | rb_cntl &= ~DMA_RB_ENABLE; | |
121 | WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl); | |
122 | ||
e7b54945 | 123 | if (adev->mman.buffer_funcs_ring == ring) |
770d13b1 | 124 | amdgpu_ttm_set_active_vram_size(adev, adev->gmc.visible_vram_size); |
30d1574f KW |
125 | ring->ready = false; |
126 | } | |
127 | } | |
128 | ||
129 | static int si_dma_start(struct amdgpu_device *adev) | |
130 | { | |
131 | struct amdgpu_ring *ring; | |
132 | u32 rb_cntl, dma_cntl, ib_cntl, rb_bufsz; | |
133 | int i, r; | |
134 | uint64_t rptr_addr; | |
135 | ||
136 | for (i = 0; i < adev->sdma.num_instances; i++) { | |
137 | ring = &adev->sdma.instance[i].ring; | |
138 | ||
139 | WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0); | |
140 | WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); | |
141 | ||
142 | /* Set ring buffer size in dwords */ | |
143 | rb_bufsz = order_base_2(ring->ring_size / 4); | |
144 | rb_cntl = rb_bufsz << 1; | |
145 | #ifdef __BIG_ENDIAN | |
146 | rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE; | |
147 | #endif | |
148 | WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl); | |
149 | ||
150 | /* Initialize the ring buffer's read and write pointers */ | |
151 | WREG32(DMA_RB_RPTR + sdma_offsets[i], 0); | |
152 | WREG32(DMA_RB_WPTR + sdma_offsets[i], 0); | |
153 | ||
154 | rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); | |
155 | ||
156 | WREG32(DMA_RB_RPTR_ADDR_LO + sdma_offsets[i], lower_32_bits(rptr_addr)); | |
157 | WREG32(DMA_RB_RPTR_ADDR_HI + sdma_offsets[i], upper_32_bits(rptr_addr) & 0xFF); | |
158 | ||
159 | rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE; | |
160 | ||
161 | WREG32(DMA_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); | |
162 | ||
163 | /* enable DMA IBs */ | |
164 | ib_cntl = DMA_IB_ENABLE | CMD_VMID_FORCE; | |
165 | #ifdef __BIG_ENDIAN | |
166 | ib_cntl |= DMA_IB_SWAP_ENABLE; | |
167 | #endif | |
168 | WREG32(DMA_IB_CNTL + sdma_offsets[i], ib_cntl); | |
169 | ||
170 | dma_cntl = RREG32(DMA_CNTL + sdma_offsets[i]); | |
171 | dma_cntl &= ~CTXEMPTY_INT_ENABLE; | |
172 | WREG32(DMA_CNTL + sdma_offsets[i], dma_cntl); | |
173 | ||
174 | ring->wptr = 0; | |
536fbf94 | 175 | WREG32(DMA_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2); |
30d1574f KW |
176 | WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl | DMA_RB_ENABLE); |
177 | ||
178 | ring->ready = true; | |
179 | ||
180 | r = amdgpu_ring_test_ring(ring); | |
181 | if (r) { | |
182 | ring->ready = false; | |
183 | return r; | |
184 | } | |
e7b54945 MD |
185 | |
186 | if (adev->mman.buffer_funcs_ring == ring) | |
770d13b1 | 187 | amdgpu_ttm_set_active_vram_size(adev, adev->gmc.real_vram_size); |
30d1574f KW |
188 | } |
189 | ||
190 | return 0; | |
191 | } | |
192 | ||
193 | /** | |
194 | * si_dma_ring_test_ring - simple async dma engine test | |
195 | * | |
196 | * @ring: amdgpu_ring structure holding ring information | |
197 | * | |
198 | * Test the DMA engine by writing using it to write an | |
199 | * value to memory. (VI). | |
200 | * Returns 0 for success, error for failure. | |
201 | */ | |
202 | static int si_dma_ring_test_ring(struct amdgpu_ring *ring) | |
203 | { | |
204 | struct amdgpu_device *adev = ring->adev; | |
205 | unsigned i; | |
206 | unsigned index; | |
207 | int r; | |
208 | u32 tmp; | |
209 | u64 gpu_addr; | |
210 | ||
131b4b36 | 211 | r = amdgpu_device_wb_get(adev, &index); |
30d1574f KW |
212 | if (r) { |
213 | dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); | |
214 | return r; | |
215 | } | |
216 | ||
217 | gpu_addr = adev->wb.gpu_addr + (index * 4); | |
218 | tmp = 0xCAFEDEAD; | |
219 | adev->wb.wb[index] = cpu_to_le32(tmp); | |
220 | ||
221 | r = amdgpu_ring_alloc(ring, 4); | |
222 | if (r) { | |
223 | DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); | |
131b4b36 | 224 | amdgpu_device_wb_free(adev, index); |
30d1574f KW |
225 | return r; |
226 | } | |
227 | ||
228 | amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 0, 1)); | |
229 | amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); | |
230 | amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xff); | |
231 | amdgpu_ring_write(ring, 0xDEADBEEF); | |
232 | amdgpu_ring_commit(ring); | |
233 | ||
234 | for (i = 0; i < adev->usec_timeout; i++) { | |
235 | tmp = le32_to_cpu(adev->wb.wb[index]); | |
236 | if (tmp == 0xDEADBEEF) | |
237 | break; | |
238 | DRM_UDELAY(1); | |
239 | } | |
240 | ||
241 | if (i < adev->usec_timeout) { | |
9953b72f | 242 | DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); |
30d1574f KW |
243 | } else { |
244 | DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", | |
245 | ring->idx, tmp); | |
246 | r = -EINVAL; | |
247 | } | |
131b4b36 | 248 | amdgpu_device_wb_free(adev, index); |
30d1574f KW |
249 | |
250 | return r; | |
251 | } | |
252 | ||
253 | /** | |
254 | * si_dma_ring_test_ib - test an IB on the DMA engine | |
255 | * | |
256 | * @ring: amdgpu_ring structure holding ring information | |
257 | * | |
258 | * Test a simple IB in the DMA ring (VI). | |
259 | * Returns 0 on success, error on failure. | |
260 | */ | |
261 | static int si_dma_ring_test_ib(struct amdgpu_ring *ring, long timeout) | |
262 | { | |
263 | struct amdgpu_device *adev = ring->adev; | |
264 | struct amdgpu_ib ib; | |
f54d1867 | 265 | struct dma_fence *f = NULL; |
30d1574f KW |
266 | unsigned index; |
267 | u32 tmp = 0; | |
268 | u64 gpu_addr; | |
269 | long r; | |
270 | ||
131b4b36 | 271 | r = amdgpu_device_wb_get(adev, &index); |
30d1574f KW |
272 | if (r) { |
273 | dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); | |
274 | return r; | |
275 | } | |
276 | ||
277 | gpu_addr = adev->wb.gpu_addr + (index * 4); | |
278 | tmp = 0xCAFEDEAD; | |
279 | adev->wb.wb[index] = cpu_to_le32(tmp); | |
280 | memset(&ib, 0, sizeof(ib)); | |
281 | r = amdgpu_ib_get(adev, NULL, 256, &ib); | |
282 | if (r) { | |
283 | DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); | |
284 | goto err0; | |
285 | } | |
286 | ||
287 | ib.ptr[0] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 0, 1); | |
288 | ib.ptr[1] = lower_32_bits(gpu_addr); | |
289 | ib.ptr[2] = upper_32_bits(gpu_addr) & 0xff; | |
290 | ib.ptr[3] = 0xDEADBEEF; | |
291 | ib.length_dw = 4; | |
50ddc75e | 292 | r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); |
30d1574f KW |
293 | if (r) |
294 | goto err1; | |
295 | ||
f54d1867 | 296 | r = dma_fence_wait_timeout(f, false, timeout); |
30d1574f KW |
297 | if (r == 0) { |
298 | DRM_ERROR("amdgpu: IB test timed out\n"); | |
299 | r = -ETIMEDOUT; | |
300 | goto err1; | |
301 | } else if (r < 0) { | |
302 | DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); | |
303 | goto err1; | |
304 | } | |
305 | tmp = le32_to_cpu(adev->wb.wb[index]); | |
306 | if (tmp == 0xDEADBEEF) { | |
9953b72f | 307 | DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); |
30d1574f KW |
308 | r = 0; |
309 | } else { | |
310 | DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); | |
311 | r = -EINVAL; | |
312 | } | |
313 | ||
314 | err1: | |
315 | amdgpu_ib_free(adev, &ib, NULL); | |
f54d1867 | 316 | dma_fence_put(f); |
30d1574f | 317 | err0: |
131b4b36 | 318 | amdgpu_device_wb_free(adev, index); |
30d1574f KW |
319 | return r; |
320 | } | |
321 | ||
322 | /** | |
323 | * cik_dma_vm_copy_pte - update PTEs by copying them from the GART | |
324 | * | |
325 | * @ib: indirect buffer to fill with commands | |
326 | * @pe: addr of the page entry | |
327 | * @src: src addr to copy from | |
328 | * @count: number of page entries to update | |
329 | * | |
330 | * Update PTEs by copying them from the GART using DMA (SI). | |
331 | */ | |
332 | static void si_dma_vm_copy_pte(struct amdgpu_ib *ib, | |
333 | uint64_t pe, uint64_t src, | |
334 | unsigned count) | |
335 | { | |
336 | unsigned bytes = count * 8; | |
337 | ||
338 | ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_COPY, | |
339 | 1, 0, 0, bytes); | |
340 | ib->ptr[ib->length_dw++] = lower_32_bits(pe); | |
341 | ib->ptr[ib->length_dw++] = lower_32_bits(src); | |
342 | ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; | |
343 | ib->ptr[ib->length_dw++] = upper_32_bits(src) & 0xff; | |
344 | } | |
345 | ||
346 | /** | |
347 | * si_dma_vm_write_pte - update PTEs by writing them manually | |
348 | * | |
349 | * @ib: indirect buffer to fill with commands | |
350 | * @pe: addr of the page entry | |
351 | * @value: dst addr to write into pe | |
352 | * @count: number of page entries to update | |
353 | * @incr: increase next addr by incr bytes | |
354 | * | |
355 | * Update PTEs by writing them manually using DMA (SI). | |
356 | */ | |
357 | static void si_dma_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, | |
358 | uint64_t value, unsigned count, | |
359 | uint32_t incr) | |
360 | { | |
361 | unsigned ndw = count * 2; | |
362 | ||
363 | ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 0, ndw); | |
364 | ib->ptr[ib->length_dw++] = lower_32_bits(pe); | |
365 | ib->ptr[ib->length_dw++] = upper_32_bits(pe); | |
366 | for (; ndw > 0; ndw -= 2) { | |
367 | ib->ptr[ib->length_dw++] = lower_32_bits(value); | |
368 | ib->ptr[ib->length_dw++] = upper_32_bits(value); | |
369 | value += incr; | |
370 | } | |
371 | } | |
372 | ||
373 | /** | |
374 | * si_dma_vm_set_pte_pde - update the page tables using sDMA | |
375 | * | |
376 | * @ib: indirect buffer to fill with commands | |
377 | * @pe: addr of the page entry | |
378 | * @addr: dst addr to write into pe | |
379 | * @count: number of page entries to update | |
380 | * @incr: increase next addr by incr bytes | |
381 | * @flags: access flags | |
382 | * | |
383 | * Update the page tables using sDMA (CIK). | |
384 | */ | |
385 | static void si_dma_vm_set_pte_pde(struct amdgpu_ib *ib, | |
386 | uint64_t pe, | |
387 | uint64_t addr, unsigned count, | |
6b777607 | 388 | uint32_t incr, uint64_t flags) |
30d1574f KW |
389 | { |
390 | uint64_t value; | |
391 | unsigned ndw; | |
392 | ||
393 | while (count) { | |
394 | ndw = count * 2; | |
395 | if (ndw > 0xFFFFE) | |
396 | ndw = 0xFFFFE; | |
397 | ||
398 | if (flags & AMDGPU_PTE_VALID) | |
399 | value = addr; | |
400 | else | |
401 | value = 0; | |
402 | ||
403 | /* for physically contiguous pages (vram) */ | |
404 | ib->ptr[ib->length_dw++] = DMA_PTE_PDE_PACKET(ndw); | |
405 | ib->ptr[ib->length_dw++] = pe; /* dst addr */ | |
406 | ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; | |
b9be700e JZ |
407 | ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ |
408 | ib->ptr[ib->length_dw++] = upper_32_bits(flags); | |
30d1574f KW |
409 | ib->ptr[ib->length_dw++] = value; /* value */ |
410 | ib->ptr[ib->length_dw++] = upper_32_bits(value); | |
411 | ib->ptr[ib->length_dw++] = incr; /* increment size */ | |
412 | ib->ptr[ib->length_dw++] = 0; | |
413 | pe += ndw * 4; | |
414 | addr += (ndw / 2) * incr; | |
415 | count -= ndw / 2; | |
416 | } | |
417 | } | |
418 | ||
419 | /** | |
420 | * si_dma_pad_ib - pad the IB to the required number of dw | |
421 | * | |
422 | * @ib: indirect buffer to fill with padding | |
423 | * | |
424 | */ | |
425 | static void si_dma_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) | |
426 | { | |
427 | while (ib->length_dw & 0x7) | |
428 | ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0); | |
429 | } | |
430 | ||
431 | /** | |
432 | * cik_sdma_ring_emit_pipeline_sync - sync the pipeline | |
433 | * | |
434 | * @ring: amdgpu_ring pointer | |
435 | * | |
436 | * Make sure all previous operations are completed (CIK). | |
437 | */ | |
438 | static void si_dma_ring_emit_pipeline_sync(struct amdgpu_ring *ring) | |
439 | { | |
440 | uint32_t seq = ring->fence_drv.sync_seq; | |
441 | uint64_t addr = ring->fence_drv.gpu_addr; | |
442 | ||
443 | /* wait for idle */ | |
444 | amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_POLL_REG_MEM, 0, 0, 0, 0) | | |
445 | (1 << 27)); /* Poll memory */ | |
446 | amdgpu_ring_write(ring, lower_32_bits(addr)); | |
447 | amdgpu_ring_write(ring, (0xff << 16) | upper_32_bits(addr)); /* retry, addr_hi */ | |
448 | amdgpu_ring_write(ring, 0xffffffff); /* mask */ | |
449 | amdgpu_ring_write(ring, seq); /* value */ | |
450 | amdgpu_ring_write(ring, (3 << 28) | 0x20); /* func(equal) | poll interval */ | |
451 | } | |
452 | ||
453 | /** | |
454 | * si_dma_ring_emit_vm_flush - cik vm flush using sDMA | |
455 | * | |
456 | * @ring: amdgpu_ring pointer | |
457 | * @vm: amdgpu_vm pointer | |
458 | * | |
459 | * Update the page table base and flush the VM TLB | |
460 | * using sDMA (VI). | |
461 | */ | |
462 | static void si_dma_ring_emit_vm_flush(struct amdgpu_ring *ring, | |
5a4633c4 CK |
463 | unsigned vmid, unsigned pasid, |
464 | uint64_t pd_addr) | |
30d1574f | 465 | { |
4fef88bd | 466 | amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pasid, pd_addr); |
30d1574f KW |
467 | |
468 | /* wait for invalidate to complete */ | |
469 | amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_POLL_REG_MEM, 0, 0, 0, 0)); | |
470 | amdgpu_ring_write(ring, VM_INVALIDATE_REQUEST); | |
471 | amdgpu_ring_write(ring, 0xff << 16); /* retry */ | |
c4f46f22 | 472 | amdgpu_ring_write(ring, 1 << vmid); /* mask */ |
30d1574f KW |
473 | amdgpu_ring_write(ring, 0); /* value */ |
474 | amdgpu_ring_write(ring, (0 << 28) | 0x20); /* func(always) | poll interval */ | |
475 | } | |
476 | ||
5b9263d9 CK |
477 | static void si_dma_ring_emit_wreg(struct amdgpu_ring *ring, |
478 | uint32_t reg, uint32_t val) | |
479 | { | |
480 | amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0)); | |
481 | amdgpu_ring_write(ring, (0xf << 16) | reg); | |
482 | amdgpu_ring_write(ring, val); | |
483 | } | |
484 | ||
30d1574f KW |
485 | static int si_dma_early_init(void *handle) |
486 | { | |
487 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
488 | ||
489 | adev->sdma.num_instances = 2; | |
490 | ||
491 | si_dma_set_ring_funcs(adev); | |
492 | si_dma_set_buffer_funcs(adev); | |
493 | si_dma_set_vm_pte_funcs(adev); | |
494 | si_dma_set_irq_funcs(adev); | |
495 | ||
496 | return 0; | |
497 | } | |
498 | ||
499 | static int si_dma_sw_init(void *handle) | |
500 | { | |
501 | struct amdgpu_ring *ring; | |
502 | int r, i; | |
503 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
504 | ||
505 | /* DMA0 trap event */ | |
d766e6a3 | 506 | r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 224, &adev->sdma.trap_irq); |
30d1574f KW |
507 | if (r) |
508 | return r; | |
509 | ||
510 | /* DMA1 trap event */ | |
d766e6a3 | 511 | r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 244, &adev->sdma.trap_irq_1); |
30d1574f KW |
512 | if (r) |
513 | return r; | |
514 | ||
515 | for (i = 0; i < adev->sdma.num_instances; i++) { | |
516 | ring = &adev->sdma.instance[i].ring; | |
517 | ring->ring_obj = NULL; | |
518 | ring->use_doorbell = false; | |
519 | sprintf(ring->name, "sdma%d", i); | |
520 | r = amdgpu_ring_init(adev, ring, 1024, | |
30d1574f KW |
521 | &adev->sdma.trap_irq, |
522 | (i == 0) ? | |
21cd942e CK |
523 | AMDGPU_SDMA_IRQ_TRAP0 : |
524 | AMDGPU_SDMA_IRQ_TRAP1); | |
30d1574f KW |
525 | if (r) |
526 | return r; | |
527 | } | |
528 | ||
529 | return r; | |
530 | } | |
531 | ||
532 | static int si_dma_sw_fini(void *handle) | |
533 | { | |
534 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
535 | int i; | |
536 | ||
537 | for (i = 0; i < adev->sdma.num_instances; i++) | |
538 | amdgpu_ring_fini(&adev->sdma.instance[i].ring); | |
539 | ||
540 | return 0; | |
541 | } | |
542 | ||
543 | static int si_dma_hw_init(void *handle) | |
544 | { | |
30d1574f KW |
545 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
546 | ||
cb5df31b | 547 | return si_dma_start(adev); |
30d1574f KW |
548 | } |
549 | ||
550 | static int si_dma_hw_fini(void *handle) | |
551 | { | |
552 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
553 | ||
554 | si_dma_stop(adev); | |
555 | ||
556 | return 0; | |
557 | } | |
558 | ||
559 | static int si_dma_suspend(void *handle) | |
560 | { | |
561 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
562 | ||
563 | return si_dma_hw_fini(adev); | |
564 | } | |
565 | ||
566 | static int si_dma_resume(void *handle) | |
567 | { | |
568 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
569 | ||
570 | return si_dma_hw_init(adev); | |
571 | } | |
572 | ||
573 | static bool si_dma_is_idle(void *handle) | |
574 | { | |
575 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
576 | u32 tmp = RREG32(SRBM_STATUS2); | |
577 | ||
578 | if (tmp & (DMA_BUSY_MASK | DMA1_BUSY_MASK)) | |
579 | return false; | |
580 | ||
581 | return true; | |
582 | } | |
583 | ||
584 | static int si_dma_wait_for_idle(void *handle) | |
585 | { | |
586 | unsigned i; | |
30d1574f KW |
587 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
588 | ||
589 | for (i = 0; i < adev->usec_timeout; i++) { | |
cb5df31b | 590 | if (si_dma_is_idle(handle)) |
30d1574f KW |
591 | return 0; |
592 | udelay(1); | |
593 | } | |
594 | return -ETIMEDOUT; | |
595 | } | |
596 | ||
597 | static int si_dma_soft_reset(void *handle) | |
598 | { | |
599 | DRM_INFO("si_dma_soft_reset --- not implemented !!!!!!!\n"); | |
600 | return 0; | |
601 | } | |
602 | ||
603 | static int si_dma_set_trap_irq_state(struct amdgpu_device *adev, | |
604 | struct amdgpu_irq_src *src, | |
605 | unsigned type, | |
606 | enum amdgpu_interrupt_state state) | |
607 | { | |
608 | u32 sdma_cntl; | |
609 | ||
610 | switch (type) { | |
611 | case AMDGPU_SDMA_IRQ_TRAP0: | |
612 | switch (state) { | |
613 | case AMDGPU_IRQ_STATE_DISABLE: | |
614 | sdma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET); | |
615 | sdma_cntl &= ~TRAP_ENABLE; | |
616 | WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl); | |
617 | break; | |
618 | case AMDGPU_IRQ_STATE_ENABLE: | |
619 | sdma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET); | |
620 | sdma_cntl |= TRAP_ENABLE; | |
621 | WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl); | |
622 | break; | |
623 | default: | |
624 | break; | |
625 | } | |
626 | break; | |
627 | case AMDGPU_SDMA_IRQ_TRAP1: | |
628 | switch (state) { | |
629 | case AMDGPU_IRQ_STATE_DISABLE: | |
630 | sdma_cntl = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET); | |
631 | sdma_cntl &= ~TRAP_ENABLE; | |
632 | WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, sdma_cntl); | |
633 | break; | |
634 | case AMDGPU_IRQ_STATE_ENABLE: | |
635 | sdma_cntl = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET); | |
636 | sdma_cntl |= TRAP_ENABLE; | |
637 | WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, sdma_cntl); | |
638 | break; | |
639 | default: | |
640 | break; | |
641 | } | |
642 | break; | |
643 | default: | |
644 | break; | |
645 | } | |
646 | return 0; | |
647 | } | |
648 | ||
649 | static int si_dma_process_trap_irq(struct amdgpu_device *adev, | |
650 | struct amdgpu_irq_src *source, | |
651 | struct amdgpu_iv_entry *entry) | |
652 | { | |
30d1574f KW |
653 | amdgpu_fence_process(&adev->sdma.instance[0].ring); |
654 | ||
655 | return 0; | |
656 | } | |
657 | ||
658 | static int si_dma_process_trap_irq_1(struct amdgpu_device *adev, | |
659 | struct amdgpu_irq_src *source, | |
660 | struct amdgpu_iv_entry *entry) | |
661 | { | |
30d1574f KW |
662 | amdgpu_fence_process(&adev->sdma.instance[1].ring); |
663 | ||
664 | return 0; | |
665 | } | |
666 | ||
667 | static int si_dma_process_illegal_inst_irq(struct amdgpu_device *adev, | |
668 | struct amdgpu_irq_src *source, | |
669 | struct amdgpu_iv_entry *entry) | |
670 | { | |
671 | DRM_ERROR("Illegal instruction in SDMA command stream\n"); | |
672 | schedule_work(&adev->reset_work); | |
673 | return 0; | |
674 | } | |
675 | ||
676 | static int si_dma_set_clockgating_state(void *handle, | |
677 | enum amd_clockgating_state state) | |
678 | { | |
679 | u32 orig, data, offset; | |
680 | int i; | |
681 | bool enable; | |
682 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
683 | ||
684 | enable = (state == AMD_CG_STATE_GATE) ? true : false; | |
685 | ||
686 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { | |
687 | for (i = 0; i < adev->sdma.num_instances; i++) { | |
688 | if (i == 0) | |
689 | offset = DMA0_REGISTER_OFFSET; | |
690 | else | |
691 | offset = DMA1_REGISTER_OFFSET; | |
692 | orig = data = RREG32(DMA_POWER_CNTL + offset); | |
693 | data &= ~MEM_POWER_OVERRIDE; | |
694 | if (data != orig) | |
695 | WREG32(DMA_POWER_CNTL + offset, data); | |
696 | WREG32(DMA_CLK_CTRL + offset, 0x00000100); | |
697 | } | |
698 | } else { | |
699 | for (i = 0; i < adev->sdma.num_instances; i++) { | |
700 | if (i == 0) | |
701 | offset = DMA0_REGISTER_OFFSET; | |
702 | else | |
703 | offset = DMA1_REGISTER_OFFSET; | |
704 | orig = data = RREG32(DMA_POWER_CNTL + offset); | |
705 | data |= MEM_POWER_OVERRIDE; | |
706 | if (data != orig) | |
707 | WREG32(DMA_POWER_CNTL + offset, data); | |
708 | ||
709 | orig = data = RREG32(DMA_CLK_CTRL + offset); | |
710 | data = 0xff000000; | |
711 | if (data != orig) | |
712 | WREG32(DMA_CLK_CTRL + offset, data); | |
713 | } | |
714 | } | |
715 | ||
716 | return 0; | |
717 | } | |
718 | ||
719 | static int si_dma_set_powergating_state(void *handle, | |
720 | enum amd_powergating_state state) | |
721 | { | |
722 | u32 tmp; | |
723 | ||
724 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
725 | ||
726 | WREG32(DMA_PGFSM_WRITE, 0x00002000); | |
727 | WREG32(DMA_PGFSM_CONFIG, 0x100010ff); | |
728 | ||
729 | for (tmp = 0; tmp < 5; tmp++) | |
730 | WREG32(DMA_PGFSM_WRITE, 0); | |
731 | ||
732 | return 0; | |
733 | } | |
734 | ||
a1255107 | 735 | static const struct amd_ip_funcs si_dma_ip_funcs = { |
30d1574f KW |
736 | .name = "si_dma", |
737 | .early_init = si_dma_early_init, | |
738 | .late_init = NULL, | |
739 | .sw_init = si_dma_sw_init, | |
740 | .sw_fini = si_dma_sw_fini, | |
741 | .hw_init = si_dma_hw_init, | |
742 | .hw_fini = si_dma_hw_fini, | |
743 | .suspend = si_dma_suspend, | |
744 | .resume = si_dma_resume, | |
745 | .is_idle = si_dma_is_idle, | |
746 | .wait_for_idle = si_dma_wait_for_idle, | |
747 | .soft_reset = si_dma_soft_reset, | |
748 | .set_clockgating_state = si_dma_set_clockgating_state, | |
749 | .set_powergating_state = si_dma_set_powergating_state, | |
750 | }; | |
751 | ||
752 | static const struct amdgpu_ring_funcs si_dma_ring_funcs = { | |
21cd942e | 753 | .type = AMDGPU_RING_TYPE_SDMA, |
79887142 CK |
754 | .align_mask = 0xf, |
755 | .nop = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0), | |
536fbf94 | 756 | .support_64bit_ptrs = false, |
30d1574f KW |
757 | .get_rptr = si_dma_ring_get_rptr, |
758 | .get_wptr = si_dma_ring_get_wptr, | |
759 | .set_wptr = si_dma_ring_set_wptr, | |
e12f3d7a | 760 | .emit_frame_size = |
2ee150cd | 761 | 3 + 3 + /* hdp flush / invalidate */ |
e12f3d7a | 762 | 6 + /* si_dma_ring_emit_pipeline_sync */ |
4fef88bd | 763 | SI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* si_dma_ring_emit_vm_flush */ |
e12f3d7a CK |
764 | 9 + 9 + 9, /* si_dma_ring_emit_fence x3 for user fence, vm fence */ |
765 | .emit_ib_size = 7 + 3, /* si_dma_ring_emit_ib */ | |
30d1574f KW |
766 | .emit_ib = si_dma_ring_emit_ib, |
767 | .emit_fence = si_dma_ring_emit_fence, | |
768 | .emit_pipeline_sync = si_dma_ring_emit_pipeline_sync, | |
769 | .emit_vm_flush = si_dma_ring_emit_vm_flush, | |
30d1574f KW |
770 | .test_ring = si_dma_ring_test_ring, |
771 | .test_ib = si_dma_ring_test_ib, | |
772 | .insert_nop = amdgpu_ring_insert_nop, | |
773 | .pad_ib = si_dma_ring_pad_ib, | |
5b9263d9 | 774 | .emit_wreg = si_dma_ring_emit_wreg, |
30d1574f KW |
775 | }; |
776 | ||
777 | static void si_dma_set_ring_funcs(struct amdgpu_device *adev) | |
778 | { | |
779 | int i; | |
780 | ||
781 | for (i = 0; i < adev->sdma.num_instances; i++) | |
782 | adev->sdma.instance[i].ring.funcs = &si_dma_ring_funcs; | |
783 | } | |
784 | ||
785 | static const struct amdgpu_irq_src_funcs si_dma_trap_irq_funcs = { | |
786 | .set = si_dma_set_trap_irq_state, | |
787 | .process = si_dma_process_trap_irq, | |
788 | }; | |
789 | ||
790 | static const struct amdgpu_irq_src_funcs si_dma_trap_irq_funcs_1 = { | |
791 | .set = si_dma_set_trap_irq_state, | |
792 | .process = si_dma_process_trap_irq_1, | |
793 | }; | |
794 | ||
795 | static const struct amdgpu_irq_src_funcs si_dma_illegal_inst_irq_funcs = { | |
796 | .process = si_dma_process_illegal_inst_irq, | |
797 | }; | |
798 | ||
799 | static void si_dma_set_irq_funcs(struct amdgpu_device *adev) | |
800 | { | |
801 | adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; | |
802 | adev->sdma.trap_irq.funcs = &si_dma_trap_irq_funcs; | |
803 | adev->sdma.trap_irq_1.funcs = &si_dma_trap_irq_funcs_1; | |
804 | adev->sdma.illegal_inst_irq.funcs = &si_dma_illegal_inst_irq_funcs; | |
805 | } | |
806 | ||
807 | /** | |
808 | * si_dma_emit_copy_buffer - copy buffer using the sDMA engine | |
809 | * | |
810 | * @ring: amdgpu_ring structure holding ring information | |
811 | * @src_offset: src GPU address | |
812 | * @dst_offset: dst GPU address | |
813 | * @byte_count: number of bytes to xfer | |
814 | * | |
815 | * Copy GPU buffers using the DMA engine (VI). | |
816 | * Used by the amdgpu ttm implementation to move pages if | |
817 | * registered as the asic copy callback. | |
818 | */ | |
819 | static void si_dma_emit_copy_buffer(struct amdgpu_ib *ib, | |
820 | uint64_t src_offset, | |
821 | uint64_t dst_offset, | |
822 | uint32_t byte_count) | |
823 | { | |
824 | ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_COPY, | |
825 | 1, 0, 0, byte_count); | |
826 | ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); | |
827 | ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); | |
828 | ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset) & 0xff; | |
829 | ib->ptr[ib->length_dw++] = upper_32_bits(src_offset) & 0xff; | |
830 | } | |
831 | ||
832 | /** | |
833 | * si_dma_emit_fill_buffer - fill buffer using the sDMA engine | |
834 | * | |
835 | * @ring: amdgpu_ring structure holding ring information | |
836 | * @src_data: value to write to buffer | |
837 | * @dst_offset: dst GPU address | |
838 | * @byte_count: number of bytes to xfer | |
839 | * | |
840 | * Fill GPU buffers using the DMA engine (VI). | |
841 | */ | |
842 | static void si_dma_emit_fill_buffer(struct amdgpu_ib *ib, | |
843 | uint32_t src_data, | |
844 | uint64_t dst_offset, | |
845 | uint32_t byte_count) | |
846 | { | |
847 | ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_CONSTANT_FILL, | |
848 | 0, 0, 0, byte_count / 4); | |
849 | ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); | |
850 | ib->ptr[ib->length_dw++] = src_data; | |
851 | ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset) << 16; | |
852 | } | |
853 | ||
854 | ||
855 | static const struct amdgpu_buffer_funcs si_dma_buffer_funcs = { | |
856 | .copy_max_bytes = 0xffff8, | |
857 | .copy_num_dw = 5, | |
858 | .emit_copy_buffer = si_dma_emit_copy_buffer, | |
859 | ||
860 | .fill_max_bytes = 0xffff8, | |
861 | .fill_num_dw = 4, | |
862 | .emit_fill_buffer = si_dma_emit_fill_buffer, | |
863 | }; | |
864 | ||
865 | static void si_dma_set_buffer_funcs(struct amdgpu_device *adev) | |
866 | { | |
867 | if (adev->mman.buffer_funcs == NULL) { | |
868 | adev->mman.buffer_funcs = &si_dma_buffer_funcs; | |
869 | adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; | |
870 | } | |
871 | } | |
872 | ||
873 | static const struct amdgpu_vm_pte_funcs si_dma_vm_pte_funcs = { | |
e6d92197 | 874 | .copy_pte_num_dw = 5, |
30d1574f | 875 | .copy_pte = si_dma_vm_copy_pte, |
e6d92197 | 876 | |
30d1574f KW |
877 | .write_pte = si_dma_vm_write_pte, |
878 | .set_pte_pde = si_dma_vm_set_pte_pde, | |
879 | }; | |
880 | ||
881 | static void si_dma_set_vm_pte_funcs(struct amdgpu_device *adev) | |
882 | { | |
883 | unsigned i; | |
884 | ||
885 | if (adev->vm_manager.vm_pte_funcs == NULL) { | |
886 | adev->vm_manager.vm_pte_funcs = &si_dma_vm_pte_funcs; | |
887 | for (i = 0; i < adev->sdma.num_instances; i++) | |
888 | adev->vm_manager.vm_pte_rings[i] = | |
889 | &adev->sdma.instance[i].ring; | |
890 | ||
891 | adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances; | |
892 | } | |
893 | } | |
a1255107 AD |
894 | |
895 | const struct amdgpu_ip_block_version si_dma_ip_block = | |
896 | { | |
897 | .type = AMD_IP_BLOCK_TYPE_SDMA, | |
898 | .major = 1, | |
899 | .minor = 0, | |
900 | .rev = 0, | |
901 | .funcs = &si_dma_ip_funcs, | |
902 | }; |