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drm/amd/powerplay: delete dpm code for Cz/St.
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / amdgpu / si_dpm.c
CommitLineData
841686df
MB		 1/*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include "drmP.h"
25#include "amdgpu.h"
26#include "amdgpu_pm.h"
27#include "amdgpu_dpm.h"
28#include "amdgpu_atombios.h"
29#include "si/sid.h"
30#include "r600_dpm.h"
31#include "si_dpm.h"
32#include "atom.h"
33#include "../include/pptable.h"
34#include <linux/math64.h>
35#include <linux/seq_file.h>
36#include <linux/firmware.h>
37
38#define MC_CG_ARB_FREQ_F0 0x0a
39#define MC_CG_ARB_FREQ_F1 0x0b
40#define MC_CG_ARB_FREQ_F2 0x0c
41#define MC_CG_ARB_FREQ_F3 0x0d
42
43#define SMC_RAM_END 0x20000
44
45#define SCLK_MIN_DEEPSLEEP_FREQ 1350
46
47
48/* sizeof(ATOM_PPLIB_EXTENDEDHEADER) */
49#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2 12
50#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3 14
51#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4 16
52#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5 18
53#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6 20
54#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7 22
55
56#define BIOS_SCRATCH_4 0x5cd
57
58MODULE_FIRMWARE("radeon/tahiti_smc.bin");
59MODULE_FIRMWARE("radeon/pitcairn_smc.bin");
a8c65c13 60MODULE_FIRMWARE("radeon/pitcairn_k_smc.bin");
841686df 61MODULE_FIRMWARE("radeon/verde_smc.bin");
a8c65c13 62MODULE_FIRMWARE("radeon/verde_k_smc.bin");
841686df 63MODULE_FIRMWARE("radeon/oland_smc.bin");
a8c65c13 64MODULE_FIRMWARE("radeon/oland_k_smc.bin");
841686df 65MODULE_FIRMWARE("radeon/hainan_smc.bin");
a8c65c13 66MODULE_FIRMWARE("radeon/hainan_k_smc.bin");
17324b6a 67MODULE_FIRMWARE("radeon/banks_k_2_smc.bin");
841686df
MB		 68
69union power_info {
70 struct _ATOM_POWERPLAY_INFO info;
71 struct _ATOM_POWERPLAY_INFO_V2 info_2;
72 struct _ATOM_POWERPLAY_INFO_V3 info_3;
73 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
74 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
75 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
76 struct _ATOM_PPLIB_POWERPLAYTABLE4 pplib4;
77 struct _ATOM_PPLIB_POWERPLAYTABLE5 pplib5;
78};
79
80union fan_info {
81 struct _ATOM_PPLIB_FANTABLE fan;
82 struct _ATOM_PPLIB_FANTABLE2 fan2;
83 struct _ATOM_PPLIB_FANTABLE3 fan3;
84};
85
86union pplib_clock_info {
77d318a6
TSD		 87 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
88 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
89 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
90 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
91 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
841686df
MB		 92};
93
a1047777 94static const u32 r600_utc[R600_PM_NUMBER_OF_TC] =
841686df
MB		 95{
96 R600_UTC_DFLT_00,
97 R600_UTC_DFLT_01,
98 R600_UTC_DFLT_02,
99 R600_UTC_DFLT_03,
100 R600_UTC_DFLT_04,
101 R600_UTC_DFLT_05,
102 R600_UTC_DFLT_06,
103 R600_UTC_DFLT_07,
104 R600_UTC_DFLT_08,
105 R600_UTC_DFLT_09,
106 R600_UTC_DFLT_10,
107 R600_UTC_DFLT_11,
108 R600_UTC_DFLT_12,
109 R600_UTC_DFLT_13,
110 R600_UTC_DFLT_14,
111};
112
a1047777 113static const u32 r600_dtc[R600_PM_NUMBER_OF_TC] =
841686df
MB		 114{
115 R600_DTC_DFLT_00,
116 R600_DTC_DFLT_01,
117 R600_DTC_DFLT_02,
118 R600_DTC_DFLT_03,
119 R600_DTC_DFLT_04,
120 R600_DTC_DFLT_05,
121 R600_DTC_DFLT_06,
122 R600_DTC_DFLT_07,
123 R600_DTC_DFLT_08,
124 R600_DTC_DFLT_09,
125 R600_DTC_DFLT_10,
126 R600_DTC_DFLT_11,
127 R600_DTC_DFLT_12,
128 R600_DTC_DFLT_13,
129 R600_DTC_DFLT_14,
130};
131
132static const struct si_cac_config_reg cac_weights_tahiti[] =
133{
134 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
135 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
136 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
137 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
138 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
139 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
140 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
141 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
142 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
143 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
144 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
145 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
146 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
147 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
148 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
149 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
150 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
151 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
152 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
153 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
154 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
155 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
156 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
157 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
158 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
159 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
160 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
161 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
162 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
163 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
164 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
165 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
166 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
167 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
168 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
169 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
170 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
171 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
172 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
173 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
174 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
175 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
176 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
177 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
178 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
179 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
180 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
181 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
182 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
183 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
184 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
185 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
186 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
187 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
188 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
189 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
190 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
191 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
192 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
193 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
194 { 0xFFFFFFFF }
195};
196
197static const struct si_cac_config_reg lcac_tahiti[] =
198{
199 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
200 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
201 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
202 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
203 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
204 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
205 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
206 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
207 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
208 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
209 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
210 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
211 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
212 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
213 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
214 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
215 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
216 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
217 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
218 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
219 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
220 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
221 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
222 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
223 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
224 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
225 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
226 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
227 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
228 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
229 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
230 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
231 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
232 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
233 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
234 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
235 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
236 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
237 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
238 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
239 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
240 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
241 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
242 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
243 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
244 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
245 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
246 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
247 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
248 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
249 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
250 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
251 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
252 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
253 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
254 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
255 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
256 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
257 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
258 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
259 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
260 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
261 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
262 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
263 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
264 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
265 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
266 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
267 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
268 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
269 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
270 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
271 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
272 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
273 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
274 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
275 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
276 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
277 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
278 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
279 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
280 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
281 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
282 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
283 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
284 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
285 { 0xFFFFFFFF }
286
287};
288
289static const struct si_cac_config_reg cac_override_tahiti[] =
290{
291 { 0xFFFFFFFF }
292};
293
294static const struct si_powertune_data powertune_data_tahiti =
295{
296 ((1 << 16) | 27027),
297 6,
298 0,
299 4,
300 95,
301 {
302 0UL,
303 0UL,
304 4521550UL,
305 309631529UL,
306 -1270850L,
307 4513710L,
308 40
309 },
310 595000000UL,
311 12,
312 {
313 0,
314 0,
315 0,
316 0,
317 0,
318 0,
319 0,
320 0
321 },
322 true
323};
324
325static const struct si_dte_data dte_data_tahiti =
326{
327 { 1159409, 0, 0, 0, 0 },
328 { 777, 0, 0, 0, 0 },
329 2,
330 54000,
331 127000,
332 25,
333 2,
334 10,
335 13,
336 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
337 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
338 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
339 85,
340 false
341};
342
e5c5304f 343#if 0
841686df
MB		 344static const struct si_dte_data dte_data_tahiti_le =
345{
346 { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 },
347 { 0x7D, 0x7D, 0x4E4, 0xB00, 0 },
348 0x5,
349 0xAFC8,
350 0x64,
351 0x32,
352 1,
353 0,
354 0x10,
355 { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 },
356 { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 },
357 { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 },
358 85,
359 true
360};
e5c5304f 361#endif
841686df
MB		 362
363static const struct si_dte_data dte_data_tahiti_pro =
364{
365 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
366 { 0x0, 0x0, 0x0, 0x0, 0x0 },
367 5,
368 45000,
369 100,
370 0xA,
371 1,
372 0,
373 0x10,
374 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
375 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
376 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
377 90,
378 true
379};
380
381static const struct si_dte_data dte_data_new_zealand =
382{
383 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
384 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
385 0x5,
386 0xAFC8,
387 0x69,
388 0x32,
389 1,
390 0,
391 0x10,
392 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
393 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
394 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
395 85,
396 true
397};
398
399static const struct si_dte_data dte_data_aruba_pro =
400{
401 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
402 { 0x0, 0x0, 0x0, 0x0, 0x0 },
403 5,
404 45000,
405 100,
406 0xA,
407 1,
408 0,
409 0x10,
410 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
411 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
412 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
413 90,
414 true
415};
416
417static const struct si_dte_data dte_data_malta =
418{
419 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
420 { 0x0, 0x0, 0x0, 0x0, 0x0 },
421 5,
422 45000,
423 100,
424 0xA,
425 1,
426 0,
427 0x10,
428 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
429 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
430 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
431 90,
432 true
433};
434
a1047777 435static const struct si_cac_config_reg cac_weights_pitcairn[] =
841686df
MB		 436{
437 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
438 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
439 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
440 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
441 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
442 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
443 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
444 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
445 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
446 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
447 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
448 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
449 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
450 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
451 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
452 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
453 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
454 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
455 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
456 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
457 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
458 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
459 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
460 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
461 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
462 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
463 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
464 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
465 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
466 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
467 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
468 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
469 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
470 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
471 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
472 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
473 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
474 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
475 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
476 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
477 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
478 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
479 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
480 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
481 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
482 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
483 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
484 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
485 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
486 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
487 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
488 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
489 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
490 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
491 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
492 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
493 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
494 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
495 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
496 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
497 { 0xFFFFFFFF }
498};
499
500static const struct si_cac_config_reg lcac_pitcairn[] =
501{
502 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
503 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
504 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
505 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
506 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
507 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
508 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
509 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
510 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
511 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
512 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
513 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
514 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
515 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
516 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
517 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
518 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
519 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
520 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
521 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
522 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
523 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
524 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
525 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
526 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
527 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
528 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
529 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
530 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
531 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
532 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
533 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
534 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
535 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
536 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
537 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
538 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
539 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
540 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
541 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
542 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
543 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
544 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
545 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
546 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
547 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
548 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
549 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
550 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
551 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
552 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
553 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
554 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
555 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
556 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
557 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
558 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
559 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
560 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
561 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
562 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
563 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
564 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
565 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
566 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
567 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
568 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
569 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
570 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
571 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
572 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
573 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
574 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
575 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
576 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
577 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
578 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
579 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
580 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
581 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
582 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
583 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
584 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
585 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
586 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
587 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
588 { 0xFFFFFFFF }
589};
590
591static const struct si_cac_config_reg cac_override_pitcairn[] =
592{
593 { 0xFFFFFFFF }
594};
595
596static const struct si_powertune_data powertune_data_pitcairn =
597{
598 ((1 << 16) | 27027),
599 5,
600 0,
601 6,
602 100,
603 {
604 51600000UL,
605 1800000UL,
606 7194395UL,
607 309631529UL,
608 -1270850L,
609 4513710L,
610 100
611 },
612 117830498UL,
613 12,
614 {
615 0,
616 0,
617 0,
618 0,
619 0,
620 0,
621 0,
622 0
623 },
624 true
625};
626
627static const struct si_dte_data dte_data_pitcairn =
628{
629 { 0, 0, 0, 0, 0 },
630 { 0, 0, 0, 0, 0 },
631 0,
632 0,
633 0,
634 0,
635 0,
636 0,
637 0,
638 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
639 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
640 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
641 0,
642 false
643};
644
645static const struct si_dte_data dte_data_curacao_xt =
646{
647 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
648 { 0x0, 0x0, 0x0, 0x0, 0x0 },
649 5,
650 45000,
651 100,
652 0xA,
653 1,
654 0,
655 0x10,
656 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
657 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
658 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
659 90,
660 true
661};
662
663static const struct si_dte_data dte_data_curacao_pro =
664{
665 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
666 { 0x0, 0x0, 0x0, 0x0, 0x0 },
667 5,
668 45000,
669 100,
670 0xA,
671 1,
672 0,
673 0x10,
674 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
675 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
676 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
677 90,
678 true
679};
680
681static const struct si_dte_data dte_data_neptune_xt =
682{
683 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
684 { 0x0, 0x0, 0x0, 0x0, 0x0 },
685 5,
686 45000,
687 100,
688 0xA,
689 1,
690 0,
691 0x10,
692 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
693 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
694 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
695 90,
696 true
697};
698
699static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
700{
701 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
702 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
703 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
704 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
705 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
706 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
707 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
708 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
709 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
710 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
711 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
712 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
713 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
714 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
715 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
716 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
717 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
718 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
719 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
720 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
721 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
722 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
723 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
724 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
725 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
726 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
727 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
728 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
729 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
730 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
731 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
732 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
733 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
734 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
735 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
736 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
737 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
738 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
739 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
740 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
741 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
742 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
743 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
744 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
745 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
746 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
747 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
748 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
749 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
750 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
751 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
752 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
753 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
754 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
755 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
756 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
757 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
758 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
759 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
760 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
761 { 0xFFFFFFFF }
762};
763
764static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
765{
766 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
767 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
768 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
769 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
770 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
771 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
772 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
773 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
774 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
775 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
776 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
777 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
778 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
779 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
780 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
781 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
782 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
783 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
784 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
785 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
786 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
787 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
788 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
789 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
790 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
791 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
792 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
793 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
794 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
795 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
796 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
797 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
798 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
799 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
800 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
801 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
802 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
803 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
804 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
805 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
806 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
807 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
808 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
809 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
810 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
811 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
812 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
813 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
814 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
815 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
816 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
817 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
818 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
819 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
820 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
821 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
822 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
823 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
824 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
825 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
826 { 0xFFFFFFFF }
827};
828
829static const struct si_cac_config_reg cac_weights_heathrow[] =
830{
831 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
832 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
833 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
834 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
835 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
836 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
837 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
838 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
839 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
840 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
841 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
842 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
843 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
844 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
845 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
846 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
847 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
848 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
849 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
850 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
851 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
852 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
853 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
854 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
855 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
856 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
857 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
858 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
859 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
860 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
861 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
862 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
863 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
864 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
865 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
866 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
867 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
868 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
869 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
870 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
871 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
872 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
873 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
874 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
875 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
876 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
877 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
878 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
879 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
880 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
881 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
882 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
883 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
884 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
885 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
886 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
887 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
888 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
889 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
890 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
891 { 0xFFFFFFFF }
892};
893
894static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
895{
896 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
897 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
898 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
899 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
900 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
901 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
902 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
903 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
904 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
905 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
906 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
907 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
908 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
909 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
910 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
911 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
912 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
913 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
914 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
915 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
916 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
917 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
918 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
919 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
920 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
921 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
922 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
923 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
924 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
925 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
926 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
927 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
928 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
929 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
930 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
931 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
932 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
933 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
934 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
935 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
936 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
937 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
938 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
939 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
940 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
941 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
942 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
943 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
944 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
945 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
946 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
947 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
948 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
949 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
950 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
951 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
952 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
953 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
954 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
955 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
956 { 0xFFFFFFFF }
957};
958
959static const struct si_cac_config_reg cac_weights_cape_verde[] =
960{
961 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
962 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
963 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
964 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
965 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
966 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
967 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
968 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
969 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
970 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
971 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
972 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
973 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
974 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
975 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
976 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
977 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
978 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
979 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
980 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
981 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
982 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
983 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
984 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
985 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
986 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
987 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
988 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
989 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
990 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
991 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
992 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
993 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
994 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
995 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
996 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
997 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
998 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
999 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1000 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1001 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1002 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1003 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1004 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1005 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1006 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1007 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1008 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1009 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1010 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1011 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1012 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1013 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1014 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1015 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1016 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1017 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1018 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1019 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1020 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1021 { 0xFFFFFFFF }
1022};
1023
1024static const struct si_cac_config_reg lcac_cape_verde[] =
1025{
1026 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1027 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1028 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1029 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1030 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1031 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1032 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1033 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1034 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1035 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1036 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1037 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1038 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1039 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1040 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1041 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1042 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1043 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1044 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1045 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1046 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1047 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1048 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1049 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1050 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1051 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1052 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1053 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1054 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1055 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1056 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1057 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1058 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1059 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1060 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1061 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1062 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1063 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1064 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1065 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1066 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1067 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1068 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1069 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1070 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1071 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1072 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1073 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1074 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1075 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1076 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1077 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1078 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1079 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1080 { 0xFFFFFFFF }
1081};
1082
1083static const struct si_cac_config_reg cac_override_cape_verde[] =
1084{
1085 { 0xFFFFFFFF }
1086};
1087
1088static const struct si_powertune_data powertune_data_cape_verde =
1089{
1090 ((1 << 16) | 0x6993),
1091 5,
1092 0,
1093 7,
1094 105,
1095 {
1096 0UL,
1097 0UL,
1098 7194395UL,
1099 309631529UL,
1100 -1270850L,
1101 4513710L,
1102 100
1103 },
1104 117830498UL,
1105 12,
1106 {
1107 0,
1108 0,
1109 0,
1110 0,
1111 0,
1112 0,
1113 0,
1114 0
1115 },
1116 true
1117};
1118
1119static const struct si_dte_data dte_data_cape_verde =
1120{
1121 { 0, 0, 0, 0, 0 },
1122 { 0, 0, 0, 0, 0 },
1123 0,
1124 0,
1125 0,
1126 0,
1127 0,
1128 0,
1129 0,
1130 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1131 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1132 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1133 0,
1134 false
1135};
1136
1137static const struct si_dte_data dte_data_venus_xtx =
1138{
1139 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1140 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1141 5,
1142 55000,
1143 0x69,
1144 0xA,
1145 1,
1146 0,
1147 0x3,
1148 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1149 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1150 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1151 90,
1152 true
1153};
1154
1155static const struct si_dte_data dte_data_venus_xt =
1156{
1157 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1158 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1159 5,
1160 55000,
1161 0x69,
1162 0xA,
1163 1,
1164 0,
1165 0x3,
1166 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1167 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1168 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1169 90,
1170 true
1171};
1172
1173static const struct si_dte_data dte_data_venus_pro =
1174{
1175 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1176 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1177 5,
1178 55000,
1179 0x69,
1180 0xA,
1181 1,
1182 0,
1183 0x3,
1184 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1185 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1186 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1187 90,
1188 true
1189};
1190
a1047777 1191static const struct si_cac_config_reg cac_weights_oland[] =
841686df
MB		 1192{
1193 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1194 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1195 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1196 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1197 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1198 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1199 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1200 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1201 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1202 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1203 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1204 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1205 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1206 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1207 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1208 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1209 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1210 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1211 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1212 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1213 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1214 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1215 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1216 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1217 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1218 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1219 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1220 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1221 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1222 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1223 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1224 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1225 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1226 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1227 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1228 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1229 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1230 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1231 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1232 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1233 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1234 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1235 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1236 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1237 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1238 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1239 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1240 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1241 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1242 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1243 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1244 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1245 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1246 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1247 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1248 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1249 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1250 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1251 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1252 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1253 { 0xFFFFFFFF }
1254};
1255
1256static const struct si_cac_config_reg cac_weights_mars_pro[] =
1257{
1258 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1259 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1260 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1261 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1262 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1263 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1264 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1265 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1266 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1267 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1268 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1269 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1270 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1271 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1272 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1273 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1274 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1275 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1276 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1277 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1278 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1279 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1280 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1281 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1282 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1283 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1284 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1285 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1286 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1287 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1288 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1289 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1290 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1291 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1292 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1293 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1294 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1295 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1296 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1297 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1298 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1299 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1300 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1301 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1302 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1303 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1304 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1305 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1306 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1307 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1308 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1309 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1310 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1311 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1312 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1313 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1314 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1315 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1316 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1317 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1318 { 0xFFFFFFFF }
1319};
1320
1321static const struct si_cac_config_reg cac_weights_mars_xt[] =
1322{
1323 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1324 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1325 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1326 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1327 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1328 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1329 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1330 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1331 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1332 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1333 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1334 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1335 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1336 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1337 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1338 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1339 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1340 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1341 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1342 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1343 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1344 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1345 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1346 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1347 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1348 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1349 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1350 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1351 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1352 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1353 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1354 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1355 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1356 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1357 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1358 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1359 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1360 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1361 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1362 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1363 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1364 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1365 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1366 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1367 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1368 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1369 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1370 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1371 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1372 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1373 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1374 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1375 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1376 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1377 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1378 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1379 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1380 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1381 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1382 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1383 { 0xFFFFFFFF }
1384};
1385
1386static const struct si_cac_config_reg cac_weights_oland_pro[] =
1387{
1388 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1389 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1390 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1391 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1392 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1393 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1394 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1395 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1396 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1397 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1398 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1399 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1400 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1401 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1402 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1403 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1404 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1405 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1406 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1407 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1408 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1409 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1410 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1411 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1412 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1413 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1414 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1415 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1416 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1417 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1418 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1419 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1420 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1421 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1422 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1423 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1424 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1425 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1426 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1427 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1428 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1429 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1430 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1431 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1432 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1433 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1434 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1435 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1436 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1437 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1438 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1439 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1440 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1441 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1442 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1443 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1444 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1445 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1446 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1447 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1448 { 0xFFFFFFFF }
1449};
1450
1451static const struct si_cac_config_reg cac_weights_oland_xt[] =
1452{
1453 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1454 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1455 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1456 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1457 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1458 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1459 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1460 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1461 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1462 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1463 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1464 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1465 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1466 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1467 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1468 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1469 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1470 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1471 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1472 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1473 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1474 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1475 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1476 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1477 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1478 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1479 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1480 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1481 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1482 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1483 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1484 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1485 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1486 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1487 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1488 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1489 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1490 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1491 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1492 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1493 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1494 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1495 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1496 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1497 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1498 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1499 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1500 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1501 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1502 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1503 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1504 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1505 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1506 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1507 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1508 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1509 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1510 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1511 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1512 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1513 { 0xFFFFFFFF }
1514};
1515
1516static const struct si_cac_config_reg lcac_oland[] =
1517{
1518 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1519 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1520 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1521 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1522 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1523 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1524 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1525 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1526 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1527 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1528 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1529 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1530 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1531 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1532 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1533 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1534 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1535 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1536 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1537 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1538 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1539 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1540 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1541 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1542 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1543 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1544 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1545 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1546 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1547 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1548 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1549 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1550 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1551 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1552 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1553 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1554 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1555 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1556 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1557 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1558 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1559 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1560 { 0xFFFFFFFF }
1561};
1562
1563static const struct si_cac_config_reg lcac_mars_pro[] =
1564{
1565 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1566 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1567 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1568 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1569 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1570 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1571 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1572 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1573 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1574 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1575 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1576 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1577 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1578 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1579 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1580 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1581 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1582 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1583 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1584 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1585 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1586 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1587 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1588 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1589 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1590 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1591 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1592 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1593 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1594 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1595 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1596 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1597 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1598 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1599 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1600 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1601 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1602 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1603 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1604 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1605 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1606 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1607 { 0xFFFFFFFF }
1608};
1609
1610static const struct si_cac_config_reg cac_override_oland[] =
1611{
1612 { 0xFFFFFFFF }
1613};
1614
1615static const struct si_powertune_data powertune_data_oland =
1616{
1617 ((1 << 16) | 0x6993),
1618 5,
1619 0,
1620 7,
1621 105,
1622 {
1623 0UL,
1624 0UL,
1625 7194395UL,
1626 309631529UL,
1627 -1270850L,
1628 4513710L,
1629 100
1630 },
1631 117830498UL,
1632 12,
1633 {
1634 0,
1635 0,
1636 0,
1637 0,
1638 0,
1639 0,
1640 0,
1641 0
1642 },
1643 true
1644};
1645
1646static const struct si_powertune_data powertune_data_mars_pro =
1647{
1648 ((1 << 16) | 0x6993),
1649 5,
1650 0,
1651 7,
1652 105,
1653 {
1654 0UL,
1655 0UL,
1656 7194395UL,
1657 309631529UL,
1658 -1270850L,
1659 4513710L,
1660 100
1661 },
1662 117830498UL,
1663 12,
1664 {
1665 0,
1666 0,
1667 0,
1668 0,
1669 0,
1670 0,
1671 0,
1672 0
1673 },
1674 true
1675};
1676
1677static const struct si_dte_data dte_data_oland =
1678{
1679 { 0, 0, 0, 0, 0 },
1680 { 0, 0, 0, 0, 0 },
1681 0,
1682 0,
1683 0,
1684 0,
1685 0,
1686 0,
1687 0,
1688 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1689 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1690 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1691 0,
1692 false
1693};
1694
1695static const struct si_dte_data dte_data_mars_pro =
1696{
1697 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1698 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1699 5,
1700 55000,
1701 105,
1702 0xA,
1703 1,
1704 0,
1705 0x10,
1706 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1707 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1708 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1709 90,
1710 true
1711};
1712
1713static const struct si_dte_data dte_data_sun_xt =
1714{
1715 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1716 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1717 5,
1718 55000,
1719 105,
1720 0xA,
1721 1,
1722 0,
1723 0x10,
1724 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1725 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1726 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1727 90,
1728 true
1729};
1730
1731
1732static const struct si_cac_config_reg cac_weights_hainan[] =
1733{
1734 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1735 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1736 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1737 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1738 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1739 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1740 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1741 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1742 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1743 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1744 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1745 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1746 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1747 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1748 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1749 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1750 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1751 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1752 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1753 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1754 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1755 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1756 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1757 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1758 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1759 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1760 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1761 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1762 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1763 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1764 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1765 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1766 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1767 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1768 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1769 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1770 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1771 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1772 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1773 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1774 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1775 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1776 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1777 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1778 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1779 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1780 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1781 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1782 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1783 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1784 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1785 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1786 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1787 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1788 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1789 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1790 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1791 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1792 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1793 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1794 { 0xFFFFFFFF }
1795};
1796
1797static const struct si_powertune_data powertune_data_hainan =
1798{
1799 ((1 << 16) | 0x6993),
1800 5,
1801 0,
1802 9,
1803 105,
1804 {
1805 0UL,
1806 0UL,
1807 7194395UL,
1808 309631529UL,
1809 -1270850L,
1810 4513710L,
1811 100
1812 },
1813 117830498UL,
1814 12,
1815 {
1816 0,
1817 0,
1818 0,
1819 0,
1820 0,
1821 0,
1822 0,
1823 0
1824 },
1825 true
1826};
1827
a1047777
AD		 1828static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev);
1829static struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev);
1830static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev);
1831static struct si_ps *si_get_ps(struct amdgpu_ps *rps);
841686df
MB		 1832
1833static int si_populate_voltage_value(struct amdgpu_device *adev,
1834 const struct atom_voltage_table *table,
1835 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1836static int si_get_std_voltage_value(struct amdgpu_device *adev,
1837 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1838 u16 *std_voltage);
1839static int si_write_smc_soft_register(struct amdgpu_device *adev,
1840 u16 reg_offset, u32 value);
1841static int si_convert_power_level_to_smc(struct amdgpu_device *adev,
1842 struct rv7xx_pl *pl,
1843 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1844static int si_calculate_sclk_params(struct amdgpu_device *adev,
1845 u32 engine_clock,
1846 SISLANDS_SMC_SCLK_VALUE *sclk);
1847
1848static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev);
1849static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev);
1850static void si_dpm_set_dpm_funcs(struct amdgpu_device *adev);
1851static void si_dpm_set_irq_funcs(struct amdgpu_device *adev);
1852
841686df
MB		 1853static struct si_power_info *si_get_pi(struct amdgpu_device *adev)
1854{
77d318a6
TSD		 1855 struct si_power_info *pi = adev->pm.dpm.priv;
1856 return pi;
841686df
MB		 1857}
1858
1859static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1860 u16 v, s32 t, u32 ileakage, u32 *leakage)
1861{
1862 s64 kt, kv, leakage_w, i_leakage, vddc;
1863 s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1864 s64 tmp;
1865
1866 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1867 vddc = div64_s64(drm_int2fixp(v), 1000);
1868 temperature = div64_s64(drm_int2fixp(t), 1000);
1869
1870 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1871 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1872 av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1873 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1874 t_ref = drm_int2fixp(coeff->t_ref);
1875
1876 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1877 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
1878 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
1879 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1880
1881 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1882
1883 *leakage = drm_fixp2int(leakage_w * 1000);
1884}
1885
1886static void si_calculate_leakage_for_v_and_t(struct amdgpu_device *adev,
1887 const struct ni_leakage_coeffients *coeff,
1888 u16 v,
1889 s32 t,
1890 u32 i_leakage,
1891 u32 *leakage)
1892{
1893 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1894}
1895
1896static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1897 const u32 fixed_kt, u16 v,
1898 u32 ileakage, u32 *leakage)
1899{
1900 s64 kt, kv, leakage_w, i_leakage, vddc;
1901
1902 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1903 vddc = div64_s64(drm_int2fixp(v), 1000);
1904
1905 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1906 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1907 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1908
1909 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1910
1911 *leakage = drm_fixp2int(leakage_w * 1000);
1912}
1913
1914static void si_calculate_leakage_for_v(struct amdgpu_device *adev,
1915 const struct ni_leakage_coeffients *coeff,
1916 const u32 fixed_kt,
1917 u16 v,
1918 u32 i_leakage,
1919 u32 *leakage)
1920{
1921 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1922}
1923
1924
1925static void si_update_dte_from_pl2(struct amdgpu_device *adev,
1926 struct si_dte_data *dte_data)
1927{
1928 u32 p_limit1 = adev->pm.dpm.tdp_limit;
1929 u32 p_limit2 = adev->pm.dpm.near_tdp_limit;
1930 u32 k = dte_data->k;
1931 u32 t_max = dte_data->max_t;
1932 u32 t_split[5] = { 10, 15, 20, 25, 30 };
1933 u32 t_0 = dte_data->t0;
1934 u32 i;
1935
1936 if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1937 dte_data->tdep_count = 3;
1938
1939 for (i = 0; i < k; i++) {
1940 dte_data->r[i] =
1941 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1942 (p_limit2 * (u32)100);
1943 }
1944
1945 dte_data->tdep_r[1] = dte_data->r[4] * 2;
1946
1947 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1948 dte_data->tdep_r[i] = dte_data->r[4];
1949 }
1950 } else {
1951 DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1952 }
1953}
1954
a1047777 1955static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev)
841686df 1956{
77d318a6 1957 struct rv7xx_power_info *pi = adev->pm.dpm.priv;
841686df 1958
77d318a6 1959 return pi;
841686df
MB		 1960}
1961
a1047777 1962static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev)
841686df 1963{
77d318a6 1964 struct ni_power_info *pi = adev->pm.dpm.priv;
841686df 1965
77d318a6 1966 return pi;
841686df
MB		 1967}
1968
a1047777 1969static struct si_ps *si_get_ps(struct amdgpu_ps *aps)
841686df 1970{
77d318a6 1971 struct si_ps *ps = aps->ps_priv;
841686df 1972
77d318a6 1973 return ps;
841686df
MB		 1974}
1975
1976static void si_initialize_powertune_defaults(struct amdgpu_device *adev)
1977{
1978 struct ni_power_info *ni_pi = ni_get_pi(adev);
1979 struct si_power_info *si_pi = si_get_pi(adev);
1980 bool update_dte_from_pl2 = false;
1981
1982 if (adev->asic_type == CHIP_TAHITI) {
1983 si_pi->cac_weights = cac_weights_tahiti;
1984 si_pi->lcac_config = lcac_tahiti;
1985 si_pi->cac_override = cac_override_tahiti;
1986 si_pi->powertune_data = &powertune_data_tahiti;
1987 si_pi->dte_data = dte_data_tahiti;
1988
1989 switch (adev->pdev->device) {
1990 case 0x6798:
1991 si_pi->dte_data.enable_dte_by_default = true;
1992 break;
1993 case 0x6799:
1994 si_pi->dte_data = dte_data_new_zealand;
1995 break;
1996 case 0x6790:
1997 case 0x6791:
1998 case 0x6792:
1999 case 0x679E:
2000 si_pi->dte_data = dte_data_aruba_pro;
2001 update_dte_from_pl2 = true;
2002 break;
2003 case 0x679B:
2004 si_pi->dte_data = dte_data_malta;
2005 update_dte_from_pl2 = true;
2006 break;
2007 case 0x679A:
2008 si_pi->dte_data = dte_data_tahiti_pro;
2009 update_dte_from_pl2 = true;
2010 break;
2011 default:
2012 if (si_pi->dte_data.enable_dte_by_default == true)
2013 DRM_ERROR("DTE is not enabled!\n");
2014 break;
2015 }
2016 } else if (adev->asic_type == CHIP_PITCAIRN) {
c3d98645
TSD		 2017 si_pi->cac_weights = cac_weights_pitcairn;
2018 si_pi->lcac_config = lcac_pitcairn;
2019 si_pi->cac_override = cac_override_pitcairn;
2020 si_pi->powertune_data = &powertune_data_pitcairn;
2021
841686df
MB		 2022 switch (adev->pdev->device) {
2023 case 0x6810:
2024 case 0x6818:
841686df
MB		 2025 si_pi->dte_data = dte_data_curacao_xt;
2026 update_dte_from_pl2 = true;
2027 break;
2028 case 0x6819:
2029 case 0x6811:
841686df
MB		 2030 si_pi->dte_data = dte_data_curacao_pro;
2031 update_dte_from_pl2 = true;
2032 break;
2033 case 0x6800:
2034 case 0x6806:
841686df
MB		 2035 si_pi->dte_data = dte_data_neptune_xt;
2036 update_dte_from_pl2 = true;
2037 break;
2038 default:
841686df
MB		 2039 si_pi->dte_data = dte_data_pitcairn;
2040 break;
2041 }
2042 } else if (adev->asic_type == CHIP_VERDE) {
2043 si_pi->lcac_config = lcac_cape_verde;
2044 si_pi->cac_override = cac_override_cape_verde;
2045 si_pi->powertune_data = &powertune_data_cape_verde;
2046
2047 switch (adev->pdev->device) {
2048 case 0x683B:
2049 case 0x683F:
2050 case 0x6829:
2051 case 0x6835:
2052 si_pi->cac_weights = cac_weights_cape_verde_pro;
2053 si_pi->dte_data = dte_data_cape_verde;
2054 break;
2055 case 0x682C:
2056 si_pi->cac_weights = cac_weights_cape_verde_pro;
2057 si_pi->dte_data = dte_data_sun_xt;
2058 break;
2059 case 0x6825:
2060 case 0x6827:
2061 si_pi->cac_weights = cac_weights_heathrow;
2062 si_pi->dte_data = dte_data_cape_verde;
2063 break;
2064 case 0x6824:
2065 case 0x682D:
2066 si_pi->cac_weights = cac_weights_chelsea_xt;
2067 si_pi->dte_data = dte_data_cape_verde;
2068 break;
2069 case 0x682F:
2070 si_pi->cac_weights = cac_weights_chelsea_pro;
2071 si_pi->dte_data = dte_data_cape_verde;
2072 break;
2073 case 0x6820:
2074 si_pi->cac_weights = cac_weights_heathrow;
2075 si_pi->dte_data = dte_data_venus_xtx;
2076 break;
2077 case 0x6821:
2078 si_pi->cac_weights = cac_weights_heathrow;
2079 si_pi->dte_data = dte_data_venus_xt;
2080 break;
2081 case 0x6823:
2082 case 0x682B:
2083 case 0x6822:
2084 case 0x682A:
2085 si_pi->cac_weights = cac_weights_chelsea_pro;
2086 si_pi->dte_data = dte_data_venus_pro;
2087 break;
2088 default:
2089 si_pi->cac_weights = cac_weights_cape_verde;
2090 si_pi->dte_data = dte_data_cape_verde;
2091 break;
2092 }
2093 } else if (adev->asic_type == CHIP_OLAND) {
c3d98645
TSD		 2094 si_pi->lcac_config = lcac_mars_pro;
2095 si_pi->cac_override = cac_override_oland;
2096 si_pi->powertune_data = &powertune_data_mars_pro;
2097 si_pi->dte_data = dte_data_mars_pro;
2098
841686df
MB		 2099 switch (adev->pdev->device) {
2100 case 0x6601:
2101 case 0x6621:
2102 case 0x6603:
2103 case 0x6605:
2104 si_pi->cac_weights = cac_weights_mars_pro;
841686df
MB		 2105 update_dte_from_pl2 = true;
2106 break;
2107 case 0x6600:
2108 case 0x6606:
2109 case 0x6620:
2110 case 0x6604:
2111 si_pi->cac_weights = cac_weights_mars_xt;
841686df
MB		 2112 update_dte_from_pl2 = true;
2113 break;
2114 case 0x6611:
2115 case 0x6613:
2116 case 0x6608:
2117 si_pi->cac_weights = cac_weights_oland_pro;
841686df
MB		 2118 update_dte_from_pl2 = true;
2119 break;
2120 case 0x6610:
2121 si_pi->cac_weights = cac_weights_oland_xt;
841686df
MB		 2122 update_dte_from_pl2 = true;
2123 break;
2124 default:
2125 si_pi->cac_weights = cac_weights_oland;
2126 si_pi->lcac_config = lcac_oland;
2127 si_pi->cac_override = cac_override_oland;
2128 si_pi->powertune_data = &powertune_data_oland;
2129 si_pi->dte_data = dte_data_oland;
2130 break;
2131 }
2132 } else if (adev->asic_type == CHIP_HAINAN) {
2133 si_pi->cac_weights = cac_weights_hainan;
2134 si_pi->lcac_config = lcac_oland;
2135 si_pi->cac_override = cac_override_oland;
2136 si_pi->powertune_data = &powertune_data_hainan;
2137 si_pi->dte_data = dte_data_sun_xt;
2138 update_dte_from_pl2 = true;
2139 } else {
2140 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2141 return;
2142 }
2143
2144 ni_pi->enable_power_containment = false;
2145 ni_pi->enable_cac = false;
2146 ni_pi->enable_sq_ramping = false;
2147 si_pi->enable_dte = false;
2148
2149 if (si_pi->powertune_data->enable_powertune_by_default) {
77d318a6 2150 ni_pi->enable_power_containment = true;
841686df
MB		 2151 ni_pi->enable_cac = true;
2152 if (si_pi->dte_data.enable_dte_by_default) {
2153 si_pi->enable_dte = true;
2154 if (update_dte_from_pl2)
2155 si_update_dte_from_pl2(adev, &si_pi->dte_data);
2156
2157 }
2158 ni_pi->enable_sq_ramping = true;
2159 }
2160
2161 ni_pi->driver_calculate_cac_leakage = true;
2162 ni_pi->cac_configuration_required = true;
2163
2164 if (ni_pi->cac_configuration_required) {
2165 ni_pi->support_cac_long_term_average = true;
2166 si_pi->dyn_powertune_data.l2_lta_window_size =
2167 si_pi->powertune_data->l2_lta_window_size_default;
2168 si_pi->dyn_powertune_data.lts_truncate =
2169 si_pi->powertune_data->lts_truncate_default;
2170 } else {
2171 ni_pi->support_cac_long_term_average = false;
2172 si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2173 si_pi->dyn_powertune_data.lts_truncate = 0;
2174 }
2175
2176 si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2177}
2178
2179static u32 si_get_smc_power_scaling_factor(struct amdgpu_device *adev)
2180{
2181 return 1;
2182}
2183
2184static u32 si_calculate_cac_wintime(struct amdgpu_device *adev)
2185{
2186 u32 xclk;
2187 u32 wintime;
2188 u32 cac_window;
2189 u32 cac_window_size;
2190
2191 xclk = amdgpu_asic_get_xclk(adev);
2192
2193 if (xclk == 0)
2194 return 0;
2195
2196 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;
2197 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2198
2199 wintime = (cac_window_size * 100) / xclk;
2200
2201 return wintime;
2202}
2203
2204static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2205{
2206 return power_in_watts;
2207}
2208
2209static int si_calculate_adjusted_tdp_limits(struct amdgpu_device *adev,
2210 bool adjust_polarity,
2211 u32 tdp_adjustment,
2212 u32 *tdp_limit,
2213 u32 *near_tdp_limit)
2214{
2215 u32 adjustment_delta, max_tdp_limit;
2216
2217 if (tdp_adjustment > (u32)adev->pm.dpm.tdp_od_limit)
2218 return -EINVAL;
2219
2220 max_tdp_limit = ((100 + 100) * adev->pm.dpm.tdp_limit) / 100;
2221
2222 if (adjust_polarity) {
2223 *tdp_limit = ((100 + tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100;
2224 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - adev->pm.dpm.tdp_limit);
2225 } else {
2226 *tdp_limit = ((100 - tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100;
2227 adjustment_delta = adev->pm.dpm.tdp_limit - *tdp_limit;
2228 if (adjustment_delta < adev->pm.dpm.near_tdp_limit_adjusted)
2229 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2230 else
2231 *near_tdp_limit = 0;
2232 }
2233
2234 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2235 return -EINVAL;
2236 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2237 return -EINVAL;
2238
2239 return 0;
2240}
2241
2242static int si_populate_smc_tdp_limits(struct amdgpu_device *adev,
2243 struct amdgpu_ps *amdgpu_state)
2244{
2245 struct ni_power_info *ni_pi = ni_get_pi(adev);
2246 struct si_power_info *si_pi = si_get_pi(adev);
2247
2248 if (ni_pi->enable_power_containment) {
2249 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2250 PP_SIslands_PAPMParameters *papm_parm;
2251 struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table;
2252 u32 scaling_factor = si_get_smc_power_scaling_factor(adev);
2253 u32 tdp_limit;
2254 u32 near_tdp_limit;
2255 int ret;
2256
2257 if (scaling_factor == 0)
2258 return -EINVAL;
2259
2260 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2261
2262 ret = si_calculate_adjusted_tdp_limits(adev,
2263 false, /* ??? */
2264 adev->pm.dpm.tdp_adjustment,
2265 &tdp_limit,
2266 &near_tdp_limit);
2267 if (ret)
2268 return ret;
2269
2270 smc_table->dpm2Params.TDPLimit =
2271 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2272 smc_table->dpm2Params.NearTDPLimit =
2273 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2274 smc_table->dpm2Params.SafePowerLimit =
2275 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2276
6861c837
AD		 2277 ret = amdgpu_si_copy_bytes_to_smc(adev,
2278 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2279 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2280 (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2281 sizeof(u32) * 3,
2282 si_pi->sram_end);
841686df
MB		 2283 if (ret)
2284 return ret;
2285
2286 if (si_pi->enable_ppm) {
2287 papm_parm = &si_pi->papm_parm;
2288 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2289 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2290 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2291 papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2292 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2293 papm_parm->PlatformPowerLimit = 0xffffffff;
2294 papm_parm->NearTDPLimitPAPM = 0xffffffff;
2295
6861c837
AD		 2296 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->papm_cfg_table_start,
2297 (u8 *)papm_parm,
2298 sizeof(PP_SIslands_PAPMParameters),
2299 si_pi->sram_end);
841686df
MB		 2300 if (ret)
2301 return ret;
2302 }
2303 }
2304 return 0;
2305}
2306
2307static int si_populate_smc_tdp_limits_2(struct amdgpu_device *adev,
2308 struct amdgpu_ps *amdgpu_state)
2309{
2310 struct ni_power_info *ni_pi = ni_get_pi(adev);
2311 struct si_power_info *si_pi = si_get_pi(adev);
2312
2313 if (ni_pi->enable_power_containment) {
2314 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2315 u32 scaling_factor = si_get_smc_power_scaling_factor(adev);
2316 int ret;
2317
2318 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2319
2320 smc_table->dpm2Params.NearTDPLimit =
2321 cpu_to_be32(si_scale_power_for_smc(adev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2322 smc_table->dpm2Params.SafePowerLimit =
2323 cpu_to_be32(si_scale_power_for_smc((adev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2324
6861c837
AD		 2325 ret = amdgpu_si_copy_bytes_to_smc(adev,
2326 (si_pi->state_table_start +
2327 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2328 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2329 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2330 sizeof(u32) * 2,
2331 si_pi->sram_end);
841686df
MB		 2332 if (ret)
2333 return ret;
2334 }
2335
2336 return 0;
2337}
2338
2339static u16 si_calculate_power_efficiency_ratio(struct amdgpu_device *adev,
2340 const u16 prev_std_vddc,
2341 const u16 curr_std_vddc)
2342{
2343 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2344 u64 prev_vddc = (u64)prev_std_vddc;
2345 u64 curr_vddc = (u64)curr_std_vddc;
2346 u64 pwr_efficiency_ratio, n, d;
2347
2348 if ((prev_vddc == 0) || (curr_vddc == 0))
2349 return 0;
2350
2351 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2352 d = prev_vddc * prev_vddc;
2353 pwr_efficiency_ratio = div64_u64(n, d);
2354
2355 if (pwr_efficiency_ratio > (u64)0xFFFF)
2356 return 0;
2357
2358 return (u16)pwr_efficiency_ratio;
2359}
2360
2361static bool si_should_disable_uvd_powertune(struct amdgpu_device *adev,
2362 struct amdgpu_ps *amdgpu_state)
2363{
2364 struct si_power_info *si_pi = si_get_pi(adev);
2365
2366 if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2367 amdgpu_state->vclk && amdgpu_state->dclk)
2368 return true;
2369
2370 return false;
2371}
2372
2373struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev)
2374{
2375 struct evergreen_power_info *pi = adev->pm.dpm.priv;
2376
2377 return pi;
2378}
2379
2380static int si_populate_power_containment_values(struct amdgpu_device *adev,
2381 struct amdgpu_ps *amdgpu_state,
2382 SISLANDS_SMC_SWSTATE *smc_state)
2383{
2384 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
2385 struct ni_power_info *ni_pi = ni_get_pi(adev);
2386 struct si_ps *state = si_get_ps(amdgpu_state);
2387 SISLANDS_SMC_VOLTAGE_VALUE vddc;
2388 u32 prev_sclk;
2389 u32 max_sclk;
2390 u32 min_sclk;
2391 u16 prev_std_vddc;
2392 u16 curr_std_vddc;
2393 int i;
2394 u16 pwr_efficiency_ratio;
2395 u8 max_ps_percent;
2396 bool disable_uvd_power_tune;
2397 int ret;
2398
2399 if (ni_pi->enable_power_containment == false)
2400 return 0;
2401
2402 if (state->performance_level_count == 0)
2403 return -EINVAL;
2404
2405 if (smc_state->levelCount != state->performance_level_count)
2406 return -EINVAL;
2407
2408 disable_uvd_power_tune = si_should_disable_uvd_powertune(adev, amdgpu_state);
2409
2410 smc_state->levels[0].dpm2.MaxPS = 0;
2411 smc_state->levels[0].dpm2.NearTDPDec = 0;
2412 smc_state->levels[0].dpm2.AboveSafeInc = 0;
2413 smc_state->levels[0].dpm2.BelowSafeInc = 0;
2414 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2415
2416 for (i = 1; i < state->performance_level_count; i++) {
2417 prev_sclk = state->performance_levels[i-1].sclk;
2418 max_sclk = state->performance_levels[i].sclk;
2419 if (i == 1)
2420 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2421 else
2422 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2423
2424 if (prev_sclk > max_sclk)
2425 return -EINVAL;
2426
2427 if ((max_ps_percent == 0) ||
2428 (prev_sclk == max_sclk) ||
77d318a6 2429 disable_uvd_power_tune)
841686df 2430 min_sclk = max_sclk;
77d318a6 2431 else if (i == 1)
841686df 2432 min_sclk = prev_sclk;
77d318a6 2433 else
841686df 2434 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
841686df
MB		 2435
2436 if (min_sclk < state->performance_levels[0].sclk)
2437 min_sclk = state->performance_levels[0].sclk;
2438
2439 if (min_sclk == 0)
2440 return -EINVAL;
2441
2442 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
2443 state->performance_levels[i-1].vddc, &vddc);
2444 if (ret)
2445 return ret;
2446
2447 ret = si_get_std_voltage_value(adev, &vddc, &prev_std_vddc);
2448 if (ret)
2449 return ret;
2450
2451 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
2452 state->performance_levels[i].vddc, &vddc);
2453 if (ret)
2454 return ret;
2455
2456 ret = si_get_std_voltage_value(adev, &vddc, &curr_std_vddc);
2457 if (ret)
2458 return ret;
2459
2460 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(adev,
2461 prev_std_vddc, curr_std_vddc);
2462
2463 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2464 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2465 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2466 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2467 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2468 }
2469
2470 return 0;
2471}
2472
2473static int si_populate_sq_ramping_values(struct amdgpu_device *adev,
2474 struct amdgpu_ps *amdgpu_state,
2475 SISLANDS_SMC_SWSTATE *smc_state)
2476{
2477 struct ni_power_info *ni_pi = ni_get_pi(adev);
2478 struct si_ps *state = si_get_ps(amdgpu_state);
2479 u32 sq_power_throttle, sq_power_throttle2;
2480 bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2481 int i;
2482
2483 if (state->performance_level_count == 0)
2484 return -EINVAL;
2485
2486 if (smc_state->levelCount != state->performance_level_count)
2487 return -EINVAL;
2488
2489 if (adev->pm.dpm.sq_ramping_threshold == 0)
2490 return -EINVAL;
2491
2492 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT))
2493 enable_sq_ramping = false;
2494
2495 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT))
2496 enable_sq_ramping = false;
2497
2498 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT))
2499 enable_sq_ramping = false;
2500
2501 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2502 enable_sq_ramping = false;
2503
2504 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2505 enable_sq_ramping = false;
2506
2507 for (i = 0; i < state->performance_level_count; i++) {
2508 sq_power_throttle = 0;
2509 sq_power_throttle2 = 0;
2510
2511 if ((state->performance_levels[i].sclk >= adev->pm.dpm.sq_ramping_threshold) &&
2512 enable_sq_ramping) {
2513 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER);
2514 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER);
2515 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA);
2516 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE);
2517 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO);
2518 } else {
2519 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK;
2520 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
2521 }
2522
2523 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2524 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2525 }
2526
2527 return 0;
2528}
2529
2530static int si_enable_power_containment(struct amdgpu_device *adev,
2531 struct amdgpu_ps *amdgpu_new_state,
2532 bool enable)
2533{
2534 struct ni_power_info *ni_pi = ni_get_pi(adev);
2535 PPSMC_Result smc_result;
2536 int ret = 0;
2537
2538 if (ni_pi->enable_power_containment) {
2539 if (enable) {
2540 if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {
6861c837 2541 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingActive);
841686df
MB		 2542 if (smc_result != PPSMC_Result_OK) {
2543 ret = -EINVAL;
2544 ni_pi->pc_enabled = false;
2545 } else {
2546 ni_pi->pc_enabled = true;
2547 }
2548 }
2549 } else {
6861c837 2550 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingInactive);
841686df
MB		 2551 if (smc_result != PPSMC_Result_OK)
2552 ret = -EINVAL;
2553 ni_pi->pc_enabled = false;
2554 }
2555 }
2556
2557 return ret;
2558}
2559
2560static int si_initialize_smc_dte_tables(struct amdgpu_device *adev)
2561{
2562 struct si_power_info *si_pi = si_get_pi(adev);
2563 int ret = 0;
2564 struct si_dte_data *dte_data = &si_pi->dte_data;
2565 Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2566 u32 table_size;
2567 u8 tdep_count;
2568 u32 i;
2569
2570 if (dte_data == NULL)
2571 si_pi->enable_dte = false;
2572
2573 if (si_pi->enable_dte == false)
2574 return 0;
2575
2576 if (dte_data->k <= 0)
2577 return -EINVAL;
2578
2579 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL);
2580 if (dte_tables == NULL) {
2581 si_pi->enable_dte = false;
2582 return -ENOMEM;
2583 }
2584
2585 table_size = dte_data->k;
2586
2587 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2588 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2589
2590 tdep_count = dte_data->tdep_count;
2591 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2592 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2593
2594 dte_tables->K = cpu_to_be32(table_size);
2595 dte_tables->T0 = cpu_to_be32(dte_data->t0);
2596 dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2597 dte_tables->WindowSize = dte_data->window_size;
2598 dte_tables->temp_select = dte_data->temp_select;
2599 dte_tables->DTE_mode = dte_data->dte_mode;
2600 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2601
2602 if (tdep_count > 0)
2603 table_size--;
2604
2605 for (i = 0; i < table_size; i++) {
2606 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2607 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]);
2608 }
2609
2610 dte_tables->Tdep_count = tdep_count;
2611
2612 for (i = 0; i < (u32)tdep_count; i++) {
2613 dte_tables->T_limits[i] = dte_data->t_limits[i];
2614 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2615 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2616 }
2617
6861c837
AD		 2618 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->dte_table_start,
2619 (u8 *)dte_tables,
2620 sizeof(Smc_SIslands_DTE_Configuration),
2621 si_pi->sram_end);
841686df
MB		 2622 kfree(dte_tables);
2623
2624 return ret;
2625}
2626
2627static int si_get_cac_std_voltage_max_min(struct amdgpu_device *adev,
2628 u16 *max, u16 *min)
2629{
2630 struct si_power_info *si_pi = si_get_pi(adev);
2631 struct amdgpu_cac_leakage_table *table =
2632 &adev->pm.dpm.dyn_state.cac_leakage_table;
2633 u32 i;
2634 u32 v0_loadline;
2635
841686df
MB		 2636 if (table == NULL)
2637 return -EINVAL;
2638
2639 *max = 0;
2640 *min = 0xFFFF;
2641
2642 for (i = 0; i < table->count; i++) {
2643 if (table->entries[i].vddc > *max)
2644 *max = table->entries[i].vddc;
2645 if (table->entries[i].vddc < *min)
2646 *min = table->entries[i].vddc;
2647 }
2648
2649 if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2650 return -EINVAL;
2651
2652 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2653
2654 if (v0_loadline > 0xFFFFUL)
2655 return -EINVAL;
2656
2657 *min = (u16)v0_loadline;
2658
2659 if ((*min > *max) || (*max == 0) || (*min == 0))
2660 return -EINVAL;
2661
2662 return 0;
2663}
2664
2665static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2666{
2667 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2668 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2669}
2670
2671static int si_init_dte_leakage_table(struct amdgpu_device *adev,
2672 PP_SIslands_CacConfig *cac_tables,
2673 u16 vddc_max, u16 vddc_min, u16 vddc_step,
2674 u16 t0, u16 t_step)
2675{
2676 struct si_power_info *si_pi = si_get_pi(adev);
2677 u32 leakage;
2678 unsigned int i, j;
2679 s32 t;
2680 u32 smc_leakage;
2681 u32 scaling_factor;
2682 u16 voltage;
2683
2684 scaling_factor = si_get_smc_power_scaling_factor(adev);
2685
2686 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2687 t = (1000 * (i * t_step + t0));
2688
2689 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2690 voltage = vddc_max - (vddc_step * j);
2691
2692 si_calculate_leakage_for_v_and_t(adev,
2693 &si_pi->powertune_data->leakage_coefficients,
2694 voltage,
2695 t,
2696 si_pi->dyn_powertune_data.cac_leakage,
2697 &leakage);
2698
2699 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2700
2701 if (smc_leakage > 0xFFFF)
2702 smc_leakage = 0xFFFF;
2703
2704 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2705 cpu_to_be16((u16)smc_leakage);
2706 }
2707 }
2708 return 0;
2709}
2710
2711static int si_init_simplified_leakage_table(struct amdgpu_device *adev,
2712 PP_SIslands_CacConfig *cac_tables,
2713 u16 vddc_max, u16 vddc_min, u16 vddc_step)
2714{
2715 struct si_power_info *si_pi = si_get_pi(adev);
2716 u32 leakage;
2717 unsigned int i, j;
2718 u32 smc_leakage;
2719 u32 scaling_factor;
2720 u16 voltage;
2721
2722 scaling_factor = si_get_smc_power_scaling_factor(adev);
2723
2724 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2725 voltage = vddc_max - (vddc_step * j);
2726
2727 si_calculate_leakage_for_v(adev,
2728 &si_pi->powertune_data->leakage_coefficients,
2729 si_pi->powertune_data->fixed_kt,
2730 voltage,
2731 si_pi->dyn_powertune_data.cac_leakage,
2732 &leakage);
2733
2734 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2735
2736 if (smc_leakage > 0xFFFF)
2737 smc_leakage = 0xFFFF;
2738
2739 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2740 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2741 cpu_to_be16((u16)smc_leakage);
2742 }
2743 return 0;
2744}
2745
2746static int si_initialize_smc_cac_tables(struct amdgpu_device *adev)
2747{
2748 struct ni_power_info *ni_pi = ni_get_pi(adev);
2749 struct si_power_info *si_pi = si_get_pi(adev);
2750 PP_SIslands_CacConfig *cac_tables = NULL;
2751 u16 vddc_max, vddc_min, vddc_step;
2752 u16 t0, t_step;
2753 u32 load_line_slope, reg;
2754 int ret = 0;
2755 u32 ticks_per_us = amdgpu_asic_get_xclk(adev) / 100;
2756
2757 if (ni_pi->enable_cac == false)
2758 return 0;
2759
2760 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL);
2761 if (!cac_tables)
2762 return -ENOMEM;
2763
2764 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
2765 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);
2766 WREG32(CG_CAC_CTRL, reg);
2767
2768 si_pi->dyn_powertune_data.cac_leakage = adev->pm.dpm.cac_leakage;
2769 si_pi->dyn_powertune_data.dc_pwr_value =
2770 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2771 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(adev);
2772 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2773
2774 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2775
2776 ret = si_get_cac_std_voltage_max_min(adev, &vddc_max, &vddc_min);
2777 if (ret)
2778 goto done_free;
2779
2780 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2781 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2782 t_step = 4;
2783 t0 = 60;
2784
2785 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2786 ret = si_init_dte_leakage_table(adev, cac_tables,
2787 vddc_max, vddc_min, vddc_step,
2788 t0, t_step);
2789 else
2790 ret = si_init_simplified_leakage_table(adev, cac_tables,
2791 vddc_max, vddc_min, vddc_step);
2792 if (ret)
2793 goto done_free;
2794
2795 load_line_slope = ((u32)adev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2796
2797 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2798 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2799 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2800 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2801 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2802 cac_tables->R_LL = cpu_to_be32(load_line_slope);
2803 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2804 cac_tables->calculation_repeats = cpu_to_be32(2);
2805 cac_tables->dc_cac = cpu_to_be32(0);
2806 cac_tables->log2_PG_LKG_SCALE = 12;
2807 cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2808 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2809 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2810
6861c837
AD		 2811 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->cac_table_start,
2812 (u8 *)cac_tables,
2813 sizeof(PP_SIslands_CacConfig),
2814 si_pi->sram_end);
841686df
MB		 2815
2816 if (ret)
2817 goto done_free;
2818
2819 ret = si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2820
2821done_free:
2822 if (ret) {
2823 ni_pi->enable_cac = false;
2824 ni_pi->enable_power_containment = false;
2825 }
2826
2827 kfree(cac_tables);
2828
ad2473af 2829 return ret;
841686df
MB		 2830}
2831
2832static int si_program_cac_config_registers(struct amdgpu_device *adev,
2833 const struct si_cac_config_reg *cac_config_regs)
2834{
2835 const struct si_cac_config_reg *config_regs = cac_config_regs;
2836 u32 data = 0, offset;
2837
2838 if (!config_regs)
2839 return -EINVAL;
2840
2841 while (config_regs->offset != 0xFFFFFFFF) {
2842 switch (config_regs->type) {
2843 case SISLANDS_CACCONFIG_CGIND:
2844 offset = SMC_CG_IND_START + config_regs->offset;
2845 if (offset < SMC_CG_IND_END)
2846 data = RREG32_SMC(offset);
2847 break;
2848 default:
2849 data = RREG32(config_regs->offset);
2850 break;
2851 }
2852
2853 data &= ~config_regs->mask;
2854 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2855
2856 switch (config_regs->type) {
2857 case SISLANDS_CACCONFIG_CGIND:
2858 offset = SMC_CG_IND_START + config_regs->offset;
2859 if (offset < SMC_CG_IND_END)
2860 WREG32_SMC(offset, data);
2861 break;
2862 default:
2863 WREG32(config_regs->offset, data);
2864 break;
2865 }
2866 config_regs++;
2867 }
2868 return 0;
2869}
2870
2871static int si_initialize_hardware_cac_manager(struct amdgpu_device *adev)
2872{
2873 struct ni_power_info *ni_pi = ni_get_pi(adev);
2874 struct si_power_info *si_pi = si_get_pi(adev);
2875 int ret;
2876
2877 if ((ni_pi->enable_cac == false) ||
2878 (ni_pi->cac_configuration_required == false))
2879 return 0;
2880
2881 ret = si_program_cac_config_registers(adev, si_pi->lcac_config);
2882 if (ret)
2883 return ret;
2884 ret = si_program_cac_config_registers(adev, si_pi->cac_override);
2885 if (ret)
2886 return ret;
2887 ret = si_program_cac_config_registers(adev, si_pi->cac_weights);
2888 if (ret)
2889 return ret;
2890
2891 return 0;
2892}
2893
2894static int si_enable_smc_cac(struct amdgpu_device *adev,
2895 struct amdgpu_ps *amdgpu_new_state,
2896 bool enable)
2897{
2898 struct ni_power_info *ni_pi = ni_get_pi(adev);
2899 struct si_power_info *si_pi = si_get_pi(adev);
2900 PPSMC_Result smc_result;
2901 int ret = 0;
2902
2903 if (ni_pi->enable_cac) {
2904 if (enable) {
2905 if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {
2906 if (ni_pi->support_cac_long_term_average) {
6861c837 2907 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgEnable);
841686df
MB		 2908 if (smc_result != PPSMC_Result_OK)
2909 ni_pi->support_cac_long_term_average = false;
2910 }
2911
6861c837 2912 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableCac);
841686df
MB		 2913 if (smc_result != PPSMC_Result_OK) {
2914 ret = -EINVAL;
2915 ni_pi->cac_enabled = false;
2916 } else {
2917 ni_pi->cac_enabled = true;
2918 }
2919
2920 if (si_pi->enable_dte) {
6861c837 2921 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE);
841686df
MB		 2922 if (smc_result != PPSMC_Result_OK)
2923 ret = -EINVAL;
2924 }
2925 }
2926 } else if (ni_pi->cac_enabled) {
2927 if (si_pi->enable_dte)
6861c837 2928 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE);
841686df 2929
6861c837 2930 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableCac);
841686df
MB		 2931
2932 ni_pi->cac_enabled = false;
2933
2934 if (ni_pi->support_cac_long_term_average)
6861c837 2935 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgDisable);
841686df
MB		 2936 }
2937 }
2938 return ret;
2939}
2940
2941static int si_init_smc_spll_table(struct amdgpu_device *adev)
2942{
2943 struct ni_power_info *ni_pi = ni_get_pi(adev);
2944 struct si_power_info *si_pi = si_get_pi(adev);
2945 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2946 SISLANDS_SMC_SCLK_VALUE sclk_params;
2947 u32 fb_div, p_div;
2948 u32 clk_s, clk_v;
2949 u32 sclk = 0;
2950 int ret = 0;
2951 u32 tmp;
2952 int i;
2953
2954 if (si_pi->spll_table_start == 0)
2955 return -EINVAL;
2956
2957 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2958 if (spll_table == NULL)
2959 return -ENOMEM;
2960
2961 for (i = 0; i < 256; i++) {
2962 ret = si_calculate_sclk_params(adev, sclk, &sclk_params);
2963 if (ret)
2964 break;
2965 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
2966 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2967 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2968 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2969
2970 fb_div &= ~0x00001FFF;
2971 fb_div >>= 1;
2972 clk_v >>= 6;
2973
2974 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2975 ret = -EINVAL;
2976 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2977 ret = -EINVAL;
2978 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2979 ret = -EINVAL;
2980 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2981 ret = -EINVAL;
2982
2983 if (ret)
2984 break;
2985
2986 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2987 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2988 spll_table->freq[i] = cpu_to_be32(tmp);
2989
2990 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2991 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2992 spll_table->ss[i] = cpu_to_be32(tmp);
2993
2994 sclk += 512;
2995 }
2996
2997
2998 if (!ret)
6861c837
AD		 2999 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->spll_table_start,
3000 (u8 *)spll_table,
3001 sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
3002 si_pi->sram_end);
841686df
MB		 3003
3004 if (ret)
3005 ni_pi->enable_power_containment = false;
3006
3007 kfree(spll_table);
3008
3009 return ret;
3010}
3011
3012struct si_dpm_quirk {
3013 u32 chip_vendor;
3014 u32 chip_device;
3015 u32 subsys_vendor;
3016 u32 subsys_device;
3017 u32 max_sclk;
3018 u32 max_mclk;
3019};
3020
3021/* cards with dpm stability problems */
3022static struct si_dpm_quirk si_dpm_quirk_list[] = {
3023 /* PITCAIRN - https://bugs.freedesktop.org/show_bug.cgi?id=76490 */
3024 { PCI_VENDOR_ID_ATI, 0x6810, 0x1462, 0x3036, 0, 120000 },
3025 { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0xe271, 0, 120000 },
9909a795 3026 { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0x2015, 0, 120000 },
841686df
MB		 3027 { PCI_VENDOR_ID_ATI, 0x6810, 0x174b, 0xe271, 85000, 90000 },
3028 { PCI_VENDOR_ID_ATI, 0x6811, 0x1462, 0x2015, 0, 120000 },
3029 { PCI_VENDOR_ID_ATI, 0x6811, 0x1043, 0x2015, 0, 120000 },
9909a795
AD		 3030 { PCI_VENDOR_ID_ATI, 0x6811, 0x148c, 0x2015, 0, 120000 },
3031 { PCI_VENDOR_ID_ATI, 0x6810, 0x1682, 0x9275, 0, 120000 },
841686df
MB		 3032 { 0, 0, 0, 0 },
3033};
3034
3035static u16 si_get_lower_of_leakage_and_vce_voltage(struct amdgpu_device *adev,
3036 u16 vce_voltage)
3037{
3038 u16 highest_leakage = 0;
3039 struct si_power_info *si_pi = si_get_pi(adev);
3040 int i;
3041
3042 for (i = 0; i < si_pi->leakage_voltage.count; i++){
3043 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage)
3044 highest_leakage = si_pi->leakage_voltage.entries[i].voltage;
3045 }
3046
3047 if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage))
3048 return highest_leakage;
3049
3050 return vce_voltage;
3051}
3052
3053static int si_get_vce_clock_voltage(struct amdgpu_device *adev,
3054 u32 evclk, u32 ecclk, u16 *voltage)
3055{
3056 u32 i;
3057 int ret = -EINVAL;
3058 struct amdgpu_vce_clock_voltage_dependency_table *table =
3059 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
3060
3061 if (((evclk == 0) && (ecclk == 0)) ||
3062 (table && (table->count == 0))) {
3063 *voltage = 0;
3064 return 0;
3065 }
3066
3067 for (i = 0; i < table->count; i++) {
3068 if ((evclk <= table->entries[i].evclk) &&
3069 (ecclk <= table->entries[i].ecclk)) {
3070 *voltage = table->entries[i].v;
3071 ret = 0;
3072 break;
3073 }
3074 }
3075
3076 /* if no match return the highest voltage */
3077 if (ret)
3078 *voltage = table->entries[table->count - 1].v;
3079
3080 *voltage = si_get_lower_of_leakage_and_vce_voltage(adev, *voltage);
3081
3082 return ret;
3083}
3084
3085static bool si_dpm_vblank_too_short(struct amdgpu_device *adev)
3086{
3087
77d318a6
TSD		 3088 u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
3089 /* we never hit the non-gddr5 limit so disable it */
3090 u32 switch_limit = adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 0;
841686df 3091
77d318a6
TSD		 3092 if (vblank_time < switch_limit)
3093 return true;
3094 else
3095 return false;
841686df
MB		 3096
3097}
3098
3099static int ni_copy_and_switch_arb_sets(struct amdgpu_device *adev,
3100 u32 arb_freq_src, u32 arb_freq_dest)
3101{
3102 u32 mc_arb_dram_timing;
3103 u32 mc_arb_dram_timing2;
3104 u32 burst_time;
3105 u32 mc_cg_config;
3106
3107 switch (arb_freq_src) {
77d318a6 3108 case MC_CG_ARB_FREQ_F0:
841686df
MB		 3109 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING);
3110 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
3111 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE0_MASK) >> STATE0_SHIFT;
3112 break;
77d318a6 3113 case MC_CG_ARB_FREQ_F1:
841686df
MB		 3114 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_1);
3115 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_1);
3116 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE1_MASK) >> STATE1_SHIFT;
3117 break;
77d318a6 3118 case MC_CG_ARB_FREQ_F2:
841686df
MB		 3119 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_2);
3120 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_2);
3121 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE2_MASK) >> STATE2_SHIFT;
3122 break;
77d318a6 3123 case MC_CG_ARB_FREQ_F3:
841686df
MB		 3124 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_3);
3125 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_3);
3126 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE3_MASK) >> STATE3_SHIFT;
3127 break;
77d318a6 3128 default:
841686df
MB		 3129 return -EINVAL;
3130 }
3131
3132 switch (arb_freq_dest) {
77d318a6 3133 case MC_CG_ARB_FREQ_F0:
841686df
MB		 3134 WREG32(MC_ARB_DRAM_TIMING, mc_arb_dram_timing);
3135 WREG32(MC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
3136 WREG32_P(MC_ARB_BURST_TIME, STATE0(burst_time), ~STATE0_MASK);
3137 break;
77d318a6 3138 case MC_CG_ARB_FREQ_F1:
841686df
MB		 3139 WREG32(MC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
3140 WREG32(MC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
3141 WREG32_P(MC_ARB_BURST_TIME, STATE1(burst_time), ~STATE1_MASK);
3142 break;
77d318a6 3143 case MC_CG_ARB_FREQ_F2:
841686df
MB		 3144 WREG32(MC_ARB_DRAM_TIMING_2, mc_arb_dram_timing);
3145 WREG32(MC_ARB_DRAM_TIMING2_2, mc_arb_dram_timing2);
3146 WREG32_P(MC_ARB_BURST_TIME, STATE2(burst_time), ~STATE2_MASK);
3147 break;
77d318a6 3148 case MC_CG_ARB_FREQ_F3:
841686df
MB		 3149 WREG32(MC_ARB_DRAM_TIMING_3, mc_arb_dram_timing);
3150 WREG32(MC_ARB_DRAM_TIMING2_3, mc_arb_dram_timing2);
3151 WREG32_P(MC_ARB_BURST_TIME, STATE3(burst_time), ~STATE3_MASK);
3152 break;
3153 default:
3154 return -EINVAL;
3155 }
3156
3157 mc_cg_config = RREG32(MC_CG_CONFIG) | 0x0000000F;
3158 WREG32(MC_CG_CONFIG, mc_cg_config);
3159 WREG32_P(MC_ARB_CG, CG_ARB_REQ(arb_freq_dest), ~CG_ARB_REQ_MASK);
3160
3161 return 0;
3162}
3163
3164static void ni_update_current_ps(struct amdgpu_device *adev,
3165 struct amdgpu_ps *rps)
3166{
77d318a6 3167 struct si_ps *new_ps = si_get_ps(rps);
841686df 3168 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
77d318a6 3169 struct ni_power_info *ni_pi = ni_get_pi(adev);
841686df
MB		 3170
3171 eg_pi->current_rps = *rps;
3172 ni_pi->current_ps = *new_ps;
3173 eg_pi->current_rps.ps_priv = &ni_pi->current_ps;
8c8e2c30 3174 adev->pm.dpm.current_ps = &eg_pi->current_rps;
841686df
MB		 3175}
3176
3177static void ni_update_requested_ps(struct amdgpu_device *adev,
3178 struct amdgpu_ps *rps)
3179{
77d318a6 3180 struct si_ps *new_ps = si_get_ps(rps);
841686df 3181 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
77d318a6 3182 struct ni_power_info *ni_pi = ni_get_pi(adev);
841686df
MB		 3183
3184 eg_pi->requested_rps = *rps;
3185 ni_pi->requested_ps = *new_ps;
3186 eg_pi->requested_rps.ps_priv = &ni_pi->requested_ps;
8c8e2c30 3187 adev->pm.dpm.requested_ps = &eg_pi->requested_rps;
841686df
MB		 3188}
3189
3190static void ni_set_uvd_clock_before_set_eng_clock(struct amdgpu_device *adev,
3191 struct amdgpu_ps *new_ps,
3192 struct amdgpu_ps *old_ps)
3193{
77d318a6
TSD		 3194 struct si_ps *new_state = si_get_ps(new_ps);
3195 struct si_ps *current_state = si_get_ps(old_ps);
841686df
MB		 3196
3197 if ((new_ps->vclk == old_ps->vclk) &&
3198 (new_ps->dclk == old_ps->dclk))
3199 return;
3200
3201 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >=
3202 current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3203 return;
3204
3205 amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);
3206}
3207
3208static void ni_set_uvd_clock_after_set_eng_clock(struct amdgpu_device *adev,
3209 struct amdgpu_ps *new_ps,
3210 struct amdgpu_ps *old_ps)
3211{
77d318a6
TSD		 3212 struct si_ps *new_state = si_get_ps(new_ps);
3213 struct si_ps *current_state = si_get_ps(old_ps);
841686df
MB		 3214
3215 if ((new_ps->vclk == old_ps->vclk) &&
3216 (new_ps->dclk == old_ps->dclk))
3217 return;
3218
3219 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk <
3220 current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3221 return;
3222
3223 amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);
3224}
3225
3226static u16 btc_find_voltage(struct atom_voltage_table *table, u16 voltage)
3227{
77d318a6 3228 unsigned int i;
841686df 3229
77d318a6
TSD		 3230 for (i = 0; i < table->count; i++)
3231 if (voltage <= table->entries[i].value)
3232 return table->entries[i].value;
841686df 3233
77d318a6 3234 return table->entries[table->count - 1].value;
841686df
MB		 3235}
3236
3237static u32 btc_find_valid_clock(struct amdgpu_clock_array *clocks,
77d318a6 3238 u32 max_clock, u32 requested_clock)
841686df 3239{
77d318a6 3240 unsigned int i;
841686df 3241
77d318a6
TSD		 3242 if ((clocks == NULL) || (clocks->count == 0))
3243 return (requested_clock < max_clock) ? requested_clock : max_clock;
841686df 3244
77d318a6
TSD		 3245 for (i = 0; i < clocks->count; i++) {
3246 if (clocks->values[i] >= requested_clock)
3247 return (clocks->values[i] < max_clock) ? clocks->values[i] : max_clock;
3248 }
841686df 3249
77d318a6
TSD		 3250 return (clocks->values[clocks->count - 1] < max_clock) ?
3251 clocks->values[clocks->count - 1] : max_clock;
841686df
MB		 3252}
3253
3254static u32 btc_get_valid_mclk(struct amdgpu_device *adev,
77d318a6 3255 u32 max_mclk, u32 requested_mclk)
841686df 3256{
77d318a6
TSD		 3257 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_mclk_values,
3258 max_mclk, requested_mclk);
841686df
MB		 3259}
3260
3261static u32 btc_get_valid_sclk(struct amdgpu_device *adev,
77d318a6 3262 u32 max_sclk, u32 requested_sclk)
841686df 3263{
77d318a6
TSD		 3264 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_sclk_values,
3265 max_sclk, requested_sclk);
841686df
MB		 3266}
3267
a1047777
AD		 3268static void btc_get_max_clock_from_voltage_dependency_table(struct amdgpu_clock_voltage_dependency_table *table,
3269 u32 *max_clock)
841686df 3270{
77d318a6 3271 u32 i, clock = 0;
841686df 3272
77d318a6
TSD		 3273 if ((table == NULL) || (table->count == 0)) {
3274 *max_clock = clock;
3275 return;
3276 }
841686df 3277
77d318a6
TSD		 3278 for (i = 0; i < table->count; i++) {
3279 if (clock < table->entries[i].clk)
3280 clock = table->entries[i].clk;
3281 }
3282 *max_clock = clock;
841686df
MB		 3283}
3284
3285static void btc_apply_voltage_dependency_rules(struct amdgpu_clock_voltage_dependency_table *table,
77d318a6 3286 u32 clock, u16 max_voltage, u16 *voltage)
841686df 3287{
77d318a6 3288 u32 i;
841686df 3289
77d318a6
TSD		 3290 if ((table == NULL) || (table->count == 0))
3291 return;
841686df 3292
77d318a6
TSD		 3293 for (i= 0; i < table->count; i++) {
3294 if (clock <= table->entries[i].clk) {
3295 if (*voltage < table->entries[i].v)
3296 *voltage = (u16)((table->entries[i].v < max_voltage) ?
3297 table->entries[i].v : max_voltage);
3298 return;
3299 }
3300 }
841686df 3301
77d318a6 3302 *voltage = (*voltage > max_voltage) ? *voltage : max_voltage;
841686df
MB		 3303}
3304
3305static void btc_adjust_clock_combinations(struct amdgpu_device *adev,
77d318a6
TSD		 3306 const struct amdgpu_clock_and_voltage_limits *max_limits,
3307 struct rv7xx_pl *pl)
841686df
MB		 3308{
3309
77d318a6
TSD		 3310 if ((pl->mclk == 0) || (pl->sclk == 0))
3311 return;
841686df 3312
77d318a6
TSD		 3313 if (pl->mclk == pl->sclk)
3314 return;
841686df 3315
77d318a6
TSD		 3316 if (pl->mclk > pl->sclk) {
3317 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > adev->pm.dpm.dyn_state.mclk_sclk_ratio)
3318 pl->sclk = btc_get_valid_sclk(adev,
3319 max_limits->sclk,
3320 (pl->mclk +
3321 (adev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) /
3322 adev->pm.dpm.dyn_state.mclk_sclk_ratio);
3323 } else {
3324 if ((pl->sclk - pl->mclk) > adev->pm.dpm.dyn_state.sclk_mclk_delta)
3325 pl->mclk = btc_get_valid_mclk(adev,
3326 max_limits->mclk,
3327 pl->sclk -
3328 adev->pm.dpm.dyn_state.sclk_mclk_delta);
3329 }
841686df
MB		 3330}
3331
3332static void btc_apply_voltage_delta_rules(struct amdgpu_device *adev,
77d318a6
TSD		 3333 u16 max_vddc, u16 max_vddci,
3334 u16 *vddc, u16 *vddci)
3335{
3336 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3337 u16 new_voltage;
3338
3339 if ((0 == *vddc) || (0 == *vddci))
3340 return;
3341
3342 if (*vddc > *vddci) {
3343 if ((*vddc - *vddci) > adev->pm.dpm.dyn_state.vddc_vddci_delta) {
3344 new_voltage = btc_find_voltage(&eg_pi->vddci_voltage_table,
3345 (*vddc - adev->pm.dpm.dyn_state.vddc_vddci_delta));
3346 *vddci = (new_voltage < max_vddci) ? new_voltage : max_vddci;
3347 }
3348 } else {
3349 if ((*vddci - *vddc) > adev->pm.dpm.dyn_state.vddc_vddci_delta) {
3350 new_voltage = btc_find_voltage(&eg_pi->vddc_voltage_table,
3351 (*vddci - adev->pm.dpm.dyn_state.vddc_vddci_delta));
3352 *vddc = (new_voltage < max_vddc) ? new_voltage : max_vddc;
3353 }
3354 }
841686df
MB		 3355}
3356
3357static enum amdgpu_pcie_gen r600_get_pcie_gen_support(struct amdgpu_device *adev,
3358 u32 sys_mask,
3359 enum amdgpu_pcie_gen asic_gen,
3360 enum amdgpu_pcie_gen default_gen)
3361{
3362 switch (asic_gen) {
3363 case AMDGPU_PCIE_GEN1:
3364 return AMDGPU_PCIE_GEN1;
3365 case AMDGPU_PCIE_GEN2:
3366 return AMDGPU_PCIE_GEN2;
3367 case AMDGPU_PCIE_GEN3:
3368 return AMDGPU_PCIE_GEN3;
3369 default:
3370 if ((sys_mask & DRM_PCIE_SPEED_80) && (default_gen == AMDGPU_PCIE_GEN3))
3371 return AMDGPU_PCIE_GEN3;
3372 else if ((sys_mask & DRM_PCIE_SPEED_50) && (default_gen == AMDGPU_PCIE_GEN2))
3373 return AMDGPU_PCIE_GEN2;
3374 else
3375 return AMDGPU_PCIE_GEN1;
3376 }
3377 return AMDGPU_PCIE_GEN1;
3378}
3379
3380static void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,
3381 u32 *p, u32 *u)
3382{
3383 u32 b_c = 0;
3384 u32 i_c;
3385 u32 tmp;
3386
3387 i_c = (i * r_c) / 100;
3388 tmp = i_c >> p_b;
3389
3390 while (tmp) {
3391 b_c++;
3392 tmp >>= 1;
3393 }
3394
3395 *u = (b_c + 1) / 2;
3396 *p = i_c / (1 << (2 * (*u)));
3397}
3398
3399static int r600_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th)
3400{
3401 u32 k, a, ah, al;
3402 u32 t1;
3403
3404 if ((fl == 0) || (fh == 0) || (fl > fh))
3405 return -EINVAL;
3406
3407 k = (100 * fh) / fl;
3408 t1 = (t * (k - 100));
3409 a = (1000 * (100 * h + t1)) / (10000 + (t1 / 100));
3410 a = (a + 5) / 10;
3411 ah = ((a * t) + 5000) / 10000;
3412 al = a - ah;
3413
3414 *th = t - ah;
3415 *tl = t + al;
3416
3417 return 0;
3418}
3419
3420static bool r600_is_uvd_state(u32 class, u32 class2)
3421{
3422 if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
3423 return true;
3424 if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
3425 return true;
3426 if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
3427 return true;
3428 if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
3429 return true;
3430 if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
3431 return true;
3432 return false;
3433}
3434
3435static u8 rv770_get_memory_module_index(struct amdgpu_device *adev)
3436{
3437 return (u8) ((RREG32(BIOS_SCRATCH_4) >> 16) & 0xff);
3438}
3439
3440static void rv770_get_max_vddc(struct amdgpu_device *adev)
3441{
3442 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3443 u16 vddc;
3444
3445 if (amdgpu_atombios_get_max_vddc(adev, 0, 0, &vddc))
3446 pi->max_vddc = 0;
3447 else
3448 pi->max_vddc = vddc;
3449}
3450
3451static void rv770_get_engine_memory_ss(struct amdgpu_device *adev)
3452{
3453 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3454 struct amdgpu_atom_ss ss;
3455
3456 pi->sclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss,
3457 ASIC_INTERNAL_ENGINE_SS, 0);
3458 pi->mclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss,
3459 ASIC_INTERNAL_MEMORY_SS, 0);
3460
3461 if (pi->sclk_ss || pi->mclk_ss)
3462 pi->dynamic_ss = true;
3463 else
3464 pi->dynamic_ss = false;
3465}
3466
3467
3468static void si_apply_state_adjust_rules(struct amdgpu_device *adev,
3469 struct amdgpu_ps *rps)
3470{
3471 struct si_ps *ps = si_get_ps(rps);
3472 struct amdgpu_clock_and_voltage_limits *max_limits;
3473 bool disable_mclk_switching = false;
3474 bool disable_sclk_switching = false;
3475 u32 mclk, sclk;
3476 u16 vddc, vddci, min_vce_voltage = 0;
3477 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
3478 u32 max_sclk = 0, max_mclk = 0;
3479 int i;
3480 struct si_dpm_quirk *p = si_dpm_quirk_list;
3481
71451bdf
AD		 3482 /* limit all SI kickers */
3483 if (adev->asic_type == CHIP_PITCAIRN) {
3484 if ((adev->pdev->revision == 0x81) ||
3485 (adev->pdev->device == 0x6810) ||
3486 (adev->pdev->device == 0x6811) ||
3487 (adev->pdev->device == 0x6816) ||
3488 (adev->pdev->device == 0x6817) ||
3489 (adev->pdev->device == 0x6806))
3490 max_mclk = 120000;
71451bdf
AD		 3491 } else if (adev->asic_type == CHIP_HAINAN) {
3492 if ((adev->pdev->revision == 0x81) ||
3493 (adev->pdev->revision == 0x83) ||
3494 (adev->pdev->revision == 0xC3) ||
3495 (adev->pdev->device == 0x6664) ||
3496 (adev->pdev->device == 0x6665) ||
3497 (adev->pdev->device == 0x6667)) {
3498 max_sclk = 75000;
71451bdf
AD		 3499 }
3500 }
841686df
MB		 3501 /* Apply dpm quirks */
3502 while (p && p->chip_device != 0) {
3503 if (adev->pdev->vendor == p->chip_vendor &&
3504 adev->pdev->device == p->chip_device &&
3505 adev->pdev->subsystem_vendor == p->subsys_vendor &&
3506 adev->pdev->subsystem_device == p->subsys_device) {
3507 max_sclk = p->max_sclk;
3508 max_mclk = p->max_mclk;
3509 break;
3510 }
3511 ++p;
3512 }
3513
3514 if (rps->vce_active) {
3515 rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;
3516 rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk;
3517 si_get_vce_clock_voltage(adev, rps->evclk, rps->ecclk,
3518 &min_vce_voltage);
3519 } else {
3520 rps->evclk = 0;
3521 rps->ecclk = 0;
3522 }
3523
3524 if ((adev->pm.dpm.new_active_crtc_count > 1) ||
3525 si_dpm_vblank_too_short(adev))
3526 disable_mclk_switching = true;
3527
3528 if (rps->vclk || rps->dclk) {
3529 disable_mclk_switching = true;
3530 disable_sclk_switching = true;
3531 }
3532
3533 if (adev->pm.dpm.ac_power)
3534 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3535 else
3536 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3537
3538 for (i = ps->performance_level_count - 2; i >= 0; i--) {
3539 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
3540 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
3541 }
3542 if (adev->pm.dpm.ac_power == false) {
3543 for (i = 0; i < ps->performance_level_count; i++) {
3544 if (ps->performance_levels[i].mclk > max_limits->mclk)
3545 ps->performance_levels[i].mclk = max_limits->mclk;
3546 if (ps->performance_levels[i].sclk > max_limits->sclk)
3547 ps->performance_levels[i].sclk = max_limits->sclk;
3548 if (ps->performance_levels[i].vddc > max_limits->vddc)
3549 ps->performance_levels[i].vddc = max_limits->vddc;
3550 if (ps->performance_levels[i].vddci > max_limits->vddci)
3551 ps->performance_levels[i].vddci = max_limits->vddci;
3552 }
3553 }
3554
3555 /* limit clocks to max supported clocks based on voltage dependency tables */
3556 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3557 &max_sclk_vddc);
3558 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3559 &max_mclk_vddci);
3560 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3561 &max_mclk_vddc);
3562
3563 for (i = 0; i < ps->performance_level_count; i++) {
3564 if (max_sclk_vddc) {
3565 if (ps->performance_levels[i].sclk > max_sclk_vddc)
3566 ps->performance_levels[i].sclk = max_sclk_vddc;
3567 }
3568 if (max_mclk_vddci) {
3569 if (ps->performance_levels[i].mclk > max_mclk_vddci)
3570 ps->performance_levels[i].mclk = max_mclk_vddci;
3571 }
3572 if (max_mclk_vddc) {
3573 if (ps->performance_levels[i].mclk > max_mclk_vddc)
3574 ps->performance_levels[i].mclk = max_mclk_vddc;
3575 }
3576 if (max_mclk) {
3577 if (ps->performance_levels[i].mclk > max_mclk)
3578 ps->performance_levels[i].mclk = max_mclk;
3579 }
3580 if (max_sclk) {
3581 if (ps->performance_levels[i].sclk > max_sclk)
3582 ps->performance_levels[i].sclk = max_sclk;
3583 }
3584 }
3585
3586 /* XXX validate the min clocks required for display */
3587
3588 if (disable_mclk_switching) {
3589 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk;
3590 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
3591 } else {
3592 mclk = ps->performance_levels[0].mclk;
3593 vddci = ps->performance_levels[0].vddci;
3594 }
3595
3596 if (disable_sclk_switching) {
3597 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk;
3598 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc;
3599 } else {
3600 sclk = ps->performance_levels[0].sclk;
3601 vddc = ps->performance_levels[0].vddc;
3602 }
3603
3604 if (rps->vce_active) {
3605 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk)
3606 sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk;
3607 if (mclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk)
3608 mclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk;
3609 }
3610
3611 /* adjusted low state */
3612 ps->performance_levels[0].sclk = sclk;
3613 ps->performance_levels[0].mclk = mclk;
3614 ps->performance_levels[0].vddc = vddc;
3615 ps->performance_levels[0].vddci = vddci;
3616
3617 if (disable_sclk_switching) {
3618 sclk = ps->performance_levels[0].sclk;
3619 for (i = 1; i < ps->performance_level_count; i++) {
3620 if (sclk < ps->performance_levels[i].sclk)
3621 sclk = ps->performance_levels[i].sclk;
3622 }
3623 for (i = 0; i < ps->performance_level_count; i++) {
3624 ps->performance_levels[i].sclk = sclk;
3625 ps->performance_levels[i].vddc = vddc;
3626 }
3627 } else {
3628 for (i = 1; i < ps->performance_level_count; i++) {
3629 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
3630 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
3631 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
3632 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
3633 }
3634 }
3635
3636 if (disable_mclk_switching) {
3637 mclk = ps->performance_levels[0].mclk;
3638 for (i = 1; i < ps->performance_level_count; i++) {
3639 if (mclk < ps->performance_levels[i].mclk)
3640 mclk = ps->performance_levels[i].mclk;
3641 }
3642 for (i = 0; i < ps->performance_level_count; i++) {
3643 ps->performance_levels[i].mclk = mclk;
3644 ps->performance_levels[i].vddci = vddci;
3645 }
3646 } else {
3647 for (i = 1; i < ps->performance_level_count; i++) {
3648 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
3649 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
3650 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
3651 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
3652 }
3653 }
3654
77d318a6
TSD		 3655 for (i = 0; i < ps->performance_level_count; i++)
3656 btc_adjust_clock_combinations(adev, max_limits,
3657 &ps->performance_levels[i]);
841686df
MB		 3658
3659 for (i = 0; i < ps->performance_level_count; i++) {
3660 if (ps->performance_levels[i].vddc < min_vce_voltage)
3661 ps->performance_levels[i].vddc = min_vce_voltage;
3662 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3663 ps->performance_levels[i].sclk,
3664 max_limits->vddc, &ps->performance_levels[i].vddc);
3665 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3666 ps->performance_levels[i].mclk,
3667 max_limits->vddci, &ps->performance_levels[i].vddci);
3668 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3669 ps->performance_levels[i].mclk,
3670 max_limits->vddc, &ps->performance_levels[i].vddc);
3671 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
3672 adev->clock.current_dispclk,
3673 max_limits->vddc, &ps->performance_levels[i].vddc);
3674 }
3675
3676 for (i = 0; i < ps->performance_level_count; i++) {
3677 btc_apply_voltage_delta_rules(adev,
3678 max_limits->vddc, max_limits->vddci,
3679 &ps->performance_levels[i].vddc,
3680 &ps->performance_levels[i].vddci);
3681 }
3682
3683 ps->dc_compatible = true;
3684 for (i = 0; i < ps->performance_level_count; i++) {
3685 if (ps->performance_levels[i].vddc > adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3686 ps->dc_compatible = false;
3687 }
3688}
3689
3690#if 0
3691static int si_read_smc_soft_register(struct amdgpu_device *adev,
3692 u16 reg_offset, u32 *value)
3693{
3694 struct si_power_info *si_pi = si_get_pi(adev);
3695
6861c837
AD		 3696 return amdgpu_si_read_smc_sram_dword(adev,
3697 si_pi->soft_regs_start + reg_offset, value,
3698 si_pi->sram_end);
841686df
MB		 3699}
3700#endif
3701
3702static int si_write_smc_soft_register(struct amdgpu_device *adev,
3703 u16 reg_offset, u32 value)
3704{
3705 struct si_power_info *si_pi = si_get_pi(adev);
3706
6861c837
AD		 3707 return amdgpu_si_write_smc_sram_dword(adev,
3708 si_pi->soft_regs_start + reg_offset,
3709 value, si_pi->sram_end);
841686df
MB		 3710}
3711
3712static bool si_is_special_1gb_platform(struct amdgpu_device *adev)
3713{
3714 bool ret = false;
3715 u32 tmp, width, row, column, bank, density;
3716 bool is_memory_gddr5, is_special;
3717
3718 tmp = RREG32(MC_SEQ_MISC0);
3719 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3720 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3721 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3722
3723 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
3724 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
3725
3726 tmp = RREG32(MC_ARB_RAMCFG);
3727 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10;
3728 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8;
3729 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
3730
3731 density = (1 << (row + column - 20 + bank)) * width;
3732
3733 if ((adev->pdev->device == 0x6819) &&
3734 is_memory_gddr5 && is_special && (density == 0x400))
3735 ret = true;
3736
3737 return ret;
3738}
3739
3740static void si_get_leakage_vddc(struct amdgpu_device *adev)
3741{
3742 struct si_power_info *si_pi = si_get_pi(adev);
3743 u16 vddc, count = 0;
3744 int i, ret;
3745
3746 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) {
3747 ret = amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(adev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3748
3749 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3750 si_pi->leakage_voltage.entries[count].voltage = vddc;
3751 si_pi->leakage_voltage.entries[count].leakage_index =
3752 SISLANDS_LEAKAGE_INDEX0 + i;
3753 count++;
3754 }
3755 }
3756 si_pi->leakage_voltage.count = count;
3757}
3758
3759static int si_get_leakage_voltage_from_leakage_index(struct amdgpu_device *adev,
3760 u32 index, u16 *leakage_voltage)
3761{
3762 struct si_power_info *si_pi = si_get_pi(adev);
3763 int i;
3764
3765 if (leakage_voltage == NULL)
3766 return -EINVAL;
3767
3768 if ((index & 0xff00) != 0xff00)
3769 return -EINVAL;
3770
3771 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1)
3772 return -EINVAL;
3773
3774 if (index < SISLANDS_LEAKAGE_INDEX0)
3775 return -EINVAL;
3776
3777 for (i = 0; i < si_pi->leakage_voltage.count; i++) {
3778 if (si_pi->leakage_voltage.entries[i].leakage_index == index) {
3779 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;
3780 return 0;
3781 }
3782 }
3783 return -EAGAIN;
3784}
3785
3786static void si_set_dpm_event_sources(struct amdgpu_device *adev, u32 sources)
3787{
3788 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3789 bool want_thermal_protection;
3790 enum amdgpu_dpm_event_src dpm_event_src;
3791
3792 switch (sources) {
3793 case 0:
3794 default:
3795 want_thermal_protection = false;
77d318a6 3796 break;
841686df
MB		 3797 case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL):
3798 want_thermal_protection = true;
3799 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGITAL;
3800 break;
3801 case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
3802 want_thermal_protection = true;
3803 dpm_event_src = AMDGPU_DPM_EVENT_SRC_EXTERNAL;
3804 break;
3805 case ((1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
3806 (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL)):
3807 want_thermal_protection = true;
3808 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
3809 break;
3810 }
3811
3812 if (want_thermal_protection) {
3813 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
3814 if (pi->thermal_protection)
3815 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3816 } else {
3817 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3818 }
3819}
3820
3821static void si_enable_auto_throttle_source(struct amdgpu_device *adev,
3822 enum amdgpu_dpm_auto_throttle_src source,
3823 bool enable)
3824{
3825 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3826
3827 if (enable) {
3828 if (!(pi->active_auto_throttle_sources & (1 << source))) {
3829 pi->active_auto_throttle_sources |= 1 << source;
3830 si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
3831 }
3832 } else {
3833 if (pi->active_auto_throttle_sources & (1 << source)) {
3834 pi->active_auto_throttle_sources &= ~(1 << source);
3835 si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
3836 }
3837 }
3838}
3839
3840static void si_start_dpm(struct amdgpu_device *adev)
3841{
3842 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
3843}
3844
3845static void si_stop_dpm(struct amdgpu_device *adev)
3846{
3847 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
3848}
3849
3850static void si_enable_sclk_control(struct amdgpu_device *adev, bool enable)
3851{
3852 if (enable)
3853 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3854 else
3855 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
3856
3857}
3858
3859#if 0
3860static int si_notify_hardware_of_thermal_state(struct amdgpu_device *adev,
3861 u32 thermal_level)
3862{
3863 PPSMC_Result ret;
3864
3865 if (thermal_level == 0) {
6861c837 3866 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
841686df
MB		 3867 if (ret == PPSMC_Result_OK)
3868 return 0;
3869 else
3870 return -EINVAL;
3871 }
3872 return 0;
3873}
3874
3875static void si_notify_hardware_vpu_recovery_event(struct amdgpu_device *adev)
3876{
3877 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3878}
3879#endif
3880
3881#if 0
3882static int si_notify_hw_of_powersource(struct amdgpu_device *adev, bool ac_power)
3883{
3884 if (ac_power)
6861c837 3885 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
841686df
MB		 3886 0 : -EINVAL;
3887
3888 return 0;
3889}
3890#endif
3891
3892static PPSMC_Result si_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
3893 PPSMC_Msg msg, u32 parameter)
3894{
3895 WREG32(SMC_SCRATCH0, parameter);
6861c837 3896 return amdgpu_si_send_msg_to_smc(adev, msg);
841686df
MB		 3897}
3898
3899static int si_restrict_performance_levels_before_switch(struct amdgpu_device *adev)
3900{
6861c837 3901 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
841686df
MB		 3902 return -EINVAL;
3903
3904 return (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3905 0 : -EINVAL;
3906}
3907
3908static int si_dpm_force_performance_level(struct amdgpu_device *adev,
3909 enum amdgpu_dpm_forced_level level)
3910{
3911 struct amdgpu_ps *rps = adev->pm.dpm.current_ps;
3912 struct si_ps *ps = si_get_ps(rps);
3913 u32 levels = ps->performance_level_count;
3914
3915 if (level == AMDGPU_DPM_FORCED_LEVEL_HIGH) {
3916 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3917 return -EINVAL;
3918
3919 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3920 return -EINVAL;
3921 } else if (level == AMDGPU_DPM_FORCED_LEVEL_LOW) {
3922 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3923 return -EINVAL;
3924
3925 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
3926 return -EINVAL;
3927 } else if (level == AMDGPU_DPM_FORCED_LEVEL_AUTO) {
3928 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3929 return -EINVAL;
3930
3931 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3932 return -EINVAL;
3933 }
3934
3935 adev->pm.dpm.forced_level = level;
3936
3937 return 0;
3938}
3939
3940#if 0
3941static int si_set_boot_state(struct amdgpu_device *adev)
3942{
6861c837 3943 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
841686df
MB		 3944 0 : -EINVAL;
3945}
3946#endif
3947
3948static int si_set_sw_state(struct amdgpu_device *adev)
3949{
6861c837 3950 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
841686df
MB		 3951 0 : -EINVAL;
3952}
3953
3954static int si_halt_smc(struct amdgpu_device *adev)
3955{
6861c837 3956 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
841686df
MB		 3957 return -EINVAL;
3958
6861c837 3959 return (amdgpu_si_wait_for_smc_inactive(adev) == PPSMC_Result_OK) ?
841686df
MB		 3960 0 : -EINVAL;
3961}
3962
3963static int si_resume_smc(struct amdgpu_device *adev)
3964{
6861c837 3965 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
841686df
MB		 3966 return -EINVAL;
3967
6861c837 3968 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
841686df
MB		 3969 0 : -EINVAL;
3970}
3971
3972static void si_dpm_start_smc(struct amdgpu_device *adev)
3973{
6861c837
AD		 3974 amdgpu_si_program_jump_on_start(adev);
3975 amdgpu_si_start_smc(adev);
3976 amdgpu_si_smc_clock(adev, true);
841686df
MB		 3977}
3978
3979static void si_dpm_stop_smc(struct amdgpu_device *adev)
3980{
6861c837
AD		 3981 amdgpu_si_reset_smc(adev);
3982 amdgpu_si_smc_clock(adev, false);
841686df
MB		 3983}
3984
3985static int si_process_firmware_header(struct amdgpu_device *adev)
3986{
3987 struct si_power_info *si_pi = si_get_pi(adev);
3988 u32 tmp;
3989 int ret;
3990
6861c837
AD		 3991 ret = amdgpu_si_read_smc_sram_dword(adev,
3992 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3993 SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
3994 &tmp, si_pi->sram_end);
841686df
MB		 3995 if (ret)
3996 return ret;
3997
77d318a6 3998 si_pi->state_table_start = tmp;
841686df 3999
6861c837
AD		 4000 ret = amdgpu_si_read_smc_sram_dword(adev,
4001 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4002 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
4003 &tmp, si_pi->sram_end);
841686df
MB		 4004 if (ret)
4005 return ret;
4006
4007 si_pi->soft_regs_start = tmp;
4008
6861c837
AD		 4009 ret = amdgpu_si_read_smc_sram_dword(adev,
4010 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4011 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
4012 &tmp, si_pi->sram_end);
841686df
MB		 4013 if (ret)
4014 return ret;
4015
4016 si_pi->mc_reg_table_start = tmp;
4017
6861c837
AD		 4018 ret = amdgpu_si_read_smc_sram_dword(adev,
4019 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4020 SISLANDS_SMC_FIRMWARE_HEADER_fanTable,
4021 &tmp, si_pi->sram_end);
841686df
MB		 4022 if (ret)
4023 return ret;
4024
4025 si_pi->fan_table_start = tmp;
4026
6861c837
AD		 4027 ret = amdgpu_si_read_smc_sram_dword(adev,
4028 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4029 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
4030 &tmp, si_pi->sram_end);
841686df
MB		 4031 if (ret)
4032 return ret;
4033
4034 si_pi->arb_table_start = tmp;
4035
6861c837
AD		 4036 ret = amdgpu_si_read_smc_sram_dword(adev,
4037 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4038 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
4039 &tmp, si_pi->sram_end);
841686df
MB		 4040 if (ret)
4041 return ret;
4042
4043 si_pi->cac_table_start = tmp;
4044
6861c837
AD		 4045 ret = amdgpu_si_read_smc_sram_dword(adev,
4046 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4047 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
4048 &tmp, si_pi->sram_end);
841686df
MB		 4049 if (ret)
4050 return ret;
4051
4052 si_pi->dte_table_start = tmp;
4053
6861c837
AD		 4054 ret = amdgpu_si_read_smc_sram_dword(adev,
4055 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4056 SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
4057 &tmp, si_pi->sram_end);
841686df
MB		 4058 if (ret)
4059 return ret;
4060
4061 si_pi->spll_table_start = tmp;
4062
6861c837
AD		 4063 ret = amdgpu_si_read_smc_sram_dword(adev,
4064 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4065 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
4066 &tmp, si_pi->sram_end);
841686df
MB		 4067 if (ret)
4068 return ret;
4069
4070 si_pi->papm_cfg_table_start = tmp;
4071
4072 return ret;
4073}
4074
4075static void si_read_clock_registers(struct amdgpu_device *adev)
4076{
4077 struct si_power_info *si_pi = si_get_pi(adev);
4078
4079 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
4080 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
4081 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
4082 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
4083 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
4084 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
4085 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
4086 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
4087 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
4088 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
4089 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
4090 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
4091 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
4092 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
4093 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
4094}
4095
4096static void si_enable_thermal_protection(struct amdgpu_device *adev,
4097 bool enable)
4098{
4099 if (enable)
4100 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
4101 else
4102 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
4103}
4104
4105static void si_enable_acpi_power_management(struct amdgpu_device *adev)
4106{
4107 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
4108}
4109
4110#if 0
4111static int si_enter_ulp_state(struct amdgpu_device *adev)
4112{
4113 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
4114
4115 udelay(25000);
4116
4117 return 0;
4118}
4119
4120static int si_exit_ulp_state(struct amdgpu_device *adev)
4121{
4122 int i;
4123
4124 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
4125
4126 udelay(7000);
4127
4128 for (i = 0; i < adev->usec_timeout; i++) {
4129 if (RREG32(SMC_RESP_0) == 1)
4130 break;
4131 udelay(1000);
4132 }
4133
4134 return 0;
4135}
4136#endif
4137
4138static int si_notify_smc_display_change(struct amdgpu_device *adev,
4139 bool has_display)
4140{
4141 PPSMC_Msg msg = has_display ?
4142 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
4143
6861c837 4144 return (amdgpu_si_send_msg_to_smc(adev, msg) == PPSMC_Result_OK) ?
841686df
MB		 4145 0 : -EINVAL;
4146}
4147
4148static void si_program_response_times(struct amdgpu_device *adev)
4149{
4150 u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;
4151 u32 vddc_dly, acpi_dly, vbi_dly;
4152 u32 reference_clock;
4153
4154 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
4155
4156 voltage_response_time = (u32)adev->pm.dpm.voltage_response_time;
77d318a6 4157 backbias_response_time = (u32)adev->pm.dpm.backbias_response_time;
841686df
MB		 4158
4159 if (voltage_response_time == 0)
4160 voltage_response_time = 1000;
4161
4162 acpi_delay_time = 15000;
4163 vbi_time_out = 100000;
4164
4165 reference_clock = amdgpu_asic_get_xclk(adev);
4166
4167 vddc_dly = (voltage_response_time * reference_clock) / 100;
4168 acpi_dly = (acpi_delay_time * reference_clock) / 100;
4169 vbi_dly = (vbi_time_out * reference_clock) / 100;
4170
4171 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly);
4172 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly);
4173 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
4174 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
4175}
4176
4177static void si_program_ds_registers(struct amdgpu_device *adev)
4178{
4179 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4180 u32 tmp;
4181
4182 /* DEEP_SLEEP_CLK_SEL field should be 0x10 on tahiti A0 */
4183 if (adev->asic_type == CHIP_TAHITI && adev->rev_id == 0x0)
4184 tmp = 0x10;
4185 else
4186 tmp = 0x1;
4187
4188 if (eg_pi->sclk_deep_sleep) {
4189 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
4190 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR,
4191 ~AUTOSCALE_ON_SS_CLEAR);
4192 }
4193}
4194
4195static void si_program_display_gap(struct amdgpu_device *adev)
4196{
4197 u32 tmp, pipe;
4198 int i;
4199
4200 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
4201 if (adev->pm.dpm.new_active_crtc_count > 0)
4202 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
4203 else
4204 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
4205
4206 if (adev->pm.dpm.new_active_crtc_count > 1)
4207 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
4208 else
4209 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
4210
4211 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
4212
4213 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
4214 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
4215
4216 if ((adev->pm.dpm.new_active_crtc_count > 0) &&
4217 (!(adev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
4218 /* find the first active crtc */
4219 for (i = 0; i < adev->mode_info.num_crtc; i++) {
4220 if (adev->pm.dpm.new_active_crtcs & (1 << i))
4221 break;
4222 }
4223 if (i == adev->mode_info.num_crtc)
4224 pipe = 0;
4225 else
4226 pipe = i;
4227
4228 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
4229 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
4230 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
4231 }
4232
4233 /* Setting this to false forces the performance state to low if the crtcs are disabled.
4234 * This can be a problem on PowerXpress systems or if you want to use the card
4235 * for offscreen rendering or compute if there are no crtcs enabled.
4236 */
4237 si_notify_smc_display_change(adev, adev->pm.dpm.new_active_crtc_count > 0);
4238}
4239
4240static void si_enable_spread_spectrum(struct amdgpu_device *adev, bool enable)
4241{
4242 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4243
4244 if (enable) {
4245 if (pi->sclk_ss)
4246 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
4247 } else {
4248 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
4249 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
4250 }
4251}
4252
4253static void si_setup_bsp(struct amdgpu_device *adev)
4254{
4255 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4256 u32 xclk = amdgpu_asic_get_xclk(adev);
4257
4258 r600_calculate_u_and_p(pi->asi,
4259 xclk,
4260 16,
4261 &pi->bsp,
4262 &pi->bsu);
4263
4264 r600_calculate_u_and_p(pi->pasi,
4265 xclk,
4266 16,
4267 &pi->pbsp,
4268 &pi->pbsu);
4269
4270
4271 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
4272 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
4273
4274 WREG32(CG_BSP, pi->dsp);
4275}
4276
4277static void si_program_git(struct amdgpu_device *adev)
4278{
4279 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);
4280}
4281
4282static void si_program_tp(struct amdgpu_device *adev)
4283{
4284 int i;
4285 enum r600_td td = R600_TD_DFLT;
4286
4287 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
4288 WREG32(CG_FFCT_0 + i, (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
4289
4290 if (td == R600_TD_AUTO)
4291 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
4292 else
4293 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
4294
4295 if (td == R600_TD_UP)
4296 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
4297
4298 if (td == R600_TD_DOWN)
4299 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
4300}
4301
4302static void si_program_tpp(struct amdgpu_device *adev)
4303{
4304 WREG32(CG_TPC, R600_TPC_DFLT);
4305}
4306
4307static void si_program_sstp(struct amdgpu_device *adev)
4308{
4309 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
4310}
4311
4312static void si_enable_display_gap(struct amdgpu_device *adev)
4313{
4314 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
4315
4316 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
4317 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
4318 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
4319
4320 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
4321 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
4322 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
4323 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
4324}
4325
4326static void si_program_vc(struct amdgpu_device *adev)
4327{
4328 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4329
4330 WREG32(CG_FTV, pi->vrc);
4331}
4332
4333static void si_clear_vc(struct amdgpu_device *adev)
4334{
4335 WREG32(CG_FTV, 0);
4336}
4337
a1047777 4338static u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
841686df
MB		 4339{
4340 u8 mc_para_index;
4341
4342 if (memory_clock < 10000)
4343 mc_para_index = 0;
4344 else if (memory_clock >= 80000)
4345 mc_para_index = 0x0f;
4346 else
4347 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
4348 return mc_para_index;
4349}
4350
a1047777 4351static u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
841686df
MB		 4352{
4353 u8 mc_para_index;
4354
4355 if (strobe_mode) {
4356 if (memory_clock < 12500)
4357 mc_para_index = 0x00;
4358 else if (memory_clock > 47500)
4359 mc_para_index = 0x0f;
4360 else
4361 mc_para_index = (u8)((memory_clock - 10000) / 2500);
4362 } else {
4363 if (memory_clock < 65000)
4364 mc_para_index = 0x00;
4365 else if (memory_clock > 135000)
4366 mc_para_index = 0x0f;
4367 else
4368 mc_para_index = (u8)((memory_clock - 60000) / 5000);
4369 }
4370 return mc_para_index;
4371}
4372
4373static u8 si_get_strobe_mode_settings(struct amdgpu_device *adev, u32 mclk)
4374{
4375 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4376 bool strobe_mode = false;
4377 u8 result = 0;
4378
4379 if (mclk <= pi->mclk_strobe_mode_threshold)
4380 strobe_mode = true;
4381
4382 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
4383 result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
4384 else
4385 result = si_get_ddr3_mclk_frequency_ratio(mclk);
4386
4387 if (strobe_mode)
4388 result |= SISLANDS_SMC_STROBE_ENABLE;
4389
4390 return result;
4391}
4392
4393static int si_upload_firmware(struct amdgpu_device *adev)
4394{
4395 struct si_power_info *si_pi = si_get_pi(adev);
841686df 4396
6861c837
AD		 4397 amdgpu_si_reset_smc(adev);
4398 amdgpu_si_smc_clock(adev, false);
841686df 4399
6861c837 4400 return amdgpu_si_load_smc_ucode(adev, si_pi->sram_end);
841686df
MB		 4401}
4402
4403static bool si_validate_phase_shedding_tables(struct amdgpu_device *adev,
4404 const struct atom_voltage_table *table,
4405 const struct amdgpu_phase_shedding_limits_table *limits)
4406{
4407 u32 data, num_bits, num_levels;
4408
4409 if ((table == NULL) || (limits == NULL))
4410 return false;
4411
4412 data = table->mask_low;
4413
4414 num_bits = hweight32(data);
4415
4416 if (num_bits == 0)
4417 return false;
4418
4419 num_levels = (1 << num_bits);
4420
4421 if (table->count != num_levels)
4422 return false;
4423
4424 if (limits->count != (num_levels - 1))
4425 return false;
4426
4427 return true;
4428}
4429
4430static void si_trim_voltage_table_to_fit_state_table(struct amdgpu_device *adev,
4431 u32 max_voltage_steps,
4432 struct atom_voltage_table *voltage_table)
4433{
4434 unsigned int i, diff;
4435
4436 if (voltage_table->count <= max_voltage_steps)
4437 return;
4438
4439 diff = voltage_table->count - max_voltage_steps;
4440
4441 for (i= 0; i < max_voltage_steps; i++)
4442 voltage_table->entries[i] = voltage_table->entries[i + diff];
4443
4444 voltage_table->count = max_voltage_steps;
4445}
4446
4447static int si_get_svi2_voltage_table(struct amdgpu_device *adev,
4448 struct amdgpu_clock_voltage_dependency_table *voltage_dependency_table,
4449 struct atom_voltage_table *voltage_table)
4450{
4451 u32 i;
4452
4453 if (voltage_dependency_table == NULL)
4454 return -EINVAL;
4455
4456 voltage_table->mask_low = 0;
4457 voltage_table->phase_delay = 0;
4458
4459 voltage_table->count = voltage_dependency_table->count;
4460 for (i = 0; i < voltage_table->count; i++) {
4461 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
4462 voltage_table->entries[i].smio_low = 0;
4463 }
4464
4465 return 0;
4466}
4467
4468static int si_construct_voltage_tables(struct amdgpu_device *adev)
4469{
4470 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4471 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4472 struct si_power_info *si_pi = si_get_pi(adev);
4473 int ret;
4474
4475 if (pi->voltage_control) {
4476 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
4477 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table);
4478 if (ret)
4479 return ret;
4480
4481 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4482 si_trim_voltage_table_to_fit_state_table(adev,
4483 SISLANDS_MAX_NO_VREG_STEPS,
4484 &eg_pi->vddc_voltage_table);
4485 } else if (si_pi->voltage_control_svi2) {
4486 ret = si_get_svi2_voltage_table(adev,
4487 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
4488 &eg_pi->vddc_voltage_table);
4489 if (ret)
4490 return ret;
4491 } else {
4492 return -EINVAL;
4493 }
4494
4495 if (eg_pi->vddci_control) {
4496 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDCI,
4497 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table);
4498 if (ret)
4499 return ret;
4500
4501 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4502 si_trim_voltage_table_to_fit_state_table(adev,
4503 SISLANDS_MAX_NO_VREG_STEPS,
4504 &eg_pi->vddci_voltage_table);
4505 }
4506 if (si_pi->vddci_control_svi2) {
4507 ret = si_get_svi2_voltage_table(adev,
4508 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
4509 &eg_pi->vddci_voltage_table);
4510 if (ret)
4511 return ret;
4512 }
4513
4514 if (pi->mvdd_control) {
4515 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_MVDDC,
4516 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);
4517
4518 if (ret) {
4519 pi->mvdd_control = false;
4520 return ret;
4521 }
4522
4523 if (si_pi->mvdd_voltage_table.count == 0) {
4524 pi->mvdd_control = false;
4525 return -EINVAL;
4526 }
4527
4528 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4529 si_trim_voltage_table_to_fit_state_table(adev,
4530 SISLANDS_MAX_NO_VREG_STEPS,
4531 &si_pi->mvdd_voltage_table);
4532 }
4533
4534 if (si_pi->vddc_phase_shed_control) {
4535 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
4536 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
4537 if (ret)
4538 si_pi->vddc_phase_shed_control = false;
4539
4540 if ((si_pi->vddc_phase_shed_table.count == 0) ||
4541 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
4542 si_pi->vddc_phase_shed_control = false;
4543 }
4544
4545 return 0;
4546}
4547
4548static void si_populate_smc_voltage_table(struct amdgpu_device *adev,
4549 const struct atom_voltage_table *voltage_table,
4550 SISLANDS_SMC_STATETABLE *table)
4551{
4552 unsigned int i;
4553
4554 for (i = 0; i < voltage_table->count; i++)
4555 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
4556}
4557
4558static int si_populate_smc_voltage_tables(struct amdgpu_device *adev,
4559 SISLANDS_SMC_STATETABLE *table)
4560{
4561 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4562 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4563 struct si_power_info *si_pi = si_get_pi(adev);
4564 u8 i;
4565
4566 if (si_pi->voltage_control_svi2) {
4567 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc,
4568 si_pi->svc_gpio_id);
4569 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd,
4570 si_pi->svd_gpio_id);
4571 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type,
4572 2);
4573 } else {
4574 if (eg_pi->vddc_voltage_table.count) {
4575 si_populate_smc_voltage_table(adev, &eg_pi->vddc_voltage_table, table);
4576 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
4577 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
4578
4579 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
4580 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
4581 table->maxVDDCIndexInPPTable = i;
4582 break;
4583 }
4584 }
4585 }
4586
4587 if (eg_pi->vddci_voltage_table.count) {
4588 si_populate_smc_voltage_table(adev, &eg_pi->vddci_voltage_table, table);
4589
4590 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =
4591 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
4592 }
4593
4594
4595 if (si_pi->mvdd_voltage_table.count) {
4596 si_populate_smc_voltage_table(adev, &si_pi->mvdd_voltage_table, table);
4597
4598 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =
4599 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);
4600 }
4601
4602 if (si_pi->vddc_phase_shed_control) {
4603 if (si_validate_phase_shedding_tables(adev, &si_pi->vddc_phase_shed_table,
4604 &adev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
4605 si_populate_smc_voltage_table(adev, &si_pi->vddc_phase_shed_table, table);
4606
bdbdb571 4607 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] =
841686df
MB		 4608 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
4609
4610 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
4611 (u32)si_pi->vddc_phase_shed_table.phase_delay);
4612 } else {
4613 si_pi->vddc_phase_shed_control = false;
4614 }
4615 }
4616 }
4617
4618 return 0;
4619}
4620
4621static int si_populate_voltage_value(struct amdgpu_device *adev,
4622 const struct atom_voltage_table *table,
4623 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4624{
4625 unsigned int i;
4626
4627 for (i = 0; i < table->count; i++) {
4628 if (value <= table->entries[i].value) {
4629 voltage->index = (u8)i;
4630 voltage->value = cpu_to_be16(table->entries[i].value);
4631 break;
4632 }
4633 }
4634
4635 if (i >= table->count)
4636 return -EINVAL;
4637
4638 return 0;
4639}
4640
4641static int si_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk,
4642 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4643{
4644 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4645 struct si_power_info *si_pi = si_get_pi(adev);
4646
4647 if (pi->mvdd_control) {
4648 if (mclk <= pi->mvdd_split_frequency)
4649 voltage->index = 0;
4650 else
4651 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;
4652
4653 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);
4654 }
4655 return 0;
4656}
4657
4658static int si_get_std_voltage_value(struct amdgpu_device *adev,
4659 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
4660 u16 *std_voltage)
4661{
4662 u16 v_index;
4663 bool voltage_found = false;
4664 *std_voltage = be16_to_cpu(voltage->value);
4665
4666 if (adev->pm.dpm.dyn_state.cac_leakage_table.entries) {
4667 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
4668 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
4669 return -EINVAL;
4670
4671 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4672 if (be16_to_cpu(voltage->value) ==
4673 (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4674 voltage_found = true;
4675 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4676 *std_voltage =
4677 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4678 else
4679 *std_voltage =
4680 adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4681 break;
4682 }
4683 }
4684
4685 if (!voltage_found) {
4686 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4687 if (be16_to_cpu(voltage->value) <=
4688 (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4689 voltage_found = true;
4690 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4691 *std_voltage =
4692 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4693 else
4694 *std_voltage =
4695 adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4696 break;
4697 }
4698 }
4699 }
4700 } else {
4701 if ((u32)voltage->index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4702 *std_voltage = adev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
4703 }
4704 }
4705
4706 return 0;
4707}
4708
4709static int si_populate_std_voltage_value(struct amdgpu_device *adev,
4710 u16 value, u8 index,
4711 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4712{
4713 voltage->index = index;
4714 voltage->value = cpu_to_be16(value);
4715
4716 return 0;
4717}
4718
4719static int si_populate_phase_shedding_value(struct amdgpu_device *adev,
4720 const struct amdgpu_phase_shedding_limits_table *limits,
4721 u16 voltage, u32 sclk, u32 mclk,
4722 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
4723{
4724 unsigned int i;
4725
4726 for (i = 0; i < limits->count; i++) {
4727 if ((voltage <= limits->entries[i].voltage) &&
4728 (sclk <= limits->entries[i].sclk) &&
4729 (mclk <= limits->entries[i].mclk))
4730 break;
4731 }
4732
4733 smc_voltage->phase_settings = (u8)i;
4734
4735 return 0;
4736}
4737
4738static int si_init_arb_table_index(struct amdgpu_device *adev)
4739{
4740 struct si_power_info *si_pi = si_get_pi(adev);
4741 u32 tmp;
4742 int ret;
4743
6861c837
AD		 4744 ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start,
4745 &tmp, si_pi->sram_end);
841686df
MB		 4746 if (ret)
4747 return ret;
4748
4749 tmp &= 0x00FFFFFF;
4750 tmp |= MC_CG_ARB_FREQ_F1 << 24;
4751
6861c837
AD		 4752 return amdgpu_si_write_smc_sram_dword(adev, si_pi->arb_table_start,
4753 tmp, si_pi->sram_end);
841686df
MB		 4754}
4755
4756static int si_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev)
4757{
4758 return ni_copy_and_switch_arb_sets(adev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4759}
4760
4761static int si_reset_to_default(struct amdgpu_device *adev)
4762{
6861c837 4763 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
841686df
MB		 4764 0 : -EINVAL;
4765}
4766
4767static int si_force_switch_to_arb_f0(struct amdgpu_device *adev)
4768{
4769 struct si_power_info *si_pi = si_get_pi(adev);
4770 u32 tmp;
4771 int ret;
4772
6861c837
AD		 4773 ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start,
4774 &tmp, si_pi->sram_end);
841686df
MB		 4775 if (ret)
4776 return ret;
4777
4778 tmp = (tmp >> 24) & 0xff;
4779
4780 if (tmp == MC_CG_ARB_FREQ_F0)
4781 return 0;
4782
4783 return ni_copy_and_switch_arb_sets(adev, tmp, MC_CG_ARB_FREQ_F0);
4784}
4785
4786static u32 si_calculate_memory_refresh_rate(struct amdgpu_device *adev,
4787 u32 engine_clock)
4788{
4789 u32 dram_rows;
4790 u32 dram_refresh_rate;
4791 u32 mc_arb_rfsh_rate;
4792 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
4793
4794 if (tmp >= 4)
4795 dram_rows = 16384;
4796 else
4797 dram_rows = 1 << (tmp + 10);
4798
4799 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4800 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4801
4802 return mc_arb_rfsh_rate;
4803}
4804
4805static int si_populate_memory_timing_parameters(struct amdgpu_device *adev,
4806 struct rv7xx_pl *pl,
4807 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4808{
4809 u32 dram_timing;
4810 u32 dram_timing2;
4811 u32 burst_time;
4812
4813 arb_regs->mc_arb_rfsh_rate =
4814 (u8)si_calculate_memory_refresh_rate(adev, pl->sclk);
4815
4816 amdgpu_atombios_set_engine_dram_timings(adev,
4817 pl->sclk,
77d318a6 4818 pl->mclk);
841686df
MB		 4819
4820 dram_timing = RREG32(MC_ARB_DRAM_TIMING);
4821 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
4822 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
4823
4824 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing);
4825 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4826 arb_regs->mc_arb_burst_time = (u8)burst_time;
4827
4828 return 0;
4829}
4830
4831static int si_do_program_memory_timing_parameters(struct amdgpu_device *adev,
4832 struct amdgpu_ps *amdgpu_state,
4833 unsigned int first_arb_set)
4834{
4835 struct si_power_info *si_pi = si_get_pi(adev);
4836 struct si_ps *state = si_get_ps(amdgpu_state);
4837 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4838 int i, ret = 0;
4839
4840 for (i = 0; i < state->performance_level_count; i++) {
4841 ret = si_populate_memory_timing_parameters(adev, &state->performance_levels[i], &arb_regs);
4842 if (ret)
4843 break;
6861c837
AD		 4844 ret = amdgpu_si_copy_bytes_to_smc(adev,
4845 si_pi->arb_table_start +
4846 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4847 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4848 (u8 *)&arb_regs,
4849 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4850 si_pi->sram_end);
841686df
MB		 4851 if (ret)
4852 break;
77d318a6 4853 }
841686df
MB		 4854
4855 return ret;
4856}
4857
4858static int si_program_memory_timing_parameters(struct amdgpu_device *adev,
4859 struct amdgpu_ps *amdgpu_new_state)
4860{
4861 return si_do_program_memory_timing_parameters(adev, amdgpu_new_state,
4862 SISLANDS_DRIVER_STATE_ARB_INDEX);
4863}
4864
4865static int si_populate_initial_mvdd_value(struct amdgpu_device *adev,
4866 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4867{
4868 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4869 struct si_power_info *si_pi = si_get_pi(adev);
4870
4871 if (pi->mvdd_control)
4872 return si_populate_voltage_value(adev, &si_pi->mvdd_voltage_table,
4873 si_pi->mvdd_bootup_value, voltage);
4874
4875 return 0;
4876}
4877
4878static int si_populate_smc_initial_state(struct amdgpu_device *adev,
4879 struct amdgpu_ps *amdgpu_initial_state,
4880 SISLANDS_SMC_STATETABLE *table)
4881{
4882 struct si_ps *initial_state = si_get_ps(amdgpu_initial_state);
4883 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4884 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4885 struct si_power_info *si_pi = si_get_pi(adev);
4886 u32 reg;
4887 int ret;
4888
4889 table->initialState.levels[0].mclk.vDLL_CNTL =
4890 cpu_to_be32(si_pi->clock_registers.dll_cntl);
4891 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4892 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4893 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4894 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4895 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4896 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4897 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =
4898 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4899 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4900 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4901 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4902 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4903 table->initialState.levels[0].mclk.vMPLL_SS =
4904 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4905 table->initialState.levels[0].mclk.vMPLL_SS2 =
4906 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4907
4908 table->initialState.levels[0].mclk.mclk_value =
4909 cpu_to_be32(initial_state->performance_levels[0].mclk);
4910
4911 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4912 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4913 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4914 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4915 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4916 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4917 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4918 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4919 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
4920 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4921 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
4922 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4923
4924 table->initialState.levels[0].sclk.sclk_value =
4925 cpu_to_be32(initial_state->performance_levels[0].sclk);
4926
4927 table->initialState.levels[0].arbRefreshState =
4928 SISLANDS_INITIAL_STATE_ARB_INDEX;
4929
4930 table->initialState.levels[0].ACIndex = 0;
4931
4932 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
4933 initial_state->performance_levels[0].vddc,
4934 &table->initialState.levels[0].vddc);
4935
4936 if (!ret) {
4937 u16 std_vddc;
4938
4939 ret = si_get_std_voltage_value(adev,
4940 &table->initialState.levels[0].vddc,
4941 &std_vddc);
4942 if (!ret)
4943 si_populate_std_voltage_value(adev, std_vddc,
4944 table->initialState.levels[0].vddc.index,
4945 &table->initialState.levels[0].std_vddc);
4946 }
4947
4948 if (eg_pi->vddci_control)
4949 si_populate_voltage_value(adev,
4950 &eg_pi->vddci_voltage_table,
4951 initial_state->performance_levels[0].vddci,
4952 &table->initialState.levels[0].vddci);
4953
4954 if (si_pi->vddc_phase_shed_control)
4955 si_populate_phase_shedding_value(adev,
4956 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
4957 initial_state->performance_levels[0].vddc,
4958 initial_state->performance_levels[0].sclk,
4959 initial_state->performance_levels[0].mclk,
4960 &table->initialState.levels[0].vddc);
4961
4962 si_populate_initial_mvdd_value(adev, &table->initialState.levels[0].mvdd);
4963
4964 reg = CG_R(0xffff) | CG_L(0);
4965 table->initialState.levels[0].aT = cpu_to_be32(reg);
841686df 4966 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
841686df
MB		 4967 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
4968
4969 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
4970 table->initialState.levels[0].strobeMode =
4971 si_get_strobe_mode_settings(adev,
4972 initial_state->performance_levels[0].mclk);
4973
4974 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4975 table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4976 else
4977 table->initialState.levels[0].mcFlags = 0;
4978 }
4979
4980 table->initialState.levelCount = 1;
4981
4982 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
4983
4984 table->initialState.levels[0].dpm2.MaxPS = 0;
4985 table->initialState.levels[0].dpm2.NearTDPDec = 0;
4986 table->initialState.levels[0].dpm2.AboveSafeInc = 0;
4987 table->initialState.levels[0].dpm2.BelowSafeInc = 0;
4988 table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4989
4990 reg = MIN_POWER_MASK | MAX_POWER_MASK;
4991 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4992
4993 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4994 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4995
4996 return 0;
4997}
4998
4999static int si_populate_smc_acpi_state(struct amdgpu_device *adev,
5000 SISLANDS_SMC_STATETABLE *table)
5001{
5002 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5003 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5004 struct si_power_info *si_pi = si_get_pi(adev);
5005 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
5006 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
5007 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
5008 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
5009 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
5010 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
5011 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
5012 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
5013 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
5014 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
5015 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
5016 u32 reg;
5017 int ret;
5018
5019 table->ACPIState = table->initialState;
5020
5021 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
5022
5023 if (pi->acpi_vddc) {
5024 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
5025 pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
5026 if (!ret) {
5027 u16 std_vddc;
5028
5029 ret = si_get_std_voltage_value(adev,
5030 &table->ACPIState.levels[0].vddc, &std_vddc);
5031 if (!ret)
5032 si_populate_std_voltage_value(adev, std_vddc,
5033 table->ACPIState.levels[0].vddc.index,
5034 &table->ACPIState.levels[0].std_vddc);
5035 }
5036 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;
5037
5038 if (si_pi->vddc_phase_shed_control) {
5039 si_populate_phase_shedding_value(adev,
5040 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5041 pi->acpi_vddc,
5042 0,
5043 0,
5044 &table->ACPIState.levels[0].vddc);
5045 }
5046 } else {
5047 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
5048 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
5049 if (!ret) {
5050 u16 std_vddc;
5051
5052 ret = si_get_std_voltage_value(adev,
5053 &table->ACPIState.levels[0].vddc, &std_vddc);
5054
5055 if (!ret)
5056 si_populate_std_voltage_value(adev, std_vddc,
5057 table->ACPIState.levels[0].vddc.index,
5058 &table->ACPIState.levels[0].std_vddc);
5059 }
5060 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(adev,
5061 si_pi->sys_pcie_mask,
5062 si_pi->boot_pcie_gen,
5063 AMDGPU_PCIE_GEN1);
5064
5065 if (si_pi->vddc_phase_shed_control)
5066 si_populate_phase_shedding_value(adev,
5067 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5068 pi->min_vddc_in_table,
5069 0,
5070 0,
5071 &table->ACPIState.levels[0].vddc);
5072 }
5073
5074 if (pi->acpi_vddc) {
5075 if (eg_pi->acpi_vddci)
5076 si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table,
5077 eg_pi->acpi_vddci,
5078 &table->ACPIState.levels[0].vddci);
5079 }
5080
5081 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
5082 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
5083
5084 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
5085
5086 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
5087 spll_func_cntl_2 |= SCLK_MUX_SEL(4);
5088
5089 table->ACPIState.levels[0].mclk.vDLL_CNTL =
5090 cpu_to_be32(dll_cntl);
5091 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
5092 cpu_to_be32(mclk_pwrmgt_cntl);
5093 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
5094 cpu_to_be32(mpll_ad_func_cntl);
5095 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
5096 cpu_to_be32(mpll_dq_func_cntl);
5097 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =
5098 cpu_to_be32(mpll_func_cntl);
5099 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
5100 cpu_to_be32(mpll_func_cntl_1);
5101 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
5102 cpu_to_be32(mpll_func_cntl_2);
5103 table->ACPIState.levels[0].mclk.vMPLL_SS =
5104 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
5105 table->ACPIState.levels[0].mclk.vMPLL_SS2 =
5106 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
5107
5108 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
5109 cpu_to_be32(spll_func_cntl);
5110 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
5111 cpu_to_be32(spll_func_cntl_2);
5112 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
5113 cpu_to_be32(spll_func_cntl_3);
5114 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
5115 cpu_to_be32(spll_func_cntl_4);
5116
5117 table->ACPIState.levels[0].mclk.mclk_value = 0;
5118 table->ACPIState.levels[0].sclk.sclk_value = 0;
5119
5120 si_populate_mvdd_value(adev, 0, &table->ACPIState.levels[0].mvdd);
5121
5122 if (eg_pi->dynamic_ac_timing)
5123 table->ACPIState.levels[0].ACIndex = 0;
5124
5125 table->ACPIState.levels[0].dpm2.MaxPS = 0;
5126 table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
5127 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
5128 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
5129 table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;
5130
5131 reg = MIN_POWER_MASK | MAX_POWER_MASK;
5132 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
5133
5134 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
5135 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
5136
5137 return 0;
5138}
5139
5140static int si_populate_ulv_state(struct amdgpu_device *adev,
5141 SISLANDS_SMC_SWSTATE *state)
5142{
5143 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5144 struct si_power_info *si_pi = si_get_pi(adev);
5145 struct si_ulv_param *ulv = &si_pi->ulv;
5146 u32 sclk_in_sr = 1350; /* ??? */
5147 int ret;
5148
5149 ret = si_convert_power_level_to_smc(adev, &ulv->pl,
5150 &state->levels[0]);
5151 if (!ret) {
5152 if (eg_pi->sclk_deep_sleep) {
5153 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5154 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5155 else
5156 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5157 }
5158 if (ulv->one_pcie_lane_in_ulv)
5159 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1;
5160 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
5161 state->levels[0].ACIndex = 1;
5162 state->levels[0].std_vddc = state->levels[0].vddc;
5163 state->levelCount = 1;
5164
5165 state->flags |= PPSMC_SWSTATE_FLAG_DC;
5166 }
5167
5168 return ret;
5169}
5170
5171static int si_program_ulv_memory_timing_parameters(struct amdgpu_device *adev)
5172{
5173 struct si_power_info *si_pi = si_get_pi(adev);
5174 struct si_ulv_param *ulv = &si_pi->ulv;
5175 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
5176 int ret;
5177
5178 ret = si_populate_memory_timing_parameters(adev, &ulv->pl,
5179 &arb_regs);
5180 if (ret)
5181 return ret;
5182
5183 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
5184 ulv->volt_change_delay);
5185
6861c837
AD		 5186 ret = amdgpu_si_copy_bytes_to_smc(adev,
5187 si_pi->arb_table_start +
5188 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
5189 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
5190 (u8 *)&arb_regs,
5191 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
5192 si_pi->sram_end);
841686df
MB		 5193
5194 return ret;
5195}
5196
5197static void si_get_mvdd_configuration(struct amdgpu_device *adev)
5198{
5199 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5200
5201 pi->mvdd_split_frequency = 30000;
5202}
5203
5204static int si_init_smc_table(struct amdgpu_device *adev)
5205{
5206 struct si_power_info *si_pi = si_get_pi(adev);
5207 struct amdgpu_ps *amdgpu_boot_state = adev->pm.dpm.boot_ps;
5208 const struct si_ulv_param *ulv = &si_pi->ulv;
5209 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable;
5210 int ret;
5211 u32 lane_width;
5212 u32 vr_hot_gpio;
5213
5214 si_populate_smc_voltage_tables(adev, table);
5215
5216 switch (adev->pm.int_thermal_type) {
5217 case THERMAL_TYPE_SI:
5218 case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
5219 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
5220 break;
5221 case THERMAL_TYPE_NONE:
5222 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
5223 break;
5224 default:
5225 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
5226 break;
5227 }
5228
5229 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
5230 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
5231
5232 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
5233 if ((adev->pdev->device != 0x6818) && (adev->pdev->device != 0x6819))
5234 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
5235 }
5236
5237 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
5238 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
5239
5240 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
5241 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
5242
5243 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
5244 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;
5245
5246 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
5247 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;
5248 vr_hot_gpio = adev->pm.dpm.backbias_response_time;
5249 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
5250 vr_hot_gpio);
5251 }
5252
5253 ret = si_populate_smc_initial_state(adev, amdgpu_boot_state, table);
5254 if (ret)
5255 return ret;
5256
5257 ret = si_populate_smc_acpi_state(adev, table);
5258 if (ret)
5259 return ret;
5260
5261 table->driverState = table->initialState;
5262
5263 ret = si_do_program_memory_timing_parameters(adev, amdgpu_boot_state,
5264 SISLANDS_INITIAL_STATE_ARB_INDEX);
5265 if (ret)
5266 return ret;
5267
5268 if (ulv->supported && ulv->pl.vddc) {
5269 ret = si_populate_ulv_state(adev, &table->ULVState);
5270 if (ret)
5271 return ret;
5272
5273 ret = si_program_ulv_memory_timing_parameters(adev);
5274 if (ret)
5275 return ret;
5276
5277 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);
5278 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
5279
5280 lane_width = amdgpu_get_pcie_lanes(adev);
5281 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5282 } else {
5283 table->ULVState = table->initialState;
5284 }
5285
6861c837
AD		 5286 return amdgpu_si_copy_bytes_to_smc(adev, si_pi->state_table_start,
5287 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
5288 si_pi->sram_end);
841686df
MB		 5289}
5290
5291static int si_calculate_sclk_params(struct amdgpu_device *adev,
5292 u32 engine_clock,
5293 SISLANDS_SMC_SCLK_VALUE *sclk)
5294{
5295 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5296 struct si_power_info *si_pi = si_get_pi(adev);
5297 struct atom_clock_dividers dividers;
5298 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
5299 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
5300 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
5301 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
5302 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;
5303 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;
5304 u64 tmp;
5305 u32 reference_clock = adev->clock.spll.reference_freq;
5306 u32 reference_divider;
5307 u32 fbdiv;
5308 int ret;
5309
5310 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
5311 engine_clock, false, &dividers);
5312 if (ret)
5313 return ret;
5314
5315 reference_divider = 1 + dividers.ref_div;
5316
5317 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
5318 do_div(tmp, reference_clock);
5319 fbdiv = (u32) tmp;
5320
5321 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
5322 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
5323 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
5324
5325 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
5326 spll_func_cntl_2 |= SCLK_MUX_SEL(2);
5327
77d318a6
TSD		 5328 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
5329 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
5330 spll_func_cntl_3 |= SPLL_DITHEN;
841686df
MB		 5331
5332 if (pi->sclk_ss) {
5333 struct amdgpu_atom_ss ss;
5334 u32 vco_freq = engine_clock * dividers.post_div;
5335
5336 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
5337 ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
5338 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
5339 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
5340
5341 cg_spll_spread_spectrum &= ~CLK_S_MASK;
5342 cg_spll_spread_spectrum |= CLK_S(clk_s);
5343 cg_spll_spread_spectrum |= SSEN;
5344
5345 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
5346 cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
5347 }
5348 }
5349
5350 sclk->sclk_value = engine_clock;
5351 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
5352 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
5353 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
5354 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
5355 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
5356 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
5357
5358 return 0;
5359}
5360
5361static int si_populate_sclk_value(struct amdgpu_device *adev,
5362 u32 engine_clock,
5363 SISLANDS_SMC_SCLK_VALUE *sclk)
5364{
5365 SISLANDS_SMC_SCLK_VALUE sclk_tmp;
5366 int ret;
5367
5368 ret = si_calculate_sclk_params(adev, engine_clock, &sclk_tmp);
5369 if (!ret) {
5370 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
5371 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
5372 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
5373 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
5374 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
5375 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
5376 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
5377 }
5378
5379 return ret;
5380}
5381
5382static int si_populate_mclk_value(struct amdgpu_device *adev,
5383 u32 engine_clock,
5384 u32 memory_clock,
5385 SISLANDS_SMC_MCLK_VALUE *mclk,
5386 bool strobe_mode,
5387 bool dll_state_on)
5388{
5389 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5390 struct si_power_info *si_pi = si_get_pi(adev);
5391 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
5392 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
5393 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
5394 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
5395 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
5396 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
5397 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
5398 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1;
5399 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2;
5400 struct atom_mpll_param mpll_param;
5401 int ret;
5402
5403 ret = amdgpu_atombios_get_memory_pll_dividers(adev, memory_clock, strobe_mode, &mpll_param);
5404 if (ret)
5405 return ret;
5406
5407 mpll_func_cntl &= ~BWCTRL_MASK;
5408 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
5409
5410 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
5411 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
5412 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
5413
5414 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
5415 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
5416
5417 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
5418 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
5419 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
5420 YCLK_POST_DIV(mpll_param.post_div);
5421 }
5422
5423 if (pi->mclk_ss) {
5424 struct amdgpu_atom_ss ss;
5425 u32 freq_nom;
5426 u32 tmp;
5427 u32 reference_clock = adev->clock.mpll.reference_freq;
5428
5429 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
5430 freq_nom = memory_clock * 4;
5431 else
5432 freq_nom = memory_clock * 2;
5433
5434 tmp = freq_nom / reference_clock;
5435 tmp = tmp * tmp;
5436 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
77d318a6 5437 ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
841686df
MB		 5438 u32 clks = reference_clock * 5 / ss.rate;
5439 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
5440
77d318a6
TSD		 5441 mpll_ss1 &= ~CLKV_MASK;
5442 mpll_ss1 |= CLKV(clkv);
841686df 5443
77d318a6
TSD		 5444 mpll_ss2 &= ~CLKS_MASK;
5445 mpll_ss2 |= CLKS(clks);
841686df
MB		 5446 }
5447 }
5448
5449 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
5450 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
5451
5452 if (dll_state_on)
5453 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
5454 else
5455 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
5456
5457 mclk->mclk_value = cpu_to_be32(memory_clock);
5458 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
5459 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
5460 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2);
5461 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
5462 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
5463 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
5464 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
5465 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
5466 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
5467
5468 return 0;
5469}
5470
5471static void si_populate_smc_sp(struct amdgpu_device *adev,
5472 struct amdgpu_ps *amdgpu_state,
5473 SISLANDS_SMC_SWSTATE *smc_state)
5474{
5475 struct si_ps *ps = si_get_ps(amdgpu_state);
5476 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5477 int i;
5478
5479 for (i = 0; i < ps->performance_level_count - 1; i++)
5480 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
5481
5482 smc_state->levels[ps->performance_level_count - 1].bSP =
5483 cpu_to_be32(pi->psp);
5484}
5485
5486static int si_convert_power_level_to_smc(struct amdgpu_device *adev,
5487 struct rv7xx_pl *pl,
5488 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
5489{
5490 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5491 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5492 struct si_power_info *si_pi = si_get_pi(adev);
5493 int ret;
5494 bool dll_state_on;
5495 u16 std_vddc;
5496 bool gmc_pg = false;
5497
5498 if (eg_pi->pcie_performance_request &&
5499 (si_pi->force_pcie_gen != AMDGPU_PCIE_GEN_INVALID))
5500 level->gen2PCIE = (u8)si_pi->force_pcie_gen;
5501 else
5502 level->gen2PCIE = (u8)pl->pcie_gen;
5503
5504 ret = si_populate_sclk_value(adev, pl->sclk, &level->sclk);
5505 if (ret)
5506 return ret;
5507
5508 level->mcFlags = 0;
5509
5510 if (pi->mclk_stutter_mode_threshold &&
5511 (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
5512 !eg_pi->uvd_enabled &&
5513 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
5514 (adev->pm.dpm.new_active_crtc_count <= 2)) {
5515 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
5516
5517 if (gmc_pg)
5518 level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
5519 }
5520
5521 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
5522 if (pl->mclk > pi->mclk_edc_enable_threshold)
5523 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
5524
5525 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
5526 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG;
5527
5528 level->strobeMode = si_get_strobe_mode_settings(adev, pl->mclk);
5529
5530 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) {
5531 if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
5532 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
5533 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5534 else
5535 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
5536 } else {
5537 dll_state_on = false;
5538 }
5539 } else {
5540 level->strobeMode = si_get_strobe_mode_settings(adev,
5541 pl->mclk);
5542
5543 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5544 }
5545
5546 ret = si_populate_mclk_value(adev,
5547 pl->sclk,
5548 pl->mclk,
5549 &level->mclk,
5550 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on);
5551 if (ret)
5552 return ret;
5553
5554 ret = si_populate_voltage_value(adev,
5555 &eg_pi->vddc_voltage_table,
5556 pl->vddc, &level->vddc);
5557 if (ret)
5558 return ret;
5559
5560
5561 ret = si_get_std_voltage_value(adev, &level->vddc, &std_vddc);
5562 if (ret)
5563 return ret;
5564
5565 ret = si_populate_std_voltage_value(adev, std_vddc,
5566 level->vddc.index, &level->std_vddc);
5567 if (ret)
5568 return ret;
5569
5570 if (eg_pi->vddci_control) {
5571 ret = si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table,
5572 pl->vddci, &level->vddci);
5573 if (ret)
5574 return ret;
5575 }
5576
5577 if (si_pi->vddc_phase_shed_control) {
5578 ret = si_populate_phase_shedding_value(adev,
5579 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5580 pl->vddc,
5581 pl->sclk,
5582 pl->mclk,
5583 &level->vddc);
5584 if (ret)
5585 return ret;
5586 }
5587
5588 level->MaxPoweredUpCU = si_pi->max_cu;
5589
5590 ret = si_populate_mvdd_value(adev, pl->mclk, &level->mvdd);
5591
5592 return ret;
5593}
5594
5595static int si_populate_smc_t(struct amdgpu_device *adev,
5596 struct amdgpu_ps *amdgpu_state,
5597 SISLANDS_SMC_SWSTATE *smc_state)
5598{
5599 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5600 struct si_ps *state = si_get_ps(amdgpu_state);
5601 u32 a_t;
5602 u32 t_l, t_h;
5603 u32 high_bsp;
5604 int i, ret;
5605
5606 if (state->performance_level_count >= 9)
5607 return -EINVAL;
5608
5609 if (state->performance_level_count < 2) {
5610 a_t = CG_R(0xffff) | CG_L(0);
5611 smc_state->levels[0].aT = cpu_to_be32(a_t);
5612 return 0;
5613 }
5614
5615 smc_state->levels[0].aT = cpu_to_be32(0);
5616
5617 for (i = 0; i <= state->performance_level_count - 2; i++) {
5618 ret = r600_calculate_at(
5619 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1),
5620 100 * R600_AH_DFLT,
5621 state->performance_levels[i + 1].sclk,
5622 state->performance_levels[i].sclk,
5623 &t_l,
5624 &t_h);
5625
5626 if (ret) {
5627 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
5628 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
5629 }
5630
5631 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
5632 a_t |= CG_R(t_l * pi->bsp / 20000);
5633 smc_state->levels[i].aT = cpu_to_be32(a_t);
5634
5635 high_bsp = (i == state->performance_level_count - 2) ?
5636 pi->pbsp : pi->bsp;
5637 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000);
5638 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
5639 }
5640
5641 return 0;
5642}
5643
5644static int si_disable_ulv(struct amdgpu_device *adev)
5645{
5646 struct si_power_info *si_pi = si_get_pi(adev);
5647 struct si_ulv_param *ulv = &si_pi->ulv;
5648
5649 if (ulv->supported)
6861c837 5650 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
841686df
MB		 5651 0 : -EINVAL;
5652
5653 return 0;
5654}
5655
5656static bool si_is_state_ulv_compatible(struct amdgpu_device *adev,
5657 struct amdgpu_ps *amdgpu_state)
5658{
5659 const struct si_power_info *si_pi = si_get_pi(adev);
5660 const struct si_ulv_param *ulv = &si_pi->ulv;
5661 const struct si_ps *state = si_get_ps(amdgpu_state);
5662 int i;
5663
5664 if (state->performance_levels[0].mclk != ulv->pl.mclk)
5665 return false;
5666
5667 /* XXX validate against display requirements! */
5668
5669 for (i = 0; i < adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
5670 if (adev->clock.current_dispclk <=
5671 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
5672 if (ulv->pl.vddc <
5673 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
5674 return false;
5675 }
5676 }
5677
5678 if ((amdgpu_state->vclk != 0) || (amdgpu_state->dclk != 0))
5679 return false;
5680
5681 return true;
5682}
5683
5684static int si_set_power_state_conditionally_enable_ulv(struct amdgpu_device *adev,
5685 struct amdgpu_ps *amdgpu_new_state)
5686{
5687 const struct si_power_info *si_pi = si_get_pi(adev);
5688 const struct si_ulv_param *ulv = &si_pi->ulv;
5689
5690 if (ulv->supported) {
5691 if (si_is_state_ulv_compatible(adev, amdgpu_new_state))
6861c837 5692 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
841686df
MB		 5693 0 : -EINVAL;
5694 }
5695 return 0;
5696}
5697
5698static int si_convert_power_state_to_smc(struct amdgpu_device *adev,
5699 struct amdgpu_ps *amdgpu_state,
5700 SISLANDS_SMC_SWSTATE *smc_state)
5701{
5702 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5703 struct ni_power_info *ni_pi = ni_get_pi(adev);
5704 struct si_power_info *si_pi = si_get_pi(adev);
5705 struct si_ps *state = si_get_ps(amdgpu_state);
5706 int i, ret;
5707 u32 threshold;
5708 u32 sclk_in_sr = 1350; /* ??? */
5709
5710 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
5711 return -EINVAL;
5712
5713 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
5714
5715 if (amdgpu_state->vclk && amdgpu_state->dclk) {
5716 eg_pi->uvd_enabled = true;
5717 if (eg_pi->smu_uvd_hs)
5718 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;
5719 } else {
5720 eg_pi->uvd_enabled = false;
5721 }
5722
5723 if (state->dc_compatible)
5724 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
5725
5726 smc_state->levelCount = 0;
5727 for (i = 0; i < state->performance_level_count; i++) {
5728 if (eg_pi->sclk_deep_sleep) {
5729 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {
5730 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5731 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5732 else
5733 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5734 }
5735 }
5736
5737 ret = si_convert_power_level_to_smc(adev, &state->performance_levels[i],
5738 &smc_state->levels[i]);
5739 smc_state->levels[i].arbRefreshState =
5740 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);
5741
5742 if (ret)
5743 return ret;
5744
5745 if (ni_pi->enable_power_containment)
5746 smc_state->levels[i].displayWatermark =
5747 (state->performance_levels[i].sclk < threshold) ?
5748 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5749 else
5750 smc_state->levels[i].displayWatermark = (i < 2) ?
5751 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5752
5753 if (eg_pi->dynamic_ac_timing)
5754 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
5755 else
5756 smc_state->levels[i].ACIndex = 0;
5757
5758 smc_state->levelCount++;
5759 }
5760
5761 si_write_smc_soft_register(adev,
5762 SI_SMC_SOFT_REGISTER_watermark_threshold,
5763 threshold / 512);
5764
5765 si_populate_smc_sp(adev, amdgpu_state, smc_state);
5766
5767 ret = si_populate_power_containment_values(adev, amdgpu_state, smc_state);
5768 if (ret)
5769 ni_pi->enable_power_containment = false;
5770
5771 ret = si_populate_sq_ramping_values(adev, amdgpu_state, smc_state);
77d318a6 5772 if (ret)
841686df
MB		 5773 ni_pi->enable_sq_ramping = false;
5774
5775 return si_populate_smc_t(adev, amdgpu_state, smc_state);
5776}
5777
5778static int si_upload_sw_state(struct amdgpu_device *adev,
5779 struct amdgpu_ps *amdgpu_new_state)
5780{
5781 struct si_power_info *si_pi = si_get_pi(adev);
5782 struct si_ps *new_state = si_get_ps(amdgpu_new_state);
5783 int ret;
5784 u32 address = si_pi->state_table_start +
5785 offsetof(SISLANDS_SMC_STATETABLE, driverState);
5786 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) +
5787 ((new_state->performance_level_count - 1) *
5788 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL));
5789 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
5790
5791 memset(smc_state, 0, state_size);
5792
5793 ret = si_convert_power_state_to_smc(adev, amdgpu_new_state, smc_state);
5794 if (ret)
5795 return ret;
5796
6861c837
AD		 5797 return amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
5798 state_size, si_pi->sram_end);
841686df
MB		 5799}
5800
5801static int si_upload_ulv_state(struct amdgpu_device *adev)
5802{
5803 struct si_power_info *si_pi = si_get_pi(adev);
5804 struct si_ulv_param *ulv = &si_pi->ulv;
5805 int ret = 0;
5806
5807 if (ulv->supported && ulv->pl.vddc) {
5808 u32 address = si_pi->state_table_start +
5809 offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5810 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;
5811 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE);
5812
5813 memset(smc_state, 0, state_size);
5814
5815 ret = si_populate_ulv_state(adev, smc_state);
5816 if (!ret)
6861c837
AD		 5817 ret = amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
5818 state_size, si_pi->sram_end);
841686df
MB		 5819 }
5820
5821 return ret;
5822}
5823
5824static int si_upload_smc_data(struct amdgpu_device *adev)
5825{
5826 struct amdgpu_crtc *amdgpu_crtc = NULL;
5827 int i;
5828
5829 if (adev->pm.dpm.new_active_crtc_count == 0)
5830 return 0;
5831
5832 for (i = 0; i < adev->mode_info.num_crtc; i++) {
5833 if (adev->pm.dpm.new_active_crtcs & (1 << i)) {
5834 amdgpu_crtc = adev->mode_info.crtcs[i];
5835 break;
5836 }
5837 }
5838
5839 if (amdgpu_crtc == NULL)
5840 return 0;
5841
5842 if (amdgpu_crtc->line_time <= 0)
5843 return 0;
5844
5845 if (si_write_smc_soft_register(adev,
5846 SI_SMC_SOFT_REGISTER_crtc_index,
5847 amdgpu_crtc->crtc_id) != PPSMC_Result_OK)
5848 return 0;
5849
5850 if (si_write_smc_soft_register(adev,
5851 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
5852 amdgpu_crtc->wm_high / amdgpu_crtc->line_time) != PPSMC_Result_OK)
5853 return 0;
5854
5855 if (si_write_smc_soft_register(adev,
5856 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
5857 amdgpu_crtc->wm_low / amdgpu_crtc->line_time) != PPSMC_Result_OK)
5858 return 0;
5859
5860 return 0;
5861}
5862
5863static int si_set_mc_special_registers(struct amdgpu_device *adev,
5864 struct si_mc_reg_table *table)
5865{
5866 u8 i, j, k;
5867 u32 temp_reg;
5868
5869 for (i = 0, j = table->last; i < table->last; i++) {
5870 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5871 return -EINVAL;
5872 switch (table->mc_reg_address[i].s1) {
5873 case MC_SEQ_MISC1:
5874 temp_reg = RREG32(MC_PMG_CMD_EMRS);
5875 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS;
5876 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP;
5877 for (k = 0; k < table->num_entries; k++)
5878 table->mc_reg_table_entry[k].mc_data[j] =
5879 ((temp_reg & 0xffff0000)) |
5880 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
5881 j++;
5882 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5883 return -EINVAL;
5884
5885 temp_reg = RREG32(MC_PMG_CMD_MRS);
5886 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS;
5887 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP;
5888 for (k = 0; k < table->num_entries; k++) {
5889 table->mc_reg_table_entry[k].mc_data[j] =
5890 (temp_reg & 0xffff0000) |
5891 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5892 if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5)
5893 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5894 }
5895 j++;
5896 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5897 return -EINVAL;
5898
5899 if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) {
5900 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD;
5901 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD;
5902 for (k = 0; k < table->num_entries; k++)
5903 table->mc_reg_table_entry[k].mc_data[j] =
5904 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5905 j++;
5906 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5907 return -EINVAL;
5908 }
5909 break;
5910 case MC_SEQ_RESERVE_M:
5911 temp_reg = RREG32(MC_PMG_CMD_MRS1);
5912 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1;
5913 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP;
5914 for(k = 0; k < table->num_entries; k++)
5915 table->mc_reg_table_entry[k].mc_data[j] =
5916 (temp_reg & 0xffff0000) |
5917 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5918 j++;
5919 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5920 return -EINVAL;
5921 break;
5922 default:
5923 break;
5924 }
5925 }
5926
5927 table->last = j;
5928
5929 return 0;
5930}
5931
5932static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
5933{
5934 bool result = true;
5935 switch (in_reg) {
5936 case MC_SEQ_RAS_TIMING:
5937 *out_reg = MC_SEQ_RAS_TIMING_LP;
5938 break;
77d318a6 5939 case MC_SEQ_CAS_TIMING:
841686df
MB		 5940 *out_reg = MC_SEQ_CAS_TIMING_LP;
5941 break;
77d318a6 5942 case MC_SEQ_MISC_TIMING:
841686df
MB		 5943 *out_reg = MC_SEQ_MISC_TIMING_LP;
5944 break;
77d318a6 5945 case MC_SEQ_MISC_TIMING2:
841686df
MB		 5946 *out_reg = MC_SEQ_MISC_TIMING2_LP;
5947 break;
77d318a6 5948 case MC_SEQ_RD_CTL_D0:
841686df
MB		 5949 *out_reg = MC_SEQ_RD_CTL_D0_LP;
5950 break;
77d318a6 5951 case MC_SEQ_RD_CTL_D1:
841686df
MB		 5952 *out_reg = MC_SEQ_RD_CTL_D1_LP;
5953 break;
77d318a6 5954 case MC_SEQ_WR_CTL_D0:
841686df
MB		 5955 *out_reg = MC_SEQ_WR_CTL_D0_LP;
5956 break;
77d318a6 5957 case MC_SEQ_WR_CTL_D1:
841686df
MB		 5958 *out_reg = MC_SEQ_WR_CTL_D1_LP;
5959 break;
77d318a6 5960 case MC_PMG_CMD_EMRS:
841686df
MB		 5961 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP;
5962 break;
77d318a6 5963 case MC_PMG_CMD_MRS:
841686df
MB		 5964 *out_reg = MC_SEQ_PMG_CMD_MRS_LP;
5965 break;
77d318a6 5966 case MC_PMG_CMD_MRS1:
841686df
MB		 5967 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP;
5968 break;
77d318a6 5969 case MC_SEQ_PMG_TIMING:
841686df
MB		 5970 *out_reg = MC_SEQ_PMG_TIMING_LP;
5971 break;
77d318a6 5972 case MC_PMG_CMD_MRS2:
841686df
MB		 5973 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP;
5974 break;
77d318a6 5975 case MC_SEQ_WR_CTL_2:
841686df
MB		 5976 *out_reg = MC_SEQ_WR_CTL_2_LP;
5977 break;
77d318a6 5978 default:
841686df
MB		 5979 result = false;
5980 break;
5981 }
5982
5983 return result;
5984}
5985
5986static void si_set_valid_flag(struct si_mc_reg_table *table)
5987{
5988 u8 i, j;
5989
5990 for (i = 0; i < table->last; i++) {
5991 for (j = 1; j < table->num_entries; j++) {
5992 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
5993 table->valid_flag |= 1 << i;
5994 break;
5995 }
5996 }
5997 }
5998}
5999
6000static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
6001{
6002 u32 i;
6003 u16 address;
6004
6005 for (i = 0; i < table->last; i++)
6006 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
6007 address : table->mc_reg_address[i].s1;
6008
6009}
6010
6011static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
6012 struct si_mc_reg_table *si_table)
6013{
6014 u8 i, j;
6015
6016 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
6017 return -EINVAL;
6018 if (table->num_entries > MAX_AC_TIMING_ENTRIES)
6019 return -EINVAL;
6020
6021 for (i = 0; i < table->last; i++)
6022 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
6023 si_table->last = table->last;
6024
6025 for (i = 0; i < table->num_entries; i++) {
6026 si_table->mc_reg_table_entry[i].mclk_max =
6027 table->mc_reg_table_entry[i].mclk_max;
6028 for (j = 0; j < table->last; j++) {
6029 si_table->mc_reg_table_entry[i].mc_data[j] =
6030 table->mc_reg_table_entry[i].mc_data[j];
6031 }
6032 }
6033 si_table->num_entries = table->num_entries;
6034
6035 return 0;
6036}
6037
6038static int si_initialize_mc_reg_table(struct amdgpu_device *adev)
6039{
6040 struct si_power_info *si_pi = si_get_pi(adev);
6041 struct atom_mc_reg_table *table;
6042 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;
6043 u8 module_index = rv770_get_memory_module_index(adev);
6044 int ret;
6045
6046 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
6047 if (!table)
6048 return -ENOMEM;
6049
6050 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
6051 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
6052 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
6053 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
6054 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
6055 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
6056 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
6057 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
6058 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
6059 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
6060 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
6061 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
6062 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
6063 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
6064
77d318a6
TSD		 6065 ret = amdgpu_atombios_init_mc_reg_table(adev, module_index, table);
6066 if (ret)
6067 goto init_mc_done;
841686df 6068
77d318a6
TSD		 6069 ret = si_copy_vbios_mc_reg_table(table, si_table);
6070 if (ret)
6071 goto init_mc_done;
841686df
MB		 6072
6073 si_set_s0_mc_reg_index(si_table);
6074
6075 ret = si_set_mc_special_registers(adev, si_table);
77d318a6
TSD		 6076 if (ret)
6077 goto init_mc_done;
841686df
MB		 6078
6079 si_set_valid_flag(si_table);
6080
6081init_mc_done:
6082 kfree(table);
6083
6084 return ret;
6085
6086}
6087
6088static void si_populate_mc_reg_addresses(struct amdgpu_device *adev,
6089 SMC_SIslands_MCRegisters *mc_reg_table)
6090{
6091 struct si_power_info *si_pi = si_get_pi(adev);
6092 u32 i, j;
6093
6094 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
6095 if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
6096 if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
6097 break;
6098 mc_reg_table->address[i].s0 =
6099 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
6100 mc_reg_table->address[i].s1 =
6101 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);
6102 i++;
6103 }
6104 }
6105 mc_reg_table->last = (u8)i;
6106}
6107
6108static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
6109 SMC_SIslands_MCRegisterSet *data,
6110 u32 num_entries, u32 valid_flag)
6111{
6112 u32 i, j;
6113
6114 for(i = 0, j = 0; j < num_entries; j++) {
6115 if (valid_flag & (1 << j)) {
6116 data->value[i] = cpu_to_be32(entry->mc_data[j]);
6117 i++;
6118 }
6119 }
6120}
6121
6122static void si_convert_mc_reg_table_entry_to_smc(struct amdgpu_device *adev,
6123 struct rv7xx_pl *pl,
6124 SMC_SIslands_MCRegisterSet *mc_reg_table_data)
6125{
6126 struct si_power_info *si_pi = si_get_pi(adev);
6127 u32 i = 0;
6128
6129 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {
6130 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
6131 break;
6132 }
6133
6134 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))
6135 --i;
6136
6137 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],
6138 mc_reg_table_data, si_pi->mc_reg_table.last,
6139 si_pi->mc_reg_table.valid_flag);
6140}
6141
6142static void si_convert_mc_reg_table_to_smc(struct amdgpu_device *adev,
6143 struct amdgpu_ps *amdgpu_state,
6144 SMC_SIslands_MCRegisters *mc_reg_table)
6145{
77d318a6 6146 struct si_ps *state = si_get_ps(amdgpu_state);
841686df
MB		 6147 int i;
6148
6149 for (i = 0; i < state->performance_level_count; i++) {
6150 si_convert_mc_reg_table_entry_to_smc(adev,
6151 &state->performance_levels[i],
6152 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
6153 }
6154}
6155
6156static int si_populate_mc_reg_table(struct amdgpu_device *adev,
6157 struct amdgpu_ps *amdgpu_boot_state)
6158{
6159 struct si_ps *boot_state = si_get_ps(amdgpu_boot_state);
6160 struct si_power_info *si_pi = si_get_pi(adev);
6161 struct si_ulv_param *ulv = &si_pi->ulv;
6162 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
6163
6164 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
6165
6166 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_seq_index, 1);
6167
6168 si_populate_mc_reg_addresses(adev, smc_mc_reg_table);
6169
6170 si_convert_mc_reg_table_entry_to_smc(adev, &boot_state->performance_levels[0],
6171 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]);
6172
6173 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
6174 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT],
6175 si_pi->mc_reg_table.last,
6176 si_pi->mc_reg_table.valid_flag);
6177
6178 if (ulv->supported && ulv->pl.vddc != 0)
6179 si_convert_mc_reg_table_entry_to_smc(adev, &ulv->pl,
6180 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]);
6181 else
6182 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
6183 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT],
6184 si_pi->mc_reg_table.last,
6185 si_pi->mc_reg_table.valid_flag);
6186
6187 si_convert_mc_reg_table_to_smc(adev, amdgpu_boot_state, smc_mc_reg_table);
6188
6861c837
AD		 6189 return amdgpu_si_copy_bytes_to_smc(adev, si_pi->mc_reg_table_start,
6190 (u8 *)smc_mc_reg_table,
6191 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
841686df
MB		 6192}
6193
6194static int si_upload_mc_reg_table(struct amdgpu_device *adev,
6195 struct amdgpu_ps *amdgpu_new_state)
6196{
77d318a6 6197 struct si_ps *new_state = si_get_ps(amdgpu_new_state);
841686df
MB		 6198 struct si_power_info *si_pi = si_get_pi(adev);
6199 u32 address = si_pi->mc_reg_table_start +
6200 offsetof(SMC_SIslands_MCRegisters,
6201 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
6202 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
6203
6204 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
6205
6206 si_convert_mc_reg_table_to_smc(adev, amdgpu_new_state, smc_mc_reg_table);
6207
6861c837
AD		 6208 return amdgpu_si_copy_bytes_to_smc(adev, address,
6209 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
6210 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
6211 si_pi->sram_end);
841686df
MB		 6212}
6213
6214static void si_enable_voltage_control(struct amdgpu_device *adev, bool enable)
6215{
77d318a6
TSD		 6216 if (enable)
6217 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
6218 else
6219 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
841686df
MB		 6220}
6221
6222static enum amdgpu_pcie_gen si_get_maximum_link_speed(struct amdgpu_device *adev,
6223 struct amdgpu_ps *amdgpu_state)
6224{
77d318a6 6225 struct si_ps *state = si_get_ps(amdgpu_state);
841686df
MB		 6226 int i;
6227 u16 pcie_speed, max_speed = 0;
6228
6229 for (i = 0; i < state->performance_level_count; i++) {
6230 pcie_speed = state->performance_levels[i].pcie_gen;
6231 if (max_speed < pcie_speed)
6232 max_speed = pcie_speed;
6233 }
6234 return max_speed;
6235}
6236
6237static u16 si_get_current_pcie_speed(struct amdgpu_device *adev)
6238{
6239 u32 speed_cntl;
6240
6241 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
6242 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
6243
6244 return (u16)speed_cntl;
6245}
6246
6247static void si_request_link_speed_change_before_state_change(struct amdgpu_device *adev,
6248 struct amdgpu_ps *amdgpu_new_state,
6249 struct amdgpu_ps *amdgpu_current_state)
6250{
6251 struct si_power_info *si_pi = si_get_pi(adev);
6252 enum amdgpu_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state);
6253 enum amdgpu_pcie_gen current_link_speed;
6254
6255 if (si_pi->force_pcie_gen == AMDGPU_PCIE_GEN_INVALID)
6256 current_link_speed = si_get_maximum_link_speed(adev, amdgpu_current_state);
6257 else
6258 current_link_speed = si_pi->force_pcie_gen;
6259
6260 si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
6261 si_pi->pspp_notify_required = false;
6262 if (target_link_speed > current_link_speed) {
6263 switch (target_link_speed) {
6264#if defined(CONFIG_ACPI)
6265 case AMDGPU_PCIE_GEN3:
6266 if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
6267 break;
6268 si_pi->force_pcie_gen = AMDGPU_PCIE_GEN2;
6269 if (current_link_speed == AMDGPU_PCIE_GEN2)
6270 break;
6271 case AMDGPU_PCIE_GEN2:
6272 if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
6273 break;
6274#endif
6275 default:
6276 si_pi->force_pcie_gen = si_get_current_pcie_speed(adev);
6277 break;
6278 }
6279 } else {
6280 if (target_link_speed < current_link_speed)
6281 si_pi->pspp_notify_required = true;
6282 }
6283}
6284
6285static void si_notify_link_speed_change_after_state_change(struct amdgpu_device *adev,
6286 struct amdgpu_ps *amdgpu_new_state,
6287 struct amdgpu_ps *amdgpu_current_state)
6288{
6289 struct si_power_info *si_pi = si_get_pi(adev);
6290 enum amdgpu_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state);
6291 u8 request;
6292
6293 if (si_pi->pspp_notify_required) {
6294 if (target_link_speed == AMDGPU_PCIE_GEN3)
6295 request = PCIE_PERF_REQ_PECI_GEN3;
6296 else if (target_link_speed == AMDGPU_PCIE_GEN2)
6297 request = PCIE_PERF_REQ_PECI_GEN2;
6298 else
6299 request = PCIE_PERF_REQ_PECI_GEN1;
6300
6301 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
6302 (si_get_current_pcie_speed(adev) > 0))
6303 return;
6304
6305#if defined(CONFIG_ACPI)
6306 amdgpu_acpi_pcie_performance_request(adev, request, false);
6307#endif
6308 }
6309}
6310
6311#if 0
6312static int si_ds_request(struct amdgpu_device *adev,
6313 bool ds_status_on, u32 count_write)
6314{
6315 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6316
6317 if (eg_pi->sclk_deep_sleep) {
6318 if (ds_status_on)
6861c837 6319 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
841686df
MB		 6320 PPSMC_Result_OK) ?
6321 0 : -EINVAL;
6322 else
6861c837 6323 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
841686df
MB		 6324 PPSMC_Result_OK) ? 0 : -EINVAL;
6325 }
6326 return 0;
6327}
6328#endif
6329
6330static void si_set_max_cu_value(struct amdgpu_device *adev)
6331{
6332 struct si_power_info *si_pi = si_get_pi(adev);
6333
6334 if (adev->asic_type == CHIP_VERDE) {
6335 switch (adev->pdev->device) {
6336 case 0x6820:
6337 case 0x6825:
6338 case 0x6821:
6339 case 0x6823:
6340 case 0x6827:
6341 si_pi->max_cu = 10;
6342 break;
6343 case 0x682D:
6344 case 0x6824:
6345 case 0x682F:
6346 case 0x6826:
6347 si_pi->max_cu = 8;
6348 break;
6349 case 0x6828:
6350 case 0x6830:
6351 case 0x6831:
6352 case 0x6838:
6353 case 0x6839:
6354 case 0x683D:
6355 si_pi->max_cu = 10;
6356 break;
6357 case 0x683B:
6358 case 0x683F:
6359 case 0x6829:
6360 si_pi->max_cu = 8;
6361 break;
6362 default:
6363 si_pi->max_cu = 0;
6364 break;
6365 }
6366 } else {
6367 si_pi->max_cu = 0;
6368 }
6369}
6370
6371static int si_patch_single_dependency_table_based_on_leakage(struct amdgpu_device *adev,
6372 struct amdgpu_clock_voltage_dependency_table *table)
6373{
6374 u32 i;
6375 int j;
6376 u16 leakage_voltage;
6377
6378 if (table) {
6379 for (i = 0; i < table->count; i++) {
6380 switch (si_get_leakage_voltage_from_leakage_index(adev,
6381 table->entries[i].v,
6382 &leakage_voltage)) {
6383 case 0:
6384 table->entries[i].v = leakage_voltage;
6385 break;
6386 case -EAGAIN:
6387 return -EINVAL;
6388 case -EINVAL:
6389 default:
6390 break;
6391 }
6392 }
6393
6394 for (j = (table->count - 2); j >= 0; j--) {
6395 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
6396 table->entries[j].v : table->entries[j + 1].v;
6397 }
6398 }
6399 return 0;
6400}
6401
6402static int si_patch_dependency_tables_based_on_leakage(struct amdgpu_device *adev)
6403{
6404 int ret = 0;
6405
6406 ret = si_patch_single_dependency_table_based_on_leakage(adev,
6407 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
ad2473af
TSD		 6408 if (ret)
6409 DRM_ERROR("Could not patch vddc_on_sclk leakage table\n");
841686df
MB		 6410 ret = si_patch_single_dependency_table_based_on_leakage(adev,
6411 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
ad2473af
TSD		 6412 if (ret)
6413 DRM_ERROR("Could not patch vddc_on_mclk leakage table\n");
841686df
MB		 6414 ret = si_patch_single_dependency_table_based_on_leakage(adev,
6415 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
ad2473af
TSD		 6416 if (ret)
6417 DRM_ERROR("Could not patch vddci_on_mclk leakage table\n");
841686df
MB		 6418 return ret;
6419}
6420
6421static void si_set_pcie_lane_width_in_smc(struct amdgpu_device *adev,
6422 struct amdgpu_ps *amdgpu_new_state,
6423 struct amdgpu_ps *amdgpu_current_state)
6424{
6425 u32 lane_width;
6426 u32 new_lane_width =
6427 (amdgpu_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
6428 u32 current_lane_width =
6429 (amdgpu_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
6430
6431 if (new_lane_width != current_lane_width) {
6432 amdgpu_set_pcie_lanes(adev, new_lane_width);
6433 lane_width = amdgpu_get_pcie_lanes(adev);
6434 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
6435 }
6436}
6437
6438static void si_dpm_setup_asic(struct amdgpu_device *adev)
6439{
6440 si_read_clock_registers(adev);
6441 si_enable_acpi_power_management(adev);
6442}
6443
6444static int si_thermal_enable_alert(struct amdgpu_device *adev,
6445 bool enable)
6446{
6447 u32 thermal_int = RREG32(CG_THERMAL_INT);
6448
6449 if (enable) {
6450 PPSMC_Result result;
6451
6452 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
6453 WREG32(CG_THERMAL_INT, thermal_int);
6861c837 6454 result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
841686df
MB		 6455 if (result != PPSMC_Result_OK) {
6456 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
6457 return -EINVAL;
6458 }
6459 } else {
6460 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
6461 WREG32(CG_THERMAL_INT, thermal_int);
6462 }
6463
6464 return 0;
6465}
6466
6467static int si_thermal_set_temperature_range(struct amdgpu_device *adev,
6468 int min_temp, int max_temp)
6469{
6470 int low_temp = 0 * 1000;
6471 int high_temp = 255 * 1000;
6472
6473 if (low_temp < min_temp)
6474 low_temp = min_temp;
6475 if (high_temp > max_temp)
6476 high_temp = max_temp;
6477 if (high_temp < low_temp) {
6478 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
6479 return -EINVAL;
6480 }
6481
6482 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
6483 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
6484 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
6485
6486 adev->pm.dpm.thermal.min_temp = low_temp;
6487 adev->pm.dpm.thermal.max_temp = high_temp;
6488
6489 return 0;
6490}
6491
6492static void si_fan_ctrl_set_static_mode(struct amdgpu_device *adev, u32 mode)
6493{
6494 struct si_power_info *si_pi = si_get_pi(adev);
6495 u32 tmp;
6496
6497 if (si_pi->fan_ctrl_is_in_default_mode) {
6498 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
6499 si_pi->fan_ctrl_default_mode = tmp;
6500 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
6501 si_pi->t_min = tmp;
6502 si_pi->fan_ctrl_is_in_default_mode = false;
6503 }
6504
6505 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6506 tmp |= TMIN(0);
6507 WREG32(CG_FDO_CTRL2, tmp);
6508
6509 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6510 tmp |= FDO_PWM_MODE(mode);
6511 WREG32(CG_FDO_CTRL2, tmp);
6512}
6513
6514static int si_thermal_setup_fan_table(struct amdgpu_device *adev)
6515{
6516 struct si_power_info *si_pi = si_get_pi(adev);
6517 PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE };
6518 u32 duty100;
6519 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
6520 u16 fdo_min, slope1, slope2;
6521 u32 reference_clock, tmp;
6522 int ret;
6523 u64 tmp64;
6524
6525 if (!si_pi->fan_table_start) {
6526 adev->pm.dpm.fan.ucode_fan_control = false;
6527 return 0;
6528 }
6529
6530 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6531
6532 if (duty100 == 0) {
6533 adev->pm.dpm.fan.ucode_fan_control = false;
6534 return 0;
6535 }
6536
6537 tmp64 = (u64)adev->pm.dpm.fan.pwm_min * duty100;
6538 do_div(tmp64, 10000);
6539 fdo_min = (u16)tmp64;
6540
6541 t_diff1 = adev->pm.dpm.fan.t_med - adev->pm.dpm.fan.t_min;
6542 t_diff2 = adev->pm.dpm.fan.t_high - adev->pm.dpm.fan.t_med;
6543
6544 pwm_diff1 = adev->pm.dpm.fan.pwm_med - adev->pm.dpm.fan.pwm_min;
6545 pwm_diff2 = adev->pm.dpm.fan.pwm_high - adev->pm.dpm.fan.pwm_med;
6546
6547 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
6548 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
6549
6550 fan_table.temp_min = cpu_to_be16((50 + adev->pm.dpm.fan.t_min) / 100);
6551 fan_table.temp_med = cpu_to_be16((50 + adev->pm.dpm.fan.t_med) / 100);
6552 fan_table.temp_max = cpu_to_be16((50 + adev->pm.dpm.fan.t_max) / 100);
841686df
MB		 6553 fan_table.slope1 = cpu_to_be16(slope1);
6554 fan_table.slope2 = cpu_to_be16(slope2);
841686df 6555 fan_table.fdo_min = cpu_to_be16(fdo_min);
841686df 6556 fan_table.hys_down = cpu_to_be16(adev->pm.dpm.fan.t_hyst);
841686df 6557 fan_table.hys_up = cpu_to_be16(1);
841686df 6558 fan_table.hys_slope = cpu_to_be16(1);
841686df 6559 fan_table.temp_resp_lim = cpu_to_be16(5);
841686df
MB		 6560 reference_clock = amdgpu_asic_get_xclk(adev);
6561
6562 fan_table.refresh_period = cpu_to_be32((adev->pm.dpm.fan.cycle_delay *
6563 reference_clock) / 1600);
841686df
MB		 6564 fan_table.fdo_max = cpu_to_be16((u16)duty100);
6565
6566 tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
6567 fan_table.temp_src = (uint8_t)tmp;
6568
6861c837
AD		 6569 ret = amdgpu_si_copy_bytes_to_smc(adev,
6570 si_pi->fan_table_start,
6571 (u8 *)(&fan_table),
6572 sizeof(fan_table),
6573 si_pi->sram_end);
841686df
MB		 6574
6575 if (ret) {
6576 DRM_ERROR("Failed to load fan table to the SMC.");
6577 adev->pm.dpm.fan.ucode_fan_control = false;
6578 }
6579
ad2473af 6580 return ret;
841686df
MB		 6581}
6582
6583static int si_fan_ctrl_start_smc_fan_control(struct amdgpu_device *adev)
6584{
6585 struct si_power_info *si_pi = si_get_pi(adev);
6586 PPSMC_Result ret;
6587
6861c837 6588 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StartFanControl);
841686df
MB		 6589 if (ret == PPSMC_Result_OK) {
6590 si_pi->fan_is_controlled_by_smc = true;
6591 return 0;
6592 } else {
6593 return -EINVAL;
6594 }
6595}
6596
6597static int si_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev)
6598{
6599 struct si_power_info *si_pi = si_get_pi(adev);
6600 PPSMC_Result ret;
6601
6861c837 6602 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StopFanControl);
841686df
MB		 6603
6604 if (ret == PPSMC_Result_OK) {
6605 si_pi->fan_is_controlled_by_smc = false;
6606 return 0;
6607 } else {
6608 return -EINVAL;
6609 }
6610}
6611
6612static int si_dpm_get_fan_speed_percent(struct amdgpu_device *adev,
6613 u32 *speed)
6614{
6615 u32 duty, duty100;
6616 u64 tmp64;
6617
6618 if (adev->pm.no_fan)
6619 return -ENOENT;
6620
6621 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6622 duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;
6623
6624 if (duty100 == 0)
6625 return -EINVAL;
6626
6627 tmp64 = (u64)duty * 100;
6628 do_div(tmp64, duty100);
6629 *speed = (u32)tmp64;
6630
6631 if (*speed > 100)
6632 *speed = 100;
6633
6634 return 0;
6635}
6636
6637static int si_dpm_set_fan_speed_percent(struct amdgpu_device *adev,
6638 u32 speed)
6639{
6640 struct si_power_info *si_pi = si_get_pi(adev);
6641 u32 tmp;
6642 u32 duty, duty100;
6643 u64 tmp64;
6644
6645 if (adev->pm.no_fan)
6646 return -ENOENT;
6647
6648 if (si_pi->fan_is_controlled_by_smc)
6649 return -EINVAL;
6650
6651 if (speed > 100)
6652 return -EINVAL;
6653
6654 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6655
6656 if (duty100 == 0)
6657 return -EINVAL;
6658
6659 tmp64 = (u64)speed * duty100;
6660 do_div(tmp64, 100);
6661 duty = (u32)tmp64;
6662
6663 tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
6664 tmp |= FDO_STATIC_DUTY(duty);
6665 WREG32(CG_FDO_CTRL0, tmp);
6666
6667 return 0;
6668}
6669
6670static void si_dpm_set_fan_control_mode(struct amdgpu_device *adev, u32 mode)
6671{
6672 if (mode) {
6673 /* stop auto-manage */
6674 if (adev->pm.dpm.fan.ucode_fan_control)
6675 si_fan_ctrl_stop_smc_fan_control(adev);
6676 si_fan_ctrl_set_static_mode(adev, mode);
6677 } else {
6678 /* restart auto-manage */
6679 if (adev->pm.dpm.fan.ucode_fan_control)
6680 si_thermal_start_smc_fan_control(adev);
6681 else
6682 si_fan_ctrl_set_default_mode(adev);
6683 }
6684}
6685
6686static u32 si_dpm_get_fan_control_mode(struct amdgpu_device *adev)
6687{
6688 struct si_power_info *si_pi = si_get_pi(adev);
6689 u32 tmp;
6690
6691 if (si_pi->fan_is_controlled_by_smc)
6692 return 0;
6693
6694 tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
6695 return (tmp >> FDO_PWM_MODE_SHIFT);
6696}
6697
6698#if 0
6699static int si_fan_ctrl_get_fan_speed_rpm(struct amdgpu_device *adev,
6700 u32 *speed)
6701{
6702 u32 tach_period;
6703 u32 xclk = amdgpu_asic_get_xclk(adev);
6704
6705 if (adev->pm.no_fan)
6706 return -ENOENT;
6707
6708 if (adev->pm.fan_pulses_per_revolution == 0)
6709 return -ENOENT;
6710
6711 tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
6712 if (tach_period == 0)
6713 return -ENOENT;
6714
6715 *speed = 60 * xclk * 10000 / tach_period;
6716
6717 return 0;
6718}
6719
6720static int si_fan_ctrl_set_fan_speed_rpm(struct amdgpu_device *adev,
6721 u32 speed)
6722{
6723 u32 tach_period, tmp;
6724 u32 xclk = amdgpu_asic_get_xclk(adev);
6725
6726 if (adev->pm.no_fan)
6727 return -ENOENT;
6728
6729 if (adev->pm.fan_pulses_per_revolution == 0)
6730 return -ENOENT;
6731
6732 if ((speed < adev->pm.fan_min_rpm) ||
6733 (speed > adev->pm.fan_max_rpm))
6734 return -EINVAL;
6735
6736 if (adev->pm.dpm.fan.ucode_fan_control)
6737 si_fan_ctrl_stop_smc_fan_control(adev);
6738
6739 tach_period = 60 * xclk * 10000 / (8 * speed);
6740 tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
6741 tmp |= TARGET_PERIOD(tach_period);
6742 WREG32(CG_TACH_CTRL, tmp);
6743
6744 si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC_RPM);
6745
6746 return 0;
6747}
6748#endif
6749
6750static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev)
6751{
6752 struct si_power_info *si_pi = si_get_pi(adev);
6753 u32 tmp;
6754
6755 if (!si_pi->fan_ctrl_is_in_default_mode) {
6756 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6757 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode);
6758 WREG32(CG_FDO_CTRL2, tmp);
6759
6760 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6761 tmp |= TMIN(si_pi->t_min);
6762 WREG32(CG_FDO_CTRL2, tmp);
6763 si_pi->fan_ctrl_is_in_default_mode = true;
6764 }
6765}
6766
6767static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev)
6768{
6769 if (adev->pm.dpm.fan.ucode_fan_control) {
6770 si_fan_ctrl_start_smc_fan_control(adev);
6771 si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC);
6772 }
6773}
6774
6775static void si_thermal_initialize(struct amdgpu_device *adev)
6776{
6777 u32 tmp;
6778
6779 if (adev->pm.fan_pulses_per_revolution) {
6780 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
6781 tmp |= EDGE_PER_REV(adev->pm.fan_pulses_per_revolution -1);
6782 WREG32(CG_TACH_CTRL, tmp);
6783 }
6784
6785 tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
6786 tmp |= TACH_PWM_RESP_RATE(0x28);
6787 WREG32(CG_FDO_CTRL2, tmp);
6788}
6789
6790static int si_thermal_start_thermal_controller(struct amdgpu_device *adev)
6791{
6792 int ret;
6793
6794 si_thermal_initialize(adev);
6795 ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6796 if (ret)
6797 return ret;
6798 ret = si_thermal_enable_alert(adev, true);
6799 if (ret)
6800 return ret;
6801 if (adev->pm.dpm.fan.ucode_fan_control) {
6802 ret = si_halt_smc(adev);
6803 if (ret)
6804 return ret;
6805 ret = si_thermal_setup_fan_table(adev);
6806 if (ret)
6807 return ret;
6808 ret = si_resume_smc(adev);
6809 if (ret)
6810 return ret;
6811 si_thermal_start_smc_fan_control(adev);
6812 }
6813
6814 return 0;
6815}
6816
6817static void si_thermal_stop_thermal_controller(struct amdgpu_device *adev)
6818{
6819 if (!adev->pm.no_fan) {
6820 si_fan_ctrl_set_default_mode(adev);
6821 si_fan_ctrl_stop_smc_fan_control(adev);
6822 }
6823}
6824
6825static int si_dpm_enable(struct amdgpu_device *adev)
6826{
6827 struct rv7xx_power_info *pi = rv770_get_pi(adev);
6828 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6829 struct si_power_info *si_pi = si_get_pi(adev);
6830 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
6831 int ret;
6832
6861c837 6833 if (amdgpu_si_is_smc_running(adev))
841686df
MB		 6834 return -EINVAL;
6835 if (pi->voltage_control || si_pi->voltage_control_svi2)
6836 si_enable_voltage_control(adev, true);
6837 if (pi->mvdd_control)
6838 si_get_mvdd_configuration(adev);
6839 if (pi->voltage_control || si_pi->voltage_control_svi2) {
6840 ret = si_construct_voltage_tables(adev);
6841 if (ret) {
6842 DRM_ERROR("si_construct_voltage_tables failed\n");
6843 return ret;
6844 }
6845 }
6846 if (eg_pi->dynamic_ac_timing) {
6847 ret = si_initialize_mc_reg_table(adev);
6848 if (ret)
6849 eg_pi->dynamic_ac_timing = false;
6850 }
6851 if (pi->dynamic_ss)
6852 si_enable_spread_spectrum(adev, true);
6853 if (pi->thermal_protection)
6854 si_enable_thermal_protection(adev, true);
6855 si_setup_bsp(adev);
6856 si_program_git(adev);
6857 si_program_tp(adev);
6858 si_program_tpp(adev);
6859 si_program_sstp(adev);
6860 si_enable_display_gap(adev);
6861 si_program_vc(adev);
6862 ret = si_upload_firmware(adev);
6863 if (ret) {
6864 DRM_ERROR("si_upload_firmware failed\n");
6865 return ret;
6866 }
6867 ret = si_process_firmware_header(adev);
6868 if (ret) {
6869 DRM_ERROR("si_process_firmware_header failed\n");
6870 return ret;
6871 }
6872 ret = si_initial_switch_from_arb_f0_to_f1(adev);
6873 if (ret) {
6874 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
6875 return ret;
6876 }
6877 ret = si_init_smc_table(adev);
6878 if (ret) {
6879 DRM_ERROR("si_init_smc_table failed\n");
6880 return ret;
6881 }
6882 ret = si_init_smc_spll_table(adev);
6883 if (ret) {
6884 DRM_ERROR("si_init_smc_spll_table failed\n");
6885 return ret;
6886 }
6887 ret = si_init_arb_table_index(adev);
6888 if (ret) {
6889 DRM_ERROR("si_init_arb_table_index failed\n");
6890 return ret;
6891 }
6892 if (eg_pi->dynamic_ac_timing) {
6893 ret = si_populate_mc_reg_table(adev, boot_ps);
6894 if (ret) {
6895 DRM_ERROR("si_populate_mc_reg_table failed\n");
6896 return ret;
6897 }
6898 }
6899 ret = si_initialize_smc_cac_tables(adev);
6900 if (ret) {
6901 DRM_ERROR("si_initialize_smc_cac_tables failed\n");
6902 return ret;
6903 }
6904 ret = si_initialize_hardware_cac_manager(adev);
6905 if (ret) {
6906 DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
6907 return ret;
6908 }
6909 ret = si_initialize_smc_dte_tables(adev);
6910 if (ret) {
6911 DRM_ERROR("si_initialize_smc_dte_tables failed\n");
6912 return ret;
6913 }
6914 ret = si_populate_smc_tdp_limits(adev, boot_ps);
6915 if (ret) {
6916 DRM_ERROR("si_populate_smc_tdp_limits failed\n");
6917 return ret;
6918 }
6919 ret = si_populate_smc_tdp_limits_2(adev, boot_ps);
6920 if (ret) {
6921 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
6922 return ret;
6923 }
6924 si_program_response_times(adev);
6925 si_program_ds_registers(adev);
6926 si_dpm_start_smc(adev);
6927 ret = si_notify_smc_display_change(adev, false);
6928 if (ret) {
6929 DRM_ERROR("si_notify_smc_display_change failed\n");
6930 return ret;
6931 }
6932 si_enable_sclk_control(adev, true);
6933 si_start_dpm(adev);
6934
6935 si_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
841686df 6936 si_thermal_start_thermal_controller(adev);
841686df
MB		 6937 ni_update_current_ps(adev, boot_ps);
6938
6939 return 0;
6940}
6941
6942static int si_set_temperature_range(struct amdgpu_device *adev)
6943{
6944 int ret;
6945
6946 ret = si_thermal_enable_alert(adev, false);
6947 if (ret)
6948 return ret;
6949 ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6950 if (ret)
6951 return ret;
6952 ret = si_thermal_enable_alert(adev, true);
6953 if (ret)
6954 return ret;
6955
6956 return ret;
6957}
6958
6959static void si_dpm_disable(struct amdgpu_device *adev)
6960{
6961 struct rv7xx_power_info *pi = rv770_get_pi(adev);
6962 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
6963
6861c837 6964 if (!amdgpu_si_is_smc_running(adev))
841686df
MB		 6965 return;
6966 si_thermal_stop_thermal_controller(adev);
6967 si_disable_ulv(adev);
6968 si_clear_vc(adev);
6969 if (pi->thermal_protection)
6970 si_enable_thermal_protection(adev, false);
6971 si_enable_power_containment(adev, boot_ps, false);
6972 si_enable_smc_cac(adev, boot_ps, false);
6973 si_enable_spread_spectrum(adev, false);
6974 si_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
6975 si_stop_dpm(adev);
6976 si_reset_to_default(adev);
6977 si_dpm_stop_smc(adev);
6978 si_force_switch_to_arb_f0(adev);
6979
6980 ni_update_current_ps(adev, boot_ps);
6981}
6982
6983static int si_dpm_pre_set_power_state(struct amdgpu_device *adev)
6984{
6985 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6986 struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
6987 struct amdgpu_ps *new_ps = &requested_ps;
6988
6989 ni_update_requested_ps(adev, new_ps);
841686df
MB		 6990 si_apply_state_adjust_rules(adev, &eg_pi->requested_rps);
6991
6992 return 0;
6993}
6994
6995static int si_power_control_set_level(struct amdgpu_device *adev)
6996{
6997 struct amdgpu_ps *new_ps = adev->pm.dpm.requested_ps;
6998 int ret;
6999
7000 ret = si_restrict_performance_levels_before_switch(adev);
7001 if (ret)
7002 return ret;
7003 ret = si_halt_smc(adev);
7004 if (ret)
7005 return ret;
7006 ret = si_populate_smc_tdp_limits(adev, new_ps);
7007 if (ret)
7008 return ret;
7009 ret = si_populate_smc_tdp_limits_2(adev, new_ps);
7010 if (ret)
7011 return ret;
7012 ret = si_resume_smc(adev);
7013 if (ret)
7014 return ret;
7015 ret = si_set_sw_state(adev);
7016 if (ret)
7017 return ret;
7018 return 0;
7019}
7020
7021static int si_dpm_set_power_state(struct amdgpu_device *adev)
7022{
7023 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7024 struct amdgpu_ps *new_ps = &eg_pi->requested_rps;
7025 struct amdgpu_ps *old_ps = &eg_pi->current_rps;
7026 int ret;
7027
7028 ret = si_disable_ulv(adev);
7029 if (ret) {
7030 DRM_ERROR("si_disable_ulv failed\n");
7031 return ret;
7032 }
7033 ret = si_restrict_performance_levels_before_switch(adev);
7034 if (ret) {
7035 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
7036 return ret;
7037 }
7038 if (eg_pi->pcie_performance_request)
7039 si_request_link_speed_change_before_state_change(adev, new_ps, old_ps);
7040 ni_set_uvd_clock_before_set_eng_clock(adev, new_ps, old_ps);
7041 ret = si_enable_power_containment(adev, new_ps, false);
7042 if (ret) {
7043 DRM_ERROR("si_enable_power_containment failed\n");
7044 return ret;
7045 }
7046 ret = si_enable_smc_cac(adev, new_ps, false);
7047 if (ret) {
7048 DRM_ERROR("si_enable_smc_cac failed\n");
7049 return ret;
7050 }
7051 ret = si_halt_smc(adev);
7052 if (ret) {
7053 DRM_ERROR("si_halt_smc failed\n");
7054 return ret;
7055 }
7056 ret = si_upload_sw_state(adev, new_ps);
7057 if (ret) {
7058 DRM_ERROR("si_upload_sw_state failed\n");
7059 return ret;
7060 }
7061 ret = si_upload_smc_data(adev);
7062 if (ret) {
7063 DRM_ERROR("si_upload_smc_data failed\n");
7064 return ret;
7065 }
7066 ret = si_upload_ulv_state(adev);
7067 if (ret) {
7068 DRM_ERROR("si_upload_ulv_state failed\n");
7069 return ret;
7070 }
7071 if (eg_pi->dynamic_ac_timing) {
7072 ret = si_upload_mc_reg_table(adev, new_ps);
7073 if (ret) {
7074 DRM_ERROR("si_upload_mc_reg_table failed\n");
7075 return ret;
7076 }
7077 }
7078 ret = si_program_memory_timing_parameters(adev, new_ps);
7079 if (ret) {
7080 DRM_ERROR("si_program_memory_timing_parameters failed\n");
7081 return ret;
7082 }
7083 si_set_pcie_lane_width_in_smc(adev, new_ps, old_ps);
7084
7085 ret = si_resume_smc(adev);
7086 if (ret) {
7087 DRM_ERROR("si_resume_smc failed\n");
7088 return ret;
7089 }
7090 ret = si_set_sw_state(adev);
7091 if (ret) {
7092 DRM_ERROR("si_set_sw_state failed\n");
7093 return ret;
7094 }
7095 ni_set_uvd_clock_after_set_eng_clock(adev, new_ps, old_ps);
7096 if (eg_pi->pcie_performance_request)
7097 si_notify_link_speed_change_after_state_change(adev, new_ps, old_ps);
7098 ret = si_set_power_state_conditionally_enable_ulv(adev, new_ps);
7099 if (ret) {
7100 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
7101 return ret;
7102 }
7103 ret = si_enable_smc_cac(adev, new_ps, true);
7104 if (ret) {
7105 DRM_ERROR("si_enable_smc_cac failed\n");
7106 return ret;
7107 }
7108 ret = si_enable_power_containment(adev, new_ps, true);
7109 if (ret) {
7110 DRM_ERROR("si_enable_power_containment failed\n");
7111 return ret;
7112 }
7113
7114 ret = si_power_control_set_level(adev);
7115 if (ret) {
7116 DRM_ERROR("si_power_control_set_level failed\n");
7117 return ret;
7118 }
7119
7120 return 0;
7121}
7122
7123static void si_dpm_post_set_power_state(struct amdgpu_device *adev)
7124{
7125 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7126 struct amdgpu_ps *new_ps = &eg_pi->requested_rps;
7127
7128 ni_update_current_ps(adev, new_ps);
7129}
7130
7131#if 0
7132void si_dpm_reset_asic(struct amdgpu_device *adev)
7133{
7134 si_restrict_performance_levels_before_switch(adev);
7135 si_disable_ulv(adev);
7136 si_set_boot_state(adev);
7137}
7138#endif
7139
7140static void si_dpm_display_configuration_changed(struct amdgpu_device *adev)
7141{
7142 si_program_display_gap(adev);
7143}
7144
7145
7146static void si_parse_pplib_non_clock_info(struct amdgpu_device *adev,
7147 struct amdgpu_ps *rps,
7148 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
7149 u8 table_rev)
7150{
7151 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
7152 rps->class = le16_to_cpu(non_clock_info->usClassification);
7153 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
7154
7155 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
7156 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
7157 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
7158 } else if (r600_is_uvd_state(rps->class, rps->class2)) {
7159 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
7160 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
7161 } else {
7162 rps->vclk = 0;
7163 rps->dclk = 0;
7164 }
7165
7166 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
7167 adev->pm.dpm.boot_ps = rps;
7168 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
7169 adev->pm.dpm.uvd_ps = rps;
7170}
7171
7172static void si_parse_pplib_clock_info(struct amdgpu_device *adev,
7173 struct amdgpu_ps *rps, int index,
7174 union pplib_clock_info *clock_info)
7175{
7176 struct rv7xx_power_info *pi = rv770_get_pi(adev);
7177 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7178 struct si_power_info *si_pi = si_get_pi(adev);
7179 struct si_ps *ps = si_get_ps(rps);
7180 u16 leakage_voltage;
7181 struct rv7xx_pl *pl = &ps->performance_levels[index];
7182 int ret;
7183
7184 ps->performance_level_count = index + 1;
7185
7186 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
7187 pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
7188 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
7189 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
7190
7191 pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
7192 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
7193 pl->flags = le32_to_cpu(clock_info->si.ulFlags);
7194 pl->pcie_gen = r600_get_pcie_gen_support(adev,
7195 si_pi->sys_pcie_mask,
7196 si_pi->boot_pcie_gen,
7197 clock_info->si.ucPCIEGen);
7198
7199 /* patch up vddc if necessary */
7200 ret = si_get_leakage_voltage_from_leakage_index(adev, pl->vddc,
7201 &leakage_voltage);
7202 if (ret == 0)
7203 pl->vddc = leakage_voltage;
7204
7205 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
7206 pi->acpi_vddc = pl->vddc;
7207 eg_pi->acpi_vddci = pl->vddci;
7208 si_pi->acpi_pcie_gen = pl->pcie_gen;
7209 }
7210
7211 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
7212 index == 0) {
7213 /* XXX disable for A0 tahiti */
7214 si_pi->ulv.supported = false;
7215 si_pi->ulv.pl = *pl;
7216 si_pi->ulv.one_pcie_lane_in_ulv = false;
7217 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
7218 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
7219 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;
7220 }
7221
7222 if (pi->min_vddc_in_table > pl->vddc)
7223 pi->min_vddc_in_table = pl->vddc;
7224
7225 if (pi->max_vddc_in_table < pl->vddc)
7226 pi->max_vddc_in_table = pl->vddc;
7227
7228 /* patch up boot state */
7229 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
7230 u16 vddc, vddci, mvdd;
7231 amdgpu_atombios_get_default_voltages(adev, &vddc, &vddci, &mvdd);
7232 pl->mclk = adev->clock.default_mclk;
7233 pl->sclk = adev->clock.default_sclk;
7234 pl->vddc = vddc;
7235 pl->vddci = vddci;
7236 si_pi->mvdd_bootup_value = mvdd;
7237 }
7238
7239 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
7240 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
7241 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
7242 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
7243 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
7244 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
7245 }
7246}
7247
7248union pplib_power_state {
77d318a6
TSD		 7249 struct _ATOM_PPLIB_STATE v1;
7250 struct _ATOM_PPLIB_STATE_V2 v2;
841686df
MB		 7251};
7252
7253static int si_parse_power_table(struct amdgpu_device *adev)
7254{
7255 struct amdgpu_mode_info *mode_info = &adev->mode_info;
7256 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
7257 union pplib_power_state *power_state;
7258 int i, j, k, non_clock_array_index, clock_array_index;
7259 union pplib_clock_info *clock_info;
7260 struct _StateArray *state_array;
7261 struct _ClockInfoArray *clock_info_array;
7262 struct _NonClockInfoArray *non_clock_info_array;
7263 union power_info *power_info;
7264 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
77d318a6 7265 u16 data_offset;
841686df
MB		 7266 u8 frev, crev;
7267 u8 *power_state_offset;
7268 struct si_ps *ps;
7269
7270 if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
7271 &frev, &crev, &data_offset))
7272 return -EINVAL;
7273 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
7274
7275 amdgpu_add_thermal_controller(adev);
7276
7277 state_array = (struct _StateArray *)
7278 (mode_info->atom_context->bios + data_offset +
7279 le16_to_cpu(power_info->pplib.usStateArrayOffset));
7280 clock_info_array = (struct _ClockInfoArray *)
7281 (mode_info->atom_context->bios + data_offset +
7282 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
7283 non_clock_info_array = (struct _NonClockInfoArray *)
7284 (mode_info->atom_context->bios + data_offset +
7285 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
7286
7287 adev->pm.dpm.ps = kzalloc(sizeof(struct amdgpu_ps) *
7288 state_array->ucNumEntries, GFP_KERNEL);
7289 if (!adev->pm.dpm.ps)
7290 return -ENOMEM;
7291 power_state_offset = (u8 *)state_array->states;
7292 for (i = 0; i < state_array->ucNumEntries; i++) {
7293 u8 *idx;
7294 power_state = (union pplib_power_state *)power_state_offset;
7295 non_clock_array_index = power_state->v2.nonClockInfoIndex;
7296 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
7297 &non_clock_info_array->nonClockInfo[non_clock_array_index];
7298 ps = kzalloc(sizeof(struct si_ps), GFP_KERNEL);
7299 if (ps == NULL) {
7300 kfree(adev->pm.dpm.ps);
7301 return -ENOMEM;
7302 }
7303 adev->pm.dpm.ps[i].ps_priv = ps;
7304 si_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i],
7305 non_clock_info,
7306 non_clock_info_array->ucEntrySize);
7307 k = 0;
7308 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
7309 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
7310 clock_array_index = idx[j];
7311 if (clock_array_index >= clock_info_array->ucNumEntries)
7312 continue;
7313 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
7314 break;
7315 clock_info = (union pplib_clock_info *)
7316 ((u8 *)&clock_info_array->clockInfo[0] +
7317 (clock_array_index * clock_info_array->ucEntrySize));
7318 si_parse_pplib_clock_info(adev,
7319 &adev->pm.dpm.ps[i], k,
7320 clock_info);
7321 k++;
7322 }
7323 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
7324 }
7325 adev->pm.dpm.num_ps = state_array->ucNumEntries;
7326
7327 /* fill in the vce power states */
66ba1afd 7328 for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) {
841686df
MB		 7329 u32 sclk, mclk;
7330 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx;
7331 clock_info = (union pplib_clock_info *)
7332 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
7333 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
7334 sclk |= clock_info->si.ucEngineClockHigh << 16;
7335 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
7336 mclk |= clock_info->si.ucMemoryClockHigh << 16;
7337 adev->pm.dpm.vce_states[i].sclk = sclk;
7338 adev->pm.dpm.vce_states[i].mclk = mclk;
7339 }
7340
7341 return 0;
7342}
7343
7344static int si_dpm_init(struct amdgpu_device *adev)
7345{
7346 struct rv7xx_power_info *pi;
7347 struct evergreen_power_info *eg_pi;
7348 struct ni_power_info *ni_pi;
7349 struct si_power_info *si_pi;
7350 struct atom_clock_dividers dividers;
7351 int ret;
7352 u32 mask;
7353
7354 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
7355 if (si_pi == NULL)
7356 return -ENOMEM;
7357 adev->pm.dpm.priv = si_pi;
7358 ni_pi = &si_pi->ni;
7359 eg_pi = &ni_pi->eg;
7360 pi = &eg_pi->rv7xx;
7361
7362 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
7363 if (ret)
7364 si_pi->sys_pcie_mask = 0;
7365 else
7366 si_pi->sys_pcie_mask = mask;
7367 si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
7368 si_pi->boot_pcie_gen = si_get_current_pcie_speed(adev);
7369
7370 si_set_max_cu_value(adev);
7371
7372 rv770_get_max_vddc(adev);
7373 si_get_leakage_vddc(adev);
7374 si_patch_dependency_tables_based_on_leakage(adev);
7375
7376 pi->acpi_vddc = 0;
7377 eg_pi->acpi_vddci = 0;
7378 pi->min_vddc_in_table = 0;
7379 pi->max_vddc_in_table = 0;
7380
7381 ret = amdgpu_get_platform_caps(adev);
7382 if (ret)
7383 return ret;
7384
7385 ret = amdgpu_parse_extended_power_table(adev);
7386 if (ret)
7387 return ret;
7388
7389 ret = si_parse_power_table(adev);
7390 if (ret)
7391 return ret;
7392
7393 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
7394 kzalloc(4 * sizeof(struct amdgpu_clock_voltage_dependency_entry), GFP_KERNEL);
7395 if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
7396 amdgpu_free_extended_power_table(adev);
7397 return -ENOMEM;
7398 }
7399 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
7400 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
7401 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
7402 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
7403 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
7404 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
7405 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
7406 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
7407 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
7408
7409 if (adev->pm.dpm.voltage_response_time == 0)
7410 adev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
7411 if (adev->pm.dpm.backbias_response_time == 0)
7412 adev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
7413
7414 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
7415 0, false, &dividers);
7416 if (ret)
7417 pi->ref_div = dividers.ref_div + 1;
7418 else
7419 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
7420
7421 eg_pi->smu_uvd_hs = false;
7422
7423 pi->mclk_strobe_mode_threshold = 40000;
7424 if (si_is_special_1gb_platform(adev))
7425 pi->mclk_stutter_mode_threshold = 0;
7426 else
7427 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;
7428 pi->mclk_edc_enable_threshold = 40000;
7429 eg_pi->mclk_edc_wr_enable_threshold = 40000;
7430
7431 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
7432
7433 pi->voltage_control =
7434 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7435 VOLTAGE_OBJ_GPIO_LUT);
7436 if (!pi->voltage_control) {
7437 si_pi->voltage_control_svi2 =
7438 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7439 VOLTAGE_OBJ_SVID2);
7440 if (si_pi->voltage_control_svi2)
7441 amdgpu_atombios_get_svi2_info(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7442 &si_pi->svd_gpio_id, &si_pi->svc_gpio_id);
7443 }
7444
7445 pi->mvdd_control =
7446 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_MVDDC,
7447 VOLTAGE_OBJ_GPIO_LUT);
7448
7449 eg_pi->vddci_control =
7450 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7451 VOLTAGE_OBJ_GPIO_LUT);
7452 if (!eg_pi->vddci_control)
7453 si_pi->vddci_control_svi2 =
7454 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7455 VOLTAGE_OBJ_SVID2);
7456
7457 si_pi->vddc_phase_shed_control =
7458 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7459 VOLTAGE_OBJ_PHASE_LUT);
7460
7461 rv770_get_engine_memory_ss(adev);
7462
7463 pi->asi = RV770_ASI_DFLT;
7464 pi->pasi = CYPRESS_HASI_DFLT;
7465 pi->vrc = SISLANDS_VRC_DFLT;
7466
7467 pi->gfx_clock_gating = true;
7468
7469 eg_pi->sclk_deep_sleep = true;
7470 si_pi->sclk_deep_sleep_above_low = false;
7471
7472 if (adev->pm.int_thermal_type != THERMAL_TYPE_NONE)
7473 pi->thermal_protection = true;
7474 else
7475 pi->thermal_protection = false;
7476
7477 eg_pi->dynamic_ac_timing = true;
7478
7479 eg_pi->light_sleep = true;
7480#if defined(CONFIG_ACPI)
7481 eg_pi->pcie_performance_request =
7482 amdgpu_acpi_is_pcie_performance_request_supported(adev);
7483#else
7484 eg_pi->pcie_performance_request = false;
7485#endif
7486
7487 si_pi->sram_end = SMC_RAM_END;
7488
7489 adev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
7490 adev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
7491 adev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
7492 adev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
7493 adev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
7494 adev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
7495 adev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
7496
7497 si_initialize_powertune_defaults(adev);
7498
7499 /* make sure dc limits are valid */
7500 if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
7501 (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
7502 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
7503 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
7504
7505 si_pi->fan_ctrl_is_in_default_mode = true;
7506
7507 return 0;
7508}
7509
7510static void si_dpm_fini(struct amdgpu_device *adev)
7511{
7512 int i;
7513
9623e4bf
TSD		 7514 if (adev->pm.dpm.ps)
7515 for (i = 0; i < adev->pm.dpm.num_ps; i++)
7516 kfree(adev->pm.dpm.ps[i].ps_priv);
841686df
MB		 7517 kfree(adev->pm.dpm.ps);
7518 kfree(adev->pm.dpm.priv);
7519 kfree(adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
7520 amdgpu_free_extended_power_table(adev);
7521}
7522
7523static void si_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
7524 struct seq_file *m)
7525{
7526 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7527 struct amdgpu_ps *rps = &eg_pi->current_rps;
7528 struct si_ps *ps = si_get_ps(rps);
7529 struct rv7xx_pl *pl;
7530 u32 current_index =
7531 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7532 CURRENT_STATE_INDEX_SHIFT;
7533
7534 if (current_index >= ps->performance_level_count) {
7535 seq_printf(m, "invalid dpm profile %d\n", current_index);
7536 } else {
7537 pl = &ps->performance_levels[current_index];
7538 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7539 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7540 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7541 }
7542}
7543
7544static int si_dpm_set_interrupt_state(struct amdgpu_device *adev,
7545 struct amdgpu_irq_src *source,
7546 unsigned type,
7547 enum amdgpu_interrupt_state state)
7548{
7549 u32 cg_thermal_int;
7550
7551 switch (type) {
7552 case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH:
7553 switch (state) {
7554 case AMDGPU_IRQ_STATE_DISABLE:
7555 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7556 cg_thermal_int |= THERM_INT_MASK_HIGH;
7557 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7558 break;
7559 case AMDGPU_IRQ_STATE_ENABLE:
7560 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7561 cg_thermal_int &= ~THERM_INT_MASK_HIGH;
7562 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7563 break;
7564 default:
7565 break;
7566 }
7567 break;
7568
7569 case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW:
7570 switch (state) {
7571 case AMDGPU_IRQ_STATE_DISABLE:
7572 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7573 cg_thermal_int |= THERM_INT_MASK_LOW;
7574 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7575 break;
7576 case AMDGPU_IRQ_STATE_ENABLE:
7577 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7578 cg_thermal_int &= ~THERM_INT_MASK_LOW;
7579 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7580 break;
7581 default:
7582 break;
7583 }
7584 break;
7585
7586 default:
7587 break;
7588 }
7589 return 0;
7590}
7591
7592static int si_dpm_process_interrupt(struct amdgpu_device *adev,
a1047777 7593 struct amdgpu_irq_src *source,
841686df
MB		 7594 struct amdgpu_iv_entry *entry)
7595{
7596 bool queue_thermal = false;
7597
7598 if (entry == NULL)
7599 return -EINVAL;
7600
7601 switch (entry->src_id) {
7602 case 230: /* thermal low to high */
7603 DRM_DEBUG("IH: thermal low to high\n");
7604 adev->pm.dpm.thermal.high_to_low = false;
7605 queue_thermal = true;
7606 break;
7607 case 231: /* thermal high to low */
7608 DRM_DEBUG("IH: thermal high to low\n");
7609 adev->pm.dpm.thermal.high_to_low = true;
7610 queue_thermal = true;
7611 break;
7612 default:
7613 break;
7614 }
7615
7616 if (queue_thermal)
7617 schedule_work(&adev->pm.dpm.thermal.work);
7618
7619 return 0;
7620}
7621
7622static int si_dpm_late_init(void *handle)
7623{
7624 int ret;
7625 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7626
7627 if (!amdgpu_dpm)
7628 return 0;
7629
7630 /* init the sysfs and debugfs files late */
7631 ret = amdgpu_pm_sysfs_init(adev);
7632 if (ret)
7633 return ret;
7634
7635 ret = si_set_temperature_range(adev);
7636 if (ret)
7637 return ret;
7638#if 0 //TODO ?
7639 si_dpm_powergate_uvd(adev, true);
7640#endif
7641 return 0;
7642}
7643
7644/**
7645 * si_dpm_init_microcode - load ucode images from disk
7646 *
7647 * @adev: amdgpu_device pointer
7648 *
7649 * Use the firmware interface to load the ucode images into
7650 * the driver (not loaded into hw).
7651 * Returns 0 on success, error on failure.
7652 */
7653static int si_dpm_init_microcode(struct amdgpu_device *adev)
7654{
7655 const char *chip_name;
7656 char fw_name[30];
7657 int err;
7658
7659 DRM_DEBUG("\n");
7660 switch (adev->asic_type) {
7661 case CHIP_TAHITI:
7662 chip_name = "tahiti";
7663 break;
7664 case CHIP_PITCAIRN:
5165484b
FC		 7665 if ((adev->pdev->revision == 0x81) &&
7666 ((adev->pdev->device == 0x6810) ||
7667 (adev->pdev->device == 0x6811)))
a8c65c13
AD		 7668 chip_name = "pitcairn_k";
7669 else
7670 chip_name = "pitcairn";
841686df
MB		 7671 break;
7672 case CHIP_VERDE:
5165484b
FC		 7673 if (((adev->pdev->device == 0x6820) &&
7674 ((adev->pdev->revision == 0x81) ||
7675 (adev->pdev->revision == 0x83))) ||
7676 ((adev->pdev->device == 0x6821) &&
7677 ((adev->pdev->revision == 0x83) ||
7678 (adev->pdev->revision == 0x87))) ||
7679 ((adev->pdev->revision == 0x87) &&
7680 ((adev->pdev->device == 0x6823) ||
7681 (adev->pdev->device == 0x682b))))
a8c65c13
AD		 7682 chip_name = "verde_k";
7683 else
7684 chip_name = "verde";
841686df
MB		 7685 break;
7686 case CHIP_OLAND:
5165484b
FC		 7687 if (((adev->pdev->revision == 0x81) &&
7688 ((adev->pdev->device == 0x6600) ||
7689 (adev->pdev->device == 0x6604) ||
7690 (adev->pdev->device == 0x6605) ||
7691 (adev->pdev->device == 0x6610))) ||
7692 ((adev->pdev->revision == 0x83) &&
7693 (adev->pdev->device == 0x6610)))
a8c65c13
AD		 7694 chip_name = "oland_k";
7695 else
7696 chip_name = "oland";
841686df
MB		 7697 break;
7698 case CHIP_HAINAN:
5165484b
FC		 7699 if (((adev->pdev->revision == 0x81) &&
7700 (adev->pdev->device == 0x6660)) ||
7701 ((adev->pdev->revision == 0x83) &&
7702 ((adev->pdev->device == 0x6660) ||
7703 (adev->pdev->device == 0x6663) ||
7704 (adev->pdev->device == 0x6665) ||
17324b6a 7705 (adev->pdev->device == 0x6667))))
a8c65c13 7706 chip_name = "hainan_k";
17324b6a
AD		 7707 else if ((adev->pdev->revision == 0xc3) &&
7708 (adev->pdev->device == 0x6665))
7709 chip_name = "banks_k_2";
a8c65c13
AD		 7710 else
7711 chip_name = "hainan";
841686df
MB		 7712 break;
7713 default: BUG();
7714 }
7715
7716 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
7717 err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
7718 if (err)
7719 goto out;
7720 err = amdgpu_ucode_validate(adev->pm.fw);
7721
7722out:
7723 if (err) {
84b77336
HR		 7724 DRM_ERROR("si_smc: Failed to load firmware. err = %d\"%s\"\n",
7725 err, fw_name);
841686df
MB		 7726 release_firmware(adev->pm.fw);
7727 adev->pm.fw = NULL;
7728 }
7729 return err;
7730
7731}
7732
7733static int si_dpm_sw_init(void *handle)
7734{
7735 int ret;
7736 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7737
7738 ret = amdgpu_irq_add_id(adev, 230, &adev->pm.dpm.thermal.irq);
7739 if (ret)
7740 return ret;
7741
7742 ret = amdgpu_irq_add_id(adev, 231, &adev->pm.dpm.thermal.irq);
7743 if (ret)
7744 return ret;
7745
7746 /* default to balanced state */
7747 adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
7748 adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
7749 adev->pm.dpm.forced_level = AMDGPU_DPM_FORCED_LEVEL_AUTO;
7750 adev->pm.default_sclk = adev->clock.default_sclk;
7751 adev->pm.default_mclk = adev->clock.default_mclk;
7752 adev->pm.current_sclk = adev->clock.default_sclk;
7753 adev->pm.current_mclk = adev->clock.default_mclk;
7754 adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
7755
7756 if (amdgpu_dpm == 0)
7757 return 0;
7758
7759 ret = si_dpm_init_microcode(adev);
7760 if (ret)
7761 return ret;
7762
7763 INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler);
7764 mutex_lock(&adev->pm.mutex);
7765 ret = si_dpm_init(adev);
7766 if (ret)
7767 goto dpm_failed;
7768 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
7769 if (amdgpu_dpm == 1)
7770 amdgpu_pm_print_power_states(adev);
7771 mutex_unlock(&adev->pm.mutex);
7772 DRM_INFO("amdgpu: dpm initialized\n");
7773
7774 return 0;
7775
7776dpm_failed:
7777 si_dpm_fini(adev);
7778 mutex_unlock(&adev->pm.mutex);
7779 DRM_ERROR("amdgpu: dpm initialization failed\n");
7780 return ret;
7781}
7782
7783static int si_dpm_sw_fini(void *handle)
7784{
7785 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7786
4560738a
AD		 7787 flush_work(&adev->pm.dpm.thermal.work);
7788
841686df
MB		 7789 mutex_lock(&adev->pm.mutex);
7790 amdgpu_pm_sysfs_fini(adev);
7791 si_dpm_fini(adev);
7792 mutex_unlock(&adev->pm.mutex);
7793
7794 return 0;
7795}
7796
7797static int si_dpm_hw_init(void *handle)
7798{
7799 int ret;
7800
7801 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7802
7803 if (!amdgpu_dpm)
7804 return 0;
7805
7806 mutex_lock(&adev->pm.mutex);
7807 si_dpm_setup_asic(adev);
7808 ret = si_dpm_enable(adev);
7809 if (ret)
7810 adev->pm.dpm_enabled = false;
7811 else
7812 adev->pm.dpm_enabled = true;
7813 mutex_unlock(&adev->pm.mutex);
7814
7815 return ret;
7816}
7817
7818static int si_dpm_hw_fini(void *handle)
7819{
7820 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7821
7822 if (adev->pm.dpm_enabled) {
7823 mutex_lock(&adev->pm.mutex);
7824 si_dpm_disable(adev);
7825 mutex_unlock(&adev->pm.mutex);
7826 }
7827
7828 return 0;
7829}
7830
7831static int si_dpm_suspend(void *handle)
7832{
7833 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7834
7835 if (adev->pm.dpm_enabled) {
7836 mutex_lock(&adev->pm.mutex);
7837 /* disable dpm */
7838 si_dpm_disable(adev);
7839 /* reset the power state */
7840 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
7841 mutex_unlock(&adev->pm.mutex);
7842 }
7843 return 0;
7844}
7845
7846static int si_dpm_resume(void *handle)
7847{
7848 int ret;
7849 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7850
7851 if (adev->pm.dpm_enabled) {
7852 /* asic init will reset to the boot state */
7853 mutex_lock(&adev->pm.mutex);
7854 si_dpm_setup_asic(adev);
7855 ret = si_dpm_enable(adev);
7856 if (ret)
7857 adev->pm.dpm_enabled = false;
7858 else
7859 adev->pm.dpm_enabled = true;
7860 mutex_unlock(&adev->pm.mutex);
7861 if (adev->pm.dpm_enabled)
7862 amdgpu_pm_compute_clocks(adev);
7863 }
7864 return 0;
7865}
7866
7867static bool si_dpm_is_idle(void *handle)
7868{
7869 /* XXX */
7870 return true;
7871}
7872
7873static int si_dpm_wait_for_idle(void *handle)
7874{
7875 /* XXX */
7876 return 0;
7877}
7878
7879static int si_dpm_soft_reset(void *handle)
7880{
7881 return 0;
7882}
7883
7884static int si_dpm_set_clockgating_state(void *handle,
7885 enum amd_clockgating_state state)
7886{
7887 return 0;
7888}
7889
7890static int si_dpm_set_powergating_state(void *handle,
7891 enum amd_powergating_state state)
7892{
7893 return 0;
7894}
7895
7896/* get temperature in millidegrees */
7897static int si_dpm_get_temp(struct amdgpu_device *adev)
7898{
7899 u32 temp;
7900 int actual_temp = 0;
7901
7902 temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
7903 CTF_TEMP_SHIFT;
7904
7905 if (temp & 0x200)
7906 actual_temp = 255;
7907 else
7908 actual_temp = temp & 0x1ff;
7909
7910 actual_temp = (actual_temp * 1000);
7911
7912 return actual_temp;
7913}
7914
7915static u32 si_dpm_get_sclk(struct amdgpu_device *adev, bool low)
7916{
77d318a6
TSD		 7917 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7918 struct si_ps *requested_state = si_get_ps(&eg_pi->requested_rps);
841686df 7919
77d318a6
TSD		 7920 if (low)
7921 return requested_state->performance_levels[0].sclk;
7922 else
7923 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
841686df
MB		 7924}
7925
7926static u32 si_dpm_get_mclk(struct amdgpu_device *adev, bool low)
7927{
77d318a6
TSD		 7928 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7929 struct si_ps *requested_state = si_get_ps(&eg_pi->requested_rps);
841686df 7930
77d318a6
TSD		 7931 if (low)
7932 return requested_state->performance_levels[0].mclk;
7933 else
7934 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;
841686df
MB		 7935}
7936
7937static void si_dpm_print_power_state(struct amdgpu_device *adev,
77d318a6
TSD		 7938 struct amdgpu_ps *rps)
7939{
7940 struct si_ps *ps = si_get_ps(rps);
7941 struct rv7xx_pl *pl;
7942 int i;
7943
7944 amdgpu_dpm_print_class_info(rps->class, rps->class2);
7945 amdgpu_dpm_print_cap_info(rps->caps);
7946 DRM_INFO("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7947 for (i = 0; i < ps->performance_level_count; i++) {
7948 pl = &ps->performance_levels[i];
7949 if (adev->asic_type >= CHIP_TAHITI)
7950 DRM_INFO("\t\tpower level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
84b77336 7951 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
77d318a6
TSD		 7952 else
7953 DRM_INFO("\t\tpower level %d sclk: %u mclk: %u vddc: %u vddci: %u\n",
84b77336 7954 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci);
77d318a6
TSD		 7955 }
7956 amdgpu_dpm_print_ps_status(adev, rps);
841686df
MB		 7957}
7958
7959static int si_dpm_early_init(void *handle)
7960{
7961
7962 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7963
7964 si_dpm_set_dpm_funcs(adev);
7965 si_dpm_set_irq_funcs(adev);
7966 return 0;
7967}
7968
34117175
RZ		 7969static inline bool si_are_power_levels_equal(const struct rv7xx_pl *si_cpl1,
7970 const struct rv7xx_pl *si_cpl2)
7971{
7972 return ((si_cpl1->mclk == si_cpl2->mclk) &&
7973 (si_cpl1->sclk == si_cpl2->sclk) &&
7974 (si_cpl1->pcie_gen == si_cpl2->pcie_gen) &&
7975 (si_cpl1->vddc == si_cpl2->vddc) &&
7976 (si_cpl1->vddci == si_cpl2->vddci));
7977}
7978
7979static int si_check_state_equal(struct amdgpu_device *adev,
7980 struct amdgpu_ps *cps,
7981 struct amdgpu_ps *rps,
7982 bool *equal)
7983{
7984 struct si_ps *si_cps;
7985 struct si_ps *si_rps;
7986 int i;
7987
7988 if (adev == NULL || cps == NULL || rps == NULL || equal == NULL)
7989 return -EINVAL;
7990
7991 si_cps = si_get_ps(cps);
7992 si_rps = si_get_ps(rps);
7993
7994 if (si_cps == NULL) {
7995 printk("si_cps is NULL\n");
7996 *equal = false;
7997 return 0;
7998 }
7999
8000 if (si_cps->performance_level_count != si_rps->performance_level_count) {
8001 *equal = false;
8002 return 0;
8003 }
8004
8005 for (i = 0; i < si_cps->performance_level_count; i++) {
8006 if (!si_are_power_levels_equal(&(si_cps->performance_levels[i]),
8007 &(si_rps->performance_levels[i]))) {
8008 *equal = false;
8009 return 0;
8010 }
8011 }
8012
8013 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
8014 *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk));
8015 *equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk));
8016
8017 return 0;
8018}
8019
841686df
MB		 8020
8021const struct amd_ip_funcs si_dpm_ip_funcs = {
8022 .name = "si_dpm",
8023 .early_init = si_dpm_early_init,
8024 .late_init = si_dpm_late_init,
8025 .sw_init = si_dpm_sw_init,
8026 .sw_fini = si_dpm_sw_fini,
8027 .hw_init = si_dpm_hw_init,
8028 .hw_fini = si_dpm_hw_fini,
8029 .suspend = si_dpm_suspend,
8030 .resume = si_dpm_resume,
8031 .is_idle = si_dpm_is_idle,
8032 .wait_for_idle = si_dpm_wait_for_idle,
8033 .soft_reset = si_dpm_soft_reset,
8034 .set_clockgating_state = si_dpm_set_clockgating_state,
8035 .set_powergating_state = si_dpm_set_powergating_state,
8036};
8037
8038static const struct amdgpu_dpm_funcs si_dpm_funcs = {
8039 .get_temperature = &si_dpm_get_temp,
8040 .pre_set_power_state = &si_dpm_pre_set_power_state,
8041 .set_power_state = &si_dpm_set_power_state,
8042 .post_set_power_state = &si_dpm_post_set_power_state,
8043 .display_configuration_changed = &si_dpm_display_configuration_changed,
8044 .get_sclk = &si_dpm_get_sclk,
8045 .get_mclk = &si_dpm_get_mclk,
8046 .print_power_state = &si_dpm_print_power_state,
8047 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
8048 .force_performance_level = &si_dpm_force_performance_level,
8049 .vblank_too_short = &si_dpm_vblank_too_short,
8050 .set_fan_control_mode = &si_dpm_set_fan_control_mode,
8051 .get_fan_control_mode = &si_dpm_get_fan_control_mode,
8052 .set_fan_speed_percent = &si_dpm_set_fan_speed_percent,
8053 .get_fan_speed_percent = &si_dpm_get_fan_speed_percent,
34117175 8054 .check_state_equal = &si_check_state_equal,
825cc997 8055 .get_vce_clock_state = amdgpu_get_vce_clock_state,
841686df
MB		 8056};
8057
8058static void si_dpm_set_dpm_funcs(struct amdgpu_device *adev)
8059{
8060 if (adev->pm.funcs == NULL)
8061 adev->pm.funcs = &si_dpm_funcs;
8062}
8063
8064static const struct amdgpu_irq_src_funcs si_dpm_irq_funcs = {
8065 .set = si_dpm_set_interrupt_state,
8066 .process = si_dpm_process_interrupt,
8067};
8068
8069static void si_dpm_set_irq_funcs(struct amdgpu_device *adev)
8070{
8071 adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST;
8072 adev->pm.dpm.thermal.irq.funcs = &si_dpm_irq_funcs;
8073}
8074
a1255107
AD		 8075const struct amdgpu_ip_block_version si_dpm_ip_block =
8076{
8077 .type = AMD_IP_BLOCK_TYPE_SMC,
8078 .major = 6,
8079 .minor = 0,
8080 .rev = 0,
8081 .funcs = &si_dpm_ip_funcs,
8082};
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