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drm/amdgpu: move some release handles into fail labels (v2)
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / amdgpu / si_dpm.c
CommitLineData
841686df
MB		 1/*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include "drmP.h"
25#include "amdgpu.h"
26#include "amdgpu_pm.h"
27#include "amdgpu_dpm.h"
28#include "amdgpu_atombios.h"
29#include "si/sid.h"
30#include "r600_dpm.h"
31#include "si_dpm.h"
32#include "atom.h"
33#include "../include/pptable.h"
34#include <linux/math64.h>
35#include <linux/seq_file.h>
36#include <linux/firmware.h>
37
38#define MC_CG_ARB_FREQ_F0 0x0a
39#define MC_CG_ARB_FREQ_F1 0x0b
40#define MC_CG_ARB_FREQ_F2 0x0c
41#define MC_CG_ARB_FREQ_F3 0x0d
42
43#define SMC_RAM_END 0x20000
44
45#define SCLK_MIN_DEEPSLEEP_FREQ 1350
46
47
48/* sizeof(ATOM_PPLIB_EXTENDEDHEADER) */
49#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2 12
50#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3 14
51#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4 16
52#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5 18
53#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6 20
54#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7 22
55
56#define BIOS_SCRATCH_4 0x5cd
57
58MODULE_FIRMWARE("radeon/tahiti_smc.bin");
a8c65c13 59MODULE_FIRMWARE("radeon/tahiti_k_smc.bin");
841686df 60MODULE_FIRMWARE("radeon/pitcairn_smc.bin");
a8c65c13 61MODULE_FIRMWARE("radeon/pitcairn_k_smc.bin");
841686df 62MODULE_FIRMWARE("radeon/verde_smc.bin");
a8c65c13 63MODULE_FIRMWARE("radeon/verde_k_smc.bin");
841686df 64MODULE_FIRMWARE("radeon/oland_smc.bin");
a8c65c13 65MODULE_FIRMWARE("radeon/oland_k_smc.bin");
841686df 66MODULE_FIRMWARE("radeon/hainan_smc.bin");
a8c65c13 67MODULE_FIRMWARE("radeon/hainan_k_smc.bin");
841686df
MB		 68
69union power_info {
70 struct _ATOM_POWERPLAY_INFO info;
71 struct _ATOM_POWERPLAY_INFO_V2 info_2;
72 struct _ATOM_POWERPLAY_INFO_V3 info_3;
73 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
74 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
75 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
76 struct _ATOM_PPLIB_POWERPLAYTABLE4 pplib4;
77 struct _ATOM_PPLIB_POWERPLAYTABLE5 pplib5;
78};
79
80union fan_info {
81 struct _ATOM_PPLIB_FANTABLE fan;
82 struct _ATOM_PPLIB_FANTABLE2 fan2;
83 struct _ATOM_PPLIB_FANTABLE3 fan3;
84};
85
86union pplib_clock_info {
77d318a6
TSD		 87 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
88 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
89 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
90 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
91 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
841686df
MB		 92};
93
94const u32 r600_utc[R600_PM_NUMBER_OF_TC] =
95{
96 R600_UTC_DFLT_00,
97 R600_UTC_DFLT_01,
98 R600_UTC_DFLT_02,
99 R600_UTC_DFLT_03,
100 R600_UTC_DFLT_04,
101 R600_UTC_DFLT_05,
102 R600_UTC_DFLT_06,
103 R600_UTC_DFLT_07,
104 R600_UTC_DFLT_08,
105 R600_UTC_DFLT_09,
106 R600_UTC_DFLT_10,
107 R600_UTC_DFLT_11,
108 R600_UTC_DFLT_12,
109 R600_UTC_DFLT_13,
110 R600_UTC_DFLT_14,
111};
112
113const u32 r600_dtc[R600_PM_NUMBER_OF_TC] =
114{
115 R600_DTC_DFLT_00,
116 R600_DTC_DFLT_01,
117 R600_DTC_DFLT_02,
118 R600_DTC_DFLT_03,
119 R600_DTC_DFLT_04,
120 R600_DTC_DFLT_05,
121 R600_DTC_DFLT_06,
122 R600_DTC_DFLT_07,
123 R600_DTC_DFLT_08,
124 R600_DTC_DFLT_09,
125 R600_DTC_DFLT_10,
126 R600_DTC_DFLT_11,
127 R600_DTC_DFLT_12,
128 R600_DTC_DFLT_13,
129 R600_DTC_DFLT_14,
130};
131
132static const struct si_cac_config_reg cac_weights_tahiti[] =
133{
134 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
135 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
136 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
137 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
138 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
139 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
140 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
141 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
142 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
143 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
144 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
145 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
146 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
147 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
148 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
149 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
150 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
151 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
152 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
153 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
154 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
155 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
156 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
157 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
158 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
159 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
160 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
161 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
162 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
163 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
164 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
165 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
166 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
167 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
168 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
169 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
170 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
171 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
172 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
173 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
174 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
175 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
176 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
177 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
178 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
179 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
180 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
181 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
182 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
183 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
184 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
185 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
186 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
187 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
188 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
189 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
190 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
191 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
192 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
193 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
194 { 0xFFFFFFFF }
195};
196
197static const struct si_cac_config_reg lcac_tahiti[] =
198{
199 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
200 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
201 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
202 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
203 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
204 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
205 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
206 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
207 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
208 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
209 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
210 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
211 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
212 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
213 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
214 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
215 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
216 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
217 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
218 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
219 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
220 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
221 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
222 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
223 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
224 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
225 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
226 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
227 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
228 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
229 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
230 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
231 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
232 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
233 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
234 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
235 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
236 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
237 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
238 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
239 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
240 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
241 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
242 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
243 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
244 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
245 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
246 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
247 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
248 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
249 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
250 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
251 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
252 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
253 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
254 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
255 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
256 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
257 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
258 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
259 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
260 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
261 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
262 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
263 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
264 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
265 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
266 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
267 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
268 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
269 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
270 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
271 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
272 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
273 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
274 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
275 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
276 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
277 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
278 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
279 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
280 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
281 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
282 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
283 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
284 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
285 { 0xFFFFFFFF }
286
287};
288
289static const struct si_cac_config_reg cac_override_tahiti[] =
290{
291 { 0xFFFFFFFF }
292};
293
294static const struct si_powertune_data powertune_data_tahiti =
295{
296 ((1 << 16) | 27027),
297 6,
298 0,
299 4,
300 95,
301 {
302 0UL,
303 0UL,
304 4521550UL,
305 309631529UL,
306 -1270850L,
307 4513710L,
308 40
309 },
310 595000000UL,
311 12,
312 {
313 0,
314 0,
315 0,
316 0,
317 0,
318 0,
319 0,
320 0
321 },
322 true
323};
324
325static const struct si_dte_data dte_data_tahiti =
326{
327 { 1159409, 0, 0, 0, 0 },
328 { 777, 0, 0, 0, 0 },
329 2,
330 54000,
331 127000,
332 25,
333 2,
334 10,
335 13,
336 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
337 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
338 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
339 85,
340 false
341};
342
e5c5304f 343#if 0
841686df
MB		 344static const struct si_dte_data dte_data_tahiti_le =
345{
346 { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 },
347 { 0x7D, 0x7D, 0x4E4, 0xB00, 0 },
348 0x5,
349 0xAFC8,
350 0x64,
351 0x32,
352 1,
353 0,
354 0x10,
355 { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 },
356 { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 },
357 { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 },
358 85,
359 true
360};
e5c5304f 361#endif
841686df
MB		 362
363static const struct si_dte_data dte_data_tahiti_pro =
364{
365 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
366 { 0x0, 0x0, 0x0, 0x0, 0x0 },
367 5,
368 45000,
369 100,
370 0xA,
371 1,
372 0,
373 0x10,
374 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
375 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
376 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
377 90,
378 true
379};
380
381static const struct si_dte_data dte_data_new_zealand =
382{
383 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
384 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
385 0x5,
386 0xAFC8,
387 0x69,
388 0x32,
389 1,
390 0,
391 0x10,
392 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
393 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
394 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
395 85,
396 true
397};
398
399static const struct si_dte_data dte_data_aruba_pro =
400{
401 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
402 { 0x0, 0x0, 0x0, 0x0, 0x0 },
403 5,
404 45000,
405 100,
406 0xA,
407 1,
408 0,
409 0x10,
410 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
411 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
412 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
413 90,
414 true
415};
416
417static const struct si_dte_data dte_data_malta =
418{
419 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
420 { 0x0, 0x0, 0x0, 0x0, 0x0 },
421 5,
422 45000,
423 100,
424 0xA,
425 1,
426 0,
427 0x10,
428 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
429 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
430 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
431 90,
432 true
433};
434
435struct si_cac_config_reg cac_weights_pitcairn[] =
436{
437 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
438 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
439 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
440 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
441 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
442 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
443 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
444 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
445 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
446 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
447 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
448 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
449 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
450 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
451 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
452 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
453 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
454 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
455 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
456 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
457 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
458 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
459 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
460 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
461 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
462 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
463 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
464 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
465 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
466 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
467 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
468 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
469 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
470 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
471 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
472 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
473 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
474 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
475 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
476 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
477 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
478 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
479 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
480 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
481 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
482 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
483 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
484 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
485 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
486 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
487 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
488 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
489 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
490 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
491 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
492 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
493 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
494 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
495 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
496 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
497 { 0xFFFFFFFF }
498};
499
500static const struct si_cac_config_reg lcac_pitcairn[] =
501{
502 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
503 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
504 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
505 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
506 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
507 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
508 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
509 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
510 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
511 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
512 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
513 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
514 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
515 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
516 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
517 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
518 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
519 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
520 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
521 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
522 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
523 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
524 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
525 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
526 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
527 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
528 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
529 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
530 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
531 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
532 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
533 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
534 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
535 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
536 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
537 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
538 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
539 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
540 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
541 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
542 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
543 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
544 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
545 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
546 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
547 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
548 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
549 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
550 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
551 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
552 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
553 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
554 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
555 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
556 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
557 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
558 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
559 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
560 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
561 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
562 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
563 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
564 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
565 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
566 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
567 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
568 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
569 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
570 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
571 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
572 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
573 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
574 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
575 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
576 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
577 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
578 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
579 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
580 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
581 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
582 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
583 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
584 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
585 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
586 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
587 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
588 { 0xFFFFFFFF }
589};
590
591static const struct si_cac_config_reg cac_override_pitcairn[] =
592{
593 { 0xFFFFFFFF }
594};
595
596static const struct si_powertune_data powertune_data_pitcairn =
597{
598 ((1 << 16) | 27027),
599 5,
600 0,
601 6,
602 100,
603 {
604 51600000UL,
605 1800000UL,
606 7194395UL,
607 309631529UL,
608 -1270850L,
609 4513710L,
610 100
611 },
612 117830498UL,
613 12,
614 {
615 0,
616 0,
617 0,
618 0,
619 0,
620 0,
621 0,
622 0
623 },
624 true
625};
626
627static const struct si_dte_data dte_data_pitcairn =
628{
629 { 0, 0, 0, 0, 0 },
630 { 0, 0, 0, 0, 0 },
631 0,
632 0,
633 0,
634 0,
635 0,
636 0,
637 0,
638 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
639 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
640 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
641 0,
642 false
643};
644
645static const struct si_dte_data dte_data_curacao_xt =
646{
647 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
648 { 0x0, 0x0, 0x0, 0x0, 0x0 },
649 5,
650 45000,
651 100,
652 0xA,
653 1,
654 0,
655 0x10,
656 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
657 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
658 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
659 90,
660 true
661};
662
663static const struct si_dte_data dte_data_curacao_pro =
664{
665 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
666 { 0x0, 0x0, 0x0, 0x0, 0x0 },
667 5,
668 45000,
669 100,
670 0xA,
671 1,
672 0,
673 0x10,
674 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
675 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
676 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
677 90,
678 true
679};
680
681static const struct si_dte_data dte_data_neptune_xt =
682{
683 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
684 { 0x0, 0x0, 0x0, 0x0, 0x0 },
685 5,
686 45000,
687 100,
688 0xA,
689 1,
690 0,
691 0x10,
692 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
693 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
694 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
695 90,
696 true
697};
698
699static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
700{
701 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
702 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
703 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
704 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
705 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
706 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
707 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
708 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
709 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
710 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
711 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
712 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
713 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
714 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
715 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
716 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
717 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
718 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
719 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
720 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
721 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
722 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
723 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
724 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
725 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
726 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
727 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
728 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
729 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
730 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
731 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
732 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
733 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
734 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
735 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
736 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
737 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
738 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
739 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
740 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
741 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
742 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
743 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
744 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
745 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
746 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
747 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
748 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
749 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
750 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
751 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
752 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
753 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
754 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
755 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
756 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
757 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
758 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
759 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
760 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
761 { 0xFFFFFFFF }
762};
763
764static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
765{
766 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
767 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
768 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
769 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
770 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
771 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
772 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
773 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
774 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
775 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
776 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
777 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
778 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
779 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
780 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
781 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
782 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
783 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
784 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
785 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
786 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
787 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
788 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
789 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
790 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
791 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
792 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
793 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
794 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
795 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
796 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
797 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
798 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
799 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
800 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
801 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
802 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
803 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
804 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
805 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
806 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
807 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
808 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
809 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
810 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
811 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
812 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
813 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
814 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
815 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
816 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
817 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
818 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
819 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
820 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
821 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
822 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
823 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
824 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
825 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
826 { 0xFFFFFFFF }
827};
828
829static const struct si_cac_config_reg cac_weights_heathrow[] =
830{
831 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
832 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
833 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
834 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
835 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
836 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
837 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
838 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
839 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
840 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
841 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
842 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
843 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
844 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
845 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
846 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
847 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
848 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
849 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
850 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
851 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
852 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
853 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
854 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
855 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
856 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
857 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
858 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
859 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
860 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
861 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
862 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
863 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
864 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
865 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
866 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
867 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
868 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
869 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
870 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
871 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
872 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
873 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
874 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
875 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
876 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
877 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
878 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
879 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
880 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
881 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
882 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
883 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
884 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
885 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
886 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
887 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
888 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
889 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
890 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
891 { 0xFFFFFFFF }
892};
893
894static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
895{
896 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
897 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
898 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
899 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
900 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
901 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
902 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
903 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
904 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
905 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
906 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
907 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
908 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
909 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
910 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
911 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
912 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
913 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
914 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
915 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
916 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
917 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
918 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
919 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
920 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
921 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
922 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
923 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
924 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
925 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
926 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
927 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
928 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
929 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
930 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
931 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
932 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
933 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
934 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
935 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
936 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
937 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
938 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
939 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
940 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
941 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
942 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
943 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
944 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
945 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
946 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
947 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
948 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
949 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
950 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
951 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
952 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
953 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
954 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
955 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
956 { 0xFFFFFFFF }
957};
958
959static const struct si_cac_config_reg cac_weights_cape_verde[] =
960{
961 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
962 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
963 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
964 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
965 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
966 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
967 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
968 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
969 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
970 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
971 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
972 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
973 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
974 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
975 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
976 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
977 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
978 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
979 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
980 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
981 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
982 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
983 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
984 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
985 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
986 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
987 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
988 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
989 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
990 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
991 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
992 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
993 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
994 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
995 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
996 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
997 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
998 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
999 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1000 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1001 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1002 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1003 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1004 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1005 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1006 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1007 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1008 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1009 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1010 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1011 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1012 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1013 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1014 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1015 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1016 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1017 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1018 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1019 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1020 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1021 { 0xFFFFFFFF }
1022};
1023
1024static const struct si_cac_config_reg lcac_cape_verde[] =
1025{
1026 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1027 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1028 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1029 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1030 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1031 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1032 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1033 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1034 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1035 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1036 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1037 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1038 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1039 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1040 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1041 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1042 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1043 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1044 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1045 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1046 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1047 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1048 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1049 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1050 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1051 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1052 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1053 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1054 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1055 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1056 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1057 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1058 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1059 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1060 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1061 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1062 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1063 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1064 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1065 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1066 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1067 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1068 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1069 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1070 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1071 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1072 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1073 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1074 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1075 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1076 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1077 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1078 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1079 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1080 { 0xFFFFFFFF }
1081};
1082
1083static const struct si_cac_config_reg cac_override_cape_verde[] =
1084{
1085 { 0xFFFFFFFF }
1086};
1087
1088static const struct si_powertune_data powertune_data_cape_verde =
1089{
1090 ((1 << 16) | 0x6993),
1091 5,
1092 0,
1093 7,
1094 105,
1095 {
1096 0UL,
1097 0UL,
1098 7194395UL,
1099 309631529UL,
1100 -1270850L,
1101 4513710L,
1102 100
1103 },
1104 117830498UL,
1105 12,
1106 {
1107 0,
1108 0,
1109 0,
1110 0,
1111 0,
1112 0,
1113 0,
1114 0
1115 },
1116 true
1117};
1118
1119static const struct si_dte_data dte_data_cape_verde =
1120{
1121 { 0, 0, 0, 0, 0 },
1122 { 0, 0, 0, 0, 0 },
1123 0,
1124 0,
1125 0,
1126 0,
1127 0,
1128 0,
1129 0,
1130 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1131 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1132 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1133 0,
1134 false
1135};
1136
1137static const struct si_dte_data dte_data_venus_xtx =
1138{
1139 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1140 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1141 5,
1142 55000,
1143 0x69,
1144 0xA,
1145 1,
1146 0,
1147 0x3,
1148 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1149 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1150 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1151 90,
1152 true
1153};
1154
1155static const struct si_dte_data dte_data_venus_xt =
1156{
1157 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1158 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1159 5,
1160 55000,
1161 0x69,
1162 0xA,
1163 1,
1164 0,
1165 0x3,
1166 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1167 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1168 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1169 90,
1170 true
1171};
1172
1173static const struct si_dte_data dte_data_venus_pro =
1174{
1175 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1176 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1177 5,
1178 55000,
1179 0x69,
1180 0xA,
1181 1,
1182 0,
1183 0x3,
1184 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1185 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1186 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1187 90,
1188 true
1189};
1190
1191struct si_cac_config_reg cac_weights_oland[] =
1192{
1193 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1194 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1195 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1196 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1197 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1198 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1199 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1200 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1201 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1202 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1203 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1204 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1205 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1206 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1207 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1208 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1209 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1210 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1211 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1212 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1213 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1214 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1215 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1216 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1217 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1218 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1219 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1220 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1221 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1222 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1223 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1224 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1225 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1226 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1227 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1228 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1229 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1230 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1231 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1232 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1233 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1234 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1235 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1236 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1237 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1238 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1239 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1240 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1241 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1242 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1243 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1244 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1245 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1246 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1247 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1248 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1249 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1250 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1251 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1252 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1253 { 0xFFFFFFFF }
1254};
1255
1256static const struct si_cac_config_reg cac_weights_mars_pro[] =
1257{
1258 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1259 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1260 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1261 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1262 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1263 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1264 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1265 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1266 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1267 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1268 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1269 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1270 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1271 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1272 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1273 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1274 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1275 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1276 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1277 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1278 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1279 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1280 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1281 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1282 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1283 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1284 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1285 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1286 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1287 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1288 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1289 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1290 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1291 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1292 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1293 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1294 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1295 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1296 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1297 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1298 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1299 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1300 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1301 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1302 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1303 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1304 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1305 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1306 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1307 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1308 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1309 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1310 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1311 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1312 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1313 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1314 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1315 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1316 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1317 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1318 { 0xFFFFFFFF }
1319};
1320
1321static const struct si_cac_config_reg cac_weights_mars_xt[] =
1322{
1323 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1324 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1325 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1326 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1327 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1328 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1329 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1330 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1331 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1332 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1333 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1334 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1335 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1336 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1337 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1338 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1339 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1340 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1341 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1342 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1343 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1344 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1345 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1346 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1347 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1348 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1349 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1350 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1351 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1352 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1353 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1354 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1355 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1356 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1357 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1358 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1359 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1360 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1361 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1362 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1363 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1364 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1365 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1366 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1367 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1368 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1369 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1370 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1371 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1372 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1373 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1374 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1375 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1376 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1377 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1378 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1379 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1380 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1381 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1382 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1383 { 0xFFFFFFFF }
1384};
1385
1386static const struct si_cac_config_reg cac_weights_oland_pro[] =
1387{
1388 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1389 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1390 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1391 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1392 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1393 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1394 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1395 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1396 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1397 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1398 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1399 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1400 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1401 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1402 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1403 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1404 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1405 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1406 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1407 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1408 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1409 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1410 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1411 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1412 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1413 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1414 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1415 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1416 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1417 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1418 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1419 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1420 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1421 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1422 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1423 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1424 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1425 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1426 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1427 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1428 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1429 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1430 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1431 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1432 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1433 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1434 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1435 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1436 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1437 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1438 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1439 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1440 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1441 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1442 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1443 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1444 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1445 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1446 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1447 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1448 { 0xFFFFFFFF }
1449};
1450
1451static const struct si_cac_config_reg cac_weights_oland_xt[] =
1452{
1453 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1454 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1455 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1456 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1457 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1458 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1459 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1460 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1461 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1462 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1463 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1464 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1465 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1466 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1467 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1468 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1469 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1470 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1471 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1472 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1473 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1474 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1475 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1476 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1477 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1478 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1479 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1480 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1481 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1482 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1483 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1484 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1485 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1486 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1487 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1488 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1489 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1490 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1491 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1492 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1493 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1494 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1495 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1496 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1497 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1498 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1499 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1500 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1501 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1502 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1503 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1504 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1505 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1506 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1507 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1508 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1509 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1510 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1511 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1512 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1513 { 0xFFFFFFFF }
1514};
1515
1516static const struct si_cac_config_reg lcac_oland[] =
1517{
1518 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1519 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1520 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1521 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1522 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1523 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1524 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1525 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1526 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1527 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1528 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1529 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1530 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1531 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1532 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1533 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1534 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1535 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1536 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1537 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1538 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1539 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1540 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1541 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1542 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1543 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1544 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1545 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1546 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1547 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1548 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1549 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1550 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1551 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1552 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1553 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1554 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1555 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1556 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1557 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1558 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1559 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1560 { 0xFFFFFFFF }
1561};
1562
1563static const struct si_cac_config_reg lcac_mars_pro[] =
1564{
1565 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1566 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1567 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1568 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1569 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1570 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1571 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1572 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1573 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1574 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1575 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1576 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1577 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1578 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1579 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1580 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1581 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1582 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1583 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1584 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1585 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1586 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1587 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1588 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1589 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1590 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1591 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1592 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1593 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1594 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1595 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1596 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1597 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1598 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1599 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1600 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1601 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1602 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1603 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1604 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1605 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1606 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1607 { 0xFFFFFFFF }
1608};
1609
1610static const struct si_cac_config_reg cac_override_oland[] =
1611{
1612 { 0xFFFFFFFF }
1613};
1614
1615static const struct si_powertune_data powertune_data_oland =
1616{
1617 ((1 << 16) | 0x6993),
1618 5,
1619 0,
1620 7,
1621 105,
1622 {
1623 0UL,
1624 0UL,
1625 7194395UL,
1626 309631529UL,
1627 -1270850L,
1628 4513710L,
1629 100
1630 },
1631 117830498UL,
1632 12,
1633 {
1634 0,
1635 0,
1636 0,
1637 0,
1638 0,
1639 0,
1640 0,
1641 0
1642 },
1643 true
1644};
1645
1646static const struct si_powertune_data powertune_data_mars_pro =
1647{
1648 ((1 << 16) | 0x6993),
1649 5,
1650 0,
1651 7,
1652 105,
1653 {
1654 0UL,
1655 0UL,
1656 7194395UL,
1657 309631529UL,
1658 -1270850L,
1659 4513710L,
1660 100
1661 },
1662 117830498UL,
1663 12,
1664 {
1665 0,
1666 0,
1667 0,
1668 0,
1669 0,
1670 0,
1671 0,
1672 0
1673 },
1674 true
1675};
1676
1677static const struct si_dte_data dte_data_oland =
1678{
1679 { 0, 0, 0, 0, 0 },
1680 { 0, 0, 0, 0, 0 },
1681 0,
1682 0,
1683 0,
1684 0,
1685 0,
1686 0,
1687 0,
1688 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1689 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1690 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1691 0,
1692 false
1693};
1694
1695static const struct si_dte_data dte_data_mars_pro =
1696{
1697 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1698 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1699 5,
1700 55000,
1701 105,
1702 0xA,
1703 1,
1704 0,
1705 0x10,
1706 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1707 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1708 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1709 90,
1710 true
1711};
1712
1713static const struct si_dte_data dte_data_sun_xt =
1714{
1715 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1716 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1717 5,
1718 55000,
1719 105,
1720 0xA,
1721 1,
1722 0,
1723 0x10,
1724 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1725 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1726 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1727 90,
1728 true
1729};
1730
1731
1732static const struct si_cac_config_reg cac_weights_hainan[] =
1733{
1734 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1735 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1736 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1737 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1738 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1739 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1740 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1741 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1742 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1743 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1744 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1745 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1746 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1747 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1748 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1749 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1750 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1751 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1752 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1753 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1754 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1755 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1756 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1757 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1758 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1759 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1760 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1761 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1762 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1763 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1764 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1765 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1766 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1767 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1768 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1769 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1770 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1771 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1772 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1773 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1774 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1775 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1776 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1777 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1778 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1779 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1780 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1781 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1782 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1783 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1784 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1785 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1786 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1787 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1788 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1789 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1790 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1791 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1792 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1793 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1794 { 0xFFFFFFFF }
1795};
1796
1797static const struct si_powertune_data powertune_data_hainan =
1798{
1799 ((1 << 16) | 0x6993),
1800 5,
1801 0,
1802 9,
1803 105,
1804 {
1805 0UL,
1806 0UL,
1807 7194395UL,
1808 309631529UL,
1809 -1270850L,
1810 4513710L,
1811 100
1812 },
1813 117830498UL,
1814 12,
1815 {
1816 0,
1817 0,
1818 0,
1819 0,
1820 0,
1821 0,
1822 0,
1823 0
1824 },
1825 true
1826};
1827
1828struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev);
1829struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev);
1830struct ni_power_info *ni_get_pi(struct amdgpu_device *adev);
1831struct si_ps *si_get_ps(struct amdgpu_ps *rps);
1832
1833static int si_populate_voltage_value(struct amdgpu_device *adev,
1834 const struct atom_voltage_table *table,
1835 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1836static int si_get_std_voltage_value(struct amdgpu_device *adev,
1837 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1838 u16 *std_voltage);
1839static int si_write_smc_soft_register(struct amdgpu_device *adev,
1840 u16 reg_offset, u32 value);
1841static int si_convert_power_level_to_smc(struct amdgpu_device *adev,
1842 struct rv7xx_pl *pl,
1843 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1844static int si_calculate_sclk_params(struct amdgpu_device *adev,
1845 u32 engine_clock,
1846 SISLANDS_SMC_SCLK_VALUE *sclk);
1847
1848static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev);
1849static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev);
1850static void si_dpm_set_dpm_funcs(struct amdgpu_device *adev);
1851static void si_dpm_set_irq_funcs(struct amdgpu_device *adev);
1852
1853extern u32 si_pciep_rreg(struct amdgpu_device *adev, u32 reg);
1854
1855static struct si_power_info *si_get_pi(struct amdgpu_device *adev)
1856{
77d318a6
TSD		 1857 struct si_power_info *pi = adev->pm.dpm.priv;
1858 return pi;
841686df
MB		 1859}
1860
1861static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1862 u16 v, s32 t, u32 ileakage, u32 *leakage)
1863{
1864 s64 kt, kv, leakage_w, i_leakage, vddc;
1865 s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1866 s64 tmp;
1867
1868 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1869 vddc = div64_s64(drm_int2fixp(v), 1000);
1870 temperature = div64_s64(drm_int2fixp(t), 1000);
1871
1872 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1873 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1874 av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1875 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1876 t_ref = drm_int2fixp(coeff->t_ref);
1877
1878 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1879 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
1880 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
1881 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1882
1883 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1884
1885 *leakage = drm_fixp2int(leakage_w * 1000);
1886}
1887
1888static void si_calculate_leakage_for_v_and_t(struct amdgpu_device *adev,
1889 const struct ni_leakage_coeffients *coeff,
1890 u16 v,
1891 s32 t,
1892 u32 i_leakage,
1893 u32 *leakage)
1894{
1895 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1896}
1897
1898static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1899 const u32 fixed_kt, u16 v,
1900 u32 ileakage, u32 *leakage)
1901{
1902 s64 kt, kv, leakage_w, i_leakage, vddc;
1903
1904 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1905 vddc = div64_s64(drm_int2fixp(v), 1000);
1906
1907 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1908 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1909 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1910
1911 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1912
1913 *leakage = drm_fixp2int(leakage_w * 1000);
1914}
1915
1916static void si_calculate_leakage_for_v(struct amdgpu_device *adev,
1917 const struct ni_leakage_coeffients *coeff,
1918 const u32 fixed_kt,
1919 u16 v,
1920 u32 i_leakage,
1921 u32 *leakage)
1922{
1923 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1924}
1925
1926
1927static void si_update_dte_from_pl2(struct amdgpu_device *adev,
1928 struct si_dte_data *dte_data)
1929{
1930 u32 p_limit1 = adev->pm.dpm.tdp_limit;
1931 u32 p_limit2 = adev->pm.dpm.near_tdp_limit;
1932 u32 k = dte_data->k;
1933 u32 t_max = dte_data->max_t;
1934 u32 t_split[5] = { 10, 15, 20, 25, 30 };
1935 u32 t_0 = dte_data->t0;
1936 u32 i;
1937
1938 if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1939 dte_data->tdep_count = 3;
1940
1941 for (i = 0; i < k; i++) {
1942 dte_data->r[i] =
1943 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1944 (p_limit2 * (u32)100);
1945 }
1946
1947 dte_data->tdep_r[1] = dte_data->r[4] * 2;
1948
1949 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1950 dte_data->tdep_r[i] = dte_data->r[4];
1951 }
1952 } else {
1953 DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1954 }
1955}
1956
1957struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev)
1958{
77d318a6 1959 struct rv7xx_power_info *pi = adev->pm.dpm.priv;
841686df 1960
77d318a6 1961 return pi;
841686df
MB		 1962}
1963
1964struct ni_power_info *ni_get_pi(struct amdgpu_device *adev)
1965{
77d318a6 1966 struct ni_power_info *pi = adev->pm.dpm.priv;
841686df 1967
77d318a6 1968 return pi;
841686df
MB		 1969}
1970
1971struct si_ps *si_get_ps(struct amdgpu_ps *aps)
1972{
77d318a6 1973 struct si_ps *ps = aps->ps_priv;
841686df 1974
77d318a6 1975 return ps;
841686df
MB		 1976}
1977
1978static void si_initialize_powertune_defaults(struct amdgpu_device *adev)
1979{
1980 struct ni_power_info *ni_pi = ni_get_pi(adev);
1981 struct si_power_info *si_pi = si_get_pi(adev);
1982 bool update_dte_from_pl2 = false;
1983
1984 if (adev->asic_type == CHIP_TAHITI) {
1985 si_pi->cac_weights = cac_weights_tahiti;
1986 si_pi->lcac_config = lcac_tahiti;
1987 si_pi->cac_override = cac_override_tahiti;
1988 si_pi->powertune_data = &powertune_data_tahiti;
1989 si_pi->dte_data = dte_data_tahiti;
1990
1991 switch (adev->pdev->device) {
1992 case 0x6798:
1993 si_pi->dte_data.enable_dte_by_default = true;
1994 break;
1995 case 0x6799:
1996 si_pi->dte_data = dte_data_new_zealand;
1997 break;
1998 case 0x6790:
1999 case 0x6791:
2000 case 0x6792:
2001 case 0x679E:
2002 si_pi->dte_data = dte_data_aruba_pro;
2003 update_dte_from_pl2 = true;
2004 break;
2005 case 0x679B:
2006 si_pi->dte_data = dte_data_malta;
2007 update_dte_from_pl2 = true;
2008 break;
2009 case 0x679A:
2010 si_pi->dte_data = dte_data_tahiti_pro;
2011 update_dte_from_pl2 = true;
2012 break;
2013 default:
2014 if (si_pi->dte_data.enable_dte_by_default == true)
2015 DRM_ERROR("DTE is not enabled!\n");
2016 break;
2017 }
2018 } else if (adev->asic_type == CHIP_PITCAIRN) {
c3d98645
TSD		 2019 si_pi->cac_weights = cac_weights_pitcairn;
2020 si_pi->lcac_config = lcac_pitcairn;
2021 si_pi->cac_override = cac_override_pitcairn;
2022 si_pi->powertune_data = &powertune_data_pitcairn;
2023
841686df
MB		 2024 switch (adev->pdev->device) {
2025 case 0x6810:
2026 case 0x6818:
841686df
MB		 2027 si_pi->dte_data = dte_data_curacao_xt;
2028 update_dte_from_pl2 = true;
2029 break;
2030 case 0x6819:
2031 case 0x6811:
841686df
MB		 2032 si_pi->dte_data = dte_data_curacao_pro;
2033 update_dte_from_pl2 = true;
2034 break;
2035 case 0x6800:
2036 case 0x6806:
841686df
MB		 2037 si_pi->dte_data = dte_data_neptune_xt;
2038 update_dte_from_pl2 = true;
2039 break;
2040 default:
841686df
MB		 2041 si_pi->dte_data = dte_data_pitcairn;
2042 break;
2043 }
2044 } else if (adev->asic_type == CHIP_VERDE) {
2045 si_pi->lcac_config = lcac_cape_verde;
2046 si_pi->cac_override = cac_override_cape_verde;
2047 si_pi->powertune_data = &powertune_data_cape_verde;
2048
2049 switch (adev->pdev->device) {
2050 case 0x683B:
2051 case 0x683F:
2052 case 0x6829:
2053 case 0x6835:
2054 si_pi->cac_weights = cac_weights_cape_verde_pro;
2055 si_pi->dte_data = dte_data_cape_verde;
2056 break;
2057 case 0x682C:
2058 si_pi->cac_weights = cac_weights_cape_verde_pro;
2059 si_pi->dte_data = dte_data_sun_xt;
2060 break;
2061 case 0x6825:
2062 case 0x6827:
2063 si_pi->cac_weights = cac_weights_heathrow;
2064 si_pi->dte_data = dte_data_cape_verde;
2065 break;
2066 case 0x6824:
2067 case 0x682D:
2068 si_pi->cac_weights = cac_weights_chelsea_xt;
2069 si_pi->dte_data = dte_data_cape_verde;
2070 break;
2071 case 0x682F:
2072 si_pi->cac_weights = cac_weights_chelsea_pro;
2073 si_pi->dte_data = dte_data_cape_verde;
2074 break;
2075 case 0x6820:
2076 si_pi->cac_weights = cac_weights_heathrow;
2077 si_pi->dte_data = dte_data_venus_xtx;
2078 break;
2079 case 0x6821:
2080 si_pi->cac_weights = cac_weights_heathrow;
2081 si_pi->dte_data = dte_data_venus_xt;
2082 break;
2083 case 0x6823:
2084 case 0x682B:
2085 case 0x6822:
2086 case 0x682A:
2087 si_pi->cac_weights = cac_weights_chelsea_pro;
2088 si_pi->dte_data = dte_data_venus_pro;
2089 break;
2090 default:
2091 si_pi->cac_weights = cac_weights_cape_verde;
2092 si_pi->dte_data = dte_data_cape_verde;
2093 break;
2094 }
2095 } else if (adev->asic_type == CHIP_OLAND) {
c3d98645
TSD		 2096 si_pi->lcac_config = lcac_mars_pro;
2097 si_pi->cac_override = cac_override_oland;
2098 si_pi->powertune_data = &powertune_data_mars_pro;
2099 si_pi->dte_data = dte_data_mars_pro;
2100
841686df
MB		 2101 switch (adev->pdev->device) {
2102 case 0x6601:
2103 case 0x6621:
2104 case 0x6603:
2105 case 0x6605:
2106 si_pi->cac_weights = cac_weights_mars_pro;
841686df
MB		 2107 update_dte_from_pl2 = true;
2108 break;
2109 case 0x6600:
2110 case 0x6606:
2111 case 0x6620:
2112 case 0x6604:
2113 si_pi->cac_weights = cac_weights_mars_xt;
841686df
MB		 2114 update_dte_from_pl2 = true;
2115 break;
2116 case 0x6611:
2117 case 0x6613:
2118 case 0x6608:
2119 si_pi->cac_weights = cac_weights_oland_pro;
841686df
MB		 2120 update_dte_from_pl2 = true;
2121 break;
2122 case 0x6610:
2123 si_pi->cac_weights = cac_weights_oland_xt;
841686df
MB		 2124 update_dte_from_pl2 = true;
2125 break;
2126 default:
2127 si_pi->cac_weights = cac_weights_oland;
2128 si_pi->lcac_config = lcac_oland;
2129 si_pi->cac_override = cac_override_oland;
2130 si_pi->powertune_data = &powertune_data_oland;
2131 si_pi->dte_data = dte_data_oland;
2132 break;
2133 }
2134 } else if (adev->asic_type == CHIP_HAINAN) {
2135 si_pi->cac_weights = cac_weights_hainan;
2136 si_pi->lcac_config = lcac_oland;
2137 si_pi->cac_override = cac_override_oland;
2138 si_pi->powertune_data = &powertune_data_hainan;
2139 si_pi->dte_data = dte_data_sun_xt;
2140 update_dte_from_pl2 = true;
2141 } else {
2142 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2143 return;
2144 }
2145
2146 ni_pi->enable_power_containment = false;
2147 ni_pi->enable_cac = false;
2148 ni_pi->enable_sq_ramping = false;
2149 si_pi->enable_dte = false;
2150
2151 if (si_pi->powertune_data->enable_powertune_by_default) {
77d318a6 2152 ni_pi->enable_power_containment = true;
841686df
MB		 2153 ni_pi->enable_cac = true;
2154 if (si_pi->dte_data.enable_dte_by_default) {
2155 si_pi->enable_dte = true;
2156 if (update_dte_from_pl2)
2157 si_update_dte_from_pl2(adev, &si_pi->dte_data);
2158
2159 }
2160 ni_pi->enable_sq_ramping = true;
2161 }
2162
2163 ni_pi->driver_calculate_cac_leakage = true;
2164 ni_pi->cac_configuration_required = true;
2165
2166 if (ni_pi->cac_configuration_required) {
2167 ni_pi->support_cac_long_term_average = true;
2168 si_pi->dyn_powertune_data.l2_lta_window_size =
2169 si_pi->powertune_data->l2_lta_window_size_default;
2170 si_pi->dyn_powertune_data.lts_truncate =
2171 si_pi->powertune_data->lts_truncate_default;
2172 } else {
2173 ni_pi->support_cac_long_term_average = false;
2174 si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2175 si_pi->dyn_powertune_data.lts_truncate = 0;
2176 }
2177
2178 si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2179}
2180
2181static u32 si_get_smc_power_scaling_factor(struct amdgpu_device *adev)
2182{
2183 return 1;
2184}
2185
2186static u32 si_calculate_cac_wintime(struct amdgpu_device *adev)
2187{
2188 u32 xclk;
2189 u32 wintime;
2190 u32 cac_window;
2191 u32 cac_window_size;
2192
2193 xclk = amdgpu_asic_get_xclk(adev);
2194
2195 if (xclk == 0)
2196 return 0;
2197
2198 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;
2199 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2200
2201 wintime = (cac_window_size * 100) / xclk;
2202
2203 return wintime;
2204}
2205
2206static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2207{
2208 return power_in_watts;
2209}
2210
2211static int si_calculate_adjusted_tdp_limits(struct amdgpu_device *adev,
2212 bool adjust_polarity,
2213 u32 tdp_adjustment,
2214 u32 *tdp_limit,
2215 u32 *near_tdp_limit)
2216{
2217 u32 adjustment_delta, max_tdp_limit;
2218
2219 if (tdp_adjustment > (u32)adev->pm.dpm.tdp_od_limit)
2220 return -EINVAL;
2221
2222 max_tdp_limit = ((100 + 100) * adev->pm.dpm.tdp_limit) / 100;
2223
2224 if (adjust_polarity) {
2225 *tdp_limit = ((100 + tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100;
2226 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - adev->pm.dpm.tdp_limit);
2227 } else {
2228 *tdp_limit = ((100 - tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100;
2229 adjustment_delta = adev->pm.dpm.tdp_limit - *tdp_limit;
2230 if (adjustment_delta < adev->pm.dpm.near_tdp_limit_adjusted)
2231 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2232 else
2233 *near_tdp_limit = 0;
2234 }
2235
2236 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2237 return -EINVAL;
2238 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2239 return -EINVAL;
2240
2241 return 0;
2242}
2243
2244static int si_populate_smc_tdp_limits(struct amdgpu_device *adev,
2245 struct amdgpu_ps *amdgpu_state)
2246{
2247 struct ni_power_info *ni_pi = ni_get_pi(adev);
2248 struct si_power_info *si_pi = si_get_pi(adev);
2249
2250 if (ni_pi->enable_power_containment) {
2251 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2252 PP_SIslands_PAPMParameters *papm_parm;
2253 struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table;
2254 u32 scaling_factor = si_get_smc_power_scaling_factor(adev);
2255 u32 tdp_limit;
2256 u32 near_tdp_limit;
2257 int ret;
2258
2259 if (scaling_factor == 0)
2260 return -EINVAL;
2261
2262 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2263
2264 ret = si_calculate_adjusted_tdp_limits(adev,
2265 false, /* ??? */
2266 adev->pm.dpm.tdp_adjustment,
2267 &tdp_limit,
2268 &near_tdp_limit);
2269 if (ret)
2270 return ret;
2271
2272 smc_table->dpm2Params.TDPLimit =
2273 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2274 smc_table->dpm2Params.NearTDPLimit =
2275 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2276 smc_table->dpm2Params.SafePowerLimit =
2277 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2278
2279 ret = si_copy_bytes_to_smc(adev,
2280 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2281 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2282 (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2283 sizeof(u32) * 3,
2284 si_pi->sram_end);
2285 if (ret)
2286 return ret;
2287
2288 if (si_pi->enable_ppm) {
2289 papm_parm = &si_pi->papm_parm;
2290 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2291 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2292 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2293 papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2294 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2295 papm_parm->PlatformPowerLimit = 0xffffffff;
2296 papm_parm->NearTDPLimitPAPM = 0xffffffff;
2297
2298 ret = si_copy_bytes_to_smc(adev, si_pi->papm_cfg_table_start,
2299 (u8 *)papm_parm,
2300 sizeof(PP_SIslands_PAPMParameters),
2301 si_pi->sram_end);
2302 if (ret)
2303 return ret;
2304 }
2305 }
2306 return 0;
2307}
2308
2309static int si_populate_smc_tdp_limits_2(struct amdgpu_device *adev,
2310 struct amdgpu_ps *amdgpu_state)
2311{
2312 struct ni_power_info *ni_pi = ni_get_pi(adev);
2313 struct si_power_info *si_pi = si_get_pi(adev);
2314
2315 if (ni_pi->enable_power_containment) {
2316 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2317 u32 scaling_factor = si_get_smc_power_scaling_factor(adev);
2318 int ret;
2319
2320 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2321
2322 smc_table->dpm2Params.NearTDPLimit =
2323 cpu_to_be32(si_scale_power_for_smc(adev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2324 smc_table->dpm2Params.SafePowerLimit =
2325 cpu_to_be32(si_scale_power_for_smc((adev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2326
2327 ret = si_copy_bytes_to_smc(adev,
2328 (si_pi->state_table_start +
2329 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2330 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2331 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2332 sizeof(u32) * 2,
2333 si_pi->sram_end);
2334 if (ret)
2335 return ret;
2336 }
2337
2338 return 0;
2339}
2340
2341static u16 si_calculate_power_efficiency_ratio(struct amdgpu_device *adev,
2342 const u16 prev_std_vddc,
2343 const u16 curr_std_vddc)
2344{
2345 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2346 u64 prev_vddc = (u64)prev_std_vddc;
2347 u64 curr_vddc = (u64)curr_std_vddc;
2348 u64 pwr_efficiency_ratio, n, d;
2349
2350 if ((prev_vddc == 0) || (curr_vddc == 0))
2351 return 0;
2352
2353 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2354 d = prev_vddc * prev_vddc;
2355 pwr_efficiency_ratio = div64_u64(n, d);
2356
2357 if (pwr_efficiency_ratio > (u64)0xFFFF)
2358 return 0;
2359
2360 return (u16)pwr_efficiency_ratio;
2361}
2362
2363static bool si_should_disable_uvd_powertune(struct amdgpu_device *adev,
2364 struct amdgpu_ps *amdgpu_state)
2365{
2366 struct si_power_info *si_pi = si_get_pi(adev);
2367
2368 if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2369 amdgpu_state->vclk && amdgpu_state->dclk)
2370 return true;
2371
2372 return false;
2373}
2374
2375struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev)
2376{
2377 struct evergreen_power_info *pi = adev->pm.dpm.priv;
2378
2379 return pi;
2380}
2381
2382static int si_populate_power_containment_values(struct amdgpu_device *adev,
2383 struct amdgpu_ps *amdgpu_state,
2384 SISLANDS_SMC_SWSTATE *smc_state)
2385{
2386 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
2387 struct ni_power_info *ni_pi = ni_get_pi(adev);
2388 struct si_ps *state = si_get_ps(amdgpu_state);
2389 SISLANDS_SMC_VOLTAGE_VALUE vddc;
2390 u32 prev_sclk;
2391 u32 max_sclk;
2392 u32 min_sclk;
2393 u16 prev_std_vddc;
2394 u16 curr_std_vddc;
2395 int i;
2396 u16 pwr_efficiency_ratio;
2397 u8 max_ps_percent;
2398 bool disable_uvd_power_tune;
2399 int ret;
2400
2401 if (ni_pi->enable_power_containment == false)
2402 return 0;
2403
2404 if (state->performance_level_count == 0)
2405 return -EINVAL;
2406
2407 if (smc_state->levelCount != state->performance_level_count)
2408 return -EINVAL;
2409
2410 disable_uvd_power_tune = si_should_disable_uvd_powertune(adev, amdgpu_state);
2411
2412 smc_state->levels[0].dpm2.MaxPS = 0;
2413 smc_state->levels[0].dpm2.NearTDPDec = 0;
2414 smc_state->levels[0].dpm2.AboveSafeInc = 0;
2415 smc_state->levels[0].dpm2.BelowSafeInc = 0;
2416 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2417
2418 for (i = 1; i < state->performance_level_count; i++) {
2419 prev_sclk = state->performance_levels[i-1].sclk;
2420 max_sclk = state->performance_levels[i].sclk;
2421 if (i == 1)
2422 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2423 else
2424 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2425
2426 if (prev_sclk > max_sclk)
2427 return -EINVAL;
2428
2429 if ((max_ps_percent == 0) ||
2430 (prev_sclk == max_sclk) ||
77d318a6 2431 disable_uvd_power_tune)
841686df 2432 min_sclk = max_sclk;
77d318a6 2433 else if (i == 1)
841686df 2434 min_sclk = prev_sclk;
77d318a6 2435 else
841686df 2436 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
841686df
MB		 2437
2438 if (min_sclk < state->performance_levels[0].sclk)
2439 min_sclk = state->performance_levels[0].sclk;
2440
2441 if (min_sclk == 0)
2442 return -EINVAL;
2443
2444 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
2445 state->performance_levels[i-1].vddc, &vddc);
2446 if (ret)
2447 return ret;
2448
2449 ret = si_get_std_voltage_value(adev, &vddc, &prev_std_vddc);
2450 if (ret)
2451 return ret;
2452
2453 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
2454 state->performance_levels[i].vddc, &vddc);
2455 if (ret)
2456 return ret;
2457
2458 ret = si_get_std_voltage_value(adev, &vddc, &curr_std_vddc);
2459 if (ret)
2460 return ret;
2461
2462 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(adev,
2463 prev_std_vddc, curr_std_vddc);
2464
2465 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2466 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2467 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2468 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2469 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2470 }
2471
2472 return 0;
2473}
2474
2475static int si_populate_sq_ramping_values(struct amdgpu_device *adev,
2476 struct amdgpu_ps *amdgpu_state,
2477 SISLANDS_SMC_SWSTATE *smc_state)
2478{
2479 struct ni_power_info *ni_pi = ni_get_pi(adev);
2480 struct si_ps *state = si_get_ps(amdgpu_state);
2481 u32 sq_power_throttle, sq_power_throttle2;
2482 bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2483 int i;
2484
2485 if (state->performance_level_count == 0)
2486 return -EINVAL;
2487
2488 if (smc_state->levelCount != state->performance_level_count)
2489 return -EINVAL;
2490
2491 if (adev->pm.dpm.sq_ramping_threshold == 0)
2492 return -EINVAL;
2493
2494 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT))
2495 enable_sq_ramping = false;
2496
2497 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT))
2498 enable_sq_ramping = false;
2499
2500 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT))
2501 enable_sq_ramping = false;
2502
2503 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2504 enable_sq_ramping = false;
2505
2506 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2507 enable_sq_ramping = false;
2508
2509 for (i = 0; i < state->performance_level_count; i++) {
2510 sq_power_throttle = 0;
2511 sq_power_throttle2 = 0;
2512
2513 if ((state->performance_levels[i].sclk >= adev->pm.dpm.sq_ramping_threshold) &&
2514 enable_sq_ramping) {
2515 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER);
2516 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER);
2517 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA);
2518 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE);
2519 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO);
2520 } else {
2521 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK;
2522 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
2523 }
2524
2525 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2526 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2527 }
2528
2529 return 0;
2530}
2531
2532static int si_enable_power_containment(struct amdgpu_device *adev,
2533 struct amdgpu_ps *amdgpu_new_state,
2534 bool enable)
2535{
2536 struct ni_power_info *ni_pi = ni_get_pi(adev);
2537 PPSMC_Result smc_result;
2538 int ret = 0;
2539
2540 if (ni_pi->enable_power_containment) {
2541 if (enable) {
2542 if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {
2543 smc_result = si_send_msg_to_smc(adev, PPSMC_TDPClampingActive);
2544 if (smc_result != PPSMC_Result_OK) {
2545 ret = -EINVAL;
2546 ni_pi->pc_enabled = false;
2547 } else {
2548 ni_pi->pc_enabled = true;
2549 }
2550 }
2551 } else {
2552 smc_result = si_send_msg_to_smc(adev, PPSMC_TDPClampingInactive);
2553 if (smc_result != PPSMC_Result_OK)
2554 ret = -EINVAL;
2555 ni_pi->pc_enabled = false;
2556 }
2557 }
2558
2559 return ret;
2560}
2561
2562static int si_initialize_smc_dte_tables(struct amdgpu_device *adev)
2563{
2564 struct si_power_info *si_pi = si_get_pi(adev);
2565 int ret = 0;
2566 struct si_dte_data *dte_data = &si_pi->dte_data;
2567 Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2568 u32 table_size;
2569 u8 tdep_count;
2570 u32 i;
2571
2572 if (dte_data == NULL)
2573 si_pi->enable_dte = false;
2574
2575 if (si_pi->enable_dte == false)
2576 return 0;
2577
2578 if (dte_data->k <= 0)
2579 return -EINVAL;
2580
2581 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL);
2582 if (dte_tables == NULL) {
2583 si_pi->enable_dte = false;
2584 return -ENOMEM;
2585 }
2586
2587 table_size = dte_data->k;
2588
2589 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2590 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2591
2592 tdep_count = dte_data->tdep_count;
2593 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2594 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2595
2596 dte_tables->K = cpu_to_be32(table_size);
2597 dte_tables->T0 = cpu_to_be32(dte_data->t0);
2598 dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2599 dte_tables->WindowSize = dte_data->window_size;
2600 dte_tables->temp_select = dte_data->temp_select;
2601 dte_tables->DTE_mode = dte_data->dte_mode;
2602 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2603
2604 if (tdep_count > 0)
2605 table_size--;
2606
2607 for (i = 0; i < table_size; i++) {
2608 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2609 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]);
2610 }
2611
2612 dte_tables->Tdep_count = tdep_count;
2613
2614 for (i = 0; i < (u32)tdep_count; i++) {
2615 dte_tables->T_limits[i] = dte_data->t_limits[i];
2616 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2617 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2618 }
2619
2620 ret = si_copy_bytes_to_smc(adev, si_pi->dte_table_start, (u8 *)dte_tables,
2621 sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end);
2622 kfree(dte_tables);
2623
2624 return ret;
2625}
2626
2627static int si_get_cac_std_voltage_max_min(struct amdgpu_device *adev,
2628 u16 *max, u16 *min)
2629{
2630 struct si_power_info *si_pi = si_get_pi(adev);
2631 struct amdgpu_cac_leakage_table *table =
2632 &adev->pm.dpm.dyn_state.cac_leakage_table;
2633 u32 i;
2634 u32 v0_loadline;
2635
841686df
MB		 2636 if (table == NULL)
2637 return -EINVAL;
2638
2639 *max = 0;
2640 *min = 0xFFFF;
2641
2642 for (i = 0; i < table->count; i++) {
2643 if (table->entries[i].vddc > *max)
2644 *max = table->entries[i].vddc;
2645 if (table->entries[i].vddc < *min)
2646 *min = table->entries[i].vddc;
2647 }
2648
2649 if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2650 return -EINVAL;
2651
2652 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2653
2654 if (v0_loadline > 0xFFFFUL)
2655 return -EINVAL;
2656
2657 *min = (u16)v0_loadline;
2658
2659 if ((*min > *max) || (*max == 0) || (*min == 0))
2660 return -EINVAL;
2661
2662 return 0;
2663}
2664
2665static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2666{
2667 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2668 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2669}
2670
2671static int si_init_dte_leakage_table(struct amdgpu_device *adev,
2672 PP_SIslands_CacConfig *cac_tables,
2673 u16 vddc_max, u16 vddc_min, u16 vddc_step,
2674 u16 t0, u16 t_step)
2675{
2676 struct si_power_info *si_pi = si_get_pi(adev);
2677 u32 leakage;
2678 unsigned int i, j;
2679 s32 t;
2680 u32 smc_leakage;
2681 u32 scaling_factor;
2682 u16 voltage;
2683
2684 scaling_factor = si_get_smc_power_scaling_factor(adev);
2685
2686 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2687 t = (1000 * (i * t_step + t0));
2688
2689 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2690 voltage = vddc_max - (vddc_step * j);
2691
2692 si_calculate_leakage_for_v_and_t(adev,
2693 &si_pi->powertune_data->leakage_coefficients,
2694 voltage,
2695 t,
2696 si_pi->dyn_powertune_data.cac_leakage,
2697 &leakage);
2698
2699 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2700
2701 if (smc_leakage > 0xFFFF)
2702 smc_leakage = 0xFFFF;
2703
2704 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2705 cpu_to_be16((u16)smc_leakage);
2706 }
2707 }
2708 return 0;
2709}
2710
2711static int si_init_simplified_leakage_table(struct amdgpu_device *adev,
2712 PP_SIslands_CacConfig *cac_tables,
2713 u16 vddc_max, u16 vddc_min, u16 vddc_step)
2714{
2715 struct si_power_info *si_pi = si_get_pi(adev);
2716 u32 leakage;
2717 unsigned int i, j;
2718 u32 smc_leakage;
2719 u32 scaling_factor;
2720 u16 voltage;
2721
2722 scaling_factor = si_get_smc_power_scaling_factor(adev);
2723
2724 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2725 voltage = vddc_max - (vddc_step * j);
2726
2727 si_calculate_leakage_for_v(adev,
2728 &si_pi->powertune_data->leakage_coefficients,
2729 si_pi->powertune_data->fixed_kt,
2730 voltage,
2731 si_pi->dyn_powertune_data.cac_leakage,
2732 &leakage);
2733
2734 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2735
2736 if (smc_leakage > 0xFFFF)
2737 smc_leakage = 0xFFFF;
2738
2739 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2740 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2741 cpu_to_be16((u16)smc_leakage);
2742 }
2743 return 0;
2744}
2745
2746static int si_initialize_smc_cac_tables(struct amdgpu_device *adev)
2747{
2748 struct ni_power_info *ni_pi = ni_get_pi(adev);
2749 struct si_power_info *si_pi = si_get_pi(adev);
2750 PP_SIslands_CacConfig *cac_tables = NULL;
2751 u16 vddc_max, vddc_min, vddc_step;
2752 u16 t0, t_step;
2753 u32 load_line_slope, reg;
2754 int ret = 0;
2755 u32 ticks_per_us = amdgpu_asic_get_xclk(adev) / 100;
2756
2757 if (ni_pi->enable_cac == false)
2758 return 0;
2759
2760 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL);
2761 if (!cac_tables)
2762 return -ENOMEM;
2763
2764 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
2765 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);
2766 WREG32(CG_CAC_CTRL, reg);
2767
2768 si_pi->dyn_powertune_data.cac_leakage = adev->pm.dpm.cac_leakage;
2769 si_pi->dyn_powertune_data.dc_pwr_value =
2770 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2771 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(adev);
2772 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2773
2774 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2775
2776 ret = si_get_cac_std_voltage_max_min(adev, &vddc_max, &vddc_min);
2777 if (ret)
2778 goto done_free;
2779
2780 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2781 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2782 t_step = 4;
2783 t0 = 60;
2784
2785 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2786 ret = si_init_dte_leakage_table(adev, cac_tables,
2787 vddc_max, vddc_min, vddc_step,
2788 t0, t_step);
2789 else
2790 ret = si_init_simplified_leakage_table(adev, cac_tables,
2791 vddc_max, vddc_min, vddc_step);
2792 if (ret)
2793 goto done_free;
2794
2795 load_line_slope = ((u32)adev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2796
2797 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2798 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2799 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2800 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2801 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2802 cac_tables->R_LL = cpu_to_be32(load_line_slope);
2803 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2804 cac_tables->calculation_repeats = cpu_to_be32(2);
2805 cac_tables->dc_cac = cpu_to_be32(0);
2806 cac_tables->log2_PG_LKG_SCALE = 12;
2807 cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2808 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2809 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2810
2811 ret = si_copy_bytes_to_smc(adev, si_pi->cac_table_start, (u8 *)cac_tables,
2812 sizeof(PP_SIslands_CacConfig), si_pi->sram_end);
2813
2814 if (ret)
2815 goto done_free;
2816
2817 ret = si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2818
2819done_free:
2820 if (ret) {
2821 ni_pi->enable_cac = false;
2822 ni_pi->enable_power_containment = false;
2823 }
2824
2825 kfree(cac_tables);
2826
2827 return 0;
2828}
2829
2830static int si_program_cac_config_registers(struct amdgpu_device *adev,
2831 const struct si_cac_config_reg *cac_config_regs)
2832{
2833 const struct si_cac_config_reg *config_regs = cac_config_regs;
2834 u32 data = 0, offset;
2835
2836 if (!config_regs)
2837 return -EINVAL;
2838
2839 while (config_regs->offset != 0xFFFFFFFF) {
2840 switch (config_regs->type) {
2841 case SISLANDS_CACCONFIG_CGIND:
2842 offset = SMC_CG_IND_START + config_regs->offset;
2843 if (offset < SMC_CG_IND_END)
2844 data = RREG32_SMC(offset);
2845 break;
2846 default:
2847 data = RREG32(config_regs->offset);
2848 break;
2849 }
2850
2851 data &= ~config_regs->mask;
2852 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2853
2854 switch (config_regs->type) {
2855 case SISLANDS_CACCONFIG_CGIND:
2856 offset = SMC_CG_IND_START + config_regs->offset;
2857 if (offset < SMC_CG_IND_END)
2858 WREG32_SMC(offset, data);
2859 break;
2860 default:
2861 WREG32(config_regs->offset, data);
2862 break;
2863 }
2864 config_regs++;
2865 }
2866 return 0;
2867}
2868
2869static int si_initialize_hardware_cac_manager(struct amdgpu_device *adev)
2870{
2871 struct ni_power_info *ni_pi = ni_get_pi(adev);
2872 struct si_power_info *si_pi = si_get_pi(adev);
2873 int ret;
2874
2875 if ((ni_pi->enable_cac == false) ||
2876 (ni_pi->cac_configuration_required == false))
2877 return 0;
2878
2879 ret = si_program_cac_config_registers(adev, si_pi->lcac_config);
2880 if (ret)
2881 return ret;
2882 ret = si_program_cac_config_registers(adev, si_pi->cac_override);
2883 if (ret)
2884 return ret;
2885 ret = si_program_cac_config_registers(adev, si_pi->cac_weights);
2886 if (ret)
2887 return ret;
2888
2889 return 0;
2890}
2891
2892static int si_enable_smc_cac(struct amdgpu_device *adev,
2893 struct amdgpu_ps *amdgpu_new_state,
2894 bool enable)
2895{
2896 struct ni_power_info *ni_pi = ni_get_pi(adev);
2897 struct si_power_info *si_pi = si_get_pi(adev);
2898 PPSMC_Result smc_result;
2899 int ret = 0;
2900
2901 if (ni_pi->enable_cac) {
2902 if (enable) {
2903 if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {
2904 if (ni_pi->support_cac_long_term_average) {
2905 smc_result = si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgEnable);
2906 if (smc_result != PPSMC_Result_OK)
2907 ni_pi->support_cac_long_term_average = false;
2908 }
2909
2910 smc_result = si_send_msg_to_smc(adev, PPSMC_MSG_EnableCac);
2911 if (smc_result != PPSMC_Result_OK) {
2912 ret = -EINVAL;
2913 ni_pi->cac_enabled = false;
2914 } else {
2915 ni_pi->cac_enabled = true;
2916 }
2917
2918 if (si_pi->enable_dte) {
2919 smc_result = si_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE);
2920 if (smc_result != PPSMC_Result_OK)
2921 ret = -EINVAL;
2922 }
2923 }
2924 } else if (ni_pi->cac_enabled) {
2925 if (si_pi->enable_dte)
2926 smc_result = si_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE);
2927
2928 smc_result = si_send_msg_to_smc(adev, PPSMC_MSG_DisableCac);
2929
2930 ni_pi->cac_enabled = false;
2931
2932 if (ni_pi->support_cac_long_term_average)
2933 smc_result = si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgDisable);
2934 }
2935 }
2936 return ret;
2937}
2938
2939static int si_init_smc_spll_table(struct amdgpu_device *adev)
2940{
2941 struct ni_power_info *ni_pi = ni_get_pi(adev);
2942 struct si_power_info *si_pi = si_get_pi(adev);
2943 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2944 SISLANDS_SMC_SCLK_VALUE sclk_params;
2945 u32 fb_div, p_div;
2946 u32 clk_s, clk_v;
2947 u32 sclk = 0;
2948 int ret = 0;
2949 u32 tmp;
2950 int i;
2951
2952 if (si_pi->spll_table_start == 0)
2953 return -EINVAL;
2954
2955 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2956 if (spll_table == NULL)
2957 return -ENOMEM;
2958
2959 for (i = 0; i < 256; i++) {
2960 ret = si_calculate_sclk_params(adev, sclk, &sclk_params);
2961 if (ret)
2962 break;
2963 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
2964 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2965 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2966 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2967
2968 fb_div &= ~0x00001FFF;
2969 fb_div >>= 1;
2970 clk_v >>= 6;
2971
2972 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2973 ret = -EINVAL;
2974 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2975 ret = -EINVAL;
2976 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2977 ret = -EINVAL;
2978 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2979 ret = -EINVAL;
2980
2981 if (ret)
2982 break;
2983
2984 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2985 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2986 spll_table->freq[i] = cpu_to_be32(tmp);
2987
2988 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2989 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2990 spll_table->ss[i] = cpu_to_be32(tmp);
2991
2992 sclk += 512;
2993 }
2994
2995
2996 if (!ret)
2997 ret = si_copy_bytes_to_smc(adev, si_pi->spll_table_start,
2998 (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
2999 si_pi->sram_end);
3000
3001 if (ret)
3002 ni_pi->enable_power_containment = false;
3003
3004 kfree(spll_table);
3005
3006 return ret;
3007}
3008
3009struct si_dpm_quirk {
3010 u32 chip_vendor;
3011 u32 chip_device;
3012 u32 subsys_vendor;
3013 u32 subsys_device;
3014 u32 max_sclk;
3015 u32 max_mclk;
3016};
3017
3018/* cards with dpm stability problems */
3019static struct si_dpm_quirk si_dpm_quirk_list[] = {
3020 /* PITCAIRN - https://bugs.freedesktop.org/show_bug.cgi?id=76490 */
3021 { PCI_VENDOR_ID_ATI, 0x6810, 0x1462, 0x3036, 0, 120000 },
3022 { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0xe271, 0, 120000 },
3023 { PCI_VENDOR_ID_ATI, 0x6810, 0x174b, 0xe271, 85000, 90000 },
3024 { PCI_VENDOR_ID_ATI, 0x6811, 0x1462, 0x2015, 0, 120000 },
3025 { PCI_VENDOR_ID_ATI, 0x6811, 0x1043, 0x2015, 0, 120000 },
3026 { 0, 0, 0, 0 },
3027};
3028
3029static u16 si_get_lower_of_leakage_and_vce_voltage(struct amdgpu_device *adev,
3030 u16 vce_voltage)
3031{
3032 u16 highest_leakage = 0;
3033 struct si_power_info *si_pi = si_get_pi(adev);
3034 int i;
3035
3036 for (i = 0; i < si_pi->leakage_voltage.count; i++){
3037 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage)
3038 highest_leakage = si_pi->leakage_voltage.entries[i].voltage;
3039 }
3040
3041 if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage))
3042 return highest_leakage;
3043
3044 return vce_voltage;
3045}
3046
3047static int si_get_vce_clock_voltage(struct amdgpu_device *adev,
3048 u32 evclk, u32 ecclk, u16 *voltage)
3049{
3050 u32 i;
3051 int ret = -EINVAL;
3052 struct amdgpu_vce_clock_voltage_dependency_table *table =
3053 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
3054
3055 if (((evclk == 0) && (ecclk == 0)) ||
3056 (table && (table->count == 0))) {
3057 *voltage = 0;
3058 return 0;
3059 }
3060
3061 for (i = 0; i < table->count; i++) {
3062 if ((evclk <= table->entries[i].evclk) &&
3063 (ecclk <= table->entries[i].ecclk)) {
3064 *voltage = table->entries[i].v;
3065 ret = 0;
3066 break;
3067 }
3068 }
3069
3070 /* if no match return the highest voltage */
3071 if (ret)
3072 *voltage = table->entries[table->count - 1].v;
3073
3074 *voltage = si_get_lower_of_leakage_and_vce_voltage(adev, *voltage);
3075
3076 return ret;
3077}
3078
3079static bool si_dpm_vblank_too_short(struct amdgpu_device *adev)
3080{
3081
77d318a6
TSD		 3082 u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
3083 /* we never hit the non-gddr5 limit so disable it */
3084 u32 switch_limit = adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 0;
841686df 3085
77d318a6
TSD		 3086 if (vblank_time < switch_limit)
3087 return true;
3088 else
3089 return false;
841686df
MB		 3090
3091}
3092
3093static int ni_copy_and_switch_arb_sets(struct amdgpu_device *adev,
3094 u32 arb_freq_src, u32 arb_freq_dest)
3095{
3096 u32 mc_arb_dram_timing;
3097 u32 mc_arb_dram_timing2;
3098 u32 burst_time;
3099 u32 mc_cg_config;
3100
3101 switch (arb_freq_src) {
77d318a6 3102 case MC_CG_ARB_FREQ_F0:
841686df
MB		 3103 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING);
3104 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
3105 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE0_MASK) >> STATE0_SHIFT;
3106 break;
77d318a6 3107 case MC_CG_ARB_FREQ_F1:
841686df
MB		 3108 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_1);
3109 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_1);
3110 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE1_MASK) >> STATE1_SHIFT;
3111 break;
77d318a6 3112 case MC_CG_ARB_FREQ_F2:
841686df
MB		 3113 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_2);
3114 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_2);
3115 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE2_MASK) >> STATE2_SHIFT;
3116 break;
77d318a6 3117 case MC_CG_ARB_FREQ_F3:
841686df
MB		 3118 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_3);
3119 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_3);
3120 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE3_MASK) >> STATE3_SHIFT;
3121 break;
77d318a6 3122 default:
841686df
MB		 3123 return -EINVAL;
3124 }
3125
3126 switch (arb_freq_dest) {
77d318a6 3127 case MC_CG_ARB_FREQ_F0:
841686df
MB		 3128 WREG32(MC_ARB_DRAM_TIMING, mc_arb_dram_timing);
3129 WREG32(MC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
3130 WREG32_P(MC_ARB_BURST_TIME, STATE0(burst_time), ~STATE0_MASK);
3131 break;
77d318a6 3132 case MC_CG_ARB_FREQ_F1:
841686df
MB		 3133 WREG32(MC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
3134 WREG32(MC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
3135 WREG32_P(MC_ARB_BURST_TIME, STATE1(burst_time), ~STATE1_MASK);
3136 break;
77d318a6 3137 case MC_CG_ARB_FREQ_F2:
841686df
MB		 3138 WREG32(MC_ARB_DRAM_TIMING_2, mc_arb_dram_timing);
3139 WREG32(MC_ARB_DRAM_TIMING2_2, mc_arb_dram_timing2);
3140 WREG32_P(MC_ARB_BURST_TIME, STATE2(burst_time), ~STATE2_MASK);
3141 break;
77d318a6 3142 case MC_CG_ARB_FREQ_F3:
841686df
MB		 3143 WREG32(MC_ARB_DRAM_TIMING_3, mc_arb_dram_timing);
3144 WREG32(MC_ARB_DRAM_TIMING2_3, mc_arb_dram_timing2);
3145 WREG32_P(MC_ARB_BURST_TIME, STATE3(burst_time), ~STATE3_MASK);
3146 break;
3147 default:
3148 return -EINVAL;
3149 }
3150
3151 mc_cg_config = RREG32(MC_CG_CONFIG) | 0x0000000F;
3152 WREG32(MC_CG_CONFIG, mc_cg_config);
3153 WREG32_P(MC_ARB_CG, CG_ARB_REQ(arb_freq_dest), ~CG_ARB_REQ_MASK);
3154
3155 return 0;
3156}
3157
3158static void ni_update_current_ps(struct amdgpu_device *adev,
3159 struct amdgpu_ps *rps)
3160{
77d318a6 3161 struct si_ps *new_ps = si_get_ps(rps);
841686df 3162 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
77d318a6 3163 struct ni_power_info *ni_pi = ni_get_pi(adev);
841686df
MB		 3164
3165 eg_pi->current_rps = *rps;
3166 ni_pi->current_ps = *new_ps;
3167 eg_pi->current_rps.ps_priv = &ni_pi->current_ps;
3168}
3169
3170static void ni_update_requested_ps(struct amdgpu_device *adev,
3171 struct amdgpu_ps *rps)
3172{
77d318a6 3173 struct si_ps *new_ps = si_get_ps(rps);
841686df 3174 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
77d318a6 3175 struct ni_power_info *ni_pi = ni_get_pi(adev);
841686df
MB		 3176
3177 eg_pi->requested_rps = *rps;
3178 ni_pi->requested_ps = *new_ps;
3179 eg_pi->requested_rps.ps_priv = &ni_pi->requested_ps;
3180}
3181
3182static void ni_set_uvd_clock_before_set_eng_clock(struct amdgpu_device *adev,
3183 struct amdgpu_ps *new_ps,
3184 struct amdgpu_ps *old_ps)
3185{
77d318a6
TSD		 3186 struct si_ps *new_state = si_get_ps(new_ps);
3187 struct si_ps *current_state = si_get_ps(old_ps);
841686df
MB		 3188
3189 if ((new_ps->vclk == old_ps->vclk) &&
3190 (new_ps->dclk == old_ps->dclk))
3191 return;
3192
3193 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >=
3194 current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3195 return;
3196
3197 amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);
3198}
3199
3200static void ni_set_uvd_clock_after_set_eng_clock(struct amdgpu_device *adev,
3201 struct amdgpu_ps *new_ps,
3202 struct amdgpu_ps *old_ps)
3203{
77d318a6
TSD		 3204 struct si_ps *new_state = si_get_ps(new_ps);
3205 struct si_ps *current_state = si_get_ps(old_ps);
841686df
MB		 3206
3207 if ((new_ps->vclk == old_ps->vclk) &&
3208 (new_ps->dclk == old_ps->dclk))
3209 return;
3210
3211 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk <
3212 current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3213 return;
3214
3215 amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);
3216}
3217
3218static u16 btc_find_voltage(struct atom_voltage_table *table, u16 voltage)
3219{
77d318a6 3220 unsigned int i;
841686df 3221
77d318a6
TSD		 3222 for (i = 0; i < table->count; i++)
3223 if (voltage <= table->entries[i].value)
3224 return table->entries[i].value;
841686df 3225
77d318a6 3226 return table->entries[table->count - 1].value;
841686df
MB		 3227}
3228
3229static u32 btc_find_valid_clock(struct amdgpu_clock_array *clocks,
77d318a6 3230 u32 max_clock, u32 requested_clock)
841686df 3231{
77d318a6 3232 unsigned int i;
841686df 3233
77d318a6
TSD		 3234 if ((clocks == NULL) || (clocks->count == 0))
3235 return (requested_clock < max_clock) ? requested_clock : max_clock;
841686df 3236
77d318a6
TSD		 3237 for (i = 0; i < clocks->count; i++) {
3238 if (clocks->values[i] >= requested_clock)
3239 return (clocks->values[i] < max_clock) ? clocks->values[i] : max_clock;
3240 }
841686df 3241
77d318a6
TSD		 3242 return (clocks->values[clocks->count - 1] < max_clock) ?
3243 clocks->values[clocks->count - 1] : max_clock;
841686df
MB		 3244}
3245
3246static u32 btc_get_valid_mclk(struct amdgpu_device *adev,
77d318a6 3247 u32 max_mclk, u32 requested_mclk)
841686df 3248{
77d318a6
TSD		 3249 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_mclk_values,
3250 max_mclk, requested_mclk);
841686df
MB		 3251}
3252
3253static u32 btc_get_valid_sclk(struct amdgpu_device *adev,
77d318a6 3254 u32 max_sclk, u32 requested_sclk)
841686df 3255{
77d318a6
TSD		 3256 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_sclk_values,
3257 max_sclk, requested_sclk);
841686df
MB		 3258}
3259
3260void btc_get_max_clock_from_voltage_dependency_table(struct amdgpu_clock_voltage_dependency_table *table,
77d318a6 3261 u32 *max_clock)
841686df 3262{
77d318a6 3263 u32 i, clock = 0;
841686df 3264
77d318a6
TSD		 3265 if ((table == NULL) || (table->count == 0)) {
3266 *max_clock = clock;
3267 return;
3268 }
841686df 3269
77d318a6
TSD		 3270 for (i = 0; i < table->count; i++) {
3271 if (clock < table->entries[i].clk)
3272 clock = table->entries[i].clk;
3273 }
3274 *max_clock = clock;
841686df
MB		 3275}
3276
3277static void btc_apply_voltage_dependency_rules(struct amdgpu_clock_voltage_dependency_table *table,
77d318a6 3278 u32 clock, u16 max_voltage, u16 *voltage)
841686df 3279{
77d318a6 3280 u32 i;
841686df 3281
77d318a6
TSD		 3282 if ((table == NULL) || (table->count == 0))
3283 return;
841686df 3284
77d318a6
TSD		 3285 for (i= 0; i < table->count; i++) {
3286 if (clock <= table->entries[i].clk) {
3287 if (*voltage < table->entries[i].v)
3288 *voltage = (u16)((table->entries[i].v < max_voltage) ?
3289 table->entries[i].v : max_voltage);
3290 return;
3291 }
3292 }
841686df 3293
77d318a6 3294 *voltage = (*voltage > max_voltage) ? *voltage : max_voltage;
841686df
MB		 3295}
3296
3297static void btc_adjust_clock_combinations(struct amdgpu_device *adev,
77d318a6
TSD		 3298 const struct amdgpu_clock_and_voltage_limits *max_limits,
3299 struct rv7xx_pl *pl)
841686df
MB		 3300{
3301
77d318a6
TSD		 3302 if ((pl->mclk == 0) || (pl->sclk == 0))
3303 return;
841686df 3304
77d318a6
TSD		 3305 if (pl->mclk == pl->sclk)
3306 return;
841686df 3307
77d318a6
TSD		 3308 if (pl->mclk > pl->sclk) {
3309 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > adev->pm.dpm.dyn_state.mclk_sclk_ratio)
3310 pl->sclk = btc_get_valid_sclk(adev,
3311 max_limits->sclk,
3312 (pl->mclk +
3313 (adev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) /
3314 adev->pm.dpm.dyn_state.mclk_sclk_ratio);
3315 } else {
3316 if ((pl->sclk - pl->mclk) > adev->pm.dpm.dyn_state.sclk_mclk_delta)
3317 pl->mclk = btc_get_valid_mclk(adev,
3318 max_limits->mclk,
3319 pl->sclk -
3320 adev->pm.dpm.dyn_state.sclk_mclk_delta);
3321 }
841686df
MB		 3322}
3323
3324static void btc_apply_voltage_delta_rules(struct amdgpu_device *adev,
77d318a6
TSD		 3325 u16 max_vddc, u16 max_vddci,
3326 u16 *vddc, u16 *vddci)
3327{
3328 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3329 u16 new_voltage;
3330
3331 if ((0 == *vddc) || (0 == *vddci))
3332 return;
3333
3334 if (*vddc > *vddci) {
3335 if ((*vddc - *vddci) > adev->pm.dpm.dyn_state.vddc_vddci_delta) {
3336 new_voltage = btc_find_voltage(&eg_pi->vddci_voltage_table,
3337 (*vddc - adev->pm.dpm.dyn_state.vddc_vddci_delta));
3338 *vddci = (new_voltage < max_vddci) ? new_voltage : max_vddci;
3339 }
3340 } else {
3341 if ((*vddci - *vddc) > adev->pm.dpm.dyn_state.vddc_vddci_delta) {
3342 new_voltage = btc_find_voltage(&eg_pi->vddc_voltage_table,
3343 (*vddci - adev->pm.dpm.dyn_state.vddc_vddci_delta));
3344 *vddc = (new_voltage < max_vddc) ? new_voltage : max_vddc;
3345 }
3346 }
841686df
MB		 3347}
3348
3349static enum amdgpu_pcie_gen r600_get_pcie_gen_support(struct amdgpu_device *adev,
3350 u32 sys_mask,
3351 enum amdgpu_pcie_gen asic_gen,
3352 enum amdgpu_pcie_gen default_gen)
3353{
3354 switch (asic_gen) {
3355 case AMDGPU_PCIE_GEN1:
3356 return AMDGPU_PCIE_GEN1;
3357 case AMDGPU_PCIE_GEN2:
3358 return AMDGPU_PCIE_GEN2;
3359 case AMDGPU_PCIE_GEN3:
3360 return AMDGPU_PCIE_GEN3;
3361 default:
3362 if ((sys_mask & DRM_PCIE_SPEED_80) && (default_gen == AMDGPU_PCIE_GEN3))
3363 return AMDGPU_PCIE_GEN3;
3364 else if ((sys_mask & DRM_PCIE_SPEED_50) && (default_gen == AMDGPU_PCIE_GEN2))
3365 return AMDGPU_PCIE_GEN2;
3366 else
3367 return AMDGPU_PCIE_GEN1;
3368 }
3369 return AMDGPU_PCIE_GEN1;
3370}
3371
3372static void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,
3373 u32 *p, u32 *u)
3374{
3375 u32 b_c = 0;
3376 u32 i_c;
3377 u32 tmp;
3378
3379 i_c = (i * r_c) / 100;
3380 tmp = i_c >> p_b;
3381
3382 while (tmp) {
3383 b_c++;
3384 tmp >>= 1;
3385 }
3386
3387 *u = (b_c + 1) / 2;
3388 *p = i_c / (1 << (2 * (*u)));
3389}
3390
3391static int r600_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th)
3392{
3393 u32 k, a, ah, al;
3394 u32 t1;
3395
3396 if ((fl == 0) || (fh == 0) || (fl > fh))
3397 return -EINVAL;
3398
3399 k = (100 * fh) / fl;
3400 t1 = (t * (k - 100));
3401 a = (1000 * (100 * h + t1)) / (10000 + (t1 / 100));
3402 a = (a + 5) / 10;
3403 ah = ((a * t) + 5000) / 10000;
3404 al = a - ah;
3405
3406 *th = t - ah;
3407 *tl = t + al;
3408
3409 return 0;
3410}
3411
3412static bool r600_is_uvd_state(u32 class, u32 class2)
3413{
3414 if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
3415 return true;
3416 if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
3417 return true;
3418 if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
3419 return true;
3420 if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
3421 return true;
3422 if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
3423 return true;
3424 return false;
3425}
3426
3427static u8 rv770_get_memory_module_index(struct amdgpu_device *adev)
3428{
3429 return (u8) ((RREG32(BIOS_SCRATCH_4) >> 16) & 0xff);
3430}
3431
3432static void rv770_get_max_vddc(struct amdgpu_device *adev)
3433{
3434 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3435 u16 vddc;
3436
3437 if (amdgpu_atombios_get_max_vddc(adev, 0, 0, &vddc))
3438 pi->max_vddc = 0;
3439 else
3440 pi->max_vddc = vddc;
3441}
3442
3443static void rv770_get_engine_memory_ss(struct amdgpu_device *adev)
3444{
3445 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3446 struct amdgpu_atom_ss ss;
3447
3448 pi->sclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss,
3449 ASIC_INTERNAL_ENGINE_SS, 0);
3450 pi->mclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss,
3451 ASIC_INTERNAL_MEMORY_SS, 0);
3452
3453 if (pi->sclk_ss || pi->mclk_ss)
3454 pi->dynamic_ss = true;
3455 else
3456 pi->dynamic_ss = false;
3457}
3458
3459
3460static void si_apply_state_adjust_rules(struct amdgpu_device *adev,
3461 struct amdgpu_ps *rps)
3462{
3463 struct si_ps *ps = si_get_ps(rps);
3464 struct amdgpu_clock_and_voltage_limits *max_limits;
3465 bool disable_mclk_switching = false;
3466 bool disable_sclk_switching = false;
3467 u32 mclk, sclk;
3468 u16 vddc, vddci, min_vce_voltage = 0;
3469 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
3470 u32 max_sclk = 0, max_mclk = 0;
3471 int i;
3472 struct si_dpm_quirk *p = si_dpm_quirk_list;
3473
3474 /* Apply dpm quirks */
3475 while (p && p->chip_device != 0) {
3476 if (adev->pdev->vendor == p->chip_vendor &&
3477 adev->pdev->device == p->chip_device &&
3478 adev->pdev->subsystem_vendor == p->subsys_vendor &&
3479 adev->pdev->subsystem_device == p->subsys_device) {
3480 max_sclk = p->max_sclk;
3481 max_mclk = p->max_mclk;
3482 break;
3483 }
3484 ++p;
3485 }
3486
3487 if (rps->vce_active) {
3488 rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;
3489 rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk;
3490 si_get_vce_clock_voltage(adev, rps->evclk, rps->ecclk,
3491 &min_vce_voltage);
3492 } else {
3493 rps->evclk = 0;
3494 rps->ecclk = 0;
3495 }
3496
3497 if ((adev->pm.dpm.new_active_crtc_count > 1) ||
3498 si_dpm_vblank_too_short(adev))
3499 disable_mclk_switching = true;
3500
3501 if (rps->vclk || rps->dclk) {
3502 disable_mclk_switching = true;
3503 disable_sclk_switching = true;
3504 }
3505
3506 if (adev->pm.dpm.ac_power)
3507 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3508 else
3509 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3510
3511 for (i = ps->performance_level_count - 2; i >= 0; i--) {
3512 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
3513 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
3514 }
3515 if (adev->pm.dpm.ac_power == false) {
3516 for (i = 0; i < ps->performance_level_count; i++) {
3517 if (ps->performance_levels[i].mclk > max_limits->mclk)
3518 ps->performance_levels[i].mclk = max_limits->mclk;
3519 if (ps->performance_levels[i].sclk > max_limits->sclk)
3520 ps->performance_levels[i].sclk = max_limits->sclk;
3521 if (ps->performance_levels[i].vddc > max_limits->vddc)
3522 ps->performance_levels[i].vddc = max_limits->vddc;
3523 if (ps->performance_levels[i].vddci > max_limits->vddci)
3524 ps->performance_levels[i].vddci = max_limits->vddci;
3525 }
3526 }
3527
3528 /* limit clocks to max supported clocks based on voltage dependency tables */
3529 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3530 &max_sclk_vddc);
3531 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3532 &max_mclk_vddci);
3533 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3534 &max_mclk_vddc);
3535
3536 for (i = 0; i < ps->performance_level_count; i++) {
3537 if (max_sclk_vddc) {
3538 if (ps->performance_levels[i].sclk > max_sclk_vddc)
3539 ps->performance_levels[i].sclk = max_sclk_vddc;
3540 }
3541 if (max_mclk_vddci) {
3542 if (ps->performance_levels[i].mclk > max_mclk_vddci)
3543 ps->performance_levels[i].mclk = max_mclk_vddci;
3544 }
3545 if (max_mclk_vddc) {
3546 if (ps->performance_levels[i].mclk > max_mclk_vddc)
3547 ps->performance_levels[i].mclk = max_mclk_vddc;
3548 }
3549 if (max_mclk) {
3550 if (ps->performance_levels[i].mclk > max_mclk)
3551 ps->performance_levels[i].mclk = max_mclk;
3552 }
3553 if (max_sclk) {
3554 if (ps->performance_levels[i].sclk > max_sclk)
3555 ps->performance_levels[i].sclk = max_sclk;
3556 }
3557 }
3558
3559 /* XXX validate the min clocks required for display */
3560
3561 if (disable_mclk_switching) {
3562 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk;
3563 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
3564 } else {
3565 mclk = ps->performance_levels[0].mclk;
3566 vddci = ps->performance_levels[0].vddci;
3567 }
3568
3569 if (disable_sclk_switching) {
3570 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk;
3571 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc;
3572 } else {
3573 sclk = ps->performance_levels[0].sclk;
3574 vddc = ps->performance_levels[0].vddc;
3575 }
3576
3577 if (rps->vce_active) {
3578 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk)
3579 sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk;
3580 if (mclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk)
3581 mclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk;
3582 }
3583
3584 /* adjusted low state */
3585 ps->performance_levels[0].sclk = sclk;
3586 ps->performance_levels[0].mclk = mclk;
3587 ps->performance_levels[0].vddc = vddc;
3588 ps->performance_levels[0].vddci = vddci;
3589
3590 if (disable_sclk_switching) {
3591 sclk = ps->performance_levels[0].sclk;
3592 for (i = 1; i < ps->performance_level_count; i++) {
3593 if (sclk < ps->performance_levels[i].sclk)
3594 sclk = ps->performance_levels[i].sclk;
3595 }
3596 for (i = 0; i < ps->performance_level_count; i++) {
3597 ps->performance_levels[i].sclk = sclk;
3598 ps->performance_levels[i].vddc = vddc;
3599 }
3600 } else {
3601 for (i = 1; i < ps->performance_level_count; i++) {
3602 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
3603 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
3604 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
3605 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
3606 }
3607 }
3608
3609 if (disable_mclk_switching) {
3610 mclk = ps->performance_levels[0].mclk;
3611 for (i = 1; i < ps->performance_level_count; i++) {
3612 if (mclk < ps->performance_levels[i].mclk)
3613 mclk = ps->performance_levels[i].mclk;
3614 }
3615 for (i = 0; i < ps->performance_level_count; i++) {
3616 ps->performance_levels[i].mclk = mclk;
3617 ps->performance_levels[i].vddci = vddci;
3618 }
3619 } else {
3620 for (i = 1; i < ps->performance_level_count; i++) {
3621 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
3622 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
3623 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
3624 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
3625 }
3626 }
3627
77d318a6
TSD		 3628 for (i = 0; i < ps->performance_level_count; i++)
3629 btc_adjust_clock_combinations(adev, max_limits,
3630 &ps->performance_levels[i]);
841686df
MB		 3631
3632 for (i = 0; i < ps->performance_level_count; i++) {
3633 if (ps->performance_levels[i].vddc < min_vce_voltage)
3634 ps->performance_levels[i].vddc = min_vce_voltage;
3635 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3636 ps->performance_levels[i].sclk,
3637 max_limits->vddc, &ps->performance_levels[i].vddc);
3638 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3639 ps->performance_levels[i].mclk,
3640 max_limits->vddci, &ps->performance_levels[i].vddci);
3641 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3642 ps->performance_levels[i].mclk,
3643 max_limits->vddc, &ps->performance_levels[i].vddc);
3644 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
3645 adev->clock.current_dispclk,
3646 max_limits->vddc, &ps->performance_levels[i].vddc);
3647 }
3648
3649 for (i = 0; i < ps->performance_level_count; i++) {
3650 btc_apply_voltage_delta_rules(adev,
3651 max_limits->vddc, max_limits->vddci,
3652 &ps->performance_levels[i].vddc,
3653 &ps->performance_levels[i].vddci);
3654 }
3655
3656 ps->dc_compatible = true;
3657 for (i = 0; i < ps->performance_level_count; i++) {
3658 if (ps->performance_levels[i].vddc > adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3659 ps->dc_compatible = false;
3660 }
3661}
3662
3663#if 0
3664static int si_read_smc_soft_register(struct amdgpu_device *adev,
3665 u16 reg_offset, u32 *value)
3666{
3667 struct si_power_info *si_pi = si_get_pi(adev);
3668
3669 return si_read_smc_sram_dword(adev,
3670 si_pi->soft_regs_start + reg_offset, value,
3671 si_pi->sram_end);
3672}
3673#endif
3674
3675static int si_write_smc_soft_register(struct amdgpu_device *adev,
3676 u16 reg_offset, u32 value)
3677{
3678 struct si_power_info *si_pi = si_get_pi(adev);
3679
3680 return si_write_smc_sram_dword(adev,
3681 si_pi->soft_regs_start + reg_offset,
3682 value, si_pi->sram_end);
3683}
3684
3685static bool si_is_special_1gb_platform(struct amdgpu_device *adev)
3686{
3687 bool ret = false;
3688 u32 tmp, width, row, column, bank, density;
3689 bool is_memory_gddr5, is_special;
3690
3691 tmp = RREG32(MC_SEQ_MISC0);
3692 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3693 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3694 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3695
3696 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
3697 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
3698
3699 tmp = RREG32(MC_ARB_RAMCFG);
3700 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10;
3701 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8;
3702 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
3703
3704 density = (1 << (row + column - 20 + bank)) * width;
3705
3706 if ((adev->pdev->device == 0x6819) &&
3707 is_memory_gddr5 && is_special && (density == 0x400))
3708 ret = true;
3709
3710 return ret;
3711}
3712
3713static void si_get_leakage_vddc(struct amdgpu_device *adev)
3714{
3715 struct si_power_info *si_pi = si_get_pi(adev);
3716 u16 vddc, count = 0;
3717 int i, ret;
3718
3719 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) {
3720 ret = amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(adev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3721
3722 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3723 si_pi->leakage_voltage.entries[count].voltage = vddc;
3724 si_pi->leakage_voltage.entries[count].leakage_index =
3725 SISLANDS_LEAKAGE_INDEX0 + i;
3726 count++;
3727 }
3728 }
3729 si_pi->leakage_voltage.count = count;
3730}
3731
3732static int si_get_leakage_voltage_from_leakage_index(struct amdgpu_device *adev,
3733 u32 index, u16 *leakage_voltage)
3734{
3735 struct si_power_info *si_pi = si_get_pi(adev);
3736 int i;
3737
3738 if (leakage_voltage == NULL)
3739 return -EINVAL;
3740
3741 if ((index & 0xff00) != 0xff00)
3742 return -EINVAL;
3743
3744 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1)
3745 return -EINVAL;
3746
3747 if (index < SISLANDS_LEAKAGE_INDEX0)
3748 return -EINVAL;
3749
3750 for (i = 0; i < si_pi->leakage_voltage.count; i++) {
3751 if (si_pi->leakage_voltage.entries[i].leakage_index == index) {
3752 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;
3753 return 0;
3754 }
3755 }
3756 return -EAGAIN;
3757}
3758
3759static void si_set_dpm_event_sources(struct amdgpu_device *adev, u32 sources)
3760{
3761 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3762 bool want_thermal_protection;
3763 enum amdgpu_dpm_event_src dpm_event_src;
3764
3765 switch (sources) {
3766 case 0:
3767 default:
3768 want_thermal_protection = false;
77d318a6 3769 break;
841686df
MB		 3770 case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL):
3771 want_thermal_protection = true;
3772 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGITAL;
3773 break;
3774 case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
3775 want_thermal_protection = true;
3776 dpm_event_src = AMDGPU_DPM_EVENT_SRC_EXTERNAL;
3777 break;
3778 case ((1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
3779 (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL)):
3780 want_thermal_protection = true;
3781 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
3782 break;
3783 }
3784
3785 if (want_thermal_protection) {
3786 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
3787 if (pi->thermal_protection)
3788 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3789 } else {
3790 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3791 }
3792}
3793
3794static void si_enable_auto_throttle_source(struct amdgpu_device *adev,
3795 enum amdgpu_dpm_auto_throttle_src source,
3796 bool enable)
3797{
3798 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3799
3800 if (enable) {
3801 if (!(pi->active_auto_throttle_sources & (1 << source))) {
3802 pi->active_auto_throttle_sources |= 1 << source;
3803 si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
3804 }
3805 } else {
3806 if (pi->active_auto_throttle_sources & (1 << source)) {
3807 pi->active_auto_throttle_sources &= ~(1 << source);
3808 si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
3809 }
3810 }
3811}
3812
3813static void si_start_dpm(struct amdgpu_device *adev)
3814{
3815 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
3816}
3817
3818static void si_stop_dpm(struct amdgpu_device *adev)
3819{
3820 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
3821}
3822
3823static void si_enable_sclk_control(struct amdgpu_device *adev, bool enable)
3824{
3825 if (enable)
3826 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3827 else
3828 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
3829
3830}
3831
3832#if 0
3833static int si_notify_hardware_of_thermal_state(struct amdgpu_device *adev,
3834 u32 thermal_level)
3835{
3836 PPSMC_Result ret;
3837
3838 if (thermal_level == 0) {
3839 ret = si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
3840 if (ret == PPSMC_Result_OK)
3841 return 0;
3842 else
3843 return -EINVAL;
3844 }
3845 return 0;
3846}
3847
3848static void si_notify_hardware_vpu_recovery_event(struct amdgpu_device *adev)
3849{
3850 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3851}
3852#endif
3853
3854#if 0
3855static int si_notify_hw_of_powersource(struct amdgpu_device *adev, bool ac_power)
3856{
3857 if (ac_power)
3858 return (si_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3859 0 : -EINVAL;
3860
3861 return 0;
3862}
3863#endif
3864
3865static PPSMC_Result si_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
3866 PPSMC_Msg msg, u32 parameter)
3867{
3868 WREG32(SMC_SCRATCH0, parameter);
3869 return si_send_msg_to_smc(adev, msg);
3870}
3871
3872static int si_restrict_performance_levels_before_switch(struct amdgpu_device *adev)
3873{
3874 if (si_send_msg_to_smc(adev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3875 return -EINVAL;
3876
3877 return (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3878 0 : -EINVAL;
3879}
3880
3881static int si_dpm_force_performance_level(struct amdgpu_device *adev,
3882 enum amdgpu_dpm_forced_level level)
3883{
3884 struct amdgpu_ps *rps = adev->pm.dpm.current_ps;
3885 struct si_ps *ps = si_get_ps(rps);
3886 u32 levels = ps->performance_level_count;
3887
3888 if (level == AMDGPU_DPM_FORCED_LEVEL_HIGH) {
3889 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3890 return -EINVAL;
3891
3892 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3893 return -EINVAL;
3894 } else if (level == AMDGPU_DPM_FORCED_LEVEL_LOW) {
3895 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3896 return -EINVAL;
3897
3898 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
3899 return -EINVAL;
3900 } else if (level == AMDGPU_DPM_FORCED_LEVEL_AUTO) {
3901 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3902 return -EINVAL;
3903
3904 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3905 return -EINVAL;
3906 }
3907
3908 adev->pm.dpm.forced_level = level;
3909
3910 return 0;
3911}
3912
3913#if 0
3914static int si_set_boot_state(struct amdgpu_device *adev)
3915{
3916 return (si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3917 0 : -EINVAL;
3918}
3919#endif
3920
3921static int si_set_sw_state(struct amdgpu_device *adev)
3922{
3923 return (si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3924 0 : -EINVAL;
3925}
3926
3927static int si_halt_smc(struct amdgpu_device *adev)
3928{
3929 if (si_send_msg_to_smc(adev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3930 return -EINVAL;
3931
3932 return (si_wait_for_smc_inactive(adev) == PPSMC_Result_OK) ?
3933 0 : -EINVAL;
3934}
3935
3936static int si_resume_smc(struct amdgpu_device *adev)
3937{
3938 if (si_send_msg_to_smc(adev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3939 return -EINVAL;
3940
3941 return (si_send_msg_to_smc(adev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3942 0 : -EINVAL;
3943}
3944
3945static void si_dpm_start_smc(struct amdgpu_device *adev)
3946{
3947 si_program_jump_on_start(adev);
3948 si_start_smc(adev);
f80c738c 3949 si_smc_clock(adev, true);
841686df
MB		 3950}
3951
3952static void si_dpm_stop_smc(struct amdgpu_device *adev)
3953{
3954 si_reset_smc(adev);
f80c738c 3955 si_smc_clock(adev, false);
841686df
MB		 3956}
3957
3958static int si_process_firmware_header(struct amdgpu_device *adev)
3959{
3960 struct si_power_info *si_pi = si_get_pi(adev);
3961 u32 tmp;
3962 int ret;
3963
3964 ret = si_read_smc_sram_dword(adev,
3965 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3966 SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
3967 &tmp, si_pi->sram_end);
3968 if (ret)
3969 return ret;
3970
77d318a6 3971 si_pi->state_table_start = tmp;
841686df
MB		 3972
3973 ret = si_read_smc_sram_dword(adev,
3974 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3975 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
3976 &tmp, si_pi->sram_end);
3977 if (ret)
3978 return ret;
3979
3980 si_pi->soft_regs_start = tmp;
3981
3982 ret = si_read_smc_sram_dword(adev,
3983 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3984 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
3985 &tmp, si_pi->sram_end);
3986 if (ret)
3987 return ret;
3988
3989 si_pi->mc_reg_table_start = tmp;
3990
3991 ret = si_read_smc_sram_dword(adev,
3992 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3993 SISLANDS_SMC_FIRMWARE_HEADER_fanTable,
3994 &tmp, si_pi->sram_end);
3995 if (ret)
3996 return ret;
3997
3998 si_pi->fan_table_start = tmp;
3999
4000 ret = si_read_smc_sram_dword(adev,
4001 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4002 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
4003 &tmp, si_pi->sram_end);
4004 if (ret)
4005 return ret;
4006
4007 si_pi->arb_table_start = tmp;
4008
4009 ret = si_read_smc_sram_dword(adev,
4010 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4011 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
4012 &tmp, si_pi->sram_end);
4013 if (ret)
4014 return ret;
4015
4016 si_pi->cac_table_start = tmp;
4017
4018 ret = si_read_smc_sram_dword(adev,
4019 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4020 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
4021 &tmp, si_pi->sram_end);
4022 if (ret)
4023 return ret;
4024
4025 si_pi->dte_table_start = tmp;
4026
4027 ret = si_read_smc_sram_dword(adev,
4028 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4029 SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
4030 &tmp, si_pi->sram_end);
4031 if (ret)
4032 return ret;
4033
4034 si_pi->spll_table_start = tmp;
4035
4036 ret = si_read_smc_sram_dword(adev,
4037 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4038 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
4039 &tmp, si_pi->sram_end);
4040 if (ret)
4041 return ret;
4042
4043 si_pi->papm_cfg_table_start = tmp;
4044
4045 return ret;
4046}
4047
4048static void si_read_clock_registers(struct amdgpu_device *adev)
4049{
4050 struct si_power_info *si_pi = si_get_pi(adev);
4051
4052 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
4053 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
4054 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
4055 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
4056 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
4057 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
4058 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
4059 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
4060 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
4061 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
4062 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
4063 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
4064 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
4065 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
4066 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
4067}
4068
4069static void si_enable_thermal_protection(struct amdgpu_device *adev,
4070 bool enable)
4071{
4072 if (enable)
4073 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
4074 else
4075 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
4076}
4077
4078static void si_enable_acpi_power_management(struct amdgpu_device *adev)
4079{
4080 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
4081}
4082
4083#if 0
4084static int si_enter_ulp_state(struct amdgpu_device *adev)
4085{
4086 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
4087
4088 udelay(25000);
4089
4090 return 0;
4091}
4092
4093static int si_exit_ulp_state(struct amdgpu_device *adev)
4094{
4095 int i;
4096
4097 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
4098
4099 udelay(7000);
4100
4101 for (i = 0; i < adev->usec_timeout; i++) {
4102 if (RREG32(SMC_RESP_0) == 1)
4103 break;
4104 udelay(1000);
4105 }
4106
4107 return 0;
4108}
4109#endif
4110
4111static int si_notify_smc_display_change(struct amdgpu_device *adev,
4112 bool has_display)
4113{
4114 PPSMC_Msg msg = has_display ?
4115 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
4116
4117 return (si_send_msg_to_smc(adev, msg) == PPSMC_Result_OK) ?
4118 0 : -EINVAL;
4119}
4120
4121static void si_program_response_times(struct amdgpu_device *adev)
4122{
4123 u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;
4124 u32 vddc_dly, acpi_dly, vbi_dly;
4125 u32 reference_clock;
4126
4127 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
4128
4129 voltage_response_time = (u32)adev->pm.dpm.voltage_response_time;
77d318a6 4130 backbias_response_time = (u32)adev->pm.dpm.backbias_response_time;
841686df
MB		 4131
4132 if (voltage_response_time == 0)
4133 voltage_response_time = 1000;
4134
4135 acpi_delay_time = 15000;
4136 vbi_time_out = 100000;
4137
4138 reference_clock = amdgpu_asic_get_xclk(adev);
4139
4140 vddc_dly = (voltage_response_time * reference_clock) / 100;
4141 acpi_dly = (acpi_delay_time * reference_clock) / 100;
4142 vbi_dly = (vbi_time_out * reference_clock) / 100;
4143
4144 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly);
4145 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly);
4146 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
4147 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
4148}
4149
4150static void si_program_ds_registers(struct amdgpu_device *adev)
4151{
4152 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4153 u32 tmp;
4154
4155 /* DEEP_SLEEP_CLK_SEL field should be 0x10 on tahiti A0 */
4156 if (adev->asic_type == CHIP_TAHITI && adev->rev_id == 0x0)
4157 tmp = 0x10;
4158 else
4159 tmp = 0x1;
4160
4161 if (eg_pi->sclk_deep_sleep) {
4162 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
4163 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR,
4164 ~AUTOSCALE_ON_SS_CLEAR);
4165 }
4166}
4167
4168static void si_program_display_gap(struct amdgpu_device *adev)
4169{
4170 u32 tmp, pipe;
4171 int i;
4172
4173 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
4174 if (adev->pm.dpm.new_active_crtc_count > 0)
4175 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
4176 else
4177 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
4178
4179 if (adev->pm.dpm.new_active_crtc_count > 1)
4180 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
4181 else
4182 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
4183
4184 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
4185
4186 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
4187 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
4188
4189 if ((adev->pm.dpm.new_active_crtc_count > 0) &&
4190 (!(adev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
4191 /* find the first active crtc */
4192 for (i = 0; i < adev->mode_info.num_crtc; i++) {
4193 if (adev->pm.dpm.new_active_crtcs & (1 << i))
4194 break;
4195 }
4196 if (i == adev->mode_info.num_crtc)
4197 pipe = 0;
4198 else
4199 pipe = i;
4200
4201 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
4202 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
4203 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
4204 }
4205
4206 /* Setting this to false forces the performance state to low if the crtcs are disabled.
4207 * This can be a problem on PowerXpress systems or if you want to use the card
4208 * for offscreen rendering or compute if there are no crtcs enabled.
4209 */
4210 si_notify_smc_display_change(adev, adev->pm.dpm.new_active_crtc_count > 0);
4211}
4212
4213static void si_enable_spread_spectrum(struct amdgpu_device *adev, bool enable)
4214{
4215 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4216
4217 if (enable) {
4218 if (pi->sclk_ss)
4219 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
4220 } else {
4221 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
4222 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
4223 }
4224}
4225
4226static void si_setup_bsp(struct amdgpu_device *adev)
4227{
4228 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4229 u32 xclk = amdgpu_asic_get_xclk(adev);
4230
4231 r600_calculate_u_and_p(pi->asi,
4232 xclk,
4233 16,
4234 &pi->bsp,
4235 &pi->bsu);
4236
4237 r600_calculate_u_and_p(pi->pasi,
4238 xclk,
4239 16,
4240 &pi->pbsp,
4241 &pi->pbsu);
4242
4243
4244 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
4245 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
4246
4247 WREG32(CG_BSP, pi->dsp);
4248}
4249
4250static void si_program_git(struct amdgpu_device *adev)
4251{
4252 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);
4253}
4254
4255static void si_program_tp(struct amdgpu_device *adev)
4256{
4257 int i;
4258 enum r600_td td = R600_TD_DFLT;
4259
4260 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
4261 WREG32(CG_FFCT_0 + i, (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
4262
4263 if (td == R600_TD_AUTO)
4264 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
4265 else
4266 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
4267
4268 if (td == R600_TD_UP)
4269 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
4270
4271 if (td == R600_TD_DOWN)
4272 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
4273}
4274
4275static void si_program_tpp(struct amdgpu_device *adev)
4276{
4277 WREG32(CG_TPC, R600_TPC_DFLT);
4278}
4279
4280static void si_program_sstp(struct amdgpu_device *adev)
4281{
4282 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
4283}
4284
4285static void si_enable_display_gap(struct amdgpu_device *adev)
4286{
4287 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
4288
4289 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
4290 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
4291 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
4292
4293 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
4294 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
4295 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
4296 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
4297}
4298
4299static void si_program_vc(struct amdgpu_device *adev)
4300{
4301 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4302
4303 WREG32(CG_FTV, pi->vrc);
4304}
4305
4306static void si_clear_vc(struct amdgpu_device *adev)
4307{
4308 WREG32(CG_FTV, 0);
4309}
4310
4311u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
4312{
4313 u8 mc_para_index;
4314
4315 if (memory_clock < 10000)
4316 mc_para_index = 0;
4317 else if (memory_clock >= 80000)
4318 mc_para_index = 0x0f;
4319 else
4320 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
4321 return mc_para_index;
4322}
4323
4324u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
4325{
4326 u8 mc_para_index;
4327
4328 if (strobe_mode) {
4329 if (memory_clock < 12500)
4330 mc_para_index = 0x00;
4331 else if (memory_clock > 47500)
4332 mc_para_index = 0x0f;
4333 else
4334 mc_para_index = (u8)((memory_clock - 10000) / 2500);
4335 } else {
4336 if (memory_clock < 65000)
4337 mc_para_index = 0x00;
4338 else if (memory_clock > 135000)
4339 mc_para_index = 0x0f;
4340 else
4341 mc_para_index = (u8)((memory_clock - 60000) / 5000);
4342 }
4343 return mc_para_index;
4344}
4345
4346static u8 si_get_strobe_mode_settings(struct amdgpu_device *adev, u32 mclk)
4347{
4348 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4349 bool strobe_mode = false;
4350 u8 result = 0;
4351
4352 if (mclk <= pi->mclk_strobe_mode_threshold)
4353 strobe_mode = true;
4354
4355 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
4356 result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
4357 else
4358 result = si_get_ddr3_mclk_frequency_ratio(mclk);
4359
4360 if (strobe_mode)
4361 result |= SISLANDS_SMC_STROBE_ENABLE;
4362
4363 return result;
4364}
4365
4366static int si_upload_firmware(struct amdgpu_device *adev)
4367{
4368 struct si_power_info *si_pi = si_get_pi(adev);
841686df
MB		 4369
4370 si_reset_smc(adev);
f80c738c 4371 si_smc_clock(adev, false);
841686df 4372
77d318a6 4373 return si_load_smc_ucode(adev, si_pi->sram_end);
841686df
MB		 4374}
4375
4376static bool si_validate_phase_shedding_tables(struct amdgpu_device *adev,
4377 const struct atom_voltage_table *table,
4378 const struct amdgpu_phase_shedding_limits_table *limits)
4379{
4380 u32 data, num_bits, num_levels;
4381
4382 if ((table == NULL) || (limits == NULL))
4383 return false;
4384
4385 data = table->mask_low;
4386
4387 num_bits = hweight32(data);
4388
4389 if (num_bits == 0)
4390 return false;
4391
4392 num_levels = (1 << num_bits);
4393
4394 if (table->count != num_levels)
4395 return false;
4396
4397 if (limits->count != (num_levels - 1))
4398 return false;
4399
4400 return true;
4401}
4402
4403static void si_trim_voltage_table_to_fit_state_table(struct amdgpu_device *adev,
4404 u32 max_voltage_steps,
4405 struct atom_voltage_table *voltage_table)
4406{
4407 unsigned int i, diff;
4408
4409 if (voltage_table->count <= max_voltage_steps)
4410 return;
4411
4412 diff = voltage_table->count - max_voltage_steps;
4413
4414 for (i= 0; i < max_voltage_steps; i++)
4415 voltage_table->entries[i] = voltage_table->entries[i + diff];
4416
4417 voltage_table->count = max_voltage_steps;
4418}
4419
4420static int si_get_svi2_voltage_table(struct amdgpu_device *adev,
4421 struct amdgpu_clock_voltage_dependency_table *voltage_dependency_table,
4422 struct atom_voltage_table *voltage_table)
4423{
4424 u32 i;
4425
4426 if (voltage_dependency_table == NULL)
4427 return -EINVAL;
4428
4429 voltage_table->mask_low = 0;
4430 voltage_table->phase_delay = 0;
4431
4432 voltage_table->count = voltage_dependency_table->count;
4433 for (i = 0; i < voltage_table->count; i++) {
4434 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
4435 voltage_table->entries[i].smio_low = 0;
4436 }
4437
4438 return 0;
4439}
4440
4441static int si_construct_voltage_tables(struct amdgpu_device *adev)
4442{
4443 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4444 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4445 struct si_power_info *si_pi = si_get_pi(adev);
4446 int ret;
4447
4448 if (pi->voltage_control) {
4449 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
4450 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table);
4451 if (ret)
4452 return ret;
4453
4454 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4455 si_trim_voltage_table_to_fit_state_table(adev,
4456 SISLANDS_MAX_NO_VREG_STEPS,
4457 &eg_pi->vddc_voltage_table);
4458 } else if (si_pi->voltage_control_svi2) {
4459 ret = si_get_svi2_voltage_table(adev,
4460 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
4461 &eg_pi->vddc_voltage_table);
4462 if (ret)
4463 return ret;
4464 } else {
4465 return -EINVAL;
4466 }
4467
4468 if (eg_pi->vddci_control) {
4469 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDCI,
4470 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table);
4471 if (ret)
4472 return ret;
4473
4474 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4475 si_trim_voltage_table_to_fit_state_table(adev,
4476 SISLANDS_MAX_NO_VREG_STEPS,
4477 &eg_pi->vddci_voltage_table);
4478 }
4479 if (si_pi->vddci_control_svi2) {
4480 ret = si_get_svi2_voltage_table(adev,
4481 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
4482 &eg_pi->vddci_voltage_table);
4483 if (ret)
4484 return ret;
4485 }
4486
4487 if (pi->mvdd_control) {
4488 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_MVDDC,
4489 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);
4490
4491 if (ret) {
4492 pi->mvdd_control = false;
4493 return ret;
4494 }
4495
4496 if (si_pi->mvdd_voltage_table.count == 0) {
4497 pi->mvdd_control = false;
4498 return -EINVAL;
4499 }
4500
4501 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4502 si_trim_voltage_table_to_fit_state_table(adev,
4503 SISLANDS_MAX_NO_VREG_STEPS,
4504 &si_pi->mvdd_voltage_table);
4505 }
4506
4507 if (si_pi->vddc_phase_shed_control) {
4508 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
4509 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
4510 if (ret)
4511 si_pi->vddc_phase_shed_control = false;
4512
4513 if ((si_pi->vddc_phase_shed_table.count == 0) ||
4514 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
4515 si_pi->vddc_phase_shed_control = false;
4516 }
4517
4518 return 0;
4519}
4520
4521static void si_populate_smc_voltage_table(struct amdgpu_device *adev,
4522 const struct atom_voltage_table *voltage_table,
4523 SISLANDS_SMC_STATETABLE *table)
4524{
4525 unsigned int i;
4526
4527 for (i = 0; i < voltage_table->count; i++)
4528 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
4529}
4530
4531static int si_populate_smc_voltage_tables(struct amdgpu_device *adev,
4532 SISLANDS_SMC_STATETABLE *table)
4533{
4534 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4535 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4536 struct si_power_info *si_pi = si_get_pi(adev);
4537 u8 i;
4538
4539 if (si_pi->voltage_control_svi2) {
4540 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc,
4541 si_pi->svc_gpio_id);
4542 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd,
4543 si_pi->svd_gpio_id);
4544 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type,
4545 2);
4546 } else {
4547 if (eg_pi->vddc_voltage_table.count) {
4548 si_populate_smc_voltage_table(adev, &eg_pi->vddc_voltage_table, table);
4549 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
4550 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
4551
4552 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
4553 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
4554 table->maxVDDCIndexInPPTable = i;
4555 break;
4556 }
4557 }
4558 }
4559
4560 if (eg_pi->vddci_voltage_table.count) {
4561 si_populate_smc_voltage_table(adev, &eg_pi->vddci_voltage_table, table);
4562
4563 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =
4564 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
4565 }
4566
4567
4568 if (si_pi->mvdd_voltage_table.count) {
4569 si_populate_smc_voltage_table(adev, &si_pi->mvdd_voltage_table, table);
4570
4571 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =
4572 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);
4573 }
4574
4575 if (si_pi->vddc_phase_shed_control) {
4576 if (si_validate_phase_shedding_tables(adev, &si_pi->vddc_phase_shed_table,
4577 &adev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
4578 si_populate_smc_voltage_table(adev, &si_pi->vddc_phase_shed_table, table);
4579
4580 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
4581 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
4582
4583 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
4584 (u32)si_pi->vddc_phase_shed_table.phase_delay);
4585 } else {
4586 si_pi->vddc_phase_shed_control = false;
4587 }
4588 }
4589 }
4590
4591 return 0;
4592}
4593
4594static int si_populate_voltage_value(struct amdgpu_device *adev,
4595 const struct atom_voltage_table *table,
4596 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4597{
4598 unsigned int i;
4599
4600 for (i = 0; i < table->count; i++) {
4601 if (value <= table->entries[i].value) {
4602 voltage->index = (u8)i;
4603 voltage->value = cpu_to_be16(table->entries[i].value);
4604 break;
4605 }
4606 }
4607
4608 if (i >= table->count)
4609 return -EINVAL;
4610
4611 return 0;
4612}
4613
4614static int si_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk,
4615 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4616{
4617 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4618 struct si_power_info *si_pi = si_get_pi(adev);
4619
4620 if (pi->mvdd_control) {
4621 if (mclk <= pi->mvdd_split_frequency)
4622 voltage->index = 0;
4623 else
4624 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;
4625
4626 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);
4627 }
4628 return 0;
4629}
4630
4631static int si_get_std_voltage_value(struct amdgpu_device *adev,
4632 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
4633 u16 *std_voltage)
4634{
4635 u16 v_index;
4636 bool voltage_found = false;
4637 *std_voltage = be16_to_cpu(voltage->value);
4638
4639 if (adev->pm.dpm.dyn_state.cac_leakage_table.entries) {
4640 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
4641 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
4642 return -EINVAL;
4643
4644 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4645 if (be16_to_cpu(voltage->value) ==
4646 (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4647 voltage_found = true;
4648 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4649 *std_voltage =
4650 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4651 else
4652 *std_voltage =
4653 adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4654 break;
4655 }
4656 }
4657
4658 if (!voltage_found) {
4659 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4660 if (be16_to_cpu(voltage->value) <=
4661 (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4662 voltage_found = true;
4663 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4664 *std_voltage =
4665 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4666 else
4667 *std_voltage =
4668 adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4669 break;
4670 }
4671 }
4672 }
4673 } else {
4674 if ((u32)voltage->index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4675 *std_voltage = adev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
4676 }
4677 }
4678
4679 return 0;
4680}
4681
4682static int si_populate_std_voltage_value(struct amdgpu_device *adev,
4683 u16 value, u8 index,
4684 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4685{
4686 voltage->index = index;
4687 voltage->value = cpu_to_be16(value);
4688
4689 return 0;
4690}
4691
4692static int si_populate_phase_shedding_value(struct amdgpu_device *adev,
4693 const struct amdgpu_phase_shedding_limits_table *limits,
4694 u16 voltage, u32 sclk, u32 mclk,
4695 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
4696{
4697 unsigned int i;
4698
4699 for (i = 0; i < limits->count; i++) {
4700 if ((voltage <= limits->entries[i].voltage) &&
4701 (sclk <= limits->entries[i].sclk) &&
4702 (mclk <= limits->entries[i].mclk))
4703 break;
4704 }
4705
4706 smc_voltage->phase_settings = (u8)i;
4707
4708 return 0;
4709}
4710
4711static int si_init_arb_table_index(struct amdgpu_device *adev)
4712{
4713 struct si_power_info *si_pi = si_get_pi(adev);
4714 u32 tmp;
4715 int ret;
4716
4717 ret = si_read_smc_sram_dword(adev, si_pi->arb_table_start, &tmp, si_pi->sram_end);
4718 if (ret)
4719 return ret;
4720
4721 tmp &= 0x00FFFFFF;
4722 tmp |= MC_CG_ARB_FREQ_F1 << 24;
4723
4724 return si_write_smc_sram_dword(adev, si_pi->arb_table_start, tmp, si_pi->sram_end);
4725}
4726
4727static int si_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev)
4728{
4729 return ni_copy_and_switch_arb_sets(adev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4730}
4731
4732static int si_reset_to_default(struct amdgpu_device *adev)
4733{
4734 return (si_send_msg_to_smc(adev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
4735 0 : -EINVAL;
4736}
4737
4738static int si_force_switch_to_arb_f0(struct amdgpu_device *adev)
4739{
4740 struct si_power_info *si_pi = si_get_pi(adev);
4741 u32 tmp;
4742 int ret;
4743
4744 ret = si_read_smc_sram_dword(adev, si_pi->arb_table_start,
4745 &tmp, si_pi->sram_end);
4746 if (ret)
4747 return ret;
4748
4749 tmp = (tmp >> 24) & 0xff;
4750
4751 if (tmp == MC_CG_ARB_FREQ_F0)
4752 return 0;
4753
4754 return ni_copy_and_switch_arb_sets(adev, tmp, MC_CG_ARB_FREQ_F0);
4755}
4756
4757static u32 si_calculate_memory_refresh_rate(struct amdgpu_device *adev,
4758 u32 engine_clock)
4759{
4760 u32 dram_rows;
4761 u32 dram_refresh_rate;
4762 u32 mc_arb_rfsh_rate;
4763 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
4764
4765 if (tmp >= 4)
4766 dram_rows = 16384;
4767 else
4768 dram_rows = 1 << (tmp + 10);
4769
4770 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4771 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4772
4773 return mc_arb_rfsh_rate;
4774}
4775
4776static int si_populate_memory_timing_parameters(struct amdgpu_device *adev,
4777 struct rv7xx_pl *pl,
4778 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4779{
4780 u32 dram_timing;
4781 u32 dram_timing2;
4782 u32 burst_time;
4783
4784 arb_regs->mc_arb_rfsh_rate =
4785 (u8)si_calculate_memory_refresh_rate(adev, pl->sclk);
4786
4787 amdgpu_atombios_set_engine_dram_timings(adev,
4788 pl->sclk,
77d318a6 4789 pl->mclk);
841686df
MB		 4790
4791 dram_timing = RREG32(MC_ARB_DRAM_TIMING);
4792 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
4793 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
4794
4795 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing);
4796 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4797 arb_regs->mc_arb_burst_time = (u8)burst_time;
4798
4799 return 0;
4800}
4801
4802static int si_do_program_memory_timing_parameters(struct amdgpu_device *adev,
4803 struct amdgpu_ps *amdgpu_state,
4804 unsigned int first_arb_set)
4805{
4806 struct si_power_info *si_pi = si_get_pi(adev);
4807 struct si_ps *state = si_get_ps(amdgpu_state);
4808 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4809 int i, ret = 0;
4810
4811 for (i = 0; i < state->performance_level_count; i++) {
4812 ret = si_populate_memory_timing_parameters(adev, &state->performance_levels[i], &arb_regs);
4813 if (ret)
4814 break;
4815 ret = si_copy_bytes_to_smc(adev,
4816 si_pi->arb_table_start +
4817 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4818 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4819 (u8 *)&arb_regs,
4820 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4821 si_pi->sram_end);
4822 if (ret)
4823 break;
77d318a6 4824 }
841686df
MB		 4825
4826 return ret;
4827}
4828
4829static int si_program_memory_timing_parameters(struct amdgpu_device *adev,
4830 struct amdgpu_ps *amdgpu_new_state)
4831{
4832 return si_do_program_memory_timing_parameters(adev, amdgpu_new_state,
4833 SISLANDS_DRIVER_STATE_ARB_INDEX);
4834}
4835
4836static int si_populate_initial_mvdd_value(struct amdgpu_device *adev,
4837 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4838{
4839 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4840 struct si_power_info *si_pi = si_get_pi(adev);
4841
4842 if (pi->mvdd_control)
4843 return si_populate_voltage_value(adev, &si_pi->mvdd_voltage_table,
4844 si_pi->mvdd_bootup_value, voltage);
4845
4846 return 0;
4847}
4848
4849static int si_populate_smc_initial_state(struct amdgpu_device *adev,
4850 struct amdgpu_ps *amdgpu_initial_state,
4851 SISLANDS_SMC_STATETABLE *table)
4852{
4853 struct si_ps *initial_state = si_get_ps(amdgpu_initial_state);
4854 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4855 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4856 struct si_power_info *si_pi = si_get_pi(adev);
4857 u32 reg;
4858 int ret;
4859
4860 table->initialState.levels[0].mclk.vDLL_CNTL =
4861 cpu_to_be32(si_pi->clock_registers.dll_cntl);
4862 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4863 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4864 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4865 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4866 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4867 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4868 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =
4869 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4870 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4871 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4872 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4873 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4874 table->initialState.levels[0].mclk.vMPLL_SS =
4875 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4876 table->initialState.levels[0].mclk.vMPLL_SS2 =
4877 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4878
4879 table->initialState.levels[0].mclk.mclk_value =
4880 cpu_to_be32(initial_state->performance_levels[0].mclk);
4881
4882 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4883 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4884 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4885 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4886 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4887 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4888 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4889 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4890 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
4891 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4892 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
4893 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4894
4895 table->initialState.levels[0].sclk.sclk_value =
4896 cpu_to_be32(initial_state->performance_levels[0].sclk);
4897
4898 table->initialState.levels[0].arbRefreshState =
4899 SISLANDS_INITIAL_STATE_ARB_INDEX;
4900
4901 table->initialState.levels[0].ACIndex = 0;
4902
4903 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
4904 initial_state->performance_levels[0].vddc,
4905 &table->initialState.levels[0].vddc);
4906
4907 if (!ret) {
4908 u16 std_vddc;
4909
4910 ret = si_get_std_voltage_value(adev,
4911 &table->initialState.levels[0].vddc,
4912 &std_vddc);
4913 if (!ret)
4914 si_populate_std_voltage_value(adev, std_vddc,
4915 table->initialState.levels[0].vddc.index,
4916 &table->initialState.levels[0].std_vddc);
4917 }
4918
4919 if (eg_pi->vddci_control)
4920 si_populate_voltage_value(adev,
4921 &eg_pi->vddci_voltage_table,
4922 initial_state->performance_levels[0].vddci,
4923 &table->initialState.levels[0].vddci);
4924
4925 if (si_pi->vddc_phase_shed_control)
4926 si_populate_phase_shedding_value(adev,
4927 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
4928 initial_state->performance_levels[0].vddc,
4929 initial_state->performance_levels[0].sclk,
4930 initial_state->performance_levels[0].mclk,
4931 &table->initialState.levels[0].vddc);
4932
4933 si_populate_initial_mvdd_value(adev, &table->initialState.levels[0].mvdd);
4934
4935 reg = CG_R(0xffff) | CG_L(0);
4936 table->initialState.levels[0].aT = cpu_to_be32(reg);
841686df 4937 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
841686df
MB		 4938 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
4939
4940 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
4941 table->initialState.levels[0].strobeMode =
4942 si_get_strobe_mode_settings(adev,
4943 initial_state->performance_levels[0].mclk);
4944
4945 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4946 table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4947 else
4948 table->initialState.levels[0].mcFlags = 0;
4949 }
4950
4951 table->initialState.levelCount = 1;
4952
4953 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
4954
4955 table->initialState.levels[0].dpm2.MaxPS = 0;
4956 table->initialState.levels[0].dpm2.NearTDPDec = 0;
4957 table->initialState.levels[0].dpm2.AboveSafeInc = 0;
4958 table->initialState.levels[0].dpm2.BelowSafeInc = 0;
4959 table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4960
4961 reg = MIN_POWER_MASK | MAX_POWER_MASK;
4962 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4963
4964 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4965 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4966
4967 return 0;
4968}
4969
4970static int si_populate_smc_acpi_state(struct amdgpu_device *adev,
4971 SISLANDS_SMC_STATETABLE *table)
4972{
4973 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4974 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4975 struct si_power_info *si_pi = si_get_pi(adev);
4976 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4977 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4978 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4979 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4980 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4981 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4982 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4983 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4984 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4985 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4986 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4987 u32 reg;
4988 int ret;
4989
4990 table->ACPIState = table->initialState;
4991
4992 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
4993
4994 if (pi->acpi_vddc) {
4995 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
4996 pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
4997 if (!ret) {
4998 u16 std_vddc;
4999
5000 ret = si_get_std_voltage_value(adev,
5001 &table->ACPIState.levels[0].vddc, &std_vddc);
5002 if (!ret)
5003 si_populate_std_voltage_value(adev, std_vddc,
5004 table->ACPIState.levels[0].vddc.index,
5005 &table->ACPIState.levels[0].std_vddc);
5006 }
5007 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;
5008
5009 if (si_pi->vddc_phase_shed_control) {
5010 si_populate_phase_shedding_value(adev,
5011 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5012 pi->acpi_vddc,
5013 0,
5014 0,
5015 &table->ACPIState.levels[0].vddc);
5016 }
5017 } else {
5018 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
5019 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
5020 if (!ret) {
5021 u16 std_vddc;
5022
5023 ret = si_get_std_voltage_value(adev,
5024 &table->ACPIState.levels[0].vddc, &std_vddc);
5025
5026 if (!ret)
5027 si_populate_std_voltage_value(adev, std_vddc,
5028 table->ACPIState.levels[0].vddc.index,
5029 &table->ACPIState.levels[0].std_vddc);
5030 }
5031 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(adev,
5032 si_pi->sys_pcie_mask,
5033 si_pi->boot_pcie_gen,
5034 AMDGPU_PCIE_GEN1);
5035
5036 if (si_pi->vddc_phase_shed_control)
5037 si_populate_phase_shedding_value(adev,
5038 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5039 pi->min_vddc_in_table,
5040 0,
5041 0,
5042 &table->ACPIState.levels[0].vddc);
5043 }
5044
5045 if (pi->acpi_vddc) {
5046 if (eg_pi->acpi_vddci)
5047 si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table,
5048 eg_pi->acpi_vddci,
5049 &table->ACPIState.levels[0].vddci);
5050 }
5051
5052 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
5053 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
5054
5055 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
5056
5057 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
5058 spll_func_cntl_2 |= SCLK_MUX_SEL(4);
5059
5060 table->ACPIState.levels[0].mclk.vDLL_CNTL =
5061 cpu_to_be32(dll_cntl);
5062 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
5063 cpu_to_be32(mclk_pwrmgt_cntl);
5064 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
5065 cpu_to_be32(mpll_ad_func_cntl);
5066 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
5067 cpu_to_be32(mpll_dq_func_cntl);
5068 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =
5069 cpu_to_be32(mpll_func_cntl);
5070 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
5071 cpu_to_be32(mpll_func_cntl_1);
5072 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
5073 cpu_to_be32(mpll_func_cntl_2);
5074 table->ACPIState.levels[0].mclk.vMPLL_SS =
5075 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
5076 table->ACPIState.levels[0].mclk.vMPLL_SS2 =
5077 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
5078
5079 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
5080 cpu_to_be32(spll_func_cntl);
5081 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
5082 cpu_to_be32(spll_func_cntl_2);
5083 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
5084 cpu_to_be32(spll_func_cntl_3);
5085 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
5086 cpu_to_be32(spll_func_cntl_4);
5087
5088 table->ACPIState.levels[0].mclk.mclk_value = 0;
5089 table->ACPIState.levels[0].sclk.sclk_value = 0;
5090
5091 si_populate_mvdd_value(adev, 0, &table->ACPIState.levels[0].mvdd);
5092
5093 if (eg_pi->dynamic_ac_timing)
5094 table->ACPIState.levels[0].ACIndex = 0;
5095
5096 table->ACPIState.levels[0].dpm2.MaxPS = 0;
5097 table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
5098 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
5099 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
5100 table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;
5101
5102 reg = MIN_POWER_MASK | MAX_POWER_MASK;
5103 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
5104
5105 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
5106 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
5107
5108 return 0;
5109}
5110
5111static int si_populate_ulv_state(struct amdgpu_device *adev,
5112 SISLANDS_SMC_SWSTATE *state)
5113{
5114 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5115 struct si_power_info *si_pi = si_get_pi(adev);
5116 struct si_ulv_param *ulv = &si_pi->ulv;
5117 u32 sclk_in_sr = 1350; /* ??? */
5118 int ret;
5119
5120 ret = si_convert_power_level_to_smc(adev, &ulv->pl,
5121 &state->levels[0]);
5122 if (!ret) {
5123 if (eg_pi->sclk_deep_sleep) {
5124 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5125 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5126 else
5127 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5128 }
5129 if (ulv->one_pcie_lane_in_ulv)
5130 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1;
5131 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
5132 state->levels[0].ACIndex = 1;
5133 state->levels[0].std_vddc = state->levels[0].vddc;
5134 state->levelCount = 1;
5135
5136 state->flags |= PPSMC_SWSTATE_FLAG_DC;
5137 }
5138
5139 return ret;
5140}
5141
5142static int si_program_ulv_memory_timing_parameters(struct amdgpu_device *adev)
5143{
5144 struct si_power_info *si_pi = si_get_pi(adev);
5145 struct si_ulv_param *ulv = &si_pi->ulv;
5146 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
5147 int ret;
5148
5149 ret = si_populate_memory_timing_parameters(adev, &ulv->pl,
5150 &arb_regs);
5151 if (ret)
5152 return ret;
5153
5154 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
5155 ulv->volt_change_delay);
5156
5157 ret = si_copy_bytes_to_smc(adev,
5158 si_pi->arb_table_start +
5159 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
5160 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
5161 (u8 *)&arb_regs,
5162 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
5163 si_pi->sram_end);
5164
5165 return ret;
5166}
5167
5168static void si_get_mvdd_configuration(struct amdgpu_device *adev)
5169{
5170 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5171
5172 pi->mvdd_split_frequency = 30000;
5173}
5174
5175static int si_init_smc_table(struct amdgpu_device *adev)
5176{
5177 struct si_power_info *si_pi = si_get_pi(adev);
5178 struct amdgpu_ps *amdgpu_boot_state = adev->pm.dpm.boot_ps;
5179 const struct si_ulv_param *ulv = &si_pi->ulv;
5180 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable;
5181 int ret;
5182 u32 lane_width;
5183 u32 vr_hot_gpio;
5184
5185 si_populate_smc_voltage_tables(adev, table);
5186
5187 switch (adev->pm.int_thermal_type) {
5188 case THERMAL_TYPE_SI:
5189 case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
5190 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
5191 break;
5192 case THERMAL_TYPE_NONE:
5193 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
5194 break;
5195 default:
5196 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
5197 break;
5198 }
5199
5200 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
5201 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
5202
5203 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
5204 if ((adev->pdev->device != 0x6818) && (adev->pdev->device != 0x6819))
5205 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
5206 }
5207
5208 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
5209 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
5210
5211 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
5212 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
5213
5214 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
5215 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;
5216
5217 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
5218 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;
5219 vr_hot_gpio = adev->pm.dpm.backbias_response_time;
5220 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
5221 vr_hot_gpio);
5222 }
5223
5224 ret = si_populate_smc_initial_state(adev, amdgpu_boot_state, table);
5225 if (ret)
5226 return ret;
5227
5228 ret = si_populate_smc_acpi_state(adev, table);
5229 if (ret)
5230 return ret;
5231
5232 table->driverState = table->initialState;
5233
5234 ret = si_do_program_memory_timing_parameters(adev, amdgpu_boot_state,
5235 SISLANDS_INITIAL_STATE_ARB_INDEX);
5236 if (ret)
5237 return ret;
5238
5239 if (ulv->supported && ulv->pl.vddc) {
5240 ret = si_populate_ulv_state(adev, &table->ULVState);
5241 if (ret)
5242 return ret;
5243
5244 ret = si_program_ulv_memory_timing_parameters(adev);
5245 if (ret)
5246 return ret;
5247
5248 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);
5249 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
5250
5251 lane_width = amdgpu_get_pcie_lanes(adev);
5252 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5253 } else {
5254 table->ULVState = table->initialState;
5255 }
5256
5257 return si_copy_bytes_to_smc(adev, si_pi->state_table_start,
5258 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
5259 si_pi->sram_end);
5260}
5261
5262static int si_calculate_sclk_params(struct amdgpu_device *adev,
5263 u32 engine_clock,
5264 SISLANDS_SMC_SCLK_VALUE *sclk)
5265{
5266 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5267 struct si_power_info *si_pi = si_get_pi(adev);
5268 struct atom_clock_dividers dividers;
5269 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
5270 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
5271 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
5272 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
5273 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;
5274 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;
5275 u64 tmp;
5276 u32 reference_clock = adev->clock.spll.reference_freq;
5277 u32 reference_divider;
5278 u32 fbdiv;
5279 int ret;
5280
5281 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
5282 engine_clock, false, &dividers);
5283 if (ret)
5284 return ret;
5285
5286 reference_divider = 1 + dividers.ref_div;
5287
5288 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
5289 do_div(tmp, reference_clock);
5290 fbdiv = (u32) tmp;
5291
5292 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
5293 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
5294 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
5295
5296 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
5297 spll_func_cntl_2 |= SCLK_MUX_SEL(2);
5298
77d318a6
TSD		 5299 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
5300 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
5301 spll_func_cntl_3 |= SPLL_DITHEN;
841686df
MB		 5302
5303 if (pi->sclk_ss) {
5304 struct amdgpu_atom_ss ss;
5305 u32 vco_freq = engine_clock * dividers.post_div;
5306
5307 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
5308 ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
5309 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
5310 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
5311
5312 cg_spll_spread_spectrum &= ~CLK_S_MASK;
5313 cg_spll_spread_spectrum |= CLK_S(clk_s);
5314 cg_spll_spread_spectrum |= SSEN;
5315
5316 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
5317 cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
5318 }
5319 }
5320
5321 sclk->sclk_value = engine_clock;
5322 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
5323 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
5324 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
5325 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
5326 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
5327 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
5328
5329 return 0;
5330}
5331
5332static int si_populate_sclk_value(struct amdgpu_device *adev,
5333 u32 engine_clock,
5334 SISLANDS_SMC_SCLK_VALUE *sclk)
5335{
5336 SISLANDS_SMC_SCLK_VALUE sclk_tmp;
5337 int ret;
5338
5339 ret = si_calculate_sclk_params(adev, engine_clock, &sclk_tmp);
5340 if (!ret) {
5341 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
5342 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
5343 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
5344 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
5345 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
5346 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
5347 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
5348 }
5349
5350 return ret;
5351}
5352
5353static int si_populate_mclk_value(struct amdgpu_device *adev,
5354 u32 engine_clock,
5355 u32 memory_clock,
5356 SISLANDS_SMC_MCLK_VALUE *mclk,
5357 bool strobe_mode,
5358 bool dll_state_on)
5359{
5360 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5361 struct si_power_info *si_pi = si_get_pi(adev);
5362 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
5363 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
5364 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
5365 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
5366 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
5367 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
5368 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
5369 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1;
5370 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2;
5371 struct atom_mpll_param mpll_param;
5372 int ret;
5373
5374 ret = amdgpu_atombios_get_memory_pll_dividers(adev, memory_clock, strobe_mode, &mpll_param);
5375 if (ret)
5376 return ret;
5377
5378 mpll_func_cntl &= ~BWCTRL_MASK;
5379 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
5380
5381 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
5382 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
5383 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
5384
5385 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
5386 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
5387
5388 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
5389 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
5390 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
5391 YCLK_POST_DIV(mpll_param.post_div);
5392 }
5393
5394 if (pi->mclk_ss) {
5395 struct amdgpu_atom_ss ss;
5396 u32 freq_nom;
5397 u32 tmp;
5398 u32 reference_clock = adev->clock.mpll.reference_freq;
5399
5400 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
5401 freq_nom = memory_clock * 4;
5402 else
5403 freq_nom = memory_clock * 2;
5404
5405 tmp = freq_nom / reference_clock;
5406 tmp = tmp * tmp;
5407 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
77d318a6 5408 ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
841686df
MB		 5409 u32 clks = reference_clock * 5 / ss.rate;
5410 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
5411
77d318a6
TSD		 5412 mpll_ss1 &= ~CLKV_MASK;
5413 mpll_ss1 |= CLKV(clkv);
841686df 5414
77d318a6
TSD		 5415 mpll_ss2 &= ~CLKS_MASK;
5416 mpll_ss2 |= CLKS(clks);
841686df
MB		 5417 }
5418 }
5419
5420 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
5421 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
5422
5423 if (dll_state_on)
5424 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
5425 else
5426 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
5427
5428 mclk->mclk_value = cpu_to_be32(memory_clock);
5429 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
5430 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
5431 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2);
5432 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
5433 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
5434 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
5435 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
5436 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
5437 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
5438
5439 return 0;
5440}
5441
5442static void si_populate_smc_sp(struct amdgpu_device *adev,
5443 struct amdgpu_ps *amdgpu_state,
5444 SISLANDS_SMC_SWSTATE *smc_state)
5445{
5446 struct si_ps *ps = si_get_ps(amdgpu_state);
5447 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5448 int i;
5449
5450 for (i = 0; i < ps->performance_level_count - 1; i++)
5451 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
5452
5453 smc_state->levels[ps->performance_level_count - 1].bSP =
5454 cpu_to_be32(pi->psp);
5455}
5456
5457static int si_convert_power_level_to_smc(struct amdgpu_device *adev,
5458 struct rv7xx_pl *pl,
5459 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
5460{
5461 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5462 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5463 struct si_power_info *si_pi = si_get_pi(adev);
5464 int ret;
5465 bool dll_state_on;
5466 u16 std_vddc;
5467 bool gmc_pg = false;
5468
5469 if (eg_pi->pcie_performance_request &&
5470 (si_pi->force_pcie_gen != AMDGPU_PCIE_GEN_INVALID))
5471 level->gen2PCIE = (u8)si_pi->force_pcie_gen;
5472 else
5473 level->gen2PCIE = (u8)pl->pcie_gen;
5474
5475 ret = si_populate_sclk_value(adev, pl->sclk, &level->sclk);
5476 if (ret)
5477 return ret;
5478
5479 level->mcFlags = 0;
5480
5481 if (pi->mclk_stutter_mode_threshold &&
5482 (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
5483 !eg_pi->uvd_enabled &&
5484 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
5485 (adev->pm.dpm.new_active_crtc_count <= 2)) {
5486 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
5487
5488 if (gmc_pg)
5489 level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
5490 }
5491
5492 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
5493 if (pl->mclk > pi->mclk_edc_enable_threshold)
5494 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
5495
5496 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
5497 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG;
5498
5499 level->strobeMode = si_get_strobe_mode_settings(adev, pl->mclk);
5500
5501 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) {
5502 if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
5503 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
5504 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5505 else
5506 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
5507 } else {
5508 dll_state_on = false;
5509 }
5510 } else {
5511 level->strobeMode = si_get_strobe_mode_settings(adev,
5512 pl->mclk);
5513
5514 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5515 }
5516
5517 ret = si_populate_mclk_value(adev,
5518 pl->sclk,
5519 pl->mclk,
5520 &level->mclk,
5521 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on);
5522 if (ret)
5523 return ret;
5524
5525 ret = si_populate_voltage_value(adev,
5526 &eg_pi->vddc_voltage_table,
5527 pl->vddc, &level->vddc);
5528 if (ret)
5529 return ret;
5530
5531
5532 ret = si_get_std_voltage_value(adev, &level->vddc, &std_vddc);
5533 if (ret)
5534 return ret;
5535
5536 ret = si_populate_std_voltage_value(adev, std_vddc,
5537 level->vddc.index, &level->std_vddc);
5538 if (ret)
5539 return ret;
5540
5541 if (eg_pi->vddci_control) {
5542 ret = si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table,
5543 pl->vddci, &level->vddci);
5544 if (ret)
5545 return ret;
5546 }
5547
5548 if (si_pi->vddc_phase_shed_control) {
5549 ret = si_populate_phase_shedding_value(adev,
5550 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5551 pl->vddc,
5552 pl->sclk,
5553 pl->mclk,
5554 &level->vddc);
5555 if (ret)
5556 return ret;
5557 }
5558
5559 level->MaxPoweredUpCU = si_pi->max_cu;
5560
5561 ret = si_populate_mvdd_value(adev, pl->mclk, &level->mvdd);
5562
5563 return ret;
5564}
5565
5566static int si_populate_smc_t(struct amdgpu_device *adev,
5567 struct amdgpu_ps *amdgpu_state,
5568 SISLANDS_SMC_SWSTATE *smc_state)
5569{
5570 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5571 struct si_ps *state = si_get_ps(amdgpu_state);
5572 u32 a_t;
5573 u32 t_l, t_h;
5574 u32 high_bsp;
5575 int i, ret;
5576
5577 if (state->performance_level_count >= 9)
5578 return -EINVAL;
5579
5580 if (state->performance_level_count < 2) {
5581 a_t = CG_R(0xffff) | CG_L(0);
5582 smc_state->levels[0].aT = cpu_to_be32(a_t);
5583 return 0;
5584 }
5585
5586 smc_state->levels[0].aT = cpu_to_be32(0);
5587
5588 for (i = 0; i <= state->performance_level_count - 2; i++) {
5589 ret = r600_calculate_at(
5590 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1),
5591 100 * R600_AH_DFLT,
5592 state->performance_levels[i + 1].sclk,
5593 state->performance_levels[i].sclk,
5594 &t_l,
5595 &t_h);
5596
5597 if (ret) {
5598 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
5599 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
5600 }
5601
5602 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
5603 a_t |= CG_R(t_l * pi->bsp / 20000);
5604 smc_state->levels[i].aT = cpu_to_be32(a_t);
5605
5606 high_bsp = (i == state->performance_level_count - 2) ?
5607 pi->pbsp : pi->bsp;
5608 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000);
5609 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
5610 }
5611
5612 return 0;
5613}
5614
5615static int si_disable_ulv(struct amdgpu_device *adev)
5616{
5617 struct si_power_info *si_pi = si_get_pi(adev);
5618 struct si_ulv_param *ulv = &si_pi->ulv;
5619
5620 if (ulv->supported)
5621 return (si_send_msg_to_smc(adev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
5622 0 : -EINVAL;
5623
5624 return 0;
5625}
5626
5627static bool si_is_state_ulv_compatible(struct amdgpu_device *adev,
5628 struct amdgpu_ps *amdgpu_state)
5629{
5630 const struct si_power_info *si_pi = si_get_pi(adev);
5631 const struct si_ulv_param *ulv = &si_pi->ulv;
5632 const struct si_ps *state = si_get_ps(amdgpu_state);
5633 int i;
5634
5635 if (state->performance_levels[0].mclk != ulv->pl.mclk)
5636 return false;
5637
5638 /* XXX validate against display requirements! */
5639
5640 for (i = 0; i < adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
5641 if (adev->clock.current_dispclk <=
5642 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
5643 if (ulv->pl.vddc <
5644 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
5645 return false;
5646 }
5647 }
5648
5649 if ((amdgpu_state->vclk != 0) || (amdgpu_state->dclk != 0))
5650 return false;
5651
5652 return true;
5653}
5654
5655static int si_set_power_state_conditionally_enable_ulv(struct amdgpu_device *adev,
5656 struct amdgpu_ps *amdgpu_new_state)
5657{
5658 const struct si_power_info *si_pi = si_get_pi(adev);
5659 const struct si_ulv_param *ulv = &si_pi->ulv;
5660
5661 if (ulv->supported) {
5662 if (si_is_state_ulv_compatible(adev, amdgpu_new_state))
5663 return (si_send_msg_to_smc(adev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
5664 0 : -EINVAL;
5665 }
5666 return 0;
5667}
5668
5669static int si_convert_power_state_to_smc(struct amdgpu_device *adev,
5670 struct amdgpu_ps *amdgpu_state,
5671 SISLANDS_SMC_SWSTATE *smc_state)
5672{
5673 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5674 struct ni_power_info *ni_pi = ni_get_pi(adev);
5675 struct si_power_info *si_pi = si_get_pi(adev);
5676 struct si_ps *state = si_get_ps(amdgpu_state);
5677 int i, ret;
5678 u32 threshold;
5679 u32 sclk_in_sr = 1350; /* ??? */
5680
5681 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
5682 return -EINVAL;
5683
5684 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
5685
5686 if (amdgpu_state->vclk && amdgpu_state->dclk) {
5687 eg_pi->uvd_enabled = true;
5688 if (eg_pi->smu_uvd_hs)
5689 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;
5690 } else {
5691 eg_pi->uvd_enabled = false;
5692 }
5693
5694 if (state->dc_compatible)
5695 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
5696
5697 smc_state->levelCount = 0;
5698 for (i = 0; i < state->performance_level_count; i++) {
5699 if (eg_pi->sclk_deep_sleep) {
5700 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {
5701 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5702 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5703 else
5704 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5705 }
5706 }
5707
5708 ret = si_convert_power_level_to_smc(adev, &state->performance_levels[i],
5709 &smc_state->levels[i]);
5710 smc_state->levels[i].arbRefreshState =
5711 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);
5712
5713 if (ret)
5714 return ret;
5715
5716 if (ni_pi->enable_power_containment)
5717 smc_state->levels[i].displayWatermark =
5718 (state->performance_levels[i].sclk < threshold) ?
5719 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5720 else
5721 smc_state->levels[i].displayWatermark = (i < 2) ?
5722 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5723
5724 if (eg_pi->dynamic_ac_timing)
5725 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
5726 else
5727 smc_state->levels[i].ACIndex = 0;
5728
5729 smc_state->levelCount++;
5730 }
5731
5732 si_write_smc_soft_register(adev,
5733 SI_SMC_SOFT_REGISTER_watermark_threshold,
5734 threshold / 512);
5735
5736 si_populate_smc_sp(adev, amdgpu_state, smc_state);
5737
5738 ret = si_populate_power_containment_values(adev, amdgpu_state, smc_state);
5739 if (ret)
5740 ni_pi->enable_power_containment = false;
5741
5742 ret = si_populate_sq_ramping_values(adev, amdgpu_state, smc_state);
77d318a6 5743 if (ret)
841686df
MB		 5744 ni_pi->enable_sq_ramping = false;
5745
5746 return si_populate_smc_t(adev, amdgpu_state, smc_state);
5747}
5748
5749static int si_upload_sw_state(struct amdgpu_device *adev,
5750 struct amdgpu_ps *amdgpu_new_state)
5751{
5752 struct si_power_info *si_pi = si_get_pi(adev);
5753 struct si_ps *new_state = si_get_ps(amdgpu_new_state);
5754 int ret;
5755 u32 address = si_pi->state_table_start +
5756 offsetof(SISLANDS_SMC_STATETABLE, driverState);
5757 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) +
5758 ((new_state->performance_level_count - 1) *
5759 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL));
5760 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
5761
5762 memset(smc_state, 0, state_size);
5763
5764 ret = si_convert_power_state_to_smc(adev, amdgpu_new_state, smc_state);
5765 if (ret)
5766 return ret;
5767
77d318a6
TSD		 5768 return si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
5769 state_size, si_pi->sram_end);
841686df
MB		 5770}
5771
5772static int si_upload_ulv_state(struct amdgpu_device *adev)
5773{
5774 struct si_power_info *si_pi = si_get_pi(adev);
5775 struct si_ulv_param *ulv = &si_pi->ulv;
5776 int ret = 0;
5777
5778 if (ulv->supported && ulv->pl.vddc) {
5779 u32 address = si_pi->state_table_start +
5780 offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5781 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;
5782 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE);
5783
5784 memset(smc_state, 0, state_size);
5785
5786 ret = si_populate_ulv_state(adev, smc_state);
5787 if (!ret)
5788 ret = si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
5789 state_size, si_pi->sram_end);
5790 }
5791
5792 return ret;
5793}
5794
5795static int si_upload_smc_data(struct amdgpu_device *adev)
5796{
5797 struct amdgpu_crtc *amdgpu_crtc = NULL;
5798 int i;
5799
5800 if (adev->pm.dpm.new_active_crtc_count == 0)
5801 return 0;
5802
5803 for (i = 0; i < adev->mode_info.num_crtc; i++) {
5804 if (adev->pm.dpm.new_active_crtcs & (1 << i)) {
5805 amdgpu_crtc = adev->mode_info.crtcs[i];
5806 break;
5807 }
5808 }
5809
5810 if (amdgpu_crtc == NULL)
5811 return 0;
5812
5813 if (amdgpu_crtc->line_time <= 0)
5814 return 0;
5815
5816 if (si_write_smc_soft_register(adev,
5817 SI_SMC_SOFT_REGISTER_crtc_index,
5818 amdgpu_crtc->crtc_id) != PPSMC_Result_OK)
5819 return 0;
5820
5821 if (si_write_smc_soft_register(adev,
5822 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
5823 amdgpu_crtc->wm_high / amdgpu_crtc->line_time) != PPSMC_Result_OK)
5824 return 0;
5825
5826 if (si_write_smc_soft_register(adev,
5827 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
5828 amdgpu_crtc->wm_low / amdgpu_crtc->line_time) != PPSMC_Result_OK)
5829 return 0;
5830
5831 return 0;
5832}
5833
5834static int si_set_mc_special_registers(struct amdgpu_device *adev,
5835 struct si_mc_reg_table *table)
5836{
5837 u8 i, j, k;
5838 u32 temp_reg;
5839
5840 for (i = 0, j = table->last; i < table->last; i++) {
5841 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5842 return -EINVAL;
5843 switch (table->mc_reg_address[i].s1) {
5844 case MC_SEQ_MISC1:
5845 temp_reg = RREG32(MC_PMG_CMD_EMRS);
5846 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS;
5847 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP;
5848 for (k = 0; k < table->num_entries; k++)
5849 table->mc_reg_table_entry[k].mc_data[j] =
5850 ((temp_reg & 0xffff0000)) |
5851 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
5852 j++;
5853 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5854 return -EINVAL;
5855
5856 temp_reg = RREG32(MC_PMG_CMD_MRS);
5857 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS;
5858 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP;
5859 for (k = 0; k < table->num_entries; k++) {
5860 table->mc_reg_table_entry[k].mc_data[j] =
5861 (temp_reg & 0xffff0000) |
5862 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5863 if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5)
5864 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5865 }
5866 j++;
5867 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5868 return -EINVAL;
5869
5870 if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) {
5871 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD;
5872 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD;
5873 for (k = 0; k < table->num_entries; k++)
5874 table->mc_reg_table_entry[k].mc_data[j] =
5875 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5876 j++;
5877 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5878 return -EINVAL;
5879 }
5880 break;
5881 case MC_SEQ_RESERVE_M:
5882 temp_reg = RREG32(MC_PMG_CMD_MRS1);
5883 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1;
5884 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP;
5885 for(k = 0; k < table->num_entries; k++)
5886 table->mc_reg_table_entry[k].mc_data[j] =
5887 (temp_reg & 0xffff0000) |
5888 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5889 j++;
5890 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5891 return -EINVAL;
5892 break;
5893 default:
5894 break;
5895 }
5896 }
5897
5898 table->last = j;
5899
5900 return 0;
5901}
5902
5903static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
5904{
5905 bool result = true;
5906 switch (in_reg) {
5907 case MC_SEQ_RAS_TIMING:
5908 *out_reg = MC_SEQ_RAS_TIMING_LP;
5909 break;
77d318a6 5910 case MC_SEQ_CAS_TIMING:
841686df
MB		 5911 *out_reg = MC_SEQ_CAS_TIMING_LP;
5912 break;
77d318a6 5913 case MC_SEQ_MISC_TIMING:
841686df
MB		 5914 *out_reg = MC_SEQ_MISC_TIMING_LP;
5915 break;
77d318a6 5916 case MC_SEQ_MISC_TIMING2:
841686df
MB		 5917 *out_reg = MC_SEQ_MISC_TIMING2_LP;
5918 break;
77d318a6 5919 case MC_SEQ_RD_CTL_D0:
841686df
MB		 5920 *out_reg = MC_SEQ_RD_CTL_D0_LP;
5921 break;
77d318a6 5922 case MC_SEQ_RD_CTL_D1:
841686df
MB		 5923 *out_reg = MC_SEQ_RD_CTL_D1_LP;
5924 break;
77d318a6 5925 case MC_SEQ_WR_CTL_D0:
841686df
MB		 5926 *out_reg = MC_SEQ_WR_CTL_D0_LP;
5927 break;
77d318a6 5928 case MC_SEQ_WR_CTL_D1:
841686df
MB		 5929 *out_reg = MC_SEQ_WR_CTL_D1_LP;
5930 break;
77d318a6 5931 case MC_PMG_CMD_EMRS:
841686df
MB		 5932 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP;
5933 break;
77d318a6 5934 case MC_PMG_CMD_MRS:
841686df
MB		 5935 *out_reg = MC_SEQ_PMG_CMD_MRS_LP;
5936 break;
77d318a6 5937 case MC_PMG_CMD_MRS1:
841686df
MB		 5938 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP;
5939 break;
77d318a6 5940 case MC_SEQ_PMG_TIMING:
841686df
MB		 5941 *out_reg = MC_SEQ_PMG_TIMING_LP;
5942 break;
77d318a6 5943 case MC_PMG_CMD_MRS2:
841686df
MB		 5944 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP;
5945 break;
77d318a6 5946 case MC_SEQ_WR_CTL_2:
841686df
MB		 5947 *out_reg = MC_SEQ_WR_CTL_2_LP;
5948 break;
77d318a6 5949 default:
841686df
MB		 5950 result = false;
5951 break;
5952 }
5953
5954 return result;
5955}
5956
5957static void si_set_valid_flag(struct si_mc_reg_table *table)
5958{
5959 u8 i, j;
5960
5961 for (i = 0; i < table->last; i++) {
5962 for (j = 1; j < table->num_entries; j++) {
5963 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
5964 table->valid_flag |= 1 << i;
5965 break;
5966 }
5967 }
5968 }
5969}
5970
5971static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
5972{
5973 u32 i;
5974 u16 address;
5975
5976 for (i = 0; i < table->last; i++)
5977 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
5978 address : table->mc_reg_address[i].s1;
5979
5980}
5981
5982static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
5983 struct si_mc_reg_table *si_table)
5984{
5985 u8 i, j;
5986
5987 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5988 return -EINVAL;
5989 if (table->num_entries > MAX_AC_TIMING_ENTRIES)
5990 return -EINVAL;
5991
5992 for (i = 0; i < table->last; i++)
5993 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
5994 si_table->last = table->last;
5995
5996 for (i = 0; i < table->num_entries; i++) {
5997 si_table->mc_reg_table_entry[i].mclk_max =
5998 table->mc_reg_table_entry[i].mclk_max;
5999 for (j = 0; j < table->last; j++) {
6000 si_table->mc_reg_table_entry[i].mc_data[j] =
6001 table->mc_reg_table_entry[i].mc_data[j];
6002 }
6003 }
6004 si_table->num_entries = table->num_entries;
6005
6006 return 0;
6007}
6008
6009static int si_initialize_mc_reg_table(struct amdgpu_device *adev)
6010{
6011 struct si_power_info *si_pi = si_get_pi(adev);
6012 struct atom_mc_reg_table *table;
6013 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;
6014 u8 module_index = rv770_get_memory_module_index(adev);
6015 int ret;
6016
6017 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
6018 if (!table)
6019 return -ENOMEM;
6020
6021 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
6022 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
6023 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
6024 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
6025 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
6026 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
6027 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
6028 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
6029 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
6030 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
6031 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
6032 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
6033 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
6034 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
6035
77d318a6
TSD		 6036 ret = amdgpu_atombios_init_mc_reg_table(adev, module_index, table);
6037 if (ret)
6038 goto init_mc_done;
841686df 6039
77d318a6
TSD		 6040 ret = si_copy_vbios_mc_reg_table(table, si_table);
6041 if (ret)
6042 goto init_mc_done;
841686df
MB		 6043
6044 si_set_s0_mc_reg_index(si_table);
6045
6046 ret = si_set_mc_special_registers(adev, si_table);
77d318a6
TSD		 6047 if (ret)
6048 goto init_mc_done;
841686df
MB		 6049
6050 si_set_valid_flag(si_table);
6051
6052init_mc_done:
6053 kfree(table);
6054
6055 return ret;
6056
6057}
6058
6059static void si_populate_mc_reg_addresses(struct amdgpu_device *adev,
6060 SMC_SIslands_MCRegisters *mc_reg_table)
6061{
6062 struct si_power_info *si_pi = si_get_pi(adev);
6063 u32 i, j;
6064
6065 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
6066 if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
6067 if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
6068 break;
6069 mc_reg_table->address[i].s0 =
6070 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
6071 mc_reg_table->address[i].s1 =
6072 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);
6073 i++;
6074 }
6075 }
6076 mc_reg_table->last = (u8)i;
6077}
6078
6079static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
6080 SMC_SIslands_MCRegisterSet *data,
6081 u32 num_entries, u32 valid_flag)
6082{
6083 u32 i, j;
6084
6085 for(i = 0, j = 0; j < num_entries; j++) {
6086 if (valid_flag & (1 << j)) {
6087 data->value[i] = cpu_to_be32(entry->mc_data[j]);
6088 i++;
6089 }
6090 }
6091}
6092
6093static void si_convert_mc_reg_table_entry_to_smc(struct amdgpu_device *adev,
6094 struct rv7xx_pl *pl,
6095 SMC_SIslands_MCRegisterSet *mc_reg_table_data)
6096{
6097 struct si_power_info *si_pi = si_get_pi(adev);
6098 u32 i = 0;
6099
6100 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {
6101 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
6102 break;
6103 }
6104
6105 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))
6106 --i;
6107
6108 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],
6109 mc_reg_table_data, si_pi->mc_reg_table.last,
6110 si_pi->mc_reg_table.valid_flag);
6111}
6112
6113static void si_convert_mc_reg_table_to_smc(struct amdgpu_device *adev,
6114 struct amdgpu_ps *amdgpu_state,
6115 SMC_SIslands_MCRegisters *mc_reg_table)
6116{
77d318a6 6117 struct si_ps *state = si_get_ps(amdgpu_state);
841686df
MB		 6118 int i;
6119
6120 for (i = 0; i < state->performance_level_count; i++) {
6121 si_convert_mc_reg_table_entry_to_smc(adev,
6122 &state->performance_levels[i],
6123 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
6124 }
6125}
6126
6127static int si_populate_mc_reg_table(struct amdgpu_device *adev,
6128 struct amdgpu_ps *amdgpu_boot_state)
6129{
6130 struct si_ps *boot_state = si_get_ps(amdgpu_boot_state);
6131 struct si_power_info *si_pi = si_get_pi(adev);
6132 struct si_ulv_param *ulv = &si_pi->ulv;
6133 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
6134
6135 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
6136
6137 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_seq_index, 1);
6138
6139 si_populate_mc_reg_addresses(adev, smc_mc_reg_table);
6140
6141 si_convert_mc_reg_table_entry_to_smc(adev, &boot_state->performance_levels[0],
6142 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]);
6143
6144 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
6145 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT],
6146 si_pi->mc_reg_table.last,
6147 si_pi->mc_reg_table.valid_flag);
6148
6149 if (ulv->supported && ulv->pl.vddc != 0)
6150 si_convert_mc_reg_table_entry_to_smc(adev, &ulv->pl,
6151 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]);
6152 else
6153 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
6154 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT],
6155 si_pi->mc_reg_table.last,
6156 si_pi->mc_reg_table.valid_flag);
6157
6158 si_convert_mc_reg_table_to_smc(adev, amdgpu_boot_state, smc_mc_reg_table);
6159
6160 return si_copy_bytes_to_smc(adev, si_pi->mc_reg_table_start,
6161 (u8 *)smc_mc_reg_table,
6162 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
6163}
6164
6165static int si_upload_mc_reg_table(struct amdgpu_device *adev,
6166 struct amdgpu_ps *amdgpu_new_state)
6167{
77d318a6 6168 struct si_ps *new_state = si_get_ps(amdgpu_new_state);
841686df
MB		 6169 struct si_power_info *si_pi = si_get_pi(adev);
6170 u32 address = si_pi->mc_reg_table_start +
6171 offsetof(SMC_SIslands_MCRegisters,
6172 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
6173 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
6174
6175 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
6176
6177 si_convert_mc_reg_table_to_smc(adev, amdgpu_new_state, smc_mc_reg_table);
6178
841686df
MB		 6179 return si_copy_bytes_to_smc(adev, address,
6180 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
6181 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
6182 si_pi->sram_end);
841686df
MB		 6183}
6184
6185static void si_enable_voltage_control(struct amdgpu_device *adev, bool enable)
6186{
77d318a6
TSD		 6187 if (enable)
6188 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
6189 else
6190 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
841686df
MB		 6191}
6192
6193static enum amdgpu_pcie_gen si_get_maximum_link_speed(struct amdgpu_device *adev,
6194 struct amdgpu_ps *amdgpu_state)
6195{
77d318a6 6196 struct si_ps *state = si_get_ps(amdgpu_state);
841686df
MB		 6197 int i;
6198 u16 pcie_speed, max_speed = 0;
6199
6200 for (i = 0; i < state->performance_level_count; i++) {
6201 pcie_speed = state->performance_levels[i].pcie_gen;
6202 if (max_speed < pcie_speed)
6203 max_speed = pcie_speed;
6204 }
6205 return max_speed;
6206}
6207
6208static u16 si_get_current_pcie_speed(struct amdgpu_device *adev)
6209{
6210 u32 speed_cntl;
6211
6212 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
6213 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
6214
6215 return (u16)speed_cntl;
6216}
6217
6218static void si_request_link_speed_change_before_state_change(struct amdgpu_device *adev,
6219 struct amdgpu_ps *amdgpu_new_state,
6220 struct amdgpu_ps *amdgpu_current_state)
6221{
6222 struct si_power_info *si_pi = si_get_pi(adev);
6223 enum amdgpu_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state);
6224 enum amdgpu_pcie_gen current_link_speed;
6225
6226 if (si_pi->force_pcie_gen == AMDGPU_PCIE_GEN_INVALID)
6227 current_link_speed = si_get_maximum_link_speed(adev, amdgpu_current_state);
6228 else
6229 current_link_speed = si_pi->force_pcie_gen;
6230
6231 si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
6232 si_pi->pspp_notify_required = false;
6233 if (target_link_speed > current_link_speed) {
6234 switch (target_link_speed) {
6235#if defined(CONFIG_ACPI)
6236 case AMDGPU_PCIE_GEN3:
6237 if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
6238 break;
6239 si_pi->force_pcie_gen = AMDGPU_PCIE_GEN2;
6240 if (current_link_speed == AMDGPU_PCIE_GEN2)
6241 break;
6242 case AMDGPU_PCIE_GEN2:
6243 if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
6244 break;
6245#endif
6246 default:
6247 si_pi->force_pcie_gen = si_get_current_pcie_speed(adev);
6248 break;
6249 }
6250 } else {
6251 if (target_link_speed < current_link_speed)
6252 si_pi->pspp_notify_required = true;
6253 }
6254}
6255
6256static void si_notify_link_speed_change_after_state_change(struct amdgpu_device *adev,
6257 struct amdgpu_ps *amdgpu_new_state,
6258 struct amdgpu_ps *amdgpu_current_state)
6259{
6260 struct si_power_info *si_pi = si_get_pi(adev);
6261 enum amdgpu_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state);
6262 u8 request;
6263
6264 if (si_pi->pspp_notify_required) {
6265 if (target_link_speed == AMDGPU_PCIE_GEN3)
6266 request = PCIE_PERF_REQ_PECI_GEN3;
6267 else if (target_link_speed == AMDGPU_PCIE_GEN2)
6268 request = PCIE_PERF_REQ_PECI_GEN2;
6269 else
6270 request = PCIE_PERF_REQ_PECI_GEN1;
6271
6272 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
6273 (si_get_current_pcie_speed(adev) > 0))
6274 return;
6275
6276#if defined(CONFIG_ACPI)
6277 amdgpu_acpi_pcie_performance_request(adev, request, false);
6278#endif
6279 }
6280}
6281
6282#if 0
6283static int si_ds_request(struct amdgpu_device *adev,
6284 bool ds_status_on, u32 count_write)
6285{
6286 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6287
6288 if (eg_pi->sclk_deep_sleep) {
6289 if (ds_status_on)
6290 return (si_send_msg_to_smc(adev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
6291 PPSMC_Result_OK) ?
6292 0 : -EINVAL;
6293 else
6294 return (si_send_msg_to_smc(adev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
6295 PPSMC_Result_OK) ? 0 : -EINVAL;
6296 }
6297 return 0;
6298}
6299#endif
6300
6301static void si_set_max_cu_value(struct amdgpu_device *adev)
6302{
6303 struct si_power_info *si_pi = si_get_pi(adev);
6304
6305 if (adev->asic_type == CHIP_VERDE) {
6306 switch (adev->pdev->device) {
6307 case 0x6820:
6308 case 0x6825:
6309 case 0x6821:
6310 case 0x6823:
6311 case 0x6827:
6312 si_pi->max_cu = 10;
6313 break;
6314 case 0x682D:
6315 case 0x6824:
6316 case 0x682F:
6317 case 0x6826:
6318 si_pi->max_cu = 8;
6319 break;
6320 case 0x6828:
6321 case 0x6830:
6322 case 0x6831:
6323 case 0x6838:
6324 case 0x6839:
6325 case 0x683D:
6326 si_pi->max_cu = 10;
6327 break;
6328 case 0x683B:
6329 case 0x683F:
6330 case 0x6829:
6331 si_pi->max_cu = 8;
6332 break;
6333 default:
6334 si_pi->max_cu = 0;
6335 break;
6336 }
6337 } else {
6338 si_pi->max_cu = 0;
6339 }
6340}
6341
6342static int si_patch_single_dependency_table_based_on_leakage(struct amdgpu_device *adev,
6343 struct amdgpu_clock_voltage_dependency_table *table)
6344{
6345 u32 i;
6346 int j;
6347 u16 leakage_voltage;
6348
6349 if (table) {
6350 for (i = 0; i < table->count; i++) {
6351 switch (si_get_leakage_voltage_from_leakage_index(adev,
6352 table->entries[i].v,
6353 &leakage_voltage)) {
6354 case 0:
6355 table->entries[i].v = leakage_voltage;
6356 break;
6357 case -EAGAIN:
6358 return -EINVAL;
6359 case -EINVAL:
6360 default:
6361 break;
6362 }
6363 }
6364
6365 for (j = (table->count - 2); j >= 0; j--) {
6366 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
6367 table->entries[j].v : table->entries[j + 1].v;
6368 }
6369 }
6370 return 0;
6371}
6372
6373static int si_patch_dependency_tables_based_on_leakage(struct amdgpu_device *adev)
6374{
6375 int ret = 0;
6376
6377 ret = si_patch_single_dependency_table_based_on_leakage(adev,
6378 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
6379 ret = si_patch_single_dependency_table_based_on_leakage(adev,
6380 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
6381 ret = si_patch_single_dependency_table_based_on_leakage(adev,
6382 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
6383 return ret;
6384}
6385
6386static void si_set_pcie_lane_width_in_smc(struct amdgpu_device *adev,
6387 struct amdgpu_ps *amdgpu_new_state,
6388 struct amdgpu_ps *amdgpu_current_state)
6389{
6390 u32 lane_width;
6391 u32 new_lane_width =
6392 (amdgpu_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
6393 u32 current_lane_width =
6394 (amdgpu_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
6395
6396 if (new_lane_width != current_lane_width) {
6397 amdgpu_set_pcie_lanes(adev, new_lane_width);
6398 lane_width = amdgpu_get_pcie_lanes(adev);
6399 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
6400 }
6401}
6402
6403static void si_dpm_setup_asic(struct amdgpu_device *adev)
6404{
6405 si_read_clock_registers(adev);
6406 si_enable_acpi_power_management(adev);
6407}
6408
6409static int si_thermal_enable_alert(struct amdgpu_device *adev,
6410 bool enable)
6411{
6412 u32 thermal_int = RREG32(CG_THERMAL_INT);
6413
6414 if (enable) {
6415 PPSMC_Result result;
6416
6417 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
6418 WREG32(CG_THERMAL_INT, thermal_int);
6419 result = si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
6420 if (result != PPSMC_Result_OK) {
6421 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
6422 return -EINVAL;
6423 }
6424 } else {
6425 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
6426 WREG32(CG_THERMAL_INT, thermal_int);
6427 }
6428
6429 return 0;
6430}
6431
6432static int si_thermal_set_temperature_range(struct amdgpu_device *adev,
6433 int min_temp, int max_temp)
6434{
6435 int low_temp = 0 * 1000;
6436 int high_temp = 255 * 1000;
6437
6438 if (low_temp < min_temp)
6439 low_temp = min_temp;
6440 if (high_temp > max_temp)
6441 high_temp = max_temp;
6442 if (high_temp < low_temp) {
6443 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
6444 return -EINVAL;
6445 }
6446
6447 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
6448 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
6449 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
6450
6451 adev->pm.dpm.thermal.min_temp = low_temp;
6452 adev->pm.dpm.thermal.max_temp = high_temp;
6453
6454 return 0;
6455}
6456
6457static void si_fan_ctrl_set_static_mode(struct amdgpu_device *adev, u32 mode)
6458{
6459 struct si_power_info *si_pi = si_get_pi(adev);
6460 u32 tmp;
6461
6462 if (si_pi->fan_ctrl_is_in_default_mode) {
6463 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
6464 si_pi->fan_ctrl_default_mode = tmp;
6465 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
6466 si_pi->t_min = tmp;
6467 si_pi->fan_ctrl_is_in_default_mode = false;
6468 }
6469
6470 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6471 tmp |= TMIN(0);
6472 WREG32(CG_FDO_CTRL2, tmp);
6473
6474 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6475 tmp |= FDO_PWM_MODE(mode);
6476 WREG32(CG_FDO_CTRL2, tmp);
6477}
6478
6479static int si_thermal_setup_fan_table(struct amdgpu_device *adev)
6480{
6481 struct si_power_info *si_pi = si_get_pi(adev);
6482 PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE };
6483 u32 duty100;
6484 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
6485 u16 fdo_min, slope1, slope2;
6486 u32 reference_clock, tmp;
6487 int ret;
6488 u64 tmp64;
6489
6490 if (!si_pi->fan_table_start) {
6491 adev->pm.dpm.fan.ucode_fan_control = false;
6492 return 0;
6493 }
6494
6495 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6496
6497 if (duty100 == 0) {
6498 adev->pm.dpm.fan.ucode_fan_control = false;
6499 return 0;
6500 }
6501
6502 tmp64 = (u64)adev->pm.dpm.fan.pwm_min * duty100;
6503 do_div(tmp64, 10000);
6504 fdo_min = (u16)tmp64;
6505
6506 t_diff1 = adev->pm.dpm.fan.t_med - adev->pm.dpm.fan.t_min;
6507 t_diff2 = adev->pm.dpm.fan.t_high - adev->pm.dpm.fan.t_med;
6508
6509 pwm_diff1 = adev->pm.dpm.fan.pwm_med - adev->pm.dpm.fan.pwm_min;
6510 pwm_diff2 = adev->pm.dpm.fan.pwm_high - adev->pm.dpm.fan.pwm_med;
6511
6512 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
6513 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
6514
6515 fan_table.temp_min = cpu_to_be16((50 + adev->pm.dpm.fan.t_min) / 100);
6516 fan_table.temp_med = cpu_to_be16((50 + adev->pm.dpm.fan.t_med) / 100);
6517 fan_table.temp_max = cpu_to_be16((50 + adev->pm.dpm.fan.t_max) / 100);
841686df
MB		 6518 fan_table.slope1 = cpu_to_be16(slope1);
6519 fan_table.slope2 = cpu_to_be16(slope2);
841686df 6520 fan_table.fdo_min = cpu_to_be16(fdo_min);
841686df 6521 fan_table.hys_down = cpu_to_be16(adev->pm.dpm.fan.t_hyst);
841686df 6522 fan_table.hys_up = cpu_to_be16(1);
841686df 6523 fan_table.hys_slope = cpu_to_be16(1);
841686df 6524 fan_table.temp_resp_lim = cpu_to_be16(5);
841686df
MB		 6525 reference_clock = amdgpu_asic_get_xclk(adev);
6526
6527 fan_table.refresh_period = cpu_to_be32((adev->pm.dpm.fan.cycle_delay *
6528 reference_clock) / 1600);
841686df
MB		 6529 fan_table.fdo_max = cpu_to_be16((u16)duty100);
6530
6531 tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
6532 fan_table.temp_src = (uint8_t)tmp;
6533
6534 ret = si_copy_bytes_to_smc(adev,
6535 si_pi->fan_table_start,
6536 (u8 *)(&fan_table),
6537 sizeof(fan_table),
6538 si_pi->sram_end);
6539
6540 if (ret) {
6541 DRM_ERROR("Failed to load fan table to the SMC.");
6542 adev->pm.dpm.fan.ucode_fan_control = false;
6543 }
6544
6545 return 0;
6546}
6547
6548static int si_fan_ctrl_start_smc_fan_control(struct amdgpu_device *adev)
6549{
6550 struct si_power_info *si_pi = si_get_pi(adev);
6551 PPSMC_Result ret;
6552
6553 ret = si_send_msg_to_smc(adev, PPSMC_StartFanControl);
6554 if (ret == PPSMC_Result_OK) {
6555 si_pi->fan_is_controlled_by_smc = true;
6556 return 0;
6557 } else {
6558 return -EINVAL;
6559 }
6560}
6561
6562static int si_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev)
6563{
6564 struct si_power_info *si_pi = si_get_pi(adev);
6565 PPSMC_Result ret;
6566
6567 ret = si_send_msg_to_smc(adev, PPSMC_StopFanControl);
6568
6569 if (ret == PPSMC_Result_OK) {
6570 si_pi->fan_is_controlled_by_smc = false;
6571 return 0;
6572 } else {
6573 return -EINVAL;
6574 }
6575}
6576
6577static int si_dpm_get_fan_speed_percent(struct amdgpu_device *adev,
6578 u32 *speed)
6579{
6580 u32 duty, duty100;
6581 u64 tmp64;
6582
6583 if (adev->pm.no_fan)
6584 return -ENOENT;
6585
6586 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6587 duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;
6588
6589 if (duty100 == 0)
6590 return -EINVAL;
6591
6592 tmp64 = (u64)duty * 100;
6593 do_div(tmp64, duty100);
6594 *speed = (u32)tmp64;
6595
6596 if (*speed > 100)
6597 *speed = 100;
6598
6599 return 0;
6600}
6601
6602static int si_dpm_set_fan_speed_percent(struct amdgpu_device *adev,
6603 u32 speed)
6604{
6605 struct si_power_info *si_pi = si_get_pi(adev);
6606 u32 tmp;
6607 u32 duty, duty100;
6608 u64 tmp64;
6609
6610 if (adev->pm.no_fan)
6611 return -ENOENT;
6612
6613 if (si_pi->fan_is_controlled_by_smc)
6614 return -EINVAL;
6615
6616 if (speed > 100)
6617 return -EINVAL;
6618
6619 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6620
6621 if (duty100 == 0)
6622 return -EINVAL;
6623
6624 tmp64 = (u64)speed * duty100;
6625 do_div(tmp64, 100);
6626 duty = (u32)tmp64;
6627
6628 tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
6629 tmp |= FDO_STATIC_DUTY(duty);
6630 WREG32(CG_FDO_CTRL0, tmp);
6631
6632 return 0;
6633}
6634
6635static void si_dpm_set_fan_control_mode(struct amdgpu_device *adev, u32 mode)
6636{
6637 if (mode) {
6638 /* stop auto-manage */
6639 if (adev->pm.dpm.fan.ucode_fan_control)
6640 si_fan_ctrl_stop_smc_fan_control(adev);
6641 si_fan_ctrl_set_static_mode(adev, mode);
6642 } else {
6643 /* restart auto-manage */
6644 if (adev->pm.dpm.fan.ucode_fan_control)
6645 si_thermal_start_smc_fan_control(adev);
6646 else
6647 si_fan_ctrl_set_default_mode(adev);
6648 }
6649}
6650
6651static u32 si_dpm_get_fan_control_mode(struct amdgpu_device *adev)
6652{
6653 struct si_power_info *si_pi = si_get_pi(adev);
6654 u32 tmp;
6655
6656 if (si_pi->fan_is_controlled_by_smc)
6657 return 0;
6658
6659 tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
6660 return (tmp >> FDO_PWM_MODE_SHIFT);
6661}
6662
6663#if 0
6664static int si_fan_ctrl_get_fan_speed_rpm(struct amdgpu_device *adev,
6665 u32 *speed)
6666{
6667 u32 tach_period;
6668 u32 xclk = amdgpu_asic_get_xclk(adev);
6669
6670 if (adev->pm.no_fan)
6671 return -ENOENT;
6672
6673 if (adev->pm.fan_pulses_per_revolution == 0)
6674 return -ENOENT;
6675
6676 tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
6677 if (tach_period == 0)
6678 return -ENOENT;
6679
6680 *speed = 60 * xclk * 10000 / tach_period;
6681
6682 return 0;
6683}
6684
6685static int si_fan_ctrl_set_fan_speed_rpm(struct amdgpu_device *adev,
6686 u32 speed)
6687{
6688 u32 tach_period, tmp;
6689 u32 xclk = amdgpu_asic_get_xclk(adev);
6690
6691 if (adev->pm.no_fan)
6692 return -ENOENT;
6693
6694 if (adev->pm.fan_pulses_per_revolution == 0)
6695 return -ENOENT;
6696
6697 if ((speed < adev->pm.fan_min_rpm) ||
6698 (speed > adev->pm.fan_max_rpm))
6699 return -EINVAL;
6700
6701 if (adev->pm.dpm.fan.ucode_fan_control)
6702 si_fan_ctrl_stop_smc_fan_control(adev);
6703
6704 tach_period = 60 * xclk * 10000 / (8 * speed);
6705 tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
6706 tmp |= TARGET_PERIOD(tach_period);
6707 WREG32(CG_TACH_CTRL, tmp);
6708
6709 si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC_RPM);
6710
6711 return 0;
6712}
6713#endif
6714
6715static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev)
6716{
6717 struct si_power_info *si_pi = si_get_pi(adev);
6718 u32 tmp;
6719
6720 if (!si_pi->fan_ctrl_is_in_default_mode) {
6721 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6722 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode);
6723 WREG32(CG_FDO_CTRL2, tmp);
6724
6725 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6726 tmp |= TMIN(si_pi->t_min);
6727 WREG32(CG_FDO_CTRL2, tmp);
6728 si_pi->fan_ctrl_is_in_default_mode = true;
6729 }
6730}
6731
6732static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev)
6733{
6734 if (adev->pm.dpm.fan.ucode_fan_control) {
6735 si_fan_ctrl_start_smc_fan_control(adev);
6736 si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC);
6737 }
6738}
6739
6740static void si_thermal_initialize(struct amdgpu_device *adev)
6741{
6742 u32 tmp;
6743
6744 if (adev->pm.fan_pulses_per_revolution) {
6745 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
6746 tmp |= EDGE_PER_REV(adev->pm.fan_pulses_per_revolution -1);
6747 WREG32(CG_TACH_CTRL, tmp);
6748 }
6749
6750 tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
6751 tmp |= TACH_PWM_RESP_RATE(0x28);
6752 WREG32(CG_FDO_CTRL2, tmp);
6753}
6754
6755static int si_thermal_start_thermal_controller(struct amdgpu_device *adev)
6756{
6757 int ret;
6758
6759 si_thermal_initialize(adev);
6760 ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6761 if (ret)
6762 return ret;
6763 ret = si_thermal_enable_alert(adev, true);
6764 if (ret)
6765 return ret;
6766 if (adev->pm.dpm.fan.ucode_fan_control) {
6767 ret = si_halt_smc(adev);
6768 if (ret)
6769 return ret;
6770 ret = si_thermal_setup_fan_table(adev);
6771 if (ret)
6772 return ret;
6773 ret = si_resume_smc(adev);
6774 if (ret)
6775 return ret;
6776 si_thermal_start_smc_fan_control(adev);
6777 }
6778
6779 return 0;
6780}
6781
6782static void si_thermal_stop_thermal_controller(struct amdgpu_device *adev)
6783{
6784 if (!adev->pm.no_fan) {
6785 si_fan_ctrl_set_default_mode(adev);
6786 si_fan_ctrl_stop_smc_fan_control(adev);
6787 }
6788}
6789
6790static int si_dpm_enable(struct amdgpu_device *adev)
6791{
6792 struct rv7xx_power_info *pi = rv770_get_pi(adev);
6793 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6794 struct si_power_info *si_pi = si_get_pi(adev);
6795 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
6796 int ret;
6797
6798 if (si_is_smc_running(adev))
6799 return -EINVAL;
6800 if (pi->voltage_control || si_pi->voltage_control_svi2)
6801 si_enable_voltage_control(adev, true);
6802 if (pi->mvdd_control)
6803 si_get_mvdd_configuration(adev);
6804 if (pi->voltage_control || si_pi->voltage_control_svi2) {
6805 ret = si_construct_voltage_tables(adev);
6806 if (ret) {
6807 DRM_ERROR("si_construct_voltage_tables failed\n");
6808 return ret;
6809 }
6810 }
6811 if (eg_pi->dynamic_ac_timing) {
6812 ret = si_initialize_mc_reg_table(adev);
6813 if (ret)
6814 eg_pi->dynamic_ac_timing = false;
6815 }
6816 if (pi->dynamic_ss)
6817 si_enable_spread_spectrum(adev, true);
6818 if (pi->thermal_protection)
6819 si_enable_thermal_protection(adev, true);
6820 si_setup_bsp(adev);
6821 si_program_git(adev);
6822 si_program_tp(adev);
6823 si_program_tpp(adev);
6824 si_program_sstp(adev);
6825 si_enable_display_gap(adev);
6826 si_program_vc(adev);
6827 ret = si_upload_firmware(adev);
6828 if (ret) {
6829 DRM_ERROR("si_upload_firmware failed\n");
6830 return ret;
6831 }
6832 ret = si_process_firmware_header(adev);
6833 if (ret) {
6834 DRM_ERROR("si_process_firmware_header failed\n");
6835 return ret;
6836 }
6837 ret = si_initial_switch_from_arb_f0_to_f1(adev);
6838 if (ret) {
6839 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
6840 return ret;
6841 }
6842 ret = si_init_smc_table(adev);
6843 if (ret) {
6844 DRM_ERROR("si_init_smc_table failed\n");
6845 return ret;
6846 }
6847 ret = si_init_smc_spll_table(adev);
6848 if (ret) {
6849 DRM_ERROR("si_init_smc_spll_table failed\n");
6850 return ret;
6851 }
6852 ret = si_init_arb_table_index(adev);
6853 if (ret) {
6854 DRM_ERROR("si_init_arb_table_index failed\n");
6855 return ret;
6856 }
6857 if (eg_pi->dynamic_ac_timing) {
6858 ret = si_populate_mc_reg_table(adev, boot_ps);
6859 if (ret) {
6860 DRM_ERROR("si_populate_mc_reg_table failed\n");
6861 return ret;
6862 }
6863 }
6864 ret = si_initialize_smc_cac_tables(adev);
6865 if (ret) {
6866 DRM_ERROR("si_initialize_smc_cac_tables failed\n");
6867 return ret;
6868 }
6869 ret = si_initialize_hardware_cac_manager(adev);
6870 if (ret) {
6871 DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
6872 return ret;
6873 }
6874 ret = si_initialize_smc_dte_tables(adev);
6875 if (ret) {
6876 DRM_ERROR("si_initialize_smc_dte_tables failed\n");
6877 return ret;
6878 }
6879 ret = si_populate_smc_tdp_limits(adev, boot_ps);
6880 if (ret) {
6881 DRM_ERROR("si_populate_smc_tdp_limits failed\n");
6882 return ret;
6883 }
6884 ret = si_populate_smc_tdp_limits_2(adev, boot_ps);
6885 if (ret) {
6886 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
6887 return ret;
6888 }
6889 si_program_response_times(adev);
6890 si_program_ds_registers(adev);
6891 si_dpm_start_smc(adev);
6892 ret = si_notify_smc_display_change(adev, false);
6893 if (ret) {
6894 DRM_ERROR("si_notify_smc_display_change failed\n");
6895 return ret;
6896 }
6897 si_enable_sclk_control(adev, true);
6898 si_start_dpm(adev);
6899
6900 si_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
841686df 6901 si_thermal_start_thermal_controller(adev);
841686df
MB		 6902 ni_update_current_ps(adev, boot_ps);
6903
6904 return 0;
6905}
6906
6907static int si_set_temperature_range(struct amdgpu_device *adev)
6908{
6909 int ret;
6910
6911 ret = si_thermal_enable_alert(adev, false);
6912 if (ret)
6913 return ret;
6914 ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6915 if (ret)
6916 return ret;
6917 ret = si_thermal_enable_alert(adev, true);
6918 if (ret)
6919 return ret;
6920
6921 return ret;
6922}
6923
6924static void si_dpm_disable(struct amdgpu_device *adev)
6925{
6926 struct rv7xx_power_info *pi = rv770_get_pi(adev);
6927 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
6928
6929 if (!si_is_smc_running(adev))
6930 return;
6931 si_thermal_stop_thermal_controller(adev);
6932 si_disable_ulv(adev);
6933 si_clear_vc(adev);
6934 if (pi->thermal_protection)
6935 si_enable_thermal_protection(adev, false);
6936 si_enable_power_containment(adev, boot_ps, false);
6937 si_enable_smc_cac(adev, boot_ps, false);
6938 si_enable_spread_spectrum(adev, false);
6939 si_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
6940 si_stop_dpm(adev);
6941 si_reset_to_default(adev);
6942 si_dpm_stop_smc(adev);
6943 si_force_switch_to_arb_f0(adev);
6944
6945 ni_update_current_ps(adev, boot_ps);
6946}
6947
6948static int si_dpm_pre_set_power_state(struct amdgpu_device *adev)
6949{
6950 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6951 struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
6952 struct amdgpu_ps *new_ps = &requested_ps;
6953
6954 ni_update_requested_ps(adev, new_ps);
841686df
MB		 6955 si_apply_state_adjust_rules(adev, &eg_pi->requested_rps);
6956
6957 return 0;
6958}
6959
6960static int si_power_control_set_level(struct amdgpu_device *adev)
6961{
6962 struct amdgpu_ps *new_ps = adev->pm.dpm.requested_ps;
6963 int ret;
6964
6965 ret = si_restrict_performance_levels_before_switch(adev);
6966 if (ret)
6967 return ret;
6968 ret = si_halt_smc(adev);
6969 if (ret)
6970 return ret;
6971 ret = si_populate_smc_tdp_limits(adev, new_ps);
6972 if (ret)
6973 return ret;
6974 ret = si_populate_smc_tdp_limits_2(adev, new_ps);
6975 if (ret)
6976 return ret;
6977 ret = si_resume_smc(adev);
6978 if (ret)
6979 return ret;
6980 ret = si_set_sw_state(adev);
6981 if (ret)
6982 return ret;
6983 return 0;
6984}
6985
6986static int si_dpm_set_power_state(struct amdgpu_device *adev)
6987{
6988 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6989 struct amdgpu_ps *new_ps = &eg_pi->requested_rps;
6990 struct amdgpu_ps *old_ps = &eg_pi->current_rps;
6991 int ret;
6992
6993 ret = si_disable_ulv(adev);
6994 if (ret) {
6995 DRM_ERROR("si_disable_ulv failed\n");
6996 return ret;
6997 }
6998 ret = si_restrict_performance_levels_before_switch(adev);
6999 if (ret) {
7000 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
7001 return ret;
7002 }
7003 if (eg_pi->pcie_performance_request)
7004 si_request_link_speed_change_before_state_change(adev, new_ps, old_ps);
7005 ni_set_uvd_clock_before_set_eng_clock(adev, new_ps, old_ps);
7006 ret = si_enable_power_containment(adev, new_ps, false);
7007 if (ret) {
7008 DRM_ERROR("si_enable_power_containment failed\n");
7009 return ret;
7010 }
7011 ret = si_enable_smc_cac(adev, new_ps, false);
7012 if (ret) {
7013 DRM_ERROR("si_enable_smc_cac failed\n");
7014 return ret;
7015 }
7016 ret = si_halt_smc(adev);
7017 if (ret) {
7018 DRM_ERROR("si_halt_smc failed\n");
7019 return ret;
7020 }
7021 ret = si_upload_sw_state(adev, new_ps);
7022 if (ret) {
7023 DRM_ERROR("si_upload_sw_state failed\n");
7024 return ret;
7025 }
7026 ret = si_upload_smc_data(adev);
7027 if (ret) {
7028 DRM_ERROR("si_upload_smc_data failed\n");
7029 return ret;
7030 }
7031 ret = si_upload_ulv_state(adev);
7032 if (ret) {
7033 DRM_ERROR("si_upload_ulv_state failed\n");
7034 return ret;
7035 }
7036 if (eg_pi->dynamic_ac_timing) {
7037 ret = si_upload_mc_reg_table(adev, new_ps);
7038 if (ret) {
7039 DRM_ERROR("si_upload_mc_reg_table failed\n");
7040 return ret;
7041 }
7042 }
7043 ret = si_program_memory_timing_parameters(adev, new_ps);
7044 if (ret) {
7045 DRM_ERROR("si_program_memory_timing_parameters failed\n");
7046 return ret;
7047 }
7048 si_set_pcie_lane_width_in_smc(adev, new_ps, old_ps);
7049
7050 ret = si_resume_smc(adev);
7051 if (ret) {
7052 DRM_ERROR("si_resume_smc failed\n");
7053 return ret;
7054 }
7055 ret = si_set_sw_state(adev);
7056 if (ret) {
7057 DRM_ERROR("si_set_sw_state failed\n");
7058 return ret;
7059 }
7060 ni_set_uvd_clock_after_set_eng_clock(adev, new_ps, old_ps);
7061 if (eg_pi->pcie_performance_request)
7062 si_notify_link_speed_change_after_state_change(adev, new_ps, old_ps);
7063 ret = si_set_power_state_conditionally_enable_ulv(adev, new_ps);
7064 if (ret) {
7065 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
7066 return ret;
7067 }
7068 ret = si_enable_smc_cac(adev, new_ps, true);
7069 if (ret) {
7070 DRM_ERROR("si_enable_smc_cac failed\n");
7071 return ret;
7072 }
7073 ret = si_enable_power_containment(adev, new_ps, true);
7074 if (ret) {
7075 DRM_ERROR("si_enable_power_containment failed\n");
7076 return ret;
7077 }
7078
7079 ret = si_power_control_set_level(adev);
7080 if (ret) {
7081 DRM_ERROR("si_power_control_set_level failed\n");
7082 return ret;
7083 }
7084
7085 return 0;
7086}
7087
7088static void si_dpm_post_set_power_state(struct amdgpu_device *adev)
7089{
7090 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7091 struct amdgpu_ps *new_ps = &eg_pi->requested_rps;
7092
7093 ni_update_current_ps(adev, new_ps);
7094}
7095
7096#if 0
7097void si_dpm_reset_asic(struct amdgpu_device *adev)
7098{
7099 si_restrict_performance_levels_before_switch(adev);
7100 si_disable_ulv(adev);
7101 si_set_boot_state(adev);
7102}
7103#endif
7104
7105static void si_dpm_display_configuration_changed(struct amdgpu_device *adev)
7106{
7107 si_program_display_gap(adev);
7108}
7109
7110
7111static void si_parse_pplib_non_clock_info(struct amdgpu_device *adev,
7112 struct amdgpu_ps *rps,
7113 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
7114 u8 table_rev)
7115{
7116 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
7117 rps->class = le16_to_cpu(non_clock_info->usClassification);
7118 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
7119
7120 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
7121 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
7122 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
7123 } else if (r600_is_uvd_state(rps->class, rps->class2)) {
7124 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
7125 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
7126 } else {
7127 rps->vclk = 0;
7128 rps->dclk = 0;
7129 }
7130
7131 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
7132 adev->pm.dpm.boot_ps = rps;
7133 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
7134 adev->pm.dpm.uvd_ps = rps;
7135}
7136
7137static void si_parse_pplib_clock_info(struct amdgpu_device *adev,
7138 struct amdgpu_ps *rps, int index,
7139 union pplib_clock_info *clock_info)
7140{
7141 struct rv7xx_power_info *pi = rv770_get_pi(adev);
7142 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7143 struct si_power_info *si_pi = si_get_pi(adev);
7144 struct si_ps *ps = si_get_ps(rps);
7145 u16 leakage_voltage;
7146 struct rv7xx_pl *pl = &ps->performance_levels[index];
7147 int ret;
7148
7149 ps->performance_level_count = index + 1;
7150
7151 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
7152 pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
7153 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
7154 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
7155
7156 pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
7157 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
7158 pl->flags = le32_to_cpu(clock_info->si.ulFlags);
7159 pl->pcie_gen = r600_get_pcie_gen_support(adev,
7160 si_pi->sys_pcie_mask,
7161 si_pi->boot_pcie_gen,
7162 clock_info->si.ucPCIEGen);
7163
7164 /* patch up vddc if necessary */
7165 ret = si_get_leakage_voltage_from_leakage_index(adev, pl->vddc,
7166 &leakage_voltage);
7167 if (ret == 0)
7168 pl->vddc = leakage_voltage;
7169
7170 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
7171 pi->acpi_vddc = pl->vddc;
7172 eg_pi->acpi_vddci = pl->vddci;
7173 si_pi->acpi_pcie_gen = pl->pcie_gen;
7174 }
7175
7176 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
7177 index == 0) {
7178 /* XXX disable for A0 tahiti */
7179 si_pi->ulv.supported = false;
7180 si_pi->ulv.pl = *pl;
7181 si_pi->ulv.one_pcie_lane_in_ulv = false;
7182 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
7183 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
7184 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;
7185 }
7186
7187 if (pi->min_vddc_in_table > pl->vddc)
7188 pi->min_vddc_in_table = pl->vddc;
7189
7190 if (pi->max_vddc_in_table < pl->vddc)
7191 pi->max_vddc_in_table = pl->vddc;
7192
7193 /* patch up boot state */
7194 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
7195 u16 vddc, vddci, mvdd;
7196 amdgpu_atombios_get_default_voltages(adev, &vddc, &vddci, &mvdd);
7197 pl->mclk = adev->clock.default_mclk;
7198 pl->sclk = adev->clock.default_sclk;
7199 pl->vddc = vddc;
7200 pl->vddci = vddci;
7201 si_pi->mvdd_bootup_value = mvdd;
7202 }
7203
7204 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
7205 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
7206 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
7207 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
7208 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
7209 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
7210 }
7211}
7212
7213union pplib_power_state {
77d318a6
TSD		 7214 struct _ATOM_PPLIB_STATE v1;
7215 struct _ATOM_PPLIB_STATE_V2 v2;
841686df
MB		 7216};
7217
7218static int si_parse_power_table(struct amdgpu_device *adev)
7219{
7220 struct amdgpu_mode_info *mode_info = &adev->mode_info;
7221 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
7222 union pplib_power_state *power_state;
7223 int i, j, k, non_clock_array_index, clock_array_index;
7224 union pplib_clock_info *clock_info;
7225 struct _StateArray *state_array;
7226 struct _ClockInfoArray *clock_info_array;
7227 struct _NonClockInfoArray *non_clock_info_array;
7228 union power_info *power_info;
7229 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
77d318a6 7230 u16 data_offset;
841686df
MB		 7231 u8 frev, crev;
7232 u8 *power_state_offset;
7233 struct si_ps *ps;
7234
7235 if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
7236 &frev, &crev, &data_offset))
7237 return -EINVAL;
7238 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
7239
7240 amdgpu_add_thermal_controller(adev);
7241
7242 state_array = (struct _StateArray *)
7243 (mode_info->atom_context->bios + data_offset +
7244 le16_to_cpu(power_info->pplib.usStateArrayOffset));
7245 clock_info_array = (struct _ClockInfoArray *)
7246 (mode_info->atom_context->bios + data_offset +
7247 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
7248 non_clock_info_array = (struct _NonClockInfoArray *)
7249 (mode_info->atom_context->bios + data_offset +
7250 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
7251
7252 adev->pm.dpm.ps = kzalloc(sizeof(struct amdgpu_ps) *
7253 state_array->ucNumEntries, GFP_KERNEL);
7254 if (!adev->pm.dpm.ps)
7255 return -ENOMEM;
7256 power_state_offset = (u8 *)state_array->states;
7257 for (i = 0; i < state_array->ucNumEntries; i++) {
7258 u8 *idx;
7259 power_state = (union pplib_power_state *)power_state_offset;
7260 non_clock_array_index = power_state->v2.nonClockInfoIndex;
7261 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
7262 &non_clock_info_array->nonClockInfo[non_clock_array_index];
7263 ps = kzalloc(sizeof(struct si_ps), GFP_KERNEL);
7264 if (ps == NULL) {
7265 kfree(adev->pm.dpm.ps);
7266 return -ENOMEM;
7267 }
7268 adev->pm.dpm.ps[i].ps_priv = ps;
7269 si_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i],
7270 non_clock_info,
7271 non_clock_info_array->ucEntrySize);
7272 k = 0;
7273 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
7274 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
7275 clock_array_index = idx[j];
7276 if (clock_array_index >= clock_info_array->ucNumEntries)
7277 continue;
7278 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
7279 break;
7280 clock_info = (union pplib_clock_info *)
7281 ((u8 *)&clock_info_array->clockInfo[0] +
7282 (clock_array_index * clock_info_array->ucEntrySize));
7283 si_parse_pplib_clock_info(adev,
7284 &adev->pm.dpm.ps[i], k,
7285 clock_info);
7286 k++;
7287 }
7288 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
7289 }
7290 adev->pm.dpm.num_ps = state_array->ucNumEntries;
7291
7292 /* fill in the vce power states */
7293 for (i = 0; i < AMDGPU_MAX_VCE_LEVELS; i++) {
7294 u32 sclk, mclk;
7295 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx;
7296 clock_info = (union pplib_clock_info *)
7297 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
7298 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
7299 sclk |= clock_info->si.ucEngineClockHigh << 16;
7300 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
7301 mclk |= clock_info->si.ucMemoryClockHigh << 16;
7302 adev->pm.dpm.vce_states[i].sclk = sclk;
7303 adev->pm.dpm.vce_states[i].mclk = mclk;
7304 }
7305
7306 return 0;
7307}
7308
7309static int si_dpm_init(struct amdgpu_device *adev)
7310{
7311 struct rv7xx_power_info *pi;
7312 struct evergreen_power_info *eg_pi;
7313 struct ni_power_info *ni_pi;
7314 struct si_power_info *si_pi;
7315 struct atom_clock_dividers dividers;
7316 int ret;
7317 u32 mask;
7318
7319 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
7320 if (si_pi == NULL)
7321 return -ENOMEM;
7322 adev->pm.dpm.priv = si_pi;
7323 ni_pi = &si_pi->ni;
7324 eg_pi = &ni_pi->eg;
7325 pi = &eg_pi->rv7xx;
7326
7327 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
7328 if (ret)
7329 si_pi->sys_pcie_mask = 0;
7330 else
7331 si_pi->sys_pcie_mask = mask;
7332 si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
7333 si_pi->boot_pcie_gen = si_get_current_pcie_speed(adev);
7334
7335 si_set_max_cu_value(adev);
7336
7337 rv770_get_max_vddc(adev);
7338 si_get_leakage_vddc(adev);
7339 si_patch_dependency_tables_based_on_leakage(adev);
7340
7341 pi->acpi_vddc = 0;
7342 eg_pi->acpi_vddci = 0;
7343 pi->min_vddc_in_table = 0;
7344 pi->max_vddc_in_table = 0;
7345
7346 ret = amdgpu_get_platform_caps(adev);
7347 if (ret)
7348 return ret;
7349
7350 ret = amdgpu_parse_extended_power_table(adev);
7351 if (ret)
7352 return ret;
7353
7354 ret = si_parse_power_table(adev);
7355 if (ret)
7356 return ret;
7357
7358 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
7359 kzalloc(4 * sizeof(struct amdgpu_clock_voltage_dependency_entry), GFP_KERNEL);
7360 if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
7361 amdgpu_free_extended_power_table(adev);
7362 return -ENOMEM;
7363 }
7364 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
7365 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
7366 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
7367 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
7368 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
7369 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
7370 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
7371 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
7372 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
7373
7374 if (adev->pm.dpm.voltage_response_time == 0)
7375 adev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
7376 if (adev->pm.dpm.backbias_response_time == 0)
7377 adev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
7378
7379 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
7380 0, false, &dividers);
7381 if (ret)
7382 pi->ref_div = dividers.ref_div + 1;
7383 else
7384 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
7385
7386 eg_pi->smu_uvd_hs = false;
7387
7388 pi->mclk_strobe_mode_threshold = 40000;
7389 if (si_is_special_1gb_platform(adev))
7390 pi->mclk_stutter_mode_threshold = 0;
7391 else
7392 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;
7393 pi->mclk_edc_enable_threshold = 40000;
7394 eg_pi->mclk_edc_wr_enable_threshold = 40000;
7395
7396 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
7397
7398 pi->voltage_control =
7399 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7400 VOLTAGE_OBJ_GPIO_LUT);
7401 if (!pi->voltage_control) {
7402 si_pi->voltage_control_svi2 =
7403 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7404 VOLTAGE_OBJ_SVID2);
7405 if (si_pi->voltage_control_svi2)
7406 amdgpu_atombios_get_svi2_info(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7407 &si_pi->svd_gpio_id, &si_pi->svc_gpio_id);
7408 }
7409
7410 pi->mvdd_control =
7411 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_MVDDC,
7412 VOLTAGE_OBJ_GPIO_LUT);
7413
7414 eg_pi->vddci_control =
7415 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7416 VOLTAGE_OBJ_GPIO_LUT);
7417 if (!eg_pi->vddci_control)
7418 si_pi->vddci_control_svi2 =
7419 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7420 VOLTAGE_OBJ_SVID2);
7421
7422 si_pi->vddc_phase_shed_control =
7423 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7424 VOLTAGE_OBJ_PHASE_LUT);
7425
7426 rv770_get_engine_memory_ss(adev);
7427
7428 pi->asi = RV770_ASI_DFLT;
7429 pi->pasi = CYPRESS_HASI_DFLT;
7430 pi->vrc = SISLANDS_VRC_DFLT;
7431
7432 pi->gfx_clock_gating = true;
7433
7434 eg_pi->sclk_deep_sleep = true;
7435 si_pi->sclk_deep_sleep_above_low = false;
7436
7437 if (adev->pm.int_thermal_type != THERMAL_TYPE_NONE)
7438 pi->thermal_protection = true;
7439 else
7440 pi->thermal_protection = false;
7441
7442 eg_pi->dynamic_ac_timing = true;
7443
7444 eg_pi->light_sleep = true;
7445#if defined(CONFIG_ACPI)
7446 eg_pi->pcie_performance_request =
7447 amdgpu_acpi_is_pcie_performance_request_supported(adev);
7448#else
7449 eg_pi->pcie_performance_request = false;
7450#endif
7451
7452 si_pi->sram_end = SMC_RAM_END;
7453
7454 adev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
7455 adev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
7456 adev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
7457 adev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
7458 adev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
7459 adev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
7460 adev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
7461
7462 si_initialize_powertune_defaults(adev);
7463
7464 /* make sure dc limits are valid */
7465 if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
7466 (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
7467 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
7468 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
7469
7470 si_pi->fan_ctrl_is_in_default_mode = true;
7471
7472 return 0;
7473}
7474
7475static void si_dpm_fini(struct amdgpu_device *adev)
7476{
7477 int i;
7478
9623e4bf
TSD		 7479 if (adev->pm.dpm.ps)
7480 for (i = 0; i < adev->pm.dpm.num_ps; i++)
7481 kfree(adev->pm.dpm.ps[i].ps_priv);
841686df
MB		 7482 kfree(adev->pm.dpm.ps);
7483 kfree(adev->pm.dpm.priv);
7484 kfree(adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
7485 amdgpu_free_extended_power_table(adev);
7486}
7487
7488static void si_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
7489 struct seq_file *m)
7490{
7491 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7492 struct amdgpu_ps *rps = &eg_pi->current_rps;
7493 struct si_ps *ps = si_get_ps(rps);
7494 struct rv7xx_pl *pl;
7495 u32 current_index =
7496 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7497 CURRENT_STATE_INDEX_SHIFT;
7498
7499 if (current_index >= ps->performance_level_count) {
7500 seq_printf(m, "invalid dpm profile %d\n", current_index);
7501 } else {
7502 pl = &ps->performance_levels[current_index];
7503 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7504 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7505 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7506 }
7507}
7508
7509static int si_dpm_set_interrupt_state(struct amdgpu_device *adev,
7510 struct amdgpu_irq_src *source,
7511 unsigned type,
7512 enum amdgpu_interrupt_state state)
7513{
7514 u32 cg_thermal_int;
7515
7516 switch (type) {
7517 case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH:
7518 switch (state) {
7519 case AMDGPU_IRQ_STATE_DISABLE:
7520 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7521 cg_thermal_int |= THERM_INT_MASK_HIGH;
7522 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7523 break;
7524 case AMDGPU_IRQ_STATE_ENABLE:
7525 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7526 cg_thermal_int &= ~THERM_INT_MASK_HIGH;
7527 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7528 break;
7529 default:
7530 break;
7531 }
7532 break;
7533
7534 case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW:
7535 switch (state) {
7536 case AMDGPU_IRQ_STATE_DISABLE:
7537 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7538 cg_thermal_int |= THERM_INT_MASK_LOW;
7539 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7540 break;
7541 case AMDGPU_IRQ_STATE_ENABLE:
7542 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7543 cg_thermal_int &= ~THERM_INT_MASK_LOW;
7544 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7545 break;
7546 default:
7547 break;
7548 }
7549 break;
7550
7551 default:
7552 break;
7553 }
7554 return 0;
7555}
7556
7557static int si_dpm_process_interrupt(struct amdgpu_device *adev,
7558 struct amdgpu_irq_src *source,
7559 struct amdgpu_iv_entry *entry)
7560{
7561 bool queue_thermal = false;
7562
7563 if (entry == NULL)
7564 return -EINVAL;
7565
7566 switch (entry->src_id) {
7567 case 230: /* thermal low to high */
7568 DRM_DEBUG("IH: thermal low to high\n");
7569 adev->pm.dpm.thermal.high_to_low = false;
7570 queue_thermal = true;
7571 break;
7572 case 231: /* thermal high to low */
7573 DRM_DEBUG("IH: thermal high to low\n");
7574 adev->pm.dpm.thermal.high_to_low = true;
7575 queue_thermal = true;
7576 break;
7577 default:
7578 break;
7579 }
7580
7581 if (queue_thermal)
7582 schedule_work(&adev->pm.dpm.thermal.work);
7583
7584 return 0;
7585}
7586
7587static int si_dpm_late_init(void *handle)
7588{
7589 int ret;
7590 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7591
7592 if (!amdgpu_dpm)
7593 return 0;
7594
7595 /* init the sysfs and debugfs files late */
7596 ret = amdgpu_pm_sysfs_init(adev);
7597 if (ret)
7598 return ret;
7599
7600 ret = si_set_temperature_range(adev);
7601 if (ret)
7602 return ret;
7603#if 0 //TODO ?
7604 si_dpm_powergate_uvd(adev, true);
7605#endif
7606 return 0;
7607}
7608
7609/**
7610 * si_dpm_init_microcode - load ucode images from disk
7611 *
7612 * @adev: amdgpu_device pointer
7613 *
7614 * Use the firmware interface to load the ucode images into
7615 * the driver (not loaded into hw).
7616 * Returns 0 on success, error on failure.
7617 */
7618static int si_dpm_init_microcode(struct amdgpu_device *adev)
7619{
7620 const char *chip_name;
7621 char fw_name[30];
7622 int err;
7623
7624 DRM_DEBUG("\n");
7625 switch (adev->asic_type) {
7626 case CHIP_TAHITI:
7627 chip_name = "tahiti";
7628 break;
7629 case CHIP_PITCAIRN:
a8c65c13
AD		 7630 if ((adev->pdev->revision == 0x81) ||
7631 (adev->pdev->device == 0x6810) ||
7632 (adev->pdev->device == 0x6811) ||
7633 (adev->pdev->device == 0x6816) ||
7634 (adev->pdev->device == 0x6817) ||
7635 (adev->pdev->device == 0x6806))
7636 chip_name = "pitcairn_k";
7637 else
7638 chip_name = "pitcairn";
841686df
MB		 7639 break;
7640 case CHIP_VERDE:
a8c65c13
AD		 7641 if ((adev->pdev->revision == 0x81) ||
7642 (adev->pdev->revision == 0x83) ||
7643 (adev->pdev->revision == 0x87) ||
7644 (adev->pdev->device == 0x6820) ||
7645 (adev->pdev->device == 0x6821) ||
7646 (adev->pdev->device == 0x6822) ||
7647 (adev->pdev->device == 0x6823) ||
7648 (adev->pdev->device == 0x682A) ||
7649 (adev->pdev->device == 0x682B))
7650 chip_name = "verde_k";
7651 else
7652 chip_name = "verde";
841686df
MB		 7653 break;
7654 case CHIP_OLAND:
a8c65c13
AD		 7655 if ((adev->pdev->revision == 0xC7) ||
7656 (adev->pdev->revision == 0x80) ||
7657 (adev->pdev->revision == 0x81) ||
7658 (adev->pdev->revision == 0x83) ||
7659 (adev->pdev->device == 0x6604) ||
7660 (adev->pdev->device == 0x6605))
7661 chip_name = "oland_k";
7662 else
7663 chip_name = "oland";
841686df
MB		 7664 break;
7665 case CHIP_HAINAN:
a8c65c13
AD		 7666 if ((adev->pdev->revision == 0x81) ||
7667 (adev->pdev->revision == 0x83) ||
7668 (adev->pdev->revision == 0xC3) ||
7669 (adev->pdev->device == 0x6664) ||
7670 (adev->pdev->device == 0x6665) ||
7671 (adev->pdev->device == 0x6667))
7672 chip_name = "hainan_k";
7673 else
7674 chip_name = "hainan";
841686df
MB		 7675 break;
7676 default: BUG();
7677 }
7678
7679 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
7680 err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
7681 if (err)
7682 goto out;
7683 err = amdgpu_ucode_validate(adev->pm.fw);
7684
7685out:
7686 if (err) {
84b77336
HR		 7687 DRM_ERROR("si_smc: Failed to load firmware. err = %d\"%s\"\n",
7688 err, fw_name);
841686df
MB		 7689 release_firmware(adev->pm.fw);
7690 adev->pm.fw = NULL;
7691 }
7692 return err;
7693
7694}
7695
7696static int si_dpm_sw_init(void *handle)
7697{
7698 int ret;
7699 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7700
7701 ret = amdgpu_irq_add_id(adev, 230, &adev->pm.dpm.thermal.irq);
7702 if (ret)
7703 return ret;
7704
7705 ret = amdgpu_irq_add_id(adev, 231, &adev->pm.dpm.thermal.irq);
7706 if (ret)
7707 return ret;
7708
7709 /* default to balanced state */
7710 adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
7711 adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
7712 adev->pm.dpm.forced_level = AMDGPU_DPM_FORCED_LEVEL_AUTO;
7713 adev->pm.default_sclk = adev->clock.default_sclk;
7714 adev->pm.default_mclk = adev->clock.default_mclk;
7715 adev->pm.current_sclk = adev->clock.default_sclk;
7716 adev->pm.current_mclk = adev->clock.default_mclk;
7717 adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
7718
7719 if (amdgpu_dpm == 0)
7720 return 0;
7721
7722 ret = si_dpm_init_microcode(adev);
7723 if (ret)
7724 return ret;
7725
7726 INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler);
7727 mutex_lock(&adev->pm.mutex);
7728 ret = si_dpm_init(adev);
7729 if (ret)
7730 goto dpm_failed;
7731 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
7732 if (amdgpu_dpm == 1)
7733 amdgpu_pm_print_power_states(adev);
7734 mutex_unlock(&adev->pm.mutex);
7735 DRM_INFO("amdgpu: dpm initialized\n");
7736
7737 return 0;
7738
7739dpm_failed:
7740 si_dpm_fini(adev);
7741 mutex_unlock(&adev->pm.mutex);
7742 DRM_ERROR("amdgpu: dpm initialization failed\n");
7743 return ret;
7744}
7745
7746static int si_dpm_sw_fini(void *handle)
7747{
7748 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7749
7750 mutex_lock(&adev->pm.mutex);
7751 amdgpu_pm_sysfs_fini(adev);
7752 si_dpm_fini(adev);
7753 mutex_unlock(&adev->pm.mutex);
7754
7755 return 0;
7756}
7757
7758static int si_dpm_hw_init(void *handle)
7759{
7760 int ret;
7761
7762 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7763
7764 if (!amdgpu_dpm)
7765 return 0;
7766
7767 mutex_lock(&adev->pm.mutex);
7768 si_dpm_setup_asic(adev);
7769 ret = si_dpm_enable(adev);
7770 if (ret)
7771 adev->pm.dpm_enabled = false;
7772 else
7773 adev->pm.dpm_enabled = true;
7774 mutex_unlock(&adev->pm.mutex);
7775
7776 return ret;
7777}
7778
7779static int si_dpm_hw_fini(void *handle)
7780{
7781 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7782
7783 if (adev->pm.dpm_enabled) {
7784 mutex_lock(&adev->pm.mutex);
7785 si_dpm_disable(adev);
7786 mutex_unlock(&adev->pm.mutex);
7787 }
7788
7789 return 0;
7790}
7791
7792static int si_dpm_suspend(void *handle)
7793{
7794 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7795
7796 if (adev->pm.dpm_enabled) {
7797 mutex_lock(&adev->pm.mutex);
7798 /* disable dpm */
7799 si_dpm_disable(adev);
7800 /* reset the power state */
7801 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
7802 mutex_unlock(&adev->pm.mutex);
7803 }
7804 return 0;
7805}
7806
7807static int si_dpm_resume(void *handle)
7808{
7809 int ret;
7810 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7811
7812 if (adev->pm.dpm_enabled) {
7813 /* asic init will reset to the boot state */
7814 mutex_lock(&adev->pm.mutex);
7815 si_dpm_setup_asic(adev);
7816 ret = si_dpm_enable(adev);
7817 if (ret)
7818 adev->pm.dpm_enabled = false;
7819 else
7820 adev->pm.dpm_enabled = true;
7821 mutex_unlock(&adev->pm.mutex);
7822 if (adev->pm.dpm_enabled)
7823 amdgpu_pm_compute_clocks(adev);
7824 }
7825 return 0;
7826}
7827
7828static bool si_dpm_is_idle(void *handle)
7829{
7830 /* XXX */
7831 return true;
7832}
7833
7834static int si_dpm_wait_for_idle(void *handle)
7835{
7836 /* XXX */
7837 return 0;
7838}
7839
7840static int si_dpm_soft_reset(void *handle)
7841{
7842 return 0;
7843}
7844
7845static int si_dpm_set_clockgating_state(void *handle,
7846 enum amd_clockgating_state state)
7847{
7848 return 0;
7849}
7850
7851static int si_dpm_set_powergating_state(void *handle,
7852 enum amd_powergating_state state)
7853{
7854 return 0;
7855}
7856
7857/* get temperature in millidegrees */
7858static int si_dpm_get_temp(struct amdgpu_device *adev)
7859{
7860 u32 temp;
7861 int actual_temp = 0;
7862
7863 temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
7864 CTF_TEMP_SHIFT;
7865
7866 if (temp & 0x200)
7867 actual_temp = 255;
7868 else
7869 actual_temp = temp & 0x1ff;
7870
7871 actual_temp = (actual_temp * 1000);
7872
7873 return actual_temp;
7874}
7875
7876static u32 si_dpm_get_sclk(struct amdgpu_device *adev, bool low)
7877{
77d318a6
TSD		 7878 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7879 struct si_ps *requested_state = si_get_ps(&eg_pi->requested_rps);
841686df 7880
77d318a6
TSD		 7881 if (low)
7882 return requested_state->performance_levels[0].sclk;
7883 else
7884 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
841686df
MB		 7885}
7886
7887static u32 si_dpm_get_mclk(struct amdgpu_device *adev, bool low)
7888{
77d318a6
TSD		 7889 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7890 struct si_ps *requested_state = si_get_ps(&eg_pi->requested_rps);
841686df 7891
77d318a6
TSD		 7892 if (low)
7893 return requested_state->performance_levels[0].mclk;
7894 else
7895 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;
841686df
MB		 7896}
7897
7898static void si_dpm_print_power_state(struct amdgpu_device *adev,
77d318a6
TSD		 7899 struct amdgpu_ps *rps)
7900{
7901 struct si_ps *ps = si_get_ps(rps);
7902 struct rv7xx_pl *pl;
7903 int i;
7904
7905 amdgpu_dpm_print_class_info(rps->class, rps->class2);
7906 amdgpu_dpm_print_cap_info(rps->caps);
7907 DRM_INFO("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7908 for (i = 0; i < ps->performance_level_count; i++) {
7909 pl = &ps->performance_levels[i];
7910 if (adev->asic_type >= CHIP_TAHITI)
7911 DRM_INFO("\t\tpower level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
84b77336 7912 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
77d318a6
TSD		 7913 else
7914 DRM_INFO("\t\tpower level %d sclk: %u mclk: %u vddc: %u vddci: %u\n",
84b77336 7915 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci);
77d318a6
TSD		 7916 }
7917 amdgpu_dpm_print_ps_status(adev, rps);
841686df
MB		 7918}
7919
7920static int si_dpm_early_init(void *handle)
7921{
7922
7923 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7924
7925 si_dpm_set_dpm_funcs(adev);
7926 si_dpm_set_irq_funcs(adev);
7927 return 0;
7928}
7929
7930
7931const struct amd_ip_funcs si_dpm_ip_funcs = {
7932 .name = "si_dpm",
7933 .early_init = si_dpm_early_init,
7934 .late_init = si_dpm_late_init,
7935 .sw_init = si_dpm_sw_init,
7936 .sw_fini = si_dpm_sw_fini,
7937 .hw_init = si_dpm_hw_init,
7938 .hw_fini = si_dpm_hw_fini,
7939 .suspend = si_dpm_suspend,
7940 .resume = si_dpm_resume,
7941 .is_idle = si_dpm_is_idle,
7942 .wait_for_idle = si_dpm_wait_for_idle,
7943 .soft_reset = si_dpm_soft_reset,
7944 .set_clockgating_state = si_dpm_set_clockgating_state,
7945 .set_powergating_state = si_dpm_set_powergating_state,
7946};
7947
7948static const struct amdgpu_dpm_funcs si_dpm_funcs = {
7949 .get_temperature = &si_dpm_get_temp,
7950 .pre_set_power_state = &si_dpm_pre_set_power_state,
7951 .set_power_state = &si_dpm_set_power_state,
7952 .post_set_power_state = &si_dpm_post_set_power_state,
7953 .display_configuration_changed = &si_dpm_display_configuration_changed,
7954 .get_sclk = &si_dpm_get_sclk,
7955 .get_mclk = &si_dpm_get_mclk,
7956 .print_power_state = &si_dpm_print_power_state,
7957 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
7958 .force_performance_level = &si_dpm_force_performance_level,
7959 .vblank_too_short = &si_dpm_vblank_too_short,
7960 .set_fan_control_mode = &si_dpm_set_fan_control_mode,
7961 .get_fan_control_mode = &si_dpm_get_fan_control_mode,
7962 .set_fan_speed_percent = &si_dpm_set_fan_speed_percent,
7963 .get_fan_speed_percent = &si_dpm_get_fan_speed_percent,
7964};
7965
7966static void si_dpm_set_dpm_funcs(struct amdgpu_device *adev)
7967{
7968 if (adev->pm.funcs == NULL)
7969 adev->pm.funcs = &si_dpm_funcs;
7970}
7971
7972static const struct amdgpu_irq_src_funcs si_dpm_irq_funcs = {
7973 .set = si_dpm_set_interrupt_state,
7974 .process = si_dpm_process_interrupt,
7975};
7976
7977static void si_dpm_set_irq_funcs(struct amdgpu_device *adev)
7978{
7979 adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST;
7980 adev->pm.dpm.thermal.irq.funcs = &si_dpm_irq_funcs;
7981}
7982
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