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drm/amdgpu/soc15: add need_reset_on_init asic callback for SOC15 (v2)
[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / amd / amdgpu / soc15.c
CommitLineData
220ab9bd
KW		 1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include <linux/slab.h>
25#include <linux/module.h>
248a1d6f 26#include <drm/drmP.h>
220ab9bd 27#include "amdgpu.h"
d05da0e2 28#include "amdgpu_atombios.h"
220ab9bd
KW		 29#include "amdgpu_ih.h"
30#include "amdgpu_uvd.h"
31#include "amdgpu_vce.h"
32#include "amdgpu_ucode.h"
33#include "amdgpu_psp.h"
34#include "atom.h"
35#include "amd_pcie.h"
36
5d735f83 37#include "uvd/uvd_7_0_offset.h"
cde5c34f
FX		 38#include "gc/gc_9_0_offset.h"
39#include "gc/gc_9_0_sh_mask.h"
812f77b7
FX		 40#include "sdma0/sdma0_4_0_offset.h"
41#include "sdma1/sdma1_4_0_offset.h"
75199b8c
FX		 42#include "hdp/hdp_4_0_offset.h"
43#include "hdp/hdp_4_0_sh_mask.h"
424d9bb4
FX		 44#include "smuio/smuio_9_0_offset.h"
45#include "smuio/smuio_9_0_sh_mask.h"
b45e18ac
KR		 46#include "nbio/nbio_7_0_default.h"
47#include "nbio/nbio_7_0_sh_mask.h"
48#include "nbio/nbio_7_0_smn.h"
9281f12c 49#include "mp/mp_9_0_offset.h"
220ab9bd
KW		 50
51#include "soc15.h"
52#include "soc15_common.h"
53#include "gfx_v9_0.h"
54#include "gmc_v9_0.h"
55#include "gfxhub_v1_0.h"
56#include "mmhub_v1_0.h"
070706c0 57#include "df_v1_7.h"
698758bb 58#include "df_v3_6.h"
220ab9bd
KW		 59#include "vega10_ih.h"
60#include "sdma_v4_0.h"
61#include "uvd_v7_0.h"
62#include "vce_v4_0.h"
f2d7e707 63#include "vcn_v1_0.h"
796b6568 64#include "dce_virtual.h"
f1a34465 65#include "mxgpu_ai.h"
220ab9bd 66
220ab9bd
KW		 67#define mmMP0_MISC_CGTT_CTRL0 0x01b9
68#define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0
69#define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba
70#define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0
71
a5d0f456
KF		 72/* for Vega20 register name change */
73#define mmHDP_MEM_POWER_CTRL 0x00d4
74#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK 0x00000001L
75#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK 0x00000002L
76#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L
77#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L
78#define mmHDP_MEM_POWER_CTRL_BASE_IDX 0
220ab9bd
KW		 79/*
80 * Indirect registers accessor
81 */
82static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
83{
84 unsigned long flags, address, data;
85 u32 r;
946a4d5b
SL		 86 address = adev->nbio_funcs->get_pcie_index_offset(adev);
87 data = adev->nbio_funcs->get_pcie_data_offset(adev);
220ab9bd
KW		 88
89 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
90 WREG32(address, reg);
91 (void)RREG32(address);
92 r = RREG32(data);
93 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
94 return r;
95}
96
97static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
98{
99 unsigned long flags, address, data;
220ab9bd 100
946a4d5b
SL		 101 address = adev->nbio_funcs->get_pcie_index_offset(adev);
102 data = adev->nbio_funcs->get_pcie_data_offset(adev);
220ab9bd
KW		 103
104 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
105 WREG32(address, reg);
106 (void)RREG32(address);
107 WREG32(data, v);
108 (void)RREG32(data);
109 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
110}
111
112static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
113{
114 unsigned long flags, address, data;
115 u32 r;
116
117 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
118 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
119
120 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
121 WREG32(address, ((reg) & 0x1ff));
122 r = RREG32(data);
123 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
124 return r;
125}
126
127static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
128{
129 unsigned long flags, address, data;
130
131 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
132 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
133
134 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
135 WREG32(address, ((reg) & 0x1ff));
136 WREG32(data, (v));
137 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
138}
139
140static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
141{
142 unsigned long flags, address, data;
143 u32 r;
144
145 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
146 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
147
148 spin_lock_irqsave(&adev->didt_idx_lock, flags);
149 WREG32(address, (reg));
150 r = RREG32(data);
151 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
152 return r;
153}
154
155static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
156{
157 unsigned long flags, address, data;
158
159 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
160 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
161
162 spin_lock_irqsave(&adev->didt_idx_lock, flags);
163 WREG32(address, (reg));
164 WREG32(data, (v));
165 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
166}
167
560460f2
EQ		 168static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
169{
170 unsigned long flags;
171 u32 r;
172
173 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
174 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
175 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
176 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
177 return r;
178}
179
180static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
181{
182 unsigned long flags;
183
184 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
185 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
186 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
187 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
188}
189
2f11fb02
EQ		 190static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
191{
192 unsigned long flags;
193 u32 r;
194
195 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
196 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
197 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
198 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
199 return r;
200}
201
202static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
203{
204 unsigned long flags;
205
206 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
207 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
208 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
209 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
210}
211
220ab9bd
KW		 212static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
213{
bf383fb6 214 return adev->nbio_funcs->get_memsize(adev);
220ab9bd
KW		 215}
216
220ab9bd
KW		 217static u32 soc15_get_xclk(struct amdgpu_device *adev)
218{
76d6172b 219 return adev->clock.spll.reference_freq;
220ab9bd
KW		 220}
221
222
223void soc15_grbm_select(struct amdgpu_device *adev,
224 u32 me, u32 pipe, u32 queue, u32 vmid)
225{
226 u32 grbm_gfx_cntl = 0;
227 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
228 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
229 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
230 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
231
232 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl);
233}
234
235static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)
236{
237 /* todo */
238}
239
240static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
241{
242 /* todo */
243 return false;
244}
245
246static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
247 u8 *bios, u32 length_bytes)
248{
249 u32 *dw_ptr;
250 u32 i, length_dw;
251
252 if (bios == NULL)
253 return false;
254 if (length_bytes == 0)
255 return false;
256 /* APU vbios image is part of sbios image */
257 if (adev->flags & AMD_IS_APU)
258 return false;
259
260 dw_ptr = (u32 *)bios;
261 length_dw = ALIGN(length_bytes, 4) / 4;
262
263 /* set rom index to 0 */
264 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0);
265 /* read out the rom data */
266 for (i = 0; i < length_dw; i++)
267 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA));
268
269 return true;
270}
271
946a4d5b
SL		 272struct soc15_allowed_register_entry {
273 uint32_t hwip;
274 uint32_t inst;
275 uint32_t seg;
276 uint32_t reg_offset;
277 bool grbm_indexed;
278};
279
280
281static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
282 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
283 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
284 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
285 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
286 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
287 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
288 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
289 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
290 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
291 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
292 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
293 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
294 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
295 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
296 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
297 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
298 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
299 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
5eeae247 300 { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)},
220ab9bd
KW		 301};
302
303static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
304 u32 sh_num, u32 reg_offset)
305{
306 uint32_t val;
307
308 mutex_lock(&adev->grbm_idx_mutex);
309 if (se_num != 0xffffffff || sh_num != 0xffffffff)
310 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
311
312 val = RREG32(reg_offset);
313
314 if (se_num != 0xffffffff || sh_num != 0xffffffff)
315 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
316 mutex_unlock(&adev->grbm_idx_mutex);
317 return val;
318}
319
c013cea2
AD		 320static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
321 bool indexed, u32 se_num,
322 u32 sh_num, u32 reg_offset)
323{
324 if (indexed) {
325 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
326 } else {
cd29253f 327 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
c013cea2 328 return adev->gfx.config.gb_addr_config;
5eeae247
AD		 329 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
330 return adev->gfx.config.db_debug2;
cd29253f 331 return RREG32(reg_offset);
c013cea2
AD		 332 }
333}
334
220ab9bd
KW		 335static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
336 u32 sh_num, u32 reg_offset, u32 *value)
337{
3032f350 338 uint32_t i;
946a4d5b 339 struct soc15_allowed_register_entry *en;
220ab9bd
KW		 340
341 *value = 0;
220ab9bd 342 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
946a4d5b
SL		 343 en = &soc15_allowed_read_registers[i];
344 if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
345 + en->reg_offset))
220ab9bd
KW		 346 continue;
347
97fcc76b
CK		 348 *value = soc15_get_register_value(adev,
349 soc15_allowed_read_registers[i].grbm_indexed,
350 se_num, sh_num, reg_offset);
220ab9bd
KW		 351 return 0;
352 }
353 return -EINVAL;
354}
355
946a4d5b
SL		 356
357/**
358 * soc15_program_register_sequence - program an array of registers.
359 *
360 * @adev: amdgpu_device pointer
361 * @regs: pointer to the register array
362 * @array_size: size of the register array
363 *
364 * Programs an array or registers with and and or masks.
365 * This is a helper for setting golden registers.
366 */
367
368void soc15_program_register_sequence(struct amdgpu_device *adev,
369 const struct soc15_reg_golden *regs,
370 const u32 array_size)
371{
372 const struct soc15_reg_golden *entry;
373 u32 tmp, reg;
374 int i;
375
376 for (i = 0; i < array_size; ++i) {
377 entry = &regs[i];
378 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
379
380 if (entry->and_mask == 0xffffffff) {
381 tmp = entry->or_mask;
382 } else {
383 tmp = RREG32(reg);
384 tmp &= ~(entry->and_mask);
385 tmp |= entry->or_mask;
386 }
387 WREG32(reg, tmp);
388 }
389
390}
391
392
98512bb8 393static int soc15_asic_reset(struct amdgpu_device *adev)
220ab9bd
KW		 394{
395 u32 i;
396
98512bb8
KW		 397 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
398
399 dev_info(adev->dev, "GPU reset\n");
220ab9bd
KW		 400
401 /* disable BM */
402 pci_clear_master(adev->pdev);
220ab9bd 403
98512bb8
KW		 404 pci_save_state(adev->pdev);
405
f75a9a5d 406 psp_gpu_reset(adev);
98512bb8
KW		 407
408 pci_restore_state(adev->pdev);
220ab9bd
KW		 409
410 /* wait for asic to come out of reset */
411 for (i = 0; i < adev->usec_timeout; i++) {
bf383fb6
AD		 412 u32 memsize = adev->nbio_funcs->get_memsize(adev);
413
aecbe64f 414 if (memsize != 0xffffffff)
220ab9bd
KW		 415 break;
416 udelay(1);
417 }
418
d05da0e2 419 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
220ab9bd
KW		 420
421 return 0;
422}
423
424/*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
425 u32 cntl_reg, u32 status_reg)
426{
427 return 0;
428}*/
429
430static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
431{
432 /*int r;
433
434 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
435 if (r)
436 return r;
437
438 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
439 */
440 return 0;
441}
442
443static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
444{
445 /* todo */
446
447 return 0;
448}
449
450static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
451{
452 if (pci_is_root_bus(adev->pdev->bus))
453 return;
454
455 if (amdgpu_pcie_gen2 == 0)
456 return;
457
458 if (adev->flags & AMD_IS_APU)
459 return;
460
461 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
462 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
463 return;
464
465 /* todo */
466}
467
468static void soc15_program_aspm(struct amdgpu_device *adev)
469{
470
471 if (amdgpu_aspm == 0)
472 return;
473
474 /* todo */
475}
476
477static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
bf383fb6 478 bool enable)
220ab9bd 479{
bf383fb6
AD		 480 adev->nbio_funcs->enable_doorbell_aperture(adev, enable);
481 adev->nbio_funcs->enable_doorbell_selfring_aperture(adev, enable);
220ab9bd
KW		 482}
483
484static const struct amdgpu_ip_block_version vega10_common_ip_block =
485{
486 .type = AMD_IP_BLOCK_TYPE_COMMON,
487 .major = 2,
488 .minor = 0,
489 .rev = 0,
490 .funcs = &soc15_common_ip_funcs,
491};
492
4cb0becb
HR		 493static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
494{
495 return adev->nbio_funcs->get_rev_id(adev);
496}
497
220ab9bd
KW		 498int soc15_set_ip_blocks(struct amdgpu_device *adev)
499{
4522824c
SL		 500 /* Set IP register base before any HW register access */
501 switch (adev->asic_type) {
502 case CHIP_VEGA10:
3084eb00 503 case CHIP_VEGA12:
4522824c
SL		 504 case CHIP_RAVEN:
505 vega10_reg_base_init(adev);
506 break;
8ee273e5
FX		 507 case CHIP_VEGA20:
508 vega20_reg_base_init(adev);
509 break;
4522824c
SL		 510 default:
511 return -EINVAL;
512 }
513
47622ba0
AD		 514 if (adev->asic_type == CHIP_VEGA20)
515 adev->gmc.xgmi.supported = true;
516
bf383fb6
AD		 517 if (adev->flags & AMD_IS_APU)
518 adev->nbio_funcs = &nbio_v7_0_funcs;
fe3c9489
FX		 519 else if (adev->asic_type == CHIP_VEGA20)
520 adev->nbio_funcs = &nbio_v7_4_funcs;
bf383fb6
AD		 521 else
522 adev->nbio_funcs = &nbio_v6_1_funcs;
523
698758bb
FX		 524 if (adev->asic_type == CHIP_VEGA20)
525 adev->df_funcs = &df_v3_6_funcs;
526 else
527 adev->df_funcs = &df_v1_7_funcs;
4cb0becb
HR		 528
529 adev->rev_id = soc15_get_rev_id(adev);
bf383fb6 530 adev->nbio_funcs->detect_hw_virt(adev);
1b922423 531
f1a34465
XY		 532 if (amdgpu_sriov_vf(adev))
533 adev->virt.ops = &xgpu_ai_virt_ops;
534
220ab9bd
KW		 535 switch (adev->asic_type) {
536 case CHIP_VEGA10:
692069a1 537 case CHIP_VEGA12:
7c7af6c1 538 case CHIP_VEGA20:
2990a1fc
AD		 539 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
540 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
541 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
654f761c
FX		 542 if (adev->asic_type == CHIP_VEGA20)
543 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
544 else
602ed6c6 545 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
009d9ed6
RZ		 546 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
547 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
a6637313
EQ		 548 if (!amdgpu_sriov_vf(adev))
549 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
f8445307 550 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
2990a1fc 551 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
ab587d4a
AD		 552#if defined(CONFIG_DRM_AMD_DC)
553 else if (amdgpu_device_has_dc_support(adev))
2990a1fc 554 amdgpu_device_ip_block_add(adev, &dm_ip_block);
ab587d4a
AD		 555#else
556# warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
557#endif
846311ae
FM		 558 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) {
559 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
560 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
561 }
220ab9bd 562 break;
1023b797 563 case CHIP_RAVEN:
40c2358b
HR		 564 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
565 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
2990a1fc
AD		 566 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
567 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
009d9ed6
RZ		 568 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
569 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
b905090d 570 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
d67fed16 571 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
2990a1fc 572 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
0bf954c1
AD		 573#if defined(CONFIG_DRM_AMD_DC)
574 else if (amdgpu_device_has_dc_support(adev))
2990a1fc 575 amdgpu_device_ip_block_add(adev, &dm_ip_block);
0bf954c1
AD		 576#else
577# warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
578#endif
2990a1fc 579 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
1023b797 580 break;
220ab9bd
KW		 581 default:
582 return -EINVAL;
583 }
584
585 return 0;
586}
587
69882565 588static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
73c73240 589{
69882565 590 adev->nbio_funcs->hdp_flush(adev, ring);
73c73240
AD		 591}
592
69882565
CK		 593static void soc15_invalidate_hdp(struct amdgpu_device *adev,
594 struct amdgpu_ring *ring)
73c73240 595{
69882565
CK		 596 if (!ring || !ring->funcs->emit_wreg)
597 WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
598 else
599 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
600 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
73c73240
AD		 601}
602
adbd4f89
AD		 603static bool soc15_need_full_reset(struct amdgpu_device *adev)
604{
605 /* change this when we implement soft reset */
606 return true;
607}
b45e18ac
KR		 608static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
609 uint64_t *count1)
610{
611 uint32_t perfctr = 0;
612 uint64_t cnt0_of, cnt1_of;
613 int tmp;
614
615 /* This reports 0 on APUs, so return to avoid writing/reading registers
616 * that may or may not be different from their GPU counterparts
617 */
618 if (adev->flags & AMD_IS_APU)
619 return;
620
621 /* Set the 2 events that we wish to watch, defined above */
622 /* Reg 40 is # received msgs, Reg 104 is # of posted requests sent */
623 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
624 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
625
626 /* Write to enable desired perf counters */
627 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr);
628 /* Zero out and enable the perf counters
629 * Write 0x5:
630 * Bit 0 = Start all counters(1)
631 * Bit 2 = Global counter reset enable(1)
632 */
633 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
634
635 msleep(1000);
636
637 /* Load the shadow and disable the perf counters
638 * Write 0x2:
639 * Bit 0 = Stop counters(0)
640 * Bit 1 = Load the shadow counters(1)
641 */
642 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
643
644 /* Read register values to get any >32bit overflow */
645 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK);
646 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
647 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
648
649 /* Get the values and add the overflow */
650 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
651 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
652}
adbd4f89 653
9281f12c
AD		 654static bool soc15_need_reset_on_init(struct amdgpu_device *adev)
655{
656 u32 sol_reg;
657
658 if (adev->flags & AMD_IS_APU)
659 return false;
660
661 /* Check sOS sign of life register to confirm sys driver and sOS
662 * are already been loaded.
663 */
664 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
665 if (sol_reg)
666 return true;
667
668 return false;
669}
670
220ab9bd
KW		 671static const struct amdgpu_asic_funcs soc15_asic_funcs =
672{
673 .read_disabled_bios = &soc15_read_disabled_bios,
674 .read_bios_from_rom = &soc15_read_bios_from_rom,
675 .read_register = &soc15_read_register,
676 .reset = &soc15_asic_reset,
677 .set_vga_state = &soc15_vga_set_state,
678 .get_xclk = &soc15_get_xclk,
679 .set_uvd_clocks = &soc15_set_uvd_clocks,
680 .set_vce_clocks = &soc15_set_vce_clocks,
681 .get_config_memsize = &soc15_get_config_memsize,
73c73240
AD		 682 .flush_hdp = &soc15_flush_hdp,
683 .invalidate_hdp = &soc15_invalidate_hdp,
adbd4f89 684 .need_full_reset = &soc15_need_full_reset,
062f3807 685 .init_doorbell_index = &vega10_doorbell_index_init,
b45e18ac 686 .get_pcie_usage = &soc15_get_pcie_usage,
9281f12c 687 .need_reset_on_init = &soc15_need_reset_on_init,
220ab9bd
KW		 688};
689
c93aa775
OZ		 690static const struct amdgpu_asic_funcs vega20_asic_funcs =
691{
692 .read_disabled_bios = &soc15_read_disabled_bios,
693 .read_bios_from_rom = &soc15_read_bios_from_rom,
694 .read_register = &soc15_read_register,
695 .reset = &soc15_asic_reset,
696 .set_vga_state = &soc15_vga_set_state,
697 .get_xclk = &soc15_get_xclk,
698 .set_uvd_clocks = &soc15_set_uvd_clocks,
699 .set_vce_clocks = &soc15_set_vce_clocks,
700 .get_config_memsize = &soc15_get_config_memsize,
701 .flush_hdp = &soc15_flush_hdp,
702 .invalidate_hdp = &soc15_invalidate_hdp,
703 .need_full_reset = &soc15_need_full_reset,
704 .init_doorbell_index = &vega20_doorbell_index_init,
b45e18ac 705 .get_pcie_usage = &soc15_get_pcie_usage,
9281f12c 706 .need_reset_on_init = &soc15_need_reset_on_init,
220ab9bd
KW		 707};
708
709static int soc15_common_early_init(void *handle)
710{
220ab9bd
KW		 711 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
712
713 adev->smc_rreg = NULL;
714 adev->smc_wreg = NULL;
715 adev->pcie_rreg = &soc15_pcie_rreg;
716 adev->pcie_wreg = &soc15_pcie_wreg;
717 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
718 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
719 adev->didt_rreg = &soc15_didt_rreg;
720 adev->didt_wreg = &soc15_didt_wreg;
560460f2
EQ		 721 adev->gc_cac_rreg = &soc15_gc_cac_rreg;
722 adev->gc_cac_wreg = &soc15_gc_cac_wreg;
2f11fb02
EQ		 723 adev->se_cac_rreg = &soc15_se_cac_rreg;
724 adev->se_cac_wreg = &soc15_se_cac_wreg;
220ab9bd 725
220ab9bd 726
220ab9bd
KW		 727 adev->external_rev_id = 0xFF;
728 switch (adev->asic_type) {
729 case CHIP_VEGA10:
c93aa775 730 adev->asic_funcs = &soc15_asic_funcs;
220ab9bd
KW		 731 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
732 AMD_CG_SUPPORT_GFX_MGLS |
733 AMD_CG_SUPPORT_GFX_RLC_LS |
734 AMD_CG_SUPPORT_GFX_CP_LS |
735 AMD_CG_SUPPORT_GFX_3D_CGCG |
736 AMD_CG_SUPPORT_GFX_3D_CGLS |
737 AMD_CG_SUPPORT_GFX_CGCG |
738 AMD_CG_SUPPORT_GFX_CGLS |
739 AMD_CG_SUPPORT_BIF_MGCG |
740 AMD_CG_SUPPORT_BIF_LS |
741 AMD_CG_SUPPORT_HDP_LS |
742 AMD_CG_SUPPORT_DRM_MGCG |
743 AMD_CG_SUPPORT_DRM_LS |
744 AMD_CG_SUPPORT_ROM_MGCG |
745 AMD_CG_SUPPORT_DF_MGCG |
746 AMD_CG_SUPPORT_SDMA_MGCG |
747 AMD_CG_SUPPORT_SDMA_LS |
748 AMD_CG_SUPPORT_MC_MGCG |
749 AMD_CG_SUPPORT_MC_LS;
750 adev->pg_flags = 0;
751 adev->external_rev_id = 0x1;
752 break;
692069a1 753 case CHIP_VEGA12:
c93aa775 754 adev->asic_funcs = &soc15_asic_funcs;
e4a38755
EQ		 755 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
756 AMD_CG_SUPPORT_GFX_MGLS |
757 AMD_CG_SUPPORT_GFX_CGCG |
758 AMD_CG_SUPPORT_GFX_CGLS |
759 AMD_CG_SUPPORT_GFX_3D_CGCG |
760 AMD_CG_SUPPORT_GFX_3D_CGLS |
761 AMD_CG_SUPPORT_GFX_CP_LS |
762 AMD_CG_SUPPORT_MC_LS |
763 AMD_CG_SUPPORT_MC_MGCG |
764 AMD_CG_SUPPORT_SDMA_MGCG |
765 AMD_CG_SUPPORT_SDMA_LS |
766 AMD_CG_SUPPORT_BIF_MGCG |
767 AMD_CG_SUPPORT_BIF_LS |
768 AMD_CG_SUPPORT_HDP_MGCG |
769 AMD_CG_SUPPORT_HDP_LS |
770 AMD_CG_SUPPORT_ROM_MGCG |
771 AMD_CG_SUPPORT_VCE_MGCG |
772 AMD_CG_SUPPORT_UVD_MGCG;
692069a1 773 adev->pg_flags = 0;
f559fe2b 774 adev->external_rev_id = adev->rev_id + 0x14;
692069a1 775 break;
935be7a0 776 case CHIP_VEGA20:
c93aa775 777 adev->asic_funcs = &vega20_asic_funcs;
3fdbab5f
EQ		 778 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
779 AMD_CG_SUPPORT_GFX_MGLS |
780 AMD_CG_SUPPORT_GFX_CGCG |
781 AMD_CG_SUPPORT_GFX_CGLS |
782 AMD_CG_SUPPORT_GFX_3D_CGCG |
783 AMD_CG_SUPPORT_GFX_3D_CGLS |
784 AMD_CG_SUPPORT_GFX_CP_LS |
785 AMD_CG_SUPPORT_MC_LS |
786 AMD_CG_SUPPORT_MC_MGCG |
787 AMD_CG_SUPPORT_SDMA_MGCG |
788 AMD_CG_SUPPORT_SDMA_LS |
789 AMD_CG_SUPPORT_BIF_MGCG |
790 AMD_CG_SUPPORT_BIF_LS |
791 AMD_CG_SUPPORT_HDP_MGCG |
102e4940 792 AMD_CG_SUPPORT_HDP_LS |
3fdbab5f
EQ		 793 AMD_CG_SUPPORT_ROM_MGCG |
794 AMD_CG_SUPPORT_VCE_MGCG |
795 AMD_CG_SUPPORT_UVD_MGCG;
935be7a0
FX		 796 adev->pg_flags = 0;
797 adev->external_rev_id = adev->rev_id + 0x28;
798 break;
957c6fe1 799 case CHIP_RAVEN:
c93aa775 800 adev->asic_funcs = &soc15_asic_funcs;
520cbe0f 801 if (adev->rev_id >= 0x8)
741deade
AD		 802 adev->external_rev_id = adev->rev_id + 0x81;
803 else if (adev->pdev->device == 0x15d8)
804 adev->external_rev_id = adev->rev_id + 0x41;
805 else
806 adev->external_rev_id = 0x1;
807
808 if (adev->rev_id >= 0x8) {
520cbe0f
HR		 809 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
810 AMD_CG_SUPPORT_GFX_MGLS |
811 AMD_CG_SUPPORT_GFX_CP_LS |
812 AMD_CG_SUPPORT_GFX_3D_CGCG |
813 AMD_CG_SUPPORT_GFX_3D_CGLS |
814 AMD_CG_SUPPORT_GFX_CGCG |
815 AMD_CG_SUPPORT_GFX_CGLS |
816 AMD_CG_SUPPORT_BIF_LS |
817 AMD_CG_SUPPORT_HDP_LS |
818 AMD_CG_SUPPORT_ROM_MGCG |
819 AMD_CG_SUPPORT_MC_MGCG |
820 AMD_CG_SUPPORT_MC_LS |
821 AMD_CG_SUPPORT_SDMA_MGCG |
822 AMD_CG_SUPPORT_SDMA_LS |
823 AMD_CG_SUPPORT_VCN_MGCG;
741deade
AD		 824
825 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
826 } else if (adev->pdev->device == 0x15d8) {
827 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGLS |
828 AMD_CG_SUPPORT_GFX_CP_LS |
829 AMD_CG_SUPPORT_GFX_3D_CGCG |
830 AMD_CG_SUPPORT_GFX_3D_CGLS |
831 AMD_CG_SUPPORT_GFX_CGCG |
832 AMD_CG_SUPPORT_GFX_CGLS |
833 AMD_CG_SUPPORT_BIF_LS |
834 AMD_CG_SUPPORT_HDP_LS |
835 AMD_CG_SUPPORT_ROM_MGCG |
836 AMD_CG_SUPPORT_MC_MGCG |
837 AMD_CG_SUPPORT_MC_LS |
838 AMD_CG_SUPPORT_SDMA_MGCG |
839 AMD_CG_SUPPORT_SDMA_LS;
840
841 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
842 AMD_PG_SUPPORT_MMHUB |
a3716d3a
JZ		 843 AMD_PG_SUPPORT_VCN |
844 AMD_PG_SUPPORT_VCN_DPG;
741deade 845 } else {
520cbe0f
HR		 846 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
847 AMD_CG_SUPPORT_GFX_MGLS |
848 AMD_CG_SUPPORT_GFX_RLC_LS |
849 AMD_CG_SUPPORT_GFX_CP_LS |
850 AMD_CG_SUPPORT_GFX_3D_CGCG |
851 AMD_CG_SUPPORT_GFX_3D_CGLS |
852 AMD_CG_SUPPORT_GFX_CGCG |
853 AMD_CG_SUPPORT_GFX_CGLS |
854 AMD_CG_SUPPORT_BIF_MGCG |
855 AMD_CG_SUPPORT_BIF_LS |
856 AMD_CG_SUPPORT_HDP_MGCG |
857 AMD_CG_SUPPORT_HDP_LS |
858 AMD_CG_SUPPORT_DRM_MGCG |
859 AMD_CG_SUPPORT_DRM_LS |
860 AMD_CG_SUPPORT_ROM_MGCG |
861 AMD_CG_SUPPORT_MC_MGCG |
862 AMD_CG_SUPPORT_MC_LS |
863 AMD_CG_SUPPORT_SDMA_MGCG |
864 AMD_CG_SUPPORT_SDMA_LS |
865 AMD_CG_SUPPORT_VCN_MGCG;
61c8e90d 866
741deade
AD		 867 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
868 }
a4494fda 869
8c7bf583
KF		 870 if (adev->powerplay.pp_feature & PP_GFXOFF_MASK)
871 adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
872 AMD_PG_SUPPORT_CP |
873 AMD_PG_SUPPORT_RLC_SMU_HS;
ad5a67a7 874 break;
220ab9bd
KW		 875 default:
876 /* FIXME: not supported yet */
877 return -EINVAL;
878 }
879
ab276632
XY		 880 if (amdgpu_sriov_vf(adev)) {
881 amdgpu_virt_init_setting(adev);
882 xgpu_ai_mailbox_set_irq_funcs(adev);
883 }
884
220ab9bd
KW		 885 return 0;
886}
887
81758c55
ML		 888static int soc15_common_late_init(void *handle)
889{
890 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
891
892 if (amdgpu_sriov_vf(adev))
893 xgpu_ai_mailbox_get_irq(adev);
894
895 return 0;
896}
897
220ab9bd
KW		 898static int soc15_common_sw_init(void *handle)
899{
81758c55
ML		 900 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
901
902 if (amdgpu_sriov_vf(adev))
903 xgpu_ai_mailbox_add_irq_id(adev);
904
220ab9bd
KW		 905 return 0;
906}
907
908static int soc15_common_sw_fini(void *handle)
909{
910 return 0;
911}
912
913static int soc15_common_hw_init(void *handle)
914{
915 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
916
220ab9bd
KW		 917 /* enable pcie gen2/3 link */
918 soc15_pcie_gen3_enable(adev);
919 /* enable aspm */
920 soc15_program_aspm(adev);
833fa075 921 /* setup nbio registers */
bf383fb6 922 adev->nbio_funcs->init_registers(adev);
220ab9bd
KW		 923 /* enable the doorbell aperture */
924 soc15_enable_doorbell_aperture(adev, true);
925
926 return 0;
927}
928
929static int soc15_common_hw_fini(void *handle)
930{
931 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
932
933 /* disable the doorbell aperture */
934 soc15_enable_doorbell_aperture(adev, false);
81758c55
ML		 935 if (amdgpu_sriov_vf(adev))
936 xgpu_ai_mailbox_put_irq(adev);
220ab9bd
KW		 937
938 return 0;
939}
940
941static int soc15_common_suspend(void *handle)
942{
943 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
944
945 return soc15_common_hw_fini(adev);
946}
947
948static int soc15_common_resume(void *handle)
949{
950 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
951
952 return soc15_common_hw_init(adev);
953}
954
955static bool soc15_common_is_idle(void *handle)
956{
957 return true;
958}
959
960static int soc15_common_wait_for_idle(void *handle)
961{
962 return 0;
963}
964
965static int soc15_common_soft_reset(void *handle)
966{
967 return 0;
968}
969
970static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable)
971{
972 uint32_t def, data;
973
a5d0f456
KF		 974 if (adev->asic_type == CHIP_VEGA20) {
975 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));
220ab9bd 976
a5d0f456
KF		 977 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
978 data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
979 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
980 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
981 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK;
982 else
983 data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
984 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
985 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
986 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK);
220ab9bd 987
a5d0f456
KF		 988 if (def != data)
989 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data);
990 } else {
991 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
992
993 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
994 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
995 else
996 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
997
998 if (def != data)
999 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
1000 }
220ab9bd
KW		 1001}
1002
1003static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
1004{
1005 uint32_t def, data;
1006
1007 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1008
1009 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
1010 data &= ~(0x01000000 |
1011 0x02000000 |
1012 0x04000000 |
1013 0x08000000 |
1014 0x10000000 |
1015 0x20000000 |
1016 0x40000000 |
1017 0x80000000);
1018 else
1019 data |= (0x01000000 |
1020 0x02000000 |
1021 0x04000000 |
1022 0x08000000 |
1023 0x10000000 |
1024 0x20000000 |
1025 0x40000000 |
1026 0x80000000);
1027
1028 if (def != data)
1029 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
1030}
1031
1032static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
1033{
1034 uint32_t def, data;
1035
1036 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1037
1038 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1039 data |= 1;
1040 else
1041 data &= ~1;
1042
1043 if (def != data)
1044 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
1045}
1046
1047static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
1048 bool enable)
1049{
1050 uint32_t def, data;
1051
1052 def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
1053
1054 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
1055 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1056 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
1057 else
1058 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1059 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
1060
1061 if (def != data)
1062 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data);
1063}
1064
220ab9bd
KW		 1065static int soc15_common_set_clockgating_state(void *handle,
1066 enum amd_clockgating_state state)
1067{
1068 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1069
6e9dc861
ML		 1070 if (amdgpu_sriov_vf(adev))
1071 return 0;
1072
220ab9bd
KW		 1073 switch (adev->asic_type) {
1074 case CHIP_VEGA10:
692069a1 1075 case CHIP_VEGA12:
f980d127 1076 case CHIP_VEGA20:
bf383fb6 1077 adev->nbio_funcs->update_medium_grain_clock_gating(adev,
220ab9bd 1078 state == AMD_CG_STATE_GATE ? true : false);
bf383fb6 1079 adev->nbio_funcs->update_medium_grain_light_sleep(adev,
220ab9bd
KW		 1080 state == AMD_CG_STATE_GATE ? true : false);
1081 soc15_update_hdp_light_sleep(adev,
1082 state == AMD_CG_STATE_GATE ? true : false);
1083 soc15_update_drm_clock_gating(adev,
1084 state == AMD_CG_STATE_GATE ? true : false);
1085 soc15_update_drm_light_sleep(adev,
1086 state == AMD_CG_STATE_GATE ? true : false);
1087 soc15_update_rom_medium_grain_clock_gating(adev,
1088 state == AMD_CG_STATE_GATE ? true : false);
070706c0 1089 adev->df_funcs->update_medium_grain_clock_gating(adev,
220ab9bd
KW		 1090 state == AMD_CG_STATE_GATE ? true : false);
1091 break;
9e5a9eb4 1092 case CHIP_RAVEN:
bf383fb6 1093 adev->nbio_funcs->update_medium_grain_clock_gating(adev,
9e5a9eb4 1094 state == AMD_CG_STATE_GATE ? true : false);
bf383fb6 1095 adev->nbio_funcs->update_medium_grain_light_sleep(adev,
9e5a9eb4
HR		 1096 state == AMD_CG_STATE_GATE ? true : false);
1097 soc15_update_hdp_light_sleep(adev,
1098 state == AMD_CG_STATE_GATE ? true : false);
1099 soc15_update_drm_clock_gating(adev,
1100 state == AMD_CG_STATE_GATE ? true : false);
1101 soc15_update_drm_light_sleep(adev,
1102 state == AMD_CG_STATE_GATE ? true : false);
1103 soc15_update_rom_medium_grain_clock_gating(adev,
1104 state == AMD_CG_STATE_GATE ? true : false);
1105 break;
220ab9bd
KW		 1106 default:
1107 break;
1108 }
1109 return 0;
1110}
1111
f9abe35c
HR		 1112static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
1113{
1114 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1115 int data;
1116
1117 if (amdgpu_sriov_vf(adev))
1118 *flags = 0;
1119
bf383fb6 1120 adev->nbio_funcs->get_clockgating_state(adev, flags);
f9abe35c
HR		 1121
1122 /* AMD_CG_SUPPORT_HDP_LS */
1123 data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
1124 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
1125 *flags |= AMD_CG_SUPPORT_HDP_LS;
1126
1127 /* AMD_CG_SUPPORT_DRM_MGCG */
1128 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1129 if (!(data & 0x01000000))
1130 *flags |= AMD_CG_SUPPORT_DRM_MGCG;
1131
1132 /* AMD_CG_SUPPORT_DRM_LS */
1133 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1134 if (data & 0x1)
1135 *flags |= AMD_CG_SUPPORT_DRM_LS;
1136
1137 /* AMD_CG_SUPPORT_ROM_MGCG */
1138 data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
1139 if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
1140 *flags |= AMD_CG_SUPPORT_ROM_MGCG;
1141
070706c0 1142 adev->df_funcs->get_clockgating_state(adev, flags);
f9abe35c
HR		 1143}
1144
220ab9bd
KW		 1145static int soc15_common_set_powergating_state(void *handle,
1146 enum amd_powergating_state state)
1147{
1148 /* todo */
1149 return 0;
1150}
1151
1152const struct amd_ip_funcs soc15_common_ip_funcs = {
1153 .name = "soc15_common",
1154 .early_init = soc15_common_early_init,
81758c55 1155 .late_init = soc15_common_late_init,
220ab9bd
KW		 1156 .sw_init = soc15_common_sw_init,
1157 .sw_fini = soc15_common_sw_fini,
1158 .hw_init = soc15_common_hw_init,
1159 .hw_fini = soc15_common_hw_fini,
1160 .suspend = soc15_common_suspend,
1161 .resume = soc15_common_resume,
1162 .is_idle = soc15_common_is_idle,
1163 .wait_for_idle = soc15_common_wait_for_idle,
1164 .soft_reset = soc15_common_soft_reset,
1165 .set_clockgating_state = soc15_common_set_clockgating_state,
1166 .set_powergating_state = soc15_common_set_powergating_state,
f9abe35c 1167 .get_clockgating_state= soc15_common_get_clockgating_state,
220ab9bd 1168};
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