[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / amdgpu / soc15d.h

/*
 * Copyright 2014 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#ifndef SOC15_H
#define SOC15_H

#define GFX9_NUM_GFX_RINGS     1
#define GFX9_NUM_COMPUTE_RINGS 8

/*
 * PM4
 */
#define	PACKET_TYPE0	0
#define	PACKET_TYPE1	1
#define	PACKET_TYPE2	2
#define	PACKET_TYPE3	3

#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
#define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF)
#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
#define PACKET0(reg, n)	((PACKET_TYPE0 << 30) |				\
			 ((reg) & 0xFFFF) |			\
			 ((n) & 0x3FFF) << 16)
#define CP_PACKET2			0x80000000
#define		PACKET2_PAD_SHIFT		0
#define		PACKET2_PAD_MASK		(0x3fffffff << 0)

#define PACKET2(v)	(CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))

#define PACKET3(op, n)	((PACKET_TYPE3 << 30) |				\
			 (((op) & 0xFF) << 8) |				\
			 ((n) & 0x3FFF) << 16)

#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)

#define	PACKETJ_CONDITION_CHECK0	0
#define	PACKETJ_CONDITION_CHECK1	1
#define	PACKETJ_CONDITION_CHECK2	2
#define	PACKETJ_CONDITION_CHECK3	3
#define	PACKETJ_CONDITION_CHECK4	4
#define	PACKETJ_CONDITION_CHECK5	5
#define	PACKETJ_CONDITION_CHECK6	6
#define	PACKETJ_CONDITION_CHECK7	7

#define	PACKETJ_TYPE0	0
#define	PACKETJ_TYPE1	1
#define	PACKETJ_TYPE2	2
#define	PACKETJ_TYPE3	3
#define	PACKETJ_TYPE4	4
#define	PACKETJ_TYPE5	5
#define	PACKETJ_TYPE6	6
#define	PACKETJ_TYPE7	7

#define PACKETJ(reg, r, cond, type)	((reg & 0x3FFFF) |			\
			 ((r & 0x3F) << 18) |			\
			 ((cond & 0xF) << 24) |				\
			 ((type & 0xF) << 28))

/* Packet 3 types */
#define	PACKET3_NOP					0x10
#define	PACKET3_SET_BASE				0x11
#define		PACKET3_BASE_INDEX(x)                  ((x) << 0)
#define			CE_PARTITION_BASE		3
#define	PACKET3_CLEAR_STATE				0x12
#define	PACKET3_INDEX_BUFFER_SIZE			0x13
#define	PACKET3_DISPATCH_DIRECT				0x15
#define	PACKET3_DISPATCH_INDIRECT			0x16
#define	PACKET3_ATOMIC_GDS				0x1D
#define	PACKET3_ATOMIC_MEM				0x1E
#define	PACKET3_OCCLUSION_QUERY				0x1F
#define	PACKET3_SET_PREDICATION				0x20
#define	PACKET3_REG_RMW					0x21
#define	PACKET3_COND_EXEC				0x22
#define	PACKET3_PRED_EXEC				0x23
#define	PACKET3_DRAW_INDIRECT				0x24
#define	PACKET3_DRAW_INDEX_INDIRECT			0x25
#define	PACKET3_INDEX_BASE				0x26
#define	PACKET3_DRAW_INDEX_2				0x27
#define	PACKET3_CONTEXT_CONTROL				0x28
#define	PACKET3_INDEX_TYPE				0x2A
#define	PACKET3_DRAW_INDIRECT_MULTI			0x2C
#define	PACKET3_DRAW_INDEX_AUTO				0x2D
#define	PACKET3_NUM_INSTANCES				0x2F
#define	PACKET3_DRAW_INDEX_MULTI_AUTO			0x30
#define	PACKET3_INDIRECT_BUFFER_CONST			0x33
#define	PACKET3_STRMOUT_BUFFER_UPDATE			0x34
#define	PACKET3_DRAW_INDEX_OFFSET_2			0x35
#define	PACKET3_DRAW_PREAMBLE				0x36
#define	PACKET3_WRITE_DATA				0x37
#define		WRITE_DATA_DST_SEL(x)                   ((x) << 8)
		/* 0 - register
		 * 1 - memory (sync - via GRBM)
		 * 2 - gl2
		 * 3 - gds
		 * 4 - reserved
		 * 5 - memory (async - direct)
		 */
#define		WR_ONE_ADDR                             (1 << 16)
#define		WR_CONFIRM                              (1 << 20)
#define		WRITE_DATA_CACHE_POLICY(x)              ((x) << 25)
		/* 0 - LRU
		 * 1 - Stream
		 */
#define		WRITE_DATA_ENGINE_SEL(x)                ((x) << 30)
		/* 0 - me
		 * 1 - pfp
		 * 2 - ce
		 */
#define	PACKET3_DRAW_INDEX_INDIRECT_MULTI		0x38
#define	PACKET3_MEM_SEMAPHORE				0x39
#              define PACKET3_SEM_USE_MAILBOX       (0x1 << 16)
#              define PACKET3_SEM_SEL_SIGNAL_TYPE   (0x1 << 20) /* 0 = increment, 1 = write 1 */
#              define PACKET3_SEM_SEL_SIGNAL	    (0x6 << 29)
#              define PACKET3_SEM_SEL_WAIT	    (0x7 << 29)
#define	PACKET3_WAIT_REG_MEM				0x3C
#define		WAIT_REG_MEM_FUNCTION(x)                ((x) << 0)
		/* 0 - always
		 * 1 - <
		 * 2 - <=
		 * 3 - ==
		 * 4 - !=
		 * 5 - >=
		 * 6 - >
		 */
#define		WAIT_REG_MEM_MEM_SPACE(x)               ((x) << 4)
		/* 0 - reg
		 * 1 - mem
		 */
#define		WAIT_REG_MEM_OPERATION(x)               ((x) << 6)
		/* 0 - wait_reg_mem
		 * 1 - wr_wait_wr_reg
		 */
#define		WAIT_REG_MEM_ENGINE(x)                  ((x) << 8)
		/* 0 - me
		 * 1 - pfp
		 */
#define	PACKET3_INDIRECT_BUFFER				0x3F
#define		INDIRECT_BUFFER_VALID                   (1 << 23)
#define		INDIRECT_BUFFER_CACHE_POLICY(x)         ((x) << 28)
		/* 0 - LRU
		 * 1 - Stream
		 * 2 - Bypass
		 */
#define     INDIRECT_BUFFER_PRE_ENB(x)		 ((x) << 21)
#define	PACKET3_COPY_DATA				0x40
#define	PACKET3_PFP_SYNC_ME				0x42
#define	PACKET3_COND_WRITE				0x45
#define	PACKET3_EVENT_WRITE				0x46
#define		EVENT_TYPE(x)                           ((x) << 0)
#define		EVENT_INDEX(x)                          ((x) << 8)
		/* 0 - any non-TS event
		 * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_*
		 * 2 - SAMPLE_PIPELINESTAT
		 * 3 - SAMPLE_STREAMOUTSTAT*
		 * 4 - *S_PARTIAL_FLUSH
		 */
#define	PACKET3_RELEASE_MEM				0x49
#define		EVENT_TYPE(x)                           ((x) << 0)
#define		EVENT_INDEX(x)                          ((x) << 8)
#define		EOP_TCL1_VOL_ACTION_EN                  (1 << 12)
#define		EOP_TC_VOL_ACTION_EN                    (1 << 13) /* L2 */
#define		EOP_TC_WB_ACTION_EN                     (1 << 15) /* L2 */
#define		EOP_TCL1_ACTION_EN                      (1 << 16)
#define		EOP_TC_ACTION_EN                        (1 << 17) /* L2 */
#define		EOP_TC_NC_ACTION_EN			(1 << 19)
#define		EOP_TC_MD_ACTION_EN			(1 << 21) /* L2 metadata */

#define		DATA_SEL(x)                             ((x) << 29)
		/* 0 - discard
		 * 1 - send low 32bit data
		 * 2 - send 64bit data
		 * 3 - send 64bit GPU counter value
		 * 4 - send 64bit sys counter value
		 */
#define		INT_SEL(x)                              ((x) << 24)
		/* 0 - none
		 * 1 - interrupt only (DATA_SEL = 0)
		 * 2 - interrupt when data write is confirmed
		 */
#define		DST_SEL(x)                              ((x) << 16)
		/* 0 - MC
		 * 1 - TC/L2
		 */


#define	PACKET3_PREAMBLE_CNTL				0x4A
#              define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE     (2 << 28)
#              define PACKET3_PREAMBLE_END_CLEAR_STATE       (3 << 28)
#define	PACKET3_DMA_DATA				0x50
/* 1. header
 * 2. CONTROL
 * 3. SRC_ADDR_LO or DATA [31:0]
 * 4. SRC_ADDR_HI [31:0]
 * 5. DST_ADDR_LO [31:0]
 * 6. DST_ADDR_HI [7:0]
 * 7. COMMAND [30:21] | BYTE_COUNT [20:0]
 */
/* CONTROL */
#              define PACKET3_DMA_DATA_ENGINE(x)     ((x) << 0)
		/* 0 - ME
		 * 1 - PFP
		 */
#              define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13)
		/* 0 - LRU
		 * 1 - Stream
		 */
#              define PACKET3_DMA_DATA_DST_SEL(x)  ((x) << 20)
		/* 0 - DST_ADDR using DAS
		 * 1 - GDS
		 * 3 - DST_ADDR using L2
		 */
#              define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25)
		/* 0 - LRU
		 * 1 - Stream
		 */
#              define PACKET3_DMA_DATA_SRC_SEL(x)  ((x) << 29)
		/* 0 - SRC_ADDR using SAS
		 * 1 - GDS
		 * 2 - DATA
		 * 3 - SRC_ADDR using L2
		 */
#              define PACKET3_DMA_DATA_CP_SYNC     (1 << 31)
/* COMMAND */
#              define PACKET3_DMA_DATA_CMD_SAS     (1 << 26)
		/* 0 - memory
		 * 1 - register
		 */
#              define PACKET3_DMA_DATA_CMD_DAS     (1 << 27)
		/* 0 - memory
		 * 1 - register
		 */
#              define PACKET3_DMA_DATA_CMD_SAIC    (1 << 28)
#              define PACKET3_DMA_DATA_CMD_DAIC    (1 << 29)
#              define PACKET3_DMA_DATA_CMD_RAW_WAIT  (1 << 30)
#define	PACKET3_ACQUIRE_MEM				0x58
/* 1.  HEADER
 * 2.  COHER_CNTL [30:0]
 * 2.1 ENGINE_SEL [31:31]
 * 3.  COHER_SIZE [31:0]
 * 4.  COHER_SIZE_HI [7:0]
 * 5.  COHER_BASE_LO [31:0]
 * 6.  COHER_BASE_HI [23:0]
 * 7.  POLL_INTERVAL [15:0]
 */
/* COHER_CNTL fields for CP_COHER_CNTL */
#define 	PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_NC_ACTION_ENA(x) ((x) << 3)
#define 	PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WC_ACTION_ENA(x) ((x) << 4)
#define 	PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_INV_METADATA_ACTION_ENA(x) ((x) << 5)
#define 	PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_VOL_ACTION_ENA(x) ((x) << 15)
#define 	PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(x) ((x) << 18)
#define 	PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(x) ((x) << 22)
#define 	PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(x) ((x) << 23)
#define 	PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_CB_ACTION_ENA(x) ((x) << 25)
#define 	PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_DB_ACTION_ENA(x) ((x) << 26)
#define 	PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(x) ((x) << 27)
#define 	PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_VOL_ACTION_ENA(x) ((x) << 28)
#define 	PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(x) ((x) << 29)
#define 	PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_WB_ACTION_ENA(x) ((x) << 30)
#define	PACKET3_REWIND					0x59
#define	PACKET3_LOAD_UCONFIG_REG			0x5E
#define	PACKET3_LOAD_SH_REG				0x5F
#define	PACKET3_LOAD_CONFIG_REG				0x60
#define	PACKET3_LOAD_CONTEXT_REG			0x61
#define	PACKET3_SET_CONFIG_REG				0x68
#define		PACKET3_SET_CONFIG_REG_START			0x00002000
#define		PACKET3_SET_CONFIG_REG_END			0x00002c00
#define	PACKET3_SET_CONTEXT_REG				0x69
#define		PACKET3_SET_CONTEXT_REG_START			0x0000a000
#define		PACKET3_SET_CONTEXT_REG_END			0x0000a400
#define	PACKET3_SET_CONTEXT_REG_INDIRECT		0x73
#define	PACKET3_SET_SH_REG				0x76
#define		PACKET3_SET_SH_REG_START			0x00002c00
#define		PACKET3_SET_SH_REG_END				0x00003000
#define	PACKET3_SET_SH_REG_OFFSET			0x77
#define	PACKET3_SET_QUEUE_REG				0x78
#define	PACKET3_SET_UCONFIG_REG				0x79
#define		PACKET3_SET_UCONFIG_REG_START			0x0000c000
#define		PACKET3_SET_UCONFIG_REG_END			0x0000c400
#define		PACKET3_SET_UCONFIG_REG_INDEX_TYPE		(2 << 28)
#define	PACKET3_SCRATCH_RAM_WRITE			0x7D
#define	PACKET3_SCRATCH_RAM_READ			0x7E
#define	PACKET3_LOAD_CONST_RAM				0x80
#define	PACKET3_WRITE_CONST_RAM				0x81
#define	PACKET3_DUMP_CONST_RAM				0x83
#define	PACKET3_INCREMENT_CE_COUNTER			0x84
#define	PACKET3_INCREMENT_DE_COUNTER			0x85
#define	PACKET3_WAIT_ON_CE_COUNTER			0x86
#define	PACKET3_WAIT_ON_DE_COUNTER_DIFF			0x88
#define	PACKET3_SWITCH_BUFFER				0x8B
#define PACKET3_FRAME_CONTROL				0x90
#			define FRAME_TMZ	(1 << 0)
#			define FRAME_CMD(x) ((x) << 28)
			/*
			 * x=0: tmz_begin
			 * x=1: tmz_end
			 */

#define	PACKET3_INVALIDATE_TLBS				0x98
#              define PACKET3_INVALIDATE_TLBS_DST_SEL(x)     ((x) << 0)
#              define PACKET3_INVALIDATE_TLBS_ALL_HUB(x)     ((x) << 4)
#              define PACKET3_INVALIDATE_TLBS_PASID(x)       ((x) << 5)
#              define PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(x)  ((x) << 29)
#define PACKET3_SET_RESOURCES				0xA0
/* 1. header
 * 2. CONTROL
 * 3. QUEUE_MASK_LO [31:0]
 * 4. QUEUE_MASK_HI [31:0]
 * 5. GWS_MASK_LO [31:0]
 * 6. GWS_MASK_HI [31:0]
 * 7. OAC_MASK [15:0]
 * 8. GDS_HEAP_SIZE [16:11] | GDS_HEAP_BASE [5:0]
 */
#              define PACKET3_SET_RESOURCES_VMID_MASK(x)     ((x) << 0)
#              define PACKET3_SET_RESOURCES_UNMAP_LATENTY(x) ((x) << 16)
#              define PACKET3_SET_RESOURCES_QUEUE_TYPE(x)    ((x) << 29)
#define PACKET3_MAP_QUEUES				0xA2
/* 1. header
 * 2. CONTROL
 * 3. CONTROL2
 * 4. MQD_ADDR_LO [31:0]
 * 5. MQD_ADDR_HI [31:0]
 * 6. WPTR_ADDR_LO [31:0]
 * 7. WPTR_ADDR_HI [31:0]
 */
/* CONTROL */
#              define PACKET3_MAP_QUEUES_QUEUE_SEL(x)       ((x) << 4)
#              define PACKET3_MAP_QUEUES_VMID(x)            ((x) << 8)
#              define PACKET3_MAP_QUEUES_QUEUE(x)           ((x) << 13)
#              define PACKET3_MAP_QUEUES_PIPE(x)            ((x) << 16)
#              define PACKET3_MAP_QUEUES_ME(x)              ((x) << 18)
#              define PACKET3_MAP_QUEUES_QUEUE_TYPE(x)      ((x) << 21)
#              define PACKET3_MAP_QUEUES_ALLOC_FORMAT(x)    ((x) << 24)
#              define PACKET3_MAP_QUEUES_ENGINE_SEL(x)      ((x) << 26)
#              define PACKET3_MAP_QUEUES_NUM_QUEUES(x)      ((x) << 29)
/* CONTROL2 */
#              define PACKET3_MAP_QUEUES_CHECK_DISABLE(x)   ((x) << 1)
#              define PACKET3_MAP_QUEUES_DOORBELL_OFFSET(x) ((x) << 2)
#define	PACKET3_UNMAP_QUEUES				0xA3
/* 1. header
 * 2. CONTROL
 * 3. CONTROL2
 * 4. CONTROL3
 * 5. CONTROL4
 * 6. CONTROL5
 */
/* CONTROL */
#              define PACKET3_UNMAP_QUEUES_ACTION(x)           ((x) << 0)
		/* 0 - PREEMPT_QUEUES
		 * 1 - RESET_QUEUES
		 * 2 - DISABLE_PROCESS_QUEUES
		 * 3 - PREEMPT_QUEUES_NO_UNMAP
		 */
#              define PACKET3_UNMAP_QUEUES_QUEUE_SEL(x)        ((x) << 4)
#              define PACKET3_UNMAP_QUEUES_ENGINE_SEL(x)       ((x) << 26)
#              define PACKET3_UNMAP_QUEUES_NUM_QUEUES(x)       ((x) << 29)
/* CONTROL2a */
#              define PACKET3_UNMAP_QUEUES_PASID(x)            ((x) << 0)
/* CONTROL2b */
#              define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(x) ((x) << 2)
/* CONTROL3a */
#              define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1(x) ((x) << 2)
/* CONTROL3b */
#              define PACKET3_UNMAP_QUEUES_RB_WPTR(x)          ((x) << 0)
/* CONTROL4 */
#              define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2(x) ((x) << 2)
/* CONTROL5 */
#              define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3(x) ((x) << 2)
#define	PACKET3_QUERY_STATUS				0xA4
/* 1. header
 * 2. CONTROL
 * 3. CONTROL2
 * 4. ADDR_LO [31:0]
 * 5. ADDR_HI [31:0]
 * 6. DATA_LO [31:0]
 * 7. DATA_HI [31:0]
 */
/* CONTROL */
#              define PACKET3_QUERY_STATUS_CONTEXT_ID(x)       ((x) << 0)
#              define PACKET3_QUERY_STATUS_INTERRUPT_SEL(x)    ((x) << 28)
#              define PACKET3_QUERY_STATUS_COMMAND(x)          ((x) << 30)
/* CONTROL2a */
#              define PACKET3_QUERY_STATUS_PASID(x)            ((x) << 0)
/* CONTROL2b */
#              define PACKET3_QUERY_STATUS_DOORBELL_OFFSET(x)  ((x) << 2)
#              define PACKET3_QUERY_STATUS_ENG_SEL(x)          ((x) << 25)


#define VCE_CMD_NO_OP		0x00000000
#define VCE_CMD_END		0x00000001
#define VCE_CMD_IB		0x00000002
#define VCE_CMD_FENCE		0x00000003
#define VCE_CMD_TRAP		0x00000004
#define VCE_CMD_IB_AUTO 	0x00000005
#define VCE_CMD_SEMAPHORE	0x00000006

#define VCE_CMD_IB_VM           0x00000102
#define VCE_CMD_WAIT_GE         0x00000106
#define VCE_CMD_UPDATE_PTB      0x00000107
#define VCE_CMD_FLUSH_TLB       0x00000108
#define VCE_CMD_REG_WRITE       0x00000109
#define VCE_CMD_REG_WAIT        0x0000010a

#define HEVC_ENC_CMD_NO_OP		0x00000000
#define HEVC_ENC_CMD_END		0x00000001
#define HEVC_ENC_CMD_FENCE		0x00000003
#define HEVC_ENC_CMD_TRAP		0x00000004
#define HEVC_ENC_CMD_IB_VM		0x00000102
#define HEVC_ENC_CMD_REG_WRITE		0x00000109
#define HEVC_ENC_CMD_REG_WAIT		0x0000010a

#endif
Commit	Line	Data
8e3153ba KW	1	/*
	2	* Copyright 2014 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23	#ifndef SOC15_H
	24	#define SOC15_H
	25
	26	#define GFX9_NUM_GFX_RINGS 1
	27	#define GFX9_NUM_COMPUTE_RINGS 8
	28
	29	/*
	30	* PM4
	31	*/
	32	#define PACKET_TYPE0 0
	33	#define PACKET_TYPE1 1
	34	#define PACKET_TYPE2 2
	35	#define PACKET_TYPE3 3
	36
	37	#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
	38	#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
	39	#define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF)
	40	#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
	41	#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) \| \
	42	((reg) & 0xFFFF) \| \
	43	((n) & 0x3FFF) << 16)
	44	#define CP_PACKET2 0x80000000
	45	#define PACKET2_PAD_SHIFT 0
	46	#define PACKET2_PAD_MASK (0x3fffffff << 0)
	47
	48	#define PACKET2(v) (CP_PACKET2 \| REG_SET(PACKET2_PAD, (v)))
	49
	50	#define PACKET3(op, n) ((PACKET_TYPE3 << 30) \| \
	51	(((op) & 0xFF) << 8) \| \
	52	((n) & 0x3FFF) << 16)
	53
	54	#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) \| 1 << 1)
	55
d521093a BZ	56	#define PACKETJ_CONDITION_CHECK0 0
	57	#define PACKETJ_CONDITION_CHECK1 1
	58	#define PACKETJ_CONDITION_CHECK2 2
	59	#define PACKETJ_CONDITION_CHECK3 3
	60	#define PACKETJ_CONDITION_CHECK4 4
	61	#define PACKETJ_CONDITION_CHECK5 5
	62	#define PACKETJ_CONDITION_CHECK6 6
	63	#define PACKETJ_CONDITION_CHECK7 7
	64
	65	#define PACKETJ_TYPE0 0
	66	#define PACKETJ_TYPE1 1
	67	#define PACKETJ_TYPE2 2
	68	#define PACKETJ_TYPE3 3
	69	#define PACKETJ_TYPE4 4
	70	#define PACKETJ_TYPE5 5
	71	#define PACKETJ_TYPE6 6
	72	#define PACKETJ_TYPE7 7
	73
	74	#define PACKETJ(reg, r, cond, type) ((reg & 0x3FFFF) \| \
	75	((r & 0x3F) << 18) \| \
	76	((cond & 0xF) << 24) \| \
	77	((type & 0xF) << 28))
	78
8e3153ba KW	79	/* Packet 3 types */
	80	#define PACKET3_NOP 0x10
	81	#define PACKET3_SET_BASE 0x11
	82	#define PACKET3_BASE_INDEX(x) ((x) << 0)
	83	#define CE_PARTITION_BASE 3
	84	#define PACKET3_CLEAR_STATE 0x12
	85	#define PACKET3_INDEX_BUFFER_SIZE 0x13
	86	#define PACKET3_DISPATCH_DIRECT 0x15
	87	#define PACKET3_DISPATCH_INDIRECT 0x16
	88	#define PACKET3_ATOMIC_GDS 0x1D
	89	#define PACKET3_ATOMIC_MEM 0x1E
	90	#define PACKET3_OCCLUSION_QUERY 0x1F
	91	#define PACKET3_SET_PREDICATION 0x20
	92	#define PACKET3_REG_RMW 0x21
	93	#define PACKET3_COND_EXEC 0x22
	94	#define PACKET3_PRED_EXEC 0x23
	95	#define PACKET3_DRAW_INDIRECT 0x24
	96	#define PACKET3_DRAW_INDEX_INDIRECT 0x25
	97	#define PACKET3_INDEX_BASE 0x26
	98	#define PACKET3_DRAW_INDEX_2 0x27
	99	#define PACKET3_CONTEXT_CONTROL 0x28
	100	#define PACKET3_INDEX_TYPE 0x2A
	101	#define PACKET3_DRAW_INDIRECT_MULTI 0x2C
	102	#define PACKET3_DRAW_INDEX_AUTO 0x2D
	103	#define PACKET3_NUM_INSTANCES 0x2F
	104	#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
	105	#define PACKET3_INDIRECT_BUFFER_CONST 0x33
	106	#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
	107	#define PACKET3_DRAW_INDEX_OFFSET_2 0x35
	108	#define PACKET3_DRAW_PREAMBLE 0x36
	109	#define PACKET3_WRITE_DATA 0x37
	110	#define WRITE_DATA_DST_SEL(x) ((x) << 8)
	111	/* 0 - register
	112	* 1 - memory (sync - via GRBM)
	113	* 2 - gl2
	114	* 3 - gds
	115	* 4 - reserved
	116	* 5 - memory (async - direct)
	117	*/
	118	#define WR_ONE_ADDR (1 << 16)
	119	#define WR_CONFIRM (1 << 20)
	120	#define WRITE_DATA_CACHE_POLICY(x) ((x) << 25)
	121	/* 0 - LRU
	122	* 1 - Stream
	123	*/
	124	#define WRITE_DATA_ENGINE_SEL(x) ((x) << 30)
	125	/* 0 - me
	126	* 1 - pfp
	127	* 2 - ce
	128	*/
	129	#define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38
	130	#define PACKET3_MEM_SEMAPHORE 0x39
	131	# define PACKET3_SEM_USE_MAILBOX (0x1 << 16)
	132	# define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */
	133	# define PACKET3_SEM_SEL_SIGNAL (0x6 << 29)
	134	# define PACKET3_SEM_SEL_WAIT (0x7 << 29)
	135	#define PACKET3_WAIT_REG_MEM 0x3C
	136	#define WAIT_REG_MEM_FUNCTION(x) ((x) << 0)
	137	/* 0 - always
	138	* 1 - <
	139	* 2 - <=
	140	* 3 - ==
	141	* 4 - !=
	142	* 5 - >=
143	* 6 - >
144	*/
145	#define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4)
146	/* 0 - reg
147	* 1 - mem
148	*/
149	#define WAIT_REG_MEM_OPERATION(x) ((x) << 6)
150	/* 0 - wait_reg_mem
151	* 1 - wr_wait_wr_reg
152	*/
153	#define WAIT_REG_MEM_ENGINE(x) ((x) << 8)
154	/* 0 - me
155	* 1 - pfp
156	*/
157	#define PACKET3_INDIRECT_BUFFER 0x3F
67fb56a6	158	#define INDIRECT_BUFFER_VALID (1 << 23)
8e3153ba KW	159	#define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28)
	160	/* 0 - LRU
	161	* 1 - Stream
	162	* 2 - Bypass
	163	*/
9ccd52eb	164	#define INDIRECT_BUFFER_PRE_ENB(x) ((x) << 21)
8e3153ba KW	165	#define PACKET3_COPY_DATA 0x40
	166	#define PACKET3_PFP_SYNC_ME 0x42
	167	#define PACKET3_COND_WRITE 0x45
	168	#define PACKET3_EVENT_WRITE 0x46
	169	#define EVENT_TYPE(x) ((x) << 0)
	170	#define EVENT_INDEX(x) ((x) << 8)
	171	/* 0 - any non-TS event
	172	* 1 - ZPASS_DONE, PIXEL_PIPE_STAT_*
	173	* 2 - SAMPLE_PIPELINESTAT
	174	* 3 - SAMPLE_STREAMOUTSTAT*
	175	* 4 - *S_PARTIAL_FLUSH
	176	*/
	177	#define PACKET3_RELEASE_MEM 0x49
	178	#define EVENT_TYPE(x) ((x) << 0)
	179	#define EVENT_INDEX(x) ((x) << 8)
	180	#define EOP_TCL1_VOL_ACTION_EN (1 << 12)
	181	#define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */
	182	#define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */
	183	#define EOP_TCL1_ACTION_EN (1 << 16)
	184	#define EOP_TC_ACTION_EN (1 << 17) /* L2 */
d240cd9e	185	#define EOP_TC_NC_ACTION_EN (1 << 19)
8e3153ba KW	186	#define EOP_TC_MD_ACTION_EN (1 << 21) /* L2 metadata */
	187
	188	#define DATA_SEL(x) ((x) << 29)
	189	/* 0 - discard
	190	* 1 - send low 32bit data
	191	* 2 - send 64bit data
	192	* 3 - send 64bit GPU counter value
	193	* 4 - send 64bit sys counter value
	194	*/
	195	#define INT_SEL(x) ((x) << 24)
	196	/* 0 - none
	197	* 1 - interrupt only (DATA_SEL = 0)
	198	* 2 - interrupt when data write is confirmed
	199	*/
	200	#define DST_SEL(x) ((x) << 16)
	201	/* 0 - MC
	202	* 1 - TC/L2
	203	*/
	204
	205
	206
	207	#define PACKET3_PREAMBLE_CNTL 0x4A
	208	# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
	209	# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
	210	#define PACKET3_DMA_DATA 0x50
	211	/* 1. header
	212	* 2. CONTROL
	213	* 3. SRC_ADDR_LO or DATA [31:0]
	214	* 4. SRC_ADDR_HI [31:0]
	215	* 5. DST_ADDR_LO [31:0]
	216	* 6. DST_ADDR_HI [7:0]
	217	* 7. COMMAND [30:21] \| BYTE_COUNT [20:0]
	218	*/
	219	/* CONTROL */
	220	# define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0)
	221	/* 0 - ME
	222	* 1 - PFP
	223	*/
	224	# define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13)
	225	/* 0 - LRU
	226	* 1 - Stream
	227	*/
	228	# define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20)
	229	/* 0 - DST_ADDR using DAS
	230	* 1 - GDS
	231	* 3 - DST_ADDR using L2
	232	*/
	233	# define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25)
	234	/* 0 - LRU
	235	* 1 - Stream
	236	*/
	237	# define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29)
	238	/* 0 - SRC_ADDR using SAS
	239	* 1 - GDS
	240	* 2 - DATA
	241	* 3 - SRC_ADDR using L2
	242	*/
	243	# define PACKET3_DMA_DATA_CP_SYNC (1 << 31)
	244	/* COMMAND */
	245	# define PACKET3_DMA_DATA_CMD_SAS (1 << 26)
	246	/* 0 - memory
	247	* 1 - register
	248	*/
	249	# define PACKET3_DMA_DATA_CMD_DAS (1 << 27)
250	/* 0 - memory
251	* 1 - register
252	*/
253	# define PACKET3_DMA_DATA_CMD_SAIC (1 << 28)
254	# define PACKET3_DMA_DATA_CMD_DAIC (1 << 29)
255	# define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30)
73339a71 AG	256	#define PACKET3_ACQUIRE_MEM 0x58
	257	/* 1. HEADER
	258	* 2. COHER_CNTL [30:0]
	259	* 2.1 ENGINE_SEL [31:31]
	260	* 3. COHER_SIZE [31:0]
	261	* 4. COHER_SIZE_HI [7:0]
	262	* 5. COHER_BASE_LO [31:0]
	263	* 6. COHER_BASE_HI [23:0]
	264	* 7. POLL_INTERVAL [15:0]
	265	*/
	266	/* COHER_CNTL fields for CP_COHER_CNTL */
	267	#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_NC_ACTION_ENA(x) ((x) << 3)
	268	#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WC_ACTION_ENA(x) ((x) << 4)
	269	#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_INV_METADATA_ACTION_ENA(x) ((x) << 5)
	270	#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_VOL_ACTION_ENA(x) ((x) << 15)
	271	#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(x) ((x) << 18)
	272	#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(x) ((x) << 22)
	273	#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(x) ((x) << 23)
	274	#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_CB_ACTION_ENA(x) ((x) << 25)
	275	#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_DB_ACTION_ENA(x) ((x) << 26)
	276	#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(x) ((x) << 27)
	277	#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_VOL_ACTION_ENA(x) ((x) << 28)
	278	#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(x) ((x) << 29)
	279	#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_WB_ACTION_ENA(x) ((x) << 30)
8e3153ba KW	280	#define PACKET3_REWIND 0x59
	281	#define PACKET3_LOAD_UCONFIG_REG 0x5E
	282	#define PACKET3_LOAD_SH_REG 0x5F
	283	#define PACKET3_LOAD_CONFIG_REG 0x60
	284	#define PACKET3_LOAD_CONTEXT_REG 0x61
	285	#define PACKET3_SET_CONFIG_REG 0x68
	286	#define PACKET3_SET_CONFIG_REG_START 0x00002000
	287	#define PACKET3_SET_CONFIG_REG_END 0x00002c00
	288	#define PACKET3_SET_CONTEXT_REG 0x69
	289	#define PACKET3_SET_CONTEXT_REG_START 0x0000a000
	290	#define PACKET3_SET_CONTEXT_REG_END 0x0000a400
	291	#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
	292	#define PACKET3_SET_SH_REG 0x76
	293	#define PACKET3_SET_SH_REG_START 0x00002c00
	294	#define PACKET3_SET_SH_REG_END 0x00003000
	295	#define PACKET3_SET_SH_REG_OFFSET 0x77
	296	#define PACKET3_SET_QUEUE_REG 0x78
	297	#define PACKET3_SET_UCONFIG_REG 0x79
	298	#define PACKET3_SET_UCONFIG_REG_START 0x0000c000
	299	#define PACKET3_SET_UCONFIG_REG_END 0x0000c400
d5de797f	300	#define PACKET3_SET_UCONFIG_REG_INDEX_TYPE (2 << 28)
8e3153ba KW	301	#define PACKET3_SCRATCH_RAM_WRITE 0x7D
	302	#define PACKET3_SCRATCH_RAM_READ 0x7E
	303	#define PACKET3_LOAD_CONST_RAM 0x80
	304	#define PACKET3_WRITE_CONST_RAM 0x81
	305	#define PACKET3_DUMP_CONST_RAM 0x83
	306	#define PACKET3_INCREMENT_CE_COUNTER 0x84
	307	#define PACKET3_INCREMENT_DE_COUNTER 0x85
	308	#define PACKET3_WAIT_ON_CE_COUNTER 0x86
	309	#define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88
	310	#define PACKET3_SWITCH_BUFFER 0x8B
d951eedd	311	#define PACKET3_FRAME_CONTROL 0x90
eda982a6	312	# define FRAME_TMZ (1 << 0)
d951eedd ML	313	# define FRAME_CMD(x) ((x) << 28)
	314	/*
	315	* x=0: tmz_begin
	316	* x=1: tmz_end
	317	*/
	318
ab88bded FK	319	#define PACKET3_INVALIDATE_TLBS 0x98
	320	# define PACKET3_INVALIDATE_TLBS_DST_SEL(x) ((x) << 0)
	321	# define PACKET3_INVALIDATE_TLBS_ALL_HUB(x) ((x) << 4)
	322	# define PACKET3_INVALIDATE_TLBS_PASID(x) ((x) << 5)
	323	# define PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(x) ((x) << 29)
464826d6	324	#define PACKET3_SET_RESOURCES 0xA0
495a7463 AD	325	/* 1. header
	326	* 2. CONTROL
	327	* 3. QUEUE_MASK_LO [31:0]
	328	* 4. QUEUE_MASK_HI [31:0]
	329	* 5. GWS_MASK_LO [31:0]
	330	* 6. GWS_MASK_HI [31:0]
	331	* 7. OAC_MASK [15:0]
	332	* 8. GDS_HEAP_SIZE [16:11] \| GDS_HEAP_BASE [5:0]
	333	*/
	334	# define PACKET3_SET_RESOURCES_VMID_MASK(x) ((x) << 0)
	335	# define PACKET3_SET_RESOURCES_UNMAP_LATENTY(x) ((x) << 16)
	336	# define PACKET3_SET_RESOURCES_QUEUE_TYPE(x) ((x) << 29)
464826d6	337	#define PACKET3_MAP_QUEUES 0xA2
495a7463 AD	338	/* 1. header
	339	* 2. CONTROL
	340	* 3. CONTROL2
	341	* 4. MQD_ADDR_LO [31:0]
	342	* 5. MQD_ADDR_HI [31:0]
	343	* 6. WPTR_ADDR_LO [31:0]
	344	* 7. WPTR_ADDR_HI [31:0]
	345	*/
	346	/* CONTROL */
	347	# define PACKET3_MAP_QUEUES_QUEUE_SEL(x) ((x) << 4)
	348	# define PACKET3_MAP_QUEUES_VMID(x) ((x) << 8)
	349	# define PACKET3_MAP_QUEUES_QUEUE(x) ((x) << 13)
	350	# define PACKET3_MAP_QUEUES_PIPE(x) ((x) << 16)
	351	# define PACKET3_MAP_QUEUES_ME(x) ((x) << 18)
	352	# define PACKET3_MAP_QUEUES_QUEUE_TYPE(x) ((x) << 21)
	353	# define PACKET3_MAP_QUEUES_ALLOC_FORMAT(x) ((x) << 24)
	354	# define PACKET3_MAP_QUEUES_ENGINE_SEL(x) ((x) << 26)
	355	# define PACKET3_MAP_QUEUES_NUM_QUEUES(x) ((x) << 29)
	356	/* CONTROL2 */
	357	# define PACKET3_MAP_QUEUES_CHECK_DISABLE(x) ((x) << 1)
	358	# define PACKET3_MAP_QUEUES_DOORBELL_OFFSET(x) ((x) << 2)
	359	#define PACKET3_UNMAP_QUEUES 0xA3
	360	/* 1. header
	361	* 2. CONTROL
	362	* 3. CONTROL2
	363	* 4. CONTROL3
	364	* 5. CONTROL4
	365	* 6. CONTROL5
	366	*/
	367	/* CONTROL */
	368	# define PACKET3_UNMAP_QUEUES_ACTION(x) ((x) << 0)
	369	/* 0 - PREEMPT_QUEUES
	370	* 1 - RESET_QUEUES
	371	* 2 - DISABLE_PROCESS_QUEUES
	372	* 3 - PREEMPT_QUEUES_NO_UNMAP
	373	*/
	374	# define PACKET3_UNMAP_QUEUES_QUEUE_SEL(x) ((x) << 4)
	375	# define PACKET3_UNMAP_QUEUES_ENGINE_SEL(x) ((x) << 26)
	376	# define PACKET3_UNMAP_QUEUES_NUM_QUEUES(x) ((x) << 29)
	377	/* CONTROL2a */
	378	# define PACKET3_UNMAP_QUEUES_PASID(x) ((x) << 0)
	379	/* CONTROL2b */
	380	# define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(x) ((x) << 2)
	381	/* CONTROL3a */
	382	# define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1(x) ((x) << 2)
	383	/* CONTROL3b */
	384	# define PACKET3_UNMAP_QUEUES_RB_WPTR(x) ((x) << 0)
	385	/* CONTROL4 */
	386	# define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2(x) ((x) << 2)
	387	/* CONTROL5 */
	388	# define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3(x) ((x) << 2)
	389	#define PACKET3_QUERY_STATUS 0xA4
	390	/* 1. header
	391	* 2. CONTROL
	392	* 3. CONTROL2
	393	* 4. ADDR_LO [31:0]
	394	* 5. ADDR_HI [31:0]
	395	* 6. DATA_LO [31:0]
	396	* 7. DATA_HI [31:0]
	397	*/
	398	/* CONTROL */
	399	# define PACKET3_QUERY_STATUS_CONTEXT_ID(x) ((x) << 0)
	400	# define PACKET3_QUERY_STATUS_INTERRUPT_SEL(x) ((x) << 28)
	401	# define PACKET3_QUERY_STATUS_COMMAND(x) ((x) << 30)
402	/* CONTROL2a */
403	# define PACKET3_QUERY_STATUS_PASID(x) ((x) << 0)
404	/* CONTROL2b */
405	# define PACKET3_QUERY_STATUS_DOORBELL_OFFSET(x) ((x) << 2)
406	# define PACKET3_QUERY_STATUS_ENG_SEL(x) ((x) << 25)
407
8e3153ba KW	408
	409	#define VCE_CMD_NO_OP 0x00000000
	410	#define VCE_CMD_END 0x00000001
	411	#define VCE_CMD_IB 0x00000002
	412	#define VCE_CMD_FENCE 0x00000003
	413	#define VCE_CMD_TRAP 0x00000004
	414	#define VCE_CMD_IB_AUTO 0x00000005
	415	#define VCE_CMD_SEMAPHORE 0x00000006
	416
	417	#define VCE_CMD_IB_VM 0x00000102
	418	#define VCE_CMD_WAIT_GE 0x00000106
	419	#define VCE_CMD_UPDATE_PTB 0x00000107
	420	#define VCE_CMD_FLUSH_TLB 0x00000108
	421	#define VCE_CMD_REG_WRITE 0x00000109
	422	#define VCE_CMD_REG_WAIT 0x0000010a
	423
	424	#define HEVC_ENC_CMD_NO_OP 0x00000000
	425	#define HEVC_ENC_CMD_END 0x00000001
	426	#define HEVC_ENC_CMD_FENCE 0x00000003
	427	#define HEVC_ENC_CMD_TRAP 0x00000004
	428	#define HEVC_ENC_CMD_IB_VM 0x00000102
	429	#define HEVC_ENC_CMD_REG_WRITE 0x00000109
	430	#define HEVC_ENC_CMD_REG_WAIT 0x0000010a
	431
	432	#endif