[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / amd / amdgpu / tonga_ih.c

/*
 * Copyright 2014 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#include "drmP.h"
#include "amdgpu.h"
#include "amdgpu_ih.h"
#include "vid.h"

#include "oss/oss_3_0_d.h"
#include "oss/oss_3_0_sh_mask.h"

#include "bif/bif_5_1_d.h"
#include "bif/bif_5_1_sh_mask.h"

/*
 * Interrupts
 * Starting with r6xx, interrupts are handled via a ring buffer.
 * Ring buffers are areas of GPU accessible memory that the GPU
 * writes interrupt vectors into and the host reads vectors out of.
 * There is a rptr (read pointer) that determines where the
 * host is currently reading, and a wptr (write pointer)
 * which determines where the GPU has written.  When the
 * pointers are equal, the ring is idle.  When the GPU
 * writes vectors to the ring buffer, it increments the
 * wptr.  When there is an interrupt, the host then starts
 * fetching commands and processing them until the pointers are
 * equal again at which point it updates the rptr.
 */

static void tonga_ih_set_interrupt_funcs(struct amdgpu_device *adev);

/**
 * tonga_ih_enable_interrupts - Enable the interrupt ring buffer
 *
 * @adev: amdgpu_device pointer
 *
 * Enable the interrupt ring buffer (VI).
 */
static void tonga_ih_enable_interrupts(struct amdgpu_device *adev)
{
	u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);

	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1);
	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
	adev->irq.ih.enabled = true;
}

/**
 * tonga_ih_disable_interrupts - Disable the interrupt ring buffer
 *
 * @adev: amdgpu_device pointer
 *
 * Disable the interrupt ring buffer (VI).
 */
static void tonga_ih_disable_interrupts(struct amdgpu_device *adev)
{
	u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);

	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);
	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0);
	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
	/* set rptr, wptr to 0 */
	WREG32(mmIH_RB_RPTR, 0);
	WREG32(mmIH_RB_WPTR, 0);
	adev->irq.ih.enabled = false;
	adev->irq.ih.rptr = 0;
}

/**
 * tonga_ih_irq_init - init and enable the interrupt ring
 *
 * @adev: amdgpu_device pointer
 *
 * Allocate a ring buffer for the interrupt controller,
 * enable the RLC, disable interrupts, enable the IH
 * ring buffer and enable it (VI).
 * Called at device load and reume.
 * Returns 0 for success, errors for failure.
 */
static int tonga_ih_irq_init(struct amdgpu_device *adev)
{
	int ret = 0;
	int rb_bufsz;
	u32 interrupt_cntl, ih_rb_cntl, ih_doorbell_rtpr;
	u64 wptr_off;

	/* disable irqs */
	tonga_ih_disable_interrupts(adev);

	/* setup interrupt control */
	WREG32(mmINTERRUPT_CNTL2, adev->dummy_page.addr >> 8);
	interrupt_cntl = RREG32(mmINTERRUPT_CNTL);
	/* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
	 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
	 */
	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
	/* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
	WREG32(mmINTERRUPT_CNTL, interrupt_cntl);

	/* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
	if (adev->irq.ih.use_bus_addr)
		WREG32(mmIH_RB_BASE, adev->irq.ih.rb_dma_addr >> 8);
	else
		WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);

	rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
	ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
	/* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */
	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);
	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);

	if (adev->irq.msi_enabled)
		ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 1);

	WREG32(mmIH_RB_CNTL, ih_rb_cntl);

	/* set the writeback address whether it's enabled or not */
	if (adev->irq.ih.use_bus_addr)
		wptr_off = adev->irq.ih.rb_dma_addr + (adev->irq.ih.wptr_offs * 4);
	else
		wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);
	WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));
	WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);

	/* set rptr, wptr to 0 */
	WREG32(mmIH_RB_RPTR, 0);
	WREG32(mmIH_RB_WPTR, 0);

	ih_doorbell_rtpr = RREG32(mmIH_DOORBELL_RPTR);
	if (adev->irq.ih.use_doorbell) {
		ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
						 OFFSET, adev->irq.ih.doorbell_index);
		ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
						 ENABLE, 1);
	} else {
		ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
						 ENABLE, 0);
	}
	WREG32(mmIH_DOORBELL_RPTR, ih_doorbell_rtpr);

	pci_set_master(adev->pdev);

	/* enable interrupts */
	tonga_ih_enable_interrupts(adev);

	return ret;
}

/**
 * tonga_ih_irq_disable - disable interrupts
 *
 * @adev: amdgpu_device pointer
 *
 * Disable interrupts on the hw (VI).
 */
static void tonga_ih_irq_disable(struct amdgpu_device *adev)
{
	tonga_ih_disable_interrupts(adev);

	/* Wait and acknowledge irq */
	mdelay(1);
}

/**
 * tonga_ih_get_wptr - get the IH ring buffer wptr
 *
 * @adev: amdgpu_device pointer
 *
 * Get the IH ring buffer wptr from either the register
 * or the writeback memory buffer (VI).  Also check for
 * ring buffer overflow and deal with it.
 * Used by cz_irq_process(VI).
 * Returns the value of the wptr.
 */
static u32 tonga_ih_get_wptr(struct amdgpu_device *adev)
{
	u32 wptr, tmp;

	if (adev->irq.ih.use_bus_addr)
		wptr = le32_to_cpu(adev->irq.ih.ring[adev->irq.ih.wptr_offs]);
	else
		wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);

	if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
		wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
		/* When a ring buffer overflow happen start parsing interrupt
		 * from the last not overwritten vector (wptr + 16). Hopefully
		 * this should allow us to catchup.
		 */
		dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
			wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask);
		adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask;
		tmp = RREG32(mmIH_RB_CNTL);
		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
		WREG32(mmIH_RB_CNTL, tmp);
	}
	return (wptr & adev->irq.ih.ptr_mask);
}

/**
 * tonga_ih_decode_iv - decode an interrupt vector
 *
 * @adev: amdgpu_device pointer
 *
 * Decodes the interrupt vector at the current rptr
 * position and also advance the position.
 */
static void tonga_ih_decode_iv(struct amdgpu_device *adev,
				 struct amdgpu_iv_entry *entry)
{
	/* wptr/rptr are in bytes! */
	u32 ring_index = adev->irq.ih.rptr >> 2;
	uint32_t dw[4];

	dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]);
	dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]);
	dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
	dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);

	entry->src_id = dw[0] & 0xff;
	entry->src_data = dw[1] & 0xfffffff;
	entry->ring_id = dw[2] & 0xff;
	entry->vm_id = (dw[2] >> 8) & 0xff;
	entry->pas_id = (dw[2] >> 16) & 0xffff;

	/* wptr/rptr are in bytes! */
	adev->irq.ih.rptr += 16;
}

/**
 * tonga_ih_set_rptr - set the IH ring buffer rptr
 *
 * @adev: amdgpu_device pointer
 *
 * Set the IH ring buffer rptr.
 */
static void tonga_ih_set_rptr(struct amdgpu_device *adev)
{
	if (adev->irq.ih.use_doorbell) {
		/* XXX check if swapping is necessary on BE */
		if (adev->irq.ih.use_bus_addr)
			adev->irq.ih.ring[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr;
		else
			adev->wb.wb[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr;
		WDOORBELL32(adev->irq.ih.doorbell_index, adev->irq.ih.rptr);
	} else {
		WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr);
	}
}

static int tonga_ih_early_init(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	tonga_ih_set_interrupt_funcs(adev);
	return 0;
}

static int tonga_ih_sw_init(void *handle)
{
	int r;
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	r = amdgpu_ih_ring_init(adev, 4 * 1024, true);
	if (r)
		return r;

	adev->irq.ih.use_doorbell = true;
	adev->irq.ih.doorbell_index = AMDGPU_DOORBELL_IH;

	r = amdgpu_irq_init(adev);

	return r;
}

static int tonga_ih_sw_fini(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	amdgpu_irq_fini(adev);
	amdgpu_ih_ring_fini(adev);

	return 0;
}

static int tonga_ih_hw_init(void *handle)
{
	int r;
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	r = tonga_ih_irq_init(adev);
	if (r)
		return r;

	return 0;
}

static int tonga_ih_hw_fini(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	tonga_ih_irq_disable(adev);

	return 0;
}

static int tonga_ih_suspend(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	return tonga_ih_hw_fini(adev);
}

static int tonga_ih_resume(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	return tonga_ih_hw_init(adev);
}

static bool tonga_ih_is_idle(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
	u32 tmp = RREG32(mmSRBM_STATUS);

	if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
		return false;

	return true;
}

static int tonga_ih_wait_for_idle(void *handle)
{
	unsigned i;
	u32 tmp;
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	for (i = 0; i < adev->usec_timeout; i++) {
		/* read MC_STATUS */
		tmp = RREG32(mmSRBM_STATUS);
		if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
			return 0;
		udelay(1);
	}
	return -ETIMEDOUT;
}

static void tonga_ih_print_status(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	dev_info(adev->dev, "TONGA IH registers\n");
	dev_info(adev->dev, "  SRBM_STATUS=0x%08X\n",
		RREG32(mmSRBM_STATUS));
	dev_info(adev->dev, "  SRBM_STATUS2=0x%08X\n",
		RREG32(mmSRBM_STATUS2));
	dev_info(adev->dev, "  INTERRUPT_CNTL=0x%08X\n",
		 RREG32(mmINTERRUPT_CNTL));
	dev_info(adev->dev, "  INTERRUPT_CNTL2=0x%08X\n",
		 RREG32(mmINTERRUPT_CNTL2));
	dev_info(adev->dev, "  IH_CNTL=0x%08X\n",
		 RREG32(mmIH_CNTL));
	dev_info(adev->dev, "  IH_RB_CNTL=0x%08X\n",
		 RREG32(mmIH_RB_CNTL));
	dev_info(adev->dev, "  IH_RB_BASE=0x%08X\n",
		 RREG32(mmIH_RB_BASE));
	dev_info(adev->dev, "  IH_RB_WPTR_ADDR_LO=0x%08X\n",
		 RREG32(mmIH_RB_WPTR_ADDR_LO));
	dev_info(adev->dev, "  IH_RB_WPTR_ADDR_HI=0x%08X\n",
		 RREG32(mmIH_RB_WPTR_ADDR_HI));
	dev_info(adev->dev, "  IH_RB_RPTR=0x%08X\n",
		 RREG32(mmIH_RB_RPTR));
	dev_info(adev->dev, "  IH_RB_WPTR=0x%08X\n",
		 RREG32(mmIH_RB_WPTR));
}

static int tonga_ih_soft_reset(void *handle)
{
	u32 srbm_soft_reset = 0;
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
	u32 tmp = RREG32(mmSRBM_STATUS);

	if (tmp & SRBM_STATUS__IH_BUSY_MASK)
		srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET,
						SOFT_RESET_IH, 1);

	if (srbm_soft_reset) {
		tonga_ih_print_status(adev);

		tmp = RREG32(mmSRBM_SOFT_RESET);
		tmp |= srbm_soft_reset;
		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
		WREG32(mmSRBM_SOFT_RESET, tmp);
		tmp = RREG32(mmSRBM_SOFT_RESET);

		udelay(50);

		tmp &= ~srbm_soft_reset;
		WREG32(mmSRBM_SOFT_RESET, tmp);
		tmp = RREG32(mmSRBM_SOFT_RESET);

		/* Wait a little for things to settle down */
		udelay(50);

		tonga_ih_print_status(adev);
	}

	return 0;
}

static int tonga_ih_set_clockgating_state(void *handle,
					  enum amd_clockgating_state state)
{
	return 0;
}

static int tonga_ih_set_powergating_state(void *handle,
					  enum amd_powergating_state state)
{
	return 0;
}

const struct amd_ip_funcs tonga_ih_ip_funcs = {
	.early_init = tonga_ih_early_init,
	.late_init = NULL,
	.sw_init = tonga_ih_sw_init,
	.sw_fini = tonga_ih_sw_fini,
	.hw_init = tonga_ih_hw_init,
	.hw_fini = tonga_ih_hw_fini,
	.suspend = tonga_ih_suspend,
	.resume = tonga_ih_resume,
	.is_idle = tonga_ih_is_idle,
	.wait_for_idle = tonga_ih_wait_for_idle,
	.soft_reset = tonga_ih_soft_reset,
	.print_status = tonga_ih_print_status,
	.set_clockgating_state = tonga_ih_set_clockgating_state,
	.set_powergating_state = tonga_ih_set_powergating_state,
};

static const struct amdgpu_ih_funcs tonga_ih_funcs = {
	.get_wptr = tonga_ih_get_wptr,
	.decode_iv = tonga_ih_decode_iv,
	.set_rptr = tonga_ih_set_rptr
};

static void tonga_ih_set_interrupt_funcs(struct amdgpu_device *adev)
{
	if (adev->irq.ih_funcs == NULL)
		adev->irq.ih_funcs = &tonga_ih_funcs;
}
Commit	Line	Data
aaa36a97 AD	1	/*
	2	* Copyright 2014 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23	#include "drmP.h"
	24	#include "amdgpu.h"
	25	#include "amdgpu_ih.h"
	26	#include "vid.h"
	27
	28	#include "oss/oss_3_0_d.h"
	29	#include "oss/oss_3_0_sh_mask.h"
	30
	31	#include "bif/bif_5_1_d.h"
	32	#include "bif/bif_5_1_sh_mask.h"
	33
	34	/*
	35	* Interrupts
	36	* Starting with r6xx, interrupts are handled via a ring buffer.
	37	* Ring buffers are areas of GPU accessible memory that the GPU
	38	* writes interrupt vectors into and the host reads vectors out of.
	39	* There is a rptr (read pointer) that determines where the
	40	* host is currently reading, and a wptr (write pointer)
	41	* which determines where the GPU has written. When the
	42	* pointers are equal, the ring is idle. When the GPU
	43	* writes vectors to the ring buffer, it increments the
	44	* wptr. When there is an interrupt, the host then starts
	45	* fetching commands and processing them until the pointers are
	46	* equal again at which point it updates the rptr.
	47	*/
	48
	49	static void tonga_ih_set_interrupt_funcs(struct amdgpu_device *adev);
	50
	51	/**
	52	* tonga_ih_enable_interrupts - Enable the interrupt ring buffer
	53	*
	54	* @adev: amdgpu_device pointer
	55	*
	56	* Enable the interrupt ring buffer (VI).
	57	*/
	58	static void tonga_ih_enable_interrupts(struct amdgpu_device *adev)
	59	{
	60	u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
	61
	62	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
	63	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1);
	64	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
65	adev->irq.ih.enabled = true;
66	}
67
68	/**
69	* tonga_ih_disable_interrupts - Disable the interrupt ring buffer
70	*
71	* @adev: amdgpu_device pointer
72	*
73	* Disable the interrupt ring buffer (VI).
74	*/
75	static void tonga_ih_disable_interrupts(struct amdgpu_device *adev)
76	{
77	u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
78
79	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);
80	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0);
81	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
82	/* set rptr, wptr to 0 */
83	WREG32(mmIH_RB_RPTR, 0);
84	WREG32(mmIH_RB_WPTR, 0);
85	adev->irq.ih.enabled = false;
86	adev->irq.ih.rptr = 0;
87	}
88
89	/**
90	* tonga_ih_irq_init - init and enable the interrupt ring
91	*
92	* @adev: amdgpu_device pointer
93	*
94	* Allocate a ring buffer for the interrupt controller,
95	* enable the RLC, disable interrupts, enable the IH
96	* ring buffer and enable it (VI).
97	* Called at device load and reume.
98	* Returns 0 for success, errors for failure.
99	*/
100	static int tonga_ih_irq_init(struct amdgpu_device *adev)
101	{
102	int ret = 0;
103	int rb_bufsz;
104	u32 interrupt_cntl, ih_rb_cntl, ih_doorbell_rtpr;
105	u64 wptr_off;
106
107	/* disable irqs */
108	tonga_ih_disable_interrupts(adev);
109
110	/* setup interrupt control */
111	WREG32(mmINTERRUPT_CNTL2, adev->dummy_page.addr >> 8);
112	interrupt_cntl = RREG32(mmINTERRUPT_CNTL);
113	/* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
114	* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
115	*/
116	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
117	/* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
118	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
119	WREG32(mmINTERRUPT_CNTL, interrupt_cntl);
120
121	/* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
122	if (adev->irq.ih.use_bus_addr)
123	WREG32(mmIH_RB_BASE, adev->irq.ih.rb_dma_addr >> 8);
124	else
125	WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);
126
127	rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
128	ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
129	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
130	/* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */
131	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);
132	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);
133
134	if (adev->irq.msi_enabled)
135	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 1);
136
137	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
138
139	/* set the writeback address whether it's enabled or not */
140	if (adev->irq.ih.use_bus_addr)
141	wptr_off = adev->irq.ih.rb_dma_addr + (adev->irq.ih.wptr_offs * 4);
142	else
143	wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);
144	WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));
145	WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);
146
147	/* set rptr, wptr to 0 */
148	WREG32(mmIH_RB_RPTR, 0);
149	WREG32(mmIH_RB_WPTR, 0);
150
151	ih_doorbell_rtpr = RREG32(mmIH_DOORBELL_RPTR);
152	if (adev->irq.ih.use_doorbell) {
153	ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
154	OFFSET, adev->irq.ih.doorbell_index);
155	ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
156	ENABLE, 1);
157	} else {
158	ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
159	ENABLE, 0);
160	}
161	WREG32(mmIH_DOORBELL_RPTR, ih_doorbell_rtpr);
162
163	pci_set_master(adev->pdev);
164
165	/* enable interrupts */
166	tonga_ih_enable_interrupts(adev);
167
168	return ret;
169	}
170
171	/**
172	* tonga_ih_irq_disable - disable interrupts
173	*
174	* @adev: amdgpu_device pointer
175	*
176	* Disable interrupts on the hw (VI).
177	*/
178	static void tonga_ih_irq_disable(struct amdgpu_device *adev)
179	{
180	tonga_ih_disable_interrupts(adev);
181
182	/* Wait and acknowledge irq */
183	mdelay(1);
184	}
185
186	/**
187	* tonga_ih_get_wptr - get the IH ring buffer wptr
188	*
189	* @adev: amdgpu_device pointer
190	*
191	* Get the IH ring buffer wptr from either the register
192	* or the writeback memory buffer (VI). Also check for
193	* ring buffer overflow and deal with it.
194	* Used by cz_irq_process(VI).
195	* Returns the value of the wptr.
196	*/
197	static u32 tonga_ih_get_wptr(struct amdgpu_device *adev)
198	{
199	u32 wptr, tmp;
200
201	if (adev->irq.ih.use_bus_addr)
202	wptr = le32_to_cpu(adev->irq.ih.ring[adev->irq.ih.wptr_offs]);
203	else
204	wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);
205
206	if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
207	wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
208	/* When a ring buffer overflow happen start parsing interrupt
209	* from the last not overwritten vector (wptr + 16). Hopefully
210	* this should allow us to catchup.
211	*/
212	dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
213	wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask);
214	adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask;
215	tmp = RREG32(mmIH_RB_CNTL);
216	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
217	WREG32(mmIH_RB_CNTL, tmp);
218	}
219	return (wptr & adev->irq.ih.ptr_mask);
220	}
221
222	/**
223	* tonga_ih_decode_iv - decode an interrupt vector
224	*
225	* @adev: amdgpu_device pointer
226	*
227	* Decodes the interrupt vector at the current rptr
228	* position and also advance the position.
229	*/
230	static void tonga_ih_decode_iv(struct amdgpu_device *adev,
231	struct amdgpu_iv_entry *entry)
232	{
233	/* wptr/rptr are in bytes! */
234	u32 ring_index = adev->irq.ih.rptr >> 2;
235	uint32_t dw[4];
236
237	dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]);
238	dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]);
239	dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
240	dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);
241
242	entry->src_id = dw[0] & 0xff;
243	entry->src_data = dw[1] & 0xfffffff;
244	entry->ring_id = dw[2] & 0xff;
245	entry->vm_id = (dw[2] >> 8) & 0xff;
246	entry->pas_id = (dw[2] >> 16) & 0xffff;
247
248	/* wptr/rptr are in bytes! */
249	adev->irq.ih.rptr += 16;
250	}
251
252	/**
253	* tonga_ih_set_rptr - set the IH ring buffer rptr
254	*
255	* @adev: amdgpu_device pointer
256	*
257	* Set the IH ring buffer rptr.
258	*/
259	static void tonga_ih_set_rptr(struct amdgpu_device *adev)
260	{
261	if (adev->irq.ih.use_doorbell) {
262	/* XXX check if swapping is necessary on BE */
263	if (adev->irq.ih.use_bus_addr)
264	adev->irq.ih.ring[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr;
265	else
266	adev->wb.wb[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr;
267	WDOORBELL32(adev->irq.ih.doorbell_index, adev->irq.ih.rptr);
268	} else {
269	WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr);
270	}
271	}
272
5fc3aeeb	273	static int tonga_ih_early_init(void *handle)
aaa36a97	274	{
5fc3aeeb	275	struct amdgpu_device adev = (struct amdgpu_device )handle;
5fc3aeeb	276
aaa36a97 AD	277	tonga_ih_set_interrupt_funcs(adev);
	278	return 0;
	279	}
	280
5fc3aeeb	281	static int tonga_ih_sw_init(void *handle)
aaa36a97 AD	282	{
aaa36a97 AD	283	int r;
5fc3aeeb	284	struct amdgpu_device adev = (struct amdgpu_device )handle;
aaa36a97 AD	285
	286	r = amdgpu_ih_ring_init(adev, 4 * 1024, true);
	287	if (r)
	288	return r;
	289
	290	adev->irq.ih.use_doorbell = true;
	291	adev->irq.ih.doorbell_index = AMDGPU_DOORBELL_IH;
	292
	293	r = amdgpu_irq_init(adev);
	294
	295	return r;
	296	}
	297
5fc3aeeb	298	static int tonga_ih_sw_fini(void *handle)
aaa36a97	299	{
5fc3aeeb	300	struct amdgpu_device adev = (struct amdgpu_device )handle;
5fc3aeeb	301
aaa36a97 AD	302	amdgpu_irq_fini(adev);
	303	amdgpu_ih_ring_fini(adev);
	304
	305	return 0;
	306	}
	307
5fc3aeeb	308	static int tonga_ih_hw_init(void *handle)
aaa36a97 AD	309	{
aaa36a97 AD	310	int r;
5fc3aeeb	311	struct amdgpu_device adev = (struct amdgpu_device )handle;
aaa36a97 AD	312
	313	r = tonga_ih_irq_init(adev);
	314	if (r)
	315	return r;
	316
	317	return 0;
	318	}
	319
5fc3aeeb	320	static int tonga_ih_hw_fini(void *handle)
aaa36a97	321	{
5fc3aeeb	322	struct amdgpu_device adev = (struct amdgpu_device )handle;
5fc3aeeb	323
aaa36a97 AD	324	tonga_ih_irq_disable(adev);
	325
	326	return 0;
	327	}
	328
5fc3aeeb	329	static int tonga_ih_suspend(void *handle)
aaa36a97	330	{
5fc3aeeb	331	struct amdgpu_device adev = (struct amdgpu_device )handle;
5fc3aeeb	332
aaa36a97 AD	333	return tonga_ih_hw_fini(adev);
	334	}
	335
5fc3aeeb	336	static int tonga_ih_resume(void *handle)
aaa36a97	337	{
5fc3aeeb	338	struct amdgpu_device adev = (struct amdgpu_device )handle;
5fc3aeeb	339
aaa36a97 AD	340	return tonga_ih_hw_init(adev);
	341	}
	342
5fc3aeeb	343	static bool tonga_ih_is_idle(void *handle)
aaa36a97	344	{
5fc3aeeb	345	struct amdgpu_device adev = (struct amdgpu_device )handle;
aaa36a97 AD	346	u32 tmp = RREG32(mmSRBM_STATUS);
	347
	348	if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
	349	return false;
	350
	351	return true;
	352	}
	353
5fc3aeeb	354	static int tonga_ih_wait_for_idle(void *handle)
aaa36a97 AD	355	{
	356	unsigned i;
	357	u32 tmp;
5fc3aeeb	358	struct amdgpu_device adev = (struct amdgpu_device )handle;
aaa36a97 AD	359
	360	for (i = 0; i < adev->usec_timeout; i++) {
	361	/* read MC_STATUS */
	362	tmp = RREG32(mmSRBM_STATUS);
	363	if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
	364	return 0;
	365	udelay(1);
	366	}
	367	return -ETIMEDOUT;
	368	}
	369
5fc3aeeb	370	static void tonga_ih_print_status(void *handle)
aaa36a97	371	{
5fc3aeeb	372	struct amdgpu_device adev = (struct amdgpu_device )handle;
5fc3aeeb	373
aaa36a97 AD	374	dev_info(adev->dev, "TONGA IH registers\n");
	375	dev_info(adev->dev, " SRBM_STATUS=0x%08X\n",
	376	RREG32(mmSRBM_STATUS));
	377	dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
	378	RREG32(mmSRBM_STATUS2));
	379	dev_info(adev->dev, " INTERRUPT_CNTL=0x%08X\n",
	380	RREG32(mmINTERRUPT_CNTL));
	381	dev_info(adev->dev, " INTERRUPT_CNTL2=0x%08X\n",
	382	RREG32(mmINTERRUPT_CNTL2));
	383	dev_info(adev->dev, " IH_CNTL=0x%08X\n",
	384	RREG32(mmIH_CNTL));
	385	dev_info(adev->dev, " IH_RB_CNTL=0x%08X\n",
	386	RREG32(mmIH_RB_CNTL));
	387	dev_info(adev->dev, " IH_RB_BASE=0x%08X\n",
	388	RREG32(mmIH_RB_BASE));
	389	dev_info(adev->dev, " IH_RB_WPTR_ADDR_LO=0x%08X\n",
	390	RREG32(mmIH_RB_WPTR_ADDR_LO));
	391	dev_info(adev->dev, " IH_RB_WPTR_ADDR_HI=0x%08X\n",
	392	RREG32(mmIH_RB_WPTR_ADDR_HI));
	393	dev_info(adev->dev, " IH_RB_RPTR=0x%08X\n",
	394	RREG32(mmIH_RB_RPTR));
	395	dev_info(adev->dev, " IH_RB_WPTR=0x%08X\n",
	396	RREG32(mmIH_RB_WPTR));
	397	}
	398
5fc3aeeb	399	static int tonga_ih_soft_reset(void *handle)
aaa36a97 AD	400	{
aaa36a97 AD	401	u32 srbm_soft_reset = 0;
5fc3aeeb	402	struct amdgpu_device adev = (struct amdgpu_device )handle;
aaa36a97 AD	403	u32 tmp = RREG32(mmSRBM_STATUS);
	404
	405	if (tmp & SRBM_STATUS__IH_BUSY_MASK)
	406	srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET,
	407	SOFT_RESET_IH, 1);
	408
	409	if (srbm_soft_reset) {
	410	tonga_ih_print_status(adev);
	411
	412	tmp = RREG32(mmSRBM_SOFT_RESET);
	413	tmp \|= srbm_soft_reset;
	414	dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
	415	WREG32(mmSRBM_SOFT_RESET, tmp);
	416	tmp = RREG32(mmSRBM_SOFT_RESET);
	417
	418	udelay(50);
	419
	420	tmp &= ~srbm_soft_reset;
	421	WREG32(mmSRBM_SOFT_RESET, tmp);
	422	tmp = RREG32(mmSRBM_SOFT_RESET);
	423
	424	/* Wait a little for things to settle down */
	425	udelay(50);
	426
	427	tonga_ih_print_status(adev);
	428	}
	429
	430	return 0;
	431	}
	432
5fc3aeeb	433	static int tonga_ih_set_clockgating_state(void *handle,
5fc3aeeb	434	enum amd_clockgating_state state)
aaa36a97	435	{
aaa36a97 AD	436	return 0;
	437	}
	438
5fc3aeeb	439	static int tonga_ih_set_powergating_state(void *handle,
5fc3aeeb	440	enum amd_powergating_state state)
aaa36a97	441	{
aaa36a97 AD	442	return 0;
	443	}
	444
5fc3aeeb	445	const struct amd_ip_funcs tonga_ih_ip_funcs = {
aaa36a97 AD	446	.early_init = tonga_ih_early_init,
	447	.late_init = NULL,
	448	.sw_init = tonga_ih_sw_init,
	449	.sw_fini = tonga_ih_sw_fini,
	450	.hw_init = tonga_ih_hw_init,
	451	.hw_fini = tonga_ih_hw_fini,
	452	.suspend = tonga_ih_suspend,
	453	.resume = tonga_ih_resume,
	454	.is_idle = tonga_ih_is_idle,
	455	.wait_for_idle = tonga_ih_wait_for_idle,
	456	.soft_reset = tonga_ih_soft_reset,
	457	.print_status = tonga_ih_print_status,
	458	.set_clockgating_state = tonga_ih_set_clockgating_state,
	459	.set_powergating_state = tonga_ih_set_powergating_state,
	460	};
	461
	462	static const struct amdgpu_ih_funcs tonga_ih_funcs = {
	463	.get_wptr = tonga_ih_get_wptr,
	464	.decode_iv = tonga_ih_decode_iv,
	465	.set_rptr = tonga_ih_set_rptr
	466	};
	467
	468	static void tonga_ih_set_interrupt_funcs(struct amdgpu_device *adev)
	469	{
	470	if (adev->irq.ih_funcs == NULL)
	471	adev->irq.ih_funcs = &tonga_ih_funcs;
	472	}
	473