[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / amdgpu / tonga_ih.c

/*
 * Copyright 2014 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#include <drm/drmP.h>
#include "amdgpu.h"
#include "amdgpu_ih.h"
#include "vid.h"

#include "oss/oss_3_0_d.h"
#include "oss/oss_3_0_sh_mask.h"

#include "bif/bif_5_1_d.h"
#include "bif/bif_5_1_sh_mask.h"

/*
 * Interrupts
 * Starting with r6xx, interrupts are handled via a ring buffer.
 * Ring buffers are areas of GPU accessible memory that the GPU
 * writes interrupt vectors into and the host reads vectors out of.
 * There is a rptr (read pointer) that determines where the
 * host is currently reading, and a wptr (write pointer)
 * which determines where the GPU has written.  When the
 * pointers are equal, the ring is idle.  When the GPU
 * writes vectors to the ring buffer, it increments the
 * wptr.  When there is an interrupt, the host then starts
 * fetching commands and processing them until the pointers are
 * equal again at which point it updates the rptr.
 */

static void tonga_ih_set_interrupt_funcs(struct amdgpu_device *adev);

/**
 * tonga_ih_enable_interrupts - Enable the interrupt ring buffer
 *
 * @adev: amdgpu_device pointer
 *
 * Enable the interrupt ring buffer (VI).
 */
static void tonga_ih_enable_interrupts(struct amdgpu_device *adev)
{
	u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);

	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1);
	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
	adev->irq.ih.enabled = true;
}

/**
 * tonga_ih_disable_interrupts - Disable the interrupt ring buffer
 *
 * @adev: amdgpu_device pointer
 *
 * Disable the interrupt ring buffer (VI).
 */
static void tonga_ih_disable_interrupts(struct amdgpu_device *adev)
{
	u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);

	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);
	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0);
	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
	/* set rptr, wptr to 0 */
	WREG32(mmIH_RB_RPTR, 0);
	WREG32(mmIH_RB_WPTR, 0);
	adev->irq.ih.enabled = false;
	adev->irq.ih.rptr = 0;
}

/**
 * tonga_ih_irq_init - init and enable the interrupt ring
 *
 * @adev: amdgpu_device pointer
 *
 * Allocate a ring buffer for the interrupt controller,
 * enable the RLC, disable interrupts, enable the IH
 * ring buffer and enable it (VI).
 * Called at device load and reume.
 * Returns 0 for success, errors for failure.
 */
static int tonga_ih_irq_init(struct amdgpu_device *adev)
{
	int rb_bufsz;
	u32 interrupt_cntl, ih_rb_cntl, ih_doorbell_rtpr;
	u64 wptr_off;

	/* disable irqs */
	tonga_ih_disable_interrupts(adev);

	/* setup interrupt control */
	WREG32(mmINTERRUPT_CNTL2, adev->dummy_page.addr >> 8);
	interrupt_cntl = RREG32(mmINTERRUPT_CNTL);
	/* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
	 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
	 */
	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
	/* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
	WREG32(mmINTERRUPT_CNTL, interrupt_cntl);

	/* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
	if (adev->irq.ih.use_bus_addr)
		WREG32(mmIH_RB_BASE, adev->irq.ih.rb_dma_addr >> 8);
	else
		WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);

	rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
	ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
	/* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */
	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);
	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);

	if (adev->irq.msi_enabled)
		ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 1);

	WREG32(mmIH_RB_CNTL, ih_rb_cntl);

	/* set the writeback address whether it's enabled or not */
	if (adev->irq.ih.use_bus_addr)
		wptr_off = adev->irq.ih.rb_dma_addr + (adev->irq.ih.wptr_offs * 4);
	else
		wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);
	WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));
	WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);

	/* set rptr, wptr to 0 */
	WREG32(mmIH_RB_RPTR, 0);
	WREG32(mmIH_RB_WPTR, 0);

	ih_doorbell_rtpr = RREG32(mmIH_DOORBELL_RPTR);
	if (adev->irq.ih.use_doorbell) {
		ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
						 OFFSET, adev->irq.ih.doorbell_index);
		ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
						 ENABLE, 1);
	} else {
		ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
						 ENABLE, 0);
	}
	WREG32(mmIH_DOORBELL_RPTR, ih_doorbell_rtpr);

	pci_set_master(adev->pdev);

	/* enable interrupts */
	tonga_ih_enable_interrupts(adev);

	return 0;
}

/**
 * tonga_ih_irq_disable - disable interrupts
 *
 * @adev: amdgpu_device pointer
 *
 * Disable interrupts on the hw (VI).
 */
static void tonga_ih_irq_disable(struct amdgpu_device *adev)
{
	tonga_ih_disable_interrupts(adev);

	/* Wait and acknowledge irq */
	mdelay(1);
}

/**
 * tonga_ih_get_wptr - get the IH ring buffer wptr
 *
 * @adev: amdgpu_device pointer
 *
 * Get the IH ring buffer wptr from either the register
 * or the writeback memory buffer (VI).  Also check for
 * ring buffer overflow and deal with it.
 * Used by cz_irq_process(VI).
 * Returns the value of the wptr.
 */
static u32 tonga_ih_get_wptr(struct amdgpu_device *adev)
{
	u32 wptr, tmp;

	if (adev->irq.ih.use_bus_addr)
		wptr = le32_to_cpu(adev->irq.ih.ring[adev->irq.ih.wptr_offs]);
	else
		wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);

	if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
		wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
		/* When a ring buffer overflow happen start parsing interrupt
		 * from the last not overwritten vector (wptr + 16). Hopefully
		 * this should allow us to catchup.
		 */
		dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
			wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask);
		adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask;
		tmp = RREG32(mmIH_RB_CNTL);
		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
		WREG32(mmIH_RB_CNTL, tmp);
	}
	return (wptr & adev->irq.ih.ptr_mask);
}

/**
 * tonga_ih_decode_iv - decode an interrupt vector
 *
 * @adev: amdgpu_device pointer
 *
 * Decodes the interrupt vector at the current rptr
 * position and also advance the position.
 */
static void tonga_ih_decode_iv(struct amdgpu_device *adev,
				 struct amdgpu_iv_entry *entry)
{
	/* wptr/rptr are in bytes! */
	u32 ring_index = adev->irq.ih.rptr >> 2;
	uint32_t dw[4];

	dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]);
	dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]);
	dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
	dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);

	entry->client_id = AMDGPU_IH_CLIENTID_LEGACY;
	entry->src_id = dw[0] & 0xff;
	entry->src_data[0] = dw[1] & 0xfffffff;
	entry->ring_id = dw[2] & 0xff;
	entry->vm_id = (dw[2] >> 8) & 0xff;
	entry->pas_id = (dw[2] >> 16) & 0xffff;

	/* wptr/rptr are in bytes! */
	adev->irq.ih.rptr += 16;
}

/**
 * tonga_ih_set_rptr - set the IH ring buffer rptr
 *
 * @adev: amdgpu_device pointer
 *
 * Set the IH ring buffer rptr.
 */
static void tonga_ih_set_rptr(struct amdgpu_device *adev)
{
	if (adev->irq.ih.use_doorbell) {
		/* XXX check if swapping is necessary on BE */
		if (adev->irq.ih.use_bus_addr)
			adev->irq.ih.ring[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr;
		else
			adev->wb.wb[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr;
		WDOORBELL32(adev->irq.ih.doorbell_index, adev->irq.ih.rptr);
	} else {
		WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr);
	}
}

static int tonga_ih_early_init(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
	int ret;

	ret = amdgpu_irq_add_domain(adev);
	if (ret)
		return ret;

	tonga_ih_set_interrupt_funcs(adev);

	return 0;
}

static int tonga_ih_sw_init(void *handle)
{
	int r;
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	r = amdgpu_ih_ring_init(adev, 64 * 1024, true);
	if (r)
		return r;

	adev->irq.ih.use_doorbell = true;
	adev->irq.ih.doorbell_index = AMDGPU_DOORBELL_IH;

	r = amdgpu_irq_init(adev);

	return r;
}

static int tonga_ih_sw_fini(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	amdgpu_irq_fini(adev);
	amdgpu_ih_ring_fini(adev);
	amdgpu_irq_remove_domain(adev);

	return 0;
}

static int tonga_ih_hw_init(void *handle)
{
	int r;
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	r = tonga_ih_irq_init(adev);
	if (r)
		return r;

	return 0;
}

static int tonga_ih_hw_fini(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	tonga_ih_irq_disable(adev);

	return 0;
}

static int tonga_ih_suspend(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	return tonga_ih_hw_fini(adev);
}

static int tonga_ih_resume(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	return tonga_ih_hw_init(adev);
}

static bool tonga_ih_is_idle(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
	u32 tmp = RREG32(mmSRBM_STATUS);

	if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
		return false;

	return true;
}

static int tonga_ih_wait_for_idle(void *handle)
{
	unsigned i;
	u32 tmp;
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	for (i = 0; i < adev->usec_timeout; i++) {
		/* read MC_STATUS */
		tmp = RREG32(mmSRBM_STATUS);
		if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
			return 0;
		udelay(1);
	}
	return -ETIMEDOUT;
}

static bool tonga_ih_check_soft_reset(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
	u32 srbm_soft_reset = 0;
	u32 tmp = RREG32(mmSRBM_STATUS);

	if (tmp & SRBM_STATUS__IH_BUSY_MASK)
		srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET,
						SOFT_RESET_IH, 1);

	if (srbm_soft_reset) {
		adev->irq.srbm_soft_reset = srbm_soft_reset;
		return true;
	} else {
		adev->irq.srbm_soft_reset = 0;
		return false;
	}
}

static int tonga_ih_pre_soft_reset(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	if (!adev->irq.srbm_soft_reset)
		return 0;

	return tonga_ih_hw_fini(adev);
}

static int tonga_ih_post_soft_reset(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	if (!adev->irq.srbm_soft_reset)
		return 0;

	return tonga_ih_hw_init(adev);
}

static int tonga_ih_soft_reset(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
	u32 srbm_soft_reset;

	if (!adev->irq.srbm_soft_reset)
		return 0;
	srbm_soft_reset = adev->irq.srbm_soft_reset;

	if (srbm_soft_reset) {
		u32 tmp;

		tmp = RREG32(mmSRBM_SOFT_RESET);
		tmp |= srbm_soft_reset;
		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
		WREG32(mmSRBM_SOFT_RESET, tmp);
		tmp = RREG32(mmSRBM_SOFT_RESET);

		udelay(50);

		tmp &= ~srbm_soft_reset;
		WREG32(mmSRBM_SOFT_RESET, tmp);
		tmp = RREG32(mmSRBM_SOFT_RESET);

		/* Wait a little for things to settle down */
		udelay(50);
	}

	return 0;
}

static int tonga_ih_set_clockgating_state(void *handle,
					  enum amd_clockgating_state state)
{
	return 0;
}

static int tonga_ih_set_powergating_state(void *handle,
					  enum amd_powergating_state state)
{
	return 0;
}

static const struct amd_ip_funcs tonga_ih_ip_funcs = {
	.name = "tonga_ih",
	.early_init = tonga_ih_early_init,
	.late_init = NULL,
	.sw_init = tonga_ih_sw_init,
	.sw_fini = tonga_ih_sw_fini,
	.hw_init = tonga_ih_hw_init,
	.hw_fini = tonga_ih_hw_fini,
	.suspend = tonga_ih_suspend,
	.resume = tonga_ih_resume,
	.is_idle = tonga_ih_is_idle,
	.wait_for_idle = tonga_ih_wait_for_idle,
	.check_soft_reset = tonga_ih_check_soft_reset,
	.pre_soft_reset = tonga_ih_pre_soft_reset,
	.soft_reset = tonga_ih_soft_reset,
	.post_soft_reset = tonga_ih_post_soft_reset,
	.set_clockgating_state = tonga_ih_set_clockgating_state,
	.set_powergating_state = tonga_ih_set_powergating_state,
};

static const struct amdgpu_ih_funcs tonga_ih_funcs = {
	.get_wptr = tonga_ih_get_wptr,
	.decode_iv = tonga_ih_decode_iv,
	.set_rptr = tonga_ih_set_rptr
};

static void tonga_ih_set_interrupt_funcs(struct amdgpu_device *adev)
{
	if (adev->irq.ih_funcs == NULL)
		adev->irq.ih_funcs = &tonga_ih_funcs;
}

const struct amdgpu_ip_block_version tonga_ih_ip_block =
{
	.type = AMD_IP_BLOCK_TYPE_IH,
	.major = 3,
	.minor = 0,
	.rev = 0,
	.funcs = &tonga_ih_ip_funcs,
};
Commit	Line	Data
aaa36a97 AD	1	/*
	2	* Copyright 2014 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
248a1d6f	23	#include <drm/drmP.h>
aaa36a97 AD	24	#include "amdgpu.h"
	25	#include "amdgpu_ih.h"
	26	#include "vid.h"
	27
	28	#include "oss/oss_3_0_d.h"
	29	#include "oss/oss_3_0_sh_mask.h"
	30
	31	#include "bif/bif_5_1_d.h"
	32	#include "bif/bif_5_1_sh_mask.h"
	33
	34	/*
	35	* Interrupts
	36	* Starting with r6xx, interrupts are handled via a ring buffer.
	37	* Ring buffers are areas of GPU accessible memory that the GPU
	38	* writes interrupt vectors into and the host reads vectors out of.
	39	* There is a rptr (read pointer) that determines where the
	40	* host is currently reading, and a wptr (write pointer)
	41	* which determines where the GPU has written. When the
	42	* pointers are equal, the ring is idle. When the GPU
	43	* writes vectors to the ring buffer, it increments the
	44	* wptr. When there is an interrupt, the host then starts
	45	* fetching commands and processing them until the pointers are
	46	* equal again at which point it updates the rptr.
	47	*/
	48
	49	static void tonga_ih_set_interrupt_funcs(struct amdgpu_device *adev);
	50
	51	/**
	52	* tonga_ih_enable_interrupts - Enable the interrupt ring buffer
	53	*
	54	* @adev: amdgpu_device pointer
	55	*
	56	* Enable the interrupt ring buffer (VI).
	57	*/
	58	static void tonga_ih_enable_interrupts(struct amdgpu_device *adev)
	59	{
	60	u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
	61
	62	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
	63	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1);
	64	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
	65	adev->irq.ih.enabled = true;
	66	}
	67
	68	/**
	69	* tonga_ih_disable_interrupts - Disable the interrupt ring buffer
	70	*
	71	* @adev: amdgpu_device pointer
	72	*
	73	* Disable the interrupt ring buffer (VI).
	74	*/
	75	static void tonga_ih_disable_interrupts(struct amdgpu_device *adev)
	76	{
	77	u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
	78
	79	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);
	80	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0);
	81	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
	82	/* set rptr, wptr to 0 */
	83	WREG32(mmIH_RB_RPTR, 0);
	84	WREG32(mmIH_RB_WPTR, 0);
	85	adev->irq.ih.enabled = false;
	86	adev->irq.ih.rptr = 0;
	87	}
88
89	/**
90	* tonga_ih_irq_init - init and enable the interrupt ring
91	*
92	* @adev: amdgpu_device pointer
93	*
94	* Allocate a ring buffer for the interrupt controller,
95	* enable the RLC, disable interrupts, enable the IH
96	* ring buffer and enable it (VI).
97	* Called at device load and reume.
98	* Returns 0 for success, errors for failure.
99	*/
100	static int tonga_ih_irq_init(struct amdgpu_device *adev)
101	{
aaa36a97 AD	102	int rb_bufsz;
	103	u32 interrupt_cntl, ih_rb_cntl, ih_doorbell_rtpr;
	104	u64 wptr_off;
	105
	106	/* disable irqs */
	107	tonga_ih_disable_interrupts(adev);
	108
	109	/* setup interrupt control */
	110	WREG32(mmINTERRUPT_CNTL2, adev->dummy_page.addr >> 8);
	111	interrupt_cntl = RREG32(mmINTERRUPT_CNTL);
	112	/* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
	113	* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
	114	*/
	115	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
	116	/* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
	117	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
	118	WREG32(mmINTERRUPT_CNTL, interrupt_cntl);
	119
	120	/* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
	121	if (adev->irq.ih.use_bus_addr)
	122	WREG32(mmIH_RB_BASE, adev->irq.ih.rb_dma_addr >> 8);
	123	else
	124	WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);
	125
	126	rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
	127	ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
	128	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
	129	/* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */
	130	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);
	131	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);
	132
	133	if (adev->irq.msi_enabled)
	134	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 1);
	135
	136	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
	137
	138	/* set the writeback address whether it's enabled or not */
	139	if (adev->irq.ih.use_bus_addr)
	140	wptr_off = adev->irq.ih.rb_dma_addr + (adev->irq.ih.wptr_offs * 4);
	141	else
	142	wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);
	143	WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));
	144	WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);
	145
	146	/* set rptr, wptr to 0 */
	147	WREG32(mmIH_RB_RPTR, 0);
	148	WREG32(mmIH_RB_WPTR, 0);
	149
	150	ih_doorbell_rtpr = RREG32(mmIH_DOORBELL_RPTR);
	151	if (adev->irq.ih.use_doorbell) {
	152	ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
	153	OFFSET, adev->irq.ih.doorbell_index);
	154	ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
	155	ENABLE, 1);
	156	} else {
	157	ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
	158	ENABLE, 0);
	159	}
	160	WREG32(mmIH_DOORBELL_RPTR, ih_doorbell_rtpr);
	161
	162	pci_set_master(adev->pdev);
	163
	164	/* enable interrupts */
	165	tonga_ih_enable_interrupts(adev);
166
2f46b2a5	167	return 0;
aaa36a97 AD	168	}
	169
	170	/**
	171	* tonga_ih_irq_disable - disable interrupts
	172	*
	173	* @adev: amdgpu_device pointer
	174	*
	175	* Disable interrupts on the hw (VI).
	176	*/
	177	static void tonga_ih_irq_disable(struct amdgpu_device *adev)
	178	{
	179	tonga_ih_disable_interrupts(adev);
	180
	181	/* Wait and acknowledge irq */
	182	mdelay(1);
	183	}
	184
	185	/**
	186	* tonga_ih_get_wptr - get the IH ring buffer wptr
	187	*
	188	* @adev: amdgpu_device pointer
	189	*
	190	* Get the IH ring buffer wptr from either the register
	191	* or the writeback memory buffer (VI). Also check for
	192	* ring buffer overflow and deal with it.
	193	* Used by cz_irq_process(VI).
	194	* Returns the value of the wptr.
	195	*/
	196	static u32 tonga_ih_get_wptr(struct amdgpu_device *adev)
	197	{
	198	u32 wptr, tmp;
	199
	200	if (adev->irq.ih.use_bus_addr)
	201	wptr = le32_to_cpu(adev->irq.ih.ring[adev->irq.ih.wptr_offs]);
	202	else
	203	wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);
	204
	205	if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
	206	wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
	207	/* When a ring buffer overflow happen start parsing interrupt
	208	* from the last not overwritten vector (wptr + 16). Hopefully
	209	* this should allow us to catchup.
	210	*/
	211	dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
	212	wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask);
	213	adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask;
	214	tmp = RREG32(mmIH_RB_CNTL);
	215	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
	216	WREG32(mmIH_RB_CNTL, tmp);
	217	}
	218	return (wptr & adev->irq.ih.ptr_mask);
	219	}
	220
	221	/**
	222	* tonga_ih_decode_iv - decode an interrupt vector
	223	*
	224	* @adev: amdgpu_device pointer
	225	*
	226	* Decodes the interrupt vector at the current rptr
	227	* position and also advance the position.
	228	*/
	229	static void tonga_ih_decode_iv(struct amdgpu_device *adev,
	230	struct amdgpu_iv_entry *entry)
	231	{
232	/* wptr/rptr are in bytes! */
233	u32 ring_index = adev->irq.ih.rptr >> 2;
234	uint32_t dw[4];
235
236	dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]);
237	dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]);
238	dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
239	dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);
240
d766e6a3	241	entry->client_id = AMDGPU_IH_CLIENTID_LEGACY;
aaa36a97	242	entry->src_id = dw[0] & 0xff;
7ccf5aa8	243	entry->src_data[0] = dw[1] & 0xfffffff;
aaa36a97 AD	244	entry->ring_id = dw[2] & 0xff;
	245	entry->vm_id = (dw[2] >> 8) & 0xff;
	246	entry->pas_id = (dw[2] >> 16) & 0xffff;
	247
	248	/* wptr/rptr are in bytes! */
	249	adev->irq.ih.rptr += 16;
	250	}
	251
	252	/**
	253	* tonga_ih_set_rptr - set the IH ring buffer rptr
	254	*
	255	* @adev: amdgpu_device pointer
	256	*
	257	* Set the IH ring buffer rptr.
	258	*/
	259	static void tonga_ih_set_rptr(struct amdgpu_device *adev)
	260	{
	261	if (adev->irq.ih.use_doorbell) {
	262	/* XXX check if swapping is necessary on BE */
	263	if (adev->irq.ih.use_bus_addr)
	264	adev->irq.ih.ring[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr;
	265	else
	266	adev->wb.wb[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr;
	267	WDOORBELL32(adev->irq.ih.doorbell_index, adev->irq.ih.rptr);
	268	} else {
	269	WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr);
	270	}
	271	}
	272
5fc3aeeb	273	static int tonga_ih_early_init(void *handle)
aaa36a97	274	{
5fc3aeeb	275	struct amdgpu_device adev = (struct amdgpu_device )handle;
5f232365 AD	276	int ret;
	277
	278	ret = amdgpu_irq_add_domain(adev);
	279	if (ret)
	280	return ret;
5fc3aeeb	281
aaa36a97	282	tonga_ih_set_interrupt_funcs(adev);
5f232365	283
aaa36a97 AD	284	return 0;
	285	}
	286
5fc3aeeb	287	static int tonga_ih_sw_init(void *handle)
aaa36a97 AD	288	{
aaa36a97 AD	289	int r;
5fc3aeeb	290	struct amdgpu_device adev = (struct amdgpu_device )handle;
aaa36a97	291
8fb6e528	292	r = amdgpu_ih_ring_init(adev, 64 * 1024, true);
aaa36a97 AD	293	if (r)
	294	return r;
	295
	296	adev->irq.ih.use_doorbell = true;
	297	adev->irq.ih.doorbell_index = AMDGPU_DOORBELL_IH;
	298
	299	r = amdgpu_irq_init(adev);
	300
	301	return r;
	302	}
	303
5fc3aeeb	304	static int tonga_ih_sw_fini(void *handle)
aaa36a97	305	{
5fc3aeeb	306	struct amdgpu_device adev = (struct amdgpu_device )handle;
5fc3aeeb	307
aaa36a97 AD	308	amdgpu_irq_fini(adev);
aaa36a97 AD	309	amdgpu_ih_ring_fini(adev);
303f551c	310	amdgpu_irq_remove_domain(adev);
aaa36a97 AD	311
	312	return 0;
	313	}
	314
5fc3aeeb	315	static int tonga_ih_hw_init(void *handle)
aaa36a97 AD	316	{
aaa36a97 AD	317	int r;
5fc3aeeb	318	struct amdgpu_device adev = (struct amdgpu_device )handle;
aaa36a97 AD	319
	320	r = tonga_ih_irq_init(adev);
	321	if (r)
	322	return r;
	323
	324	return 0;
	325	}
	326
5fc3aeeb	327	static int tonga_ih_hw_fini(void *handle)
aaa36a97	328	{
5fc3aeeb	329	struct amdgpu_device adev = (struct amdgpu_device )handle;
5fc3aeeb	330
aaa36a97 AD	331	tonga_ih_irq_disable(adev);
	332
	333	return 0;
	334	}
	335
5fc3aeeb	336	static int tonga_ih_suspend(void *handle)
aaa36a97	337	{
5fc3aeeb	338	struct amdgpu_device adev = (struct amdgpu_device )handle;
5fc3aeeb	339
aaa36a97 AD	340	return tonga_ih_hw_fini(adev);
	341	}
	342
5fc3aeeb	343	static int tonga_ih_resume(void *handle)
aaa36a97	344	{
5fc3aeeb	345	struct amdgpu_device adev = (struct amdgpu_device )handle;
5fc3aeeb	346
aaa36a97 AD	347	return tonga_ih_hw_init(adev);
	348	}
	349
5fc3aeeb	350	static bool tonga_ih_is_idle(void *handle)
aaa36a97	351	{
5fc3aeeb	352	struct amdgpu_device adev = (struct amdgpu_device )handle;
aaa36a97 AD	353	u32 tmp = RREG32(mmSRBM_STATUS);
	354
	355	if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
	356	return false;
	357
	358	return true;
	359	}
	360
5fc3aeeb	361	static int tonga_ih_wait_for_idle(void *handle)
aaa36a97 AD	362	{
	363	unsigned i;
	364	u32 tmp;
5fc3aeeb	365	struct amdgpu_device adev = (struct amdgpu_device )handle;
aaa36a97 AD	366
	367	for (i = 0; i < adev->usec_timeout; i++) {
	368	/* read MC_STATUS */
	369	tmp = RREG32(mmSRBM_STATUS);
	370	if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
	371	return 0;
	372	udelay(1);
	373	}
	374	return -ETIMEDOUT;
	375	}
	376
da146d3b	377	static bool tonga_ih_check_soft_reset(void *handle)
aaa36a97	378	{
5fc3aeeb	379	struct amdgpu_device adev = (struct amdgpu_device )handle;
1015a1b1	380	u32 srbm_soft_reset = 0;
aaa36a97 AD	381	u32 tmp = RREG32(mmSRBM_STATUS);
	382
	383	if (tmp & SRBM_STATUS__IH_BUSY_MASK)
	384	srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET,
	385	SOFT_RESET_IH, 1);
	386
	387	if (srbm_soft_reset) {
1015a1b1	388	adev->irq.srbm_soft_reset = srbm_soft_reset;
da146d3b	389	return true;
1015a1b1	390	} else {
1015a1b1	391	adev->irq.srbm_soft_reset = 0;
da146d3b	392	return false;
1015a1b1	393	}
1015a1b1 CZ	394	}
	395
	396	static int tonga_ih_pre_soft_reset(void *handle)
	397	{
	398	struct amdgpu_device adev = (struct amdgpu_device )handle;
	399
da146d3b	400	if (!adev->irq.srbm_soft_reset)
1015a1b1 CZ	401	return 0;
	402
	403	return tonga_ih_hw_fini(adev);
	404	}
	405
	406	static int tonga_ih_post_soft_reset(void *handle)
	407	{
	408	struct amdgpu_device adev = (struct amdgpu_device )handle;
	409
da146d3b	410	if (!adev->irq.srbm_soft_reset)
1015a1b1 CZ	411	return 0;
	412
	413	return tonga_ih_hw_init(adev);
	414	}
	415
	416	static int tonga_ih_soft_reset(void *handle)
	417	{
	418	struct amdgpu_device adev = (struct amdgpu_device )handle;
	419	u32 srbm_soft_reset;
	420
da146d3b	421	if (!adev->irq.srbm_soft_reset)
1015a1b1 CZ	422	return 0;
	423	srbm_soft_reset = adev->irq.srbm_soft_reset;
	424
	425	if (srbm_soft_reset) {
	426	u32 tmp;
	427
aaa36a97 AD	428	tmp = RREG32(mmSRBM_SOFT_RESET);
	429	tmp \|= srbm_soft_reset;
	430	dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
	431	WREG32(mmSRBM_SOFT_RESET, tmp);
	432	tmp = RREG32(mmSRBM_SOFT_RESET);
	433
	434	udelay(50);
	435
	436	tmp &= ~srbm_soft_reset;
	437	WREG32(mmSRBM_SOFT_RESET, tmp);
	438	tmp = RREG32(mmSRBM_SOFT_RESET);
	439
	440	/* Wait a little for things to settle down */
	441	udelay(50);
aaa36a97 AD	442	}
	443
	444	return 0;
	445	}
	446
5fc3aeeb	447	static int tonga_ih_set_clockgating_state(void *handle,
5fc3aeeb	448	enum amd_clockgating_state state)
aaa36a97	449	{
aaa36a97 AD	450	return 0;
	451	}
	452
5fc3aeeb	453	static int tonga_ih_set_powergating_state(void *handle,
5fc3aeeb	454	enum amd_powergating_state state)
aaa36a97	455	{
aaa36a97 AD	456	return 0;
	457	}
	458
a1255107	459	static const struct amd_ip_funcs tonga_ih_ip_funcs = {
88a907d6	460	.name = "tonga_ih",
aaa36a97 AD	461	.early_init = tonga_ih_early_init,
	462	.late_init = NULL,
	463	.sw_init = tonga_ih_sw_init,
	464	.sw_fini = tonga_ih_sw_fini,
	465	.hw_init = tonga_ih_hw_init,
	466	.hw_fini = tonga_ih_hw_fini,
	467	.suspend = tonga_ih_suspend,
	468	.resume = tonga_ih_resume,
	469	.is_idle = tonga_ih_is_idle,
	470	.wait_for_idle = tonga_ih_wait_for_idle,
1015a1b1 CZ	471	.check_soft_reset = tonga_ih_check_soft_reset,
1015a1b1 CZ	472	.pre_soft_reset = tonga_ih_pre_soft_reset,
aaa36a97	473	.soft_reset = tonga_ih_soft_reset,
1015a1b1	474	.post_soft_reset = tonga_ih_post_soft_reset,
aaa36a97 AD	475	.set_clockgating_state = tonga_ih_set_clockgating_state,
	476	.set_powergating_state = tonga_ih_set_powergating_state,
	477	};
	478
	479	static const struct amdgpu_ih_funcs tonga_ih_funcs = {
	480	.get_wptr = tonga_ih_get_wptr,
	481	.decode_iv = tonga_ih_decode_iv,
	482	.set_rptr = tonga_ih_set_rptr
	483	};
	484
	485	static void tonga_ih_set_interrupt_funcs(struct amdgpu_device *adev)
	486	{
	487	if (adev->irq.ih_funcs == NULL)
	488	adev->irq.ih_funcs = &tonga_ih_funcs;
	489	}
	490
a1255107 AD	491	const struct amdgpu_ip_block_version tonga_ih_ip_block =
	492	{
	493	.type = AMD_IP_BLOCK_TYPE_IH,
	494	.major = 3,
	495	.minor = 0,
	496	.rev = 0,
	497	.funcs = &tonga_ih_ip_funcs,
	498	};