]> git.proxmox.com Git - mirror_ubuntu-jammy-kernel.git/blame - drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
projects / mirror_ubuntu-jammy-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/amdgpu: move the context from the IBs into the job
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / amdgpu / uvd_v5_0.c
CommitLineData
aaa36a97
AD		 1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Christian König <christian.koenig@amd.com>
23 */
24
25#include <linux/firmware.h>
26#include <drm/drmP.h>
27#include "amdgpu.h"
28#include "amdgpu_uvd.h"
29#include "vid.h"
30#include "uvd/uvd_5_0_d.h"
31#include "uvd/uvd_5_0_sh_mask.h"
32#include "oss/oss_2_0_d.h"
33#include "oss/oss_2_0_sh_mask.h"
be3ecca7 34#include "vi.h"
aaa36a97
AD		 35
36static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev);
37static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev);
38static int uvd_v5_0_start(struct amdgpu_device *adev);
39static void uvd_v5_0_stop(struct amdgpu_device *adev);
40
41/**
42 * uvd_v5_0_ring_get_rptr - get read pointer
43 *
44 * @ring: amdgpu_ring pointer
45 *
46 * Returns the current hardware read pointer
47 */
48static uint32_t uvd_v5_0_ring_get_rptr(struct amdgpu_ring *ring)
49{
50 struct amdgpu_device *adev = ring->adev;
51
52 return RREG32(mmUVD_RBC_RB_RPTR);
53}
54
55/**
56 * uvd_v5_0_ring_get_wptr - get write pointer
57 *
58 * @ring: amdgpu_ring pointer
59 *
60 * Returns the current hardware write pointer
61 */
62static uint32_t uvd_v5_0_ring_get_wptr(struct amdgpu_ring *ring)
63{
64 struct amdgpu_device *adev = ring->adev;
65
66 return RREG32(mmUVD_RBC_RB_WPTR);
67}
68
69/**
70 * uvd_v5_0_ring_set_wptr - set write pointer
71 *
72 * @ring: amdgpu_ring pointer
73 *
74 * Commits the write pointer to the hardware
75 */
76static void uvd_v5_0_ring_set_wptr(struct amdgpu_ring *ring)
77{
78 struct amdgpu_device *adev = ring->adev;
79
80 WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);
81}
82
5fc3aeeb 83static int uvd_v5_0_early_init(void *handle)
aaa36a97 84{
5fc3aeeb 85 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
86
aaa36a97
AD		 87 uvd_v5_0_set_ring_funcs(adev);
88 uvd_v5_0_set_irq_funcs(adev);
89
90 return 0;
91}
92
5fc3aeeb 93static int uvd_v5_0_sw_init(void *handle)
aaa36a97
AD		 94{
95 struct amdgpu_ring *ring;
5fc3aeeb 96 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 97 int r;
98
99 /* UVD TRAP */
100 r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq);
101 if (r)
102 return r;
103
104 r = amdgpu_uvd_sw_init(adev);
105 if (r)
106 return r;
107
108 r = amdgpu_uvd_resume(adev);
109 if (r)
110 return r;
111
112 ring = &adev->uvd.ring;
113 sprintf(ring->name, "uvd");
a3f1cf35 114 r = amdgpu_ring_init(adev, ring, 512, CP_PACKET2, 0xf,
aaa36a97
AD		 115 &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD);
116
117 return r;
118}
119
5fc3aeeb 120static int uvd_v5_0_sw_fini(void *handle)
aaa36a97
AD		 121{
122 int r;
5fc3aeeb 123 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 124
125 r = amdgpu_uvd_suspend(adev);
126 if (r)
127 return r;
128
129 r = amdgpu_uvd_sw_fini(adev);
130 if (r)
131 return r;
132
133 return r;
134}
135
136/**
137 * uvd_v5_0_hw_init - start and test UVD block
138 *
139 * @adev: amdgpu_device pointer
140 *
141 * Initialize the hardware, boot up the VCPU and do some testing
142 */
5fc3aeeb 143static int uvd_v5_0_hw_init(void *handle)
aaa36a97 144{
5fc3aeeb 145 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 146 struct amdgpu_ring *ring = &adev->uvd.ring;
147 uint32_t tmp;
148 int r;
149
150 /* raise clocks while booting up the VCPU */
151 amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
152
153 r = uvd_v5_0_start(adev);
154 if (r)
155 goto done;
156
157 ring->ready = true;
158 r = amdgpu_ring_test_ring(ring);
159 if (r) {
160 ring->ready = false;
161 goto done;
162 }
163
a27de35c 164 r = amdgpu_ring_alloc(ring, 10);
aaa36a97
AD		 165 if (r) {
166 DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r);
167 goto done;
168 }
169
170 tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
171 amdgpu_ring_write(ring, tmp);
172 amdgpu_ring_write(ring, 0xFFFFF);
173
174 tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
175 amdgpu_ring_write(ring, tmp);
176 amdgpu_ring_write(ring, 0xFFFFF);
177
178 tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
179 amdgpu_ring_write(ring, tmp);
180 amdgpu_ring_write(ring, 0xFFFFF);
181
182 /* Clear timeout status bits */
183 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));
184 amdgpu_ring_write(ring, 0x8);
185
186 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));
187 amdgpu_ring_write(ring, 3);
188
a27de35c 189 amdgpu_ring_commit(ring);
aaa36a97
AD		 190
191done:
192 /* lower clocks again */
193 amdgpu_asic_set_uvd_clocks(adev, 0, 0);
194
195 if (!r)
196 DRM_INFO("UVD initialized successfully.\n");
197
198 return r;
199}
200
201/**
202 * uvd_v5_0_hw_fini - stop the hardware block
203 *
204 * @adev: amdgpu_device pointer
205 *
206 * Stop the UVD block, mark ring as not ready any more
207 */
5fc3aeeb 208static int uvd_v5_0_hw_fini(void *handle)
aaa36a97 209{
5fc3aeeb 210 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 211 struct amdgpu_ring *ring = &adev->uvd.ring;
212
213 uvd_v5_0_stop(adev);
214 ring->ready = false;
215
216 return 0;
217}
218
5fc3aeeb 219static int uvd_v5_0_suspend(void *handle)
aaa36a97
AD		 220{
221 int r;
5fc3aeeb 222 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97 223
3f99dd81 224 r = uvd_v5_0_hw_fini(adev);
aaa36a97
AD		 225 if (r)
226 return r;
227
3f99dd81 228 r = amdgpu_uvd_suspend(adev);
aaa36a97
AD		 229 if (r)
230 return r;
231
232 return r;
233}
234
5fc3aeeb 235static int uvd_v5_0_resume(void *handle)
aaa36a97
AD		 236{
237 int r;
5fc3aeeb 238 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 239
240 r = amdgpu_uvd_resume(adev);
241 if (r)
242 return r;
243
244 r = uvd_v5_0_hw_init(adev);
245 if (r)
246 return r;
247
248 return r;
249}
250
251/**
252 * uvd_v5_0_mc_resume - memory controller programming
253 *
254 * @adev: amdgpu_device pointer
255 *
256 * Let the UVD memory controller know it's offsets
257 */
258static void uvd_v5_0_mc_resume(struct amdgpu_device *adev)
259{
260 uint64_t offset;
261 uint32_t size;
262
263 /* programm memory controller bits 0-27 */
264 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
265 lower_32_bits(adev->uvd.gpu_addr));
266 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
267 upper_32_bits(adev->uvd.gpu_addr));
268
269 offset = AMDGPU_UVD_FIRMWARE_OFFSET;
270 size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
271 WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);
272 WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
273
274 offset += size;
c0365541 275 size = AMDGPU_UVD_HEAP_SIZE;
aaa36a97
AD		 276 WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3);
277 WREG32(mmUVD_VCPU_CACHE_SIZE1, size);
278
279 offset += size;
c0365541
AN		 280 size = AMDGPU_UVD_STACK_SIZE +
281 (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles);
aaa36a97
AD		 282 WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3);
283 WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
549300ce
AD		 284
285 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
286 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
287 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
aaa36a97
AD		 288}
289
290/**
291 * uvd_v5_0_start - start UVD block
292 *
293 * @adev: amdgpu_device pointer
294 *
295 * Setup and start the UVD block
296 */
297static int uvd_v5_0_start(struct amdgpu_device *adev)
298{
299 struct amdgpu_ring *ring = &adev->uvd.ring;
300 uint32_t rb_bufsz, tmp;
301 uint32_t lmi_swap_cntl;
302 uint32_t mp_swap_cntl;
303 int i, j, r;
304
305 /*disable DPG */
306 WREG32_P(mmUVD_POWER_STATUS, 0, ~(1 << 2));
307
308 /* disable byte swapping */
309 lmi_swap_cntl = 0;
310 mp_swap_cntl = 0;
311
312 uvd_v5_0_mc_resume(adev);
313
314 /* disable clock gating */
315 WREG32(mmUVD_CGC_GATE, 0);
316
317 /* disable interupt */
318 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));
319
320 /* stall UMC and register bus before resetting VCPU */
321 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
322 mdelay(1);
323
324 /* put LMI, VCPU, RBC etc... into reset */
325 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
326 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
327 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
328 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
329 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
330 mdelay(5);
331
332 /* take UVD block out of reset */
333 WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
334 mdelay(5);
335
336 /* initialize UVD memory controller */
337 WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) |
338 (1 << 21) | (1 << 9) | (1 << 20));
339
340#ifdef __BIG_ENDIAN
341 /* swap (8 in 32) RB and IB */
342 lmi_swap_cntl = 0xa;
343 mp_swap_cntl = 0;
344#endif
345 WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
346 WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
347
348 WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
349 WREG32(mmUVD_MPC_SET_MUXA1, 0x0);
350 WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);
351 WREG32(mmUVD_MPC_SET_MUXB1, 0x0);
352 WREG32(mmUVD_MPC_SET_ALU, 0);
353 WREG32(mmUVD_MPC_SET_MUX, 0x88);
354
355 /* take all subblocks out of reset, except VCPU */
356 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
357 mdelay(5);
358
359 /* enable VCPU clock */
360 WREG32(mmUVD_VCPU_CNTL, 1 << 9);
361
362 /* enable UMC */
363 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
364
365 /* boot up the VCPU */
366 WREG32(mmUVD_SOFT_RESET, 0);
367 mdelay(10);
368
369 for (i = 0; i < 10; ++i) {
370 uint32_t status;
371 for (j = 0; j < 100; ++j) {
372 status = RREG32(mmUVD_STATUS);
373 if (status & 2)
374 break;
375 mdelay(10);
376 }
377 r = 0;
378 if (status & 2)
379 break;
380
381 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
382 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
383 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
384 mdelay(10);
385 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
386 mdelay(10);
387 r = -1;
388 }
389
390 if (r) {
391 DRM_ERROR("UVD not responding, giving up!!!\n");
392 return r;
393 }
394 /* enable master interrupt */
395 WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1));
396
397 /* clear the bit 4 of UVD_STATUS */
398 WREG32_P(mmUVD_STATUS, 0, ~(2 << 1));
399
400 rb_bufsz = order_base_2(ring->ring_size);
401 tmp = 0;
402 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
403 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
404 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
405 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
406 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
407 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
408 /* force RBC into idle state */
409 WREG32(mmUVD_RBC_RB_CNTL, tmp);
410
411 /* set the write pointer delay */
412 WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);
413
414 /* set the wb address */
415 WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2));
416
417 /* programm the RB_BASE for ring buffer */
418 WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
419 lower_32_bits(ring->gpu_addr));
420 WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
421 upper_32_bits(ring->gpu_addr));
422
423 /* Initialize the ring buffer's read and write pointers */
424 WREG32(mmUVD_RBC_RB_RPTR, 0);
425
426 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
427 WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);
428
429 WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
430
431 return 0;
432}
433
434/**
435 * uvd_v5_0_stop - stop UVD block
436 *
437 * @adev: amdgpu_device pointer
438 *
439 * stop the UVD block
440 */
441static void uvd_v5_0_stop(struct amdgpu_device *adev)
442{
443 /* force RBC into idle state */
444 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
445
446 /* Stall UMC and register bus before resetting VCPU */
447 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
448 mdelay(1);
449
450 /* put VCPU into reset */
451 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
452 mdelay(5);
453
454 /* disable VCPU clock */
455 WREG32(mmUVD_VCPU_CNTL, 0x0);
456
457 /* Unstall UMC and register bus */
458 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
459}
460
461/**
462 * uvd_v5_0_ring_emit_fence - emit an fence & trap command
463 *
464 * @ring: amdgpu_ring pointer
465 * @fence: fence to emit
466 *
467 * Write a fence and a trap command to the ring.
468 */
469static void uvd_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
890ee23f 470 unsigned flags)
aaa36a97 471{
890ee23f 472 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
aaa36a97
AD		 473
474 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
475 amdgpu_ring_write(ring, seq);
476 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
477 amdgpu_ring_write(ring, addr & 0xffffffff);
478 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
479 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
480 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
481 amdgpu_ring_write(ring, 0);
482
483 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
484 amdgpu_ring_write(ring, 0);
485 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
486 amdgpu_ring_write(ring, 0);
487 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
488 amdgpu_ring_write(ring, 2);
489}
490
aaa36a97
AD		 491/**
492 * uvd_v5_0_ring_test_ring - register write test
493 *
494 * @ring: amdgpu_ring pointer
495 *
496 * Test if we can successfully write to the context register
497 */
498static int uvd_v5_0_ring_test_ring(struct amdgpu_ring *ring)
499{
500 struct amdgpu_device *adev = ring->adev;
501 uint32_t tmp = 0;
502 unsigned i;
503 int r;
504
505 WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
a27de35c 506 r = amdgpu_ring_alloc(ring, 3);
aaa36a97
AD		 507 if (r) {
508 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
509 ring->idx, r);
510 return r;
511 }
512 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
513 amdgpu_ring_write(ring, 0xDEADBEEF);
a27de35c 514 amdgpu_ring_commit(ring);
aaa36a97
AD		 515 for (i = 0; i < adev->usec_timeout; i++) {
516 tmp = RREG32(mmUVD_CONTEXT_ID);
517 if (tmp == 0xDEADBEEF)
518 break;
519 DRM_UDELAY(1);
520 }
521
522 if (i < adev->usec_timeout) {
523 DRM_INFO("ring test on %d succeeded in %d usecs\n",
524 ring->idx, i);
525 } else {
526 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
527 ring->idx, tmp);
528 r = -EINVAL;
529 }
530 return r;
531}
532
533/**
534 * uvd_v5_0_ring_emit_ib - execute indirect buffer
535 *
536 * @ring: amdgpu_ring pointer
537 * @ib: indirect buffer to execute
538 *
539 * Write ring commands to execute the indirect buffer
540 */
541static void uvd_v5_0_ring_emit_ib(struct amdgpu_ring *ring,
f153d286 542 struct amdgpu_ib *ib, bool ctx_switch)
aaa36a97
AD		 543{
544 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0));
545 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
546 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0));
547 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
548 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0));
549 amdgpu_ring_write(ring, ib->length_dw);
550}
551
552/**
553 * uvd_v5_0_ring_test_ib - test ib execution
554 *
555 * @ring: amdgpu_ring pointer
556 *
557 * Test if we can successfully execute an IB
558 */
559static int uvd_v5_0_ring_test_ib(struct amdgpu_ring *ring)
560{
561 struct amdgpu_device *adev = ring->adev;
0e3f154a 562 struct fence *fence = NULL;
aaa36a97
AD		 563 int r;
564
565 r = amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
566 if (r) {
567 DRM_ERROR("amdgpu: failed to raise UVD clocks (%d).\n", r);
568 return r;
569 }
570
571 r = amdgpu_uvd_get_create_msg(ring, 1, NULL);
572 if (r) {
573 DRM_ERROR("amdgpu: failed to get create msg (%d).\n", r);
574 goto error;
575 }
576
d7af97db 577 r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence);
aaa36a97
AD		 578 if (r) {
579 DRM_ERROR("amdgpu: failed to get destroy ib (%d).\n", r);
580 goto error;
581 }
582
0e3f154a 583 r = fence_wait(fence, false);
aaa36a97
AD		 584 if (r) {
585 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
586 goto error;
587 }
588 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
589error:
0e3f154a 590 fence_put(fence);
aaa36a97
AD		 591 amdgpu_asic_set_uvd_clocks(adev, 0, 0);
592 return r;
593}
594
5fc3aeeb 595static bool uvd_v5_0_is_idle(void *handle)
aaa36a97 596{
5fc3aeeb 597 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
598
aaa36a97
AD		 599 return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
600}
601
5fc3aeeb 602static int uvd_v5_0_wait_for_idle(void *handle)
aaa36a97
AD		 603{
604 unsigned i;
5fc3aeeb 605 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 606
607 for (i = 0; i < adev->usec_timeout; i++) {
608 if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK))
609 return 0;
610 }
611 return -ETIMEDOUT;
612}
613
5fc3aeeb 614static int uvd_v5_0_soft_reset(void *handle)
aaa36a97 615{
5fc3aeeb 616 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
617
aaa36a97
AD		 618 uvd_v5_0_stop(adev);
619
620 WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK,
621 ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
622 mdelay(5);
623
624 return uvd_v5_0_start(adev);
625}
626
aaa36a97
AD		 627static int uvd_v5_0_set_interrupt_state(struct amdgpu_device *adev,
628 struct amdgpu_irq_src *source,
629 unsigned type,
630 enum amdgpu_interrupt_state state)
631{
632 // TODO
633 return 0;
634}
635
636static int uvd_v5_0_process_interrupt(struct amdgpu_device *adev,
637 struct amdgpu_irq_src *source,
638 struct amdgpu_iv_entry *entry)
639{
640 DRM_DEBUG("IH: UVD TRAP\n");
641 amdgpu_fence_process(&adev->uvd.ring);
642 return 0;
643}
644
be3ecca7
TSD		 645static void uvd_v5_0_set_sw_clock_gating(struct amdgpu_device *adev)
646{
647 uint32_t data, data1, data2, suvd_flags;
648
649 data = RREG32(mmUVD_CGC_CTRL);
650 data1 = RREG32(mmUVD_SUVD_CGC_GATE);
651 data2 = RREG32(mmUVD_SUVD_CGC_CTRL);
652
653 data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
654 UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
655
656 suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
657 UVD_SUVD_CGC_GATE__SIT_MASK |
658 UVD_SUVD_CGC_GATE__SMP_MASK |
659 UVD_SUVD_CGC_GATE__SCM_MASK |
660 UVD_SUVD_CGC_GATE__SDB_MASK;
661
662 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
663 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
664 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
665
666 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
667 UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
668 UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
669 UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
670 UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
671 UVD_CGC_CTRL__SYS_MODE_MASK |
672 UVD_CGC_CTRL__UDEC_MODE_MASK |
673 UVD_CGC_CTRL__MPEG2_MODE_MASK |
674 UVD_CGC_CTRL__REGS_MODE_MASK |
675 UVD_CGC_CTRL__RBC_MODE_MASK |
676 UVD_CGC_CTRL__LMI_MC_MODE_MASK |
677 UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
678 UVD_CGC_CTRL__IDCT_MODE_MASK |
679 UVD_CGC_CTRL__MPRD_MODE_MASK |
680 UVD_CGC_CTRL__MPC_MODE_MASK |
681 UVD_CGC_CTRL__LBSI_MODE_MASK |
682 UVD_CGC_CTRL__LRBBM_MODE_MASK |
683 UVD_CGC_CTRL__WCB_MODE_MASK |
684 UVD_CGC_CTRL__VCPU_MODE_MASK |
685 UVD_CGC_CTRL__JPEG_MODE_MASK |
686 UVD_CGC_CTRL__SCPU_MODE_MASK);
687 data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
688 UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |
689 UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
690 UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
691 UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
692 data1 |= suvd_flags;
693
694 WREG32(mmUVD_CGC_CTRL, data);
695 WREG32(mmUVD_CGC_GATE, 0);
696 WREG32(mmUVD_SUVD_CGC_GATE, data1);
697 WREG32(mmUVD_SUVD_CGC_CTRL, data2);
698}
699
700#if 0
701static void uvd_v5_0_set_hw_clock_gating(struct amdgpu_device *adev)
702{
703 uint32_t data, data1, cgc_flags, suvd_flags;
704
705 data = RREG32(mmUVD_CGC_GATE);
706 data1 = RREG32(mmUVD_SUVD_CGC_GATE);
707
708 cgc_flags = UVD_CGC_GATE__SYS_MASK |
709 UVD_CGC_GATE__UDEC_MASK |
710 UVD_CGC_GATE__MPEG2_MASK |
711 UVD_CGC_GATE__RBC_MASK |
712 UVD_CGC_GATE__LMI_MC_MASK |
713 UVD_CGC_GATE__IDCT_MASK |
714 UVD_CGC_GATE__MPRD_MASK |
715 UVD_CGC_GATE__MPC_MASK |
716 UVD_CGC_GATE__LBSI_MASK |
717 UVD_CGC_GATE__LRBBM_MASK |
718 UVD_CGC_GATE__UDEC_RE_MASK |
719 UVD_CGC_GATE__UDEC_CM_MASK |
720 UVD_CGC_GATE__UDEC_IT_MASK |
721 UVD_CGC_GATE__UDEC_DB_MASK |
722 UVD_CGC_GATE__UDEC_MP_MASK |
723 UVD_CGC_GATE__WCB_MASK |
724 UVD_CGC_GATE__VCPU_MASK |
725 UVD_CGC_GATE__SCPU_MASK;
726
727 suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
728 UVD_SUVD_CGC_GATE__SIT_MASK |
729 UVD_SUVD_CGC_GATE__SMP_MASK |
730 UVD_SUVD_CGC_GATE__SCM_MASK |
731 UVD_SUVD_CGC_GATE__SDB_MASK;
732
733 data |= cgc_flags;
734 data1 |= suvd_flags;
735
736 WREG32(mmUVD_CGC_GATE, data);
737 WREG32(mmUVD_SUVD_CGC_GATE, data1);
738}
739#endif
740
5fc3aeeb 741static int uvd_v5_0_set_clockgating_state(void *handle,
742 enum amd_clockgating_state state)
aaa36a97 743{
35e5912d 744 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
be3ecca7
TSD		 745 bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
746 static int curstate = -1;
35e5912d 747
e3b04bc7 748 if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
35e5912d
AD		 749 return 0;
750
be3ecca7
TSD		 751 if (curstate == state)
752 return 0;
753
754 curstate = state;
755 if (enable) {
756 /* disable HW gating and enable Sw gating */
757 uvd_v5_0_set_sw_clock_gating(adev);
758 } else {
759 /* wait for STATUS to clear */
760 if (uvd_v5_0_wait_for_idle(handle))
761 return -EBUSY;
762
763 /* enable HW gates because UVD is idle */
764/* uvd_v5_0_set_hw_clock_gating(adev); */
765 }
766
aaa36a97
AD		 767 return 0;
768}
769
5fc3aeeb 770static int uvd_v5_0_set_powergating_state(void *handle,
771 enum amd_powergating_state state)
aaa36a97
AD		 772{
773 /* This doesn't actually powergate the UVD block.
774 * That's done in the dpm code via the SMC. This
775 * just re-inits the block as necessary. The actual
776 * gating still happens in the dpm code. We should
777 * revisit this when there is a cleaner line between
778 * the smc and the hw blocks
779 */
5fc3aeeb 780 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
781
e3b04bc7 782 if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD))
b6df77fc
AD		 783 return 0;
784
5fc3aeeb 785 if (state == AMD_PG_STATE_GATE) {
aaa36a97
AD		 786 uvd_v5_0_stop(adev);
787 return 0;
788 } else {
789 return uvd_v5_0_start(adev);
790 }
791}
792
5fc3aeeb 793const struct amd_ip_funcs uvd_v5_0_ip_funcs = {
88a907d6 794 .name = "uvd_v5_0",
aaa36a97
AD		 795 .early_init = uvd_v5_0_early_init,
796 .late_init = NULL,
797 .sw_init = uvd_v5_0_sw_init,
798 .sw_fini = uvd_v5_0_sw_fini,
799 .hw_init = uvd_v5_0_hw_init,
800 .hw_fini = uvd_v5_0_hw_fini,
801 .suspend = uvd_v5_0_suspend,
802 .resume = uvd_v5_0_resume,
803 .is_idle = uvd_v5_0_is_idle,
804 .wait_for_idle = uvd_v5_0_wait_for_idle,
805 .soft_reset = uvd_v5_0_soft_reset,
aaa36a97
AD		 806 .set_clockgating_state = uvd_v5_0_set_clockgating_state,
807 .set_powergating_state = uvd_v5_0_set_powergating_state,
808};
809
810static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = {
811 .get_rptr = uvd_v5_0_ring_get_rptr,
812 .get_wptr = uvd_v5_0_ring_get_wptr,
813 .set_wptr = uvd_v5_0_ring_set_wptr,
814 .parse_cs = amdgpu_uvd_ring_parse_cs,
815 .emit_ib = uvd_v5_0_ring_emit_ib,
816 .emit_fence = uvd_v5_0_ring_emit_fence,
aaa36a97
AD		 817 .test_ring = uvd_v5_0_ring_test_ring,
818 .test_ib = uvd_v5_0_ring_test_ib,
edff0e28 819 .insert_nop = amdgpu_ring_insert_nop,
9e5d5309 820 .pad_ib = amdgpu_ring_generic_pad_ib,
aaa36a97
AD		 821};
822
823static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev)
824{
825 adev->uvd.ring.funcs = &uvd_v5_0_ring_funcs;
826}
827
828static const struct amdgpu_irq_src_funcs uvd_v5_0_irq_funcs = {
829 .set = uvd_v5_0_set_interrupt_state,
830 .process = uvd_v5_0_process_interrupt,
831};
832
833static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev)
834{
835 adev->uvd.irq.num_types = 1;
836 adev->uvd.irq.funcs = &uvd_v5_0_irq_funcs;
837}
Ubuntu Jammy Linux kernel mirror