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Merge tag 'drm-amdkfd-next-2017-10-18' of git://people.freedesktop.org/~gabbayo/linux...
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / amdgpu / uvd_v6_0.c
CommitLineData
aaa36a97
AD		 1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Christian König <christian.koenig@amd.com>
23 */
24
25#include <linux/firmware.h>
26#include <drm/drmP.h>
27#include "amdgpu.h"
28#include "amdgpu_uvd.h"
29#include "vid.h"
30#include "uvd/uvd_6_0_d.h"
31#include "uvd/uvd_6_0_sh_mask.h"
32#include "oss/oss_2_0_d.h"
33#include "oss/oss_2_0_sh_mask.h"
a0cdef9e
AD		 34#include "smu/smu_7_1_3_d.h"
35#include "smu/smu_7_1_3_sh_mask.h"
d5b4e25d 36#include "bif/bif_5_1_d.h"
0f30a397 37#include "gmc/gmc_8_1_d.h"
be3ecca7 38#include "vi.h"
aaa36a97
AD		 39
40static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev);
c259ee6e
JZ		 41static void uvd_v6_0_set_enc_ring_funcs(struct amdgpu_device *adev);
42
aaa36a97
AD		 43static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev);
44static int uvd_v6_0_start(struct amdgpu_device *adev);
45static void uvd_v6_0_stop(struct amdgpu_device *adev);
be3ecca7 46static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev);
805b3ba8
RZ		 47static int uvd_v6_0_set_clockgating_state(void *handle,
48 enum amd_clockgating_state state);
49static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev,
50 bool enable);
aaa36a97 51
06a7e9cb
JZ		 52/**
53* uvd_v6_0_enc_support - get encode support status
54*
55* @adev: amdgpu_device pointer
56*
57* Returns the current hardware encode support status
58*/
59static inline bool uvd_v6_0_enc_support(struct amdgpu_device *adev)
60{
61 return ((adev->asic_type >= CHIP_POLARIS10) && (adev->asic_type <= CHIP_POLARIS12));
62}
63
aaa36a97
AD		 64/**
65 * uvd_v6_0_ring_get_rptr - get read pointer
66 *
67 * @ring: amdgpu_ring pointer
68 *
69 * Returns the current hardware read pointer
70 */
536fbf94 71static uint64_t uvd_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
aaa36a97
AD		 72{
73 struct amdgpu_device *adev = ring->adev;
74
75 return RREG32(mmUVD_RBC_RB_RPTR);
76}
77
c0f2f2e6
JZ		 78/**
79 * uvd_v6_0_enc_ring_get_rptr - get enc read pointer
80 *
81 * @ring: amdgpu_ring pointer
82 *
83 * Returns the current hardware enc read pointer
84 */
85static uint64_t uvd_v6_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
86{
87 struct amdgpu_device *adev = ring->adev;
88
89 if (ring == &adev->uvd.ring_enc[0])
90 return RREG32(mmUVD_RB_RPTR);
91 else
92 return RREG32(mmUVD_RB_RPTR2);
93}
aaa36a97
AD		 94/**
95 * uvd_v6_0_ring_get_wptr - get write pointer
96 *
97 * @ring: amdgpu_ring pointer
98 *
99 * Returns the current hardware write pointer
100 */
536fbf94 101static uint64_t uvd_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
aaa36a97
AD		 102{
103 struct amdgpu_device *adev = ring->adev;
104
105 return RREG32(mmUVD_RBC_RB_WPTR);
106}
107
c0f2f2e6
JZ		 108/**
109 * uvd_v6_0_enc_ring_get_wptr - get enc write pointer
110 *
111 * @ring: amdgpu_ring pointer
112 *
113 * Returns the current hardware enc write pointer
114 */
115static uint64_t uvd_v6_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
116{
117 struct amdgpu_device *adev = ring->adev;
118
119 if (ring == &adev->uvd.ring_enc[0])
120 return RREG32(mmUVD_RB_WPTR);
121 else
122 return RREG32(mmUVD_RB_WPTR2);
123}
124
aaa36a97
AD		 125/**
126 * uvd_v6_0_ring_set_wptr - set write pointer
127 *
128 * @ring: amdgpu_ring pointer
129 *
130 * Commits the write pointer to the hardware
131 */
132static void uvd_v6_0_ring_set_wptr(struct amdgpu_ring *ring)
133{
134 struct amdgpu_device *adev = ring->adev;
135
536fbf94 136 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
aaa36a97
AD		 137}
138
c0f2f2e6
JZ		 139/**
140 * uvd_v6_0_enc_ring_set_wptr - set enc write pointer
141 *
142 * @ring: amdgpu_ring pointer
143 *
144 * Commits the enc write pointer to the hardware
145 */
146static void uvd_v6_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
147{
148 struct amdgpu_device *adev = ring->adev;
149
150 if (ring == &adev->uvd.ring_enc[0])
151 WREG32(mmUVD_RB_WPTR,
152 lower_32_bits(ring->wptr));
153 else
154 WREG32(mmUVD_RB_WPTR2,
155 lower_32_bits(ring->wptr));
156}
157
2a91f272
JZ		 158/**
159 * uvd_v6_0_enc_ring_test_ring - test if UVD ENC ring is working
160 *
161 * @ring: the engine to test on
162 *
163 */
164static int uvd_v6_0_enc_ring_test_ring(struct amdgpu_ring *ring)
165{
166 struct amdgpu_device *adev = ring->adev;
167 uint32_t rptr = amdgpu_ring_get_rptr(ring);
168 unsigned i;
169 int r;
170
171 r = amdgpu_ring_alloc(ring, 16);
172 if (r) {
173 DRM_ERROR("amdgpu: uvd enc failed to lock ring %d (%d).\n",
174 ring->idx, r);
175 return r;
176 }
177 amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
178 amdgpu_ring_commit(ring);
179
180 for (i = 0; i < adev->usec_timeout; i++) {
181 if (amdgpu_ring_get_rptr(ring) != rptr)
182 break;
183 DRM_UDELAY(1);
184 }
185
186 if (i < adev->usec_timeout) {
187 DRM_INFO("ring test on %d succeeded in %d usecs\n",
188 ring->idx, i);
189 } else {
190 DRM_ERROR("amdgpu: ring %d test failed\n",
191 ring->idx);
192 r = -ETIMEDOUT;
193 }
194
195 return r;
196}
197
e0128efb
JZ		 198/**
199 * uvd_v6_0_enc_get_create_msg - generate a UVD ENC create msg
200 *
201 * @adev: amdgpu_device pointer
202 * @ring: ring we should submit the msg to
203 * @handle: session handle to use
204 * @fence: optional fence to return
205 *
206 * Open up a stream for HW test
207 */
208static int uvd_v6_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
209 struct dma_fence **fence)
210{
211 const unsigned ib_size_dw = 16;
212 struct amdgpu_job *job;
213 struct amdgpu_ib *ib;
214 struct dma_fence *f = NULL;
215 uint64_t dummy;
216 int i, r;
217
218 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
219 if (r)
220 return r;
221
222 ib = &job->ibs[0];
223 dummy = ib->gpu_addr + 1024;
224
225 ib->length_dw = 0;
226 ib->ptr[ib->length_dw++] = 0x00000018;
227 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
228 ib->ptr[ib->length_dw++] = handle;
229 ib->ptr[ib->length_dw++] = 0x00010000;
230 ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
231 ib->ptr[ib->length_dw++] = dummy;
232
233 ib->ptr[ib->length_dw++] = 0x00000014;
234 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
235 ib->ptr[ib->length_dw++] = 0x0000001c;
236 ib->ptr[ib->length_dw++] = 0x00000001;
237 ib->ptr[ib->length_dw++] = 0x00000000;
238
239 ib->ptr[ib->length_dw++] = 0x00000008;
240 ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */
241
242 for (i = ib->length_dw; i < ib_size_dw; ++i)
243 ib->ptr[i] = 0x0;
244
245 r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
246 job->fence = dma_fence_get(f);
247 if (r)
248 goto err;
249
250 amdgpu_job_free(job);
251 if (fence)
252 *fence = dma_fence_get(f);
253 dma_fence_put(f);
254 return 0;
255
256err:
257 amdgpu_job_free(job);
258 return r;
259}
260
261/**
262 * uvd_v6_0_enc_get_destroy_msg - generate a UVD ENC destroy msg
263 *
264 * @adev: amdgpu_device pointer
265 * @ring: ring we should submit the msg to
266 * @handle: session handle to use
267 * @fence: optional fence to return
268 *
269 * Close up a stream for HW test or if userspace failed to do so
270 */
f15507a1
CIK		 271static int uvd_v6_0_enc_get_destroy_msg(struct amdgpu_ring *ring,
272 uint32_t handle,
273 bool direct, struct dma_fence **fence)
e0128efb
JZ		 274{
275 const unsigned ib_size_dw = 16;
276 struct amdgpu_job *job;
277 struct amdgpu_ib *ib;
278 struct dma_fence *f = NULL;
279 uint64_t dummy;
280 int i, r;
281
282 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
283 if (r)
284 return r;
285
286 ib = &job->ibs[0];
287 dummy = ib->gpu_addr + 1024;
288
289 ib->length_dw = 0;
290 ib->ptr[ib->length_dw++] = 0x00000018;
291 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
292 ib->ptr[ib->length_dw++] = handle;
293 ib->ptr[ib->length_dw++] = 0x00010000;
294 ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
295 ib->ptr[ib->length_dw++] = dummy;
296
297 ib->ptr[ib->length_dw++] = 0x00000014;
298 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
299 ib->ptr[ib->length_dw++] = 0x0000001c;
300 ib->ptr[ib->length_dw++] = 0x00000001;
301 ib->ptr[ib->length_dw++] = 0x00000000;
302
303 ib->ptr[ib->length_dw++] = 0x00000008;
304 ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */
305
306 for (i = ib->length_dw; i < ib_size_dw; ++i)
307 ib->ptr[i] = 0x0;
308
309 if (direct) {
310 r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
311 job->fence = dma_fence_get(f);
312 if (r)
313 goto err;
314
315 amdgpu_job_free(job);
316 } else {
317 r = amdgpu_job_submit(job, ring, &ring->adev->vce.entity,
318 AMDGPU_FENCE_OWNER_UNDEFINED, &f);
319 if (r)
320 goto err;
321 }
322
323 if (fence)
324 *fence = dma_fence_get(f);
325 dma_fence_put(f);
326 return 0;
327
328err:
329 amdgpu_job_free(job);
330 return r;
331}
332
333/**
334 * uvd_v6_0_enc_ring_test_ib - test if UVD ENC IBs are working
335 *
336 * @ring: the engine to test on
337 *
338 */
339static int uvd_v6_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
340{
341 struct dma_fence *fence = NULL;
342 long r;
343
344 r = uvd_v6_0_enc_get_create_msg(ring, 1, NULL);
345 if (r) {
346 DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r);
347 goto error;
348 }
349
350 r = uvd_v6_0_enc_get_destroy_msg(ring, 1, true, &fence);
351 if (r) {
352 DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r);
353 goto error;
354 }
355
356 r = dma_fence_wait_timeout(fence, false, timeout);
357 if (r == 0) {
358 DRM_ERROR("amdgpu: IB test timed out.\n");
359 r = -ETIMEDOUT;
360 } else if (r < 0) {
361 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
362 } else {
363 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
364 r = 0;
365 }
366error:
367 dma_fence_put(fence);
368 return r;
369}
5fc3aeeb 370static int uvd_v6_0_early_init(void *handle)
aaa36a97 371{
5fc3aeeb 372 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
373
aaa36a97 374 uvd_v6_0_set_ring_funcs(adev);
06a7e9cb
JZ		 375
376 if (uvd_v6_0_enc_support(adev)) {
377 adev->uvd.num_enc_rings = 2;
c259ee6e 378 uvd_v6_0_set_enc_ring_funcs(adev);
06a7e9cb
JZ		 379 }
380
aaa36a97
AD		 381 uvd_v6_0_set_irq_funcs(adev);
382
383 return 0;
384}
385
5fc3aeeb 386static int uvd_v6_0_sw_init(void *handle)
aaa36a97
AD		 387{
388 struct amdgpu_ring *ring;
06a7e9cb 389 int i, r;
5fc3aeeb 390 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 391
392 /* UVD TRAP */
d766e6a3 393 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 124, &adev->uvd.irq);
aaa36a97
AD		 394 if (r)
395 return r;
396
65da0d40
JZ		 397 /* UVD ENC TRAP */
398 if (uvd_v6_0_enc_support(adev)) {
399 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
400 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 119, &adev->uvd.irq);
401 if (r)
402 return r;
403 }
404 }
405
aaa36a97
AD		 406 r = amdgpu_uvd_sw_init(adev);
407 if (r)
408 return r;
409
296191c5
JZ		 410 if (uvd_v6_0_enc_support(adev)) {
411 struct amd_sched_rq *rq;
412 ring = &adev->uvd.ring_enc[0];
413 rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
414 r = amd_sched_entity_init(&ring->sched, &adev->uvd.entity_enc,
415 rq, amdgpu_sched_jobs);
416 if (r) {
417 DRM_ERROR("Failed setting up UVD ENC run queue.\n");
418 return r;
419 }
420 }
421
aaa36a97
AD		 422 r = amdgpu_uvd_resume(adev);
423 if (r)
424 return r;
425
426 ring = &adev->uvd.ring;
427 sprintf(ring->name, "uvd");
79887142 428 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
06a7e9cb
JZ		 429 if (r)
430 return r;
431
432 if (uvd_v6_0_enc_support(adev)) {
433 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
434 ring = &adev->uvd.ring_enc[i];
435 sprintf(ring->name, "uvd_enc%d", i);
436 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
437 if (r)
438 return r;
439 }
440 }
aaa36a97
AD		 441
442 return r;
443}
444
5fc3aeeb 445static int uvd_v6_0_sw_fini(void *handle)
aaa36a97 446{
06a7e9cb 447 int i, r;
5fc3aeeb 448 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 449
450 r = amdgpu_uvd_suspend(adev);
451 if (r)
452 return r;
453
06a7e9cb 454 if (uvd_v6_0_enc_support(adev)) {
296191c5
JZ		 455 amd_sched_entity_fini(&adev->uvd.ring_enc[0].sched, &adev->uvd.entity_enc);
456
06a7e9cb
JZ		 457 for (i = 0; i < adev->uvd.num_enc_rings; ++i)
458 amdgpu_ring_fini(&adev->uvd.ring_enc[i]);
459 }
460
50237287 461 return amdgpu_uvd_sw_fini(adev);
aaa36a97
AD		 462}
463
464/**
465 * uvd_v6_0_hw_init - start and test UVD block
466 *
467 * @adev: amdgpu_device pointer
468 *
469 * Initialize the hardware, boot up the VCPU and do some testing
470 */
5fc3aeeb 471static int uvd_v6_0_hw_init(void *handle)
aaa36a97 472{
5fc3aeeb 473 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 474 struct amdgpu_ring *ring = &adev->uvd.ring;
475 uint32_t tmp;
2a91f272 476 int i, r;
aaa36a97 477
e3e672e6
RZ		 478 amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);
479 uvd_v6_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE);
480 uvd_v6_0_enable_mgcg(adev, true);
aaa36a97
AD		 481
482 ring->ready = true;
483 r = amdgpu_ring_test_ring(ring);
484 if (r) {
485 ring->ready = false;
486 goto done;
487 }
488
a27de35c 489 r = amdgpu_ring_alloc(ring, 10);
aaa36a97
AD		 490 if (r) {
491 DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r);
492 goto done;
493 }
494
495 tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
496 amdgpu_ring_write(ring, tmp);
497 amdgpu_ring_write(ring, 0xFFFFF);
498
499 tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
500 amdgpu_ring_write(ring, tmp);
501 amdgpu_ring_write(ring, 0xFFFFF);
502
503 tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
504 amdgpu_ring_write(ring, tmp);
505 amdgpu_ring_write(ring, 0xFFFFF);
506
507 /* Clear timeout status bits */
508 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));
509 amdgpu_ring_write(ring, 0x8);
510
511 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));
512 amdgpu_ring_write(ring, 3);
513
a27de35c 514 amdgpu_ring_commit(ring);
aaa36a97 515
2a91f272
JZ		 516 if (uvd_v6_0_enc_support(adev)) {
517 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
518 ring = &adev->uvd.ring_enc[i];
519 ring->ready = true;
520 r = amdgpu_ring_test_ring(ring);
521 if (r) {
522 ring->ready = false;
523 goto done;
524 }
525 }
526 }
527
aaa36a97 528done:
c259ee6e
JZ		 529 if (!r) {
530 if (uvd_v6_0_enc_support(adev))
531 DRM_INFO("UVD and UVD ENC initialized successfully.\n");
532 else
533 DRM_INFO("UVD initialized successfully.\n");
534 }
aaa36a97
AD		 535
536 return r;
537}
538
539/**
540 * uvd_v6_0_hw_fini - stop the hardware block
541 *
542 * @adev: amdgpu_device pointer
543 *
544 * Stop the UVD block, mark ring as not ready any more
545 */
5fc3aeeb 546static int uvd_v6_0_hw_fini(void *handle)
aaa36a97 547{
5fc3aeeb 548 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 549 struct amdgpu_ring *ring = &adev->uvd.ring;
550
e3e672e6
RZ		 551 if (RREG32(mmUVD_STATUS) != 0)
552 uvd_v6_0_stop(adev);
553
aaa36a97
AD		 554 ring->ready = false;
555
556 return 0;
557}
558
5fc3aeeb 559static int uvd_v6_0_suspend(void *handle)
aaa36a97
AD		 560{
561 int r;
5fc3aeeb 562 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97 563
3f99dd81
LL		 564 r = uvd_v6_0_hw_fini(adev);
565 if (r)
566 return r;
567
1f445210 568 /* Skip this for APU for now */
50237287 569 if (!(adev->flags & AMD_IS_APU))
1f445210 570 r = amdgpu_uvd_suspend(adev);
aaa36a97
AD		 571
572 return r;
573}
574
5fc3aeeb 575static int uvd_v6_0_resume(void *handle)
aaa36a97
AD		 576{
577 int r;
5fc3aeeb 578 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97 579
1f445210
LL		 580 /* Skip this for APU for now */
581 if (!(adev->flags & AMD_IS_APU)) {
582 r = amdgpu_uvd_resume(adev);
583 if (r)
584 return r;
585 }
50237287 586 return uvd_v6_0_hw_init(adev);
aaa36a97
AD		 587}
588
589/**
590 * uvd_v6_0_mc_resume - memory controller programming
591 *
592 * @adev: amdgpu_device pointer
593 *
594 * Let the UVD memory controller know it's offsets
595 */
596static void uvd_v6_0_mc_resume(struct amdgpu_device *adev)
597{
598 uint64_t offset;
599 uint32_t size;
600
601 /* programm memory controller bits 0-27 */
602 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
603 lower_32_bits(adev->uvd.gpu_addr));
604 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
605 upper_32_bits(adev->uvd.gpu_addr));
606
607 offset = AMDGPU_UVD_FIRMWARE_OFFSET;
608 size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
609 WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);
610 WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
611
612 offset += size;
c0365541 613 size = AMDGPU_UVD_HEAP_SIZE;
aaa36a97
AD		 614 WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3);
615 WREG32(mmUVD_VCPU_CACHE_SIZE1, size);
616
617 offset += size;
c0365541
AN		 618 size = AMDGPU_UVD_STACK_SIZE +
619 (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles);
aaa36a97
AD		 620 WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3);
621 WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
549300ce
AD		 622
623 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
624 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
625 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
c0365541
AN		 626
627 WREG32(mmUVD_GP_SCRATCH4, adev->uvd.max_handles);
aaa36a97
AD		 628}
629
be3ecca7 630#if 0
9b08a306
EH		 631static void cz_set_uvd_clock_gating_branches(struct amdgpu_device *adev,
632 bool enable)
633{
634 u32 data, data1;
635
636 data = RREG32(mmUVD_CGC_GATE);
637 data1 = RREG32(mmUVD_SUVD_CGC_GATE);
638 if (enable) {
639 data |= UVD_CGC_GATE__SYS_MASK |
640 UVD_CGC_GATE__UDEC_MASK |
641 UVD_CGC_GATE__MPEG2_MASK |
642 UVD_CGC_GATE__RBC_MASK |
643 UVD_CGC_GATE__LMI_MC_MASK |
644 UVD_CGC_GATE__IDCT_MASK |
645 UVD_CGC_GATE__MPRD_MASK |
646 UVD_CGC_GATE__MPC_MASK |
647 UVD_CGC_GATE__LBSI_MASK |
648 UVD_CGC_GATE__LRBBM_MASK |
649 UVD_CGC_GATE__UDEC_RE_MASK |
650 UVD_CGC_GATE__UDEC_CM_MASK |
651 UVD_CGC_GATE__UDEC_IT_MASK |
652 UVD_CGC_GATE__UDEC_DB_MASK |
653 UVD_CGC_GATE__UDEC_MP_MASK |
654 UVD_CGC_GATE__WCB_MASK |
655 UVD_CGC_GATE__VCPU_MASK |
656 UVD_CGC_GATE__SCPU_MASK;
657 data1 |= UVD_SUVD_CGC_GATE__SRE_MASK |
658 UVD_SUVD_CGC_GATE__SIT_MASK |
659 UVD_SUVD_CGC_GATE__SMP_MASK |
660 UVD_SUVD_CGC_GATE__SCM_MASK |
661 UVD_SUVD_CGC_GATE__SDB_MASK |
662 UVD_SUVD_CGC_GATE__SRE_H264_MASK |
663 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK |
664 UVD_SUVD_CGC_GATE__SIT_H264_MASK |
665 UVD_SUVD_CGC_GATE__SIT_HEVC_MASK |
666 UVD_SUVD_CGC_GATE__SCM_H264_MASK |
667 UVD_SUVD_CGC_GATE__SCM_HEVC_MASK |
668 UVD_SUVD_CGC_GATE__SDB_H264_MASK |
669 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK;
670 } else {
671 data &= ~(UVD_CGC_GATE__SYS_MASK |
672 UVD_CGC_GATE__UDEC_MASK |
673 UVD_CGC_GATE__MPEG2_MASK |
674 UVD_CGC_GATE__RBC_MASK |
675 UVD_CGC_GATE__LMI_MC_MASK |
676 UVD_CGC_GATE__LMI_UMC_MASK |
677 UVD_CGC_GATE__IDCT_MASK |
678 UVD_CGC_GATE__MPRD_MASK |
679 UVD_CGC_GATE__MPC_MASK |
680 UVD_CGC_GATE__LBSI_MASK |
681 UVD_CGC_GATE__LRBBM_MASK |
682 UVD_CGC_GATE__UDEC_RE_MASK |
683 UVD_CGC_GATE__UDEC_CM_MASK |
684 UVD_CGC_GATE__UDEC_IT_MASK |
685 UVD_CGC_GATE__UDEC_DB_MASK |
686 UVD_CGC_GATE__UDEC_MP_MASK |
687 UVD_CGC_GATE__WCB_MASK |
688 UVD_CGC_GATE__VCPU_MASK |
689 UVD_CGC_GATE__SCPU_MASK);
690 data1 &= ~(UVD_SUVD_CGC_GATE__SRE_MASK |
691 UVD_SUVD_CGC_GATE__SIT_MASK |
692 UVD_SUVD_CGC_GATE__SMP_MASK |
693 UVD_SUVD_CGC_GATE__SCM_MASK |
694 UVD_SUVD_CGC_GATE__SDB_MASK |
695 UVD_SUVD_CGC_GATE__SRE_H264_MASK |
696 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK |
697 UVD_SUVD_CGC_GATE__SIT_H264_MASK |
698 UVD_SUVD_CGC_GATE__SIT_HEVC_MASK |
699 UVD_SUVD_CGC_GATE__SCM_H264_MASK |
700 UVD_SUVD_CGC_GATE__SCM_HEVC_MASK |
701 UVD_SUVD_CGC_GATE__SDB_H264_MASK |
702 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK);
703 }
704 WREG32(mmUVD_CGC_GATE, data);
705 WREG32(mmUVD_SUVD_CGC_GATE, data1);
706}
be3ecca7 707#endif
9b08a306 708
aaa36a97
AD		 709/**
710 * uvd_v6_0_start - start UVD block
711 *
712 * @adev: amdgpu_device pointer
713 *
714 * Setup and start the UVD block
715 */
716static int uvd_v6_0_start(struct amdgpu_device *adev)
717{
718 struct amdgpu_ring *ring = &adev->uvd.ring;
719 uint32_t rb_bufsz, tmp;
720 uint32_t lmi_swap_cntl;
721 uint32_t mp_swap_cntl;
722 int i, j, r;
723
f78c3422
TSD		 724 /* disable DPG */
725 WREG32_P(mmUVD_POWER_STATUS, 0, ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
aaa36a97
AD		 726
727 /* disable byte swapping */
728 lmi_swap_cntl = 0;
729 mp_swap_cntl = 0;
730
731 uvd_v6_0_mc_resume(adev);
732
aaa36a97 733 /* disable interupt */
f4a7f127 734 WREG32_FIELD(UVD_MASTINT_EN, VCPU_EN, 0);
aaa36a97
AD		 735
736 /* stall UMC and register bus before resetting VCPU */
f4a7f127 737 WREG32_FIELD(UVD_LMI_CTRL2, STALL_ARB_UMC, 1);
aaa36a97
AD		 738 mdelay(1);
739
740 /* put LMI, VCPU, RBC etc... into reset */
f78c3422
TSD		 741 WREG32(mmUVD_SOFT_RESET,
742 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
743 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
744 UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
745 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
746 UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
747 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
748 UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
aaa36a97
AD		 749 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
750 mdelay(5);
751
752 /* take UVD block out of reset */
f4a7f127 753 WREG32_FIELD(SRBM_SOFT_RESET, SOFT_RESET_UVD, 0);
aaa36a97
AD		 754 mdelay(5);
755
756 /* initialize UVD memory controller */
f78c3422
TSD		 757 WREG32(mmUVD_LMI_CTRL,
758 (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
759 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
760 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
761 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
762 UVD_LMI_CTRL__REQ_MODE_MASK |
763 UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK);
aaa36a97
AD		 764
765#ifdef __BIG_ENDIAN
766 /* swap (8 in 32) RB and IB */
767 lmi_swap_cntl = 0xa;
768 mp_swap_cntl = 0;
769#endif
770 WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
771 WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
772
773 WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
774 WREG32(mmUVD_MPC_SET_MUXA1, 0x0);
775 WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);
776 WREG32(mmUVD_MPC_SET_MUXB1, 0x0);
777 WREG32(mmUVD_MPC_SET_ALU, 0);
778 WREG32(mmUVD_MPC_SET_MUX, 0x88);
779
780 /* take all subblocks out of reset, except VCPU */
781 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
782 mdelay(5);
783
784 /* enable VCPU clock */
f78c3422 785 WREG32(mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK);
aaa36a97
AD		 786
787 /* enable UMC */
f4a7f127 788 WREG32_FIELD(UVD_LMI_CTRL2, STALL_ARB_UMC, 0);
aaa36a97
AD		 789
790 /* boot up the VCPU */
791 WREG32(mmUVD_SOFT_RESET, 0);
792 mdelay(10);
793
794 for (i = 0; i < 10; ++i) {
795 uint32_t status;
796
797 for (j = 0; j < 100; ++j) {
798 status = RREG32(mmUVD_STATUS);
799 if (status & 2)
800 break;
801 mdelay(10);
802 }
803 r = 0;
804 if (status & 2)
805 break;
806
807 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
f4a7f127 808 WREG32_FIELD(UVD_SOFT_RESET, VCPU_SOFT_RESET, 1);
aaa36a97 809 mdelay(10);
f4a7f127 810 WREG32_FIELD(UVD_SOFT_RESET, VCPU_SOFT_RESET, 0);
aaa36a97
AD		 811 mdelay(10);
812 r = -1;
813 }
814
815 if (r) {
816 DRM_ERROR("UVD not responding, giving up!!!\n");
817 return r;
818 }
819 /* enable master interrupt */
f78c3422
TSD		 820 WREG32_P(mmUVD_MASTINT_EN,
821 (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
822 ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
aaa36a97
AD		 823
824 /* clear the bit 4 of UVD_STATUS */
f78c3422 825 WREG32_P(mmUVD_STATUS, 0, ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
aaa36a97 826
f4a7f127 827 /* force RBC into idle state */
aaa36a97 828 rb_bufsz = order_base_2(ring->ring_size);
f4a7f127 829 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
aaa36a97
AD		 830 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
831 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
832 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
833 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
834 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
aaa36a97
AD		 835 WREG32(mmUVD_RBC_RB_CNTL, tmp);
836
837 /* set the write pointer delay */
838 WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);
839
840 /* set the wb address */
841 WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2));
842
843 /* programm the RB_BASE for ring buffer */
844 WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
845 lower_32_bits(ring->gpu_addr));
846 WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
847 upper_32_bits(ring->gpu_addr));
848
849 /* Initialize the ring buffer's read and write pointers */
850 WREG32(mmUVD_RBC_RB_RPTR, 0);
851
852 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
536fbf94 853 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
aaa36a97 854
f4a7f127 855 WREG32_FIELD(UVD_RBC_RB_CNTL, RB_NO_FETCH, 0);
aaa36a97 856
06a7e9cb
JZ		 857 if (uvd_v6_0_enc_support(adev)) {
858 ring = &adev->uvd.ring_enc[0];
859 WREG32(mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
860 WREG32(mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
861 WREG32(mmUVD_RB_BASE_LO, ring->gpu_addr);
862 WREG32(mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
863 WREG32(mmUVD_RB_SIZE, ring->ring_size / 4);
864
865 ring = &adev->uvd.ring_enc[1];
866 WREG32(mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
867 WREG32(mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
868 WREG32(mmUVD_RB_BASE_LO2, ring->gpu_addr);
869 WREG32(mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
870 WREG32(mmUVD_RB_SIZE2, ring->ring_size / 4);
871 }
872
aaa36a97
AD		 873 return 0;
874}
875
876/**
877 * uvd_v6_0_stop - stop UVD block
878 *
879 * @adev: amdgpu_device pointer
880 *
881 * stop the UVD block
882 */
883static void uvd_v6_0_stop(struct amdgpu_device *adev)
884{
885 /* force RBC into idle state */
886 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
887
888 /* Stall UMC and register bus before resetting VCPU */
889 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
890 mdelay(1);
891
892 /* put VCPU into reset */
893 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
894 mdelay(5);
895
896 /* disable VCPU clock */
897 WREG32(mmUVD_VCPU_CNTL, 0x0);
898
899 /* Unstall UMC and register bus */
900 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
e3e672e6
RZ		 901
902 WREG32(mmUVD_STATUS, 0);
aaa36a97
AD		 903}
904
905/**
906 * uvd_v6_0_ring_emit_fence - emit an fence & trap command
907 *
908 * @ring: amdgpu_ring pointer
909 * @fence: fence to emit
910 *
911 * Write a fence and a trap command to the ring.
912 */
913static void uvd_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
890ee23f 914 unsigned flags)
aaa36a97 915{
890ee23f 916 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
aaa36a97
AD		 917
918 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
919 amdgpu_ring_write(ring, seq);
920 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
921 amdgpu_ring_write(ring, addr & 0xffffffff);
922 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
923 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
924 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
925 amdgpu_ring_write(ring, 0);
926
927 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
928 amdgpu_ring_write(ring, 0);
929 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
930 amdgpu_ring_write(ring, 0);
931 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
932 amdgpu_ring_write(ring, 2);
933}
934
c0f2f2e6
JZ		 935/**
936 * uvd_v6_0_enc_ring_emit_fence - emit an enc fence & trap command
937 *
938 * @ring: amdgpu_ring pointer
939 * @fence: fence to emit
940 *
941 * Write enc a fence and a trap command to the ring.
942 */
943static void uvd_v6_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
944 u64 seq, unsigned flags)
945{
946 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
947
948 amdgpu_ring_write(ring, HEVC_ENC_CMD_FENCE);
949 amdgpu_ring_write(ring, addr);
950 amdgpu_ring_write(ring, upper_32_bits(addr));
951 amdgpu_ring_write(ring, seq);
952 amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP);
953}
954
d5b4e25d
CK		 955/**
956 * uvd_v6_0_ring_emit_hdp_flush - emit an hdp flush
957 *
958 * @ring: amdgpu_ring pointer
959 *
960 * Emits an hdp flush.
961 */
962static void uvd_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
963{
964 amdgpu_ring_write(ring, PACKET0(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0));
965 amdgpu_ring_write(ring, 0);
966}
967
968/**
969 * uvd_v6_0_ring_hdp_invalidate - emit an hdp invalidate
970 *
971 * @ring: amdgpu_ring pointer
972 *
973 * Emits an hdp invalidate.
974 */
975static void uvd_v6_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
976{
977 amdgpu_ring_write(ring, PACKET0(mmHDP_DEBUG0, 0));
978 amdgpu_ring_write(ring, 1);
979}
980
aaa36a97
AD		 981/**
982 * uvd_v6_0_ring_test_ring - register write test
983 *
984 * @ring: amdgpu_ring pointer
985 *
986 * Test if we can successfully write to the context register
987 */
988static int uvd_v6_0_ring_test_ring(struct amdgpu_ring *ring)
989{
990 struct amdgpu_device *adev = ring->adev;
991 uint32_t tmp = 0;
992 unsigned i;
993 int r;
994
995 WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
a27de35c 996 r = amdgpu_ring_alloc(ring, 3);
aaa36a97
AD		 997 if (r) {
998 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
999 ring->idx, r);
1000 return r;
1001 }
1002 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
1003 amdgpu_ring_write(ring, 0xDEADBEEF);
a27de35c 1004 amdgpu_ring_commit(ring);
aaa36a97
AD		 1005 for (i = 0; i < adev->usec_timeout; i++) {
1006 tmp = RREG32(mmUVD_CONTEXT_ID);
1007 if (tmp == 0xDEADBEEF)
1008 break;
1009 DRM_UDELAY(1);
1010 }
1011
1012 if (i < adev->usec_timeout) {
1013 DRM_INFO("ring test on %d succeeded in %d usecs\n",
1014 ring->idx, i);
1015 } else {
1016 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
1017 ring->idx, tmp);
1018 r = -EINVAL;
1019 }
1020 return r;
1021}
1022
1023/**
1024 * uvd_v6_0_ring_emit_ib - execute indirect buffer
1025 *
1026 * @ring: amdgpu_ring pointer
1027 * @ib: indirect buffer to execute
1028 *
1029 * Write ring commands to execute the indirect buffer
1030 */
1031static void uvd_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
d88bf583
CK		 1032 struct amdgpu_ib *ib,
1033 unsigned vm_id, bool ctx_switch)
aaa36a97 1034{
0f30a397
CK		 1035 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_VMID, 0));
1036 amdgpu_ring_write(ring, vm_id);
1037
aaa36a97
AD		 1038 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0));
1039 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1040 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0));
1041 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1042 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0));
1043 amdgpu_ring_write(ring, ib->length_dw);
1044}
1045
c0f2f2e6
JZ		 1046/**
1047 * uvd_v6_0_enc_ring_emit_ib - enc execute indirect buffer
1048 *
1049 * @ring: amdgpu_ring pointer
1050 * @ib: indirect buffer to execute
1051 *
1052 * Write enc ring commands to execute the indirect buffer
1053 */
1054static void uvd_v6_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1055 struct amdgpu_ib *ib, unsigned int vm_id, bool ctx_switch)
1056{
1057 amdgpu_ring_write(ring, HEVC_ENC_CMD_IB_VM);
1058 amdgpu_ring_write(ring, vm_id);
1059 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1060 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1061 amdgpu_ring_write(ring, ib->length_dw);
1062}
1063
0f30a397
CK		 1064static void uvd_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1065 unsigned vm_id, uint64_t pd_addr)
1066{
1067 uint32_t reg;
1068
1069 if (vm_id < 8)
1070 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id;
1071 else
1072 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8;
1073
1074 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
1075 amdgpu_ring_write(ring, reg << 2);
1076 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
1077 amdgpu_ring_write(ring, pd_addr >> 12);
1078 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
1079 amdgpu_ring_write(ring, 0x8);
1080
1081 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
1082 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
1083 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
1084 amdgpu_ring_write(ring, 1 << vm_id);
1085 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
1086 amdgpu_ring_write(ring, 0x8);
1087
1088 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
1089 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
1090 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
1091 amdgpu_ring_write(ring, 0);
1092 amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0));
1093 amdgpu_ring_write(ring, 1 << vm_id); /* mask */
1094 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
1095 amdgpu_ring_write(ring, 0xC);
1096}
1097
1098static void uvd_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1099{
1100 uint32_t seq = ring->fence_drv.sync_seq;
1101 uint64_t addr = ring->fence_drv.gpu_addr;
1102
1103 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
1104 amdgpu_ring_write(ring, lower_32_bits(addr));
1105 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
1106 amdgpu_ring_write(ring, upper_32_bits(addr));
1107 amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0));
1108 amdgpu_ring_write(ring, 0xffffffff); /* mask */
1109 amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH9, 0));
1110 amdgpu_ring_write(ring, seq);
1111 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
1112 amdgpu_ring_write(ring, 0xE);
1113}
1114
c0f2f2e6
JZ		 1115static void uvd_v6_0_enc_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1116{
1117 uint32_t seq = ring->fence_drv.sync_seq;
1118 uint64_t addr = ring->fence_drv.gpu_addr;
1119
1120 amdgpu_ring_write(ring, HEVC_ENC_CMD_WAIT_GE);
1121 amdgpu_ring_write(ring, lower_32_bits(addr));
1122 amdgpu_ring_write(ring, upper_32_bits(addr));
1123 amdgpu_ring_write(ring, seq);
1124}
1125
1126static void uvd_v6_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1127{
1128 amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
1129}
1130
1131static void uvd_v6_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1132 unsigned int vm_id, uint64_t pd_addr)
1133{
1134 amdgpu_ring_write(ring, HEVC_ENC_CMD_UPDATE_PTB);
1135 amdgpu_ring_write(ring, vm_id);
1136 amdgpu_ring_write(ring, pd_addr >> 12);
1137
1138 amdgpu_ring_write(ring, HEVC_ENC_CMD_FLUSH_TLB);
1139 amdgpu_ring_write(ring, vm_id);
1140}
1141
5fc3aeeb 1142static bool uvd_v6_0_is_idle(void *handle)
aaa36a97 1143{
5fc3aeeb 1144 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1145
aaa36a97
AD		 1146 return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
1147}
1148
5fc3aeeb 1149static int uvd_v6_0_wait_for_idle(void *handle)
aaa36a97
AD		 1150{
1151 unsigned i;
5fc3aeeb 1152 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1153
1154 for (i = 0; i < adev->usec_timeout; i++) {
f4a7f127 1155 if (uvd_v6_0_is_idle(handle))
aaa36a97
AD		 1156 return 0;
1157 }
1158 return -ETIMEDOUT;
1159}
1160
fc0b3b90 1161#define AMDGPU_UVD_STATUS_BUSY_MASK 0xfd
da146d3b 1162static bool uvd_v6_0_check_soft_reset(void *handle)
fc0b3b90
CZ		 1163{
1164 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1165 u32 srbm_soft_reset = 0;
1166 u32 tmp = RREG32(mmSRBM_STATUS);
1167
1168 if (REG_GET_FIELD(tmp, SRBM_STATUS, UVD_RQ_PENDING) ||
1169 REG_GET_FIELD(tmp, SRBM_STATUS, UVD_BUSY) ||
1170 (RREG32(mmUVD_STATUS) & AMDGPU_UVD_STATUS_BUSY_MASK))
1171 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_UVD, 1);
1172
1173 if (srbm_soft_reset) {
fc0b3b90 1174 adev->uvd.srbm_soft_reset = srbm_soft_reset;
da146d3b 1175 return true;
fc0b3b90 1176 } else {
fc0b3b90 1177 adev->uvd.srbm_soft_reset = 0;
da146d3b 1178 return false;
fc0b3b90 1179 }
fc0b3b90 1180}
da146d3b 1181
fc0b3b90 1182static int uvd_v6_0_pre_soft_reset(void *handle)
aaa36a97 1183{
5fc3aeeb 1184 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1185
da146d3b 1186 if (!adev->uvd.srbm_soft_reset)
fc0b3b90
CZ		 1187 return 0;
1188
aaa36a97 1189 uvd_v6_0_stop(adev);
fc0b3b90
CZ		 1190 return 0;
1191}
1192
1193static int uvd_v6_0_soft_reset(void *handle)
1194{
1195 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1196 u32 srbm_soft_reset;
1197
da146d3b 1198 if (!adev->uvd.srbm_soft_reset)
fc0b3b90
CZ		 1199 return 0;
1200 srbm_soft_reset = adev->uvd.srbm_soft_reset;
1201
1202 if (srbm_soft_reset) {
1203 u32 tmp;
1204
1205 tmp = RREG32(mmSRBM_SOFT_RESET);
1206 tmp |= srbm_soft_reset;
1207 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1208 WREG32(mmSRBM_SOFT_RESET, tmp);
1209 tmp = RREG32(mmSRBM_SOFT_RESET);
1210
1211 udelay(50);
1212
1213 tmp &= ~srbm_soft_reset;
1214 WREG32(mmSRBM_SOFT_RESET, tmp);
1215 tmp = RREG32(mmSRBM_SOFT_RESET);
1216
1217 /* Wait a little for things to settle down */
1218 udelay(50);
1219 }
1220
1221 return 0;
1222}
1223
1224static int uvd_v6_0_post_soft_reset(void *handle)
1225{
1226 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1227
da146d3b 1228 if (!adev->uvd.srbm_soft_reset)
fc0b3b90 1229 return 0;
aaa36a97 1230
aaa36a97
AD		 1231 mdelay(5);
1232
1233 return uvd_v6_0_start(adev);
1234}
1235
aaa36a97
AD		 1236static int uvd_v6_0_set_interrupt_state(struct amdgpu_device *adev,
1237 struct amdgpu_irq_src *source,
1238 unsigned type,
1239 enum amdgpu_interrupt_state state)
1240{
1241 // TODO
1242 return 0;
1243}
1244
1245static int uvd_v6_0_process_interrupt(struct amdgpu_device *adev,
1246 struct amdgpu_irq_src *source,
1247 struct amdgpu_iv_entry *entry)
1248{
65da0d40 1249 bool int_handled = true;
aaa36a97 1250 DRM_DEBUG("IH: UVD TRAP\n");
65da0d40
JZ		 1251
1252 switch (entry->src_id) {
1253 case 124:
1254 amdgpu_fence_process(&adev->uvd.ring);
1255 break;
1256 case 119:
1257 if (likely(uvd_v6_0_enc_support(adev)))
1258 amdgpu_fence_process(&adev->uvd.ring_enc[0]);
1259 else
1260 int_handled = false;
1261 break;
1262 case 120:
1263 if (likely(uvd_v6_0_enc_support(adev)))
1264 amdgpu_fence_process(&adev->uvd.ring_enc[1]);
1265 else
1266 int_handled = false;
1267 break;
1268 }
1269
1270 if (false == int_handled)
1271 DRM_ERROR("Unhandled interrupt: %d %d\n",
1272 entry->src_id, entry->src_data[0]);
1273
aaa36a97
AD		 1274 return 0;
1275}
1276
805b3ba8
RZ		 1277static void uvd_v6_0_enable_clock_gating(struct amdgpu_device *adev, bool enable)
1278{
1279 uint32_t data1, data3;
1280
1281 data1 = RREG32(mmUVD_SUVD_CGC_GATE);
1282 data3 = RREG32(mmUVD_CGC_GATE);
1283
1284 data1 |= UVD_SUVD_CGC_GATE__SRE_MASK |
1285 UVD_SUVD_CGC_GATE__SIT_MASK |
1286 UVD_SUVD_CGC_GATE__SMP_MASK |
1287 UVD_SUVD_CGC_GATE__SCM_MASK |
1288 UVD_SUVD_CGC_GATE__SDB_MASK |
1289 UVD_SUVD_CGC_GATE__SRE_H264_MASK |
1290 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK |
1291 UVD_SUVD_CGC_GATE__SIT_H264_MASK |
1292 UVD_SUVD_CGC_GATE__SIT_HEVC_MASK |
1293 UVD_SUVD_CGC_GATE__SCM_H264_MASK |
1294 UVD_SUVD_CGC_GATE__SCM_HEVC_MASK |
1295 UVD_SUVD_CGC_GATE__SDB_H264_MASK |
1296 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK;
1297
1298 if (enable) {
1299 data3 |= (UVD_CGC_GATE__SYS_MASK |
1300 UVD_CGC_GATE__UDEC_MASK |
1301 UVD_CGC_GATE__MPEG2_MASK |
1302 UVD_CGC_GATE__RBC_MASK |
1303 UVD_CGC_GATE__LMI_MC_MASK |
1304 UVD_CGC_GATE__LMI_UMC_MASK |
1305 UVD_CGC_GATE__IDCT_MASK |
1306 UVD_CGC_GATE__MPRD_MASK |
1307 UVD_CGC_GATE__MPC_MASK |
1308 UVD_CGC_GATE__LBSI_MASK |
1309 UVD_CGC_GATE__LRBBM_MASK |
1310 UVD_CGC_GATE__UDEC_RE_MASK |
1311 UVD_CGC_GATE__UDEC_CM_MASK |
1312 UVD_CGC_GATE__UDEC_IT_MASK |
1313 UVD_CGC_GATE__UDEC_DB_MASK |
1314 UVD_CGC_GATE__UDEC_MP_MASK |
1315 UVD_CGC_GATE__WCB_MASK |
805b3ba8
RZ		 1316 UVD_CGC_GATE__JPEG_MASK |
1317 UVD_CGC_GATE__SCPU_MASK |
1318 UVD_CGC_GATE__JPEG2_MASK);
3c3a7e61
RZ		 1319 /* only in pg enabled, we can gate clock to vcpu*/
1320 if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
1321 data3 |= UVD_CGC_GATE__VCPU_MASK;
1322
805b3ba8
RZ		 1323 data3 &= ~UVD_CGC_GATE__REGS_MASK;
1324 } else {
1325 data3 = 0;
1326 }
1327
1328 WREG32(mmUVD_SUVD_CGC_GATE, data1);
1329 WREG32(mmUVD_CGC_GATE, data3);
1330}
1331
be3ecca7
TSD		 1332static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev)
1333{
805b3ba8 1334 uint32_t data, data2;
be3ecca7
TSD		 1335
1336 data = RREG32(mmUVD_CGC_CTRL);
be3ecca7
TSD		 1337 data2 = RREG32(mmUVD_SUVD_CGC_CTRL);
1338
805b3ba8 1339
be3ecca7
TSD		 1340 data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
1341 UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
1342
be3ecca7
TSD		 1343
1344 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
1345 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
1346 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
1347
1348 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
1349 UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
1350 UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
1351 UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
1352 UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
1353 UVD_CGC_CTRL__SYS_MODE_MASK |
1354 UVD_CGC_CTRL__UDEC_MODE_MASK |
1355 UVD_CGC_CTRL__MPEG2_MODE_MASK |
1356 UVD_CGC_CTRL__REGS_MODE_MASK |
1357 UVD_CGC_CTRL__RBC_MODE_MASK |
1358 UVD_CGC_CTRL__LMI_MC_MODE_MASK |
1359 UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
1360 UVD_CGC_CTRL__IDCT_MODE_MASK |
1361 UVD_CGC_CTRL__MPRD_MODE_MASK |
1362 UVD_CGC_CTRL__MPC_MODE_MASK |
1363 UVD_CGC_CTRL__LBSI_MODE_MASK |
1364 UVD_CGC_CTRL__LRBBM_MODE_MASK |
1365 UVD_CGC_CTRL__WCB_MODE_MASK |
1366 UVD_CGC_CTRL__VCPU_MODE_MASK |
1367 UVD_CGC_CTRL__JPEG_MODE_MASK |
1368 UVD_CGC_CTRL__SCPU_MODE_MASK |
1369 UVD_CGC_CTRL__JPEG2_MODE_MASK);
1370 data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
1371 UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |
1372 UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
1373 UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
1374 UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
be3ecca7
TSD		 1375
1376 WREG32(mmUVD_CGC_CTRL, data);
be3ecca7
TSD		 1377 WREG32(mmUVD_SUVD_CGC_CTRL, data2);
1378}
1379
1380#if 0
1381static void uvd_v6_0_set_hw_clock_gating(struct amdgpu_device *adev)
1382{
1383 uint32_t data, data1, cgc_flags, suvd_flags;
1384
1385 data = RREG32(mmUVD_CGC_GATE);
1386 data1 = RREG32(mmUVD_SUVD_CGC_GATE);
1387
1388 cgc_flags = UVD_CGC_GATE__SYS_MASK |
1389 UVD_CGC_GATE__UDEC_MASK |
1390 UVD_CGC_GATE__MPEG2_MASK |
1391 UVD_CGC_GATE__RBC_MASK |
1392 UVD_CGC_GATE__LMI_MC_MASK |
1393 UVD_CGC_GATE__IDCT_MASK |
1394 UVD_CGC_GATE__MPRD_MASK |
1395 UVD_CGC_GATE__MPC_MASK |
1396 UVD_CGC_GATE__LBSI_MASK |
1397 UVD_CGC_GATE__LRBBM_MASK |
1398 UVD_CGC_GATE__UDEC_RE_MASK |
1399 UVD_CGC_GATE__UDEC_CM_MASK |
1400 UVD_CGC_GATE__UDEC_IT_MASK |
1401 UVD_CGC_GATE__UDEC_DB_MASK |
1402 UVD_CGC_GATE__UDEC_MP_MASK |
1403 UVD_CGC_GATE__WCB_MASK |
1404 UVD_CGC_GATE__VCPU_MASK |
1405 UVD_CGC_GATE__SCPU_MASK |
1406 UVD_CGC_GATE__JPEG_MASK |
1407 UVD_CGC_GATE__JPEG2_MASK;
1408
1409 suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
1410 UVD_SUVD_CGC_GATE__SIT_MASK |
1411 UVD_SUVD_CGC_GATE__SMP_MASK |
1412 UVD_SUVD_CGC_GATE__SCM_MASK |
1413 UVD_SUVD_CGC_GATE__SDB_MASK;
1414
1415 data |= cgc_flags;
1416 data1 |= suvd_flags;
1417
1418 WREG32(mmUVD_CGC_GATE, data);
1419 WREG32(mmUVD_SUVD_CGC_GATE, data1);
1420}
1421#endif
1422
805b3ba8
RZ		 1423static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev,
1424 bool enable)
1425{
1426 u32 orig, data;
1427
1428 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) {
1429 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
1430 data |= 0xfff;
1431 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
1432
1433 orig = data = RREG32(mmUVD_CGC_CTRL);
1434 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
1435 if (orig != data)
1436 WREG32(mmUVD_CGC_CTRL, data);
1437 } else {
1438 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
1439 data &= ~0xfff;
1440 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
1441
1442 orig = data = RREG32(mmUVD_CGC_CTRL);
1443 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
1444 if (orig != data)
1445 WREG32(mmUVD_CGC_CTRL, data);
1446 }
1447}
1448
5fc3aeeb 1449static int uvd_v6_0_set_clockgating_state(void *handle,
1450 enum amd_clockgating_state state)
aaa36a97 1451{
9b08a306 1452 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4be5097c 1453 bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
a0cdef9e 1454
4be5097c 1455 if (enable) {
be3ecca7
TSD		 1456 /* wait for STATUS to clear */
1457 if (uvd_v6_0_wait_for_idle(handle))
1458 return -EBUSY;
805b3ba8 1459 uvd_v6_0_enable_clock_gating(adev, true);
be3ecca7
TSD		 1460 /* enable HW gates because UVD is idle */
1461/* uvd_v6_0_set_hw_clock_gating(adev); */
805b3ba8
RZ		 1462 } else {
1463 /* disable HW gating and enable Sw gating */
1464 uvd_v6_0_enable_clock_gating(adev, false);
9b08a306 1465 }
805b3ba8 1466 uvd_v6_0_set_sw_clock_gating(adev);
aaa36a97
AD		 1467 return 0;
1468}
1469
5fc3aeeb 1470static int uvd_v6_0_set_powergating_state(void *handle,
1471 enum amd_powergating_state state)
aaa36a97
AD		 1472{
1473 /* This doesn't actually powergate the UVD block.
1474 * That's done in the dpm code via the SMC. This
1475 * just re-inits the block as necessary. The actual
1476 * gating still happens in the dpm code. We should
1477 * revisit this when there is a cleaner line between
1478 * the smc and the hw blocks
1479 */
5fc3aeeb 1480 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
c8781f56 1481 int ret = 0;
5fc3aeeb 1482
fa5d2e0c
TSD		 1483 WREG32(mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
1484
5fc3aeeb 1485 if (state == AMD_PG_STATE_GATE) {
aaa36a97 1486 uvd_v6_0_stop(adev);
aaa36a97 1487 } else {
c8781f56
HR		 1488 ret = uvd_v6_0_start(adev);
1489 if (ret)
1490 goto out;
c8781f56
HR		 1491 }
1492
1493out:
1494 return ret;
1495}
1496
1497static void uvd_v6_0_get_clockgating_state(void *handle, u32 *flags)
1498{
1499 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1500 int data;
1501
1502 mutex_lock(&adev->pm.mutex);
1503
1c622002
RZ		 1504 if (adev->flags & AMD_IS_APU)
1505 data = RREG32_SMC(ixCURRENT_PG_STATUS_APU);
1506 else
1507 data = RREG32_SMC(ixCURRENT_PG_STATUS);
1508
1509 if (data & CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) {
c8781f56
HR		 1510 DRM_INFO("Cannot get clockgating state when UVD is powergated.\n");
1511 goto out;
aaa36a97 1512 }
c8781f56
HR		 1513
1514 /* AMD_CG_SUPPORT_UVD_MGCG */
1515 data = RREG32(mmUVD_CGC_CTRL);
1516 if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK)
1517 *flags |= AMD_CG_SUPPORT_UVD_MGCG;
1518
1519out:
1520 mutex_unlock(&adev->pm.mutex);
aaa36a97
AD		 1521}
1522
a1255107 1523static const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
88a907d6 1524 .name = "uvd_v6_0",
aaa36a97
AD		 1525 .early_init = uvd_v6_0_early_init,
1526 .late_init = NULL,
1527 .sw_init = uvd_v6_0_sw_init,
1528 .sw_fini = uvd_v6_0_sw_fini,
1529 .hw_init = uvd_v6_0_hw_init,
1530 .hw_fini = uvd_v6_0_hw_fini,
1531 .suspend = uvd_v6_0_suspend,
1532 .resume = uvd_v6_0_resume,
1533 .is_idle = uvd_v6_0_is_idle,
1534 .wait_for_idle = uvd_v6_0_wait_for_idle,
fc0b3b90
CZ		 1535 .check_soft_reset = uvd_v6_0_check_soft_reset,
1536 .pre_soft_reset = uvd_v6_0_pre_soft_reset,
aaa36a97 1537 .soft_reset = uvd_v6_0_soft_reset,
fc0b3b90 1538 .post_soft_reset = uvd_v6_0_post_soft_reset,
aaa36a97
AD		 1539 .set_clockgating_state = uvd_v6_0_set_clockgating_state,
1540 .set_powergating_state = uvd_v6_0_set_powergating_state,
c8781f56 1541 .get_clockgating_state = uvd_v6_0_get_clockgating_state,
aaa36a97
AD		 1542};
1543
0f30a397 1544static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = {
21cd942e 1545 .type = AMDGPU_RING_TYPE_UVD,
79887142
CK		 1546 .align_mask = 0xf,
1547 .nop = PACKET0(mmUVD_NO_OP, 0),
536fbf94 1548 .support_64bit_ptrs = false,
aaa36a97
AD		 1549 .get_rptr = uvd_v6_0_ring_get_rptr,
1550 .get_wptr = uvd_v6_0_ring_get_wptr,
1551 .set_wptr = uvd_v6_0_ring_set_wptr,
1552 .parse_cs = amdgpu_uvd_ring_parse_cs,
e12f3d7a
CK		 1553 .emit_frame_size =
1554 2 + /* uvd_v6_0_ring_emit_hdp_flush */
1555 2 + /* uvd_v6_0_ring_emit_hdp_invalidate */
1556 10 + /* uvd_v6_0_ring_emit_pipeline_sync */
1557 14, /* uvd_v6_0_ring_emit_fence x1 no user fence */
1558 .emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */
aaa36a97
AD		 1559 .emit_ib = uvd_v6_0_ring_emit_ib,
1560 .emit_fence = uvd_v6_0_ring_emit_fence,
d5b4e25d
CK		 1561 .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush,
1562 .emit_hdp_invalidate = uvd_v6_0_ring_emit_hdp_invalidate,
aaa36a97 1563 .test_ring = uvd_v6_0_ring_test_ring,
8de190c9 1564 .test_ib = amdgpu_uvd_ring_test_ib,
edff0e28 1565 .insert_nop = amdgpu_ring_insert_nop,
9e5d5309 1566 .pad_ib = amdgpu_ring_generic_pad_ib,
c4120d55
CK		 1567 .begin_use = amdgpu_uvd_ring_begin_use,
1568 .end_use = amdgpu_uvd_ring_end_use,
aaa36a97
AD		 1569};
1570
0f30a397 1571static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = {
21cd942e 1572 .type = AMDGPU_RING_TYPE_UVD,
79887142
CK		 1573 .align_mask = 0xf,
1574 .nop = PACKET0(mmUVD_NO_OP, 0),
536fbf94 1575 .support_64bit_ptrs = false,
0f30a397
CK		 1576 .get_rptr = uvd_v6_0_ring_get_rptr,
1577 .get_wptr = uvd_v6_0_ring_get_wptr,
1578 .set_wptr = uvd_v6_0_ring_set_wptr,
e12f3d7a
CK		 1579 .emit_frame_size =
1580 2 + /* uvd_v6_0_ring_emit_hdp_flush */
1581 2 + /* uvd_v6_0_ring_emit_hdp_invalidate */
1582 10 + /* uvd_v6_0_ring_emit_pipeline_sync */
1583 20 + /* uvd_v6_0_ring_emit_vm_flush */
1584 14 + 14, /* uvd_v6_0_ring_emit_fence x2 vm fence */
1585 .emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */
0f30a397
CK		 1586 .emit_ib = uvd_v6_0_ring_emit_ib,
1587 .emit_fence = uvd_v6_0_ring_emit_fence,
1588 .emit_vm_flush = uvd_v6_0_ring_emit_vm_flush,
1589 .emit_pipeline_sync = uvd_v6_0_ring_emit_pipeline_sync,
1590 .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush,
1591 .emit_hdp_invalidate = uvd_v6_0_ring_emit_hdp_invalidate,
1592 .test_ring = uvd_v6_0_ring_test_ring,
8de190c9 1593 .test_ib = amdgpu_uvd_ring_test_ib,
0f30a397
CK		 1594 .insert_nop = amdgpu_ring_insert_nop,
1595 .pad_ib = amdgpu_ring_generic_pad_ib,
c4120d55
CK		 1596 .begin_use = amdgpu_uvd_ring_begin_use,
1597 .end_use = amdgpu_uvd_ring_end_use,
0f30a397
CK		 1598};
1599
c259ee6e
JZ		 1600static const struct amdgpu_ring_funcs uvd_v6_0_enc_ring_vm_funcs = {
1601 .type = AMDGPU_RING_TYPE_UVD_ENC,
1602 .align_mask = 0x3f,
1603 .nop = HEVC_ENC_CMD_NO_OP,
1604 .support_64bit_ptrs = false,
1605 .get_rptr = uvd_v6_0_enc_ring_get_rptr,
1606 .get_wptr = uvd_v6_0_enc_ring_get_wptr,
1607 .set_wptr = uvd_v6_0_enc_ring_set_wptr,
1608 .emit_frame_size =
1609 4 + /* uvd_v6_0_enc_ring_emit_pipeline_sync */
1610 6 + /* uvd_v6_0_enc_ring_emit_vm_flush */
1611 5 + 5 + /* uvd_v6_0_enc_ring_emit_fence x2 vm fence */
1612 1, /* uvd_v6_0_enc_ring_insert_end */
1613 .emit_ib_size = 5, /* uvd_v6_0_enc_ring_emit_ib */
1614 .emit_ib = uvd_v6_0_enc_ring_emit_ib,
1615 .emit_fence = uvd_v6_0_enc_ring_emit_fence,
1616 .emit_vm_flush = uvd_v6_0_enc_ring_emit_vm_flush,
1617 .emit_pipeline_sync = uvd_v6_0_enc_ring_emit_pipeline_sync,
2a91f272 1618 .test_ring = uvd_v6_0_enc_ring_test_ring,
e0128efb 1619 .test_ib = uvd_v6_0_enc_ring_test_ib,
c259ee6e
JZ		 1620 .insert_nop = amdgpu_ring_insert_nop,
1621 .insert_end = uvd_v6_0_enc_ring_insert_end,
1622 .pad_ib = amdgpu_ring_generic_pad_ib,
1623 .begin_use = amdgpu_uvd_ring_begin_use,
1624 .end_use = amdgpu_uvd_ring_end_use,
1625};
1626
aaa36a97
AD		 1627static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev)
1628{
a05c92d1 1629 if (adev->asic_type >= CHIP_POLARIS10) {
0f30a397
CK		 1630 adev->uvd.ring.funcs = &uvd_v6_0_ring_vm_funcs;
1631 DRM_INFO("UVD is enabled in VM mode\n");
1632 } else {
1633 adev->uvd.ring.funcs = &uvd_v6_0_ring_phys_funcs;
1634 DRM_INFO("UVD is enabled in physical mode\n");
1635 }
aaa36a97
AD		 1636}
1637
c259ee6e
JZ		 1638static void uvd_v6_0_set_enc_ring_funcs(struct amdgpu_device *adev)
1639{
1640 int i;
1641
1642 for (i = 0; i < adev->uvd.num_enc_rings; ++i)
1643 adev->uvd.ring_enc[i].funcs = &uvd_v6_0_enc_ring_vm_funcs;
1644
1645 DRM_INFO("UVD ENC is enabled in VM mode\n");
1646}
1647
aaa36a97
AD		 1648static const struct amdgpu_irq_src_funcs uvd_v6_0_irq_funcs = {
1649 .set = uvd_v6_0_set_interrupt_state,
1650 .process = uvd_v6_0_process_interrupt,
1651};
1652
1653static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev)
1654{
65da0d40
JZ		 1655 if (uvd_v6_0_enc_support(adev))
1656 adev->uvd.irq.num_types = adev->uvd.num_enc_rings + 1;
1657 else
1658 adev->uvd.irq.num_types = 1;
1659
aaa36a97
AD		 1660 adev->uvd.irq.funcs = &uvd_v6_0_irq_funcs;
1661}
a1255107
AD		 1662
1663const struct amdgpu_ip_block_version uvd_v6_0_ip_block =
1664{
1665 .type = AMD_IP_BLOCK_TYPE_UVD,
1666 .major = 6,
1667 .minor = 0,
1668 .rev = 0,
1669 .funcs = &uvd_v6_0_ip_funcs,
1670};
1671
1672const struct amdgpu_ip_block_version uvd_v6_2_ip_block =
1673{
1674 .type = AMD_IP_BLOCK_TYPE_UVD,
1675 .major = 6,
1676 .minor = 2,
1677 .rev = 0,
1678 .funcs = &uvd_v6_0_ip_funcs,
1679};
1680
1681const struct amdgpu_ip_block_version uvd_v6_3_ip_block =
1682{
1683 .type = AMD_IP_BLOCK_TYPE_UVD,
1684 .major = 6,
1685 .minor = 3,
1686 .rev = 0,
1687 .funcs = &uvd_v6_0_ip_funcs,
1688};
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