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Merge existing fixes from regmap/for-5.8
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / amdgpu / vcn_v2_0.c
CommitLineData
1b61de45
LL		 1/*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/firmware.h>
9a2ffeb5 25
1b61de45
LL		 26#include "amdgpu.h"
27#include "amdgpu_vcn.h"
28#include "soc15.h"
29#include "soc15d.h"
c113ba15 30#include "amdgpu_pm.h"
dc8ae677 31#include "amdgpu_psp.h"
dd26858a 32#include "mmsch_v2_0.h"
1b61de45
LL		 33
34#include "vcn/vcn_2_0_0_offset.h"
35#include "vcn/vcn_2_0_0_sh_mask.h"
36#include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
37
38#define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x1fd
39#define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x503
40#define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET 0x504
41#define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET 0x505
42#define mmUVD_NO_OP_INTERNAL_OFFSET 0x53f
43#define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET 0x54a
44#define mmUVD_SCRATCH9_INTERNAL_OFFSET 0xc01d
45
46#define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x1e1
47#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x5a6
48#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x5a7
49#define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x1e2
1b61de45 50
1b61de45
LL		 51static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev);
52static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev);
1b61de45
LL		 53static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev);
54static int vcn_v2_0_set_powergating_state(void *handle,
55 enum amd_powergating_state state);
7282da0b 56static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,
597e6ac3 57 int inst_idx, struct dpg_pause_state *new_state);
dd26858a 58static int vcn_v2_0_start_sriov(struct amdgpu_device *adev);
1b61de45
LL		 59/**
60 * vcn_v2_0_early_init - set function pointers
61 *
62 * @handle: amdgpu_device pointer
63 *
64 * Set ring and irq function pointers
65 */
66static int vcn_v2_0_early_init(void *handle)
67{
68 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
69
c01b6a1d 70 adev->vcn.num_vcn_inst = 1;
dd26858a
ML		 71 if (amdgpu_sriov_vf(adev))
72 adev->vcn.num_enc_rings = 1;
73 else
74 adev->vcn.num_enc_rings = 2;
1b61de45
LL		 75
76 vcn_v2_0_set_dec_ring_funcs(adev);
77 vcn_v2_0_set_enc_ring_funcs(adev);
1b61de45
LL		 78 vcn_v2_0_set_irq_funcs(adev);
79
80 return 0;
81}
82
83/**
84 * vcn_v2_0_sw_init - sw init for VCN block
85 *
86 * @handle: amdgpu_device pointer
87 *
88 * Load firmware and sw initialization
89 */
90static int vcn_v2_0_sw_init(void *handle)
91{
92 struct amdgpu_ring *ring;
93 int i, r;
94 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
93521410 95 volatile struct amdgpu_fw_shared *fw_shared;
1b61de45
LL		 96
97 /* VCN DEC TRAP */
98 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
99 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT,
c01b6a1d 100 &adev->vcn.inst->irq);
1b61de45
LL		 101 if (r)
102 return r;
103
104 /* VCN ENC TRAP */
105 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
106 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
107 i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE,
c01b6a1d 108 &adev->vcn.inst->irq);
1b61de45
LL		 109 if (r)
110 return r;
111 }
112
1b61de45
LL		 113 r = amdgpu_vcn_sw_init(adev);
114 if (r)
115 return r;
116
117 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
118 const struct common_firmware_header *hdr;
119 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
120 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN;
121 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
122 adev->firmware.fw_size +=
123 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
124 DRM_INFO("PSP loading VCN firmware\n");
125 }
126
127 r = amdgpu_vcn_resume(adev);
128 if (r)
129 return r;
130
c01b6a1d 131 ring = &adev->vcn.inst->ring_dec;
1b61de45
LL		 132
133 ring->use_doorbell = true;
134 ring->doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1 << 1;
135
136 sprintf(ring->name, "vcn_dec");
1c6d567b
ND		 137 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,
138 AMDGPU_RING_PRIO_DEFAULT);
1b61de45
LL		 139 if (r)
140 return r;
141
22a8f442
LL		 142 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;
143 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;
144 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;
145 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;
146 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;
147 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;
148
1b61de45 149 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;
c01b6a1d 150 adev->vcn.inst->external.scratch9 = SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9);
1b61de45 151 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;
c01b6a1d 152 adev->vcn.inst->external.data0 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0);
1b61de45 153 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;
c01b6a1d 154 adev->vcn.inst->external.data1 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1);
1b61de45 155 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;
c01b6a1d 156 adev->vcn.inst->external.cmd = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD);
1b61de45 157 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;
c01b6a1d 158 adev->vcn.inst->external.nop = SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP);
1b61de45
LL		 159
160 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
c01b6a1d 161 ring = &adev->vcn.inst->ring_enc[i];
1b61de45 162 ring->use_doorbell = true;
dd26858a
ML		 163 if (!amdgpu_sriov_vf(adev))
164 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + i;
165 else
166 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + i;
1b61de45 167 sprintf(ring->name, "vcn_enc%d", i);
1c6d567b
ND		 168 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,
169 AMDGPU_RING_PRIO_DEFAULT);
1b61de45
LL		 170 if (r)
171 return r;
172 }
173
7282da0b
LL		 174 adev->vcn.pause_dpg_mode = vcn_v2_0_pause_dpg_mode;
175
dd26858a
ML		 176 r = amdgpu_virt_alloc_mm_table(adev);
177 if (r)
178 return r;
179
93521410
JZ		 180 fw_shared = adev->vcn.inst->fw_shared_cpu_addr;
181 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG);
1b61de45
LL		 182 return 0;
183}
184
185/**
186 * vcn_v2_0_sw_fini - sw fini for VCN block
187 *
188 * @handle: amdgpu_device pointer
189 *
190 * VCN suspend and free up sw allocation
191 */
192static int vcn_v2_0_sw_fini(void *handle)
193{
194 int r;
195 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
93521410
JZ		 196 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared_cpu_addr;
197
198 fw_shared->present_flag_0 = 0;
1b61de45 199
dd26858a
ML		 200 amdgpu_virt_free_mm_table(adev);
201
1b61de45
LL		 202 r = amdgpu_vcn_suspend(adev);
203 if (r)
204 return r;
205
206 r = amdgpu_vcn_sw_fini(adev);
207
208 return r;
209}
210
211/**
212 * vcn_v2_0_hw_init - start and test VCN block
213 *
214 * @handle: amdgpu_device pointer
215 *
216 * Initialize the hardware, boot up the VCPU and do some testing
217 */
218static int vcn_v2_0_hw_init(void *handle)
219{
220 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
c01b6a1d 221 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
1b61de45
LL		 222 int i, r;
223
bebc0762 224 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
989b6a05 225 ring->doorbell_index, 0);
1b61de45 226
dd26858a
ML		 227 if (amdgpu_sriov_vf(adev))
228 vcn_v2_0_start_sriov(adev);
229
fd287c8c
LL		 230 r = amdgpu_ring_test_helper(ring);
231 if (r)
1b61de45 232 goto done;
1b61de45 233
ad31da43
ED		 234 //Disable vcn decode for sriov
235 if (amdgpu_sriov_vf(adev))
236 ring->sched.ready = false;
237
1b61de45 238 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
c01b6a1d 239 ring = &adev->vcn.inst->ring_enc[i];
fd287c8c
LL		 240 r = amdgpu_ring_test_helper(ring);
241 if (r)
1b61de45 242 goto done;
1b61de45
LL		 243 }
244
1b61de45
LL		 245done:
246 if (!r)
bf4865b5
LL		 247 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n",
248 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode");
1b61de45
LL		 249
250 return r;
251}
252
253/**
254 * vcn_v2_0_hw_fini - stop the hardware block
255 *
256 * @handle: amdgpu_device pointer
257 *
258 * Stop the VCN block, mark ring as not ready any more
259 */
260static int vcn_v2_0_hw_fini(void *handle)
261{
262 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1b61de45 263
bf4865b5
LL		 264 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
265 (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
266 RREG32_SOC15(VCN, 0, mmUVD_STATUS)))
1b61de45
LL		 267 vcn_v2_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
268
1b61de45
LL		 269 return 0;
270}
271
272/**
273 * vcn_v2_0_suspend - suspend VCN block
274 *
275 * @handle: amdgpu_device pointer
276 *
277 * HW fini and suspend VCN block
278 */
279static int vcn_v2_0_suspend(void *handle)
280{
281 int r;
282 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
283
284 r = vcn_v2_0_hw_fini(adev);
285 if (r)
286 return r;
287
288 r = amdgpu_vcn_suspend(adev);
289
290 return r;
291}
292
293/**
294 * vcn_v2_0_resume - resume VCN block
295 *
296 * @handle: amdgpu_device pointer
297 *
298 * Resume firmware and hw init VCN block
299 */
300static int vcn_v2_0_resume(void *handle)
301{
302 int r;
303 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
304
305 r = amdgpu_vcn_resume(adev);
306 if (r)
307 return r;
308
309 r = vcn_v2_0_hw_init(adev);
310
311 return r;
312}
313
314/**
315 * vcn_v2_0_mc_resume - memory controller programming
316 *
317 * @adev: amdgpu_device pointer
318 *
319 * Let the VCN memory controller know it's offsets
320 */
321static void vcn_v2_0_mc_resume(struct amdgpu_device *adev)
322{
323 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
324 uint32_t offset;
325
cc9f2fba
ML		 326 if (amdgpu_sriov_vf(adev))
327 return;
328
1b61de45
LL		 329 /* cache window 0: fw */
330 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
331 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
332 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));
333 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
334 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi));
335 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
336 offset = 0;
337 } else {
338 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
c01b6a1d 339 lower_32_bits(adev->vcn.inst->gpu_addr));
1b61de45 340 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
c01b6a1d 341 upper_32_bits(adev->vcn.inst->gpu_addr));
1b61de45 342 offset = size;
1b61de45
LL		 343 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
344 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
1b61de45
LL		 345 }
346
347 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
348
349 /* cache window 1: stack */
350 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
c01b6a1d 351 lower_32_bits(adev->vcn.inst->gpu_addr + offset));
1b61de45 352 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
c01b6a1d 353 upper_32_bits(adev->vcn.inst->gpu_addr + offset));
1b61de45
LL		 354 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0);
355 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
356
357 /* cache window 2: context */
358 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
c01b6a1d 359 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
1b61de45 360 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
c01b6a1d 361 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
1b61de45
LL		 362 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);
363 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
364
93521410
JZ		 365 /* non-cache window */
366 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,
367 lower_32_bits(adev->vcn.inst->fw_shared_gpu_addr));
368 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,
369 upper_32_bits(adev->vcn.inst->fw_shared_gpu_addr));
370 WREG32_SOC15(UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0, 0);
371 WREG32_SOC15(UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0,
372 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)));
373
1b61de45 374 WREG32_SOC15(UVD, 0, mmUVD_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
1b61de45
LL		 375}
376
bf4865b5
LL		 377static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device *adev, bool indirect)
378{
379 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
380 uint32_t offset;
381
382 /* cache window 0: fw */
383 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
dc8ae677 384 if (!indirect) {
5db86843 385 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
dc8ae677
LL		 386 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
387 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 0, indirect);
5db86843 388 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
dc8ae677
LL		 389 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
390 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 0, indirect);
5db86843 391 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
dc8ae677
LL		 392 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
393 } else {
5db86843 394 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
dc8ae677 395 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
5db86843 396 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
dc8ae677 397 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
5db86843 398 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
dc8ae677
LL		 399 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
400 }
bf4865b5
LL		 401 offset = 0;
402 } else {
5db86843 403 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5 404 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
c01b6a1d 405 lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);
5db86843 406 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5 407 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
c01b6a1d 408 upper_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);
bf4865b5 409 offset = size;
5db86843 410 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 411 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0),
412 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
413 }
414
dc8ae677 415 if (!indirect)
5db86843 416 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
dc8ae677
LL		 417 UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
418 else
5db86843 419 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
dc8ae677 420 UVD, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
bf4865b5
LL		 421
422 /* cache window 1: stack */
dc8ae677 423 if (!indirect) {
5db86843 424 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
dc8ae677 425 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
c01b6a1d 426 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect);
5db86843 427 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
dc8ae677 428 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
c01b6a1d 429 upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect);
5db86843 430 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
dc8ae677
LL		 431 UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
432 } else {
5db86843 433 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
dc8ae677 434 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
5db86843 435 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
dc8ae677 436 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
5db86843 437 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
dc8ae677
LL		 438 UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
439 }
5db86843 440 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 441 UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
442
443 /* cache window 2: context */
5db86843 444 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5 445 UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
c01b6a1d 446 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
5db86843 447 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5 448 UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
c01b6a1d 449 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
5db86843 450 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5 451 UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
5db86843 452 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 453 UVD, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
454
455 /* non-cache window */
5db86843 456 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
93521410
JZ		 457 UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
458 lower_32_bits(adev->vcn.inst->fw_shared_gpu_addr), 0, indirect);
5db86843 459 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
93521410
JZ		 460 UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
461 upper_32_bits(adev->vcn.inst->fw_shared_gpu_addr), 0, indirect);
5db86843 462 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5 463 UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
5db86843 464 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
93521410
JZ		 465 UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0),
466 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect);
bf4865b5
LL		 467
468 /* VCN global tiling registers */
5db86843 469 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 470 UVD, 0, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
471}
472
1b61de45
LL		 473/**
474 * vcn_v2_0_disable_clock_gating - disable VCN clock gating
475 *
476 * @adev: amdgpu_device pointer
477 * @sw: enable SW clock gating
478 *
479 * Disable clock gating for VCN block
480 */
481static void vcn_v2_0_disable_clock_gating(struct amdgpu_device *adev)
482{
483 uint32_t data;
484
cc9f2fba
ML		 485 if (amdgpu_sriov_vf(adev))
486 return;
487
1b61de45
LL		 488 /* UVD disable CGC */
489 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
490 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
491 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
492 else
493 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
494 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
495 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
496 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
497
498 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE);
499 data &= ~(UVD_CGC_GATE__SYS_MASK
500 | UVD_CGC_GATE__UDEC_MASK
501 | UVD_CGC_GATE__MPEG2_MASK
502 | UVD_CGC_GATE__REGS_MASK
503 | UVD_CGC_GATE__RBC_MASK
504 | UVD_CGC_GATE__LMI_MC_MASK
505 | UVD_CGC_GATE__LMI_UMC_MASK
506 | UVD_CGC_GATE__IDCT_MASK
507 | UVD_CGC_GATE__MPRD_MASK
508 | UVD_CGC_GATE__MPC_MASK
509 | UVD_CGC_GATE__LBSI_MASK
510 | UVD_CGC_GATE__LRBBM_MASK
511 | UVD_CGC_GATE__UDEC_RE_MASK
512 | UVD_CGC_GATE__UDEC_CM_MASK
513 | UVD_CGC_GATE__UDEC_IT_MASK
514 | UVD_CGC_GATE__UDEC_DB_MASK
515 | UVD_CGC_GATE__UDEC_MP_MASK
516 | UVD_CGC_GATE__WCB_MASK
517 | UVD_CGC_GATE__VCPU_MASK
518 | UVD_CGC_GATE__SCPU_MASK);
519 WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data);
520
521 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
522 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
523 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
524 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
525 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
526 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
527 | UVD_CGC_CTRL__SYS_MODE_MASK
528 | UVD_CGC_CTRL__UDEC_MODE_MASK
529 | UVD_CGC_CTRL__MPEG2_MODE_MASK
530 | UVD_CGC_CTRL__REGS_MODE_MASK
531 | UVD_CGC_CTRL__RBC_MODE_MASK
532 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
533 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
534 | UVD_CGC_CTRL__IDCT_MODE_MASK
535 | UVD_CGC_CTRL__MPRD_MODE_MASK
536 | UVD_CGC_CTRL__MPC_MODE_MASK
537 | UVD_CGC_CTRL__LBSI_MODE_MASK
538 | UVD_CGC_CTRL__LRBBM_MODE_MASK
539 | UVD_CGC_CTRL__WCB_MODE_MASK
540 | UVD_CGC_CTRL__VCPU_MODE_MASK
541 | UVD_CGC_CTRL__SCPU_MODE_MASK);
542 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
543
544 /* turn on */
545 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE);
546 data |= (UVD_SUVD_CGC_GATE__SRE_MASK
547 | UVD_SUVD_CGC_GATE__SIT_MASK
548 | UVD_SUVD_CGC_GATE__SMP_MASK
549 | UVD_SUVD_CGC_GATE__SCM_MASK
550 | UVD_SUVD_CGC_GATE__SDB_MASK
551 | UVD_SUVD_CGC_GATE__SRE_H264_MASK
552 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
553 | UVD_SUVD_CGC_GATE__SIT_H264_MASK
554 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
555 | UVD_SUVD_CGC_GATE__SCM_H264_MASK
556 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
557 | UVD_SUVD_CGC_GATE__SDB_H264_MASK
558 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
559 | UVD_SUVD_CGC_GATE__SCLR_MASK
560 | UVD_SUVD_CGC_GATE__UVD_SC_MASK
561 | UVD_SUVD_CGC_GATE__ENT_MASK
562 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
563 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
564 | UVD_SUVD_CGC_GATE__SITE_MASK
565 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
566 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
567 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
568 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
569 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
570 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data);
571
572 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
573 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
574 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
575 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
576 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
577 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
578 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
579 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
580 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
581 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
582 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
583 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
584}
585
bf4865b5
LL		 586static void vcn_v2_0_clock_gating_dpg_mode(struct amdgpu_device *adev,
587 uint8_t sram_sel, uint8_t indirect)
588{
589 uint32_t reg_data = 0;
590
591 /* enable sw clock gating control */
592 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
593 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
594 else
595 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
596 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
597 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
598 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
599 UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
600 UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
601 UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
602 UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
603 UVD_CGC_CTRL__SYS_MODE_MASK |
604 UVD_CGC_CTRL__UDEC_MODE_MASK |
605 UVD_CGC_CTRL__MPEG2_MODE_MASK |
606 UVD_CGC_CTRL__REGS_MODE_MASK |
607 UVD_CGC_CTRL__RBC_MODE_MASK |
608 UVD_CGC_CTRL__LMI_MC_MODE_MASK |
609 UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
610 UVD_CGC_CTRL__IDCT_MODE_MASK |
611 UVD_CGC_CTRL__MPRD_MODE_MASK |
612 UVD_CGC_CTRL__MPC_MODE_MASK |
613 UVD_CGC_CTRL__LBSI_MODE_MASK |
614 UVD_CGC_CTRL__LRBBM_MODE_MASK |
615 UVD_CGC_CTRL__WCB_MODE_MASK |
616 UVD_CGC_CTRL__VCPU_MODE_MASK |
617 UVD_CGC_CTRL__SCPU_MODE_MASK);
5db86843 618 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 619 UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
620
621 /* turn off clock gating */
5db86843 622 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 623 UVD, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect);
624
625 /* turn on SUVD clock gating */
5db86843 626 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 627 UVD, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
628
629 /* turn on sw mode in UVD_SUVD_CGC_CTRL */
5db86843 630 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 631 UVD, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
632}
633
1b61de45
LL		 634/**
635 * vcn_v2_0_enable_clock_gating - enable VCN clock gating
636 *
637 * @adev: amdgpu_device pointer
638 * @sw: enable SW clock gating
639 *
640 * Enable clock gating for VCN block
641 */
642static void vcn_v2_0_enable_clock_gating(struct amdgpu_device *adev)
643{
644 uint32_t data = 0;
645
cc9f2fba
ML		 646 if (amdgpu_sriov_vf(adev))
647 return;
648
1b61de45
LL		 649 /* enable UVD CGC */
650 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
651 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
652 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
653 else
654 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
655 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
656 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
657 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
658
659 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
660 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
661 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
662 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
663 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
664 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
665 | UVD_CGC_CTRL__SYS_MODE_MASK
666 | UVD_CGC_CTRL__UDEC_MODE_MASK
667 | UVD_CGC_CTRL__MPEG2_MODE_MASK
668 | UVD_CGC_CTRL__REGS_MODE_MASK
669 | UVD_CGC_CTRL__RBC_MODE_MASK
670 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
671 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
672 | UVD_CGC_CTRL__IDCT_MODE_MASK
673 | UVD_CGC_CTRL__MPRD_MODE_MASK
674 | UVD_CGC_CTRL__MPC_MODE_MASK
675 | UVD_CGC_CTRL__LBSI_MODE_MASK
676 | UVD_CGC_CTRL__LRBBM_MODE_MASK
677 | UVD_CGC_CTRL__WCB_MODE_MASK
678 | UVD_CGC_CTRL__VCPU_MODE_MASK
679 | UVD_CGC_CTRL__SCPU_MODE_MASK);
680 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
681
682 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
683 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
684 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
685 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
686 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
687 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
688 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
689 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
690 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
691 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
692 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
693 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
694}
695
696static void vcn_v2_0_disable_static_power_gating(struct amdgpu_device *adev)
697{
698 uint32_t data = 0;
699 int ret;
700
cc9f2fba
ML		 701 if (amdgpu_sriov_vf(adev))
702 return;
703
1b61de45
LL		 704 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
705 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
706 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
707 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
708 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
709 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
710 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
711 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
712 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
713 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
863dd269 714 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT);
1b61de45
LL		 715
716 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
717 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS,
863dd269 718 UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON_2_0, 0xFFFFF, ret);
1b61de45
LL		 719 } else {
720 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
721 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
722 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
723 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
724 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
725 | 1 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
726 | 1 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
727 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
728 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
863dd269 729 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT);
1b61de45 730 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
863dd269 731 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFF, ret);
1b61de45
LL		 732 }
733
734 /* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS,
735 * UVDU_PWR_STATUS are 0 (power on) */
736
737 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
738 data &= ~0x103;
739 if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
740 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON |
741 UVD_POWER_STATUS__UVD_PG_EN_MASK;
742
743 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
744}
745
746static void vcn_v2_0_enable_static_power_gating(struct amdgpu_device *adev)
747{
748 uint32_t data = 0;
749 int ret;
750
cc9f2fba
ML		 751 if (amdgpu_sriov_vf(adev))
752 return;
753
1b61de45
LL		 754 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
755 /* Before power off, this indicator has to be turned on */
756 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
757 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK;
758 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF;
759 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
760
761
762 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
763 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
764 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
765 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
766 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
767 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
768 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
769 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
770 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
863dd269 771 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT);
1b61de45
LL		 772
773 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
774
775 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT
776 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT
777 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT
778 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT
779 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT
780 | 2 << UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT
781 | 2 << UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT
782 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT
783 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT
863dd269
LL		 784 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT);
785 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFF, ret);
1b61de45
LL		 786 }
787}
788
bf4865b5
LL		 789static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect)
790{
93521410 791 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared_cpu_addr;
c01b6a1d 792 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
bf4865b5
LL		 793 uint32_t rb_bufsz, tmp;
794
795 vcn_v2_0_enable_static_power_gating(adev);
796
797 /* enable dynamic power gating mode */
798 tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);
799 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
800 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
801 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp);
802
dc8ae677 803 if (indirect)
5db86843 804 adev->vcn.inst->dpg_sram_curr_addr = (uint32_t*)adev->vcn.inst->dpg_sram_cpu_addr;
dc8ae677 805
bf4865b5
LL		 806 /* enable clock gating */
807 vcn_v2_0_clock_gating_dpg_mode(adev, 0, indirect);
808
809 /* enable VCPU clock */
810 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
811 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
812 tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK;
5db86843 813 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 814 UVD, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);
815
816 /* disable master interupt */
5db86843 817 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 818 UVD, 0, mmUVD_MASTINT_EN), 0, 0, indirect);
819
820 /* setup mmUVD_LMI_CTRL */
821 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
822 UVD_LMI_CTRL__REQ_MODE_MASK |
823 UVD_LMI_CTRL__CRC_RESET_MASK |
824 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
825 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
826 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
827 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
828 0x00100000L);
5db86843 829 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 830 UVD, 0, mmUVD_LMI_CTRL), tmp, 0, indirect);
831
5db86843 832 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 833 UVD, 0, mmUVD_MPC_CNTL),
834 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
835
5db86843 836 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 837 UVD, 0, mmUVD_MPC_SET_MUXA0),
838 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
839 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
840 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
841 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
842
5db86843 843 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 844 UVD, 0, mmUVD_MPC_SET_MUXB0),
845 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
846 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
847 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
848 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
849
5db86843 850 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 851 UVD, 0, mmUVD_MPC_SET_MUX),
852 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
853 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
854 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
855
856 vcn_v2_0_mc_resume_dpg_mode(adev, indirect);
857
5db86843 858 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5 859 UVD, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
5db86843 860 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 861 UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
862
863 /* release VCPU reset to boot */
5db86843 864 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 865 UVD, 0, mmUVD_SOFT_RESET), 0, 0, indirect);
866
867 /* enable LMI MC and UMC channels */
5db86843 868 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 869 UVD, 0, mmUVD_LMI_CTRL2),
870 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT, 0, indirect);
871
872 /* enable master interrupt */
5db86843 873 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 874 UVD, 0, mmUVD_MASTINT_EN),
875 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
876
dc8ae677 877 if (indirect)
5db86843
JZ		 878 psp_update_vcn_sram(adev, 0, adev->vcn.inst->dpg_sram_gpu_addr,
879 (uint32_t)((uintptr_t)adev->vcn.inst->dpg_sram_curr_addr -
880 (uintptr_t)adev->vcn.inst->dpg_sram_cpu_addr));
dc8ae677 881
bf4865b5
LL		 882 /* force RBC into idle state */
883 rb_bufsz = order_base_2(ring->ring_size);
884 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
885 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
886 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
887 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
888 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
889 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
890
ef563ff4
JZ		 891 /* Stall DPG before WPTR/RPTR reset */
892 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),
893 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,
894 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
93521410
JZ		 895 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET;
896
bf4865b5
LL		 897 /* set the write pointer delay */
898 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);
899
900 /* set the wb address */
901 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR,
902 (upper_32_bits(ring->gpu_addr) >> 2));
903
904 /* programm the RB_BASE for ring buffer */
905 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
906 lower_32_bits(ring->gpu_addr));
907 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
908 upper_32_bits(ring->gpu_addr));
909
910 /* Initialize the ring buffer's read and write pointers */
911 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
912
913 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0);
914
915 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
916 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
917 lower_32_bits(ring->wptr));
918
93521410 919 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET;
ef563ff4
JZ		 920 /* Unstall DPG */
921 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),
922 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
bf4865b5
LL		 923 return 0;
924}
925
1b61de45
LL		 926static int vcn_v2_0_start(struct amdgpu_device *adev)
927{
93521410 928 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared_cpu_addr;
c01b6a1d 929 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
1b61de45
LL		 930 uint32_t rb_bufsz, tmp;
931 uint32_t lmi_swap_cntl;
932 int i, j, r;
933
c113ba15
JX		 934 if (adev->pm.dpm_enabled)
935 amdgpu_dpm_enable_uvd(adev, true);
936
b0f3cd31
LL		 937 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
938 return vcn_v2_0_start_dpg_mode(adev, adev->vcn.indirect_sram);
bf4865b5 939
1b61de45
LL		 940 vcn_v2_0_disable_static_power_gating(adev);
941
942 /* set uvd status busy */
943 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
944 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
945
946 /*SW clock gating */
947 vcn_v2_0_disable_clock_gating(adev);
948
949 /* enable VCPU clock */
950 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL),
951 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
952
953 /* disable master interrupt */
954 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
955 ~UVD_MASTINT_EN__VCPU_EN_MASK);
956
957 /* setup mmUVD_LMI_CTRL */
958 tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL);
959 WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp |
960 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
961 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
962 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
963 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
964
965 /* setup mmUVD_MPC_CNTL */
966 tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL);
967 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
968 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
969 WREG32_SOC15(VCN, 0, mmUVD_MPC_CNTL, tmp);
970
971 /* setup UVD_MPC_SET_MUXA0 */
972 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0,
973 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
974 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
975 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
976 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
977
978 /* setup UVD_MPC_SET_MUXB0 */
979 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0,
980 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
981 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
982 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
983 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
984
985 /* setup mmUVD_MPC_SET_MUX */
986 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX,
987 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
988 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
989 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
990
991 vcn_v2_0_mc_resume(adev);
992
993 /* release VCPU reset to boot */
994 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
995 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
996
997 /* enable LMI MC and UMC channels */
998 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
999 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1000
1001 tmp = RREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET);
1002 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
1003 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
1004 WREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET, tmp);
1005
1006 /* disable byte swapping */
1007 lmi_swap_cntl = 0;
1008#ifdef __BIG_ENDIAN
1009 /* swap (8 in 32) RB and IB */
1010 lmi_swap_cntl = 0xa;
1011#endif
1012 WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
1013
1014 for (i = 0; i < 10; ++i) {
1015 uint32_t status;
1016
1017 for (j = 0; j < 100; ++j) {
1018 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);
1019 if (status & 2)
1020 break;
1021 mdelay(10);
1022 }
1023 r = 0;
1024 if (status & 2)
1025 break;
1026
1027 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n");
1028 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1029 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
1030 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1031 mdelay(10);
1032 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
1033 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1034 mdelay(10);
1035 r = -1;
1036 }
1037
1038 if (r) {
1039 DRM_ERROR("VCN decode not responding, giving up!!!\n");
1040 return r;
1041 }
1042
1043 /* enable master interrupt */
1044 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
1045 UVD_MASTINT_EN__VCPU_EN_MASK,
1046 ~UVD_MASTINT_EN__VCPU_EN_MASK);
1047
1048 /* clear the busy bit of VCN_STATUS */
1049 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0,
1050 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
1051
1052 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_VMID, 0);
1053
1054 /* force RBC into idle state */
1055 rb_bufsz = order_base_2(ring->ring_size);
1056 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1057 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1058 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1059 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1060 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1061 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
1062
93521410 1063 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET;
1b61de45
LL		 1064 /* programm the RB_BASE for ring buffer */
1065 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1066 lower_32_bits(ring->gpu_addr));
1067 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1068 upper_32_bits(ring->gpu_addr));
1069
1070 /* Initialize the ring buffer's read and write pointers */
1071 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
1072
1073 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1074 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1075 lower_32_bits(ring->wptr));
93521410 1076 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET;
1b61de45 1077
93521410 1078 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET;
c01b6a1d 1079 ring = &adev->vcn.inst->ring_enc[0];
1b61de45
LL		 1080 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1081 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1082 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
1083 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1084 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
93521410 1085 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET;
1b61de45 1086
93521410 1087 fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET;
c01b6a1d 1088 ring = &adev->vcn.inst->ring_enc[1];
1b61de45
LL		 1089 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1090 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1091 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1092 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1093 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
93521410 1094 fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET;
1b61de45 1095
b0f3cd31 1096 return 0;
1b61de45
LL		 1097}
1098
bf4865b5
LL		 1099static int vcn_v2_0_stop_dpg_mode(struct amdgpu_device *adev)
1100{
1101 int ret_code = 0;
1102 uint32_t tmp;
1103
1104 /* Wait for power status to be 1 */
1105 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1,
1106 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
1107
1108 /* wait for read ptr to be equal to write ptr */
1109 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
1110 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
1111
1112 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
1113 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF, ret_code);
1114
bf4865b5
LL		 1115 tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
1116 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
1117
1118 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1,
1119 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
1120
1121 /* disable dynamic power gating mode */
1122 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
1123 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
1124
1125 return 0;
1126}
1127
1b61de45
LL		 1128static int vcn_v2_0_stop(struct amdgpu_device *adev)
1129{
1130 uint32_t tmp;
1131 int r;
1132
bf4865b5
LL		 1133 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1134 r = vcn_v2_0_stop_dpg_mode(adev);
1135 if (r)
1136 return r;
1137 goto power_off;
1138 }
1139
1b61de45
LL		 1140 /* wait for uvd idle */
1141 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, r);
1142 if (r)
1143 return r;
1144
1145 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
1146 UVD_LMI_STATUS__READ_CLEAN_MASK |
1147 UVD_LMI_STATUS__WRITE_CLEAN_MASK |
1148 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
1149 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp, r);
1150 if (r)
1151 return r;
1152
1153 /* stall UMC channel */
1154 tmp = RREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2);
1155 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
1156 WREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2, tmp);
1157
1158 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK|
1159 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
1160 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp, r);
1161 if (r)
1162 return r;
1163
1164 /* disable VCPU clock */
1165 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
1166 ~(UVD_VCPU_CNTL__CLK_EN_MASK));
1167
1168 /* reset LMI UMC */
1169 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1170 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK,
1171 ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
1172
1173 /* reset LMI */
1174 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1175 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK,
1176 ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK);
1177
1178 /* reset VCPU */
1179 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1180 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
1181 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1182
1183 /* clear status */
1184 WREG32_SOC15(VCN, 0, mmUVD_STATUS, 0);
1185
1186 vcn_v2_0_enable_clock_gating(adev);
1187 vcn_v2_0_enable_static_power_gating(adev);
1188
bf4865b5 1189power_off:
c113ba15
JX		 1190 if (adev->pm.dpm_enabled)
1191 amdgpu_dpm_enable_uvd(adev, false);
1192
1b61de45
LL		 1193 return 0;
1194}
1195
7282da0b 1196static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,
597e6ac3 1197 int inst_idx, struct dpg_pause_state *new_state)
7282da0b
LL		 1198{
1199 struct amdgpu_ring *ring;
1200 uint32_t reg_data = 0;
1201 int ret_code;
1202
1203 /* pause/unpause if state is changed */
f4d0242b 1204 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
7282da0b 1205 DRM_DEBUG("dpg pause state changed %d -> %d",
f4d0242b 1206 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based);
7282da0b
LL		 1207 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &
1208 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1209
1210 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
1211 ret_code = 0;
1212 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 0x1,
1213 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
1214
1215 if (!ret_code) {
93521410 1216 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared_cpu_addr;
7282da0b
LL		 1217 /* pause DPG */
1218 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1219 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1220
1221 /* wait for ACK */
1222 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE,
1223 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
1224 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, ret_code);
1225
ef563ff4
JZ		 1226 /* Stall DPG before WPTR/RPTR reset */
1227 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),
1228 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,
1229 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
7282da0b 1230 /* Restore */
93521410 1231 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET;
c01b6a1d 1232 ring = &adev->vcn.inst->ring_enc[0];
ef563ff4 1233 ring->wptr = 0;
7282da0b
LL		 1234 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
1235 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1236 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
1237 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1238 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
93521410 1239 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET;
7282da0b 1240
93521410 1241 fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET;
c01b6a1d 1242 ring = &adev->vcn.inst->ring_enc[1];
ef563ff4 1243 ring->wptr = 0;
7282da0b
LL		 1244 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1245 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1246 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
1247 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1248 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
93521410 1249 fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET;
7282da0b 1250
93521410 1251 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET;
7282da0b
LL		 1252 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1253 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);
93521410 1254 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET;
ef563ff4
JZ		 1255 /* Unstall DPG */
1256 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),
1257 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
7282da0b
LL		 1258
1259 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1260 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,
1261 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
1262 }
1263 } else {
1264 /* unpause dpg, no need to wait */
1265 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1266 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1267 }
f4d0242b 1268 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
7282da0b
LL		 1269 }
1270
1271 return 0;
1272}
1273
1b61de45
LL		 1274static bool vcn_v2_0_is_idle(void *handle)
1275{
1276 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1277
1278 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);
1279}
1280
1281static int vcn_v2_0_wait_for_idle(void *handle)
1282{
1283 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1284 int ret = 0;
1285
1286 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE,
1287 UVD_STATUS__IDLE, ret);
1288
1289 return ret;
1290}
1291
1292static int vcn_v2_0_set_clockgating_state(void *handle,
1293 enum amd_clockgating_state state)
1294{
1295 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a9d4fe2f 1296 bool enable = (state == AMD_CG_STATE_GATE);
1b61de45 1297
cc9f2fba
ML		 1298 if (amdgpu_sriov_vf(adev))
1299 return 0;
1300
1b61de45
LL		 1301 if (enable) {
1302 /* wait for STATUS to clear */
23edf7f1 1303 if (!vcn_v2_0_is_idle(handle))
1b61de45
LL		 1304 return -EBUSY;
1305 vcn_v2_0_enable_clock_gating(adev);
1306 } else {
1307 /* disable HW gating and enable Sw gating */
1308 vcn_v2_0_disable_clock_gating(adev);
1309 }
1310 return 0;
1311}
1312
1313/**
1314 * vcn_v2_0_dec_ring_get_rptr - get read pointer
1315 *
1316 * @ring: amdgpu_ring pointer
1317 *
1318 * Returns the current hardware read pointer
1319 */
1320static uint64_t vcn_v2_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
1321{
1322 struct amdgpu_device *adev = ring->adev;
1323
1324 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1325}
1326
1327/**
1328 * vcn_v2_0_dec_ring_get_wptr - get write pointer
1329 *
1330 * @ring: amdgpu_ring pointer
1331 *
1332 * Returns the current hardware write pointer
1333 */
1334static uint64_t vcn_v2_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
1335{
1336 struct amdgpu_device *adev = ring->adev;
1337
1338 if (ring->use_doorbell)
1339 return adev->wb.wb[ring->wptr_offs];
1340 else
1341 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR);
1342}
1343
1344/**
1345 * vcn_v2_0_dec_ring_set_wptr - set write pointer
1346 *
1347 * @ring: amdgpu_ring pointer
1348 *
1349 * Commits the write pointer to the hardware
1350 */
1351static void vcn_v2_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
1352{
1353 struct amdgpu_device *adev = ring->adev;
1354
7282da0b
LL		 1355 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1356 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2,
1357 lower_32_bits(ring->wptr) | 0x80000000);
1358
1b61de45
LL		 1359 if (ring->use_doorbell) {
1360 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
1361 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1362 } else {
1363 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
1364 }
1365}
1366
1367/**
1368 * vcn_v2_0_dec_ring_insert_start - insert a start command
1369 *
1370 * @ring: amdgpu_ring pointer
1371 *
1372 * Write a start command to the ring.
1373 */
cdbd115e 1374void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring)
1b61de45 1375{
22a8f442
LL		 1376 struct amdgpu_device *adev = ring->adev;
1377
1378 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1b61de45 1379 amdgpu_ring_write(ring, 0);
22a8f442 1380 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
333fe325 1381 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1));
1b61de45
LL		 1382}
1383
1384/**
1385 * vcn_v2_0_dec_ring_insert_end - insert a end command
1386 *
1387 * @ring: amdgpu_ring pointer
1388 *
1389 * Write a end command to the ring.
1390 */
cdbd115e 1391void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring)
1b61de45 1392{
22a8f442
LL		 1393 struct amdgpu_device *adev = ring->adev;
1394
1395 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
333fe325 1396 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_END << 1));
1b61de45
LL		 1397}
1398
1399/**
1400 * vcn_v2_0_dec_ring_insert_nop - insert a nop command
1401 *
1402 * @ring: amdgpu_ring pointer
1403 *
1404 * Write a nop command to the ring.
1405 */
cdbd115e 1406void vcn_v2_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
1b61de45 1407{
22a8f442 1408 struct amdgpu_device *adev = ring->adev;
1b61de45
LL		 1409 int i;
1410
1411 WARN_ON(ring->wptr % 2 || count % 2);
1412
1413 for (i = 0; i < count / 2; i++) {
22a8f442 1414 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.nop, 0));
1b61de45
LL		 1415 amdgpu_ring_write(ring, 0);
1416 }
1417}
1418
1419/**
1420 * vcn_v2_0_dec_ring_emit_fence - emit an fence & trap command
1421 *
1422 * @ring: amdgpu_ring pointer
1423 * @fence: fence to emit
1424 *
1425 * Write a fence and a trap command to the ring.
1426 */
cdbd115e
LL		 1427void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1428 unsigned flags)
1b61de45 1429{
22a8f442 1430 struct amdgpu_device *adev = ring->adev;
1b61de45 1431
22a8f442
LL		 1432 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1433 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.context_id, 0));
1b61de45
LL		 1434 amdgpu_ring_write(ring, seq);
1435
22a8f442 1436 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1b61de45
LL		 1437 amdgpu_ring_write(ring, addr & 0xffffffff);
1438
22a8f442 1439 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));
1b61de45
LL		 1440 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
1441
22a8f442 1442 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
333fe325 1443 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_FENCE << 1));
1b61de45 1444
22a8f442 1445 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1b61de45
LL		 1446 amdgpu_ring_write(ring, 0);
1447
22a8f442 1448 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));
1b61de45
LL		 1449 amdgpu_ring_write(ring, 0);
1450
22a8f442 1451 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1b61de45 1452
333fe325 1453 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_TRAP << 1));
1b61de45
LL		 1454}
1455
1456/**
1457 * vcn_v2_0_dec_ring_emit_ib - execute indirect buffer
1458 *
1459 * @ring: amdgpu_ring pointer
1460 * @ib: indirect buffer to execute
1461 *
1462 * Write ring commands to execute the indirect buffer
1463 */
cdbd115e
LL		 1464void vcn_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
1465 struct amdgpu_job *job,
1466 struct amdgpu_ib *ib,
1467 uint32_t flags)
1b61de45 1468{
22a8f442 1469 struct amdgpu_device *adev = ring->adev;
1b61de45
LL		 1470 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1471
22a8f442 1472 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_vmid, 0));
1b61de45
LL		 1473 amdgpu_ring_write(ring, vmid);
1474
22a8f442 1475 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_bar_low, 0));
1b61de45 1476 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
22a8f442 1477 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_bar_high, 0));
1b61de45 1478 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
22a8f442 1479 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_size, 0));
1b61de45
LL		 1480 amdgpu_ring_write(ring, ib->length_dw);
1481}
1482
cdbd115e
LL		 1483void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1484 uint32_t val, uint32_t mask)
1b61de45 1485{
22a8f442
LL		 1486 struct amdgpu_device *adev = ring->adev;
1487
1488 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1b61de45
LL		 1489 amdgpu_ring_write(ring, reg << 2);
1490
22a8f442 1491 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));
1b61de45
LL		 1492 amdgpu_ring_write(ring, val);
1493
22a8f442 1494 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.gp_scratch8, 0));
1b61de45
LL		 1495 amdgpu_ring_write(ring, mask);
1496
22a8f442 1497 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1b61de45 1498
333fe325 1499 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_REG_READ_COND_WAIT << 1));
1b61de45
LL		 1500}
1501
cdbd115e
LL		 1502void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
1503 unsigned vmid, uint64_t pd_addr)
1b61de45
LL		 1504{
1505 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1506 uint32_t data0, data1, mask;
1507
1508 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1509
1510 /* wait for register write */
1511 data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2;
1512 data1 = lower_32_bits(pd_addr);
1513 mask = 0xffffffff;
1514 vcn_v2_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);
1515}
1516
cdbd115e
LL		 1517void vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring,
1518 uint32_t reg, uint32_t val)
1b61de45 1519{
22a8f442
LL		 1520 struct amdgpu_device *adev = ring->adev;
1521
1522 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1b61de45
LL		 1523 amdgpu_ring_write(ring, reg << 2);
1524
22a8f442 1525 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));
1b61de45
LL		 1526 amdgpu_ring_write(ring, val);
1527
22a8f442 1528 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1b61de45 1529
333fe325 1530 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_WRITE_REG << 1));
1b61de45
LL		 1531}
1532
1533/**
1534 * vcn_v2_0_enc_ring_get_rptr - get enc read pointer
1535 *
1536 * @ring: amdgpu_ring pointer
1537 *
1538 * Returns the current hardware enc read pointer
1539 */
1540static uint64_t vcn_v2_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
1541{
1542 struct amdgpu_device *adev = ring->adev;
1543
c01b6a1d 1544 if (ring == &adev->vcn.inst->ring_enc[0])
1b61de45
LL		 1545 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);
1546 else
1547 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2);
1548}
1549
1550 /**
1551 * vcn_v2_0_enc_ring_get_wptr - get enc write pointer
1552 *
1553 * @ring: amdgpu_ring pointer
1554 *
1555 * Returns the current hardware enc write pointer
1556 */
1557static uint64_t vcn_v2_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
1558{
1559 struct amdgpu_device *adev = ring->adev;
1560
c01b6a1d 1561 if (ring == &adev->vcn.inst->ring_enc[0]) {
1b61de45
LL		 1562 if (ring->use_doorbell)
1563 return adev->wb.wb[ring->wptr_offs];
1564 else
1565 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
1566 } else {
1567 if (ring->use_doorbell)
1568 return adev->wb.wb[ring->wptr_offs];
1569 else
1570 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
1571 }
1572}
1573
1574 /**
1575 * vcn_v2_0_enc_ring_set_wptr - set enc write pointer
1576 *
1577 * @ring: amdgpu_ring pointer
1578 *
1579 * Commits the enc write pointer to the hardware
1580 */
1581static void vcn_v2_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
1582{
1583 struct amdgpu_device *adev = ring->adev;
1584
c01b6a1d 1585 if (ring == &adev->vcn.inst->ring_enc[0]) {
1b61de45
LL		 1586 if (ring->use_doorbell) {
1587 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
1588 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1589 } else {
1590 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1591 }
1592 } else {
1593 if (ring->use_doorbell) {
1594 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
1595 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1596 } else {
1597 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1598 }
1599 }
1600}
1601
1602/**
1603 * vcn_v2_0_enc_ring_emit_fence - emit an enc fence & trap command
1604 *
1605 * @ring: amdgpu_ring pointer
1606 * @fence: fence to emit
1607 *
1608 * Write enc a fence and a trap command to the ring.
1609 */
cdbd115e
LL		 1610void vcn_v2_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1611 u64 seq, unsigned flags)
1b61de45
LL		 1612{
1613 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1614
1615 amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE);
1616 amdgpu_ring_write(ring, addr);
1617 amdgpu_ring_write(ring, upper_32_bits(addr));
1618 amdgpu_ring_write(ring, seq);
1619 amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP);
1620}
1621
cdbd115e 1622void vcn_v2_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1b61de45
LL		 1623{
1624 amdgpu_ring_write(ring, VCN_ENC_CMD_END);
1625}
1626
1627/**
1628 * vcn_v2_0_enc_ring_emit_ib - enc execute indirect buffer
1629 *
1630 * @ring: amdgpu_ring pointer
1631 * @ib: indirect buffer to execute
1632 *
1633 * Write enc ring commands to execute the indirect buffer
1634 */
cdbd115e
LL		 1635void vcn_v2_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1636 struct amdgpu_job *job,
1637 struct amdgpu_ib *ib,
1638 uint32_t flags)
1b61de45
LL		 1639{
1640 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1641
1642 amdgpu_ring_write(ring, VCN_ENC_CMD_IB);
1643 amdgpu_ring_write(ring, vmid);
1644 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1645 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1646 amdgpu_ring_write(ring, ib->length_dw);
1647}
1648
cdbd115e
LL		 1649void vcn_v2_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1650 uint32_t val, uint32_t mask)
1b61de45
LL		 1651{
1652 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT);
1653 amdgpu_ring_write(ring, reg << 2);
1654 amdgpu_ring_write(ring, mask);
1655 amdgpu_ring_write(ring, val);
1656}
1657
cdbd115e
LL		 1658void vcn_v2_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1659 unsigned int vmid, uint64_t pd_addr)
1b61de45
LL		 1660{
1661 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1662
1663 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1664
1665 /* wait for reg writes */
1666 vcn_v2_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2,
1667 lower_32_bits(pd_addr), 0xffffffff);
1668}
1669
cdbd115e 1670void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
1b61de45
LL		 1671{
1672 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
1673 amdgpu_ring_write(ring, reg << 2);
1674 amdgpu_ring_write(ring, val);
1675}
1676
1b61de45
LL		 1677static int vcn_v2_0_set_interrupt_state(struct amdgpu_device *adev,
1678 struct amdgpu_irq_src *source,
1679 unsigned type,
1680 enum amdgpu_interrupt_state state)
1681{
1682 return 0;
1683}
1684
1685static int vcn_v2_0_process_interrupt(struct amdgpu_device *adev,
1686 struct amdgpu_irq_src *source,
1687 struct amdgpu_iv_entry *entry)
1688{
1689 DRM_DEBUG("IH: VCN TRAP\n");
1690
1691 switch (entry->src_id) {
1692 case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT:
c01b6a1d 1693 amdgpu_fence_process(&adev->vcn.inst->ring_dec);
1b61de45
LL		 1694 break;
1695 case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE:
c01b6a1d 1696 amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]);
1b61de45
LL		 1697 break;
1698 case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY:
c01b6a1d 1699 amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]);
1b61de45 1700 break;
1b61de45
LL		 1701 default:
1702 DRM_ERROR("Unhandled interrupt: %d %d\n",
1703 entry->src_id, entry->src_data[0]);
1704 break;
1705 }
1706
1707 return 0;
1708}
1709
b6501217 1710int vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring *ring)
c74dbe44
TT		 1711{
1712 struct amdgpu_device *adev = ring->adev;
1713 uint32_t tmp = 0;
1714 unsigned i;
1715 int r;
1716
68430c6b
ML		 1717 if (amdgpu_sriov_vf(adev))
1718 return 0;
1719
c74dbe44
TT		 1720 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);
1721 r = amdgpu_ring_alloc(ring, 4);
1722 if (r)
1723 return r;
1724 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1725 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1));
1726 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0));
1727 amdgpu_ring_write(ring, 0xDEADBEEF);
1728 amdgpu_ring_commit(ring);
1729 for (i = 0; i < adev->usec_timeout; i++) {
1730 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9);
1731 if (tmp == 0xDEADBEEF)
1732 break;
9a2ffeb5 1733 udelay(1);
c74dbe44
TT		 1734 }
1735
1736 if (i >= adev->usec_timeout)
1737 r = -ETIMEDOUT;
1738
1739 return r;
1740}
1741
1742
1b61de45
LL		 1743static int vcn_v2_0_set_powergating_state(void *handle,
1744 enum amd_powergating_state state)
1745{
1746 /* This doesn't actually powergate the VCN block.
1747 * That's done in the dpm code via the SMC. This
1748 * just re-inits the block as necessary. The actual
1749 * gating still happens in the dpm code. We should
1750 * revisit this when there is a cleaner line between
1751 * the smc and the hw blocks
1752 */
1753 int ret;
1754 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1755
cc9f2fba
ML		 1756 if (amdgpu_sriov_vf(adev)) {
1757 adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
1758 return 0;
1759 }
1760
1b61de45
LL		 1761 if (state == adev->vcn.cur_state)
1762 return 0;
1763
1764 if (state == AMD_PG_STATE_GATE)
1765 ret = vcn_v2_0_stop(adev);
1766 else
1767 ret = vcn_v2_0_start(adev);
1768
1769 if (!ret)
1770 adev->vcn.cur_state = state;
1771 return ret;
1772}
1773
dd26858a
ML		 1774static int vcn_v2_0_start_mmsch(struct amdgpu_device *adev,
1775 struct amdgpu_mm_table *table)
1776{
1777 uint32_t data = 0, loop;
1778 uint64_t addr = table->gpu_addr;
1779 struct mmsch_v2_0_init_header *header;
1780 uint32_t size;
1781 int i;
1782
1783 header = (struct mmsch_v2_0_init_header *)table->cpu_addr;
1784 size = header->header_size + header->vcn_table_size;
1785
1786 /* 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr
1787 * of memory descriptor location
1788 */
1789 WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr));
1790 WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr));
1791
1792 /* 2, update vmid of descriptor */
1793 data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_VMID);
1794 data &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;
1795 /* use domain0 for MM scheduler */
1796 data |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);
1797 WREG32_SOC15(UVD, 0, mmMMSCH_VF_VMID, data);
1798
1799 /* 3, notify mmsch about the size of this descriptor */
1800 WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_SIZE, size);
1801
1802 /* 4, set resp to zero */
1803 WREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP, 0);
1804
1805 adev->vcn.inst->ring_dec.wptr = 0;
1806 adev->vcn.inst->ring_dec.wptr_old = 0;
1807 vcn_v2_0_dec_ring_set_wptr(&adev->vcn.inst->ring_dec);
1808
1809 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
1810 adev->vcn.inst->ring_enc[i].wptr = 0;
1811 adev->vcn.inst->ring_enc[i].wptr_old = 0;
1812 vcn_v2_0_enc_ring_set_wptr(&adev->vcn.inst->ring_enc[i]);
1813 }
1814
1815 /* 5, kick off the initialization and wait until
1816 * VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero
1817 */
1818 WREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_HOST, 0x10000001);
1819
1820 data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP);
1821 loop = 1000;
1822 while ((data & 0x10000002) != 0x10000002) {
1823 udelay(10);
1824 data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP);
1825 loop--;
1826 if (!loop)
1827 break;
1828 }
1829
1830 if (!loop) {
1831 DRM_ERROR("failed to init MMSCH, " \
1832 "mmMMSCH_VF_MAILBOX_RESP = 0x%08x\n", data);
1833 return -EBUSY;
1834 }
1835
1836 return 0;
1837}
1838
1839static int vcn_v2_0_start_sriov(struct amdgpu_device *adev)
1840{
1841 int r;
1842 uint32_t tmp;
1843 struct amdgpu_ring *ring;
1844 uint32_t offset, size;
1845 uint32_t table_size = 0;
1846 struct mmsch_v2_0_cmd_direct_write direct_wt = { {0} };
1847 struct mmsch_v2_0_cmd_direct_read_modify_write direct_rd_mod_wt = { {0} };
dd26858a
ML		 1848 struct mmsch_v2_0_cmd_end end = { {0} };
1849 struct mmsch_v2_0_init_header *header;
1850 uint32_t *init_table = adev->virt.mm_table.cpu_addr;
1851 uint8_t i = 0;
1852
1853 header = (struct mmsch_v2_0_init_header *)init_table;
1854 direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE;
1855 direct_rd_mod_wt.cmd_header.command_type =
1856 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
dd26858a
ML		 1857 end.cmd_header.command_type = MMSCH_COMMAND__END;
1858
1859 if (header->vcn_table_offset == 0 && header->vcn_table_size == 0) {
1860 header->version = MMSCH_VERSION;
1861 header->header_size = sizeof(struct mmsch_v2_0_init_header) >> 2;
1862
1863 header->vcn_table_offset = header->header_size;
1864
1865 init_table += header->vcn_table_offset;
1866
1867 size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
1868
1869 MMSCH_V2_0_INSERT_DIRECT_RD_MOD_WT(
1870 SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),
1871 0xFFFFFFFF, 0x00000004);
1872
1873 /* mc resume*/
1874 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1875 tmp = AMDGPU_UCODE_ID_VCN;
1876 MMSCH_V2_0_INSERT_DIRECT_WT(
1877 SOC15_REG_OFFSET(UVD, i,
1878 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1879 adev->firmware.ucode[tmp].tmr_mc_addr_lo);
1880 MMSCH_V2_0_INSERT_DIRECT_WT(
1881 SOC15_REG_OFFSET(UVD, i,
1882 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1883 adev->firmware.ucode[tmp].tmr_mc_addr_hi);
1884 offset = 0;
1885 } else {
1886 MMSCH_V2_0_INSERT_DIRECT_WT(
1887 SOC15_REG_OFFSET(UVD, i,
1888 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1889 lower_32_bits(adev->vcn.inst->gpu_addr));
1890 MMSCH_V2_0_INSERT_DIRECT_WT(
1891 SOC15_REG_OFFSET(UVD, i,
1892 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1893 upper_32_bits(adev->vcn.inst->gpu_addr));
1894 offset = size;
1895 }
1896
1897 MMSCH_V2_0_INSERT_DIRECT_WT(
1898 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET0),
1899 0);
1900 MMSCH_V2_0_INSERT_DIRECT_WT(
1901 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0),
1902 size);
1903
1904 MMSCH_V2_0_INSERT_DIRECT_WT(
1905 SOC15_REG_OFFSET(UVD, i,
1906 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
1907 lower_32_bits(adev->vcn.inst->gpu_addr + offset));
1908 MMSCH_V2_0_INSERT_DIRECT_WT(
1909 SOC15_REG_OFFSET(UVD, i,
1910 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
1911 upper_32_bits(adev->vcn.inst->gpu_addr + offset));
1912 MMSCH_V2_0_INSERT_DIRECT_WT(
1913 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET1),
1914 0);
1915 MMSCH_V2_0_INSERT_DIRECT_WT(
1916 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE1),
1917 AMDGPU_VCN_STACK_SIZE);
1918
1919 MMSCH_V2_0_INSERT_DIRECT_WT(
1920 SOC15_REG_OFFSET(UVD, i,
1921 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
1922 lower_32_bits(adev->vcn.inst->gpu_addr + offset +
1923 AMDGPU_VCN_STACK_SIZE));
1924 MMSCH_V2_0_INSERT_DIRECT_WT(
1925 SOC15_REG_OFFSET(UVD, i,
1926 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
1927 upper_32_bits(adev->vcn.inst->gpu_addr + offset +
1928 AMDGPU_VCN_STACK_SIZE));
1929 MMSCH_V2_0_INSERT_DIRECT_WT(
1930 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET2),
1931 0);
1932 MMSCH_V2_0_INSERT_DIRECT_WT(
1933 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2),
1934 AMDGPU_VCN_CONTEXT_SIZE);
1935
1936 for (r = 0; r < adev->vcn.num_enc_rings; ++r) {
1937 ring = &adev->vcn.inst->ring_enc[r];
1938 ring->wptr = 0;
1939 MMSCH_V2_0_INSERT_DIRECT_WT(
1940 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO),
1941 lower_32_bits(ring->gpu_addr));
1942 MMSCH_V2_0_INSERT_DIRECT_WT(
1943 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI),
1944 upper_32_bits(ring->gpu_addr));
1945 MMSCH_V2_0_INSERT_DIRECT_WT(
1946 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE),
1947 ring->ring_size / 4);
1948 }
1949
1950 ring = &adev->vcn.inst->ring_dec;
1951 ring->wptr = 0;
1952 MMSCH_V2_0_INSERT_DIRECT_WT(
1953 SOC15_REG_OFFSET(UVD, i,
1954 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW),
1955 lower_32_bits(ring->gpu_addr));
1956 MMSCH_V2_0_INSERT_DIRECT_WT(
1957 SOC15_REG_OFFSET(UVD, i,
1958 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH),
1959 upper_32_bits(ring->gpu_addr));
1960 /* force RBC into idle state */
1961 tmp = order_base_2(ring->ring_size);
1962 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp);
1963 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1964 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1965 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1966 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1967 MMSCH_V2_0_INSERT_DIRECT_WT(
1968 SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp);
1969
1970 /* add end packet */
1971 tmp = sizeof(struct mmsch_v2_0_cmd_end);
1972 memcpy((void *)init_table, &end, tmp);
1973 table_size += (tmp / 4);
1974 header->vcn_table_size = table_size;
1975
1976 }
1977 return vcn_v2_0_start_mmsch(adev, &adev->virt.mm_table);
1978}
1979
1b61de45
LL		 1980static const struct amd_ip_funcs vcn_v2_0_ip_funcs = {
1981 .name = "vcn_v2_0",
1982 .early_init = vcn_v2_0_early_init,
1983 .late_init = NULL,
1984 .sw_init = vcn_v2_0_sw_init,
1985 .sw_fini = vcn_v2_0_sw_fini,
1986 .hw_init = vcn_v2_0_hw_init,
1987 .hw_fini = vcn_v2_0_hw_fini,
1988 .suspend = vcn_v2_0_suspend,
1989 .resume = vcn_v2_0_resume,
1990 .is_idle = vcn_v2_0_is_idle,
1991 .wait_for_idle = vcn_v2_0_wait_for_idle,
1992 .check_soft_reset = NULL,
1993 .pre_soft_reset = NULL,
1994 .soft_reset = NULL,
1995 .post_soft_reset = NULL,
1996 .set_clockgating_state = vcn_v2_0_set_clockgating_state,
1997 .set_powergating_state = vcn_v2_0_set_powergating_state,
1998};
1999
2000static const struct amdgpu_ring_funcs vcn_v2_0_dec_ring_vm_funcs = {
2001 .type = AMDGPU_RING_TYPE_VCN_DEC,
2002 .align_mask = 0xf,
a2d15ed7 2003 .vmhub = AMDGPU_MMHUB_0,
1b61de45
LL		 2004 .get_rptr = vcn_v2_0_dec_ring_get_rptr,
2005 .get_wptr = vcn_v2_0_dec_ring_get_wptr,
2006 .set_wptr = vcn_v2_0_dec_ring_set_wptr,
2007 .emit_frame_size =
2008 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
2009 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
2010 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */
2011 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */
2012 6,
2013 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */
2014 .emit_ib = vcn_v2_0_dec_ring_emit_ib,
2015 .emit_fence = vcn_v2_0_dec_ring_emit_fence,
2016 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush,
c74dbe44 2017 .test_ring = vcn_v2_0_dec_ring_test_ring,
1b61de45
LL		 2018 .test_ib = amdgpu_vcn_dec_ring_test_ib,
2019 .insert_nop = vcn_v2_0_dec_ring_insert_nop,
2020 .insert_start = vcn_v2_0_dec_ring_insert_start,
2021 .insert_end = vcn_v2_0_dec_ring_insert_end,
2022 .pad_ib = amdgpu_ring_generic_pad_ib,
2023 .begin_use = amdgpu_vcn_ring_begin_use,
2024 .end_use = amdgpu_vcn_ring_end_use,
2025 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg,
2026 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait,
2027 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2028};
2029
2030static const struct amdgpu_ring_funcs vcn_v2_0_enc_ring_vm_funcs = {
2031 .type = AMDGPU_RING_TYPE_VCN_ENC,
2032 .align_mask = 0x3f,
2033 .nop = VCN_ENC_CMD_NO_OP,
a2d15ed7 2034 .vmhub = AMDGPU_MMHUB_0,
1b61de45
LL		 2035 .get_rptr = vcn_v2_0_enc_ring_get_rptr,
2036 .get_wptr = vcn_v2_0_enc_ring_get_wptr,
2037 .set_wptr = vcn_v2_0_enc_ring_set_wptr,
2038 .emit_frame_size =
2039 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2040 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
2041 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */
2042 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */
2043 1, /* vcn_v2_0_enc_ring_insert_end */
2044 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */
2045 .emit_ib = vcn_v2_0_enc_ring_emit_ib,
2046 .emit_fence = vcn_v2_0_enc_ring_emit_fence,
2047 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush,
2048 .test_ring = amdgpu_vcn_enc_ring_test_ring,
2049 .test_ib = amdgpu_vcn_enc_ring_test_ib,
2050 .insert_nop = amdgpu_ring_insert_nop,
2051 .insert_end = vcn_v2_0_enc_ring_insert_end,
2052 .pad_ib = amdgpu_ring_generic_pad_ib,
2053 .begin_use = amdgpu_vcn_ring_begin_use,
2054 .end_use = amdgpu_vcn_ring_end_use,
2055 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg,
2056 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,
2057 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2058};
2059
1b61de45
LL		 2060static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev)
2061{
c01b6a1d 2062 adev->vcn.inst->ring_dec.funcs = &vcn_v2_0_dec_ring_vm_funcs;
1b61de45
LL		 2063 DRM_INFO("VCN decode is enabled in VM mode\n");
2064}
2065
2066static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev)
2067{
2068 int i;
2069
2070 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
c01b6a1d 2071 adev->vcn.inst->ring_enc[i].funcs = &vcn_v2_0_enc_ring_vm_funcs;
1b61de45
LL		 2072
2073 DRM_INFO("VCN encode is enabled in VM mode\n");
2074}
2075
1b61de45
LL		 2076static const struct amdgpu_irq_src_funcs vcn_v2_0_irq_funcs = {
2077 .set = vcn_v2_0_set_interrupt_state,
2078 .process = vcn_v2_0_process_interrupt,
2079};
2080
2081static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev)
2082{
21a174f5 2083 adev->vcn.inst->irq.num_types = adev->vcn.num_enc_rings + 1;
c01b6a1d 2084 adev->vcn.inst->irq.funcs = &vcn_v2_0_irq_funcs;
1b61de45
LL		 2085}
2086
2087const struct amdgpu_ip_block_version vcn_v2_0_ip_block =
2088{
2089 .type = AMD_IP_BLOCK_TYPE_VCN,
2090 .major = 2,
2091 .minor = 0,
2092 .rev = 0,
2093 .funcs = &vcn_v2_0_ip_funcs,
2094};
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