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drm/amdgpu/vcn: Add firmware share memory support
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / amdgpu / vcn_v2_0.c
CommitLineData
1b61de45
LL		 1/*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/firmware.h>
9a2ffeb5 25
1b61de45
LL		 26#include "amdgpu.h"
27#include "amdgpu_vcn.h"
28#include "soc15.h"
29#include "soc15d.h"
c113ba15 30#include "amdgpu_pm.h"
dc8ae677 31#include "amdgpu_psp.h"
dd26858a 32#include "mmsch_v2_0.h"
1b61de45
LL		 33
34#include "vcn/vcn_2_0_0_offset.h"
35#include "vcn/vcn_2_0_0_sh_mask.h"
36#include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
37
38#define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x1fd
39#define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x503
40#define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET 0x504
41#define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET 0x505
42#define mmUVD_NO_OP_INTERNAL_OFFSET 0x53f
43#define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET 0x54a
44#define mmUVD_SCRATCH9_INTERNAL_OFFSET 0xc01d
45
46#define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x1e1
47#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x5a6
48#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x5a7
49#define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x1e2
1b61de45 50
1b61de45
LL		 51static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev);
52static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev);
1b61de45
LL		 53static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev);
54static int vcn_v2_0_set_powergating_state(void *handle,
55 enum amd_powergating_state state);
7282da0b 56static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,
597e6ac3 57 int inst_idx, struct dpg_pause_state *new_state);
dd26858a 58static int vcn_v2_0_start_sriov(struct amdgpu_device *adev);
1b61de45
LL		 59/**
60 * vcn_v2_0_early_init - set function pointers
61 *
62 * @handle: amdgpu_device pointer
63 *
64 * Set ring and irq function pointers
65 */
66static int vcn_v2_0_early_init(void *handle)
67{
68 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
69
c01b6a1d 70 adev->vcn.num_vcn_inst = 1;
dd26858a
ML		 71 if (amdgpu_sriov_vf(adev))
72 adev->vcn.num_enc_rings = 1;
73 else
74 adev->vcn.num_enc_rings = 2;
1b61de45
LL		 75
76 vcn_v2_0_set_dec_ring_funcs(adev);
77 vcn_v2_0_set_enc_ring_funcs(adev);
1b61de45
LL		 78 vcn_v2_0_set_irq_funcs(adev);
79
80 return 0;
81}
82
83/**
84 * vcn_v2_0_sw_init - sw init for VCN block
85 *
86 * @handle: amdgpu_device pointer
87 *
88 * Load firmware and sw initialization
89 */
90static int vcn_v2_0_sw_init(void *handle)
91{
92 struct amdgpu_ring *ring;
93 int i, r;
94 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
95
96 /* VCN DEC TRAP */
97 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
98 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT,
c01b6a1d 99 &adev->vcn.inst->irq);
1b61de45
LL		 100 if (r)
101 return r;
102
103 /* VCN ENC TRAP */
104 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
105 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
106 i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE,
c01b6a1d 107 &adev->vcn.inst->irq);
1b61de45
LL		 108 if (r)
109 return r;
110 }
111
1b61de45
LL		 112 r = amdgpu_vcn_sw_init(adev);
113 if (r)
114 return r;
115
116 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
117 const struct common_firmware_header *hdr;
118 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
119 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN;
120 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
121 adev->firmware.fw_size +=
122 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
123 DRM_INFO("PSP loading VCN firmware\n");
124 }
125
126 r = amdgpu_vcn_resume(adev);
127 if (r)
128 return r;
129
c01b6a1d 130 ring = &adev->vcn.inst->ring_dec;
1b61de45
LL		 131
132 ring->use_doorbell = true;
133 ring->doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1 << 1;
134
135 sprintf(ring->name, "vcn_dec");
c01b6a1d 136 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0);
1b61de45
LL		 137 if (r)
138 return r;
139
22a8f442
LL		 140 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;
141 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;
142 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;
143 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;
144 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;
145 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;
146
1b61de45 147 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;
c01b6a1d 148 adev->vcn.inst->external.scratch9 = SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9);
1b61de45 149 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;
c01b6a1d 150 adev->vcn.inst->external.data0 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0);
1b61de45 151 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;
c01b6a1d 152 adev->vcn.inst->external.data1 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1);
1b61de45 153 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;
c01b6a1d 154 adev->vcn.inst->external.cmd = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD);
1b61de45 155 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;
c01b6a1d 156 adev->vcn.inst->external.nop = SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP);
1b61de45
LL		 157
158 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
c01b6a1d 159 ring = &adev->vcn.inst->ring_enc[i];
1b61de45 160 ring->use_doorbell = true;
dd26858a
ML		 161 if (!amdgpu_sriov_vf(adev))
162 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + i;
163 else
164 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + i;
1b61de45 165 sprintf(ring->name, "vcn_enc%d", i);
c01b6a1d 166 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0);
1b61de45
LL		 167 if (r)
168 return r;
169 }
170
7282da0b
LL		 171 adev->vcn.pause_dpg_mode = vcn_v2_0_pause_dpg_mode;
172
dd26858a
ML		 173 r = amdgpu_virt_alloc_mm_table(adev);
174 if (r)
175 return r;
176
1b61de45
LL		 177 return 0;
178}
179
180/**
181 * vcn_v2_0_sw_fini - sw fini for VCN block
182 *
183 * @handle: amdgpu_device pointer
184 *
185 * VCN suspend and free up sw allocation
186 */
187static int vcn_v2_0_sw_fini(void *handle)
188{
189 int r;
190 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
191
dd26858a
ML		 192 amdgpu_virt_free_mm_table(adev);
193
1b61de45
LL		 194 r = amdgpu_vcn_suspend(adev);
195 if (r)
196 return r;
197
198 r = amdgpu_vcn_sw_fini(adev);
199
200 return r;
201}
202
203/**
204 * vcn_v2_0_hw_init - start and test VCN block
205 *
206 * @handle: amdgpu_device pointer
207 *
208 * Initialize the hardware, boot up the VCPU and do some testing
209 */
210static int vcn_v2_0_hw_init(void *handle)
211{
212 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
c01b6a1d 213 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
1b61de45
LL		 214 int i, r;
215
bebc0762 216 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
989b6a05 217 ring->doorbell_index, 0);
1b61de45 218
dd26858a
ML		 219 if (amdgpu_sriov_vf(adev))
220 vcn_v2_0_start_sriov(adev);
221
fd287c8c
LL		 222 r = amdgpu_ring_test_helper(ring);
223 if (r)
1b61de45 224 goto done;
1b61de45 225
ad31da43
ED		 226 //Disable vcn decode for sriov
227 if (amdgpu_sriov_vf(adev))
228 ring->sched.ready = false;
229
1b61de45 230 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
c01b6a1d 231 ring = &adev->vcn.inst->ring_enc[i];
fd287c8c
LL		 232 r = amdgpu_ring_test_helper(ring);
233 if (r)
1b61de45 234 goto done;
1b61de45
LL		 235 }
236
1b61de45
LL		 237done:
238 if (!r)
bf4865b5
LL		 239 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n",
240 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode");
1b61de45
LL		 241
242 return r;
243}
244
245/**
246 * vcn_v2_0_hw_fini - stop the hardware block
247 *
248 * @handle: amdgpu_device pointer
249 *
250 * Stop the VCN block, mark ring as not ready any more
251 */
252static int vcn_v2_0_hw_fini(void *handle)
253{
254 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1b61de45 255
bf4865b5
LL		 256 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
257 (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
258 RREG32_SOC15(VCN, 0, mmUVD_STATUS)))
1b61de45
LL		 259 vcn_v2_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
260
1b61de45
LL		 261 return 0;
262}
263
264/**
265 * vcn_v2_0_suspend - suspend VCN block
266 *
267 * @handle: amdgpu_device pointer
268 *
269 * HW fini and suspend VCN block
270 */
271static int vcn_v2_0_suspend(void *handle)
272{
273 int r;
274 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
275
276 r = vcn_v2_0_hw_fini(adev);
277 if (r)
278 return r;
279
280 r = amdgpu_vcn_suspend(adev);
281
282 return r;
283}
284
285/**
286 * vcn_v2_0_resume - resume VCN block
287 *
288 * @handle: amdgpu_device pointer
289 *
290 * Resume firmware and hw init VCN block
291 */
292static int vcn_v2_0_resume(void *handle)
293{
294 int r;
295 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
296
297 r = amdgpu_vcn_resume(adev);
298 if (r)
299 return r;
300
301 r = vcn_v2_0_hw_init(adev);
302
303 return r;
304}
305
306/**
307 * vcn_v2_0_mc_resume - memory controller programming
308 *
309 * @adev: amdgpu_device pointer
310 *
311 * Let the VCN memory controller know it's offsets
312 */
313static void vcn_v2_0_mc_resume(struct amdgpu_device *adev)
314{
315 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
316 uint32_t offset;
317
cc9f2fba
ML		 318 if (amdgpu_sriov_vf(adev))
319 return;
320
1b61de45
LL		 321 /* cache window 0: fw */
322 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
323 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
324 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));
325 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
326 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi));
327 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
328 offset = 0;
329 } else {
330 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
c01b6a1d 331 lower_32_bits(adev->vcn.inst->gpu_addr));
1b61de45 332 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
c01b6a1d 333 upper_32_bits(adev->vcn.inst->gpu_addr));
1b61de45 334 offset = size;
1b61de45
LL		 335 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
336 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
1b61de45
LL		 337 }
338
339 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
340
341 /* cache window 1: stack */
342 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
c01b6a1d 343 lower_32_bits(adev->vcn.inst->gpu_addr + offset));
1b61de45 344 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
c01b6a1d 345 upper_32_bits(adev->vcn.inst->gpu_addr + offset));
1b61de45
LL		 346 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0);
347 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
348
349 /* cache window 2: context */
350 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
c01b6a1d 351 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
1b61de45 352 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
c01b6a1d 353 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
1b61de45
LL		 354 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);
355 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
356
357 WREG32_SOC15(UVD, 0, mmUVD_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
1b61de45
LL		 358}
359
bf4865b5
LL		 360static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device *adev, bool indirect)
361{
362 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
363 uint32_t offset;
364
365 /* cache window 0: fw */
366 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
dc8ae677 367 if (!indirect) {
5db86843 368 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
dc8ae677
LL		 369 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
370 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 0, indirect);
5db86843 371 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
dc8ae677
LL		 372 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
373 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 0, indirect);
5db86843 374 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
dc8ae677
LL		 375 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
376 } else {
5db86843 377 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
dc8ae677 378 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
5db86843 379 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
dc8ae677 380 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
5db86843 381 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
dc8ae677
LL		 382 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
383 }
bf4865b5
LL		 384 offset = 0;
385 } else {
5db86843 386 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5 387 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
c01b6a1d 388 lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);
5db86843 389 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5 390 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
c01b6a1d 391 upper_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);
bf4865b5 392 offset = size;
5db86843 393 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 394 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0),
395 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
396 }
397
dc8ae677 398 if (!indirect)
5db86843 399 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
dc8ae677
LL		 400 UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
401 else
5db86843 402 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
dc8ae677 403 UVD, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
bf4865b5
LL		 404
405 /* cache window 1: stack */
dc8ae677 406 if (!indirect) {
5db86843 407 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
dc8ae677 408 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
c01b6a1d 409 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect);
5db86843 410 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
dc8ae677 411 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
c01b6a1d 412 upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect);
5db86843 413 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
dc8ae677
LL		 414 UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
415 } else {
5db86843 416 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
dc8ae677 417 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
5db86843 418 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
dc8ae677 419 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
5db86843 420 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
dc8ae677
LL		 421 UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
422 }
5db86843 423 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 424 UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
425
426 /* cache window 2: context */
5db86843 427 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5 428 UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
c01b6a1d 429 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
5db86843 430 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5 431 UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
c01b6a1d 432 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
5db86843 433 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5 434 UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
5db86843 435 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 436 UVD, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
437
438 /* non-cache window */
5db86843 439 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5 440 UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0, indirect);
5db86843 441 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5 442 UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0, indirect);
5db86843 443 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5 444 UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
5db86843 445 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 446 UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect);
447
448 /* VCN global tiling registers */
5db86843 449 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 450 UVD, 0, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
451}
452
1b61de45
LL		 453/**
454 * vcn_v2_0_disable_clock_gating - disable VCN clock gating
455 *
456 * @adev: amdgpu_device pointer
457 * @sw: enable SW clock gating
458 *
459 * Disable clock gating for VCN block
460 */
461static void vcn_v2_0_disable_clock_gating(struct amdgpu_device *adev)
462{
463 uint32_t data;
464
cc9f2fba
ML		 465 if (amdgpu_sriov_vf(adev))
466 return;
467
1b61de45
LL		 468 /* UVD disable CGC */
469 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
470 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
471 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
472 else
473 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
474 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
475 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
476 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
477
478 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE);
479 data &= ~(UVD_CGC_GATE__SYS_MASK
480 | UVD_CGC_GATE__UDEC_MASK
481 | UVD_CGC_GATE__MPEG2_MASK
482 | UVD_CGC_GATE__REGS_MASK
483 | UVD_CGC_GATE__RBC_MASK
484 | UVD_CGC_GATE__LMI_MC_MASK
485 | UVD_CGC_GATE__LMI_UMC_MASK
486 | UVD_CGC_GATE__IDCT_MASK
487 | UVD_CGC_GATE__MPRD_MASK
488 | UVD_CGC_GATE__MPC_MASK
489 | UVD_CGC_GATE__LBSI_MASK
490 | UVD_CGC_GATE__LRBBM_MASK
491 | UVD_CGC_GATE__UDEC_RE_MASK
492 | UVD_CGC_GATE__UDEC_CM_MASK
493 | UVD_CGC_GATE__UDEC_IT_MASK
494 | UVD_CGC_GATE__UDEC_DB_MASK
495 | UVD_CGC_GATE__UDEC_MP_MASK
496 | UVD_CGC_GATE__WCB_MASK
497 | UVD_CGC_GATE__VCPU_MASK
498 | UVD_CGC_GATE__SCPU_MASK);
499 WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data);
500
501 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
502 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
503 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
504 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
505 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
506 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
507 | UVD_CGC_CTRL__SYS_MODE_MASK
508 | UVD_CGC_CTRL__UDEC_MODE_MASK
509 | UVD_CGC_CTRL__MPEG2_MODE_MASK
510 | UVD_CGC_CTRL__REGS_MODE_MASK
511 | UVD_CGC_CTRL__RBC_MODE_MASK
512 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
513 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
514 | UVD_CGC_CTRL__IDCT_MODE_MASK
515 | UVD_CGC_CTRL__MPRD_MODE_MASK
516 | UVD_CGC_CTRL__MPC_MODE_MASK
517 | UVD_CGC_CTRL__LBSI_MODE_MASK
518 | UVD_CGC_CTRL__LRBBM_MODE_MASK
519 | UVD_CGC_CTRL__WCB_MODE_MASK
520 | UVD_CGC_CTRL__VCPU_MODE_MASK
521 | UVD_CGC_CTRL__SCPU_MODE_MASK);
522 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
523
524 /* turn on */
525 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE);
526 data |= (UVD_SUVD_CGC_GATE__SRE_MASK
527 | UVD_SUVD_CGC_GATE__SIT_MASK
528 | UVD_SUVD_CGC_GATE__SMP_MASK
529 | UVD_SUVD_CGC_GATE__SCM_MASK
530 | UVD_SUVD_CGC_GATE__SDB_MASK
531 | UVD_SUVD_CGC_GATE__SRE_H264_MASK
532 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
533 | UVD_SUVD_CGC_GATE__SIT_H264_MASK
534 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
535 | UVD_SUVD_CGC_GATE__SCM_H264_MASK
536 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
537 | UVD_SUVD_CGC_GATE__SDB_H264_MASK
538 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
539 | UVD_SUVD_CGC_GATE__SCLR_MASK
540 | UVD_SUVD_CGC_GATE__UVD_SC_MASK
541 | UVD_SUVD_CGC_GATE__ENT_MASK
542 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
543 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
544 | UVD_SUVD_CGC_GATE__SITE_MASK
545 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
546 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
547 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
548 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
549 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
550 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data);
551
552 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
553 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
554 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
555 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
556 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
557 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
558 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
559 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
560 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
561 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
562 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
563 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
564}
565
bf4865b5
LL		 566static void vcn_v2_0_clock_gating_dpg_mode(struct amdgpu_device *adev,
567 uint8_t sram_sel, uint8_t indirect)
568{
569 uint32_t reg_data = 0;
570
571 /* enable sw clock gating control */
572 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
573 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
574 else
575 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
576 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
577 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
578 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
579 UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
580 UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
581 UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
582 UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
583 UVD_CGC_CTRL__SYS_MODE_MASK |
584 UVD_CGC_CTRL__UDEC_MODE_MASK |
585 UVD_CGC_CTRL__MPEG2_MODE_MASK |
586 UVD_CGC_CTRL__REGS_MODE_MASK |
587 UVD_CGC_CTRL__RBC_MODE_MASK |
588 UVD_CGC_CTRL__LMI_MC_MODE_MASK |
589 UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
590 UVD_CGC_CTRL__IDCT_MODE_MASK |
591 UVD_CGC_CTRL__MPRD_MODE_MASK |
592 UVD_CGC_CTRL__MPC_MODE_MASK |
593 UVD_CGC_CTRL__LBSI_MODE_MASK |
594 UVD_CGC_CTRL__LRBBM_MODE_MASK |
595 UVD_CGC_CTRL__WCB_MODE_MASK |
596 UVD_CGC_CTRL__VCPU_MODE_MASK |
597 UVD_CGC_CTRL__SCPU_MODE_MASK);
5db86843 598 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 599 UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
600
601 /* turn off clock gating */
5db86843 602 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 603 UVD, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect);
604
605 /* turn on SUVD clock gating */
5db86843 606 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 607 UVD, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
608
609 /* turn on sw mode in UVD_SUVD_CGC_CTRL */
5db86843 610 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 611 UVD, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
612}
613
1b61de45
LL		 614/**
615 * vcn_v2_0_enable_clock_gating - enable VCN clock gating
616 *
617 * @adev: amdgpu_device pointer
618 * @sw: enable SW clock gating
619 *
620 * Enable clock gating for VCN block
621 */
622static void vcn_v2_0_enable_clock_gating(struct amdgpu_device *adev)
623{
624 uint32_t data = 0;
625
cc9f2fba
ML		 626 if (amdgpu_sriov_vf(adev))
627 return;
628
1b61de45
LL		 629 /* enable UVD CGC */
630 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
631 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
632 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
633 else
634 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
635 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
636 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
637 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
638
639 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
640 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
641 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
642 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
643 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
644 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
645 | UVD_CGC_CTRL__SYS_MODE_MASK
646 | UVD_CGC_CTRL__UDEC_MODE_MASK
647 | UVD_CGC_CTRL__MPEG2_MODE_MASK
648 | UVD_CGC_CTRL__REGS_MODE_MASK
649 | UVD_CGC_CTRL__RBC_MODE_MASK
650 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
651 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
652 | UVD_CGC_CTRL__IDCT_MODE_MASK
653 | UVD_CGC_CTRL__MPRD_MODE_MASK
654 | UVD_CGC_CTRL__MPC_MODE_MASK
655 | UVD_CGC_CTRL__LBSI_MODE_MASK
656 | UVD_CGC_CTRL__LRBBM_MODE_MASK
657 | UVD_CGC_CTRL__WCB_MODE_MASK
658 | UVD_CGC_CTRL__VCPU_MODE_MASK
659 | UVD_CGC_CTRL__SCPU_MODE_MASK);
660 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
661
662 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
663 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
664 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
665 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
666 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
667 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
668 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
669 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
670 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
671 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
672 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
673 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
674}
675
676static void vcn_v2_0_disable_static_power_gating(struct amdgpu_device *adev)
677{
678 uint32_t data = 0;
679 int ret;
680
cc9f2fba
ML		 681 if (amdgpu_sriov_vf(adev))
682 return;
683
1b61de45
LL		 684 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
685 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
686 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
687 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
688 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
689 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
690 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
691 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
692 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
693 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
863dd269 694 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT);
1b61de45
LL		 695
696 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
697 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS,
863dd269 698 UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON_2_0, 0xFFFFF, ret);
1b61de45
LL		 699 } else {
700 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
701 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
702 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
703 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
704 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
705 | 1 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
706 | 1 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
707 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
708 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
863dd269 709 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT);
1b61de45 710 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
863dd269 711 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFF, ret);
1b61de45
LL		 712 }
713
714 /* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS,
715 * UVDU_PWR_STATUS are 0 (power on) */
716
717 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
718 data &= ~0x103;
719 if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
720 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON |
721 UVD_POWER_STATUS__UVD_PG_EN_MASK;
722
723 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
724}
725
726static void vcn_v2_0_enable_static_power_gating(struct amdgpu_device *adev)
727{
728 uint32_t data = 0;
729 int ret;
730
cc9f2fba
ML		 731 if (amdgpu_sriov_vf(adev))
732 return;
733
1b61de45
LL		 734 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
735 /* Before power off, this indicator has to be turned on */
736 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
737 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK;
738 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF;
739 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
740
741
742 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
743 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
744 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
745 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
746 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
747 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
748 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
749 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
750 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
863dd269 751 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT);
1b61de45
LL		 752
753 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
754
755 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT
756 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT
757 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT
758 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT
759 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT
760 | 2 << UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT
761 | 2 << UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT
762 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT
763 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT
863dd269
LL		 764 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT);
765 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFF, ret);
1b61de45
LL		 766 }
767}
768
bf4865b5
LL		 769static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect)
770{
c01b6a1d 771 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
bf4865b5
LL		 772 uint32_t rb_bufsz, tmp;
773
774 vcn_v2_0_enable_static_power_gating(adev);
775
776 /* enable dynamic power gating mode */
777 tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);
778 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
779 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
780 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp);
781
dc8ae677 782 if (indirect)
5db86843 783 adev->vcn.inst->dpg_sram_curr_addr = (uint32_t*)adev->vcn.inst->dpg_sram_cpu_addr;
dc8ae677 784
bf4865b5
LL		 785 /* enable clock gating */
786 vcn_v2_0_clock_gating_dpg_mode(adev, 0, indirect);
787
788 /* enable VCPU clock */
789 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
790 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
791 tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK;
5db86843 792 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 793 UVD, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);
794
795 /* disable master interupt */
5db86843 796 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 797 UVD, 0, mmUVD_MASTINT_EN), 0, 0, indirect);
798
799 /* setup mmUVD_LMI_CTRL */
800 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
801 UVD_LMI_CTRL__REQ_MODE_MASK |
802 UVD_LMI_CTRL__CRC_RESET_MASK |
803 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
804 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
805 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
806 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
807 0x00100000L);
5db86843 808 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 809 UVD, 0, mmUVD_LMI_CTRL), tmp, 0, indirect);
810
5db86843 811 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 812 UVD, 0, mmUVD_MPC_CNTL),
813 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
814
5db86843 815 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 816 UVD, 0, mmUVD_MPC_SET_MUXA0),
817 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
818 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
819 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
820 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
821
5db86843 822 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 823 UVD, 0, mmUVD_MPC_SET_MUXB0),
824 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
825 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
826 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
827 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
828
5db86843 829 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 830 UVD, 0, mmUVD_MPC_SET_MUX),
831 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
832 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
833 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
834
835 vcn_v2_0_mc_resume_dpg_mode(adev, indirect);
836
5db86843 837 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5 838 UVD, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
5db86843 839 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 840 UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
841
842 /* release VCPU reset to boot */
5db86843 843 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 844 UVD, 0, mmUVD_SOFT_RESET), 0, 0, indirect);
845
846 /* enable LMI MC and UMC channels */
5db86843 847 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 848 UVD, 0, mmUVD_LMI_CTRL2),
849 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT, 0, indirect);
850
851 /* enable master interrupt */
5db86843 852 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 853 UVD, 0, mmUVD_MASTINT_EN),
854 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
855
dc8ae677 856 if (indirect)
5db86843
JZ		 857 psp_update_vcn_sram(adev, 0, adev->vcn.inst->dpg_sram_gpu_addr,
858 (uint32_t)((uintptr_t)adev->vcn.inst->dpg_sram_curr_addr -
859 (uintptr_t)adev->vcn.inst->dpg_sram_cpu_addr));
dc8ae677 860
bf4865b5
LL		 861 /* force RBC into idle state */
862 rb_bufsz = order_base_2(ring->ring_size);
863 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
864 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
865 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
866 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
867 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
868 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
869
ef563ff4
JZ		 870 /* Stall DPG before WPTR/RPTR reset */
871 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),
872 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,
873 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
bf4865b5
LL		 874 /* set the write pointer delay */
875 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);
876
877 /* set the wb address */
878 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR,
879 (upper_32_bits(ring->gpu_addr) >> 2));
880
881 /* programm the RB_BASE for ring buffer */
882 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
883 lower_32_bits(ring->gpu_addr));
884 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
885 upper_32_bits(ring->gpu_addr));
886
887 /* Initialize the ring buffer's read and write pointers */
888 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
889
890 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0);
891
892 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
893 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
894 lower_32_bits(ring->wptr));
895
ef563ff4
JZ		 896 /* Unstall DPG */
897 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),
898 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
bf4865b5
LL		 899 return 0;
900}
901
1b61de45
LL		 902static int vcn_v2_0_start(struct amdgpu_device *adev)
903{
c01b6a1d 904 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
1b61de45
LL		 905 uint32_t rb_bufsz, tmp;
906 uint32_t lmi_swap_cntl;
907 int i, j, r;
908
c113ba15
JX		 909 if (adev->pm.dpm_enabled)
910 amdgpu_dpm_enable_uvd(adev, true);
911
b0f3cd31
LL		 912 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
913 return vcn_v2_0_start_dpg_mode(adev, adev->vcn.indirect_sram);
bf4865b5 914
1b61de45
LL		 915 vcn_v2_0_disable_static_power_gating(adev);
916
917 /* set uvd status busy */
918 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
919 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
920
921 /*SW clock gating */
922 vcn_v2_0_disable_clock_gating(adev);
923
924 /* enable VCPU clock */
925 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL),
926 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
927
928 /* disable master interrupt */
929 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
930 ~UVD_MASTINT_EN__VCPU_EN_MASK);
931
932 /* setup mmUVD_LMI_CTRL */
933 tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL);
934 WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp |
935 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
936 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
937 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
938 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
939
940 /* setup mmUVD_MPC_CNTL */
941 tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL);
942 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
943 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
944 WREG32_SOC15(VCN, 0, mmUVD_MPC_CNTL, tmp);
945
946 /* setup UVD_MPC_SET_MUXA0 */
947 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0,
948 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
949 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
950 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
951 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
952
953 /* setup UVD_MPC_SET_MUXB0 */
954 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0,
955 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
956 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
957 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
958 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
959
960 /* setup mmUVD_MPC_SET_MUX */
961 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX,
962 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
963 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
964 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
965
966 vcn_v2_0_mc_resume(adev);
967
968 /* release VCPU reset to boot */
969 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
970 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
971
972 /* enable LMI MC and UMC channels */
973 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
974 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
975
976 tmp = RREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET);
977 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
978 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
979 WREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET, tmp);
980
981 /* disable byte swapping */
982 lmi_swap_cntl = 0;
983#ifdef __BIG_ENDIAN
984 /* swap (8 in 32) RB and IB */
985 lmi_swap_cntl = 0xa;
986#endif
987 WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
988
989 for (i = 0; i < 10; ++i) {
990 uint32_t status;
991
992 for (j = 0; j < 100; ++j) {
993 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);
994 if (status & 2)
995 break;
996 mdelay(10);
997 }
998 r = 0;
999 if (status & 2)
1000 break;
1001
1002 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n");
1003 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1004 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
1005 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1006 mdelay(10);
1007 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
1008 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1009 mdelay(10);
1010 r = -1;
1011 }
1012
1013 if (r) {
1014 DRM_ERROR("VCN decode not responding, giving up!!!\n");
1015 return r;
1016 }
1017
1018 /* enable master interrupt */
1019 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
1020 UVD_MASTINT_EN__VCPU_EN_MASK,
1021 ~UVD_MASTINT_EN__VCPU_EN_MASK);
1022
1023 /* clear the busy bit of VCN_STATUS */
1024 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0,
1025 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
1026
1027 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_VMID, 0);
1028
1029 /* force RBC into idle state */
1030 rb_bufsz = order_base_2(ring->ring_size);
1031 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1032 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1033 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1034 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1035 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1036 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
1037
1038 /* programm the RB_BASE for ring buffer */
1039 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1040 lower_32_bits(ring->gpu_addr));
1041 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1042 upper_32_bits(ring->gpu_addr));
1043
1044 /* Initialize the ring buffer's read and write pointers */
1045 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
1046
1047 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1048 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1049 lower_32_bits(ring->wptr));
1050
c01b6a1d 1051 ring = &adev->vcn.inst->ring_enc[0];
1b61de45
LL		 1052 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1053 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1054 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
1055 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1056 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
1057
c01b6a1d 1058 ring = &adev->vcn.inst->ring_enc[1];
1b61de45
LL		 1059 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1060 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1061 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1062 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1063 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
1064
b0f3cd31 1065 return 0;
1b61de45
LL		 1066}
1067
bf4865b5
LL		 1068static int vcn_v2_0_stop_dpg_mode(struct amdgpu_device *adev)
1069{
1070 int ret_code = 0;
1071 uint32_t tmp;
1072
1073 /* Wait for power status to be 1 */
1074 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1,
1075 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
1076
1077 /* wait for read ptr to be equal to write ptr */
1078 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
1079 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
1080
1081 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
1082 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF, ret_code);
1083
bf4865b5
LL		 1084 tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
1085 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
1086
1087 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1,
1088 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
1089
1090 /* disable dynamic power gating mode */
1091 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
1092 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
1093
1094 return 0;
1095}
1096
1b61de45
LL		 1097static int vcn_v2_0_stop(struct amdgpu_device *adev)
1098{
1099 uint32_t tmp;
1100 int r;
1101
bf4865b5
LL		 1102 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1103 r = vcn_v2_0_stop_dpg_mode(adev);
1104 if (r)
1105 return r;
1106 goto power_off;
1107 }
1108
1b61de45
LL		 1109 /* wait for uvd idle */
1110 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, r);
1111 if (r)
1112 return r;
1113
1114 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
1115 UVD_LMI_STATUS__READ_CLEAN_MASK |
1116 UVD_LMI_STATUS__WRITE_CLEAN_MASK |
1117 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
1118 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp, r);
1119 if (r)
1120 return r;
1121
1122 /* stall UMC channel */
1123 tmp = RREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2);
1124 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
1125 WREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2, tmp);
1126
1127 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK|
1128 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
1129 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp, r);
1130 if (r)
1131 return r;
1132
1133 /* disable VCPU clock */
1134 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
1135 ~(UVD_VCPU_CNTL__CLK_EN_MASK));
1136
1137 /* reset LMI UMC */
1138 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1139 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK,
1140 ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
1141
1142 /* reset LMI */
1143 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1144 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK,
1145 ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK);
1146
1147 /* reset VCPU */
1148 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1149 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
1150 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1151
1152 /* clear status */
1153 WREG32_SOC15(VCN, 0, mmUVD_STATUS, 0);
1154
1155 vcn_v2_0_enable_clock_gating(adev);
1156 vcn_v2_0_enable_static_power_gating(adev);
1157
bf4865b5 1158power_off:
c113ba15
JX		 1159 if (adev->pm.dpm_enabled)
1160 amdgpu_dpm_enable_uvd(adev, false);
1161
1b61de45
LL		 1162 return 0;
1163}
1164
7282da0b 1165static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,
597e6ac3 1166 int inst_idx, struct dpg_pause_state *new_state)
7282da0b
LL		 1167{
1168 struct amdgpu_ring *ring;
1169 uint32_t reg_data = 0;
1170 int ret_code;
1171
1172 /* pause/unpause if state is changed */
f4d0242b 1173 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
7282da0b 1174 DRM_DEBUG("dpg pause state changed %d -> %d",
f4d0242b 1175 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based);
7282da0b
LL		 1176 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &
1177 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1178
1179 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
1180 ret_code = 0;
1181 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 0x1,
1182 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
1183
1184 if (!ret_code) {
1185 /* pause DPG */
1186 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1187 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1188
1189 /* wait for ACK */
1190 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE,
1191 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
1192 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, ret_code);
1193
ef563ff4
JZ		 1194 /* Stall DPG before WPTR/RPTR reset */
1195 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),
1196 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,
1197 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
7282da0b 1198 /* Restore */
c01b6a1d 1199 ring = &adev->vcn.inst->ring_enc[0];
ef563ff4 1200 ring->wptr = 0;
7282da0b
LL		 1201 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
1202 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1203 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
1204 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1205 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1206
c01b6a1d 1207 ring = &adev->vcn.inst->ring_enc[1];
ef563ff4 1208 ring->wptr = 0;
7282da0b
LL		 1209 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1210 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1211 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
1212 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1213 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1214
1215 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1216 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);
ef563ff4
JZ		 1217 /* Unstall DPG */
1218 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),
1219 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
7282da0b
LL		 1220
1221 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1222 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,
1223 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
1224 }
1225 } else {
1226 /* unpause dpg, no need to wait */
1227 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1228 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1229 }
f4d0242b 1230 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
7282da0b
LL		 1231 }
1232
1233 return 0;
1234}
1235
1b61de45
LL		 1236static bool vcn_v2_0_is_idle(void *handle)
1237{
1238 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1239
1240 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);
1241}
1242
1243static int vcn_v2_0_wait_for_idle(void *handle)
1244{
1245 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1246 int ret = 0;
1247
1248 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE,
1249 UVD_STATUS__IDLE, ret);
1250
1251 return ret;
1252}
1253
1254static int vcn_v2_0_set_clockgating_state(void *handle,
1255 enum amd_clockgating_state state)
1256{
1257 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a9d4fe2f 1258 bool enable = (state == AMD_CG_STATE_GATE);
1b61de45 1259
cc9f2fba
ML		 1260 if (amdgpu_sriov_vf(adev))
1261 return 0;
1262
1b61de45
LL		 1263 if (enable) {
1264 /* wait for STATUS to clear */
23edf7f1 1265 if (!vcn_v2_0_is_idle(handle))
1b61de45
LL		 1266 return -EBUSY;
1267 vcn_v2_0_enable_clock_gating(adev);
1268 } else {
1269 /* disable HW gating and enable Sw gating */
1270 vcn_v2_0_disable_clock_gating(adev);
1271 }
1272 return 0;
1273}
1274
1275/**
1276 * vcn_v2_0_dec_ring_get_rptr - get read pointer
1277 *
1278 * @ring: amdgpu_ring pointer
1279 *
1280 * Returns the current hardware read pointer
1281 */
1282static uint64_t vcn_v2_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
1283{
1284 struct amdgpu_device *adev = ring->adev;
1285
1286 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1287}
1288
1289/**
1290 * vcn_v2_0_dec_ring_get_wptr - get write pointer
1291 *
1292 * @ring: amdgpu_ring pointer
1293 *
1294 * Returns the current hardware write pointer
1295 */
1296static uint64_t vcn_v2_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
1297{
1298 struct amdgpu_device *adev = ring->adev;
1299
1300 if (ring->use_doorbell)
1301 return adev->wb.wb[ring->wptr_offs];
1302 else
1303 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR);
1304}
1305
1306/**
1307 * vcn_v2_0_dec_ring_set_wptr - set write pointer
1308 *
1309 * @ring: amdgpu_ring pointer
1310 *
1311 * Commits the write pointer to the hardware
1312 */
1313static void vcn_v2_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
1314{
1315 struct amdgpu_device *adev = ring->adev;
1316
7282da0b
LL		 1317 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1318 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2,
1319 lower_32_bits(ring->wptr) | 0x80000000);
1320
1b61de45
LL		 1321 if (ring->use_doorbell) {
1322 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
1323 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1324 } else {
1325 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
1326 }
1327}
1328
1329/**
1330 * vcn_v2_0_dec_ring_insert_start - insert a start command
1331 *
1332 * @ring: amdgpu_ring pointer
1333 *
1334 * Write a start command to the ring.
1335 */
cdbd115e 1336void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring)
1b61de45 1337{
22a8f442
LL		 1338 struct amdgpu_device *adev = ring->adev;
1339
1340 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1b61de45 1341 amdgpu_ring_write(ring, 0);
22a8f442 1342 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
333fe325 1343 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1));
1b61de45
LL		 1344}
1345
1346/**
1347 * vcn_v2_0_dec_ring_insert_end - insert a end command
1348 *
1349 * @ring: amdgpu_ring pointer
1350 *
1351 * Write a end command to the ring.
1352 */
cdbd115e 1353void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring)
1b61de45 1354{
22a8f442
LL		 1355 struct amdgpu_device *adev = ring->adev;
1356
1357 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
333fe325 1358 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_END << 1));
1b61de45
LL		 1359}
1360
1361/**
1362 * vcn_v2_0_dec_ring_insert_nop - insert a nop command
1363 *
1364 * @ring: amdgpu_ring pointer
1365 *
1366 * Write a nop command to the ring.
1367 */
cdbd115e 1368void vcn_v2_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
1b61de45 1369{
22a8f442 1370 struct amdgpu_device *adev = ring->adev;
1b61de45
LL		 1371 int i;
1372
1373 WARN_ON(ring->wptr % 2 || count % 2);
1374
1375 for (i = 0; i < count / 2; i++) {
22a8f442 1376 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.nop, 0));
1b61de45
LL		 1377 amdgpu_ring_write(ring, 0);
1378 }
1379}
1380
1381/**
1382 * vcn_v2_0_dec_ring_emit_fence - emit an fence & trap command
1383 *
1384 * @ring: amdgpu_ring pointer
1385 * @fence: fence to emit
1386 *
1387 * Write a fence and a trap command to the ring.
1388 */
cdbd115e
LL		 1389void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1390 unsigned flags)
1b61de45 1391{
22a8f442 1392 struct amdgpu_device *adev = ring->adev;
1b61de45 1393
22a8f442
LL		 1394 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1395 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.context_id, 0));
1b61de45
LL		 1396 amdgpu_ring_write(ring, seq);
1397
22a8f442 1398 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1b61de45
LL		 1399 amdgpu_ring_write(ring, addr & 0xffffffff);
1400
22a8f442 1401 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));
1b61de45
LL		 1402 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
1403
22a8f442 1404 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
333fe325 1405 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_FENCE << 1));
1b61de45 1406
22a8f442 1407 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1b61de45
LL		 1408 amdgpu_ring_write(ring, 0);
1409
22a8f442 1410 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));
1b61de45
LL		 1411 amdgpu_ring_write(ring, 0);
1412
22a8f442 1413 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1b61de45 1414
333fe325 1415 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_TRAP << 1));
1b61de45
LL		 1416}
1417
1418/**
1419 * vcn_v2_0_dec_ring_emit_ib - execute indirect buffer
1420 *
1421 * @ring: amdgpu_ring pointer
1422 * @ib: indirect buffer to execute
1423 *
1424 * Write ring commands to execute the indirect buffer
1425 */
cdbd115e
LL		 1426void vcn_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
1427 struct amdgpu_job *job,
1428 struct amdgpu_ib *ib,
1429 uint32_t flags)
1b61de45 1430{
22a8f442 1431 struct amdgpu_device *adev = ring->adev;
1b61de45
LL		 1432 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1433
22a8f442 1434 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_vmid, 0));
1b61de45
LL		 1435 amdgpu_ring_write(ring, vmid);
1436
22a8f442 1437 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_bar_low, 0));
1b61de45 1438 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
22a8f442 1439 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_bar_high, 0));
1b61de45 1440 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
22a8f442 1441 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_size, 0));
1b61de45
LL		 1442 amdgpu_ring_write(ring, ib->length_dw);
1443}
1444
cdbd115e
LL		 1445void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1446 uint32_t val, uint32_t mask)
1b61de45 1447{
22a8f442
LL		 1448 struct amdgpu_device *adev = ring->adev;
1449
1450 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1b61de45
LL		 1451 amdgpu_ring_write(ring, reg << 2);
1452
22a8f442 1453 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));
1b61de45
LL		 1454 amdgpu_ring_write(ring, val);
1455
22a8f442 1456 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.gp_scratch8, 0));
1b61de45
LL		 1457 amdgpu_ring_write(ring, mask);
1458
22a8f442 1459 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1b61de45 1460
333fe325 1461 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_REG_READ_COND_WAIT << 1));
1b61de45
LL		 1462}
1463
cdbd115e
LL		 1464void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
1465 unsigned vmid, uint64_t pd_addr)
1b61de45
LL		 1466{
1467 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1468 uint32_t data0, data1, mask;
1469
1470 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1471
1472 /* wait for register write */
1473 data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2;
1474 data1 = lower_32_bits(pd_addr);
1475 mask = 0xffffffff;
1476 vcn_v2_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);
1477}
1478
cdbd115e
LL		 1479void vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring,
1480 uint32_t reg, uint32_t val)
1b61de45 1481{
22a8f442
LL		 1482 struct amdgpu_device *adev = ring->adev;
1483
1484 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1b61de45
LL		 1485 amdgpu_ring_write(ring, reg << 2);
1486
22a8f442 1487 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));
1b61de45
LL		 1488 amdgpu_ring_write(ring, val);
1489
22a8f442 1490 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1b61de45 1491
333fe325 1492 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_WRITE_REG << 1));
1b61de45
LL		 1493}
1494
1495/**
1496 * vcn_v2_0_enc_ring_get_rptr - get enc read pointer
1497 *
1498 * @ring: amdgpu_ring pointer
1499 *
1500 * Returns the current hardware enc read pointer
1501 */
1502static uint64_t vcn_v2_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
1503{
1504 struct amdgpu_device *adev = ring->adev;
1505
c01b6a1d 1506 if (ring == &adev->vcn.inst->ring_enc[0])
1b61de45
LL		 1507 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);
1508 else
1509 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2);
1510}
1511
1512 /**
1513 * vcn_v2_0_enc_ring_get_wptr - get enc write pointer
1514 *
1515 * @ring: amdgpu_ring pointer
1516 *
1517 * Returns the current hardware enc write pointer
1518 */
1519static uint64_t vcn_v2_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
1520{
1521 struct amdgpu_device *adev = ring->adev;
1522
c01b6a1d 1523 if (ring == &adev->vcn.inst->ring_enc[0]) {
1b61de45
LL		 1524 if (ring->use_doorbell)
1525 return adev->wb.wb[ring->wptr_offs];
1526 else
1527 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
1528 } else {
1529 if (ring->use_doorbell)
1530 return adev->wb.wb[ring->wptr_offs];
1531 else
1532 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
1533 }
1534}
1535
1536 /**
1537 * vcn_v2_0_enc_ring_set_wptr - set enc write pointer
1538 *
1539 * @ring: amdgpu_ring pointer
1540 *
1541 * Commits the enc write pointer to the hardware
1542 */
1543static void vcn_v2_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
1544{
1545 struct amdgpu_device *adev = ring->adev;
1546
c01b6a1d 1547 if (ring == &adev->vcn.inst->ring_enc[0]) {
1b61de45
LL		 1548 if (ring->use_doorbell) {
1549 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
1550 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1551 } else {
1552 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1553 }
1554 } else {
1555 if (ring->use_doorbell) {
1556 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
1557 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1558 } else {
1559 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1560 }
1561 }
1562}
1563
1564/**
1565 * vcn_v2_0_enc_ring_emit_fence - emit an enc fence & trap command
1566 *
1567 * @ring: amdgpu_ring pointer
1568 * @fence: fence to emit
1569 *
1570 * Write enc a fence and a trap command to the ring.
1571 */
cdbd115e
LL		 1572void vcn_v2_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1573 u64 seq, unsigned flags)
1b61de45
LL		 1574{
1575 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1576
1577 amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE);
1578 amdgpu_ring_write(ring, addr);
1579 amdgpu_ring_write(ring, upper_32_bits(addr));
1580 amdgpu_ring_write(ring, seq);
1581 amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP);
1582}
1583
cdbd115e 1584void vcn_v2_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1b61de45
LL		 1585{
1586 amdgpu_ring_write(ring, VCN_ENC_CMD_END);
1587}
1588
1589/**
1590 * vcn_v2_0_enc_ring_emit_ib - enc execute indirect buffer
1591 *
1592 * @ring: amdgpu_ring pointer
1593 * @ib: indirect buffer to execute
1594 *
1595 * Write enc ring commands to execute the indirect buffer
1596 */
cdbd115e
LL		 1597void vcn_v2_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1598 struct amdgpu_job *job,
1599 struct amdgpu_ib *ib,
1600 uint32_t flags)
1b61de45
LL		 1601{
1602 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1603
1604 amdgpu_ring_write(ring, VCN_ENC_CMD_IB);
1605 amdgpu_ring_write(ring, vmid);
1606 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1607 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1608 amdgpu_ring_write(ring, ib->length_dw);
1609}
1610
cdbd115e
LL		 1611void vcn_v2_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1612 uint32_t val, uint32_t mask)
1b61de45
LL		 1613{
1614 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT);
1615 amdgpu_ring_write(ring, reg << 2);
1616 amdgpu_ring_write(ring, mask);
1617 amdgpu_ring_write(ring, val);
1618}
1619
cdbd115e
LL		 1620void vcn_v2_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1621 unsigned int vmid, uint64_t pd_addr)
1b61de45
LL		 1622{
1623 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1624
1625 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1626
1627 /* wait for reg writes */
1628 vcn_v2_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2,
1629 lower_32_bits(pd_addr), 0xffffffff);
1630}
1631
cdbd115e 1632void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
1b61de45
LL		 1633{
1634 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
1635 amdgpu_ring_write(ring, reg << 2);
1636 amdgpu_ring_write(ring, val);
1637}
1638
1b61de45
LL		 1639static int vcn_v2_0_set_interrupt_state(struct amdgpu_device *adev,
1640 struct amdgpu_irq_src *source,
1641 unsigned type,
1642 enum amdgpu_interrupt_state state)
1643{
1644 return 0;
1645}
1646
1647static int vcn_v2_0_process_interrupt(struct amdgpu_device *adev,
1648 struct amdgpu_irq_src *source,
1649 struct amdgpu_iv_entry *entry)
1650{
1651 DRM_DEBUG("IH: VCN TRAP\n");
1652
1653 switch (entry->src_id) {
1654 case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT:
c01b6a1d 1655 amdgpu_fence_process(&adev->vcn.inst->ring_dec);
1b61de45
LL		 1656 break;
1657 case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE:
c01b6a1d 1658 amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]);
1b61de45
LL		 1659 break;
1660 case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY:
c01b6a1d 1661 amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]);
1b61de45 1662 break;
1b61de45
LL		 1663 default:
1664 DRM_ERROR("Unhandled interrupt: %d %d\n",
1665 entry->src_id, entry->src_data[0]);
1666 break;
1667 }
1668
1669 return 0;
1670}
1671
b6501217 1672int vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring *ring)
c74dbe44
TT		 1673{
1674 struct amdgpu_device *adev = ring->adev;
1675 uint32_t tmp = 0;
1676 unsigned i;
1677 int r;
1678
68430c6b
ML		 1679 if (amdgpu_sriov_vf(adev))
1680 return 0;
1681
c74dbe44
TT		 1682 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);
1683 r = amdgpu_ring_alloc(ring, 4);
1684 if (r)
1685 return r;
1686 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1687 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1));
1688 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0));
1689 amdgpu_ring_write(ring, 0xDEADBEEF);
1690 amdgpu_ring_commit(ring);
1691 for (i = 0; i < adev->usec_timeout; i++) {
1692 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9);
1693 if (tmp == 0xDEADBEEF)
1694 break;
9a2ffeb5 1695 udelay(1);
c74dbe44
TT		 1696 }
1697
1698 if (i >= adev->usec_timeout)
1699 r = -ETIMEDOUT;
1700
1701 return r;
1702}
1703
1704
1b61de45
LL		 1705static int vcn_v2_0_set_powergating_state(void *handle,
1706 enum amd_powergating_state state)
1707{
1708 /* This doesn't actually powergate the VCN block.
1709 * That's done in the dpm code via the SMC. This
1710 * just re-inits the block as necessary. The actual
1711 * gating still happens in the dpm code. We should
1712 * revisit this when there is a cleaner line between
1713 * the smc and the hw blocks
1714 */
1715 int ret;
1716 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1717
cc9f2fba
ML		 1718 if (amdgpu_sriov_vf(adev)) {
1719 adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
1720 return 0;
1721 }
1722
1b61de45
LL		 1723 if (state == adev->vcn.cur_state)
1724 return 0;
1725
1726 if (state == AMD_PG_STATE_GATE)
1727 ret = vcn_v2_0_stop(adev);
1728 else
1729 ret = vcn_v2_0_start(adev);
1730
1731 if (!ret)
1732 adev->vcn.cur_state = state;
1733 return ret;
1734}
1735
dd26858a
ML		 1736static int vcn_v2_0_start_mmsch(struct amdgpu_device *adev,
1737 struct amdgpu_mm_table *table)
1738{
1739 uint32_t data = 0, loop;
1740 uint64_t addr = table->gpu_addr;
1741 struct mmsch_v2_0_init_header *header;
1742 uint32_t size;
1743 int i;
1744
1745 header = (struct mmsch_v2_0_init_header *)table->cpu_addr;
1746 size = header->header_size + header->vcn_table_size;
1747
1748 /* 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr
1749 * of memory descriptor location
1750 */
1751 WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr));
1752 WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr));
1753
1754 /* 2, update vmid of descriptor */
1755 data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_VMID);
1756 data &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;
1757 /* use domain0 for MM scheduler */
1758 data |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);
1759 WREG32_SOC15(UVD, 0, mmMMSCH_VF_VMID, data);
1760
1761 /* 3, notify mmsch about the size of this descriptor */
1762 WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_SIZE, size);
1763
1764 /* 4, set resp to zero */
1765 WREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP, 0);
1766
1767 adev->vcn.inst->ring_dec.wptr = 0;
1768 adev->vcn.inst->ring_dec.wptr_old = 0;
1769 vcn_v2_0_dec_ring_set_wptr(&adev->vcn.inst->ring_dec);
1770
1771 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
1772 adev->vcn.inst->ring_enc[i].wptr = 0;
1773 adev->vcn.inst->ring_enc[i].wptr_old = 0;
1774 vcn_v2_0_enc_ring_set_wptr(&adev->vcn.inst->ring_enc[i]);
1775 }
1776
1777 /* 5, kick off the initialization and wait until
1778 * VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero
1779 */
1780 WREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_HOST, 0x10000001);
1781
1782 data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP);
1783 loop = 1000;
1784 while ((data & 0x10000002) != 0x10000002) {
1785 udelay(10);
1786 data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP);
1787 loop--;
1788 if (!loop)
1789 break;
1790 }
1791
1792 if (!loop) {
1793 DRM_ERROR("failed to init MMSCH, " \
1794 "mmMMSCH_VF_MAILBOX_RESP = 0x%08x\n", data);
1795 return -EBUSY;
1796 }
1797
1798 return 0;
1799}
1800
1801static int vcn_v2_0_start_sriov(struct amdgpu_device *adev)
1802{
1803 int r;
1804 uint32_t tmp;
1805 struct amdgpu_ring *ring;
1806 uint32_t offset, size;
1807 uint32_t table_size = 0;
1808 struct mmsch_v2_0_cmd_direct_write direct_wt = { {0} };
1809 struct mmsch_v2_0_cmd_direct_read_modify_write direct_rd_mod_wt = { {0} };
1810 struct mmsch_v2_0_cmd_direct_polling direct_poll = { {0} };
1811 struct mmsch_v2_0_cmd_end end = { {0} };
1812 struct mmsch_v2_0_init_header *header;
1813 uint32_t *init_table = adev->virt.mm_table.cpu_addr;
1814 uint8_t i = 0;
1815
1816 header = (struct mmsch_v2_0_init_header *)init_table;
1817 direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE;
1818 direct_rd_mod_wt.cmd_header.command_type =
1819 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
1820 direct_poll.cmd_header.command_type =
1821 MMSCH_COMMAND__DIRECT_REG_POLLING;
1822 end.cmd_header.command_type = MMSCH_COMMAND__END;
1823
1824 if (header->vcn_table_offset == 0 && header->vcn_table_size == 0) {
1825 header->version = MMSCH_VERSION;
1826 header->header_size = sizeof(struct mmsch_v2_0_init_header) >> 2;
1827
1828 header->vcn_table_offset = header->header_size;
1829
1830 init_table += header->vcn_table_offset;
1831
1832 size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
1833
1834 MMSCH_V2_0_INSERT_DIRECT_RD_MOD_WT(
1835 SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),
1836 0xFFFFFFFF, 0x00000004);
1837
1838 /* mc resume*/
1839 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1840 tmp = AMDGPU_UCODE_ID_VCN;
1841 MMSCH_V2_0_INSERT_DIRECT_WT(
1842 SOC15_REG_OFFSET(UVD, i,
1843 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1844 adev->firmware.ucode[tmp].tmr_mc_addr_lo);
1845 MMSCH_V2_0_INSERT_DIRECT_WT(
1846 SOC15_REG_OFFSET(UVD, i,
1847 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1848 adev->firmware.ucode[tmp].tmr_mc_addr_hi);
1849 offset = 0;
1850 } else {
1851 MMSCH_V2_0_INSERT_DIRECT_WT(
1852 SOC15_REG_OFFSET(UVD, i,
1853 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1854 lower_32_bits(adev->vcn.inst->gpu_addr));
1855 MMSCH_V2_0_INSERT_DIRECT_WT(
1856 SOC15_REG_OFFSET(UVD, i,
1857 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1858 upper_32_bits(adev->vcn.inst->gpu_addr));
1859 offset = size;
1860 }
1861
1862 MMSCH_V2_0_INSERT_DIRECT_WT(
1863 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET0),
1864 0);
1865 MMSCH_V2_0_INSERT_DIRECT_WT(
1866 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0),
1867 size);
1868
1869 MMSCH_V2_0_INSERT_DIRECT_WT(
1870 SOC15_REG_OFFSET(UVD, i,
1871 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
1872 lower_32_bits(adev->vcn.inst->gpu_addr + offset));
1873 MMSCH_V2_0_INSERT_DIRECT_WT(
1874 SOC15_REG_OFFSET(UVD, i,
1875 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
1876 upper_32_bits(adev->vcn.inst->gpu_addr + offset));
1877 MMSCH_V2_0_INSERT_DIRECT_WT(
1878 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET1),
1879 0);
1880 MMSCH_V2_0_INSERT_DIRECT_WT(
1881 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE1),
1882 AMDGPU_VCN_STACK_SIZE);
1883
1884 MMSCH_V2_0_INSERT_DIRECT_WT(
1885 SOC15_REG_OFFSET(UVD, i,
1886 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
1887 lower_32_bits(adev->vcn.inst->gpu_addr + offset +
1888 AMDGPU_VCN_STACK_SIZE));
1889 MMSCH_V2_0_INSERT_DIRECT_WT(
1890 SOC15_REG_OFFSET(UVD, i,
1891 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
1892 upper_32_bits(adev->vcn.inst->gpu_addr + offset +
1893 AMDGPU_VCN_STACK_SIZE));
1894 MMSCH_V2_0_INSERT_DIRECT_WT(
1895 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET2),
1896 0);
1897 MMSCH_V2_0_INSERT_DIRECT_WT(
1898 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2),
1899 AMDGPU_VCN_CONTEXT_SIZE);
1900
1901 for (r = 0; r < adev->vcn.num_enc_rings; ++r) {
1902 ring = &adev->vcn.inst->ring_enc[r];
1903 ring->wptr = 0;
1904 MMSCH_V2_0_INSERT_DIRECT_WT(
1905 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO),
1906 lower_32_bits(ring->gpu_addr));
1907 MMSCH_V2_0_INSERT_DIRECT_WT(
1908 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI),
1909 upper_32_bits(ring->gpu_addr));
1910 MMSCH_V2_0_INSERT_DIRECT_WT(
1911 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE),
1912 ring->ring_size / 4);
1913 }
1914
1915 ring = &adev->vcn.inst->ring_dec;
1916 ring->wptr = 0;
1917 MMSCH_V2_0_INSERT_DIRECT_WT(
1918 SOC15_REG_OFFSET(UVD, i,
1919 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW),
1920 lower_32_bits(ring->gpu_addr));
1921 MMSCH_V2_0_INSERT_DIRECT_WT(
1922 SOC15_REG_OFFSET(UVD, i,
1923 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH),
1924 upper_32_bits(ring->gpu_addr));
1925 /* force RBC into idle state */
1926 tmp = order_base_2(ring->ring_size);
1927 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp);
1928 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1929 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1930 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1931 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1932 MMSCH_V2_0_INSERT_DIRECT_WT(
1933 SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp);
1934
1935 /* add end packet */
1936 tmp = sizeof(struct mmsch_v2_0_cmd_end);
1937 memcpy((void *)init_table, &end, tmp);
1938 table_size += (tmp / 4);
1939 header->vcn_table_size = table_size;
1940
1941 }
1942 return vcn_v2_0_start_mmsch(adev, &adev->virt.mm_table);
1943}
1944
1b61de45
LL		 1945static const struct amd_ip_funcs vcn_v2_0_ip_funcs = {
1946 .name = "vcn_v2_0",
1947 .early_init = vcn_v2_0_early_init,
1948 .late_init = NULL,
1949 .sw_init = vcn_v2_0_sw_init,
1950 .sw_fini = vcn_v2_0_sw_fini,
1951 .hw_init = vcn_v2_0_hw_init,
1952 .hw_fini = vcn_v2_0_hw_fini,
1953 .suspend = vcn_v2_0_suspend,
1954 .resume = vcn_v2_0_resume,
1955 .is_idle = vcn_v2_0_is_idle,
1956 .wait_for_idle = vcn_v2_0_wait_for_idle,
1957 .check_soft_reset = NULL,
1958 .pre_soft_reset = NULL,
1959 .soft_reset = NULL,
1960 .post_soft_reset = NULL,
1961 .set_clockgating_state = vcn_v2_0_set_clockgating_state,
1962 .set_powergating_state = vcn_v2_0_set_powergating_state,
1963};
1964
1965static const struct amdgpu_ring_funcs vcn_v2_0_dec_ring_vm_funcs = {
1966 .type = AMDGPU_RING_TYPE_VCN_DEC,
1967 .align_mask = 0xf,
a2d15ed7 1968 .vmhub = AMDGPU_MMHUB_0,
1b61de45
LL		 1969 .get_rptr = vcn_v2_0_dec_ring_get_rptr,
1970 .get_wptr = vcn_v2_0_dec_ring_get_wptr,
1971 .set_wptr = vcn_v2_0_dec_ring_set_wptr,
1972 .emit_frame_size =
1973 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
1974 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
1975 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */
1976 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */
1977 6,
1978 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */
1979 .emit_ib = vcn_v2_0_dec_ring_emit_ib,
1980 .emit_fence = vcn_v2_0_dec_ring_emit_fence,
1981 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush,
c74dbe44 1982 .test_ring = vcn_v2_0_dec_ring_test_ring,
1b61de45
LL		 1983 .test_ib = amdgpu_vcn_dec_ring_test_ib,
1984 .insert_nop = vcn_v2_0_dec_ring_insert_nop,
1985 .insert_start = vcn_v2_0_dec_ring_insert_start,
1986 .insert_end = vcn_v2_0_dec_ring_insert_end,
1987 .pad_ib = amdgpu_ring_generic_pad_ib,
1988 .begin_use = amdgpu_vcn_ring_begin_use,
1989 .end_use = amdgpu_vcn_ring_end_use,
1990 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg,
1991 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait,
1992 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1993};
1994
1995static const struct amdgpu_ring_funcs vcn_v2_0_enc_ring_vm_funcs = {
1996 .type = AMDGPU_RING_TYPE_VCN_ENC,
1997 .align_mask = 0x3f,
1998 .nop = VCN_ENC_CMD_NO_OP,
a2d15ed7 1999 .vmhub = AMDGPU_MMHUB_0,
1b61de45
LL		 2000 .get_rptr = vcn_v2_0_enc_ring_get_rptr,
2001 .get_wptr = vcn_v2_0_enc_ring_get_wptr,
2002 .set_wptr = vcn_v2_0_enc_ring_set_wptr,
2003 .emit_frame_size =
2004 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2005 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
2006 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */
2007 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */
2008 1, /* vcn_v2_0_enc_ring_insert_end */
2009 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */
2010 .emit_ib = vcn_v2_0_enc_ring_emit_ib,
2011 .emit_fence = vcn_v2_0_enc_ring_emit_fence,
2012 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush,
2013 .test_ring = amdgpu_vcn_enc_ring_test_ring,
2014 .test_ib = amdgpu_vcn_enc_ring_test_ib,
2015 .insert_nop = amdgpu_ring_insert_nop,
2016 .insert_end = vcn_v2_0_enc_ring_insert_end,
2017 .pad_ib = amdgpu_ring_generic_pad_ib,
2018 .begin_use = amdgpu_vcn_ring_begin_use,
2019 .end_use = amdgpu_vcn_ring_end_use,
2020 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg,
2021 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,
2022 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2023};
2024
1b61de45
LL		 2025static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev)
2026{
c01b6a1d 2027 adev->vcn.inst->ring_dec.funcs = &vcn_v2_0_dec_ring_vm_funcs;
1b61de45
LL		 2028 DRM_INFO("VCN decode is enabled in VM mode\n");
2029}
2030
2031static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev)
2032{
2033 int i;
2034
2035 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
c01b6a1d 2036 adev->vcn.inst->ring_enc[i].funcs = &vcn_v2_0_enc_ring_vm_funcs;
1b61de45
LL		 2037
2038 DRM_INFO("VCN encode is enabled in VM mode\n");
2039}
2040
1b61de45
LL		 2041static const struct amdgpu_irq_src_funcs vcn_v2_0_irq_funcs = {
2042 .set = vcn_v2_0_set_interrupt_state,
2043 .process = vcn_v2_0_process_interrupt,
2044};
2045
2046static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev)
2047{
21a174f5 2048 adev->vcn.inst->irq.num_types = adev->vcn.num_enc_rings + 1;
c01b6a1d 2049 adev->vcn.inst->irq.funcs = &vcn_v2_0_irq_funcs;
1b61de45
LL		 2050}
2051
2052const struct amdgpu_ip_block_version vcn_v2_0_ip_block =
2053{
2054 .type = AMD_IP_BLOCK_TYPE_VCN,
2055 .major = 2,
2056 .minor = 0,
2057 .rev = 0,
2058 .funcs = &vcn_v2_0_ip_funcs,
2059};
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