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[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / amd / amdkfd / kfd_device_queue_manager.c
CommitLineData
64c7f8cf
BG		 1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/slab.h>
25#include <linux/list.h>
26#include <linux/types.h>
27#include <linux/printk.h>
28#include <linux/bitops.h>
29#include "kfd_priv.h"
30#include "kfd_device_queue_manager.h"
31#include "kfd_mqd_manager.h"
32#include "cik_regs.h"
33#include "kfd_kernel_queue.h"
64c7f8cf
BG		 34
35/* Size of the per-pipe EOP queue */
36#define CIK_HPD_EOP_BYTES_LOG2 11
37#define CIK_HPD_EOP_BYTES (1U << CIK_HPD_EOP_BYTES_LOG2)
38
64c7f8cf
BG		 39static int set_pasid_vmid_mapping(struct device_queue_manager *dqm,
40 unsigned int pasid, unsigned int vmid);
41
42static int create_compute_queue_nocpsch(struct device_queue_manager *dqm,
43 struct queue *q,
44 struct qcm_process_device *qpd);
bcea3081 45
64c7f8cf
BG		 46static int execute_queues_cpsch(struct device_queue_manager *dqm, bool lock);
47static int destroy_queues_cpsch(struct device_queue_manager *dqm, bool lock);
48
bcea3081
BG		 49static int create_sdma_queue_nocpsch(struct device_queue_manager *dqm,
50 struct queue *q,
51 struct qcm_process_device *qpd);
52
53static void deallocate_sdma_queue(struct device_queue_manager *dqm,
54 unsigned int sdma_queue_id);
55
56static inline
57enum KFD_MQD_TYPE get_mqd_type_from_queue_type(enum kfd_queue_type type)
58{
59 if (type == KFD_QUEUE_TYPE_SDMA)
85d258f9
BG		 60 return KFD_MQD_TYPE_SDMA;
61 return KFD_MQD_TYPE_CP;
bcea3081 62}
64c7f8cf
BG		 63
64static inline unsigned int get_pipes_num(struct device_queue_manager *dqm)
65{
66 BUG_ON(!dqm || !dqm->dev);
67 return dqm->dev->shared_resources.compute_pipe_count;
68}
69
70static inline unsigned int get_first_pipe(struct device_queue_manager *dqm)
71{
72 BUG_ON(!dqm);
73 return dqm->dev->shared_resources.first_compute_pipe;
74}
75
76static inline unsigned int get_pipes_num_cpsch(void)
77{
78 return PIPE_PER_ME_CP_SCHEDULING;
79}
80
52a5fdce
AS		 81static inline unsigned int
82get_sh_mem_bases_nybble_64(struct kfd_process_device *pdd)
64c7f8cf 83{
64c7f8cf
BG		 84 uint32_t nybble;
85
64c7f8cf
BG		 86 nybble = (pdd->lds_base >> 60) & 0x0E;
87
88 return nybble;
64c7f8cf
BG		 89}
90
52a5fdce 91static inline unsigned int get_sh_mem_bases_32(struct kfd_process_device *pdd)
64c7f8cf 92{
64c7f8cf
BG		 93 unsigned int shared_base;
94
64c7f8cf
BG		 95 shared_base = (pdd->lds_base >> 16) & 0xFF;
96
97 return shared_base;
98}
99
100static uint32_t compute_sh_mem_bases_64bit(unsigned int top_address_nybble);
101static void init_process_memory(struct device_queue_manager *dqm,
102 struct qcm_process_device *qpd)
103{
52a5fdce 104 struct kfd_process_device *pdd;
64c7f8cf
BG		 105 unsigned int temp;
106
107 BUG_ON(!dqm || !qpd);
108
52a5fdce
AS		 109 pdd = qpd_to_pdd(qpd);
110
64c7f8cf
BG		 111 /* check if sh_mem_config register already configured */
112 if (qpd->sh_mem_config == 0) {
113 qpd->sh_mem_config =
114 ALIGNMENT_MODE(SH_MEM_ALIGNMENT_MODE_UNALIGNED) |
115 DEFAULT_MTYPE(MTYPE_NONCACHED) |
116 APE1_MTYPE(MTYPE_NONCACHED);
117 qpd->sh_mem_ape1_limit = 0;
118 qpd->sh_mem_ape1_base = 0;
119 }
120
121 if (qpd->pqm->process->is_32bit_user_mode) {
52a5fdce 122 temp = get_sh_mem_bases_32(pdd);
64c7f8cf
BG		 123 qpd->sh_mem_bases = SHARED_BASE(temp);
124 qpd->sh_mem_config |= PTR32;
125 } else {
52a5fdce 126 temp = get_sh_mem_bases_nybble_64(pdd);
64c7f8cf
BG		 127 qpd->sh_mem_bases = compute_sh_mem_bases_64bit(temp);
128 }
129
130 pr_debug("kfd: is32bit process: %d sh_mem_bases nybble: 0x%X and register 0x%X\n",
131 qpd->pqm->process->is_32bit_user_mode, temp, qpd->sh_mem_bases);
132}
133
134static void program_sh_mem_settings(struct device_queue_manager *dqm,
135 struct qcm_process_device *qpd)
136{
137 return kfd2kgd->program_sh_mem_settings(dqm->dev->kgd, qpd->vmid,
138 qpd->sh_mem_config,
139 qpd->sh_mem_ape1_base,
140 qpd->sh_mem_ape1_limit,
141 qpd->sh_mem_bases);
142}
143
144static int allocate_vmid(struct device_queue_manager *dqm,
145 struct qcm_process_device *qpd,
146 struct queue *q)
147{
148 int bit, allocated_vmid;
149
150 if (dqm->vmid_bitmap == 0)
151 return -ENOMEM;
152
153 bit = find_first_bit((unsigned long *)&dqm->vmid_bitmap, CIK_VMID_NUM);
154 clear_bit(bit, (unsigned long *)&dqm->vmid_bitmap);
155
156 /* Kaveri kfd vmid's starts from vmid 8 */
157 allocated_vmid = bit + KFD_VMID_START_OFFSET;
158 pr_debug("kfd: vmid allocation %d\n", allocated_vmid);
159 qpd->vmid = allocated_vmid;
160 q->properties.vmid = allocated_vmid;
161
162 set_pasid_vmid_mapping(dqm, q->process->pasid, q->properties.vmid);
163 program_sh_mem_settings(dqm, qpd);
164
165 return 0;
166}
167
168static void deallocate_vmid(struct device_queue_manager *dqm,
169 struct qcm_process_device *qpd,
170 struct queue *q)
171{
172 int bit = qpd->vmid - KFD_VMID_START_OFFSET;
173
174 set_bit(bit, (unsigned long *)&dqm->vmid_bitmap);
175 qpd->vmid = 0;
176 q->properties.vmid = 0;
177}
178
179static int create_queue_nocpsch(struct device_queue_manager *dqm,
180 struct queue *q,
181 struct qcm_process_device *qpd,
182 int *allocated_vmid)
183{
184 int retval;
185
186 BUG_ON(!dqm || !q || !qpd || !allocated_vmid);
187
188 pr_debug("kfd: In func %s\n", __func__);
189 print_queue(q);
190
191 mutex_lock(&dqm->lock);
192
193 if (list_empty(&qpd->queues_list)) {
194 retval = allocate_vmid(dqm, qpd, q);
195 if (retval != 0) {
196 mutex_unlock(&dqm->lock);
197 return retval;
198 }
199 }
200 *allocated_vmid = qpd->vmid;
201 q->properties.vmid = qpd->vmid;
202
bcea3081
BG		 203 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE)
204 retval = create_compute_queue_nocpsch(dqm, q, qpd);
205 if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
206 retval = create_sdma_queue_nocpsch(dqm, q, qpd);
64c7f8cf
BG		 207
208 if (retval != 0) {
209 if (list_empty(&qpd->queues_list)) {
210 deallocate_vmid(dqm, qpd, q);
211 *allocated_vmid = 0;
212 }
213 mutex_unlock(&dqm->lock);
214 return retval;
215 }
216
217 list_add(&q->list, &qpd->queues_list);
218 dqm->queue_count++;
bcea3081
BG		 219 if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
220 dqm->sdma_queue_count++;
64c7f8cf
BG		 221 mutex_unlock(&dqm->lock);
222 return 0;
223}
224
225static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q)
226{
227 bool set;
228 int pipe, bit;
229
230 set = false;
231
232 for (pipe = dqm->next_pipe_to_allocate; pipe < get_pipes_num(dqm);
233 pipe = (pipe + 1) % get_pipes_num(dqm)) {
234 if (dqm->allocated_queues[pipe] != 0) {
235 bit = find_first_bit(
236 (unsigned long *)&dqm->allocated_queues[pipe],
237 QUEUES_PER_PIPE);
238
239 clear_bit(bit,
240 (unsigned long *)&dqm->allocated_queues[pipe]);
241 q->pipe = pipe;
242 q->queue = bit;
243 set = true;
244 break;
245 }
246 }
247
248 if (set == false)
249 return -EBUSY;
250
251 pr_debug("kfd: DQM %s hqd slot - pipe (%d) queue(%d)\n",
252 __func__, q->pipe, q->queue);
253 /* horizontal hqd allocation */
254 dqm->next_pipe_to_allocate = (pipe + 1) % get_pipes_num(dqm);
255
256 return 0;
257}
258
259static inline void deallocate_hqd(struct device_queue_manager *dqm,
260 struct queue *q)
261{
262 set_bit(q->queue, (unsigned long *)&dqm->allocated_queues[q->pipe]);
263}
264
265static int create_compute_queue_nocpsch(struct device_queue_manager *dqm,
266 struct queue *q,
267 struct qcm_process_device *qpd)
268{
269 int retval;
270 struct mqd_manager *mqd;
271
272 BUG_ON(!dqm || !q || !qpd);
273
85d258f9 274 mqd = dqm->get_mqd_manager(dqm, KFD_MQD_TYPE_COMPUTE);
64c7f8cf
BG		 275 if (mqd == NULL)
276 return -ENOMEM;
277
278 retval = allocate_hqd(dqm, q);
279 if (retval != 0)
280 return retval;
281
282 retval = mqd->init_mqd(mqd, &q->mqd, &q->mqd_mem_obj,
283 &q->gart_mqd_addr, &q->properties);
284 if (retval != 0) {
285 deallocate_hqd(dqm, q);
286 return retval;
287 }
288
289 return 0;
290}
291
292static int destroy_queue_nocpsch(struct device_queue_manager *dqm,
293 struct qcm_process_device *qpd,
294 struct queue *q)
295{
296 int retval;
bcea3081 297 struct mqd_manager *mqd, *mqd_sdma;
64c7f8cf
BG		 298 BUG_ON(!dqm || !q || !q->mqd || !qpd);
299
300 retval = 0;
301
302 pr_debug("kfd: In Func %s\n", __func__);
303
304 mutex_lock(&dqm->lock);
85d258f9 305 mqd = dqm->get_mqd_manager(dqm, KFD_MQD_TYPE_COMPUTE);
64c7f8cf
BG		 306 if (mqd == NULL) {
307 retval = -ENOMEM;
308 goto out;
309 }
310
85d258f9 311 mqd_sdma = dqm->get_mqd_manager(dqm, KFD_MQD_TYPE_SDMA);
bcea3081
BG		 312 if (mqd_sdma == NULL) {
313 mutex_unlock(&dqm->lock);
314 return -ENOMEM;
315 }
316
64c7f8cf
BG		 317 retval = mqd->destroy_mqd(mqd, q->mqd,
318 KFD_PREEMPT_TYPE_WAVEFRONT,
319 QUEUE_PREEMPT_DEFAULT_TIMEOUT_MS,
320 q->pipe, q->queue);
321
322 if (retval != 0)
323 goto out;
324
bcea3081
BG		 325 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE)
326 deallocate_hqd(dqm, q);
327 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
328 dqm->sdma_queue_count--;
329 deallocate_sdma_queue(dqm, q->sdma_id);
330 }
64c7f8cf
BG		 331
332 mqd->uninit_mqd(mqd, q->mqd, q->mqd_mem_obj);
333
334 list_del(&q->list);
335 if (list_empty(&qpd->queues_list))
336 deallocate_vmid(dqm, qpd, q);
337 dqm->queue_count--;
338out:
339 mutex_unlock(&dqm->lock);
340 return retval;
341}
342
343static int update_queue(struct device_queue_manager *dqm, struct queue *q)
344{
345 int retval;
346 struct mqd_manager *mqd;
347
348 BUG_ON(!dqm || !q || !q->mqd);
349
350 mutex_lock(&dqm->lock);
bcea3081 351 mqd = dqm->get_mqd_manager(dqm, q->properties.type);
64c7f8cf
BG		 352 if (mqd == NULL) {
353 mutex_unlock(&dqm->lock);
354 return -ENOMEM;
355 }
356
357 retval = mqd->update_mqd(mqd, q->mqd, &q->properties);
358 if (q->properties.is_active == true)
359 dqm->queue_count++;
360 else
361 dqm->queue_count--;
362
363 if (sched_policy != KFD_SCHED_POLICY_NO_HWS)
364 retval = execute_queues_cpsch(dqm, false);
365
366 mutex_unlock(&dqm->lock);
367 return retval;
368}
369
370static struct mqd_manager *get_mqd_manager_nocpsch(
371 struct device_queue_manager *dqm, enum KFD_MQD_TYPE type)
372{
373 struct mqd_manager *mqd;
374
375 BUG_ON(!dqm || type >= KFD_MQD_TYPE_MAX);
376
377 pr_debug("kfd: In func %s mqd type %d\n", __func__, type);
378
379 mqd = dqm->mqds[type];
380 if (!mqd) {
381 mqd = mqd_manager_init(type, dqm->dev);
382 if (mqd == NULL)
383 pr_err("kfd: mqd manager is NULL");
384 dqm->mqds[type] = mqd;
385 }
386
387 return mqd;
388}
389
390static int register_process_nocpsch(struct device_queue_manager *dqm,
391 struct qcm_process_device *qpd)
392{
393 struct device_process_node *n;
394
395 BUG_ON(!dqm || !qpd);
396
397 pr_debug("kfd: In func %s\n", __func__);
398
399 n = kzalloc(sizeof(struct device_process_node), GFP_KERNEL);
400 if (!n)
401 return -ENOMEM;
402
403 n->qpd = qpd;
404
405 mutex_lock(&dqm->lock);
406 list_add(&n->list, &dqm->queues);
407
408 init_process_memory(dqm, qpd);
409 dqm->processes_count++;
410
411 mutex_unlock(&dqm->lock);
412
413 return 0;
414}
415
416static int unregister_process_nocpsch(struct device_queue_manager *dqm,
417 struct qcm_process_device *qpd)
418{
419 int retval;
420 struct device_process_node *cur, *next;
421
422 BUG_ON(!dqm || !qpd);
423
424 BUG_ON(!list_empty(&qpd->queues_list));
425
426 pr_debug("kfd: In func %s\n", __func__);
427
428 retval = 0;
429 mutex_lock(&dqm->lock);
430
431 list_for_each_entry_safe(cur, next, &dqm->queues, list) {
432 if (qpd == cur->qpd) {
433 list_del(&cur->list);
f5d896bb 434 kfree(cur);
64c7f8cf
BG		 435 dqm->processes_count--;
436 goto out;
437 }
438 }
439 /* qpd not found in dqm list */
440 retval = 1;
441out:
442 mutex_unlock(&dqm->lock);
443 return retval;
444}
445
446static int
447set_pasid_vmid_mapping(struct device_queue_manager *dqm, unsigned int pasid,
448 unsigned int vmid)
449{
450 uint32_t pasid_mapping;
451
452 pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid |
453 ATC_VMID_PASID_MAPPING_VALID;
454 return kfd2kgd->set_pasid_vmid_mapping(dqm->dev->kgd, pasid_mapping,
455 vmid);
456}
457
458static uint32_t compute_sh_mem_bases_64bit(unsigned int top_address_nybble)
459{
460 /* In 64-bit mode, we can only control the top 3 bits of the LDS,
461 * scratch and GPUVM apertures.
462 * The hardware fills in the remaining 59 bits according to the
463 * following pattern:
464 * LDS: X0000000'00000000 - X0000001'00000000 (4GB)
465 * Scratch: X0000001'00000000 - X0000002'00000000 (4GB)
466 * GPUVM: Y0010000'00000000 - Y0020000'00000000 (1TB)
467 *
468 * (where X/Y is the configurable nybble with the low-bit 0)
469 *
470 * LDS and scratch will have the same top nybble programmed in the
471 * top 3 bits of SH_MEM_BASES.PRIVATE_BASE.
472 * GPUVM can have a different top nybble programmed in the
473 * top 3 bits of SH_MEM_BASES.SHARED_BASE.
474 * We don't bother to support different top nybbles
475 * for LDS/Scratch and GPUVM.
476 */
477
478 BUG_ON((top_address_nybble & 1) || top_address_nybble > 0xE ||
479 top_address_nybble == 0);
480
481 return PRIVATE_BASE(top_address_nybble << 12) |
482 SHARED_BASE(top_address_nybble << 12);
483}
484
64c7f8cf
BG		 485static int init_pipelines(struct device_queue_manager *dqm,
486 unsigned int pipes_num, unsigned int first_pipe)
487{
488 void *hpdptr;
489 struct mqd_manager *mqd;
490 unsigned int i, err, inx;
491 uint64_t pipe_hpd_addr;
492
493 BUG_ON(!dqm || !dqm->dev);
494
495 pr_debug("kfd: In func %s\n", __func__);
496
497 /*
498 * Allocate memory for the HPDs. This is hardware-owned per-pipe data.
499 * The driver never accesses this memory after zeroing it.
500 * It doesn't even have to be saved/restored on suspend/resume
501 * because it contains no data when there are no active queues.
502 */
503
a86aa3ca
OG		 504 err = kfd_gtt_sa_allocate(dqm->dev, CIK_HPD_EOP_BYTES * pipes_num,
505 &dqm->pipeline_mem);
64c7f8cf
BG		 506
507 if (err) {
508 pr_err("kfd: error allocate vidmem num pipes: %d\n",
509 pipes_num);
510 return -ENOMEM;
511 }
512
513 hpdptr = dqm->pipeline_mem->cpu_ptr;
514 dqm->pipelines_addr = dqm->pipeline_mem->gpu_addr;
515
516 memset(hpdptr, 0, CIK_HPD_EOP_BYTES * pipes_num);
517
85d258f9 518 mqd = dqm->get_mqd_manager(dqm, KFD_MQD_TYPE_COMPUTE);
64c7f8cf 519 if (mqd == NULL) {
a86aa3ca 520 kfd_gtt_sa_free(dqm->dev, dqm->pipeline_mem);
64c7f8cf
BG		 521 return -ENOMEM;
522 }
523
524 for (i = 0; i < pipes_num; i++) {
525 inx = i + first_pipe;
526 pipe_hpd_addr = dqm->pipelines_addr + i * CIK_HPD_EOP_BYTES;
527 pr_debug("kfd: pipeline address %llX\n", pipe_hpd_addr);
528 /* = log2(bytes/4)-1 */
529 kfd2kgd->init_pipeline(dqm->dev->kgd, i,
530 CIK_HPD_EOP_BYTES_LOG2 - 3, pipe_hpd_addr);
531 }
532
533 return 0;
534}
535
64c7f8cf
BG		 536static int init_scheduler(struct device_queue_manager *dqm)
537{
538 int retval;
539
540 BUG_ON(!dqm);
541
542 pr_debug("kfd: In %s\n", __func__);
543
544 retval = init_pipelines(dqm, get_pipes_num(dqm), KFD_DQM_FIRST_PIPE);
64c7f8cf
BG		 545
546 return retval;
547}
548
549static int initialize_nocpsch(struct device_queue_manager *dqm)
550{
551 int i;
552
553 BUG_ON(!dqm);
554
555 pr_debug("kfd: In func %s num of pipes: %d\n",
556 __func__, get_pipes_num(dqm));
557
558 mutex_init(&dqm->lock);
559 INIT_LIST_HEAD(&dqm->queues);
560 dqm->queue_count = dqm->next_pipe_to_allocate = 0;
bcea3081 561 dqm->sdma_queue_count = 0;
64c7f8cf
BG		 562 dqm->allocated_queues = kcalloc(get_pipes_num(dqm),
563 sizeof(unsigned int), GFP_KERNEL);
564 if (!dqm->allocated_queues) {
565 mutex_destroy(&dqm->lock);
566 return -ENOMEM;
567 }
568
569 for (i = 0; i < get_pipes_num(dqm); i++)
570 dqm->allocated_queues[i] = (1 << QUEUES_PER_PIPE) - 1;
571
572 dqm->vmid_bitmap = (1 << VMID_PER_DEVICE) - 1;
bcea3081 573 dqm->sdma_bitmap = (1 << CIK_SDMA_QUEUES) - 1;
64c7f8cf
BG		 574
575 init_scheduler(dqm);
576 return 0;
577}
578
579static void uninitialize_nocpsch(struct device_queue_manager *dqm)
580{
6f9d54fd
OG		 581 int i;
582
64c7f8cf
BG		 583 BUG_ON(!dqm);
584
585 BUG_ON(dqm->queue_count > 0 || dqm->processes_count > 0);
586
587 kfree(dqm->allocated_queues);
6f9d54fd
OG		 588 for (i = 0 ; i < KFD_MQD_TYPE_MAX ; i++)
589 kfree(dqm->mqds[i]);
64c7f8cf 590 mutex_destroy(&dqm->lock);
a86aa3ca 591 kfd_gtt_sa_free(dqm->dev, dqm->pipeline_mem);
64c7f8cf
BG		 592}
593
594static int start_nocpsch(struct device_queue_manager *dqm)
595{
596 return 0;
597}
598
599static int stop_nocpsch(struct device_queue_manager *dqm)
600{
601 return 0;
602}
603
bcea3081
BG		 604static int allocate_sdma_queue(struct device_queue_manager *dqm,
605 unsigned int *sdma_queue_id)
606{
607 int bit;
608
609 if (dqm->sdma_bitmap == 0)
610 return -ENOMEM;
611
612 bit = find_first_bit((unsigned long *)&dqm->sdma_bitmap,
613 CIK_SDMA_QUEUES);
614
615 clear_bit(bit, (unsigned long *)&dqm->sdma_bitmap);
616 *sdma_queue_id = bit;
617
618 return 0;
619}
620
621static void deallocate_sdma_queue(struct device_queue_manager *dqm,
622 unsigned int sdma_queue_id)
623{
624 if (sdma_queue_id < 0 || sdma_queue_id >= CIK_SDMA_QUEUES)
625 return;
626 set_bit(sdma_queue_id, (unsigned long *)&dqm->sdma_bitmap);
627}
628
629static void init_sdma_vm(struct device_queue_manager *dqm, struct queue *q,
630 struct qcm_process_device *qpd)
631{
632 uint32_t value = SDMA_ATC;
633
634 if (q->process->is_32bit_user_mode)
635 value |= SDMA_VA_PTR32 | get_sh_mem_bases_32(qpd_to_pdd(qpd));
636 else
637 value |= SDMA_VA_SHARED_BASE(get_sh_mem_bases_nybble_64(
638 qpd_to_pdd(qpd)));
639 q->properties.sdma_vm_addr = value;
640}
641
642static int create_sdma_queue_nocpsch(struct device_queue_manager *dqm,
643 struct queue *q,
644 struct qcm_process_device *qpd)
645{
646 struct mqd_manager *mqd;
647 int retval;
648
85d258f9 649 mqd = dqm->get_mqd_manager(dqm, KFD_MQD_TYPE_SDMA);
bcea3081
BG		 650 if (!mqd)
651 return -ENOMEM;
652
653 retval = allocate_sdma_queue(dqm, &q->sdma_id);
654 if (retval != 0)
655 return retval;
656
657 q->properties.sdma_queue_id = q->sdma_id % CIK_SDMA_QUEUES_PER_ENGINE;
658 q->properties.sdma_engine_id = q->sdma_id / CIK_SDMA_ENGINE_NUM;
659
660 pr_debug("kfd: sdma id is: %d\n", q->sdma_id);
661 pr_debug(" sdma queue id: %d\n", q->properties.sdma_queue_id);
662 pr_debug(" sdma engine id: %d\n", q->properties.sdma_engine_id);
663
664 retval = mqd->init_mqd(mqd, &q->mqd, &q->mqd_mem_obj,
665 &q->gart_mqd_addr, &q->properties);
666 if (retval != 0) {
667 deallocate_sdma_queue(dqm, q->sdma_id);
668 return retval;
669 }
670
671 init_sdma_vm(dqm, q, qpd);
672 return 0;
673}
674
64c7f8cf
BG		 675/*
676 * Device Queue Manager implementation for cp scheduler
677 */
678
679static int set_sched_resources(struct device_queue_manager *dqm)
680{
681 struct scheduling_resources res;
682 unsigned int queue_num, queue_mask;
683
684 BUG_ON(!dqm);
685
686 pr_debug("kfd: In func %s\n", __func__);
687
688 queue_num = get_pipes_num_cpsch() * QUEUES_PER_PIPE;
689 queue_mask = (1 << queue_num) - 1;
690 res.vmid_mask = (1 << VMID_PER_DEVICE) - 1;
691 res.vmid_mask <<= KFD_VMID_START_OFFSET;
692 res.queue_mask = queue_mask << (get_first_pipe(dqm) * QUEUES_PER_PIPE);
693 res.gws_mask = res.oac_mask = res.gds_heap_base =
694 res.gds_heap_size = 0;
695
696 pr_debug("kfd: scheduling resources:\n"
697 " vmid mask: 0x%8X\n"
698 " queue mask: 0x%8llX\n",
699 res.vmid_mask, res.queue_mask);
700
701 return pm_send_set_resources(&dqm->packets, &res);
702}
703
704static int initialize_cpsch(struct device_queue_manager *dqm)
705{
706 int retval;
707
708 BUG_ON(!dqm);
709
710 pr_debug("kfd: In func %s num of pipes: %d\n",
711 __func__, get_pipes_num_cpsch());
712
713 mutex_init(&dqm->lock);
714 INIT_LIST_HEAD(&dqm->queues);
715 dqm->queue_count = dqm->processes_count = 0;
bcea3081 716 dqm->sdma_queue_count = 0;
64c7f8cf
BG		 717 dqm->active_runlist = false;
718 retval = init_pipelines(dqm, get_pipes_num(dqm), 0);
719 if (retval != 0)
720 goto fail_init_pipelines;
721
722 return 0;
723
724fail_init_pipelines:
725 mutex_destroy(&dqm->lock);
726 return retval;
727}
728
729static int start_cpsch(struct device_queue_manager *dqm)
730{
731 struct device_process_node *node;
732 int retval;
733
734 BUG_ON(!dqm);
735
736 retval = 0;
737
738 retval = pm_init(&dqm->packets, dqm);
739 if (retval != 0)
740 goto fail_packet_manager_init;
741
742 retval = set_sched_resources(dqm);
743 if (retval != 0)
744 goto fail_set_sched_resources;
745
746 pr_debug("kfd: allocating fence memory\n");
747
748 /* allocate fence memory on the gart */
a86aa3ca
OG		 749 retval = kfd_gtt_sa_allocate(dqm->dev, sizeof(*dqm->fence_addr),
750 &dqm->fence_mem);
64c7f8cf
BG		 751
752 if (retval != 0)
753 goto fail_allocate_vidmem;
754
755 dqm->fence_addr = dqm->fence_mem->cpu_ptr;
756 dqm->fence_gpu_addr = dqm->fence_mem->gpu_addr;
64c7f8cf
BG		 757 list_for_each_entry(node, &dqm->queues, list)
758 if (node->qpd->pqm->process && dqm->dev)
759 kfd_bind_process_to_device(dqm->dev,
760 node->qpd->pqm->process);
761
762 execute_queues_cpsch(dqm, true);
763
764 return 0;
765fail_allocate_vidmem:
766fail_set_sched_resources:
767 pm_uninit(&dqm->packets);
768fail_packet_manager_init:
769 return retval;
770}
771
772static int stop_cpsch(struct device_queue_manager *dqm)
773{
774 struct device_process_node *node;
775 struct kfd_process_device *pdd;
776
777 BUG_ON(!dqm);
778
779 destroy_queues_cpsch(dqm, true);
780
781 list_for_each_entry(node, &dqm->queues, list) {
52a5fdce 782 pdd = qpd_to_pdd(node->qpd);
64c7f8cf
BG		 783 pdd->bound = false;
784 }
a86aa3ca 785 kfd_gtt_sa_free(dqm->dev, dqm->fence_mem);
64c7f8cf
BG		 786 pm_uninit(&dqm->packets);
787
788 return 0;
789}
790
791static int create_kernel_queue_cpsch(struct device_queue_manager *dqm,
792 struct kernel_queue *kq,
793 struct qcm_process_device *qpd)
794{
795 BUG_ON(!dqm || !kq || !qpd);
796
797 pr_debug("kfd: In func %s\n", __func__);
798
799 mutex_lock(&dqm->lock);
800 list_add(&kq->list, &qpd->priv_queue_list);
801 dqm->queue_count++;
802 qpd->is_debug = true;
803 execute_queues_cpsch(dqm, false);
804 mutex_unlock(&dqm->lock);
805
806 return 0;
807}
808
809static void destroy_kernel_queue_cpsch(struct device_queue_manager *dqm,
810 struct kernel_queue *kq,
811 struct qcm_process_device *qpd)
812{
813 BUG_ON(!dqm || !kq);
814
815 pr_debug("kfd: In %s\n", __func__);
816
817 mutex_lock(&dqm->lock);
818 destroy_queues_cpsch(dqm, false);
819 list_del(&kq->list);
820 dqm->queue_count--;
821 qpd->is_debug = false;
822 execute_queues_cpsch(dqm, false);
823 mutex_unlock(&dqm->lock);
824}
825
bcea3081
BG		 826static void select_sdma_engine_id(struct queue *q)
827{
828 static int sdma_id;
829
830 q->sdma_id = sdma_id;
831 sdma_id = (sdma_id + 1) % 2;
832}
833
64c7f8cf
BG		 834static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q,
835 struct qcm_process_device *qpd, int *allocate_vmid)
836{
837 int retval;
838 struct mqd_manager *mqd;
839
840 BUG_ON(!dqm || !q || !qpd);
841
842 retval = 0;
843
844 if (allocate_vmid)
845 *allocate_vmid = 0;
846
847 mutex_lock(&dqm->lock);
848
bcea3081
BG		 849 if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
850 select_sdma_engine_id(q);
851
852 mqd = dqm->get_mqd_manager(dqm,
853 get_mqd_type_from_queue_type(q->properties.type));
854
64c7f8cf
BG		 855 if (mqd == NULL) {
856 mutex_unlock(&dqm->lock);
857 return -ENOMEM;
858 }
859
860 retval = mqd->init_mqd(mqd, &q->mqd, &q->mqd_mem_obj,
861 &q->gart_mqd_addr, &q->properties);
862 if (retval != 0)
863 goto out;
864
865 list_add(&q->list, &qpd->queues_list);
866 if (q->properties.is_active) {
867 dqm->queue_count++;
868 retval = execute_queues_cpsch(dqm, false);
869 }
870
bcea3081
BG		 871 if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
872 dqm->sdma_queue_count++;
873
64c7f8cf
BG		 874out:
875 mutex_unlock(&dqm->lock);
876 return retval;
877}
878
d80d19bd
OG		 879static int fence_wait_timeout(unsigned int *fence_addr,
880 unsigned int fence_value,
881 unsigned long timeout)
64c7f8cf
BG		 882{
883 BUG_ON(!fence_addr);
884 timeout += jiffies;
885
886 while (*fence_addr != fence_value) {
887 if (time_after(jiffies, timeout)) {
888 pr_err("kfd: qcm fence wait loop timeout expired\n");
889 return -ETIME;
890 }
891 cpu_relax();
892 }
893
894 return 0;
895}
896
bcea3081
BG		 897static int destroy_sdma_queues(struct device_queue_manager *dqm,
898 unsigned int sdma_engine)
899{
900 return pm_send_unmap_queue(&dqm->packets, KFD_QUEUE_TYPE_SDMA,
901 KFD_PREEMPT_TYPE_FILTER_ALL_QUEUES, 0, false,
902 sdma_engine);
903}
904
64c7f8cf
BG		 905static int destroy_queues_cpsch(struct device_queue_manager *dqm, bool lock)
906{
907 int retval;
908
909 BUG_ON(!dqm);
910
911 retval = 0;
912
913 if (lock)
914 mutex_lock(&dqm->lock);
915 if (dqm->active_runlist == false)
916 goto out;
bcea3081
BG		 917
918 pr_debug("kfd: Before destroying queues, sdma queue count is : %u\n",
919 dqm->sdma_queue_count);
920
921 if (dqm->sdma_queue_count > 0) {
922 destroy_sdma_queues(dqm, 0);
923 destroy_sdma_queues(dqm, 1);
924 }
925
64c7f8cf
BG		 926 retval = pm_send_unmap_queue(&dqm->packets, KFD_QUEUE_TYPE_COMPUTE,
927 KFD_PREEMPT_TYPE_FILTER_ALL_QUEUES, 0, false, 0);
928 if (retval != 0)
929 goto out;
930
931 *dqm->fence_addr = KFD_FENCE_INIT;
932 pm_send_query_status(&dqm->packets, dqm->fence_gpu_addr,
933 KFD_FENCE_COMPLETED);
934 /* should be timed out */
935 fence_wait_timeout(dqm->fence_addr, KFD_FENCE_COMPLETED,
936 QUEUE_PREEMPT_DEFAULT_TIMEOUT_MS);
937 pm_release_ib(&dqm->packets);
938 dqm->active_runlist = false;
939
940out:
941 if (lock)
942 mutex_unlock(&dqm->lock);
943 return retval;
944}
945
946static int execute_queues_cpsch(struct device_queue_manager *dqm, bool lock)
947{
948 int retval;
949
950 BUG_ON(!dqm);
951
952 if (lock)
953 mutex_lock(&dqm->lock);
954
955 retval = destroy_queues_cpsch(dqm, false);
956 if (retval != 0) {
957 pr_err("kfd: the cp might be in an unrecoverable state due to an unsuccessful queues preemption");
958 goto out;
959 }
960
961 if (dqm->queue_count <= 0 || dqm->processes_count <= 0) {
962 retval = 0;
963 goto out;
964 }
965
966 if (dqm->active_runlist) {
967 retval = 0;
968 goto out;
969 }
970
971 retval = pm_send_runlist(&dqm->packets, &dqm->queues);
972 if (retval != 0) {
973 pr_err("kfd: failed to execute runlist");
974 goto out;
975 }
976 dqm->active_runlist = true;
977
978out:
979 if (lock)
980 mutex_unlock(&dqm->lock);
981 return retval;
982}
983
984static int destroy_queue_cpsch(struct device_queue_manager *dqm,
985 struct qcm_process_device *qpd,
986 struct queue *q)
987{
988 int retval;
989 struct mqd_manager *mqd;
990
991 BUG_ON(!dqm || !qpd || !q);
992
993 retval = 0;
994
995 /* remove queue from list to prevent rescheduling after preemption */
996 mutex_lock(&dqm->lock);
bcea3081
BG		 997 mqd = dqm->get_mqd_manager(dqm,
998 get_mqd_type_from_queue_type(q->properties.type));
64c7f8cf
BG		 999 if (!mqd) {
1000 retval = -ENOMEM;
1001 goto failed;
1002 }
1003
bcea3081
BG		 1004 if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
1005 dqm->sdma_queue_count--;
1006
64c7f8cf
BG		 1007 list_del(&q->list);
1008 dqm->queue_count--;
1009
1010 execute_queues_cpsch(dqm, false);
1011
1012 mqd->uninit_mqd(mqd, q->mqd, q->mqd_mem_obj);
1013
1014 mutex_unlock(&dqm->lock);
1015
1016 return 0;
1017
1018failed:
1019 mutex_unlock(&dqm->lock);
1020 return retval;
1021}
1022
1023/*
1024 * Low bits must be 0000/FFFF as required by HW, high bits must be 0 to
1025 * stay in user mode.
1026 */
1027#define APE1_FIXED_BITS_MASK 0xFFFF80000000FFFFULL
1028/* APE1 limit is inclusive and 64K aligned. */
1029#define APE1_LIMIT_ALIGNMENT 0xFFFF
1030
1031static bool set_cache_memory_policy(struct device_queue_manager *dqm,
1032 struct qcm_process_device *qpd,
1033 enum cache_policy default_policy,
1034 enum cache_policy alternate_policy,
1035 void __user *alternate_aperture_base,
1036 uint64_t alternate_aperture_size)
1037{
1038 uint32_t default_mtype;
1039 uint32_t ape1_mtype;
1040
1041 pr_debug("kfd: In func %s\n", __func__);
1042
1043 mutex_lock(&dqm->lock);
1044
1045 if (alternate_aperture_size == 0) {
1046 /* base > limit disables APE1 */
1047 qpd->sh_mem_ape1_base = 1;
1048 qpd->sh_mem_ape1_limit = 0;
1049 } else {
1050 /*
1051 * In FSA64, APE1_Base[63:0] = { 16{SH_MEM_APE1_BASE[31]},
1052 * SH_MEM_APE1_BASE[31:0], 0x0000 }
1053 * APE1_Limit[63:0] = { 16{SH_MEM_APE1_LIMIT[31]},
1054 * SH_MEM_APE1_LIMIT[31:0], 0xFFFF }
1055 * Verify that the base and size parameters can be
1056 * represented in this format and convert them.
1057 * Additionally restrict APE1 to user-mode addresses.
1058 */
1059
1060 uint64_t base = (uintptr_t)alternate_aperture_base;
1061 uint64_t limit = base + alternate_aperture_size - 1;
1062
1063 if (limit <= base)
1064 goto out;
1065
1066 if ((base & APE1_FIXED_BITS_MASK) != 0)
1067 goto out;
1068
1069 if ((limit & APE1_FIXED_BITS_MASK) != APE1_LIMIT_ALIGNMENT)
1070 goto out;
1071
1072 qpd->sh_mem_ape1_base = base >> 16;
1073 qpd->sh_mem_ape1_limit = limit >> 16;
1074 }
1075
1076 default_mtype = (default_policy == cache_policy_coherent) ?
1077 MTYPE_NONCACHED :
1078 MTYPE_CACHED;
1079
1080 ape1_mtype = (alternate_policy == cache_policy_coherent) ?
1081 MTYPE_NONCACHED :
1082 MTYPE_CACHED;
1083
1084 qpd->sh_mem_config = (qpd->sh_mem_config & PTR32)
1085 | ALIGNMENT_MODE(SH_MEM_ALIGNMENT_MODE_UNALIGNED)
1086 | DEFAULT_MTYPE(default_mtype)
1087 | APE1_MTYPE(ape1_mtype);
1088
1089 if ((sched_policy == KFD_SCHED_POLICY_NO_HWS) && (qpd->vmid != 0))
1090 program_sh_mem_settings(dqm, qpd);
1091
1092 pr_debug("kfd: sh_mem_config: 0x%x, ape1_base: 0x%x, ape1_limit: 0x%x\n",
1093 qpd->sh_mem_config, qpd->sh_mem_ape1_base,
1094 qpd->sh_mem_ape1_limit);
1095
1096 mutex_unlock(&dqm->lock);
1097 return true;
1098
1099out:
1100 mutex_unlock(&dqm->lock);
1101 return false;
1102}
1103
1104struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev)
1105{
1106 struct device_queue_manager *dqm;
1107
1108 BUG_ON(!dev);
1109
1110 dqm = kzalloc(sizeof(struct device_queue_manager), GFP_KERNEL);
1111 if (!dqm)
1112 return NULL;
1113
1114 dqm->dev = dev;
1115 switch (sched_policy) {
1116 case KFD_SCHED_POLICY_HWS:
1117 case KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION:
1118 /* initialize dqm for cp scheduling */
1119 dqm->create_queue = create_queue_cpsch;
1120 dqm->initialize = initialize_cpsch;
1121 dqm->start = start_cpsch;
1122 dqm->stop = stop_cpsch;
1123 dqm->destroy_queue = destroy_queue_cpsch;
1124 dqm->update_queue = update_queue;
1125 dqm->get_mqd_manager = get_mqd_manager_nocpsch;
1126 dqm->register_process = register_process_nocpsch;
1127 dqm->unregister_process = unregister_process_nocpsch;
1128 dqm->uninitialize = uninitialize_nocpsch;
1129 dqm->create_kernel_queue = create_kernel_queue_cpsch;
1130 dqm->destroy_kernel_queue = destroy_kernel_queue_cpsch;
1131 dqm->set_cache_memory_policy = set_cache_memory_policy;
1132 break;
1133 case KFD_SCHED_POLICY_NO_HWS:
1134 /* initialize dqm for no cp scheduling */
1135 dqm->start = start_nocpsch;
1136 dqm->stop = stop_nocpsch;
1137 dqm->create_queue = create_queue_nocpsch;
1138 dqm->destroy_queue = destroy_queue_nocpsch;
1139 dqm->update_queue = update_queue;
1140 dqm->get_mqd_manager = get_mqd_manager_nocpsch;
1141 dqm->register_process = register_process_nocpsch;
1142 dqm->unregister_process = unregister_process_nocpsch;
1143 dqm->initialize = initialize_nocpsch;
1144 dqm->uninitialize = uninitialize_nocpsch;
1145 dqm->set_cache_memory_policy = set_cache_memory_policy;
1146 break;
1147 default:
1148 BUG();
1149 break;
1150 }
1151
1152 if (dqm->initialize(dqm) != 0) {
1153 kfree(dqm);
1154 return NULL;
1155 }
1156
1157 return dqm;
1158}
1159
1160void device_queue_manager_uninit(struct device_queue_manager *dqm)
1161{
1162 BUG_ON(!dqm);
1163
1164 dqm->uninitialize(dqm);
1165 kfree(dqm);
1166}
1167
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