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drm/amd/display: Simplify dm_late_init()
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / display / amdgpu_dm / amdgpu_dm.c
CommitLineData
4562236b
HW		 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "dm_services_types.h"
27#include "dc.h"
1dc90497 28#include "dc/inc/core_types.h"
4562236b
HW		 29
30#include "vid.h"
31#include "amdgpu.h"
a49dcb88 32#include "amdgpu_display.h"
4562236b
HW		 33#include "atom.h"
34#include "amdgpu_dm.h"
e7b07cee 35#include "amdgpu_pm.h"
4562236b
HW		 36
37#include "amd_shared.h"
38#include "amdgpu_dm_irq.h"
39#include "dm_helpers.h"
e7b07cee
HW		 40#include "dm_services_types.h"
41#include "amdgpu_dm_mst_types.h"
4562236b
HW		 42
43#include "ivsrcid/ivsrcid_vislands30.h"
44
45#include <linux/module.h>
46#include <linux/moduleparam.h>
47#include <linux/version.h>
e7b07cee 48#include <linux/types.h>
4562236b 49
e7b07cee 50#include <drm/drmP.h>
4562236b
HW		 51#include <drm/drm_atomic.h>
52#include <drm/drm_atomic_helper.h>
53#include <drm/drm_dp_mst_helper.h>
e7b07cee
HW		 54#include <drm/drm_fb_helper.h>
55#include <drm/drm_edid.h>
4562236b
HW		 56
57#include "modules/inc/mod_freesync.h"
58
ff5ef992
AD		 59#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
60#include "ivsrcid/irqsrcs_dcn_1_0.h"
61
62#include "raven1/DCN/dcn_1_0_offset.h"
63#include "raven1/DCN/dcn_1_0_sh_mask.h"
64#include "vega10/soc15ip.h"
65
66#include "soc15_common.h"
67#endif
68
e7b07cee
HW		 69#include "modules/inc/mod_freesync.h"
70
71#include "i2caux_interface.h"
72
7578ecda
AD		 73/* basic init/fini API */
74static int amdgpu_dm_init(struct amdgpu_device *adev);
75static void amdgpu_dm_fini(struct amdgpu_device *adev);
76
77/* initializes drm_device display related structures, based on the information
78 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
79 * drm_encoder, drm_mode_config
80 *
81 * Returns 0 on success
82 */
83static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
84/* removes and deallocates the drm structures, created by the above function */
85static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
86
87static void
88amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector);
89
90static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
91 struct amdgpu_plane *aplane,
92 unsigned long possible_crtcs);
93static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
94 struct drm_plane *plane,
95 uint32_t link_index);
96static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
97 struct amdgpu_dm_connector *amdgpu_dm_connector,
98 uint32_t link_index,
99 struct amdgpu_encoder *amdgpu_encoder);
100static int amdgpu_dm_encoder_init(struct drm_device *dev,
101 struct amdgpu_encoder *aencoder,
102 uint32_t link_index);
103
104static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
105
106static int amdgpu_dm_atomic_commit(struct drm_device *dev,
107 struct drm_atomic_state *state,
108 bool nonblock);
109
110static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
111
112static int amdgpu_dm_atomic_check(struct drm_device *dev,
113 struct drm_atomic_state *state);
114
115
116
e7b07cee 117
e04a6123 118static const enum drm_plane_type dm_plane_type_default[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 119 DRM_PLANE_TYPE_PRIMARY,
120 DRM_PLANE_TYPE_PRIMARY,
121 DRM_PLANE_TYPE_PRIMARY,
122 DRM_PLANE_TYPE_PRIMARY,
123 DRM_PLANE_TYPE_PRIMARY,
124 DRM_PLANE_TYPE_PRIMARY,
125};
126
e04a6123 127static const enum drm_plane_type dm_plane_type_carizzo[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 128 DRM_PLANE_TYPE_PRIMARY,
129 DRM_PLANE_TYPE_PRIMARY,
130 DRM_PLANE_TYPE_PRIMARY,
131 DRM_PLANE_TYPE_OVERLAY,/* YUV Capable Underlay */
132};
133
e04a6123 134static const enum drm_plane_type dm_plane_type_stoney[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 135 DRM_PLANE_TYPE_PRIMARY,
136 DRM_PLANE_TYPE_PRIMARY,
137 DRM_PLANE_TYPE_OVERLAY, /* YUV Capable Underlay */
138};
139
4562236b
HW		 140/*
141 * dm_vblank_get_counter
142 *
143 * @brief
144 * Get counter for number of vertical blanks
145 *
146 * @param
147 * struct amdgpu_device *adev - [in] desired amdgpu device
148 * int disp_idx - [in] which CRTC to get the counter from
149 *
150 * @return
151 * Counter for vertical blanks
152 */
153static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
154{
155 if (crtc >= adev->mode_info.num_crtc)
156 return 0;
157 else {
158 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
da5c47f6
AG		 159 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
160 acrtc->base.state);
4562236b 161
da5c47f6
AG		 162
163 if (acrtc_state->stream == NULL) {
0971c40e
HW		 164 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
165 crtc);
4562236b
HW		 166 return 0;
167 }
168
da5c47f6 169 return dc_stream_get_vblank_counter(acrtc_state->stream);
4562236b
HW		 170 }
171}
172
173static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
3ee6b26b 174 u32 *vbl, u32 *position)
4562236b 175{
81c50963
ST		 176 uint32_t v_blank_start, v_blank_end, h_position, v_position;
177
4562236b
HW		 178 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
179 return -EINVAL;
180 else {
181 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
da5c47f6
AG		 182 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
183 acrtc->base.state);
4562236b 184
da5c47f6 185 if (acrtc_state->stream == NULL) {
0971c40e
HW		 186 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
187 crtc);
4562236b
HW		 188 return 0;
189 }
190
81c50963
ST		 191 /*
192 * TODO rework base driver to use values directly.
193 * for now parse it back into reg-format
194 */
da5c47f6 195 dc_stream_get_scanoutpos(acrtc_state->stream,
81c50963
ST		 196 &v_blank_start,
197 &v_blank_end,
198 &h_position,
199 &v_position);
200
e806208d
AG		 201 *position = v_position | (h_position << 16);
202 *vbl = v_blank_start | (v_blank_end << 16);
4562236b
HW		 203 }
204
205 return 0;
206}
207
208static bool dm_is_idle(void *handle)
209{
210 /* XXX todo */
211 return true;
212}
213
214static int dm_wait_for_idle(void *handle)
215{
216 /* XXX todo */
217 return 0;
218}
219
220static bool dm_check_soft_reset(void *handle)
221{
222 return false;
223}
224
225static int dm_soft_reset(void *handle)
226{
227 /* XXX todo */
228 return 0;
229}
230
3ee6b26b
AD		 231static struct amdgpu_crtc *
232get_crtc_by_otg_inst(struct amdgpu_device *adev,
233 int otg_inst)
4562236b
HW		 234{
235 struct drm_device *dev = adev->ddev;
236 struct drm_crtc *crtc;
237 struct amdgpu_crtc *amdgpu_crtc;
238
239 /*
240 * following if is check inherited from both functions where this one is
241 * used now. Need to be checked why it could happen.
242 */
243 if (otg_inst == -1) {
244 WARN_ON(1);
245 return adev->mode_info.crtcs[0];
246 }
247
248 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
249 amdgpu_crtc = to_amdgpu_crtc(crtc);
250
251 if (amdgpu_crtc->otg_inst == otg_inst)
252 return amdgpu_crtc;
253 }
254
255 return NULL;
256}
257
258static void dm_pflip_high_irq(void *interrupt_params)
259{
4562236b
HW		 260 struct amdgpu_crtc *amdgpu_crtc;
261 struct common_irq_params *irq_params = interrupt_params;
262 struct amdgpu_device *adev = irq_params->adev;
263 unsigned long flags;
264
265 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
266
267 /* IRQ could occur when in initial stage */
268 /*TODO work and BO cleanup */
269 if (amdgpu_crtc == NULL) {
270 DRM_DEBUG_DRIVER("CRTC is null, returning.\n");
271 return;
272 }
273
274 spin_lock_irqsave(&adev->ddev->event_lock, flags);
4562236b
HW		 275
276 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
277 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
278 amdgpu_crtc->pflip_status,
279 AMDGPU_FLIP_SUBMITTED,
280 amdgpu_crtc->crtc_id,
281 amdgpu_crtc);
282 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
283 return;
284 }
285
4562236b
HW		 286
287 /* wakeup usersapce */
1159898a 288 if (amdgpu_crtc->event) {
753c66c9
MK		 289 /* Update to correct count/ts if racing with vblank irq */
290 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
291
54f5499a 292 drm_crtc_send_vblank_event(&amdgpu_crtc->base, amdgpu_crtc->event);
1159898a 293
54f5499a
AG		 294 /* page flip completed. clean up */
295 amdgpu_crtc->event = NULL;
1159898a 296
54f5499a
AG		 297 } else
298 WARN_ON(1);
4562236b 299
54f5499a 300 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
4562236b
HW		 301 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
302
54f5499a
AG		 303 DRM_DEBUG_DRIVER("%s - crtc :%d[%p], pflip_stat:AMDGPU_FLIP_NONE\n",
304 __func__, amdgpu_crtc->crtc_id, amdgpu_crtc);
4562236b
HW		 305
306 drm_crtc_vblank_put(&amdgpu_crtc->base);
4562236b
HW		 307}
308
309static void dm_crtc_high_irq(void *interrupt_params)
310{
311 struct common_irq_params *irq_params = interrupt_params;
312 struct amdgpu_device *adev = irq_params->adev;
313 uint8_t crtc_index = 0;
314 struct amdgpu_crtc *acrtc;
315
b57de80a 316 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
4562236b
HW		 317
318 if (acrtc)
319 crtc_index = acrtc->crtc_id;
320
321 drm_handle_vblank(adev->ddev, crtc_index);
322}
323
324static int dm_set_clockgating_state(void *handle,
325 enum amd_clockgating_state state)
326{
327 return 0;
328}
329
330static int dm_set_powergating_state(void *handle,
331 enum amd_powergating_state state)
332{
333 return 0;
334}
335
336/* Prototypes of private functions */
337static int dm_early_init(void* handle);
338
339static void hotplug_notify_work_func(struct work_struct *work)
340{
341 struct amdgpu_display_manager *dm = container_of(work, struct amdgpu_display_manager, mst_hotplug_work);
342 struct drm_device *dev = dm->ddev;
343
344 drm_kms_helper_hotplug_event(dev);
345}
346
a32e24b4
RL		 347#ifdef ENABLE_FBC
348#include "dal_asic_id.h"
349/* Allocate memory for FBC compressed data */
350/* TODO: Dynamic allocation */
351#define AMDGPU_FBC_SIZE (3840 * 2160 * 4)
352
7578ecda 353static void amdgpu_dm_initialize_fbc(struct amdgpu_device *adev)
a32e24b4
RL		 354{
355 int r;
356 struct dm_comressor_info *compressor = &adev->dm.compressor;
357
358 if (!compressor->bo_ptr) {
359 r = amdgpu_bo_create_kernel(adev, AMDGPU_FBC_SIZE, PAGE_SIZE,
360 AMDGPU_GEM_DOMAIN_VRAM, &compressor->bo_ptr,
361 &compressor->gpu_addr, &compressor->cpu_addr);
362
363 if (r)
364 DRM_ERROR("DM: Failed to initialize fbc\n");
365 }
366
367}
368#endif
369
370
4562236b
HW		 371/* Init display KMS
372 *
373 * Returns 0 on success
374 */
7578ecda 375static int amdgpu_dm_init(struct amdgpu_device *adev)
4562236b
HW		 376{
377 struct dc_init_data init_data;
378 adev->dm.ddev = adev->ddev;
379 adev->dm.adev = adev;
380
4562236b
HW		 381 /* Zero all the fields */
382 memset(&init_data, 0, sizeof(init_data));
383
384 /* initialize DAL's lock (for SYNC context use) */
385 spin_lock_init(&adev->dm.dal_lock);
386
387 /* initialize DAL's mutex */
388 mutex_init(&adev->dm.dal_mutex);
389
390 if(amdgpu_dm_irq_init(adev)) {
391 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
392 goto error;
393 }
394
395 init_data.asic_id.chip_family = adev->family;
396
397 init_data.asic_id.pci_revision_id = adev->rev_id;
398 init_data.asic_id.hw_internal_rev = adev->external_rev_id;
399
400 init_data.asic_id.vram_width = adev->mc.vram_width;
401 /* TODO: initialize init_data.asic_id.vram_type here!!!! */
402 init_data.asic_id.atombios_base_address =
403 adev->mode_info.atom_context->bios;
404
405 init_data.driver = adev;
406
407 adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
408
409 if (!adev->dm.cgs_device) {
410 DRM_ERROR("amdgpu: failed to create cgs device.\n");
411 goto error;
412 }
413
414 init_data.cgs_device = adev->dm.cgs_device;
415
416 adev->dm.dal = NULL;
417
418 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
419
f1ad2f5e
HW		 420 if (amdgpu_dc_log)
421 init_data.log_mask = DC_DEFAULT_LOG_MASK;
422 else
423 init_data.log_mask = DC_MIN_LOG_MASK;
01a526f3 424
a32e24b4
RL		 425#ifdef ENABLE_FBC
426 if (adev->family == FAMILY_CZ)
427 amdgpu_dm_initialize_fbc(adev);
428 init_data.fbc_gpu_addr = adev->dm.compressor.gpu_addr;
429#endif
4562236b
HW		 430 /* Display Core create. */
431 adev->dm.dc = dc_create(&init_data);
432
f1ad2f5e
HW		 433 if (adev->dm.dc)
434 DRM_INFO("Display Core initialized!\n");
435 else
4562236b
HW		 436 DRM_INFO("Display Core failed to initialize!\n");
437
438 INIT_WORK(&adev->dm.mst_hotplug_work, hotplug_notify_work_func);
439
440 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
441 if (!adev->dm.freesync_module) {
442 DRM_ERROR(
443 "amdgpu: failed to initialize freesync_module.\n");
444 } else
f1ad2f5e 445 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
4562236b
HW		 446 adev->dm.freesync_module);
447
448 if (amdgpu_dm_initialize_drm_device(adev)) {
449 DRM_ERROR(
450 "amdgpu: failed to initialize sw for display support.\n");
451 goto error;
452 }
453
454 /* Update the actual used number of crtc */
455 adev->mode_info.num_crtc = adev->dm.display_indexes_num;
456
457 /* TODO: Add_display_info? */
458
459 /* TODO use dynamic cursor width */
ce75805e
AG		 460 adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
461 adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
4562236b
HW		 462
463 if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) {
464 DRM_ERROR(
465 "amdgpu: failed to initialize sw for display support.\n");
466 goto error;
467 }
468
f1ad2f5e 469 DRM_DEBUG_DRIVER("KMS initialized.\n");
4562236b
HW		 470
471 return 0;
472error:
473 amdgpu_dm_fini(adev);
474
475 return -1;
476}
477
7578ecda 478static void amdgpu_dm_fini(struct amdgpu_device *adev)
4562236b
HW		 479{
480 amdgpu_dm_destroy_drm_device(&adev->dm);
481 /*
482 * TODO: pageflip, vlank interrupt
483 *
484 * amdgpu_dm_irq_fini(adev);
485 */
486
487 if (adev->dm.cgs_device) {
488 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
489 adev->dm.cgs_device = NULL;
490 }
491 if (adev->dm.freesync_module) {
492 mod_freesync_destroy(adev->dm.freesync_module);
493 adev->dm.freesync_module = NULL;
494 }
495 /* DC Destroy TODO: Replace destroy DAL */
21de3396 496 if (adev->dm.dc)
4562236b 497 dc_destroy(&adev->dm.dc);
4562236b
HW		 498 return;
499}
500
4562236b
HW		 501static int dm_sw_init(void *handle)
502{
503 return 0;
504}
505
506static int dm_sw_fini(void *handle)
507{
508 return 0;
509}
510
7abcf6b5 511static int detect_mst_link_for_all_connectors(struct drm_device *dev)
4562236b 512{
c84dec2f 513 struct amdgpu_dm_connector *aconnector;
4562236b 514 struct drm_connector *connector;
7abcf6b5 515 int ret = 0;
4562236b
HW		 516
517 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
518
519 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
c84dec2f 520 aconnector = to_amdgpu_dm_connector(connector);
7abcf6b5 521 if (aconnector->dc_link->type == dc_connection_mst_branch) {
f1ad2f5e 522 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
7abcf6b5
AG		 523 aconnector, aconnector->base.base.id);
524
525 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
526 if (ret < 0) {
527 DRM_ERROR("DM_MST: Failed to start MST\n");
528 ((struct dc_link *)aconnector->dc_link)->type = dc_connection_single;
529 return ret;
4562236b 530 }
7abcf6b5 531 }
4562236b
HW		 532 }
533
534 drm_modeset_unlock(&dev->mode_config.connection_mutex);
7abcf6b5
AG		 535 return ret;
536}
537
538static int dm_late_init(void *handle)
539{
540 struct drm_device *dev = ((struct amdgpu_device *)handle)->ddev;
7abcf6b5 541
33be2785 542 return detect_mst_link_for_all_connectors(dev);
4562236b
HW		 543}
544
545static void s3_handle_mst(struct drm_device *dev, bool suspend)
546{
c84dec2f 547 struct amdgpu_dm_connector *aconnector;
4562236b
HW		 548 struct drm_connector *connector;
549
550 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
551
552 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
c84dec2f 553 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 554 if (aconnector->dc_link->type == dc_connection_mst_branch &&
555 !aconnector->mst_port) {
556
557 if (suspend)
558 drm_dp_mst_topology_mgr_suspend(&aconnector->mst_mgr);
559 else
560 drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr);
561 }
562 }
563
564 drm_modeset_unlock(&dev->mode_config.connection_mutex);
565}
566
567static int dm_hw_init(void *handle)
568{
569 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
570 /* Create DAL display manager */
571 amdgpu_dm_init(adev);
4562236b
HW		 572 amdgpu_dm_hpd_init(adev);
573
4562236b
HW		 574 return 0;
575}
576
577static int dm_hw_fini(void *handle)
578{
579 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
580
581 amdgpu_dm_hpd_fini(adev);
582
583 amdgpu_dm_irq_fini(adev);
21de3396 584 amdgpu_dm_fini(adev);
4562236b
HW		 585 return 0;
586}
587
588static int dm_suspend(void *handle)
589{
590 struct amdgpu_device *adev = handle;
591 struct amdgpu_display_manager *dm = &adev->dm;
592 int ret = 0;
4562236b
HW		 593
594 s3_handle_mst(adev->ddev, true);
595
4562236b
HW		 596 amdgpu_dm_irq_suspend(adev);
597
0a214e2f 598 WARN_ON(adev->dm.cached_state);
a3621485
AG		 599 adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);
600
4562236b
HW		 601 dc_set_power_state(
602 dm->dc,
a3621485
AG		 603 DC_ACPI_CM_POWER_STATE_D3
604 );
4562236b
HW		 605
606 return ret;
607}
608
1daf8c63
AD		 609static struct amdgpu_dm_connector *
610amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
611 struct drm_crtc *crtc)
4562236b
HW		 612{
613 uint32_t i;
c2cea706 614 struct drm_connector_state *new_con_state;
4562236b
HW		 615 struct drm_connector *connector;
616 struct drm_crtc *crtc_from_state;
617
c2cea706
LSL		 618 for_each_new_connector_in_state(state, connector, new_con_state, i) {
619 crtc_from_state = new_con_state->crtc;
4562236b
HW		 620
621 if (crtc_from_state == crtc)
c84dec2f 622 return to_amdgpu_dm_connector(connector);
4562236b
HW		 623 }
624
625 return NULL;
626}
627
4562236b
HW		 628static int dm_resume(void *handle)
629{
630 struct amdgpu_device *adev = handle;
631 struct amdgpu_display_manager *dm = &adev->dm;
632
633 /* power on hardware */
634 dc_set_power_state(
635 dm->dc,
a3621485
AG		 636 DC_ACPI_CM_POWER_STATE_D0
637 );
4562236b
HW		 638
639 return 0;
640}
641
1ecfc3da 642int amdgpu_dm_display_resume(struct amdgpu_device *adev)
4562236b
HW		 643{
644 struct drm_device *ddev = adev->ddev;
645 struct amdgpu_display_manager *dm = &adev->dm;
c84dec2f 646 struct amdgpu_dm_connector *aconnector;
4562236b 647 struct drm_connector *connector;
4562236b 648 struct drm_crtc *crtc;
c2cea706 649 struct drm_crtc_state *new_crtc_state;
4f346e65
LSL		 650 struct dm_crtc_state *dm_crtc_state;
651 struct drm_plane *plane;
652 struct drm_plane_state *plane_state;
653 struct dm_plane_state *dm_plane_state;
654 struct dm_atomic_state *cached_state;
a3621485
AG		 655 int ret = 0;
656 int i;
4562236b
HW		 657
658 /* program HPD filter */
659 dc_resume(dm->dc);
660
661 /* On resume we need to rewrite the MSTM control bits to enamble MST*/
662 s3_handle_mst(ddev, false);
663
664 /*
665 * early enable HPD Rx IRQ, should be done before set mode as short
666 * pulse interrupts are used for MST
667 */
668 amdgpu_dm_irq_resume_early(adev);
669
4562236b
HW		 670 /* Do detection*/
671 list_for_each_entry(connector,
672 &ddev->mode_config.connector_list, head) {
c84dec2f 673 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 674
675 /*
676 * this is the case when traversing through already created
677 * MST connectors, should be skipped
678 */
679 if (aconnector->mst_port)
680 continue;
681
03ea364c 682 mutex_lock(&aconnector->hpd_lock);
8f38b66c 683 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
4562236b
HW		 684 aconnector->dc_sink = NULL;
685 amdgpu_dm_update_connector_after_detect(aconnector);
03ea364c 686 mutex_unlock(&aconnector->hpd_lock);
4562236b
HW		 687 }
688
a3621485 689 /* Force mode set in atomic comit */
c2cea706
LSL		 690 for_each_new_crtc_in_state(adev->dm.cached_state, crtc, new_crtc_state, i)
691 new_crtc_state->active_changed = true;
a3621485 692
4f346e65
LSL		 693 cached_state = to_dm_atomic_state(adev->dm.cached_state);
694
695 /*
696 * During suspend, the cached state is saved before all streams are
697 * disabled. Refresh cached state to match actual current state before
698 * restoring it.
699 */
700 WARN_ON(kref_read(&cached_state->context->refcount) > 1);
701 dc_release_state(cached_state->context);
702
703 cached_state->context = dc_create_state();
5771ec8f 704 ASSERT(cached_state->context);
4f346e65
LSL		 705 dc_resource_state_copy_construct_current(adev->dm.dc, cached_state->context);
706
707 for_each_new_crtc_in_state(adev->dm.cached_state, crtc, new_crtc_state, i) {
708 dm_crtc_state = to_dm_crtc_state(new_crtc_state);
709 if (dm_crtc_state->stream) {
710 WARN_ON(kref_read(&dm_crtc_state->stream->refcount) > 1);
711 dc_stream_release(dm_crtc_state->stream);
712 dm_crtc_state->stream = NULL;
713 }
714 }
715
716 for_each_new_plane_in_state(adev->dm.cached_state, plane, plane_state, i) {
717 dm_plane_state = to_dm_plane_state(plane_state);
718 if (dm_plane_state->dc_state) {
719 WARN_ON(kref_read(&dm_plane_state->dc_state->refcount) > 1);
720 dc_plane_state_release(dm_plane_state->dc_state);
721 dm_plane_state->dc_state = NULL;
722 }
723 }
724
a3621485 725 ret = drm_atomic_helper_resume(ddev, adev->dm.cached_state);
4562236b 726
0a214e2f
AG		 727 drm_atomic_state_put(adev->dm.cached_state);
728 adev->dm.cached_state = NULL;
729
9faa4237 730 amdgpu_dm_irq_resume_late(adev);
4562236b
HW		 731
732 return ret;
733}
734
735static const struct amd_ip_funcs amdgpu_dm_funcs = {
736 .name = "dm",
737 .early_init = dm_early_init,
7abcf6b5 738 .late_init = dm_late_init,
4562236b
HW		 739 .sw_init = dm_sw_init,
740 .sw_fini = dm_sw_fini,
741 .hw_init = dm_hw_init,
742 .hw_fini = dm_hw_fini,
743 .suspend = dm_suspend,
744 .resume = dm_resume,
745 .is_idle = dm_is_idle,
746 .wait_for_idle = dm_wait_for_idle,
747 .check_soft_reset = dm_check_soft_reset,
748 .soft_reset = dm_soft_reset,
749 .set_clockgating_state = dm_set_clockgating_state,
750 .set_powergating_state = dm_set_powergating_state,
751};
752
753const struct amdgpu_ip_block_version dm_ip_block =
754{
755 .type = AMD_IP_BLOCK_TYPE_DCE,
756 .major = 1,
757 .minor = 0,
758 .rev = 0,
759 .funcs = &amdgpu_dm_funcs,
760};
761
ca3268c4 762
7578ecda 763static struct drm_atomic_state *
ca3268c4
HW		 764dm_atomic_state_alloc(struct drm_device *dev)
765{
766 struct dm_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
767
1dc90497 768 if (!state)
ca3268c4 769 return NULL;
1dc90497
AG		 770
771 if (drm_atomic_state_init(dev, &state->base) < 0)
772 goto fail;
773
ca3268c4 774 return &state->base;
1dc90497
AG		 775
776fail:
777 kfree(state);
778 return NULL;
ca3268c4
HW		 779}
780
0a323b84
AG		 781static void
782dm_atomic_state_clear(struct drm_atomic_state *state)
783{
784 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
785
786 if (dm_state->context) {
608ac7bb 787 dc_release_state(dm_state->context);
0a323b84
AG		 788 dm_state->context = NULL;
789 }
790
791 drm_atomic_state_default_clear(state);
792}
793
794static void
795dm_atomic_state_alloc_free(struct drm_atomic_state *state)
796{
797 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
798 drm_atomic_state_default_release(state);
799 kfree(dm_state);
800}
801
b3663f70 802static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
a49dcb88
HW		 803 .fb_create = amdgpu_user_framebuffer_create,
804 .output_poll_changed = amdgpu_output_poll_changed,
4562236b 805 .atomic_check = amdgpu_dm_atomic_check,
da5c47f6 806 .atomic_commit = amdgpu_dm_atomic_commit,
ca3268c4 807 .atomic_state_alloc = dm_atomic_state_alloc,
0a323b84
AG		 808 .atomic_state_clear = dm_atomic_state_clear,
809 .atomic_state_free = dm_atomic_state_alloc_free
54f5499a
AG		 810};
811
812static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
813 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail
4562236b
HW		 814};
815
7578ecda 816static void
3ee6b26b 817amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
4562236b
HW		 818{
819 struct drm_connector *connector = &aconnector->base;
820 struct drm_device *dev = connector->dev;
b73a22d3 821 struct dc_sink *sink;
4562236b
HW		 822
823 /* MST handled by drm_mst framework */
824 if (aconnector->mst_mgr.mst_state == true)
825 return;
826
827
828 sink = aconnector->dc_link->local_sink;
829
830 /* Edid mgmt connector gets first update only in mode_valid hook and then
831 * the connector sink is set to either fake or physical sink depends on link status.
832 * don't do it here if u are during boot
833 */
834 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
835 && aconnector->dc_em_sink) {
836
ab2541b6 837 /* For S3 resume with headless use eml_sink to fake stream
4562236b
HW		 838 * because on resume connecotr->sink is set ti NULL
839 */
840 mutex_lock(&dev->mode_config.mutex);
841
842 if (sink) {
922aa1e1 843 if (aconnector->dc_sink) {
4562236b
HW		 844 amdgpu_dm_remove_sink_from_freesync_module(
845 connector);
922aa1e1
AG		 846 /* retain and release bellow are used for
847 * bump up refcount for sink because the link don't point
848 * to it anymore after disconnect so on next crtc to connector
849 * reshuffle by UMD we will get into unwanted dc_sink release
850 */
851 if (aconnector->dc_sink != aconnector->dc_em_sink)
852 dc_sink_release(aconnector->dc_sink);
853 }
4562236b
HW		 854 aconnector->dc_sink = sink;
855 amdgpu_dm_add_sink_to_freesync_module(
856 connector, aconnector->edid);
857 } else {
858 amdgpu_dm_remove_sink_from_freesync_module(connector);
859 if (!aconnector->dc_sink)
860 aconnector->dc_sink = aconnector->dc_em_sink;
922aa1e1
AG		 861 else if (aconnector->dc_sink != aconnector->dc_em_sink)
862 dc_sink_retain(aconnector->dc_sink);
4562236b
HW		 863 }
864
865 mutex_unlock(&dev->mode_config.mutex);
866 return;
867 }
868
869 /*
870 * TODO: temporary guard to look for proper fix
871 * if this sink is MST sink, we should not do anything
872 */
873 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
874 return;
875
876 if (aconnector->dc_sink == sink) {
877 /* We got a DP short pulse (Link Loss, DP CTS, etc...).
878 * Do nothing!! */
f1ad2f5e 879 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
4562236b
HW		 880 aconnector->connector_id);
881 return;
882 }
883
f1ad2f5e 884 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
4562236b
HW		 885 aconnector->connector_id, aconnector->dc_sink, sink);
886
887 mutex_lock(&dev->mode_config.mutex);
888
889 /* 1. Update status of the drm connector
890 * 2. Send an event and let userspace tell us what to do */
891 if (sink) {
892 /* TODO: check if we still need the S3 mode update workaround.
893 * If yes, put it here. */
894 if (aconnector->dc_sink)
895 amdgpu_dm_remove_sink_from_freesync_module(
896 connector);
897
898 aconnector->dc_sink = sink;
899 if (sink->dc_edid.length == 0)
900 aconnector->edid = NULL;
901 else {
902 aconnector->edid =
903 (struct edid *) sink->dc_edid.raw_edid;
904
905
906 drm_mode_connector_update_edid_property(connector,
907 aconnector->edid);
908 }
909 amdgpu_dm_add_sink_to_freesync_module(connector, aconnector->edid);
910
911 } else {
912 amdgpu_dm_remove_sink_from_freesync_module(connector);
913 drm_mode_connector_update_edid_property(connector, NULL);
914 aconnector->num_modes = 0;
915 aconnector->dc_sink = NULL;
916 }
917
918 mutex_unlock(&dev->mode_config.mutex);
919}
920
921static void handle_hpd_irq(void *param)
922{
c84dec2f 923 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
4562236b
HW		 924 struct drm_connector *connector = &aconnector->base;
925 struct drm_device *dev = connector->dev;
926
927 /* In case of failure or MST no need to update connector status or notify the OS
928 * since (for MST case) MST does this in it's own context.
929 */
930 mutex_lock(&aconnector->hpd_lock);
2e0ac3d6
HW		 931
932 if (aconnector->fake_enable)
933 aconnector->fake_enable = false;
934
8f38b66c 935 if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
4562236b
HW		 936 amdgpu_dm_update_connector_after_detect(aconnector);
937
938
939 drm_modeset_lock_all(dev);
940 dm_restore_drm_connector_state(dev, connector);
941 drm_modeset_unlock_all(dev);
942
943 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
944 drm_kms_helper_hotplug_event(dev);
945 }
946 mutex_unlock(&aconnector->hpd_lock);
947
948}
949
c84dec2f 950static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector)
4562236b
HW		 951{
952 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
953 uint8_t dret;
954 bool new_irq_handled = false;
955 int dpcd_addr;
956 int dpcd_bytes_to_read;
957
958 const int max_process_count = 30;
959 int process_count = 0;
960
961 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
962
963 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
964 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
965 /* DPCD 0x200 - 0x201 for downstream IRQ */
966 dpcd_addr = DP_SINK_COUNT;
967 } else {
968 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
969 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
970 dpcd_addr = DP_SINK_COUNT_ESI;
971 }
972
973 dret = drm_dp_dpcd_read(
974 &aconnector->dm_dp_aux.aux,
975 dpcd_addr,
976 esi,
977 dpcd_bytes_to_read);
978
979 while (dret == dpcd_bytes_to_read &&
980 process_count < max_process_count) {
981 uint8_t retry;
982 dret = 0;
983
984 process_count++;
985
f1ad2f5e 986 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
4562236b
HW		 987 /* handle HPD short pulse irq */
988 if (aconnector->mst_mgr.mst_state)
989 drm_dp_mst_hpd_irq(
990 &aconnector->mst_mgr,
991 esi,
992 &new_irq_handled);
4562236b
HW		 993
994 if (new_irq_handled) {
995 /* ACK at DPCD to notify down stream */
996 const int ack_dpcd_bytes_to_write =
997 dpcd_bytes_to_read - 1;
998
999 for (retry = 0; retry < 3; retry++) {
1000 uint8_t wret;
1001
1002 wret = drm_dp_dpcd_write(
1003 &aconnector->dm_dp_aux.aux,
1004 dpcd_addr + 1,
1005 &esi[1],
1006 ack_dpcd_bytes_to_write);
1007 if (wret == ack_dpcd_bytes_to_write)
1008 break;
1009 }
1010
1011 /* check if there is new irq to be handle */
1012 dret = drm_dp_dpcd_read(
1013 &aconnector->dm_dp_aux.aux,
1014 dpcd_addr,
1015 esi,
1016 dpcd_bytes_to_read);
1017
1018 new_irq_handled = false;
1019 } else
1020 break;
1021 }
1022
1023 if (process_count == max_process_count)
f1ad2f5e 1024 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
4562236b
HW		 1025}
1026
1027static void handle_hpd_rx_irq(void *param)
1028{
c84dec2f 1029 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
4562236b
HW		 1030 struct drm_connector *connector = &aconnector->base;
1031 struct drm_device *dev = connector->dev;
1032 const struct dc_link *dc_link = aconnector->dc_link;
1033 bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
1034
1035 /* TODO:Temporary add mutex to protect hpd interrupt not have a gpio
1036 * conflict, after implement i2c helper, this mutex should be
1037 * retired.
1038 */
1039 if (aconnector->dc_link->type != dc_connection_mst_branch)
1040 mutex_lock(&aconnector->hpd_lock);
1041
8ee65d7c 1042 if (dc_link_handle_hpd_rx_irq(aconnector->dc_link, NULL) &&
4562236b
HW		 1043 !is_mst_root_connector) {
1044 /* Downstream Port status changed. */
8f38b66c 1045 if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPDRX)) {
4562236b
HW		 1046 amdgpu_dm_update_connector_after_detect(aconnector);
1047
1048
1049 drm_modeset_lock_all(dev);
1050 dm_restore_drm_connector_state(dev, connector);
1051 drm_modeset_unlock_all(dev);
1052
1053 drm_kms_helper_hotplug_event(dev);
1054 }
1055 }
1056 if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
1057 (dc_link->type == dc_connection_mst_branch))
1058 dm_handle_hpd_rx_irq(aconnector);
1059
1060 if (aconnector->dc_link->type != dc_connection_mst_branch)
1061 mutex_unlock(&aconnector->hpd_lock);
1062}
1063
1064static void register_hpd_handlers(struct amdgpu_device *adev)
1065{
1066 struct drm_device *dev = adev->ddev;
1067 struct drm_connector *connector;
c84dec2f 1068 struct amdgpu_dm_connector *aconnector;
4562236b
HW		 1069 const struct dc_link *dc_link;
1070 struct dc_interrupt_params int_params = {0};
1071
1072 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1073 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1074
1075 list_for_each_entry(connector,
1076 &dev->mode_config.connector_list, head) {
1077
c84dec2f 1078 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 1079 dc_link = aconnector->dc_link;
1080
1081 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
1082 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1083 int_params.irq_source = dc_link->irq_source_hpd;
1084
1085 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1086 handle_hpd_irq,
1087 (void *) aconnector);
1088 }
1089
1090 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
1091
1092 /* Also register for DP short pulse (hpd_rx). */
1093 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1094 int_params.irq_source = dc_link->irq_source_hpd_rx;
1095
1096 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1097 handle_hpd_rx_irq,
1098 (void *) aconnector);
1099 }
1100 }
1101}
1102
1103/* Register IRQ sources and initialize IRQ callbacks */
1104static int dce110_register_irq_handlers(struct amdgpu_device *adev)
1105{
1106 struct dc *dc = adev->dm.dc;
1107 struct common_irq_params *c_irq_params;
1108 struct dc_interrupt_params int_params = {0};
1109 int r;
1110 int i;
2c8ad2d5
AD		 1111 unsigned client_id = AMDGPU_IH_CLIENTID_LEGACY;
1112
ff5ef992
AD		 1113 if (adev->asic_type == CHIP_VEGA10 ||
1114 adev->asic_type == CHIP_RAVEN)
2c8ad2d5 1115 client_id = AMDGPU_IH_CLIENTID_DCE;
4562236b
HW		 1116
1117 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1118 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1119
1120 /* Actions of amdgpu_irq_add_id():
1121 * 1. Register a set() function with base driver.
1122 * Base driver will call set() function to enable/disable an
1123 * interrupt in DC hardware.
1124 * 2. Register amdgpu_dm_irq_handler().
1125 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1126 * coming from DC hardware.
1127 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1128 * for acknowledging and handling. */
1129
b57de80a 1130 /* Use VBLANK interrupt */
e9029155 1131 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
2c8ad2d5 1132 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
4562236b
HW		 1133 if (r) {
1134 DRM_ERROR("Failed to add crtc irq id!\n");
1135 return r;
1136 }
1137
1138 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1139 int_params.irq_source =
3d761e79 1140 dc_interrupt_to_irq_source(dc, i, 0);
4562236b 1141
b57de80a 1142 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
4562236b
HW		 1143
1144 c_irq_params->adev = adev;
1145 c_irq_params->irq_src = int_params.irq_source;
1146
1147 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1148 dm_crtc_high_irq, c_irq_params);
1149 }
1150
3d761e79 1151 /* Use GRPH_PFLIP interrupt */
4562236b
HW		 1152 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
1153 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
2c8ad2d5 1154 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
4562236b
HW		 1155 if (r) {
1156 DRM_ERROR("Failed to add page flip irq id!\n");
1157 return r;
1158 }
1159
1160 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1161 int_params.irq_source =
1162 dc_interrupt_to_irq_source(dc, i, 0);
1163
1164 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1165
1166 c_irq_params->adev = adev;
1167 c_irq_params->irq_src = int_params.irq_source;
1168
1169 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1170 dm_pflip_high_irq, c_irq_params);
1171
1172 }
1173
1174 /* HPD */
2c8ad2d5
AD		 1175 r = amdgpu_irq_add_id(adev, client_id,
1176 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
4562236b
HW		 1177 if (r) {
1178 DRM_ERROR("Failed to add hpd irq id!\n");
1179 return r;
1180 }
1181
1182 register_hpd_handlers(adev);
1183
1184 return 0;
1185}
1186
ff5ef992
AD		 1187#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1188/* Register IRQ sources and initialize IRQ callbacks */
1189static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
1190{
1191 struct dc *dc = adev->dm.dc;
1192 struct common_irq_params *c_irq_params;
1193 struct dc_interrupt_params int_params = {0};
1194 int r;
1195 int i;
1196
1197 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1198 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1199
1200 /* Actions of amdgpu_irq_add_id():
1201 * 1. Register a set() function with base driver.
1202 * Base driver will call set() function to enable/disable an
1203 * interrupt in DC hardware.
1204 * 2. Register amdgpu_dm_irq_handler().
1205 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1206 * coming from DC hardware.
1207 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1208 * for acknowledging and handling.
1209 * */
1210
1211 /* Use VSTARTUP interrupt */
1212 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
1213 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
1214 i++) {
1215 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, i, &adev->crtc_irq);
1216
1217 if (r) {
1218 DRM_ERROR("Failed to add crtc irq id!\n");
1219 return r;
1220 }
1221
1222 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1223 int_params.irq_source =
1224 dc_interrupt_to_irq_source(dc, i, 0);
1225
1226 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1227
1228 c_irq_params->adev = adev;
1229 c_irq_params->irq_src = int_params.irq_source;
1230
1231 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1232 dm_crtc_high_irq, c_irq_params);
1233 }
1234
1235 /* Use GRPH_PFLIP interrupt */
1236 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
1237 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
1238 i++) {
1239 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
1240 if (r) {
1241 DRM_ERROR("Failed to add page flip irq id!\n");
1242 return r;
1243 }
1244
1245 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1246 int_params.irq_source =
1247 dc_interrupt_to_irq_source(dc, i, 0);
1248
1249 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1250
1251 c_irq_params->adev = adev;
1252 c_irq_params->irq_src = int_params.irq_source;
1253
1254 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1255 dm_pflip_high_irq, c_irq_params);
1256
1257 }
1258
1259 /* HPD */
1260 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
1261 &adev->hpd_irq);
1262 if (r) {
1263 DRM_ERROR("Failed to add hpd irq id!\n");
1264 return r;
1265 }
1266
1267 register_hpd_handlers(adev);
1268
1269 return 0;
1270}
1271#endif
1272
4562236b
HW		 1273static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
1274{
1275 int r;
1276
1277 adev->mode_info.mode_config_initialized = true;
1278
4562236b 1279 adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
54f5499a 1280 adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
4562236b
HW		 1281
1282 adev->ddev->mode_config.max_width = 16384;
1283 adev->ddev->mode_config.max_height = 16384;
1284
1285 adev->ddev->mode_config.preferred_depth = 24;
1286 adev->ddev->mode_config.prefer_shadow = 1;
1287 /* indicate support of immediate flip */
1288 adev->ddev->mode_config.async_page_flip = true;
1289
1290 adev->ddev->mode_config.fb_base = adev->mc.aper_base;
1291
1292 r = amdgpu_modeset_create_props(adev);
1293 if (r)
1294 return r;
1295
1296 return 0;
1297}
1298
1299#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1300 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1301
1302static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
1303{
1304 struct amdgpu_display_manager *dm = bl_get_data(bd);
1305
1306 if (dc_link_set_backlight_level(dm->backlight_link,
1307 bd->props.brightness, 0, 0))
1308 return 0;
1309 else
1310 return 1;
1311}
1312
1313static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
1314{
1315 return bd->props.brightness;
1316}
1317
1318static const struct backlight_ops amdgpu_dm_backlight_ops = {
1319 .get_brightness = amdgpu_dm_backlight_get_brightness,
1320 .update_status = amdgpu_dm_backlight_update_status,
1321};
1322
7578ecda
AD		 1323static void
1324amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
4562236b
HW		 1325{
1326 char bl_name[16];
1327 struct backlight_properties props = { 0 };
1328
1329 props.max_brightness = AMDGPU_MAX_BL_LEVEL;
1330 props.type = BACKLIGHT_RAW;
1331
1332 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
1333 dm->adev->ddev->primary->index);
1334
1335 dm->backlight_dev = backlight_device_register(bl_name,
1336 dm->adev->ddev->dev,
1337 dm,
1338 &amdgpu_dm_backlight_ops,
1339 &props);
1340
1341 if (NULL == dm->backlight_dev)
1342 DRM_ERROR("DM: Backlight registration failed!\n");
1343 else
f1ad2f5e 1344 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4562236b
HW		 1345}
1346
1347#endif
1348
1349/* In this architecture, the association
1350 * connector -> encoder -> crtc
1351 * id not really requried. The crtc and connector will hold the
1352 * display_index as an abstraction to use with DAL component
1353 *
1354 * Returns 0 on success
1355 */
7578ecda 1356static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4562236b
HW		 1357{
1358 struct amdgpu_display_manager *dm = &adev->dm;
1359 uint32_t i;
c84dec2f 1360 struct amdgpu_dm_connector *aconnector = NULL;
f2a0f5e6 1361 struct amdgpu_encoder *aencoder = NULL;
d4e13b0d 1362 struct amdgpu_mode_info *mode_info = &adev->mode_info;
4562236b 1363 uint32_t link_cnt;
92f3ac40 1364 unsigned long possible_crtcs;
4562236b
HW		 1365
1366 link_cnt = dm->dc->caps.max_links;
4562236b
HW		 1367 if (amdgpu_dm_mode_config_init(dm->adev)) {
1368 DRM_ERROR("DM: Failed to initialize mode config\n");
f2a0f5e6 1369 return -1;
4562236b
HW		 1370 }
1371
3be5262e 1372 for (i = 0; i < dm->dc->caps.max_planes; i++) {
d4e13b0d
AD		 1373 mode_info->planes[i] = kzalloc(sizeof(struct amdgpu_plane),
1374 GFP_KERNEL);
1375 if (!mode_info->planes[i]) {
3be5262e 1376 DRM_ERROR("KMS: Failed to allocate plane\n");
d4e13b0d
AD		 1377 goto fail_free_planes;
1378 }
1605b3be 1379 mode_info->planes[i]->base.type = mode_info->plane_type[i];
92f3ac40
LSL		 1380
1381 /*
1382 * HACK: IGT tests expect that each plane can only have one
1383 * one possible CRTC. For now, set one CRTC for each
1384 * plane that is not an underlay, but still allow multiple
1385 * CRTCs for underlay planes.
1386 */
1387 possible_crtcs = 1 << i;
1388 if (i >= dm->dc->caps.max_streams)
1389 possible_crtcs = 0xff;
1390
1391 if (amdgpu_dm_plane_init(dm, mode_info->planes[i], possible_crtcs)) {
d4e13b0d
AD		 1392 DRM_ERROR("KMS: Failed to initialize plane\n");
1393 goto fail_free_planes;
1394 }
1395 }
4562236b 1396
d4e13b0d
AD		 1397 for (i = 0; i < dm->dc->caps.max_streams; i++)
1398 if (amdgpu_dm_crtc_init(dm, &mode_info->planes[i]->base, i)) {
4562236b 1399 DRM_ERROR("KMS: Failed to initialize crtc\n");
d4e13b0d 1400 goto fail_free_planes;
4562236b 1401 }
4562236b 1402
ab2541b6 1403 dm->display_indexes_num = dm->dc->caps.max_streams;
4562236b
HW		 1404
1405 /* loops over all connectors on the board */
1406 for (i = 0; i < link_cnt; i++) {
1407
1408 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
1409 DRM_ERROR(
1410 "KMS: Cannot support more than %d display indexes\n",
1411 AMDGPU_DM_MAX_DISPLAY_INDEX);
1412 continue;
1413 }
1414
1415 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
1416 if (!aconnector)
f2a0f5e6 1417 goto fail_free_planes;
4562236b
HW		 1418
1419 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
1420 if (!aencoder) {
1421 goto fail_free_connector;
1422 }
1423
1424 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
1425 DRM_ERROR("KMS: Failed to initialize encoder\n");
1426 goto fail_free_encoder;
1427 }
1428
1429 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
1430 DRM_ERROR("KMS: Failed to initialize connector\n");
f2a0f5e6 1431 goto fail_free_encoder;
4562236b
HW		 1432 }
1433
8f38b66c
HW		 1434 if (dc_link_detect(dc_get_link_at_index(dm->dc, i),
1435 DETECT_REASON_BOOT))
4562236b
HW		 1436 amdgpu_dm_update_connector_after_detect(aconnector);
1437 }
1438
1439 /* Software is initialized. Now we can register interrupt handlers. */
1440 switch (adev->asic_type) {
1441 case CHIP_BONAIRE:
1442 case CHIP_HAWAII:
cd4b356f
AD		 1443 case CHIP_KAVERI:
1444 case CHIP_KABINI:
1445 case CHIP_MULLINS:
4562236b
HW		 1446 case CHIP_TONGA:
1447 case CHIP_FIJI:
1448 case CHIP_CARRIZO:
1449 case CHIP_STONEY:
1450 case CHIP_POLARIS11:
1451 case CHIP_POLARIS10:
b264d345 1452 case CHIP_POLARIS12:
2c8ad2d5 1453 case CHIP_VEGA10:
4562236b
HW		 1454 if (dce110_register_irq_handlers(dm->adev)) {
1455 DRM_ERROR("DM: Failed to initialize IRQ\n");
d4e13b0d 1456 goto fail_free_encoder;
4562236b
HW		 1457 }
1458 break;
ff5ef992
AD		 1459#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1460 case CHIP_RAVEN:
1461 if (dcn10_register_irq_handlers(dm->adev)) {
1462 DRM_ERROR("DM: Failed to initialize IRQ\n");
1463 goto fail_free_encoder;
1464 }
79c24086
BL		 1465 /*
1466 * Temporary disable until pplib/smu interaction is implemented
1467 */
1468 dm->dc->debug.disable_stutter = true;
ff5ef992
AD		 1469 break;
1470#endif
4562236b
HW		 1471 default:
1472 DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type);
d4e13b0d 1473 goto fail_free_encoder;
4562236b
HW		 1474 }
1475
1476 drm_mode_config_reset(dm->ddev);
1477
1478 return 0;
1479fail_free_encoder:
1480 kfree(aencoder);
1481fail_free_connector:
1482 kfree(aconnector);
d4e13b0d 1483fail_free_planes:
3be5262e 1484 for (i = 0; i < dm->dc->caps.max_planes; i++)
d4e13b0d 1485 kfree(mode_info->planes[i]);
4562236b
HW		 1486 return -1;
1487}
1488
7578ecda 1489static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4562236b
HW		 1490{
1491 drm_mode_config_cleanup(dm->ddev);
1492 return;
1493}
1494
1495/******************************************************************************
1496 * amdgpu_display_funcs functions
1497 *****************************************************************************/
1498
1499/**
1500 * dm_bandwidth_update - program display watermarks
1501 *
1502 * @adev: amdgpu_device pointer
1503 *
1504 * Calculate and program the display watermarks and line buffer allocation.
1505 */
1506static void dm_bandwidth_update(struct amdgpu_device *adev)
1507{
49c07a99 1508 /* TODO: implement later */
4562236b
HW		 1509}
1510
1511static void dm_set_backlight_level(struct amdgpu_encoder *amdgpu_encoder,
1512 u8 level)
1513{
1514 /* TODO: translate amdgpu_encoder to display_index and call DAL */
4562236b
HW		 1515}
1516
1517static u8 dm_get_backlight_level(struct amdgpu_encoder *amdgpu_encoder)
1518{
1519 /* TODO: translate amdgpu_encoder to display_index and call DAL */
4562236b
HW		 1520 return 0;
1521}
1522
4562236b
HW		 1523static int amdgpu_notify_freesync(struct drm_device *dev, void *data,
1524 struct drm_file *filp)
1525{
1526 struct mod_freesync_params freesync_params;
ab2541b6 1527 uint8_t num_streams;
4562236b 1528 uint8_t i;
4562236b
HW		 1529
1530 struct amdgpu_device *adev = dev->dev_private;
1531 int r = 0;
1532
1533 /* Get freesync enable flag from DRM */
1534
ab2541b6 1535 num_streams = dc_get_current_stream_count(adev->dm.dc);
4562236b 1536
ab2541b6 1537 for (i = 0; i < num_streams; i++) {
0971c40e 1538 struct dc_stream_state *stream;
ab2541b6 1539 stream = dc_get_stream_at_index(adev->dm.dc, i);
4562236b
HW		 1540
1541 mod_freesync_update_state(adev->dm.freesync_module,
ab2541b6 1542 &stream, 1, &freesync_params);
4562236b
HW		 1543 }
1544
1545 return r;
1546}
1547
39cc5be2 1548static const struct amdgpu_display_funcs dm_display_funcs = {
4562236b
HW		 1549 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
1550 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
1551 .vblank_wait = NULL,
1552 .backlight_set_level =
1553 dm_set_backlight_level,/* called unconditionally */
1554 .backlight_get_level =
1555 dm_get_backlight_level,/* called unconditionally */
1556 .hpd_sense = NULL,/* called unconditionally */
1557 .hpd_set_polarity = NULL, /* called unconditionally */
1558 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4562236b
HW		 1559 .page_flip_get_scanoutpos =
1560 dm_crtc_get_scanoutpos,/* called unconditionally */
1561 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
1562 .add_connector = NULL, /* VBIOS parsing. DAL does it. */
1563 .notify_freesync = amdgpu_notify_freesync,
1564
1565};
1566
1567#if defined(CONFIG_DEBUG_KERNEL_DC)
1568
3ee6b26b
AD		 1569static ssize_t s3_debug_store(struct device *device,
1570 struct device_attribute *attr,
1571 const char *buf,
1572 size_t count)
4562236b
HW		 1573{
1574 int ret;
1575 int s3_state;
1576 struct pci_dev *pdev = to_pci_dev(device);
1577 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1578 struct amdgpu_device *adev = drm_dev->dev_private;
1579
1580 ret = kstrtoint(buf, 0, &s3_state);
1581
1582 if (ret == 0) {
1583 if (s3_state) {
1584 dm_resume(adev);
1585 amdgpu_dm_display_resume(adev);
1586 drm_kms_helper_hotplug_event(adev->ddev);
1587 } else
1588 dm_suspend(adev);
1589 }
1590
1591 return ret == 0 ? count : 0;
1592}
1593
1594DEVICE_ATTR_WO(s3_debug);
1595
1596#endif
1597
1598static int dm_early_init(void *handle)
1599{
1600 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1601
d7ec53d9 1602 adev->ddev->driver->driver_features |= DRIVER_ATOMIC;
4562236b
HW		 1603 amdgpu_dm_set_irq_funcs(adev);
1604
1605 switch (adev->asic_type) {
1606 case CHIP_BONAIRE:
1607 case CHIP_HAWAII:
1608 adev->mode_info.num_crtc = 6;
1609 adev->mode_info.num_hpd = 6;
1610 adev->mode_info.num_dig = 6;
3be5262e 1611 adev->mode_info.plane_type = dm_plane_type_default;
4562236b 1612 break;
cd4b356f
AD		 1613 case CHIP_KAVERI:
1614 adev->mode_info.num_crtc = 4;
1615 adev->mode_info.num_hpd = 6;
1616 adev->mode_info.num_dig = 7;
1617 adev->mode_info.plane_type = dm_plane_type_default;
1618 break;
1619 case CHIP_KABINI:
1620 case CHIP_MULLINS:
1621 adev->mode_info.num_crtc = 2;
1622 adev->mode_info.num_hpd = 6;
1623 adev->mode_info.num_dig = 6;
1624 adev->mode_info.plane_type = dm_plane_type_default;
1625 break;
4562236b
HW		 1626 case CHIP_FIJI:
1627 case CHIP_TONGA:
1628 adev->mode_info.num_crtc = 6;
1629 adev->mode_info.num_hpd = 6;
1630 adev->mode_info.num_dig = 7;
3be5262e 1631 adev->mode_info.plane_type = dm_plane_type_default;
4562236b
HW		 1632 break;
1633 case CHIP_CARRIZO:
1634 adev->mode_info.num_crtc = 3;
1635 adev->mode_info.num_hpd = 6;
1636 adev->mode_info.num_dig = 9;
3be5262e 1637 adev->mode_info.plane_type = dm_plane_type_carizzo;
4562236b
HW		 1638 break;
1639 case CHIP_STONEY:
1640 adev->mode_info.num_crtc = 2;
1641 adev->mode_info.num_hpd = 6;
1642 adev->mode_info.num_dig = 9;
3be5262e 1643 adev->mode_info.plane_type = dm_plane_type_stoney;
4562236b
HW		 1644 break;
1645 case CHIP_POLARIS11:
b264d345 1646 case CHIP_POLARIS12:
4562236b
HW		 1647 adev->mode_info.num_crtc = 5;
1648 adev->mode_info.num_hpd = 5;
1649 adev->mode_info.num_dig = 5;
3be5262e 1650 adev->mode_info.plane_type = dm_plane_type_default;
4562236b
HW		 1651 break;
1652 case CHIP_POLARIS10:
1653 adev->mode_info.num_crtc = 6;
1654 adev->mode_info.num_hpd = 6;
1655 adev->mode_info.num_dig = 6;
3be5262e 1656 adev->mode_info.plane_type = dm_plane_type_default;
4562236b 1657 break;
2c8ad2d5
AD		 1658 case CHIP_VEGA10:
1659 adev->mode_info.num_crtc = 6;
1660 adev->mode_info.num_hpd = 6;
1661 adev->mode_info.num_dig = 6;
3be5262e 1662 adev->mode_info.plane_type = dm_plane_type_default;
2c8ad2d5 1663 break;
ff5ef992
AD		 1664#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1665 case CHIP_RAVEN:
1666 adev->mode_info.num_crtc = 4;
1667 adev->mode_info.num_hpd = 4;
1668 adev->mode_info.num_dig = 4;
3be5262e 1669 adev->mode_info.plane_type = dm_plane_type_default;
ff5ef992
AD		 1670 break;
1671#endif
4562236b
HW		 1672 default:
1673 DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type);
1674 return -EINVAL;
1675 }
1676
39cc5be2
AD		 1677 if (adev->mode_info.funcs == NULL)
1678 adev->mode_info.funcs = &dm_display_funcs;
1679
4562236b
HW		 1680 /* Note: Do NOT change adev->audio_endpt_rreg and
1681 * adev->audio_endpt_wreg because they are initialised in
1682 * amdgpu_device_init() */
1683#if defined(CONFIG_DEBUG_KERNEL_DC)
1684 device_create_file(
1685 adev->ddev->dev,
1686 &dev_attr_s3_debug);
1687#endif
1688
1689 return 0;
1690}
1691
e7b07cee
HW		 1692struct dm_connector_state {
1693 struct drm_connector_state base;
1694
1695 enum amdgpu_rmx_type scaling;
1696 uint8_t underscan_vborder;
1697 uint8_t underscan_hborder;
1698 bool underscan_enable;
1699};
1700
1701#define to_dm_connector_state(x)\
1702 container_of((x), struct dm_connector_state, base)
1703
9b690ef3 1704static bool modeset_required(struct drm_crtc_state *crtc_state,
0971c40e
HW		 1705 struct dc_stream_state *new_stream,
1706 struct dc_stream_state *old_stream)
9b690ef3 1707{
e7b07cee
HW		 1708 if (!drm_atomic_crtc_needs_modeset(crtc_state))
1709 return false;
1710
1711 if (!crtc_state->enable)
1712 return false;
1713
1714 return crtc_state->active;
1715}
1716
1717static bool modereset_required(struct drm_crtc_state *crtc_state)
1718{
1719 if (!drm_atomic_crtc_needs_modeset(crtc_state))
1720 return false;
1721
1722 return !crtc_state->enable || !crtc_state->active;
1723}
1724
7578ecda 1725static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
e7b07cee
HW		 1726{
1727 drm_encoder_cleanup(encoder);
1728 kfree(encoder);
1729}
1730
1731static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
1732 .destroy = amdgpu_dm_encoder_destroy,
1733};
1734
3ee6b26b
AD		 1735static bool fill_rects_from_plane_state(const struct drm_plane_state *state,
1736 struct dc_plane_state *plane_state)
e7b07cee 1737{
3be5262e
HW		 1738 plane_state->src_rect.x = state->src_x >> 16;
1739 plane_state->src_rect.y = state->src_y >> 16;
e7b07cee 1740 /*we ignore for now mantissa and do not to deal with floating pixels :(*/
3be5262e 1741 plane_state->src_rect.width = state->src_w >> 16;
e7b07cee 1742
3be5262e 1743 if (plane_state->src_rect.width == 0)
e7b07cee
HW		 1744 return false;
1745
3be5262e
HW		 1746 plane_state->src_rect.height = state->src_h >> 16;
1747 if (plane_state->src_rect.height == 0)
e7b07cee
HW		 1748 return false;
1749
3be5262e
HW		 1750 plane_state->dst_rect.x = state->crtc_x;
1751 plane_state->dst_rect.y = state->crtc_y;
e7b07cee
HW		 1752
1753 if (state->crtc_w == 0)
1754 return false;
1755
3be5262e 1756 plane_state->dst_rect.width = state->crtc_w;
e7b07cee
HW		 1757
1758 if (state->crtc_h == 0)
1759 return false;
1760
3be5262e 1761 plane_state->dst_rect.height = state->crtc_h;
e7b07cee 1762
3be5262e 1763 plane_state->clip_rect = plane_state->dst_rect;
e7b07cee
HW		 1764
1765 switch (state->rotation & DRM_MODE_ROTATE_MASK) {
1766 case DRM_MODE_ROTATE_0:
3be5262e 1767 plane_state->rotation = ROTATION_ANGLE_0;
e7b07cee
HW		 1768 break;
1769 case DRM_MODE_ROTATE_90:
3be5262e 1770 plane_state->rotation = ROTATION_ANGLE_90;
e7b07cee
HW		 1771 break;
1772 case DRM_MODE_ROTATE_180:
3be5262e 1773 plane_state->rotation = ROTATION_ANGLE_180;
e7b07cee
HW		 1774 break;
1775 case DRM_MODE_ROTATE_270:
3be5262e 1776 plane_state->rotation = ROTATION_ANGLE_270;
e7b07cee
HW		 1777 break;
1778 default:
3be5262e 1779 plane_state->rotation = ROTATION_ANGLE_0;
e7b07cee
HW		 1780 break;
1781 }
1782
4562236b
HW		 1783 return true;
1784}
3ee6b26b
AD		 1785static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
1786 uint64_t *tiling_flags,
1787 uint64_t *fb_location)
e7b07cee
HW		 1788{
1789 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
1790 int r = amdgpu_bo_reserve(rbo, false);
b830ebc9 1791
e7b07cee 1792 if (unlikely(r)) {
9bbc3031
JZ		 1793 // Don't show error msg. when return -ERESTARTSYS
1794 if (r != -ERESTARTSYS)
1795 DRM_ERROR("Unable to reserve buffer: %d\n", r);
e7b07cee
HW		 1796 return r;
1797 }
1798
1799 if (fb_location)
1800 *fb_location = amdgpu_bo_gpu_offset(rbo);
1801
1802 if (tiling_flags)
1803 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
1804
1805 amdgpu_bo_unreserve(rbo);
1806
1807 return r;
1808}
1809
3ee6b26b
AD		 1810static int fill_plane_attributes_from_fb(struct amdgpu_device *adev,
1811 struct dc_plane_state *plane_state,
1812 const struct amdgpu_framebuffer *amdgpu_fb,
1813 bool addReq)
e7b07cee
HW		 1814{
1815 uint64_t tiling_flags;
1816 uint64_t fb_location = 0;
1817 unsigned int awidth;
1818 const struct drm_framebuffer *fb = &amdgpu_fb->base;
1819 int ret = 0;
1820 struct drm_format_name_buf format_name;
1821
1822 ret = get_fb_info(
1823 amdgpu_fb,
1824 &tiling_flags,
1825 addReq == true ? &fb_location:NULL);
1826
1827 if (ret)
1828 return ret;
1829
1830 switch (fb->format->format) {
1831 case DRM_FORMAT_C8:
3be5262e 1832 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
e7b07cee
HW		 1833 break;
1834 case DRM_FORMAT_RGB565:
3be5262e 1835 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
e7b07cee
HW		 1836 break;
1837 case DRM_FORMAT_XRGB8888:
1838 case DRM_FORMAT_ARGB8888:
3be5262e 1839 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
e7b07cee
HW		 1840 break;
1841 case DRM_FORMAT_XRGB2101010:
1842 case DRM_FORMAT_ARGB2101010:
3be5262e 1843 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
e7b07cee
HW		 1844 break;
1845 case DRM_FORMAT_XBGR2101010:
1846 case DRM_FORMAT_ABGR2101010:
3be5262e 1847 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
e7b07cee
HW		 1848 break;
1849 case DRM_FORMAT_NV21:
3be5262e 1850 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
e7b07cee
HW		 1851 break;
1852 case DRM_FORMAT_NV12:
3be5262e 1853 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
e7b07cee
HW		 1854 break;
1855 default:
1856 DRM_ERROR("Unsupported screen format %s\n",
1ecfc3da 1857 drm_get_format_name(fb->format->format, &format_name));
e7b07cee
HW		 1858 return -EINVAL;
1859 }
1860
3be5262e
HW		 1861 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
1862 plane_state->address.type = PLN_ADDR_TYPE_GRAPHICS;
1863 plane_state->address.grph.addr.low_part = lower_32_bits(fb_location);
1864 plane_state->address.grph.addr.high_part = upper_32_bits(fb_location);
1865 plane_state->plane_size.grph.surface_size.x = 0;
1866 plane_state->plane_size.grph.surface_size.y = 0;
1867 plane_state->plane_size.grph.surface_size.width = fb->width;
1868 plane_state->plane_size.grph.surface_size.height = fb->height;
1869 plane_state->plane_size.grph.surface_pitch =
e7b07cee
HW		 1870 fb->pitches[0] / fb->format->cpp[0];
1871 /* TODO: unhardcode */
3be5262e 1872 plane_state->color_space = COLOR_SPACE_SRGB;
e7b07cee
HW		 1873
1874 } else {
1875 awidth = ALIGN(fb->width, 64);
3be5262e
HW		 1876 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
1877 plane_state->address.video_progressive.luma_addr.low_part
e7b07cee 1878 = lower_32_bits(fb_location);
3be5262e 1879 plane_state->address.video_progressive.chroma_addr.low_part
e7b07cee
HW		 1880 = lower_32_bits(fb_location) +
1881 (awidth * fb->height);
3be5262e
HW		 1882 plane_state->plane_size.video.luma_size.x = 0;
1883 plane_state->plane_size.video.luma_size.y = 0;
1884 plane_state->plane_size.video.luma_size.width = awidth;
1885 plane_state->plane_size.video.luma_size.height = fb->height;
e7b07cee 1886 /* TODO: unhardcode */
3be5262e 1887 plane_state->plane_size.video.luma_pitch = awidth;
e7b07cee 1888
3be5262e
HW		 1889 plane_state->plane_size.video.chroma_size.x = 0;
1890 plane_state->plane_size.video.chroma_size.y = 0;
1891 plane_state->plane_size.video.chroma_size.width = awidth;
1892 plane_state->plane_size.video.chroma_size.height = fb->height;
1893 plane_state->plane_size.video.chroma_pitch = awidth / 2;
e7b07cee
HW		 1894
1895 /* TODO: unhardcode */
3be5262e 1896 plane_state->color_space = COLOR_SPACE_YCBCR709;
e7b07cee
HW		 1897 }
1898
3be5262e 1899 memset(&plane_state->tiling_info, 0, sizeof(plane_state->tiling_info));
e7b07cee 1900
b830ebc9
HW		 1901 /* Fill GFX8 params */
1902 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
1903 unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
e7b07cee
HW		 1904
1905 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1906 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1907 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1908 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1909 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1910
1911 /* XXX fix me for VI */
3be5262e
HW		 1912 plane_state->tiling_info.gfx8.num_banks = num_banks;
1913 plane_state->tiling_info.gfx8.array_mode =
e7b07cee 1914 DC_ARRAY_2D_TILED_THIN1;
3be5262e
HW		 1915 plane_state->tiling_info.gfx8.tile_split = tile_split;
1916 plane_state->tiling_info.gfx8.bank_width = bankw;
1917 plane_state->tiling_info.gfx8.bank_height = bankh;
1918 plane_state->tiling_info.gfx8.tile_aspect = mtaspect;
1919 plane_state->tiling_info.gfx8.tile_mode =
e7b07cee
HW		 1920 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
1921 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
1922 == DC_ARRAY_1D_TILED_THIN1) {
3be5262e 1923 plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
e7b07cee
HW		 1924 }
1925
3be5262e 1926 plane_state->tiling_info.gfx8.pipe_config =
e7b07cee
HW		 1927 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1928
1929 if (adev->asic_type == CHIP_VEGA10 ||
1930 adev->asic_type == CHIP_RAVEN) {
1931 /* Fill GFX9 params */
3be5262e 1932 plane_state->tiling_info.gfx9.num_pipes =
e7b07cee 1933 adev->gfx.config.gb_addr_config_fields.num_pipes;
3be5262e 1934 plane_state->tiling_info.gfx9.num_banks =
e7b07cee 1935 adev->gfx.config.gb_addr_config_fields.num_banks;
3be5262e 1936 plane_state->tiling_info.gfx9.pipe_interleave =
e7b07cee 1937 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
3be5262e 1938 plane_state->tiling_info.gfx9.num_shader_engines =
e7b07cee 1939 adev->gfx.config.gb_addr_config_fields.num_se;
3be5262e 1940 plane_state->tiling_info.gfx9.max_compressed_frags =
e7b07cee 1941 adev->gfx.config.gb_addr_config_fields.max_compress_frags;
3be5262e 1942 plane_state->tiling_info.gfx9.num_rb_per_se =
e7b07cee 1943 adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
3be5262e 1944 plane_state->tiling_info.gfx9.swizzle =
e7b07cee 1945 AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
3be5262e 1946 plane_state->tiling_info.gfx9.shaderEnable = 1;
e7b07cee
HW		 1947 }
1948
3be5262e
HW		 1949 plane_state->visible = true;
1950 plane_state->scaling_quality.h_taps_c = 0;
1951 plane_state->scaling_quality.v_taps_c = 0;
e7b07cee 1952
3be5262e
HW		 1953 /* is this needed? is plane_state zeroed at allocation? */
1954 plane_state->scaling_quality.h_taps = 0;
1955 plane_state->scaling_quality.v_taps = 0;
1956 plane_state->stereo_format = PLANE_STEREO_FORMAT_NONE;
e7b07cee
HW		 1957
1958 return ret;
1959
1960}
1961
3ee6b26b
AD		 1962static void fill_gamma_from_crtc_state(const struct drm_crtc_state *crtc_state,
1963 struct dc_plane_state *plane_state)
e7b07cee
HW		 1964{
1965 int i;
1966 struct dc_gamma *gamma;
d66cf5f5
AK		 1967 struct drm_color_lut *lut =
1968 (struct drm_color_lut *) crtc_state->gamma_lut->data;
e7b07cee
HW		 1969
1970 gamma = dc_create_gamma();
1971
1972 if (gamma == NULL) {
1973 WARN_ON(1);
1974 return;
1975 }
1976
7483bed4
HW		 1977 gamma->type = GAMMA_RGB_256;
1978 gamma->num_entries = GAMMA_RGB_256_ENTRIES;
d66cf5f5
AK		 1979 for (i = 0; i < GAMMA_RGB_256_ENTRIES; i++) {
1980 gamma->entries.red[i] = dal_fixed31_32_from_int(lut[i].red);
1981 gamma->entries.green[i] = dal_fixed31_32_from_int(lut[i].green);
1982 gamma->entries.blue[i] = dal_fixed31_32_from_int(lut[i].blue);
e7b07cee
HW		 1983 }
1984
3be5262e 1985 plane_state->gamma_correction = gamma;
e7b07cee
HW		 1986}
1987
3ee6b26b
AD		 1988static int fill_plane_attributes(struct amdgpu_device *adev,
1989 struct dc_plane_state *dc_plane_state,
1990 struct drm_plane_state *plane_state,
1991 struct drm_crtc_state *crtc_state,
1992 bool addrReq)
e7b07cee
HW		 1993{
1994 const struct amdgpu_framebuffer *amdgpu_fb =
1995 to_amdgpu_framebuffer(plane_state->fb);
1996 const struct drm_crtc *crtc = plane_state->crtc;
1997 struct dc_transfer_func *input_tf;
1998 int ret = 0;
1999
3be5262e 2000 if (!fill_rects_from_plane_state(plane_state, dc_plane_state))
e7b07cee
HW		 2001 return -EINVAL;
2002
2003 ret = fill_plane_attributes_from_fb(
2004 crtc->dev->dev_private,
3be5262e 2005 dc_plane_state,
e7b07cee
HW		 2006 amdgpu_fb,
2007 addrReq);
2008
2009 if (ret)
2010 return ret;
2011
2012 input_tf = dc_create_transfer_func();
2013
2014 if (input_tf == NULL)
2015 return -ENOMEM;
2016
2017 input_tf->type = TF_TYPE_PREDEFINED;
2018 input_tf->tf = TRANSFER_FUNCTION_SRGB;
2019
3be5262e 2020 dc_plane_state->in_transfer_func = input_tf;
e7b07cee
HW		 2021
2022 /* In case of gamma set, update gamma value */
2023 if (crtc_state->gamma_lut)
3be5262e 2024 fill_gamma_from_crtc_state(crtc_state, dc_plane_state);
e7b07cee
HW		 2025
2026 return ret;
2027}
2028
2029/*****************************************************************************/
2030
3ee6b26b
AD		 2031static void update_stream_scaling_settings(const struct drm_display_mode *mode,
2032 const struct dm_connector_state *dm_state,
2033 struct dc_stream_state *stream)
e7b07cee
HW		 2034{
2035 enum amdgpu_rmx_type rmx_type;
2036
2037 struct rect src = { 0 }; /* viewport in composition space*/
2038 struct rect dst = { 0 }; /* stream addressable area */
2039
2040 /* no mode. nothing to be done */
2041 if (!mode)
2042 return;
2043
2044 /* Full screen scaling by default */
2045 src.width = mode->hdisplay;
2046 src.height = mode->vdisplay;
2047 dst.width = stream->timing.h_addressable;
2048 dst.height = stream->timing.v_addressable;
2049
2050 rmx_type = dm_state->scaling;
2051 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
2052 if (src.width * dst.height <
2053 src.height * dst.width) {
2054 /* height needs less upscaling/more downscaling */
2055 dst.width = src.width *
2056 dst.height / src.height;
2057 } else {
2058 /* width needs less upscaling/more downscaling */
2059 dst.height = src.height *
2060 dst.width / src.width;
2061 }
2062 } else if (rmx_type == RMX_CENTER) {
2063 dst = src;
2064 }
2065
2066 dst.x = (stream->timing.h_addressable - dst.width) / 2;
2067 dst.y = (stream->timing.v_addressable - dst.height) / 2;
2068
2069 if (dm_state->underscan_enable) {
2070 dst.x += dm_state->underscan_hborder / 2;
2071 dst.y += dm_state->underscan_vborder / 2;
2072 dst.width -= dm_state->underscan_hborder;
2073 dst.height -= dm_state->underscan_vborder;
2074 }
2075
2076 stream->src = src;
2077 stream->dst = dst;
2078
f1ad2f5e 2079 DRM_DEBUG_DRIVER("Destination Rectangle x:%d y:%d width:%d height:%d\n",
e7b07cee
HW		 2080 dst.x, dst.y, dst.width, dst.height);
2081
2082}
2083
3ee6b26b
AD		 2084static enum dc_color_depth
2085convert_color_depth_from_display_info(const struct drm_connector *connector)
e7b07cee
HW		 2086{
2087 uint32_t bpc = connector->display_info.bpc;
2088
2089 /* Limited color depth to 8bit
b830ebc9
HW		 2090 * TODO: Still need to handle deep color
2091 */
e7b07cee
HW		 2092 if (bpc > 8)
2093 bpc = 8;
2094
2095 switch (bpc) {
2096 case 0:
2097 /* Temporary Work around, DRM don't parse color depth for
2098 * EDID revision before 1.4
2099 * TODO: Fix edid parsing
2100 */
2101 return COLOR_DEPTH_888;
2102 case 6:
2103 return COLOR_DEPTH_666;
2104 case 8:
2105 return COLOR_DEPTH_888;
2106 case 10:
2107 return COLOR_DEPTH_101010;
2108 case 12:
2109 return COLOR_DEPTH_121212;
2110 case 14:
2111 return COLOR_DEPTH_141414;
2112 case 16:
2113 return COLOR_DEPTH_161616;
2114 default:
2115 return COLOR_DEPTH_UNDEFINED;
2116 }
2117}
2118
3ee6b26b
AD		 2119static enum dc_aspect_ratio
2120get_aspect_ratio(const struct drm_display_mode *mode_in)
e7b07cee
HW		 2121{
2122 int32_t width = mode_in->crtc_hdisplay * 9;
2123 int32_t height = mode_in->crtc_vdisplay * 16;
b830ebc9 2124
e7b07cee
HW		 2125 if ((width - height) < 10 && (width - height) > -10)
2126 return ASPECT_RATIO_16_9;
2127 else
2128 return ASPECT_RATIO_4_3;
2129}
2130
3ee6b26b
AD		 2131static enum dc_color_space
2132get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
e7b07cee
HW		 2133{
2134 enum dc_color_space color_space = COLOR_SPACE_SRGB;
2135
2136 switch (dc_crtc_timing->pixel_encoding) {
2137 case PIXEL_ENCODING_YCBCR422:
2138 case PIXEL_ENCODING_YCBCR444:
2139 case PIXEL_ENCODING_YCBCR420:
2140 {
2141 /*
2142 * 27030khz is the separation point between HDTV and SDTV
2143 * according to HDMI spec, we use YCbCr709 and YCbCr601
2144 * respectively
2145 */
2146 if (dc_crtc_timing->pix_clk_khz > 27030) {
2147 if (dc_crtc_timing->flags.Y_ONLY)
2148 color_space =
2149 COLOR_SPACE_YCBCR709_LIMITED;
2150 else
2151 color_space = COLOR_SPACE_YCBCR709;
2152 } else {
2153 if (dc_crtc_timing->flags.Y_ONLY)
2154 color_space =
2155 COLOR_SPACE_YCBCR601_LIMITED;
2156 else
2157 color_space = COLOR_SPACE_YCBCR601;
2158 }
2159
2160 }
2161 break;
2162 case PIXEL_ENCODING_RGB:
2163 color_space = COLOR_SPACE_SRGB;
2164 break;
2165
2166 default:
2167 WARN_ON(1);
2168 break;
2169 }
2170
2171 return color_space;
2172}
2173
2174/*****************************************************************************/
2175
3ee6b26b
AD		 2176static void
2177fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream,
2178 const struct drm_display_mode *mode_in,
2179 const struct drm_connector *connector)
e7b07cee
HW		 2180{
2181 struct dc_crtc_timing *timing_out = &stream->timing;
b830ebc9 2182
e7b07cee
HW		 2183 memset(timing_out, 0, sizeof(struct dc_crtc_timing));
2184
2185 timing_out->h_border_left = 0;
2186 timing_out->h_border_right = 0;
2187 timing_out->v_border_top = 0;
2188 timing_out->v_border_bottom = 0;
2189 /* TODO: un-hardcode */
2190
2191 if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
2192 && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
2193 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
2194 else
2195 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
2196
2197 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
2198 timing_out->display_color_depth = convert_color_depth_from_display_info(
2199 connector);
2200 timing_out->scan_type = SCANNING_TYPE_NODATA;
2201 timing_out->hdmi_vic = 0;
2202 timing_out->vic = drm_match_cea_mode(mode_in);
2203
2204 timing_out->h_addressable = mode_in->crtc_hdisplay;
2205 timing_out->h_total = mode_in->crtc_htotal;
2206 timing_out->h_sync_width =
2207 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
2208 timing_out->h_front_porch =
2209 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
2210 timing_out->v_total = mode_in->crtc_vtotal;
2211 timing_out->v_addressable = mode_in->crtc_vdisplay;
2212 timing_out->v_front_porch =
2213 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
2214 timing_out->v_sync_width =
2215 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
2216 timing_out->pix_clk_khz = mode_in->crtc_clock;
2217 timing_out->aspect_ratio = get_aspect_ratio(mode_in);
2218 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
2219 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
2220 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
2221 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
2222
2223 stream->output_color_space = get_output_color_space(timing_out);
2224
2225 {
2226 struct dc_transfer_func *tf = dc_create_transfer_func();
b830ebc9 2227
e7b07cee
HW		 2228 tf->type = TF_TYPE_PREDEFINED;
2229 tf->tf = TRANSFER_FUNCTION_SRGB;
2230 stream->out_transfer_func = tf;
2231 }
2232}
2233
3ee6b26b
AD		 2234static void fill_audio_info(struct audio_info *audio_info,
2235 const struct drm_connector *drm_connector,
2236 const struct dc_sink *dc_sink)
e7b07cee
HW		 2237{
2238 int i = 0;
2239 int cea_revision = 0;
2240 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
2241
2242 audio_info->manufacture_id = edid_caps->manufacturer_id;
2243 audio_info->product_id = edid_caps->product_id;
2244
2245 cea_revision = drm_connector->display_info.cea_rev;
2246
2247 while (i < AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS &&
2248 edid_caps->display_name[i]) {
2249 audio_info->display_name[i] = edid_caps->display_name[i];
2250 i++;
2251 }
2252
b830ebc9 2253 if (cea_revision >= 3) {
e7b07cee
HW		 2254 audio_info->mode_count = edid_caps->audio_mode_count;
2255
2256 for (i = 0; i < audio_info->mode_count; ++i) {
2257 audio_info->modes[i].format_code =
2258 (enum audio_format_code)
2259 (edid_caps->audio_modes[i].format_code);
2260 audio_info->modes[i].channel_count =
2261 edid_caps->audio_modes[i].channel_count;
2262 audio_info->modes[i].sample_rates.all =
2263 edid_caps->audio_modes[i].sample_rate;
2264 audio_info->modes[i].sample_size =
2265 edid_caps->audio_modes[i].sample_size;
2266 }
2267 }
2268
2269 audio_info->flags.all = edid_caps->speaker_flags;
2270
2271 /* TODO: We only check for the progressive mode, check for interlace mode too */
b830ebc9 2272 if (drm_connector->latency_present[0]) {
e7b07cee
HW		 2273 audio_info->video_latency = drm_connector->video_latency[0];
2274 audio_info->audio_latency = drm_connector->audio_latency[0];
2275 }
2276
2277 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
2278
2279}
2280
3ee6b26b
AD		 2281static void
2282copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
2283 struct drm_display_mode *dst_mode)
e7b07cee
HW		 2284{
2285 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
2286 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
2287 dst_mode->crtc_clock = src_mode->crtc_clock;
2288 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
2289 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
b830ebc9 2290 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start;
e7b07cee
HW		 2291 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
2292 dst_mode->crtc_htotal = src_mode->crtc_htotal;
2293 dst_mode->crtc_hskew = src_mode->crtc_hskew;
2294 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
2295 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
2296 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
2297 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
2298 dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
2299}
2300
3ee6b26b
AD		 2301static void
2302decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
2303 const struct drm_display_mode *native_mode,
2304 bool scale_enabled)
e7b07cee
HW		 2305{
2306 if (scale_enabled) {
2307 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2308 } else if (native_mode->clock == drm_mode->clock &&
2309 native_mode->htotal == drm_mode->htotal &&
2310 native_mode->vtotal == drm_mode->vtotal) {
2311 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2312 } else {
2313 /* no scaling nor amdgpu inserted, no need to patch */
2314 }
2315}
2316
2e0ac3d6
HW		 2317static void create_fake_sink(struct amdgpu_dm_connector *aconnector)
2318{
2319 struct dc_sink *sink = NULL;
2320 struct dc_sink_init_data sink_init_data = { 0 };
2321
2322 sink_init_data.link = aconnector->dc_link;
2323 sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
2324
2325 sink = dc_sink_create(&sink_init_data);
2326 if (!sink)
2327 DRM_ERROR("Failed to create sink!\n");
2328
2329 sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
2330 aconnector->fake_enable = true;
2331
2332 aconnector->dc_sink = sink;
2333 aconnector->dc_link->local_sink = sink;
2334}
2335
3ee6b26b
AD		 2336static struct dc_stream_state *
2337create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
2338 const struct drm_display_mode *drm_mode,
2339 const struct dm_connector_state *dm_state)
e7b07cee
HW		 2340{
2341 struct drm_display_mode *preferred_mode = NULL;
2342 const struct drm_connector *drm_connector;
0971c40e 2343 struct dc_stream_state *stream = NULL;
e7b07cee
HW		 2344 struct drm_display_mode mode = *drm_mode;
2345 bool native_mode_found = false;
2346
b830ebc9 2347 if (aconnector == NULL) {
e7b07cee
HW		 2348 DRM_ERROR("aconnector is NULL!\n");
2349 goto drm_connector_null;
2350 }
2351
b830ebc9 2352 if (dm_state == NULL) {
e7b07cee
HW		 2353 DRM_ERROR("dm_state is NULL!\n");
2354 goto dm_state_null;
2355 }
4562236b 2356
e7b07cee 2357 drm_connector = &aconnector->base;
2e0ac3d6 2358
f4ac176e
JZ		 2359 if (!aconnector->dc_sink) {
2360 /*
2361 * Exclude MST from creating fake_sink
2362 * TODO: need to enable MST into fake_sink feature
2363 */
2364 if (aconnector->mst_port)
2365 goto stream_create_fail;
2366
2e0ac3d6 2367 create_fake_sink(aconnector);
f4ac176e 2368 }
2e0ac3d6 2369
e7b07cee 2370 stream = dc_create_stream_for_sink(aconnector->dc_sink);
4562236b 2371
b830ebc9 2372 if (stream == NULL) {
e7b07cee
HW		 2373 DRM_ERROR("Failed to create stream for sink!\n");
2374 goto stream_create_fail;
2375 }
2376
2377 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
2378 /* Search for preferred mode */
2379 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
2380 native_mode_found = true;
2381 break;
2382 }
2383 }
2384 if (!native_mode_found)
2385 preferred_mode = list_first_entry_or_null(
2386 &aconnector->base.modes,
2387 struct drm_display_mode,
2388 head);
2389
b830ebc9 2390 if (preferred_mode == NULL) {
e7b07cee
HW		 2391 /* This may not be an error, the use case is when we we have no
2392 * usermode calls to reset and set mode upon hotplug. In this
2393 * case, we call set mode ourselves to restore the previous mode
2394 * and the modelist may not be filled in in time.
2395 */
f1ad2f5e 2396 DRM_DEBUG_DRIVER("No preferred mode found\n");
e7b07cee
HW		 2397 } else {
2398 decide_crtc_timing_for_drm_display_mode(
2399 &mode, preferred_mode,
2400 dm_state->scaling != RMX_OFF);
2401 }
2402
2403 fill_stream_properties_from_drm_display_mode(stream,
2404 &mode, &aconnector->base);
2405 update_stream_scaling_settings(&mode, dm_state, stream);
2406
2407 fill_audio_info(
2408 &stream->audio_info,
2409 drm_connector,
2410 aconnector->dc_sink);
2411
2412stream_create_fail:
2413dm_state_null:
2414drm_connector_null:
2415 return stream;
2416}
2417
7578ecda 2418static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
e7b07cee
HW		 2419{
2420 drm_crtc_cleanup(crtc);
2421 kfree(crtc);
2422}
2423
2424static void dm_crtc_destroy_state(struct drm_crtc *crtc,
3ee6b26b 2425 struct drm_crtc_state *state)
e7b07cee
HW		 2426{
2427 struct dm_crtc_state *cur = to_dm_crtc_state(state);
2428
2429 /* TODO Destroy dc_stream objects are stream object is flattened */
2430 if (cur->stream)
2431 dc_stream_release(cur->stream);
2432
2433
2434 __drm_atomic_helper_crtc_destroy_state(state);
2435
2436
2437 kfree(state);
2438}
2439
2440static void dm_crtc_reset_state(struct drm_crtc *crtc)
2441{
2442 struct dm_crtc_state *state;
2443
2444 if (crtc->state)
2445 dm_crtc_destroy_state(crtc, crtc->state);
2446
2447 state = kzalloc(sizeof(*state), GFP_KERNEL);
2448 if (WARN_ON(!state))
2449 return;
2450
2451 crtc->state = &state->base;
2452 crtc->state->crtc = crtc;
2453
2454}
2455
2456static struct drm_crtc_state *
2457dm_crtc_duplicate_state(struct drm_crtc *crtc)
2458{
2459 struct dm_crtc_state *state, *cur;
2460
2461 cur = to_dm_crtc_state(crtc->state);
2462
2463 if (WARN_ON(!crtc->state))
2464 return NULL;
2465
2004f45e 2466 state = kzalloc(sizeof(*state), GFP_KERNEL);
e7b07cee
HW		 2467
2468 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
2469
2470 if (cur->stream) {
2471 state->stream = cur->stream;
2472 dc_stream_retain(state->stream);
2473 }
2474
2475 /* TODO Duplicate dc_stream after objects are stream object is flattened */
2476
2477 return &state->base;
2478}
2479
2480/* Implemented only the options currently availible for the driver */
2481static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
2482 .reset = dm_crtc_reset_state,
2483 .destroy = amdgpu_dm_crtc_destroy,
2484 .gamma_set = drm_atomic_helper_legacy_gamma_set,
2485 .set_config = drm_atomic_helper_set_config,
2486 .page_flip = drm_atomic_helper_page_flip,
2487 .atomic_duplicate_state = dm_crtc_duplicate_state,
2488 .atomic_destroy_state = dm_crtc_destroy_state,
2489};
2490
2491static enum drm_connector_status
2492amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
2493{
2494 bool connected;
c84dec2f 2495 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 2496
2497 /* Notes:
2498 * 1. This interface is NOT called in context of HPD irq.
2499 * 2. This interface *is called* in context of user-mode ioctl. Which
2500 * makes it a bad place for *any* MST-related activit. */
2501
8580d60b
HW		 2502 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
2503 !aconnector->fake_enable)
e7b07cee
HW		 2504 connected = (aconnector->dc_sink != NULL);
2505 else
2506 connected = (aconnector->base.force == DRM_FORCE_ON);
2507
2508 return (connected ? connector_status_connected :
2509 connector_status_disconnected);
2510}
2511
3ee6b26b
AD		 2512int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
2513 struct drm_connector_state *connector_state,
2514 struct drm_property *property,
2515 uint64_t val)
e7b07cee
HW		 2516{
2517 struct drm_device *dev = connector->dev;
2518 struct amdgpu_device *adev = dev->dev_private;
2519 struct dm_connector_state *dm_old_state =
2520 to_dm_connector_state(connector->state);
2521 struct dm_connector_state *dm_new_state =
2522 to_dm_connector_state(connector_state);
2523
2524 int ret = -EINVAL;
2525
2526 if (property == dev->mode_config.scaling_mode_property) {
2527 enum amdgpu_rmx_type rmx_type;
2528
2529 switch (val) {
2530 case DRM_MODE_SCALE_CENTER:
2531 rmx_type = RMX_CENTER;
2532 break;
2533 case DRM_MODE_SCALE_ASPECT:
2534 rmx_type = RMX_ASPECT;
2535 break;
2536 case DRM_MODE_SCALE_FULLSCREEN:
2537 rmx_type = RMX_FULL;
2538 break;
2539 case DRM_MODE_SCALE_NONE:
2540 default:
2541 rmx_type = RMX_OFF;
2542 break;
2543 }
2544
2545 if (dm_old_state->scaling == rmx_type)
2546 return 0;
2547
2548 dm_new_state->scaling = rmx_type;
2549 ret = 0;
2550 } else if (property == adev->mode_info.underscan_hborder_property) {
2551 dm_new_state->underscan_hborder = val;
2552 ret = 0;
2553 } else if (property == adev->mode_info.underscan_vborder_property) {
2554 dm_new_state->underscan_vborder = val;
2555 ret = 0;
2556 } else if (property == adev->mode_info.underscan_property) {
2557 dm_new_state->underscan_enable = val;
2558 ret = 0;
2559 }
2560
2561 return ret;
2562}
2563
3ee6b26b
AD		 2564int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
2565 const struct drm_connector_state *state,
2566 struct drm_property *property,
2567 uint64_t *val)
e7b07cee
HW		 2568{
2569 struct drm_device *dev = connector->dev;
2570 struct amdgpu_device *adev = dev->dev_private;
2571 struct dm_connector_state *dm_state =
2572 to_dm_connector_state(state);
2573 int ret = -EINVAL;
2574
2575 if (property == dev->mode_config.scaling_mode_property) {
2576 switch (dm_state->scaling) {
2577 case RMX_CENTER:
2578 *val = DRM_MODE_SCALE_CENTER;
2579 break;
2580 case RMX_ASPECT:
2581 *val = DRM_MODE_SCALE_ASPECT;
2582 break;
2583 case RMX_FULL:
2584 *val = DRM_MODE_SCALE_FULLSCREEN;
2585 break;
2586 case RMX_OFF:
2587 default:
2588 *val = DRM_MODE_SCALE_NONE;
2589 break;
2590 }
2591 ret = 0;
2592 } else if (property == adev->mode_info.underscan_hborder_property) {
2593 *val = dm_state->underscan_hborder;
2594 ret = 0;
2595 } else if (property == adev->mode_info.underscan_vborder_property) {
2596 *val = dm_state->underscan_vborder;
2597 ret = 0;
2598 } else if (property == adev->mode_info.underscan_property) {
2599 *val = dm_state->underscan_enable;
2600 ret = 0;
2601 }
2602 return ret;
2603}
2604
7578ecda 2605static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
e7b07cee 2606{
c84dec2f 2607 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 2608 const struct dc_link *link = aconnector->dc_link;
2609 struct amdgpu_device *adev = connector->dev->dev_private;
2610 struct amdgpu_display_manager *dm = &adev->dm;
2611#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
2612 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
2613
2614 if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) {
2615 amdgpu_dm_register_backlight_device(dm);
2616
2617 if (dm->backlight_dev) {
2618 backlight_device_unregister(dm->backlight_dev);
2619 dm->backlight_dev = NULL;
2620 }
2621
2622 }
2623#endif
2624 drm_connector_unregister(connector);
2625 drm_connector_cleanup(connector);
2626 kfree(connector);
2627}
2628
2629void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
2630{
2631 struct dm_connector_state *state =
2632 to_dm_connector_state(connector->state);
2633
2634 kfree(state);
2635
2636 state = kzalloc(sizeof(*state), GFP_KERNEL);
2637
2638 if (state) {
2639 state->scaling = RMX_OFF;
2640 state->underscan_enable = false;
2641 state->underscan_hborder = 0;
2642 state->underscan_vborder = 0;
2643
2644 connector->state = &state->base;
2645 connector->state->connector = connector;
2646 }
2647}
2648
3ee6b26b
AD		 2649struct drm_connector_state *
2650amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
e7b07cee
HW		 2651{
2652 struct dm_connector_state *state =
2653 to_dm_connector_state(connector->state);
2654
2655 struct dm_connector_state *new_state =
2656 kmemdup(state, sizeof(*state), GFP_KERNEL);
2657
2658 if (new_state) {
2659 __drm_atomic_helper_connector_duplicate_state(connector,
1ecfc3da 2660 &new_state->base);
e7b07cee
HW		 2661 return &new_state->base;
2662 }
2663
2664 return NULL;
2665}
2666
2667static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
2668 .reset = amdgpu_dm_connector_funcs_reset,
2669 .detect = amdgpu_dm_connector_detect,
2670 .fill_modes = drm_helper_probe_single_connector_modes,
2671 .destroy = amdgpu_dm_connector_destroy,
2672 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
2673 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2674 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
2675 .atomic_get_property = amdgpu_dm_connector_atomic_get_property
2676};
2677
2678static struct drm_encoder *best_encoder(struct drm_connector *connector)
2679{
2680 int enc_id = connector->encoder_ids[0];
2681 struct drm_mode_object *obj;
2682 struct drm_encoder *encoder;
2683
f1ad2f5e 2684 DRM_DEBUG_DRIVER("Finding the best encoder\n");
e7b07cee
HW		 2685
2686 /* pick the encoder ids */
2687 if (enc_id) {
bd21a37d 2688 obj = drm_mode_object_find(connector->dev, NULL, enc_id, DRM_MODE_OBJECT_ENCODER);
e7b07cee
HW		 2689 if (!obj) {
2690 DRM_ERROR("Couldn't find a matching encoder for our connector\n");
2691 return NULL;
2692 }
2693 encoder = obj_to_encoder(obj);
2694 return encoder;
2695 }
2696 DRM_ERROR("No encoder id\n");
2697 return NULL;
2698}
2699
2700static int get_modes(struct drm_connector *connector)
2701{
2702 return amdgpu_dm_connector_get_modes(connector);
2703}
2704
c84dec2f 2705static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 2706{
2707 struct dc_sink_init_data init_params = {
2708 .link = aconnector->dc_link,
2709 .sink_signal = SIGNAL_TYPE_VIRTUAL
2710 };
2711 struct edid *edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
2712
2713 if (!aconnector->base.edid_blob_ptr ||
2714 !aconnector->base.edid_blob_ptr->data) {
2715 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
2716 aconnector->base.name);
2717
2718 aconnector->base.force = DRM_FORCE_OFF;
2719 aconnector->base.override_edid = false;
2720 return;
2721 }
2722
2723 aconnector->edid = edid;
2724
2725 aconnector->dc_em_sink = dc_link_add_remote_sink(
2726 aconnector->dc_link,
2727 (uint8_t *)edid,
2728 (edid->extensions + 1) * EDID_LENGTH,
2729 &init_params);
2730
2731 if (aconnector->base.force
2732 == DRM_FORCE_ON)
2733 aconnector->dc_sink = aconnector->dc_link->local_sink ?
2734 aconnector->dc_link->local_sink :
2735 aconnector->dc_em_sink;
2736}
2737
c84dec2f 2738static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 2739{
2740 struct dc_link *link = (struct dc_link *)aconnector->dc_link;
2741
2742 /* In case of headless boot with force on for DP managed connector
2743 * Those settings have to be != 0 to get initial modeset
2744 */
2745 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
2746 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
2747 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
2748 }
2749
2750
2751 aconnector->base.override_edid = true;
2752 create_eml_sink(aconnector);
2753}
2754
3ee6b26b
AD		 2755int amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
2756 struct drm_display_mode *mode)
e7b07cee
HW		 2757{
2758 int result = MODE_ERROR;
2759 struct dc_sink *dc_sink;
2760 struct amdgpu_device *adev = connector->dev->dev_private;
2761 /* TODO: Unhardcode stream count */
0971c40e 2762 struct dc_stream_state *stream;
c84dec2f 2763 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 2764
2765 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
2766 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
2767 return result;
2768
2769 /* Only run this the first time mode_valid is called to initilialize
2770 * EDID mgmt
2771 */
2772 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
2773 !aconnector->dc_em_sink)
2774 handle_edid_mgmt(aconnector);
2775
c84dec2f 2776 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
e7b07cee 2777
b830ebc9 2778 if (dc_sink == NULL) {
e7b07cee
HW		 2779 DRM_ERROR("dc_sink is NULL!\n");
2780 goto fail;
2781 }
2782
2783 stream = dc_create_stream_for_sink(dc_sink);
b830ebc9 2784 if (stream == NULL) {
e7b07cee
HW		 2785 DRM_ERROR("Failed to create stream for sink!\n");
2786 goto fail;
2787 }
2788
2789 drm_mode_set_crtcinfo(mode, 0);
2790 fill_stream_properties_from_drm_display_mode(stream, mode, connector);
2791
2792 stream->src.width = mode->hdisplay;
2793 stream->src.height = mode->vdisplay;
2794 stream->dst = stream->src;
2795
62c933f9 2796 if (dc_validate_stream(adev->dm.dc, stream) == DC_OK)
e7b07cee
HW		 2797 result = MODE_OK;
2798
2799 dc_stream_release(stream);
2800
2801fail:
2802 /* TODO: error handling*/
2803 return result;
2804}
2805
2806static const struct drm_connector_helper_funcs
2807amdgpu_dm_connector_helper_funcs = {
2808 /*
b830ebc9
HW		 2809 * If hotplug a second bigger display in FB Con mode, bigger resolution
2810 * modes will be filtered by drm_mode_validate_size(), and those modes
2811 * is missing after user start lightdm. So we need to renew modes list.
2812 * in get_modes call back, not just return the modes count
2813 */
e7b07cee
HW		 2814 .get_modes = get_modes,
2815 .mode_valid = amdgpu_dm_connector_mode_valid,
2816 .best_encoder = best_encoder
2817};
2818
2819static void dm_crtc_helper_disable(struct drm_crtc *crtc)
2820{
2821}
2822
3ee6b26b
AD		 2823static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
2824 struct drm_crtc_state *state)
e7b07cee
HW		 2825{
2826 struct amdgpu_device *adev = crtc->dev->dev_private;
2827 struct dc *dc = adev->dm.dc;
2828 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state);
2829 int ret = -EINVAL;
2830
9b690ef3
BL		 2831 if (unlikely(!dm_crtc_state->stream &&
2832 modeset_required(state, NULL, dm_crtc_state->stream))) {
e7b07cee
HW		 2833 WARN_ON(1);
2834 return ret;
2835 }
2836
2837 /* In some use cases, like reset, no stream is attached */
2838 if (!dm_crtc_state->stream)
2839 return 0;
2840
62c933f9 2841 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
e7b07cee
HW		 2842 return 0;
2843
2844 return ret;
2845}
2846
3ee6b26b
AD		 2847static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
2848 const struct drm_display_mode *mode,
2849 struct drm_display_mode *adjusted_mode)
e7b07cee
HW		 2850{
2851 return true;
2852}
2853
2854static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
2855 .disable = dm_crtc_helper_disable,
2856 .atomic_check = dm_crtc_helper_atomic_check,
2857 .mode_fixup = dm_crtc_helper_mode_fixup
2858};
2859
2860static void dm_encoder_helper_disable(struct drm_encoder *encoder)
2861{
2862
2863}
2864
3ee6b26b
AD		 2865static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
2866 struct drm_crtc_state *crtc_state,
2867 struct drm_connector_state *conn_state)
e7b07cee
HW		 2868{
2869 return 0;
2870}
2871
2872const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
2873 .disable = dm_encoder_helper_disable,
2874 .atomic_check = dm_encoder_helper_atomic_check
2875};
2876
2877static void dm_drm_plane_reset(struct drm_plane *plane)
2878{
2879 struct dm_plane_state *amdgpu_state = NULL;
2880
2881 if (plane->state)
2882 plane->funcs->atomic_destroy_state(plane, plane->state);
2883
2884 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
2885
2886 if (amdgpu_state) {
2887 plane->state = &amdgpu_state->base;
2888 plane->state->plane = plane;
2889 plane->state->rotation = DRM_MODE_ROTATE_0;
2890 } else
2891 WARN_ON(1);
2892}
2893
2894static struct drm_plane_state *
2895dm_drm_plane_duplicate_state(struct drm_plane *plane)
2896{
2897 struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
2898
2899 old_dm_plane_state = to_dm_plane_state(plane->state);
2900 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
2901 if (!dm_plane_state)
2902 return NULL;
2903
2904 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
2905
3be5262e
HW		 2906 if (old_dm_plane_state->dc_state) {
2907 dm_plane_state->dc_state = old_dm_plane_state->dc_state;
2908 dc_plane_state_retain(dm_plane_state->dc_state);
e7b07cee
HW		 2909 }
2910
2911 return &dm_plane_state->base;
2912}
2913
2914void dm_drm_plane_destroy_state(struct drm_plane *plane,
3ee6b26b 2915 struct drm_plane_state *state)
e7b07cee
HW		 2916{
2917 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
2918
3be5262e
HW		 2919 if (dm_plane_state->dc_state)
2920 dc_plane_state_release(dm_plane_state->dc_state);
e7b07cee 2921
0627bbd3 2922 drm_atomic_helper_plane_destroy_state(plane, state);
e7b07cee
HW		 2923}
2924
2925static const struct drm_plane_funcs dm_plane_funcs = {
2926 .update_plane = drm_atomic_helper_update_plane,
2927 .disable_plane = drm_atomic_helper_disable_plane,
2928 .destroy = drm_plane_cleanup,
2929 .reset = dm_drm_plane_reset,
2930 .atomic_duplicate_state = dm_drm_plane_duplicate_state,
2931 .atomic_destroy_state = dm_drm_plane_destroy_state,
2932};
2933
3ee6b26b
AD		 2934static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
2935 struct drm_plane_state *new_state)
e7b07cee
HW		 2936{
2937 struct amdgpu_framebuffer *afb;
2938 struct drm_gem_object *obj;
2939 struct amdgpu_bo *rbo;
2940 int r;
2941 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
2942 unsigned int awidth;
2943
2944 dm_plane_state_old = to_dm_plane_state(plane->state);
2945 dm_plane_state_new = to_dm_plane_state(new_state);
2946
2947 if (!new_state->fb) {
f1ad2f5e 2948 DRM_DEBUG_DRIVER("No FB bound\n");
e7b07cee
HW		 2949 return 0;
2950 }
2951
2952 afb = to_amdgpu_framebuffer(new_state->fb);
2953
2954 obj = afb->obj;
2955 rbo = gem_to_amdgpu_bo(obj);
2956 r = amdgpu_bo_reserve(rbo, false);
2957 if (unlikely(r != 0))
2958 return r;
2959
2960 r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &afb->address);
2961
2962
2963 amdgpu_bo_unreserve(rbo);
2964
2965 if (unlikely(r != 0)) {
2966 DRM_ERROR("Failed to pin framebuffer\n");
2967 return r;
2968 }
2969
2970 amdgpu_bo_ref(rbo);
2971
3be5262e
HW		 2972 if (dm_plane_state_new->dc_state &&
2973 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
2974 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;
e7b07cee 2975
3be5262e
HW		 2976 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
2977 plane_state->address.grph.addr.low_part = lower_32_bits(afb->address);
2978 plane_state->address.grph.addr.high_part = upper_32_bits(afb->address);
e7b07cee
HW		 2979 } else {
2980 awidth = ALIGN(new_state->fb->width, 64);
3be5262e 2981 plane_state->address.video_progressive.luma_addr.low_part
e7b07cee 2982 = lower_32_bits(afb->address);
3be5262e 2983 plane_state->address.video_progressive.chroma_addr.low_part
e7b07cee
HW		 2984 = lower_32_bits(afb->address) +
2985 (awidth * new_state->fb->height);
2986 }
2987 }
2988
2989 /* It's a hack for s3 since in 4.9 kernel filter out cursor buffer
2990 * prepare and cleanup in drm_atomic_helper_prepare_planes
2991 * and drm_atomic_helper_cleanup_planes because fb doens't in s3.
2992 * IN 4.10 kernel this code should be removed and amdgpu_device_suspend
2993 * code touching fram buffers should be avoided for DC.
2994 */
2995 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
2996 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_state->crtc);
2997
2998 acrtc->cursor_bo = obj;
2999 }
3000 return 0;
3001}
3002
3ee6b26b
AD		 3003static void dm_plane_helper_cleanup_fb(struct drm_plane *plane,
3004 struct drm_plane_state *old_state)
e7b07cee
HW		 3005{
3006 struct amdgpu_bo *rbo;
3007 struct amdgpu_framebuffer *afb;
3008 int r;
3009
3010 if (!old_state->fb)
3011 return;
3012
3013 afb = to_amdgpu_framebuffer(old_state->fb);
3014 rbo = gem_to_amdgpu_bo(afb->obj);
3015 r = amdgpu_bo_reserve(rbo, false);
3016 if (unlikely(r)) {
3017 DRM_ERROR("failed to reserve rbo before unpin\n");
3018 return;
b830ebc9
HW		 3019 }
3020
3021 amdgpu_bo_unpin(rbo);
3022 amdgpu_bo_unreserve(rbo);
3023 amdgpu_bo_unref(&rbo);
e7b07cee
HW		 3024}
3025
7578ecda
AD		 3026static int dm_plane_atomic_check(struct drm_plane *plane,
3027 struct drm_plane_state *state)
cbd19488
AG		 3028{
3029 struct amdgpu_device *adev = plane->dev->dev_private;
3030 struct dc *dc = adev->dm.dc;
3031 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
3032
3be5262e 3033 if (!dm_plane_state->dc_state)
9a3329b1 3034 return 0;
cbd19488 3035
62c933f9 3036 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
cbd19488
AG		 3037 return 0;
3038
3039 return -EINVAL;
3040}
3041
e7b07cee
HW		 3042static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
3043 .prepare_fb = dm_plane_helper_prepare_fb,
3044 .cleanup_fb = dm_plane_helper_cleanup_fb,
cbd19488 3045 .atomic_check = dm_plane_atomic_check,
e7b07cee
HW		 3046};
3047
3048/*
3049 * TODO: these are currently initialized to rgb formats only.
3050 * For future use cases we should either initialize them dynamically based on
3051 * plane capabilities, or initialize this array to all formats, so internal drm
3052 * check will succeed, and let DC to implement proper check
3053 */
d90371b0 3054static const uint32_t rgb_formats[] = {
e7b07cee
HW		 3055 DRM_FORMAT_RGB888,
3056 DRM_FORMAT_XRGB8888,
3057 DRM_FORMAT_ARGB8888,
3058 DRM_FORMAT_RGBA8888,
3059 DRM_FORMAT_XRGB2101010,
3060 DRM_FORMAT_XBGR2101010,
3061 DRM_FORMAT_ARGB2101010,
3062 DRM_FORMAT_ABGR2101010,
3063};
3064
99d1abf8 3065static const uint32_t yuv_formats[] = {
e7b07cee
HW		 3066 DRM_FORMAT_NV12,
3067 DRM_FORMAT_NV21,
3068};
3069
3070static const u32 cursor_formats[] = {
3071 DRM_FORMAT_ARGB8888
3072};
3073
7578ecda
AD		 3074static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
3075 struct amdgpu_plane *aplane,
3076 unsigned long possible_crtcs)
e7b07cee
HW		 3077{
3078 int res = -EPERM;
3079
3080 switch (aplane->base.type) {
3081 case DRM_PLANE_TYPE_PRIMARY:
3082 aplane->base.format_default = true;
3083
3084 res = drm_universal_plane_init(
3085 dm->adev->ddev,
3086 &aplane->base,
3087 possible_crtcs,
3088 &dm_plane_funcs,
3089 rgb_formats,
3090 ARRAY_SIZE(rgb_formats),
3091 NULL, aplane->base.type, NULL);
3092 break;
3093 case DRM_PLANE_TYPE_OVERLAY:
3094 res = drm_universal_plane_init(
3095 dm->adev->ddev,
3096 &aplane->base,
3097 possible_crtcs,
3098 &dm_plane_funcs,
3099 yuv_formats,
3100 ARRAY_SIZE(yuv_formats),
3101 NULL, aplane->base.type, NULL);
3102 break;
3103 case DRM_PLANE_TYPE_CURSOR:
3104 res = drm_universal_plane_init(
3105 dm->adev->ddev,
3106 &aplane->base,
3107 possible_crtcs,
3108 &dm_plane_funcs,
3109 cursor_formats,
3110 ARRAY_SIZE(cursor_formats),
3111 NULL, aplane->base.type, NULL);
3112 break;
3113 }
3114
3115 drm_plane_helper_add(&aplane->base, &dm_plane_helper_funcs);
3116
3117 return res;
3118}
3119
7578ecda
AD		 3120static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
3121 struct drm_plane *plane,
3122 uint32_t crtc_index)
e7b07cee
HW		 3123{
3124 struct amdgpu_crtc *acrtc = NULL;
3125 struct amdgpu_plane *cursor_plane;
3126
3127 int res = -ENOMEM;
3128
3129 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
3130 if (!cursor_plane)
3131 goto fail;
3132
3133 cursor_plane->base.type = DRM_PLANE_TYPE_CURSOR;
3134 res = amdgpu_dm_plane_init(dm, cursor_plane, 0);
3135
3136 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
3137 if (!acrtc)
3138 goto fail;
3139
3140 res = drm_crtc_init_with_planes(
3141 dm->ddev,
3142 &acrtc->base,
3143 plane,
3144 &cursor_plane->base,
3145 &amdgpu_dm_crtc_funcs, NULL);
3146
3147 if (res)
3148 goto fail;
3149
3150 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
3151
3152 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
3153 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
3154
3155 acrtc->crtc_id = crtc_index;
3156 acrtc->base.enabled = false;
3157
3158 dm->adev->mode_info.crtcs[crtc_index] = acrtc;
3159 drm_mode_crtc_set_gamma_size(&acrtc->base, 256);
3160
3161 return 0;
3162
3163fail:
b830ebc9
HW		 3164 kfree(acrtc);
3165 kfree(cursor_plane);
e7b07cee
HW		 3166 return res;
3167}
3168
3169
3170static int to_drm_connector_type(enum signal_type st)
3171{
3172 switch (st) {
3173 case SIGNAL_TYPE_HDMI_TYPE_A:
3174 return DRM_MODE_CONNECTOR_HDMIA;
3175 case SIGNAL_TYPE_EDP:
3176 return DRM_MODE_CONNECTOR_eDP;
3177 case SIGNAL_TYPE_RGB:
3178 return DRM_MODE_CONNECTOR_VGA;
3179 case SIGNAL_TYPE_DISPLAY_PORT:
3180 case SIGNAL_TYPE_DISPLAY_PORT_MST:
3181 return DRM_MODE_CONNECTOR_DisplayPort;
3182 case SIGNAL_TYPE_DVI_DUAL_LINK:
3183 case SIGNAL_TYPE_DVI_SINGLE_LINK:
3184 return DRM_MODE_CONNECTOR_DVID;
3185 case SIGNAL_TYPE_VIRTUAL:
3186 return DRM_MODE_CONNECTOR_VIRTUAL;
3187
3188 default:
3189 return DRM_MODE_CONNECTOR_Unknown;
3190 }
3191}
3192
3193static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
3194{
3195 const struct drm_connector_helper_funcs *helper =
3196 connector->helper_private;
3197 struct drm_encoder *encoder;
3198 struct amdgpu_encoder *amdgpu_encoder;
3199
3200 encoder = helper->best_encoder(connector);
3201
3202 if (encoder == NULL)
3203 return;
3204
3205 amdgpu_encoder = to_amdgpu_encoder(encoder);
3206
3207 amdgpu_encoder->native_mode.clock = 0;
3208
3209 if (!list_empty(&connector->probed_modes)) {
3210 struct drm_display_mode *preferred_mode = NULL;
b830ebc9 3211
e7b07cee 3212 list_for_each_entry(preferred_mode,
b830ebc9
HW		 3213 &connector->probed_modes,
3214 head) {
3215 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
3216 amdgpu_encoder->native_mode = *preferred_mode;
3217
e7b07cee
HW		 3218 break;
3219 }
3220
3221 }
3222}
3223
3ee6b26b
AD		 3224static struct drm_display_mode *
3225amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
3226 char *name,
3227 int hdisplay, int vdisplay)
e7b07cee
HW		 3228{
3229 struct drm_device *dev = encoder->dev;
3230 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3231 struct drm_display_mode *mode = NULL;
3232 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
3233
3234 mode = drm_mode_duplicate(dev, native_mode);
3235
b830ebc9 3236 if (mode == NULL)
e7b07cee
HW		 3237 return NULL;
3238
3239 mode->hdisplay = hdisplay;
3240 mode->vdisplay = vdisplay;
3241 mode->type &= ~DRM_MODE_TYPE_PREFERRED;
3242 strncpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
3243
3244 return mode;
3245
3246}
3247
3248static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
3ee6b26b 3249 struct drm_connector *connector)
e7b07cee
HW		 3250{
3251 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3252 struct drm_display_mode *mode = NULL;
3253 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
c84dec2f
HW		 3254 struct amdgpu_dm_connector *amdgpu_dm_connector =
3255 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 3256 int i;
3257 int n;
3258 struct mode_size {
3259 char name[DRM_DISPLAY_MODE_LEN];
3260 int w;
3261 int h;
b830ebc9 3262 } common_modes[] = {
e7b07cee
HW		 3263 { "640x480", 640, 480},
3264 { "800x600", 800, 600},
3265 { "1024x768", 1024, 768},
3266 { "1280x720", 1280, 720},
3267 { "1280x800", 1280, 800},
3268 {"1280x1024", 1280, 1024},
3269 { "1440x900", 1440, 900},
3270 {"1680x1050", 1680, 1050},
3271 {"1600x1200", 1600, 1200},
3272 {"1920x1080", 1920, 1080},
3273 {"1920x1200", 1920, 1200}
3274 };
3275
b830ebc9 3276 n = ARRAY_SIZE(common_modes);
e7b07cee
HW		 3277
3278 for (i = 0; i < n; i++) {
3279 struct drm_display_mode *curmode = NULL;
3280 bool mode_existed = false;
3281
3282 if (common_modes[i].w > native_mode->hdisplay ||
b830ebc9
HW		 3283 common_modes[i].h > native_mode->vdisplay ||
3284 (common_modes[i].w == native_mode->hdisplay &&
3285 common_modes[i].h == native_mode->vdisplay))
3286 continue;
e7b07cee
HW		 3287
3288 list_for_each_entry(curmode, &connector->probed_modes, head) {
3289 if (common_modes[i].w == curmode->hdisplay &&
b830ebc9 3290 common_modes[i].h == curmode->vdisplay) {
e7b07cee
HW		 3291 mode_existed = true;
3292 break;
3293 }
3294 }
3295
3296 if (mode_existed)
3297 continue;
3298
3299 mode = amdgpu_dm_create_common_mode(encoder,
3300 common_modes[i].name, common_modes[i].w,
3301 common_modes[i].h);
3302 drm_mode_probed_add(connector, mode);
c84dec2f 3303 amdgpu_dm_connector->num_modes++;
e7b07cee
HW		 3304 }
3305}
3306
3ee6b26b
AD		 3307static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
3308 struct edid *edid)
e7b07cee 3309{
c84dec2f
HW		 3310 struct amdgpu_dm_connector *amdgpu_dm_connector =
3311 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 3312
3313 if (edid) {
3314 /* empty probed_modes */
3315 INIT_LIST_HEAD(&connector->probed_modes);
c84dec2f 3316 amdgpu_dm_connector->num_modes =
e7b07cee
HW		 3317 drm_add_edid_modes(connector, edid);
3318
3319 drm_edid_to_eld(connector, edid);
3320
3321 amdgpu_dm_get_native_mode(connector);
3322 } else
c84dec2f 3323 amdgpu_dm_connector->num_modes = 0;
e7b07cee
HW		 3324}
3325
7578ecda 3326static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
e7b07cee
HW		 3327{
3328 const struct drm_connector_helper_funcs *helper =
3329 connector->helper_private;
c84dec2f
HW		 3330 struct amdgpu_dm_connector *amdgpu_dm_connector =
3331 to_amdgpu_dm_connector(connector);
e7b07cee 3332 struct drm_encoder *encoder;
c84dec2f 3333 struct edid *edid = amdgpu_dm_connector->edid;
e7b07cee
HW		 3334
3335 encoder = helper->best_encoder(connector);
3336
3337 amdgpu_dm_connector_ddc_get_modes(connector, edid);
3338 amdgpu_dm_connector_add_common_modes(encoder, connector);
c84dec2f 3339 return amdgpu_dm_connector->num_modes;
e7b07cee
HW		 3340}
3341
3ee6b26b
AD		 3342void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
3343 struct amdgpu_dm_connector *aconnector,
3344 int connector_type,
3345 struct dc_link *link,
3346 int link_index)
e7b07cee
HW		 3347{
3348 struct amdgpu_device *adev = dm->ddev->dev_private;
3349
3350 aconnector->connector_id = link_index;
3351 aconnector->dc_link = link;
3352 aconnector->base.interlace_allowed = false;
3353 aconnector->base.doublescan_allowed = false;
3354 aconnector->base.stereo_allowed = false;
3355 aconnector->base.dpms = DRM_MODE_DPMS_OFF;
3356 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
3357
3358 mutex_init(&aconnector->hpd_lock);
3359
b830ebc9
HW		 3360 /* configure support HPD hot plug connector_>polled default value is 0
3361 * which means HPD hot plug not supported
3362 */
e7b07cee
HW		 3363 switch (connector_type) {
3364 case DRM_MODE_CONNECTOR_HDMIA:
3365 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3366 break;
3367 case DRM_MODE_CONNECTOR_DisplayPort:
3368 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3369 break;
3370 case DRM_MODE_CONNECTOR_DVID:
3371 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3372 break;
3373 default:
3374 break;
3375 }
3376
3377 drm_object_attach_property(&aconnector->base.base,
3378 dm->ddev->mode_config.scaling_mode_property,
3379 DRM_MODE_SCALE_NONE);
3380
3381 drm_object_attach_property(&aconnector->base.base,
3382 adev->mode_info.underscan_property,
3383 UNDERSCAN_OFF);
3384 drm_object_attach_property(&aconnector->base.base,
3385 adev->mode_info.underscan_hborder_property,
3386 0);
3387 drm_object_attach_property(&aconnector->base.base,
3388 adev->mode_info.underscan_vborder_property,
3389 0);
3390
3391}
3392
7578ecda
AD		 3393static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
3394 struct i2c_msg *msgs, int num)
e7b07cee
HW		 3395{
3396 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
3397 struct ddc_service *ddc_service = i2c->ddc_service;
3398 struct i2c_command cmd;
3399 int i;
3400 int result = -EIO;
3401
b830ebc9 3402 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
e7b07cee
HW		 3403
3404 if (!cmd.payloads)
3405 return result;
3406
3407 cmd.number_of_payloads = num;
3408 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
3409 cmd.speed = 100;
3410
3411 for (i = 0; i < num; i++) {
3412 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
3413 cmd.payloads[i].address = msgs[i].addr;
3414 cmd.payloads[i].length = msgs[i].len;
3415 cmd.payloads[i].data = msgs[i].buf;
3416 }
3417
3418 if (dal_i2caux_submit_i2c_command(
3419 ddc_service->ctx->i2caux,
3420 ddc_service->ddc_pin,
3421 &cmd))
3422 result = num;
3423
3424 kfree(cmd.payloads);
3425 return result;
3426}
3427
7578ecda 3428static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
e7b07cee
HW		 3429{
3430 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
3431}
3432
3433static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
3434 .master_xfer = amdgpu_dm_i2c_xfer,
3435 .functionality = amdgpu_dm_i2c_func,
3436};
3437
3ee6b26b
AD		 3438static struct amdgpu_i2c_adapter *
3439create_i2c(struct ddc_service *ddc_service,
3440 int link_index,
3441 int *res)
e7b07cee
HW		 3442{
3443 struct amdgpu_device *adev = ddc_service->ctx->driver_context;
3444 struct amdgpu_i2c_adapter *i2c;
3445
b830ebc9 3446 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
e7b07cee
HW		 3447 i2c->base.owner = THIS_MODULE;
3448 i2c->base.class = I2C_CLASS_DDC;
3449 i2c->base.dev.parent = &adev->pdev->dev;
3450 i2c->base.algo = &amdgpu_dm_i2c_algo;
b830ebc9 3451 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
e7b07cee
HW		 3452 i2c_set_adapdata(&i2c->base, i2c);
3453 i2c->ddc_service = ddc_service;
3454
3455 return i2c;
3456}
3457
3458/* Note: this function assumes that dc_link_detect() was called for the
b830ebc9
HW		 3459 * dc_link which will be represented by this aconnector.
3460 */
7578ecda
AD		 3461static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
3462 struct amdgpu_dm_connector *aconnector,
3463 uint32_t link_index,
3464 struct amdgpu_encoder *aencoder)
e7b07cee
HW		 3465{
3466 int res = 0;
3467 int connector_type;
3468 struct dc *dc = dm->dc;
3469 struct dc_link *link = dc_get_link_at_index(dc, link_index);
3470 struct amdgpu_i2c_adapter *i2c;
3471 ((struct dc_link *)link)->priv = aconnector;
3472
f1ad2f5e 3473 DRM_DEBUG_DRIVER("%s()\n", __func__);
e7b07cee
HW		 3474
3475 i2c = create_i2c(link->ddc, link->link_index, &res);
3476 aconnector->i2c = i2c;
3477 res = i2c_add_adapter(&i2c->base);
3478
3479 if (res) {
3480 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
3481 goto out_free;
3482 }
3483
3484 connector_type = to_drm_connector_type(link->connector_signal);
3485
3486 res = drm_connector_init(
3487 dm->ddev,
3488 &aconnector->base,
3489 &amdgpu_dm_connector_funcs,
3490 connector_type);
3491
3492 if (res) {
3493 DRM_ERROR("connector_init failed\n");
3494 aconnector->connector_id = -1;
3495 goto out_free;
3496 }
3497
3498 drm_connector_helper_add(
3499 &aconnector->base,
3500 &amdgpu_dm_connector_helper_funcs);
3501
3502 amdgpu_dm_connector_init_helper(
3503 dm,
3504 aconnector,
3505 connector_type,
3506 link,
3507 link_index);
3508
3509 drm_mode_connector_attach_encoder(
3510 &aconnector->base, &aencoder->base);
3511
3512 drm_connector_register(&aconnector->base);
3513
3514 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
3515 || connector_type == DRM_MODE_CONNECTOR_eDP)
3516 amdgpu_dm_initialize_dp_connector(dm, aconnector);
3517
3518#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
3519 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
3520
3521 /* NOTE: this currently will create backlight device even if a panel
3522 * is not connected to the eDP/LVDS connector.
3523 *
3524 * This is less than ideal but we don't have sink information at this
3525 * stage since detection happens after. We can't do detection earlier
3526 * since MST detection needs connectors to be created first.
3527 */
3528 if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) {
3529 /* Event if registration failed, we should continue with
3530 * DM initialization because not having a backlight control
b830ebc9
HW		 3531 * is better then a black screen.
3532 */
e7b07cee
HW		 3533 amdgpu_dm_register_backlight_device(dm);
3534
3535 if (dm->backlight_dev)
3536 dm->backlight_link = link;
3537 }
3538#endif
3539
3540out_free:
3541 if (res) {
3542 kfree(i2c);
3543 aconnector->i2c = NULL;
3544 }
3545 return res;
3546}
3547
3548int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
3549{
3550 switch (adev->mode_info.num_crtc) {
3551 case 1:
3552 return 0x1;
3553 case 2:
3554 return 0x3;
3555 case 3:
3556 return 0x7;
3557 case 4:
3558 return 0xf;
3559 case 5:
3560 return 0x1f;
3561 case 6:
3562 default:
3563 return 0x3f;
3564 }
3565}
3566
7578ecda
AD		 3567static int amdgpu_dm_encoder_init(struct drm_device *dev,
3568 struct amdgpu_encoder *aencoder,
3569 uint32_t link_index)
e7b07cee
HW		 3570{
3571 struct amdgpu_device *adev = dev->dev_private;
3572
3573 int res = drm_encoder_init(dev,
3574 &aencoder->base,
3575 &amdgpu_dm_encoder_funcs,
3576 DRM_MODE_ENCODER_TMDS,
3577 NULL);
3578
3579 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
3580
3581 if (!res)
3582 aencoder->encoder_id = link_index;
3583 else
3584 aencoder->encoder_id = -1;
3585
3586 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
3587
3588 return res;
3589}
3590
3ee6b26b
AD		 3591static void manage_dm_interrupts(struct amdgpu_device *adev,
3592 struct amdgpu_crtc *acrtc,
3593 bool enable)
e7b07cee
HW		 3594{
3595 /*
3596 * this is not correct translation but will work as soon as VBLANK
3597 * constant is the same as PFLIP
3598 */
3599 int irq_type =
3600 amdgpu_crtc_idx_to_irq_type(
3601 adev,
3602 acrtc->crtc_id);
3603
3604 if (enable) {
3605 drm_crtc_vblank_on(&acrtc->base);
3606 amdgpu_irq_get(
3607 adev,
3608 &adev->pageflip_irq,
3609 irq_type);
3610 } else {
3611
3612 amdgpu_irq_put(
3613 adev,
3614 &adev->pageflip_irq,
3615 irq_type);
3616 drm_crtc_vblank_off(&acrtc->base);
3617 }
3618}
3619
3ee6b26b
AD		 3620static bool
3621is_scaling_state_different(const struct dm_connector_state *dm_state,
3622 const struct dm_connector_state *old_dm_state)
e7b07cee
HW		 3623{
3624 if (dm_state->scaling != old_dm_state->scaling)
3625 return true;
3626 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
3627 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
3628 return true;
3629 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
3630 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
3631 return true;
b830ebc9
HW		 3632 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
3633 dm_state->underscan_vborder != old_dm_state->underscan_vborder)
3634 return true;
e7b07cee
HW		 3635 return false;
3636}
3637
3ee6b26b
AD		 3638static void remove_stream(struct amdgpu_device *adev,
3639 struct amdgpu_crtc *acrtc,
3640 struct dc_stream_state *stream)
e7b07cee
HW		 3641{
3642 /* this is the update mode case */
3643 if (adev->dm.freesync_module)
3644 mod_freesync_remove_stream(adev->dm.freesync_module, stream);
3645
3646 acrtc->otg_inst = -1;
3647 acrtc->enabled = false;
3648}
3649
7578ecda
AD		 3650static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
3651 struct dc_cursor_position *position)
2a8f6ccb
HW		 3652{
3653 struct amdgpu_crtc *amdgpu_crtc = amdgpu_crtc = to_amdgpu_crtc(crtc);
3654 int x, y;
3655 int xorigin = 0, yorigin = 0;
3656
3657 if (!crtc || !plane->state->fb) {
3658 position->enable = false;
3659 position->x = 0;
3660 position->y = 0;
3661 return 0;
3662 }
3663
3664 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
3665 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
3666 DRM_ERROR("%s: bad cursor width or height %d x %d\n",
3667 __func__,
3668 plane->state->crtc_w,
3669 plane->state->crtc_h);
3670 return -EINVAL;
3671 }
3672
3673 x = plane->state->crtc_x;
3674 y = plane->state->crtc_y;
3675 /* avivo cursor are offset into the total surface */
3676 x += crtc->primary->state->src_x >> 16;
3677 y += crtc->primary->state->src_y >> 16;
3678 if (x < 0) {
3679 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
3680 x = 0;
3681 }
3682 if (y < 0) {
3683 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
3684 y = 0;
3685 }
3686 position->enable = true;
3687 position->x = x;
3688 position->y = y;
3689 position->x_hotspot = xorigin;
3690 position->y_hotspot = yorigin;
3691
3692 return 0;
3693}
3694
3ee6b26b
AD		 3695static void handle_cursor_update(struct drm_plane *plane,
3696 struct drm_plane_state *old_plane_state)
e7b07cee 3697{
2a8f6ccb
HW		 3698 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);
3699 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
3700 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
3701 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
3702 uint64_t address = afb ? afb->address : 0;
3703 struct dc_cursor_position position;
3704 struct dc_cursor_attributes attributes;
3705 int ret;
3706
e7b07cee
HW		 3707 if (!plane->state->fb && !old_plane_state->fb)
3708 return;
3709
f1ad2f5e 3710 DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n",
c12a7ba5
HW		 3711 __func__,
3712 amdgpu_crtc->crtc_id,
3713 plane->state->crtc_w,
3714 plane->state->crtc_h);
2a8f6ccb
HW		 3715
3716 ret = get_cursor_position(plane, crtc, &position);
3717 if (ret)
3718 return;
3719
3720 if (!position.enable) {
3721 /* turn off cursor */
3722 if (crtc_state && crtc_state->stream)
3723 dc_stream_set_cursor_position(crtc_state->stream,
3724 &position);
3725 return;
e7b07cee 3726 }
e7b07cee 3727
2a8f6ccb
HW		 3728 amdgpu_crtc->cursor_width = plane->state->crtc_w;
3729 amdgpu_crtc->cursor_height = plane->state->crtc_h;
3730
3731 attributes.address.high_part = upper_32_bits(address);
3732 attributes.address.low_part = lower_32_bits(address);
3733 attributes.width = plane->state->crtc_w;
3734 attributes.height = plane->state->crtc_h;
3735 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
3736 attributes.rotation_angle = 0;
3737 attributes.attribute_flags.value = 0;
3738
3739 attributes.pitch = attributes.width;
3740
886daac9
JZ		 3741 if (crtc_state->stream) {
3742 if (!dc_stream_set_cursor_attributes(crtc_state->stream,
3743 &attributes))
3744 DRM_ERROR("DC failed to set cursor attributes\n");
2a8f6ccb 3745
2a8f6ccb
HW		 3746 if (!dc_stream_set_cursor_position(crtc_state->stream,
3747 &position))
3748 DRM_ERROR("DC failed to set cursor position\n");
886daac9 3749 }
2a8f6ccb 3750}
e7b07cee
HW		 3751
3752static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
3753{
3754
3755 assert_spin_locked(&acrtc->base.dev->event_lock);
3756 WARN_ON(acrtc->event);
3757
3758 acrtc->event = acrtc->base.state->event;
3759
3760 /* Set the flip status */
3761 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
3762
3763 /* Mark this event as consumed */
3764 acrtc->base.state->event = NULL;
3765
3766 DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
3767 acrtc->crtc_id);
3768}
3769
3770/*
3771 * Executes flip
3772 *
3773 * Waits on all BO's fences and for proper vblank count
3774 */
3ee6b26b
AD		 3775static void amdgpu_dm_do_flip(struct drm_crtc *crtc,
3776 struct drm_framebuffer *fb,
bc6828e0
BL		 3777 uint32_t target,
3778 struct dc_state *state)
e7b07cee
HW		 3779{
3780 unsigned long flags;
3781 uint32_t target_vblank;
3782 int r, vpos, hpos;
3783 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3784 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
3785 struct amdgpu_bo *abo = gem_to_amdgpu_bo(afb->obj);
3786 struct amdgpu_device *adev = crtc->dev->dev_private;
aac6a07e 3787 bool async_flip = (crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
e7b07cee 3788 struct dc_flip_addrs addr = { {0} };
3be5262e 3789 /* TODO eliminate or rename surface_update */
e7b07cee
HW		 3790 struct dc_surface_update surface_updates[1] = { {0} };
3791 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
3792
3793
3794 /* Prepare wait for target vblank early - before the fence-waits */
3795 target_vblank = target - drm_crtc_vblank_count(crtc) +
3796 amdgpu_get_vblank_counter_kms(crtc->dev, acrtc->crtc_id);
3797
b830ebc9 3798 /* TODO This might fail and hence better not used, wait
e7b07cee
HW		 3799 * explicitly on fences instead
3800 * and in general should be called for
3801 * blocking commit to as per framework helpers
b830ebc9 3802 */
e7b07cee
HW		 3803 r = amdgpu_bo_reserve(abo, true);
3804 if (unlikely(r != 0)) {
3805 DRM_ERROR("failed to reserve buffer before flip\n");
3806 WARN_ON(1);
3807 }
3808
3809 /* Wait for all fences on this FB */
3810 WARN_ON(reservation_object_wait_timeout_rcu(abo->tbo.resv, true, false,
3811 MAX_SCHEDULE_TIMEOUT) < 0);
3812
3813 amdgpu_bo_unreserve(abo);
3814
3815 /* Wait until we're out of the vertical blank period before the one
3816 * targeted by the flip
3817 */
3818 while ((acrtc->enabled &&
3819 (amdgpu_get_crtc_scanoutpos(adev->ddev, acrtc->crtc_id, 0,
3820 &vpos, &hpos, NULL, NULL,
3821 &crtc->hwmode)
3822 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
3823 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
3824 (int)(target_vblank -
3825 amdgpu_get_vblank_counter_kms(adev->ddev, acrtc->crtc_id)) > 0)) {
3826 usleep_range(1000, 1100);
3827 }
3828
3829 /* Flip */
3830 spin_lock_irqsave(&crtc->dev->event_lock, flags);
3831 /* update crtc fb */
3832 crtc->primary->fb = fb;
3833
3834 WARN_ON(acrtc->pflip_status != AMDGPU_FLIP_NONE);
3835 WARN_ON(!acrtc_state->stream);
3836
3837 addr.address.grph.addr.low_part = lower_32_bits(afb->address);
3838 addr.address.grph.addr.high_part = upper_32_bits(afb->address);
3839 addr.flip_immediate = async_flip;
3840
3841
3842 if (acrtc->base.state->event)
3843 prepare_flip_isr(acrtc);
3844
3be5262e 3845 surface_updates->surface = dc_stream_get_status(acrtc_state->stream)->plane_states[0];
e7b07cee
HW		 3846 surface_updates->flip_addr = &addr;
3847
3848
bc6828e0
BL		 3849 dc_commit_updates_for_stream(adev->dm.dc,
3850 surface_updates,
3851 1,
3852 acrtc_state->stream,
3853 NULL,
3854 &surface_updates->surface,
3855 state);
e7b07cee
HW		 3856
3857 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n",
3858 __func__,
3859 addr.address.grph.addr.high_part,
3860 addr.address.grph.addr.low_part);
3861
3862
3863 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
3864}
3865
3be5262e 3866static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
3ee6b26b
AD		 3867 struct drm_device *dev,
3868 struct amdgpu_display_manager *dm,
3869 struct drm_crtc *pcrtc,
3870 bool *wait_for_vblank)
e7b07cee
HW		 3871{
3872 uint32_t i;
3873 struct drm_plane *plane;
0bc9706d 3874 struct drm_plane_state *old_plane_state, *new_plane_state;
0971c40e 3875 struct dc_stream_state *dc_stream_attach;
3be5262e 3876 struct dc_plane_state *plane_states_constructed[MAX_SURFACES];
e7b07cee 3877 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
0bc9706d
LSL		 3878 struct drm_crtc_state *new_pcrtc_state =
3879 drm_atomic_get_new_crtc_state(state, pcrtc);
3880 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
bc6828e0 3881 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
e7b07cee
HW		 3882 int planes_count = 0;
3883 unsigned long flags;
3884
3885 /* update planes when needed */
0bc9706d
LSL		 3886 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
3887 struct drm_crtc *crtc = new_plane_state->crtc;
3888 struct drm_crtc_state *new_crtc_state =
3889 drm_atomic_get_new_crtc_state(state, crtc);
3890 struct drm_framebuffer *fb = new_plane_state->fb;
e7b07cee 3891 bool pflip_needed;
54d76575 3892 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
e7b07cee
HW		 3893
3894 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
3895 handle_cursor_update(plane, old_plane_state);
3896 continue;
3897 }
3898
0bc9706d 3899 if (!fb || !crtc || pcrtc != crtc || !new_crtc_state->active)
e7b07cee
HW		 3900 continue;
3901
3902 pflip_needed = !state->allow_modeset;
3903
3904 spin_lock_irqsave(&crtc->dev->event_lock, flags);
3905 if (acrtc_attach->pflip_status != AMDGPU_FLIP_NONE) {
3be5262e
HW		 3906 DRM_ERROR("%s: acrtc %d, already busy\n",
3907 __func__,
3908 acrtc_attach->crtc_id);
e7b07cee 3909 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
b830ebc9 3910 /* In commit tail framework this cannot happen */
e7b07cee
HW		 3911 WARN_ON(1);
3912 }
3913 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
3914
3915 if (!pflip_needed) {
54d76575 3916 WARN_ON(!dm_new_plane_state->dc_state);
e7b07cee 3917
54d76575 3918 plane_states_constructed[planes_count] = dm_new_plane_state->dc_state;
e7b07cee
HW		 3919
3920 dc_stream_attach = acrtc_state->stream;
3921 planes_count++;
3922
0bc9706d 3923 } else if (new_crtc_state->planes_changed) {
e7b07cee
HW		 3924 /* Assume even ONE crtc with immediate flip means
3925 * entire can't wait for VBLANK
3926 * TODO Check if it's correct
3927 */
3928 *wait_for_vblank =
0bc9706d 3929 new_pcrtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC ?
e7b07cee
HW		 3930 false : true;
3931
3932 /* TODO: Needs rework for multiplane flip */
3933 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
3934 drm_crtc_vblank_get(crtc);
3935
3936 amdgpu_dm_do_flip(
3937 crtc,
3938 fb,
bc6828e0
BL		 3939 drm_crtc_vblank_count(crtc) + *wait_for_vblank,
3940 dm_state->context);
e7b07cee
HW		 3941 }
3942
3943 }
3944
3945 if (planes_count) {
3946 unsigned long flags;
3947
0bc9706d 3948 if (new_pcrtc_state->event) {
e7b07cee
HW		 3949
3950 drm_crtc_vblank_get(pcrtc);
3951
3952 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
3953 prepare_flip_isr(acrtc_attach);
3954 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
3955 }
3956
3be5262e
HW		 3957 if (false == dc_commit_planes_to_stream(dm->dc,
3958 plane_states_constructed,
3959 planes_count,
bc6828e0
BL		 3960 dc_stream_attach,
3961 dm_state->context))
3be5262e 3962 dm_error("%s: Failed to attach plane!\n", __func__);
e7b07cee
HW		 3963 } else {
3964 /*TODO BUG Here should go disable planes on CRTC. */
3965 }
3966}
3967
3968
7578ecda
AD		 3969static int amdgpu_dm_atomic_commit(struct drm_device *dev,
3970 struct drm_atomic_state *state,
3971 bool nonblock)
e7b07cee
HW		 3972{
3973 struct drm_crtc *crtc;
c2cea706 3974 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
e7b07cee
HW		 3975 struct amdgpu_device *adev = dev->dev_private;
3976 int i;
3977
3978 /*
3979 * We evade vblanks and pflips on crtc that
3980 * should be changed. We do it here to flush & disable
3981 * interrupts before drm_swap_state is called in drm_atomic_helper_commit
3982 * it will update crtc->dm_crtc_state->stream pointer which is used in
3983 * the ISRs.
3984 */
c2cea706 3985 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
54d76575 3986 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
e7b07cee
HW		 3987 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3988
54d76575 3989 if (drm_atomic_crtc_needs_modeset(new_crtc_state) && dm_old_crtc_state->stream)
e7b07cee
HW		 3990 manage_dm_interrupts(adev, acrtc, false);
3991 }
3992
3993 return drm_atomic_helper_commit(dev, state, nonblock);
3994
3995 /*TODO Handle EINTR, reenable IRQ*/
3996}
3997
7578ecda 3998static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
e7b07cee
HW		 3999{
4000 struct drm_device *dev = state->dev;
4001 struct amdgpu_device *adev = dev->dev_private;
4002 struct amdgpu_display_manager *dm = &adev->dm;
4003 struct dm_atomic_state *dm_state;
4004 uint32_t i, j;
4005 uint32_t new_crtcs_count = 0;
5cc6dcbd 4006 struct drm_crtc *crtc;
0bc9706d 4007 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
e7b07cee 4008 struct amdgpu_crtc *new_crtcs[MAX_STREAMS];
0971c40e 4009 struct dc_stream_state *new_stream = NULL;
e7b07cee
HW		 4010 unsigned long flags;
4011 bool wait_for_vblank = true;
4012 struct drm_connector *connector;
c2cea706 4013 struct drm_connector_state *old_con_state, *new_con_state;
54d76575 4014 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
e7b07cee
HW		 4015
4016 drm_atomic_helper_update_legacy_modeset_state(dev, state);
4017
4018 dm_state = to_dm_atomic_state(state);
4019
4020 /* update changed items */
0bc9706d 4021 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
e7b07cee 4022 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 4023
54d76575
LSL		 4024 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4025 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
e7b07cee 4026
f1ad2f5e 4027 DRM_DEBUG_DRIVER(
e7b07cee
HW		 4028 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
4029 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
4030 "connectors_changed:%d\n",
4031 acrtc->crtc_id,
0bc9706d
LSL		 4032 new_crtc_state->enable,
4033 new_crtc_state->active,
4034 new_crtc_state->planes_changed,
4035 new_crtc_state->mode_changed,
4036 new_crtc_state->active_changed,
4037 new_crtc_state->connectors_changed);
e7b07cee
HW		 4038
4039 /* handles headless hotplug case, updating new_state and
4040 * aconnector as needed
4041 */
4042
54d76575 4043 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
e7b07cee 4044
f1ad2f5e 4045 DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
e7b07cee 4046
54d76575 4047 if (!dm_new_crtc_state->stream) {
e7b07cee 4048 /*
b830ebc9
HW		 4049 * this could happen because of issues with
4050 * userspace notifications delivery.
4051 * In this case userspace tries to set mode on
4052 * display which is disconnect in fact.
4053 * dc_sink in NULL in this case on aconnector.
4054 * We expect reset mode will come soon.
4055 *
4056 * This can also happen when unplug is done
4057 * during resume sequence ended
4058 *
4059 * In this case, we want to pretend we still
4060 * have a sink to keep the pipe running so that
4061 * hw state is consistent with the sw state
4062 */
f1ad2f5e 4063 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
e7b07cee
HW		 4064 __func__, acrtc->base.base.id);
4065 continue;
4066 }
4067
4068
54d76575
LSL		 4069 if (dm_old_crtc_state->stream)
4070 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
e7b07cee
HW		 4071
4072
4073 /*
4074 * this loop saves set mode crtcs
4075 * we needed to enable vblanks once all
4076 * resources acquired in dc after dc_commit_streams
4077 */
4078
4079 /*TODO move all this into dm_crtc_state, get rid of
4080 * new_crtcs array and use old and new atomic states
4081 * instead
4082 */
4083 new_crtcs[new_crtcs_count] = acrtc;
4084 new_crtcs_count++;
4085
0bc9706d 4086 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
e7b07cee 4087 acrtc->enabled = true;
0bc9706d
LSL		 4088 acrtc->hw_mode = new_crtc_state->mode;
4089 crtc->hwmode = new_crtc_state->mode;
4090 } else if (modereset_required(new_crtc_state)) {
f1ad2f5e 4091 DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
e7b07cee
HW		 4092
4093 /* i.e. reset mode */
54d76575
LSL		 4094 if (dm_old_crtc_state->stream)
4095 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
e7b07cee
HW		 4096 }
4097 } /* for_each_crtc_in_state() */
4098
4099 /*
4100 * Add streams after required streams from new and replaced streams
4101 * are removed from freesync module
4102 */
4103 if (adev->dm.freesync_module) {
4104 for (i = 0; i < new_crtcs_count; i++) {
c84dec2f 4105 struct amdgpu_dm_connector *aconnector = NULL;
b830ebc9 4106
0bc9706d
LSL		 4107 new_crtc_state = drm_atomic_get_new_crtc_state(state,
4108 &new_crtcs[i]->base);
54d76575 4109 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 4110
54d76575 4111 new_stream = dm_new_crtc_state->stream;
1daf8c63 4112 aconnector = amdgpu_dm_find_first_crtc_matching_connector(
e7b07cee 4113 state,
9ba29fcb 4114 &new_crtcs[i]->base);
e7b07cee 4115 if (!aconnector) {
f1ad2f5e 4116 DRM_DEBUG_DRIVER("Atomic commit: Failed to find connector for acrtc id:%d "
b830ebc9
HW		 4117 "skipping freesync init\n",
4118 new_crtcs[i]->crtc_id);
e7b07cee
HW		 4119 continue;
4120 }
4121
4122 mod_freesync_add_stream(adev->dm.freesync_module,
4123 new_stream, &aconnector->caps);
4124 }
4125 }
4126
4127 if (dm_state->context)
608ac7bb 4128 WARN_ON(!dc_commit_state(dm->dc, dm_state->context));
e7b07cee 4129
0bc9706d 4130 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 4131 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 4132
54d76575 4133 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 4134
54d76575 4135 if (dm_new_crtc_state->stream != NULL) {
e7b07cee 4136 const struct dc_stream_status *status =
54d76575 4137 dc_stream_get_status(dm_new_crtc_state->stream);
e7b07cee
HW		 4138
4139 if (!status)
54d76575 4140 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
e7b07cee
HW		 4141 else
4142 acrtc->otg_inst = status->primary_otg_inst;
4143 }
4144 }
4145
ebdd27e1 4146 /* Handle scaling and underscan changes*/
c2cea706 4147 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 4148 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
4149 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
4150 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
e7b07cee
HW		 4151 struct dc_stream_status *status = NULL;
4152
0bc9706d
LSL		 4153 if (acrtc)
4154 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
4155
e7b07cee 4156 /* Skip any modesets/resets */
0bc9706d 4157 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
e7b07cee
HW		 4158 continue;
4159
4160 /* Skip any thing not scale or underscan changes */
54d76575 4161 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
e7b07cee
HW		 4162 continue;
4163
54d76575 4164 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 4165
54d76575
LSL		 4166 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
4167 dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream);
e7b07cee 4168
54d76575 4169 status = dc_stream_get_status(dm_new_crtc_state->stream);
e7b07cee 4170 WARN_ON(!status);
3be5262e 4171 WARN_ON(!status->plane_count);
e7b07cee 4172
54d76575 4173 if (!dm_new_crtc_state->stream)
e7b07cee
HW		 4174 continue;
4175
4176 /*TODO How it works with MPO ?*/
3be5262e 4177 if (!dc_commit_planes_to_stream(
e7b07cee 4178 dm->dc,
3be5262e
HW		 4179 status->plane_states,
4180 status->plane_count,
bc6828e0
BL		 4181 dm_new_crtc_state->stream,
4182 dm_state->context))
e7b07cee
HW		 4183 dm_error("%s: Failed to update stream scaling!\n", __func__);
4184 }
4185
4186 for (i = 0; i < new_crtcs_count; i++) {
4187 /*
4188 * loop to enable interrupts on newly arrived crtc
4189 */
4190 struct amdgpu_crtc *acrtc = new_crtcs[i];
b830ebc9 4191
0bc9706d 4192 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
54d76575 4193 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee
HW		 4194
4195 if (adev->dm.freesync_module)
4196 mod_freesync_notify_mode_change(
54d76575 4197 adev->dm.freesync_module, &dm_new_crtc_state->stream, 1);
e7b07cee
HW		 4198
4199 manage_dm_interrupts(adev, acrtc, true);
4200 }
4201
4202 /* update planes when needed per crtc*/
5cc6dcbd 4203 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
54d76575 4204 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 4205
54d76575 4206 if (dm_new_crtc_state->stream)
5cc6dcbd 4207 amdgpu_dm_commit_planes(state, dev, dm, crtc, &wait_for_vblank);
e7b07cee
HW		 4208 }
4209
4210
4211 /*
4212 * send vblank event on all events not handled in flip and
4213 * mark consumed event for drm_atomic_helper_commit_hw_done
4214 */
4215 spin_lock_irqsave(&adev->ddev->event_lock, flags);
0bc9706d 4216 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 4217
0bc9706d
LSL		 4218 if (new_crtc_state->event)
4219 drm_send_event_locked(dev, &new_crtc_state->event->base);
e7b07cee 4220
0bc9706d 4221 new_crtc_state->event = NULL;
e7b07cee
HW		 4222 }
4223 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
4224
4225 /* Signal HW programming completion */
4226 drm_atomic_helper_commit_hw_done(state);
4227
4228 if (wait_for_vblank)
4229 drm_atomic_helper_wait_for_vblanks(dev, state);
4230
4231 drm_atomic_helper_cleanup_planes(dev, state);
4232}
4233
4234
4235static int dm_force_atomic_commit(struct drm_connector *connector)
4236{
4237 int ret = 0;
4238 struct drm_device *ddev = connector->dev;
4239 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
4240 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
4241 struct drm_plane *plane = disconnected_acrtc->base.primary;
4242 struct drm_connector_state *conn_state;
4243 struct drm_crtc_state *crtc_state;
4244 struct drm_plane_state *plane_state;
4245
4246 if (!state)
4247 return -ENOMEM;
4248
4249 state->acquire_ctx = ddev->mode_config.acquire_ctx;
4250
4251 /* Construct an atomic state to restore previous display setting */
4252
4253 /*
4254 * Attach connectors to drm_atomic_state
4255 */
4256 conn_state = drm_atomic_get_connector_state(state, connector);
4257
4258 ret = PTR_ERR_OR_ZERO(conn_state);
4259 if (ret)
4260 goto err;
4261
4262 /* Attach crtc to drm_atomic_state*/
4263 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
4264
4265 ret = PTR_ERR_OR_ZERO(crtc_state);
4266 if (ret)
4267 goto err;
4268
4269 /* force a restore */
4270 crtc_state->mode_changed = true;
4271
4272 /* Attach plane to drm_atomic_state */
4273 plane_state = drm_atomic_get_plane_state(state, plane);
4274
4275 ret = PTR_ERR_OR_ZERO(plane_state);
4276 if (ret)
4277 goto err;
4278
4279
4280 /* Call commit internally with the state we just constructed */
4281 ret = drm_atomic_commit(state);
4282 if (!ret)
4283 return 0;
4284
4285err:
4286 DRM_ERROR("Restoring old state failed with %i\n", ret);
4287 drm_atomic_state_put(state);
4288
4289 return ret;
4290}
4291
4292/*
4293 * This functions handle all cases when set mode does not come upon hotplug.
4294 * This include when the same display is unplugged then plugged back into the
4295 * same port and when we are running without usermode desktop manager supprot
4296 */
3ee6b26b
AD		 4297void dm_restore_drm_connector_state(struct drm_device *dev,
4298 struct drm_connector *connector)
e7b07cee 4299{
c84dec2f 4300 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 4301 struct amdgpu_crtc *disconnected_acrtc;
4302 struct dm_crtc_state *acrtc_state;
4303
4304 if (!aconnector->dc_sink || !connector->state || !connector->encoder)
4305 return;
4306
4307 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
4308 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
4309
4310 if (!disconnected_acrtc || !acrtc_state->stream)
4311 return;
4312
4313 /*
4314 * If the previous sink is not released and different from the current,
4315 * we deduce we are in a state where we can not rely on usermode call
4316 * to turn on the display, so we do it here
4317 */
4318 if (acrtc_state->stream->sink != aconnector->dc_sink)
4319 dm_force_atomic_commit(&aconnector->base);
4320}
4321
e7b07cee
HW		 4322/*`
4323 * Grabs all modesetting locks to serialize against any blocking commits,
4324 * Waits for completion of all non blocking commits.
4325 */
3ee6b26b
AD		 4326static int do_aquire_global_lock(struct drm_device *dev,
4327 struct drm_atomic_state *state)
e7b07cee
HW		 4328{
4329 struct drm_crtc *crtc;
4330 struct drm_crtc_commit *commit;
4331 long ret;
4332
4333 /* Adding all modeset locks to aquire_ctx will
4334 * ensure that when the framework release it the
4335 * extra locks we are locking here will get released to
4336 */
4337 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
4338 if (ret)
4339 return ret;
4340
4341 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4342 spin_lock(&crtc->commit_lock);
4343 commit = list_first_entry_or_null(&crtc->commit_list,
4344 struct drm_crtc_commit, commit_entry);
4345 if (commit)
4346 drm_crtc_commit_get(commit);
4347 spin_unlock(&crtc->commit_lock);
4348
4349 if (!commit)
4350 continue;
4351
4352 /* Make sure all pending HW programming completed and
4353 * page flips done
4354 */
4355 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
4356
4357 if (ret > 0)
4358 ret = wait_for_completion_interruptible_timeout(
4359 &commit->flip_done, 10*HZ);
4360
4361 if (ret == 0)
4362 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
b830ebc9 4363 "timed out\n", crtc->base.id, crtc->name);
e7b07cee
HW		 4364
4365 drm_crtc_commit_put(commit);
4366 }
4367
4368 return ret < 0 ? ret : 0;
4369}
4370
3ee6b26b
AD		 4371static int dm_update_crtcs_state(struct dc *dc,
4372 struct drm_atomic_state *state,
4373 bool enable,
4374 bool *lock_and_validation_needed)
e7b07cee 4375{
e7b07cee 4376 struct drm_crtc *crtc;
c2cea706 4377 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
62f55537 4378 int i;
54d76575 4379 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
1dc90497 4380 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
9635b754 4381 struct dc_stream_state *new_stream;
62f55537 4382 int ret = 0;
d4d4a645 4383
62f55537
AG		 4384 /*TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set */
4385 /* update changed items */
c2cea706 4386 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
62f55537 4387 struct amdgpu_crtc *acrtc = NULL;
c84dec2f 4388 struct amdgpu_dm_connector *aconnector = NULL;
c2cea706 4389 struct drm_connector_state *new_con_state = NULL;
62f55537 4390 struct dm_connector_state *dm_conn_state = NULL;
e7b07cee 4391
9635b754
DS		 4392 new_stream = NULL;
4393
54d76575
LSL		 4394 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4395 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
62f55537 4396 acrtc = to_amdgpu_crtc(crtc);
e7b07cee 4397
1daf8c63 4398 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
19f89e23 4399
62f55537 4400 /* TODO This hack should go away */
f4ac176e
JZ		 4401 if (aconnector && enable) {
4402 // Make sure fake sink is created in plug-in scenario
c2cea706
LSL		 4403 new_con_state = drm_atomic_get_connector_state(state,
4404 &aconnector->base);
19f89e23 4405
c2cea706
LSL		 4406 if (IS_ERR(new_con_state)) {
4407 ret = PTR_ERR_OR_ZERO(new_con_state);
62f55537
AG		 4408 break;
4409 }
19f89e23 4410
c2cea706 4411 dm_conn_state = to_dm_connector_state(new_con_state);
19f89e23 4412
62f55537 4413 new_stream = create_stream_for_sink(aconnector,
c2cea706 4414 &new_crtc_state->mode,
62f55537 4415 dm_conn_state);
19f89e23 4416
62f55537
AG		 4417 /*
4418 * we can have no stream on ACTION_SET if a display
4419 * was disconnected during S3, in this case it not and
4420 * error, the OS will be updated after detection, and
4421 * do the right thing on next atomic commit
4422 */
19f89e23 4423
62f55537 4424 if (!new_stream) {
f1ad2f5e 4425 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
62f55537
AG		 4426 __func__, acrtc->base.base.id);
4427 break;
19f89e23 4428 }
62f55537 4429 }
19f89e23 4430
9a5d9c48
LSL		 4431 if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
4432 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
19f89e23 4433
c2cea706 4434 new_crtc_state->mode_changed = false;
e7b07cee 4435
c2cea706 4436 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
9a5d9c48 4437 new_crtc_state->mode_changed);
62f55537 4438 }
b830ebc9 4439
e7b07cee 4440
c2cea706 4441 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9635b754 4442 goto next_crtc;
e7b07cee 4443
f1ad2f5e 4444 DRM_DEBUG_DRIVER(
e7b07cee
HW		 4445 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
4446 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
4447 "connectors_changed:%d\n",
4448 acrtc->crtc_id,
c2cea706
LSL		 4449 new_crtc_state->enable,
4450 new_crtc_state->active,
4451 new_crtc_state->planes_changed,
4452 new_crtc_state->mode_changed,
4453 new_crtc_state->active_changed,
4454 new_crtc_state->connectors_changed);
e7b07cee 4455
62f55537
AG		 4456 /* Remove stream for any changed/disabled CRTC */
4457 if (!enable) {
4458
54d76575 4459 if (!dm_old_crtc_state->stream)
9635b754 4460 goto next_crtc;
62f55537 4461
f1ad2f5e 4462 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
62f55537 4463 crtc->base.id);
e7b07cee 4464
1dc90497 4465 /* i.e. reset mode */
62c933f9 4466 if (dc_remove_stream_from_ctx(
62f55537
AG		 4467 dc,
4468 dm_state->context,
62c933f9 4469 dm_old_crtc_state->stream) != DC_OK) {
62f55537 4470 ret = -EINVAL;
9635b754 4471 goto fail;
62f55537
AG		 4472 }
4473
54d76575
LSL		 4474 dc_stream_release(dm_old_crtc_state->stream);
4475 dm_new_crtc_state->stream = NULL;
62f55537
AG		 4476
4477 *lock_and_validation_needed = true;
4478
4479 } else {/* Add stream for any updated/enabled CRTC */
fc17235f
JZ		 4480 /*
4481 * Quick fix to prevent NULL pointer on new_stream when
4482 * added MST connectors not found in existing crtc_state in the chained mode
4483 * TODO: need to dig out the root cause of that
4484 */
4485 if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port))
1bed4d09 4486 goto next_crtc;
62f55537 4487
c2cea706 4488 if (modereset_required(new_crtc_state))
9635b754 4489 goto next_crtc;
62f55537 4490
c2cea706 4491 if (modeset_required(new_crtc_state, new_stream,
54d76575 4492 dm_old_crtc_state->stream)) {
62f55537 4493
54d76575 4494 WARN_ON(dm_new_crtc_state->stream);
62f55537 4495
54d76575 4496 dm_new_crtc_state->stream = new_stream;
62f55537
AG		 4497 dc_stream_retain(new_stream);
4498
f1ad2f5e 4499 DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n",
62f55537 4500 crtc->base.id);
1dc90497 4501
13ab1b44 4502 if (dc_add_stream_to_ctx(
1dc90497
AG		 4503 dc,
4504 dm_state->context,
13ab1b44 4505 dm_new_crtc_state->stream) != DC_OK) {
1dc90497 4506 ret = -EINVAL;
9635b754 4507 goto fail;
1dc90497
AG		 4508 }
4509
62f55537 4510 *lock_and_validation_needed = true;
9b690ef3 4511 }
62f55537 4512 }
9b690ef3 4513
9635b754 4514next_crtc:
62f55537
AG		 4515 /* Release extra reference */
4516 if (new_stream)
4517 dc_stream_release(new_stream);
4518 }
e7b07cee 4519
62f55537 4520 return ret;
9635b754
DS		 4521
4522fail:
4523 if (new_stream)
4524 dc_stream_release(new_stream);
4525 return ret;
62f55537 4526}
9b690ef3 4527
3ee6b26b
AD		 4528static int dm_update_planes_state(struct dc *dc,
4529 struct drm_atomic_state *state,
4530 bool enable,
4531 bool *lock_and_validation_needed)
62f55537
AG		 4532{
4533 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
0bc9706d 4534 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
62f55537
AG		 4535 struct drm_plane *plane;
4536 struct drm_plane_state *old_plane_state, *new_plane_state;
54d76575 4537 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
62f55537 4538 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
54d76575 4539 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
62f55537
AG		 4540 int i ;
4541 /* TODO return page_flip_needed() function */
4542 bool pflip_needed = !state->allow_modeset;
4543 int ret = 0;
e7b07cee 4544
62f55537
AG		 4545 if (pflip_needed)
4546 return ret;
9b690ef3 4547
62f55537
AG		 4548 /* Add new planes */
4549 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
4550 new_plane_crtc = new_plane_state->crtc;
4551 old_plane_crtc = old_plane_state->crtc;
54d76575
LSL		 4552 dm_new_plane_state = to_dm_plane_state(new_plane_state);
4553 dm_old_plane_state = to_dm_plane_state(old_plane_state);
62f55537
AG		 4554
4555 /*TODO Implement atomic check for cursor plane */
4556 if (plane->type == DRM_PLANE_TYPE_CURSOR)
4557 continue;
9b690ef3 4558
62f55537
AG		 4559 /* Remove any changed/removed planes */
4560 if (!enable) {
a7b06724 4561
62f55537
AG		 4562 if (!old_plane_crtc)
4563 continue;
4564
0bc9706d
LSL		 4565 old_crtc_state = drm_atomic_get_old_crtc_state(
4566 state, old_plane_crtc);
54d76575 4567 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9b690ef3 4568
54d76575 4569 if (!dm_old_crtc_state->stream)
62f55537
AG		 4570 continue;
4571
f1ad2f5e 4572 DRM_DEBUG_DRIVER("Disabling DRM plane: %d on DRM crtc %d\n",
62f55537 4573 plane->base.id, old_plane_crtc->base.id);
9b690ef3 4574
62f55537
AG		 4575 if (!dc_remove_plane_from_context(
4576 dc,
54d76575
LSL		 4577 dm_old_crtc_state->stream,
4578 dm_old_plane_state->dc_state,
62f55537
AG		 4579 dm_state->context)) {
4580
4581 ret = EINVAL;
4582 return ret;
e7b07cee
HW		 4583 }
4584
9b690ef3 4585
54d76575
LSL		 4586 dc_plane_state_release(dm_old_plane_state->dc_state);
4587 dm_new_plane_state->dc_state = NULL;
1dc90497 4588
62f55537 4589 *lock_and_validation_needed = true;
1dc90497 4590
62f55537 4591 } else { /* Add new planes */
1dc90497 4592
62f55537
AG		 4593 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
4594 continue;
e7b07cee 4595
62f55537
AG		 4596 if (!new_plane_crtc)
4597 continue;
e7b07cee 4598
62f55537 4599 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
54d76575 4600 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
1dc90497 4601
54d76575 4602 if (!dm_new_crtc_state->stream)
62f55537
AG		 4603 continue;
4604
4605
54d76575 4606 WARN_ON(dm_new_plane_state->dc_state);
9b690ef3 4607
54d76575 4608 dm_new_plane_state->dc_state = dc_create_plane_state(dc);
62f55537 4609
f1ad2f5e 4610 DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
62f55537
AG		 4611 plane->base.id, new_plane_crtc->base.id);
4612
54d76575 4613 if (!dm_new_plane_state->dc_state) {
62f55537
AG		 4614 ret = -EINVAL;
4615 return ret;
4616 }
4617
4618 ret = fill_plane_attributes(
4619 new_plane_crtc->dev->dev_private,
54d76575 4620 dm_new_plane_state->dc_state,
62f55537
AG		 4621 new_plane_state,
4622 new_crtc_state,
4623 false);
4624 if (ret)
4625 return ret;
4626
4627
4628 if (!dc_add_plane_to_context(
4629 dc,
54d76575
LSL		 4630 dm_new_crtc_state->stream,
4631 dm_new_plane_state->dc_state,
62f55537
AG		 4632 dm_state->context)) {
4633
4634 ret = -EINVAL;
4635 return ret;
e7b07cee 4636 }
62f55537
AG		 4637
4638 *lock_and_validation_needed = true;
e7b07cee 4639 }
62f55537 4640 }
e7b07cee
HW		 4641
4642
62f55537
AG		 4643 return ret;
4644}
4645
7578ecda
AD		 4646static int amdgpu_dm_atomic_check(struct drm_device *dev,
4647 struct drm_atomic_state *state)
62f55537
AG		 4648{
4649 int i;
4650 int ret;
4651 struct amdgpu_device *adev = dev->dev_private;
4652 struct dc *dc = adev->dm.dc;
4653 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
4654 struct drm_connector *connector;
c2cea706 4655 struct drm_connector_state *old_con_state, *new_con_state;
62f55537 4656 struct drm_crtc *crtc;
c2cea706 4657 struct drm_crtc_state *new_crtc_state;
e7b07cee 4658
62f55537
AG		 4659 /*
4660 * This bool will be set for true for any modeset/reset
4661 * or plane update which implies non fast surface update.
4662 */
4663 bool lock_and_validation_needed = false;
4664
4665 ret = drm_atomic_helper_check_modeset(dev, state);
4666
4667 if (ret) {
4668 DRM_ERROR("Atomic state validation failed with error :%d !\n", ret);
4669 return ret;
4670 }
4671
4672 /*
4673 * Hack: Commit needs planes right now, specifically for gamma
4674 * TODO rework commit to check CRTC for gamma change
4675 */
c2cea706
LSL		 4676 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
4677 if (new_crtc_state->color_mgmt_changed) {
e7b07cee
HW		 4678 ret = drm_atomic_add_affected_planes(state, crtc);
4679 if (ret)
4680 goto fail;
4681 }
4682 }
4683
62f55537
AG		 4684 dm_state->context = dc_create_state();
4685 ASSERT(dm_state->context);
f36cc577 4686 dc_resource_state_copy_construct_current(dc, dm_state->context);
62f55537
AG		 4687
4688 /* Remove exiting planes if they are modified */
4689 ret = dm_update_planes_state(dc, state, false, &lock_and_validation_needed);
4690 if (ret) {
4691 goto fail;
4692 }
4693
4694 /* Disable all crtcs which require disable */
4695 ret = dm_update_crtcs_state(dc, state, false, &lock_and_validation_needed);
4696 if (ret) {
4697 goto fail;
4698 }
4699
4700 /* Enable all crtcs which require enable */
4701 ret = dm_update_crtcs_state(dc, state, true, &lock_and_validation_needed);
4702 if (ret) {
4703 goto fail;
4704 }
4705
4706 /* Add new/modified planes */
4707 ret = dm_update_planes_state(dc, state, true, &lock_and_validation_needed);
4708 if (ret) {
4709 goto fail;
4710 }
4711
4712 /* Run this here since we want to validate the streams we created */
4713 ret = drm_atomic_helper_check_planes(dev, state);
4714 if (ret)
4715 goto fail;
4716
ebdd27e1 4717 /* Check scaling and underscan changes*/
e7b07cee
HW		 4718 /*TODO Removed scaling changes validation due to inability to commit
4719 * new stream into context w\o causing full reset. Need to
4720 * decide how to handle.
4721 */
c2cea706 4722 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 4723 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
4724 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
4725 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
e7b07cee
HW		 4726
4727 /* Skip any modesets/resets */
0bc9706d
LSL		 4728 if (!acrtc || drm_atomic_crtc_needs_modeset(
4729 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
e7b07cee
HW		 4730 continue;
4731
b830ebc9 4732 /* Skip any thing not scale or underscan changes */
54d76575 4733 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
e7b07cee
HW		 4734 continue;
4735
4736 lock_and_validation_needed = true;
4737 }
4738
e7b07cee
HW		 4739 /*
4740 * For full updates case when
4741 * removing/adding/updating streams on once CRTC while flipping
4742 * on another CRTC,
4743 * acquiring global lock will guarantee that any such full
4744 * update commit
4745 * will wait for completion of any outstanding flip using DRMs
4746 * synchronization events.
4747 */
4748
4749 if (lock_and_validation_needed) {
4750
4751 ret = do_aquire_global_lock(dev, state);
4752 if (ret)
4753 goto fail;
1dc90497 4754
e750d56d 4755 if (dc_validate_global_state(dc, dm_state->context) != DC_OK) {
e7b07cee
HW		 4756 ret = -EINVAL;
4757 goto fail;
4758 }
4759 }
4760
4761 /* Must be success */
4762 WARN_ON(ret);
4763 return ret;
4764
4765fail:
4766 if (ret == -EDEADLK)
f1ad2f5e 4767 DRM_DEBUG_DRIVER("Atomic check stopped due to to deadlock.\n");
e7b07cee 4768 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
f1ad2f5e 4769 DRM_DEBUG_DRIVER("Atomic check stopped due to to signal.\n");
e7b07cee 4770 else
62f55537 4771 DRM_ERROR("Atomic check failed with err: %d \n", ret);
e7b07cee
HW		 4772
4773 return ret;
4774}
4775
3ee6b26b
AD		 4776static bool is_dp_capable_without_timing_msa(struct dc *dc,
4777 struct amdgpu_dm_connector *amdgpu_dm_connector)
e7b07cee
HW		 4778{
4779 uint8_t dpcd_data;
4780 bool capable = false;
4781
c84dec2f 4782 if (amdgpu_dm_connector->dc_link &&
e7b07cee
HW		 4783 dm_helpers_dp_read_dpcd(
4784 NULL,
c84dec2f 4785 amdgpu_dm_connector->dc_link,
e7b07cee
HW		 4786 DP_DOWN_STREAM_PORT_COUNT,
4787 &dpcd_data,
4788 sizeof(dpcd_data))) {
4789 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
4790 }
4791
4792 return capable;
4793}
3ee6b26b
AD		 4794void amdgpu_dm_add_sink_to_freesync_module(struct drm_connector *connector,
4795 struct edid *edid)
e7b07cee
HW		 4796{
4797 int i;
4798 uint64_t val_capable;
4799 bool edid_check_required;
4800 struct detailed_timing *timing;
4801 struct detailed_non_pixel *data;
4802 struct detailed_data_monitor_range *range;
c84dec2f
HW		 4803 struct amdgpu_dm_connector *amdgpu_dm_connector =
4804 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 4805
4806 struct drm_device *dev = connector->dev;
4807 struct amdgpu_device *adev = dev->dev_private;
b830ebc9 4808
e7b07cee 4809 edid_check_required = false;
c84dec2f 4810 if (!amdgpu_dm_connector->dc_sink) {
e7b07cee
HW		 4811 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
4812 return;
4813 }
4814 if (!adev->dm.freesync_module)
4815 return;
4816 /*
4817 * if edid non zero restrict freesync only for dp and edp
4818 */
4819 if (edid) {
c84dec2f
HW		 4820 if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
4821 || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
e7b07cee
HW		 4822 edid_check_required = is_dp_capable_without_timing_msa(
4823 adev->dm.dc,
c84dec2f 4824 amdgpu_dm_connector);
e7b07cee
HW		 4825 }
4826 }
4827 val_capable = 0;
4828 if (edid_check_required == true && (edid->version > 1 ||
4829 (edid->version == 1 && edid->revision > 1))) {
4830 for (i = 0; i < 4; i++) {
4831
4832 timing = &edid->detailed_timings[i];
4833 data = &timing->data.other_data;
4834 range = &data->data.range;
4835 /*
4836 * Check if monitor has continuous frequency mode
4837 */
4838 if (data->type != EDID_DETAIL_MONITOR_RANGE)
4839 continue;
4840 /*
4841 * Check for flag range limits only. If flag == 1 then
4842 * no additional timing information provided.
4843 * Default GTF, GTF Secondary curve and CVT are not
4844 * supported
4845 */
4846 if (range->flags != 1)
4847 continue;
4848
c84dec2f
HW		 4849 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
4850 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
4851 amdgpu_dm_connector->pixel_clock_mhz =
e7b07cee
HW		 4852 range->pixel_clock_mhz * 10;
4853 break;
4854 }
4855
c84dec2f
HW		 4856 if (amdgpu_dm_connector->max_vfreq -
4857 amdgpu_dm_connector->min_vfreq > 10) {
4858 amdgpu_dm_connector->caps.supported = true;
4859 amdgpu_dm_connector->caps.min_refresh_in_micro_hz =
4860 amdgpu_dm_connector->min_vfreq * 1000000;
4861 amdgpu_dm_connector->caps.max_refresh_in_micro_hz =
4862 amdgpu_dm_connector->max_vfreq * 1000000;
e7b07cee
HW		 4863 val_capable = 1;
4864 }
4865 }
4866
4867 /*
4868 * TODO figure out how to notify user-mode or DRM of freesync caps
4869 * once we figure out how to deal with freesync in an upstreamable
4870 * fashion
4871 */
4872
4873}
4874
3ee6b26b 4875void amdgpu_dm_remove_sink_from_freesync_module(struct drm_connector *connector)
e7b07cee
HW		 4876{
4877 /*
4878 * TODO fill in once we figure out how to deal with freesync in
4879 * an upstreamable fashion
4880 */
4881}
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