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drm: drop _mode_ from drm_mode_connector_attach_encoder
[mirror_ubuntu-focal-kernel.git] / drivers / gpu / drm / amd / display / amdgpu_dm / amdgpu_dm.c
CommitLineData
4562236b
HW		 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "dm_services_types.h"
27#include "dc.h"
1dc90497 28#include "dc/inc/core_types.h"
4562236b
HW		 29
30#include "vid.h"
31#include "amdgpu.h"
a49dcb88 32#include "amdgpu_display.h"
4562236b
HW		 33#include "atom.h"
34#include "amdgpu_dm.h"
e7b07cee 35#include "amdgpu_pm.h"
4562236b
HW		 36
37#include "amd_shared.h"
38#include "amdgpu_dm_irq.h"
39#include "dm_helpers.h"
e7b07cee
HW		 40#include "dm_services_types.h"
41#include "amdgpu_dm_mst_types.h"
4562236b
HW		 42
43#include "ivsrcid/ivsrcid_vislands30.h"
44
45#include <linux/module.h>
46#include <linux/moduleparam.h>
47#include <linux/version.h>
e7b07cee 48#include <linux/types.h>
97028037 49#include <linux/pm_runtime.h>
4562236b 50
e7b07cee 51#include <drm/drmP.h>
4562236b
HW		 52#include <drm/drm_atomic.h>
53#include <drm/drm_atomic_helper.h>
54#include <drm/drm_dp_mst_helper.h>
e7b07cee
HW		 55#include <drm/drm_fb_helper.h>
56#include <drm/drm_edid.h>
4562236b
HW		 57
58#include "modules/inc/mod_freesync.h"
59
ff5ef992
AD		 60#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
61#include "ivsrcid/irqsrcs_dcn_1_0.h"
62
ad941f7a
FX		 63#include "dcn/dcn_1_0_offset.h"
64#include "dcn/dcn_1_0_sh_mask.h"
407e7517
HZ		 65#include "soc15_hw_ip.h"
66#include "vega10_ip_offset.h"
ff5ef992
AD		 67
68#include "soc15_common.h"
69#endif
70
e7b07cee
HW		 71#include "modules/inc/mod_freesync.h"
72
73#include "i2caux_interface.h"
74
7578ecda
AD		 75/* basic init/fini API */
76static int amdgpu_dm_init(struct amdgpu_device *adev);
77static void amdgpu_dm_fini(struct amdgpu_device *adev);
78
79/* initializes drm_device display related structures, based on the information
80 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
81 * drm_encoder, drm_mode_config
82 *
83 * Returns 0 on success
84 */
85static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
86/* removes and deallocates the drm structures, created by the above function */
87static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
88
89static void
90amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector);
91
92static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
93 struct amdgpu_plane *aplane,
94 unsigned long possible_crtcs);
95static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
96 struct drm_plane *plane,
97 uint32_t link_index);
98static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
99 struct amdgpu_dm_connector *amdgpu_dm_connector,
100 uint32_t link_index,
101 struct amdgpu_encoder *amdgpu_encoder);
102static int amdgpu_dm_encoder_init(struct drm_device *dev,
103 struct amdgpu_encoder *aencoder,
104 uint32_t link_index);
105
106static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
107
108static int amdgpu_dm_atomic_commit(struct drm_device *dev,
109 struct drm_atomic_state *state,
110 bool nonblock);
111
112static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
113
114static int amdgpu_dm_atomic_check(struct drm_device *dev,
115 struct drm_atomic_state *state);
116
117
118
e7b07cee 119
e04a6123 120static const enum drm_plane_type dm_plane_type_default[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 121 DRM_PLANE_TYPE_PRIMARY,
122 DRM_PLANE_TYPE_PRIMARY,
123 DRM_PLANE_TYPE_PRIMARY,
124 DRM_PLANE_TYPE_PRIMARY,
125 DRM_PLANE_TYPE_PRIMARY,
126 DRM_PLANE_TYPE_PRIMARY,
127};
128
e04a6123 129static const enum drm_plane_type dm_plane_type_carizzo[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 130 DRM_PLANE_TYPE_PRIMARY,
131 DRM_PLANE_TYPE_PRIMARY,
132 DRM_PLANE_TYPE_PRIMARY,
133 DRM_PLANE_TYPE_OVERLAY,/* YUV Capable Underlay */
134};
135
e04a6123 136static const enum drm_plane_type dm_plane_type_stoney[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 137 DRM_PLANE_TYPE_PRIMARY,
138 DRM_PLANE_TYPE_PRIMARY,
139 DRM_PLANE_TYPE_OVERLAY, /* YUV Capable Underlay */
140};
141
4562236b
HW		 142/*
143 * dm_vblank_get_counter
144 *
145 * @brief
146 * Get counter for number of vertical blanks
147 *
148 * @param
149 * struct amdgpu_device *adev - [in] desired amdgpu device
150 * int disp_idx - [in] which CRTC to get the counter from
151 *
152 * @return
153 * Counter for vertical blanks
154 */
155static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
156{
157 if (crtc >= adev->mode_info.num_crtc)
158 return 0;
159 else {
160 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
da5c47f6
AG		 161 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
162 acrtc->base.state);
4562236b 163
da5c47f6
AG		 164
165 if (acrtc_state->stream == NULL) {
0971c40e
HW		 166 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
167 crtc);
4562236b
HW		 168 return 0;
169 }
170
da5c47f6 171 return dc_stream_get_vblank_counter(acrtc_state->stream);
4562236b
HW		 172 }
173}
174
175static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
3ee6b26b 176 u32 *vbl, u32 *position)
4562236b 177{
81c50963
ST		 178 uint32_t v_blank_start, v_blank_end, h_position, v_position;
179
4562236b
HW		 180 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
181 return -EINVAL;
182 else {
183 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
da5c47f6
AG		 184 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
185 acrtc->base.state);
4562236b 186
da5c47f6 187 if (acrtc_state->stream == NULL) {
0971c40e
HW		 188 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
189 crtc);
4562236b
HW		 190 return 0;
191 }
192
81c50963
ST		 193 /*
194 * TODO rework base driver to use values directly.
195 * for now parse it back into reg-format
196 */
da5c47f6 197 dc_stream_get_scanoutpos(acrtc_state->stream,
81c50963
ST		 198 &v_blank_start,
199 &v_blank_end,
200 &h_position,
201 &v_position);
202
e806208d
AG		 203 *position = v_position | (h_position << 16);
204 *vbl = v_blank_start | (v_blank_end << 16);
4562236b
HW		 205 }
206
207 return 0;
208}
209
210static bool dm_is_idle(void *handle)
211{
212 /* XXX todo */
213 return true;
214}
215
216static int dm_wait_for_idle(void *handle)
217{
218 /* XXX todo */
219 return 0;
220}
221
222static bool dm_check_soft_reset(void *handle)
223{
224 return false;
225}
226
227static int dm_soft_reset(void *handle)
228{
229 /* XXX todo */
230 return 0;
231}
232
3ee6b26b
AD		 233static struct amdgpu_crtc *
234get_crtc_by_otg_inst(struct amdgpu_device *adev,
235 int otg_inst)
4562236b
HW		 236{
237 struct drm_device *dev = adev->ddev;
238 struct drm_crtc *crtc;
239 struct amdgpu_crtc *amdgpu_crtc;
240
241 /*
242 * following if is check inherited from both functions where this one is
243 * used now. Need to be checked why it could happen.
244 */
245 if (otg_inst == -1) {
246 WARN_ON(1);
247 return adev->mode_info.crtcs[0];
248 }
249
250 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
251 amdgpu_crtc = to_amdgpu_crtc(crtc);
252
253 if (amdgpu_crtc->otg_inst == otg_inst)
254 return amdgpu_crtc;
255 }
256
257 return NULL;
258}
259
260static void dm_pflip_high_irq(void *interrupt_params)
261{
4562236b
HW		 262 struct amdgpu_crtc *amdgpu_crtc;
263 struct common_irq_params *irq_params = interrupt_params;
264 struct amdgpu_device *adev = irq_params->adev;
265 unsigned long flags;
266
267 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
268
269 /* IRQ could occur when in initial stage */
270 /*TODO work and BO cleanup */
271 if (amdgpu_crtc == NULL) {
272 DRM_DEBUG_DRIVER("CRTC is null, returning.\n");
273 return;
274 }
275
276 spin_lock_irqsave(&adev->ddev->event_lock, flags);
4562236b
HW		 277
278 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
279 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
280 amdgpu_crtc->pflip_status,
281 AMDGPU_FLIP_SUBMITTED,
282 amdgpu_crtc->crtc_id,
283 amdgpu_crtc);
284 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
285 return;
286 }
287
4562236b
HW		 288
289 /* wakeup usersapce */
1159898a 290 if (amdgpu_crtc->event) {
753c66c9
MK		 291 /* Update to correct count/ts if racing with vblank irq */
292 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
293
54f5499a 294 drm_crtc_send_vblank_event(&amdgpu_crtc->base, amdgpu_crtc->event);
1159898a 295
54f5499a
AG		 296 /* page flip completed. clean up */
297 amdgpu_crtc->event = NULL;
1159898a 298
54f5499a
AG		 299 } else
300 WARN_ON(1);
4562236b 301
54f5499a 302 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
4562236b
HW		 303 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
304
54f5499a
AG		 305 DRM_DEBUG_DRIVER("%s - crtc :%d[%p], pflip_stat:AMDGPU_FLIP_NONE\n",
306 __func__, amdgpu_crtc->crtc_id, amdgpu_crtc);
4562236b
HW		 307
308 drm_crtc_vblank_put(&amdgpu_crtc->base);
4562236b
HW		 309}
310
311static void dm_crtc_high_irq(void *interrupt_params)
312{
313 struct common_irq_params *irq_params = interrupt_params;
314 struct amdgpu_device *adev = irq_params->adev;
315 uint8_t crtc_index = 0;
316 struct amdgpu_crtc *acrtc;
317
b57de80a 318 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
4562236b
HW		 319
320 if (acrtc)
321 crtc_index = acrtc->crtc_id;
322
323 drm_handle_vblank(adev->ddev, crtc_index);
31aec354 324 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
4562236b
HW		 325}
326
327static int dm_set_clockgating_state(void *handle,
328 enum amd_clockgating_state state)
329{
330 return 0;
331}
332
333static int dm_set_powergating_state(void *handle,
334 enum amd_powergating_state state)
335{
336 return 0;
337}
338
339/* Prototypes of private functions */
340static int dm_early_init(void* handle);
341
342static void hotplug_notify_work_func(struct work_struct *work)
343{
344 struct amdgpu_display_manager *dm = container_of(work, struct amdgpu_display_manager, mst_hotplug_work);
345 struct drm_device *dev = dm->ddev;
346
347 drm_kms_helper_hotplug_event(dev);
348}
349
a32e24b4 350/* Allocate memory for FBC compressed data */
3e332d3a 351static void amdgpu_dm_fbc_init(struct drm_connector *connector)
a32e24b4 352{
3e332d3a
RL		 353 struct drm_device *dev = connector->dev;
354 struct amdgpu_device *adev = dev->dev_private;
a32e24b4 355 struct dm_comressor_info *compressor = &adev->dm.compressor;
3e332d3a
RL		 356 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
357 struct drm_display_mode *mode;
42e67c3b
RL		 358 unsigned long max_size = 0;
359
360 if (adev->dm.dc->fbc_compressor == NULL)
361 return;
a32e24b4 362
3e332d3a 363 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
42e67c3b
RL		 364 return;
365
3e332d3a
RL		 366 if (compressor->bo_ptr)
367 return;
42e67c3b 368
42e67c3b 369
3e332d3a
RL		 370 list_for_each_entry(mode, &connector->modes, head) {
371 if (max_size < mode->htotal * mode->vtotal)
372 max_size = mode->htotal * mode->vtotal;
42e67c3b
RL		 373 }
374
375 if (max_size) {
376 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
0e5916ff 377 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
42e67c3b 378 &compressor->gpu_addr, &compressor->cpu_addr);
a32e24b4
RL		 379
380 if (r)
42e67c3b
RL		 381 DRM_ERROR("DM: Failed to initialize FBC\n");
382 else {
383 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
384 DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
385 }
386
a32e24b4
RL		 387 }
388
389}
a32e24b4
RL		 390
391
4562236b
HW		 392/* Init display KMS
393 *
394 * Returns 0 on success
395 */
7578ecda 396static int amdgpu_dm_init(struct amdgpu_device *adev)
4562236b
HW		 397{
398 struct dc_init_data init_data;
399 adev->dm.ddev = adev->ddev;
400 adev->dm.adev = adev;
401
4562236b
HW		 402 /* Zero all the fields */
403 memset(&init_data, 0, sizeof(init_data));
404
4562236b
HW		 405 if(amdgpu_dm_irq_init(adev)) {
406 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
407 goto error;
408 }
409
410 init_data.asic_id.chip_family = adev->family;
411
412 init_data.asic_id.pci_revision_id = adev->rev_id;
413 init_data.asic_id.hw_internal_rev = adev->external_rev_id;
414
770d13b1 415 init_data.asic_id.vram_width = adev->gmc.vram_width;
4562236b
HW		 416 /* TODO: initialize init_data.asic_id.vram_type here!!!! */
417 init_data.asic_id.atombios_base_address =
418 adev->mode_info.atom_context->bios;
419
420 init_data.driver = adev;
421
422 adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
423
424 if (!adev->dm.cgs_device) {
425 DRM_ERROR("amdgpu: failed to create cgs device.\n");
426 goto error;
427 }
428
429 init_data.cgs_device = adev->dm.cgs_device;
430
431 adev->dm.dal = NULL;
432
433 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
434
6e227308
HW		 435 /*
436 * TODO debug why this doesn't work on Raven
437 */
438 if (adev->flags & AMD_IS_APU &&
439 adev->asic_type >= CHIP_CARRIZO &&
440 adev->asic_type < CHIP_RAVEN)
441 init_data.flags.gpu_vm_support = true;
442
4562236b
HW		 443 /* Display Core create. */
444 adev->dm.dc = dc_create(&init_data);
445
423788c7 446 if (adev->dm.dc) {
76121231 447 DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
423788c7 448 } else {
76121231 449 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
423788c7
ES		 450 goto error;
451 }
4562236b
HW		 452
453 INIT_WORK(&adev->dm.mst_hotplug_work, hotplug_notify_work_func);
454
455 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
456 if (!adev->dm.freesync_module) {
457 DRM_ERROR(
458 "amdgpu: failed to initialize freesync_module.\n");
459 } else
f1ad2f5e 460 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
4562236b
HW		 461 adev->dm.freesync_module);
462
e277adc5
LSL		 463 amdgpu_dm_init_color_mod();
464
4562236b
HW		 465 if (amdgpu_dm_initialize_drm_device(adev)) {
466 DRM_ERROR(
467 "amdgpu: failed to initialize sw for display support.\n");
468 goto error;
469 }
470
471 /* Update the actual used number of crtc */
472 adev->mode_info.num_crtc = adev->dm.display_indexes_num;
473
474 /* TODO: Add_display_info? */
475
476 /* TODO use dynamic cursor width */
ce75805e
AG		 477 adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
478 adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
4562236b
HW		 479
480 if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) {
481 DRM_ERROR(
482 "amdgpu: failed to initialize sw for display support.\n");
483 goto error;
484 }
485
f1ad2f5e 486 DRM_DEBUG_DRIVER("KMS initialized.\n");
4562236b
HW		 487
488 return 0;
489error:
490 amdgpu_dm_fini(adev);
491
492 return -1;
493}
494
7578ecda 495static void amdgpu_dm_fini(struct amdgpu_device *adev)
4562236b
HW		 496{
497 amdgpu_dm_destroy_drm_device(&adev->dm);
498 /*
499 * TODO: pageflip, vlank interrupt
500 *
501 * amdgpu_dm_irq_fini(adev);
502 */
503
504 if (adev->dm.cgs_device) {
505 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
506 adev->dm.cgs_device = NULL;
507 }
508 if (adev->dm.freesync_module) {
509 mod_freesync_destroy(adev->dm.freesync_module);
510 adev->dm.freesync_module = NULL;
511 }
512 /* DC Destroy TODO: Replace destroy DAL */
21de3396 513 if (adev->dm.dc)
4562236b 514 dc_destroy(&adev->dm.dc);
4562236b
HW		 515 return;
516}
517
4562236b
HW		 518static int dm_sw_init(void *handle)
519{
520 return 0;
521}
522
523static int dm_sw_fini(void *handle)
524{
525 return 0;
526}
527
7abcf6b5 528static int detect_mst_link_for_all_connectors(struct drm_device *dev)
4562236b 529{
c84dec2f 530 struct amdgpu_dm_connector *aconnector;
4562236b 531 struct drm_connector *connector;
7abcf6b5 532 int ret = 0;
4562236b
HW		 533
534 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
535
536 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
b349f76e 537 aconnector = to_amdgpu_dm_connector(connector);
30ec2b97
JFZ		 538 if (aconnector->dc_link->type == dc_connection_mst_branch &&
539 aconnector->mst_mgr.aux) {
f1ad2f5e 540 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
7abcf6b5
AG		 541 aconnector, aconnector->base.base.id);
542
543 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
544 if (ret < 0) {
545 DRM_ERROR("DM_MST: Failed to start MST\n");
546 ((struct dc_link *)aconnector->dc_link)->type = dc_connection_single;
547 return ret;
4562236b 548 }
7abcf6b5 549 }
4562236b
HW		 550 }
551
552 drm_modeset_unlock(&dev->mode_config.connection_mutex);
7abcf6b5
AG		 553 return ret;
554}
555
556static int dm_late_init(void *handle)
557{
42e67c3b 558 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7abcf6b5 559
42e67c3b 560 return detect_mst_link_for_all_connectors(adev->ddev);
4562236b
HW		 561}
562
563static void s3_handle_mst(struct drm_device *dev, bool suspend)
564{
c84dec2f 565 struct amdgpu_dm_connector *aconnector;
4562236b
HW		 566 struct drm_connector *connector;
567
568 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
569
570 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
c84dec2f 571 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 572 if (aconnector->dc_link->type == dc_connection_mst_branch &&
573 !aconnector->mst_port) {
574
575 if (suspend)
576 drm_dp_mst_topology_mgr_suspend(&aconnector->mst_mgr);
577 else
578 drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr);
579 }
580 }
581
582 drm_modeset_unlock(&dev->mode_config.connection_mutex);
583}
584
585static int dm_hw_init(void *handle)
586{
587 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
588 /* Create DAL display manager */
589 amdgpu_dm_init(adev);
4562236b
HW		 590 amdgpu_dm_hpd_init(adev);
591
4562236b
HW		 592 return 0;
593}
594
595static int dm_hw_fini(void *handle)
596{
597 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
598
599 amdgpu_dm_hpd_fini(adev);
600
601 amdgpu_dm_irq_fini(adev);
21de3396 602 amdgpu_dm_fini(adev);
4562236b
HW		 603 return 0;
604}
605
606static int dm_suspend(void *handle)
607{
608 struct amdgpu_device *adev = handle;
609 struct amdgpu_display_manager *dm = &adev->dm;
610 int ret = 0;
4562236b
HW		 611
612 s3_handle_mst(adev->ddev, true);
613
4562236b
HW		 614 amdgpu_dm_irq_suspend(adev);
615
0a214e2f 616 WARN_ON(adev->dm.cached_state);
a3621485
AG		 617 adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);
618
32f5062d 619 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
4562236b
HW		 620
621 return ret;
622}
623
1daf8c63
AD		 624static struct amdgpu_dm_connector *
625amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
626 struct drm_crtc *crtc)
4562236b
HW		 627{
628 uint32_t i;
c2cea706 629 struct drm_connector_state *new_con_state;
4562236b
HW		 630 struct drm_connector *connector;
631 struct drm_crtc *crtc_from_state;
632
c2cea706
LSL		 633 for_each_new_connector_in_state(state, connector, new_con_state, i) {
634 crtc_from_state = new_con_state->crtc;
4562236b
HW		 635
636 if (crtc_from_state == crtc)
c84dec2f 637 return to_amdgpu_dm_connector(connector);
4562236b
HW		 638 }
639
640 return NULL;
641}
642
4562236b
HW		 643static int dm_resume(void *handle)
644{
645 struct amdgpu_device *adev = handle;
4562236b
HW		 646 struct drm_device *ddev = adev->ddev;
647 struct amdgpu_display_manager *dm = &adev->dm;
c84dec2f 648 struct amdgpu_dm_connector *aconnector;
4562236b 649 struct drm_connector *connector;
4562236b 650 struct drm_crtc *crtc;
c2cea706 651 struct drm_crtc_state *new_crtc_state;
fcb4019e
LSL		 652 struct dm_crtc_state *dm_new_crtc_state;
653 struct drm_plane *plane;
654 struct drm_plane_state *new_plane_state;
655 struct dm_plane_state *dm_new_plane_state;
a80aa93d 656 int ret;
a3621485 657 int i;
4562236b 658
a80aa93d
ML		 659 /* power on hardware */
660 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
661
4562236b
HW		 662 /* program HPD filter */
663 dc_resume(dm->dc);
664
665 /* On resume we need to rewrite the MSTM control bits to enamble MST*/
666 s3_handle_mst(ddev, false);
667
668 /*
669 * early enable HPD Rx IRQ, should be done before set mode as short
670 * pulse interrupts are used for MST
671 */
672 amdgpu_dm_irq_resume_early(adev);
673
4562236b 674 /* Do detection*/
a80aa93d 675 list_for_each_entry(connector, &ddev->mode_config.connector_list, head) {
c84dec2f 676 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 677
678 /*
679 * this is the case when traversing through already created
680 * MST connectors, should be skipped
681 */
682 if (aconnector->mst_port)
683 continue;
684
03ea364c 685 mutex_lock(&aconnector->hpd_lock);
8f38b66c 686 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3eb4eba4
RL		 687
688 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
689 aconnector->fake_enable = false;
690
4562236b
HW		 691 aconnector->dc_sink = NULL;
692 amdgpu_dm_update_connector_after_detect(aconnector);
03ea364c 693 mutex_unlock(&aconnector->hpd_lock);
4562236b
HW		 694 }
695
a3621485 696 /* Force mode set in atomic comit */
a80aa93d 697 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
c2cea706 698 new_crtc_state->active_changed = true;
4f346e65 699
fcb4019e
LSL		 700 /*
701 * atomic_check is expected to create the dc states. We need to release
702 * them here, since they were duplicated as part of the suspend
703 * procedure.
704 */
a80aa93d 705 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
fcb4019e
LSL		 706 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
707 if (dm_new_crtc_state->stream) {
708 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
709 dc_stream_release(dm_new_crtc_state->stream);
710 dm_new_crtc_state->stream = NULL;
711 }
712 }
713
a80aa93d 714 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
fcb4019e
LSL		 715 dm_new_plane_state = to_dm_plane_state(new_plane_state);
716 if (dm_new_plane_state->dc_state) {
717 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
718 dc_plane_state_release(dm_new_plane_state->dc_state);
719 dm_new_plane_state->dc_state = NULL;
720 }
721 }
722
a80aa93d 723 ret = drm_atomic_helper_resume(ddev, dm->cached_state);
4562236b 724
a80aa93d 725 dm->cached_state = NULL;
0a214e2f 726
9faa4237 727 amdgpu_dm_irq_resume_late(adev);
4562236b
HW		 728
729 return ret;
730}
731
732static const struct amd_ip_funcs amdgpu_dm_funcs = {
733 .name = "dm",
734 .early_init = dm_early_init,
7abcf6b5 735 .late_init = dm_late_init,
4562236b
HW		 736 .sw_init = dm_sw_init,
737 .sw_fini = dm_sw_fini,
738 .hw_init = dm_hw_init,
739 .hw_fini = dm_hw_fini,
740 .suspend = dm_suspend,
741 .resume = dm_resume,
742 .is_idle = dm_is_idle,
743 .wait_for_idle = dm_wait_for_idle,
744 .check_soft_reset = dm_check_soft_reset,
745 .soft_reset = dm_soft_reset,
746 .set_clockgating_state = dm_set_clockgating_state,
747 .set_powergating_state = dm_set_powergating_state,
748};
749
750const struct amdgpu_ip_block_version dm_ip_block =
751{
752 .type = AMD_IP_BLOCK_TYPE_DCE,
753 .major = 1,
754 .minor = 0,
755 .rev = 0,
756 .funcs = &amdgpu_dm_funcs,
757};
758
ca3268c4 759
7578ecda 760static struct drm_atomic_state *
ca3268c4
HW		 761dm_atomic_state_alloc(struct drm_device *dev)
762{
763 struct dm_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
764
1dc90497 765 if (!state)
ca3268c4 766 return NULL;
1dc90497
AG		 767
768 if (drm_atomic_state_init(dev, &state->base) < 0)
769 goto fail;
770
ca3268c4 771 return &state->base;
1dc90497
AG		 772
773fail:
774 kfree(state);
775 return NULL;
ca3268c4
HW		 776}
777
0a323b84
AG		 778static void
779dm_atomic_state_clear(struct drm_atomic_state *state)
780{
781 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
782
783 if (dm_state->context) {
608ac7bb 784 dc_release_state(dm_state->context);
0a323b84
AG		 785 dm_state->context = NULL;
786 }
787
788 drm_atomic_state_default_clear(state);
789}
790
791static void
792dm_atomic_state_alloc_free(struct drm_atomic_state *state)
793{
794 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
795 drm_atomic_state_default_release(state);
796 kfree(dm_state);
797}
798
b3663f70 799static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
4d4772f6 800 .fb_create = amdgpu_display_user_framebuffer_create,
366c1baa 801 .output_poll_changed = drm_fb_helper_output_poll_changed,
4562236b 802 .atomic_check = amdgpu_dm_atomic_check,
da5c47f6 803 .atomic_commit = amdgpu_dm_atomic_commit,
ca3268c4 804 .atomic_state_alloc = dm_atomic_state_alloc,
0a323b84
AG		 805 .atomic_state_clear = dm_atomic_state_clear,
806 .atomic_state_free = dm_atomic_state_alloc_free
54f5499a
AG		 807};
808
809static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
810 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail
4562236b
HW		 811};
812
7578ecda 813static void
3ee6b26b 814amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
4562236b
HW		 815{
816 struct drm_connector *connector = &aconnector->base;
817 struct drm_device *dev = connector->dev;
b73a22d3 818 struct dc_sink *sink;
4562236b
HW		 819
820 /* MST handled by drm_mst framework */
821 if (aconnector->mst_mgr.mst_state == true)
822 return;
823
824
825 sink = aconnector->dc_link->local_sink;
826
827 /* Edid mgmt connector gets first update only in mode_valid hook and then
828 * the connector sink is set to either fake or physical sink depends on link status.
829 * don't do it here if u are during boot
830 */
831 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
832 && aconnector->dc_em_sink) {
833
ab2541b6 834 /* For S3 resume with headless use eml_sink to fake stream
4562236b
HW		 835 * because on resume connecotr->sink is set ti NULL
836 */
837 mutex_lock(&dev->mode_config.mutex);
838
839 if (sink) {
922aa1e1 840 if (aconnector->dc_sink) {
4562236b
HW		 841 amdgpu_dm_remove_sink_from_freesync_module(
842 connector);
922aa1e1
AG		 843 /* retain and release bellow are used for
844 * bump up refcount for sink because the link don't point
845 * to it anymore after disconnect so on next crtc to connector
846 * reshuffle by UMD we will get into unwanted dc_sink release
847 */
848 if (aconnector->dc_sink != aconnector->dc_em_sink)
849 dc_sink_release(aconnector->dc_sink);
850 }
4562236b
HW		 851 aconnector->dc_sink = sink;
852 amdgpu_dm_add_sink_to_freesync_module(
853 connector, aconnector->edid);
854 } else {
855 amdgpu_dm_remove_sink_from_freesync_module(connector);
856 if (!aconnector->dc_sink)
857 aconnector->dc_sink = aconnector->dc_em_sink;
922aa1e1
AG		 858 else if (aconnector->dc_sink != aconnector->dc_em_sink)
859 dc_sink_retain(aconnector->dc_sink);
4562236b
HW		 860 }
861
862 mutex_unlock(&dev->mode_config.mutex);
863 return;
864 }
865
866 /*
867 * TODO: temporary guard to look for proper fix
868 * if this sink is MST sink, we should not do anything
869 */
870 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
871 return;
872
873 if (aconnector->dc_sink == sink) {
874 /* We got a DP short pulse (Link Loss, DP CTS, etc...).
875 * Do nothing!! */
f1ad2f5e 876 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
4562236b
HW		 877 aconnector->connector_id);
878 return;
879 }
880
f1ad2f5e 881 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
4562236b
HW		 882 aconnector->connector_id, aconnector->dc_sink, sink);
883
884 mutex_lock(&dev->mode_config.mutex);
885
886 /* 1. Update status of the drm connector
887 * 2. Send an event and let userspace tell us what to do */
888 if (sink) {
889 /* TODO: check if we still need the S3 mode update workaround.
890 * If yes, put it here. */
891 if (aconnector->dc_sink)
892 amdgpu_dm_remove_sink_from_freesync_module(
893 connector);
894
895 aconnector->dc_sink = sink;
900b3cb1 896 if (sink->dc_edid.length == 0) {
4562236b 897 aconnector->edid = NULL;
900b3cb1 898 } else {
4562236b
HW		 899 aconnector->edid =
900 (struct edid *) sink->dc_edid.raw_edid;
901
902
c555f023 903 drm_connector_update_edid_property(connector,
4562236b
HW		 904 aconnector->edid);
905 }
906 amdgpu_dm_add_sink_to_freesync_module(connector, aconnector->edid);
907
908 } else {
909 amdgpu_dm_remove_sink_from_freesync_module(connector);
c555f023 910 drm_connector_update_edid_property(connector, NULL);
4562236b
HW		 911 aconnector->num_modes = 0;
912 aconnector->dc_sink = NULL;
5326c452 913 aconnector->edid = NULL;
4562236b
HW		 914 }
915
916 mutex_unlock(&dev->mode_config.mutex);
917}
918
919static void handle_hpd_irq(void *param)
920{
c84dec2f 921 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
4562236b
HW		 922 struct drm_connector *connector = &aconnector->base;
923 struct drm_device *dev = connector->dev;
924
925 /* In case of failure or MST no need to update connector status or notify the OS
926 * since (for MST case) MST does this in it's own context.
927 */
928 mutex_lock(&aconnector->hpd_lock);
2e0ac3d6
HW		 929
930 if (aconnector->fake_enable)
931 aconnector->fake_enable = false;
932
8f38b66c 933 if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
4562236b
HW		 934 amdgpu_dm_update_connector_after_detect(aconnector);
935
936
937 drm_modeset_lock_all(dev);
938 dm_restore_drm_connector_state(dev, connector);
939 drm_modeset_unlock_all(dev);
940
941 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
942 drm_kms_helper_hotplug_event(dev);
943 }
944 mutex_unlock(&aconnector->hpd_lock);
945
946}
947
c84dec2f 948static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector)
4562236b
HW		 949{
950 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
951 uint8_t dret;
952 bool new_irq_handled = false;
953 int dpcd_addr;
954 int dpcd_bytes_to_read;
955
956 const int max_process_count = 30;
957 int process_count = 0;
958
959 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
960
961 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
962 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
963 /* DPCD 0x200 - 0x201 for downstream IRQ */
964 dpcd_addr = DP_SINK_COUNT;
965 } else {
966 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
967 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
968 dpcd_addr = DP_SINK_COUNT_ESI;
969 }
970
971 dret = drm_dp_dpcd_read(
972 &aconnector->dm_dp_aux.aux,
973 dpcd_addr,
974 esi,
975 dpcd_bytes_to_read);
976
977 while (dret == dpcd_bytes_to_read &&
978 process_count < max_process_count) {
979 uint8_t retry;
980 dret = 0;
981
982 process_count++;
983
f1ad2f5e 984 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
4562236b
HW		 985 /* handle HPD short pulse irq */
986 if (aconnector->mst_mgr.mst_state)
987 drm_dp_mst_hpd_irq(
988 &aconnector->mst_mgr,
989 esi,
990 &new_irq_handled);
4562236b
HW		 991
992 if (new_irq_handled) {
993 /* ACK at DPCD to notify down stream */
994 const int ack_dpcd_bytes_to_write =
995 dpcd_bytes_to_read - 1;
996
997 for (retry = 0; retry < 3; retry++) {
998 uint8_t wret;
999
1000 wret = drm_dp_dpcd_write(
1001 &aconnector->dm_dp_aux.aux,
1002 dpcd_addr + 1,
1003 &esi[1],
1004 ack_dpcd_bytes_to_write);
1005 if (wret == ack_dpcd_bytes_to_write)
1006 break;
1007 }
1008
1009 /* check if there is new irq to be handle */
1010 dret = drm_dp_dpcd_read(
1011 &aconnector->dm_dp_aux.aux,
1012 dpcd_addr,
1013 esi,
1014 dpcd_bytes_to_read);
1015
1016 new_irq_handled = false;
d4a6e8a9 1017 } else {
4562236b 1018 break;
d4a6e8a9 1019 }
4562236b
HW		 1020 }
1021
1022 if (process_count == max_process_count)
f1ad2f5e 1023 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
4562236b
HW		 1024}
1025
1026static void handle_hpd_rx_irq(void *param)
1027{
c84dec2f 1028 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
4562236b
HW		 1029 struct drm_connector *connector = &aconnector->base;
1030 struct drm_device *dev = connector->dev;
53cbf65c 1031 struct dc_link *dc_link = aconnector->dc_link;
4562236b
HW		 1032 bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
1033
1034 /* TODO:Temporary add mutex to protect hpd interrupt not have a gpio
1035 * conflict, after implement i2c helper, this mutex should be
1036 * retired.
1037 */
53cbf65c 1038 if (dc_link->type != dc_connection_mst_branch)
4562236b
HW		 1039 mutex_lock(&aconnector->hpd_lock);
1040
53cbf65c 1041 if (dc_link_handle_hpd_rx_irq(dc_link, NULL) &&
4562236b
HW		 1042 !is_mst_root_connector) {
1043 /* Downstream Port status changed. */
53cbf65c 1044 if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) {
88ac3dda
RL		 1045
1046 if (aconnector->fake_enable)
1047 aconnector->fake_enable = false;
1048
4562236b
HW		 1049 amdgpu_dm_update_connector_after_detect(aconnector);
1050
1051
1052 drm_modeset_lock_all(dev);
1053 dm_restore_drm_connector_state(dev, connector);
1054 drm_modeset_unlock_all(dev);
1055
1056 drm_kms_helper_hotplug_event(dev);
1057 }
1058 }
1059 if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
53cbf65c 1060 (dc_link->type == dc_connection_mst_branch))
4562236b
HW		 1061 dm_handle_hpd_rx_irq(aconnector);
1062
53cbf65c 1063 if (dc_link->type != dc_connection_mst_branch)
4562236b
HW		 1064 mutex_unlock(&aconnector->hpd_lock);
1065}
1066
1067static void register_hpd_handlers(struct amdgpu_device *adev)
1068{
1069 struct drm_device *dev = adev->ddev;
1070 struct drm_connector *connector;
c84dec2f 1071 struct amdgpu_dm_connector *aconnector;
4562236b
HW		 1072 const struct dc_link *dc_link;
1073 struct dc_interrupt_params int_params = {0};
1074
1075 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1076 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1077
1078 list_for_each_entry(connector,
1079 &dev->mode_config.connector_list, head) {
1080
c84dec2f 1081 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 1082 dc_link = aconnector->dc_link;
1083
1084 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
1085 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1086 int_params.irq_source = dc_link->irq_source_hpd;
1087
1088 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1089 handle_hpd_irq,
1090 (void *) aconnector);
1091 }
1092
1093 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
1094
1095 /* Also register for DP short pulse (hpd_rx). */
1096 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1097 int_params.irq_source = dc_link->irq_source_hpd_rx;
1098
1099 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1100 handle_hpd_rx_irq,
1101 (void *) aconnector);
1102 }
1103 }
1104}
1105
1106/* Register IRQ sources and initialize IRQ callbacks */
1107static int dce110_register_irq_handlers(struct amdgpu_device *adev)
1108{
1109 struct dc *dc = adev->dm.dc;
1110 struct common_irq_params *c_irq_params;
1111 struct dc_interrupt_params int_params = {0};
1112 int r;
1113 int i;
2c8ad2d5
AD		 1114 unsigned client_id = AMDGPU_IH_CLIENTID_LEGACY;
1115
ff5ef992 1116 if (adev->asic_type == CHIP_VEGA10 ||
2325ff30 1117 adev->asic_type == CHIP_VEGA12 ||
1fe6bf2f 1118 adev->asic_type == CHIP_VEGA20 ||
ff5ef992 1119 adev->asic_type == CHIP_RAVEN)
3760f76c 1120 client_id = SOC15_IH_CLIENTID_DCE;
4562236b
HW		 1121
1122 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1123 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1124
1125 /* Actions of amdgpu_irq_add_id():
1126 * 1. Register a set() function with base driver.
1127 * Base driver will call set() function to enable/disable an
1128 * interrupt in DC hardware.
1129 * 2. Register amdgpu_dm_irq_handler().
1130 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1131 * coming from DC hardware.
1132 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1133 * for acknowledging and handling. */
1134
b57de80a 1135 /* Use VBLANK interrupt */
e9029155 1136 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
2c8ad2d5 1137 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
4562236b
HW		 1138 if (r) {
1139 DRM_ERROR("Failed to add crtc irq id!\n");
1140 return r;
1141 }
1142
1143 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1144 int_params.irq_source =
3d761e79 1145 dc_interrupt_to_irq_source(dc, i, 0);
4562236b 1146
b57de80a 1147 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
4562236b
HW		 1148
1149 c_irq_params->adev = adev;
1150 c_irq_params->irq_src = int_params.irq_source;
1151
1152 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1153 dm_crtc_high_irq, c_irq_params);
1154 }
1155
3d761e79 1156 /* Use GRPH_PFLIP interrupt */
4562236b
HW		 1157 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
1158 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
2c8ad2d5 1159 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
4562236b
HW		 1160 if (r) {
1161 DRM_ERROR("Failed to add page flip irq id!\n");
1162 return r;
1163 }
1164
1165 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1166 int_params.irq_source =
1167 dc_interrupt_to_irq_source(dc, i, 0);
1168
1169 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1170
1171 c_irq_params->adev = adev;
1172 c_irq_params->irq_src = int_params.irq_source;
1173
1174 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1175 dm_pflip_high_irq, c_irq_params);
1176
1177 }
1178
1179 /* HPD */
2c8ad2d5
AD		 1180 r = amdgpu_irq_add_id(adev, client_id,
1181 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
4562236b
HW		 1182 if (r) {
1183 DRM_ERROR("Failed to add hpd irq id!\n");
1184 return r;
1185 }
1186
1187 register_hpd_handlers(adev);
1188
1189 return 0;
1190}
1191
ff5ef992
AD		 1192#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1193/* Register IRQ sources and initialize IRQ callbacks */
1194static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
1195{
1196 struct dc *dc = adev->dm.dc;
1197 struct common_irq_params *c_irq_params;
1198 struct dc_interrupt_params int_params = {0};
1199 int r;
1200 int i;
1201
1202 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1203 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1204
1205 /* Actions of amdgpu_irq_add_id():
1206 * 1. Register a set() function with base driver.
1207 * Base driver will call set() function to enable/disable an
1208 * interrupt in DC hardware.
1209 * 2. Register amdgpu_dm_irq_handler().
1210 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1211 * coming from DC hardware.
1212 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1213 * for acknowledging and handling.
1214 * */
1215
1216 /* Use VSTARTUP interrupt */
1217 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
1218 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
1219 i++) {
3760f76c 1220 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
ff5ef992
AD		 1221
1222 if (r) {
1223 DRM_ERROR("Failed to add crtc irq id!\n");
1224 return r;
1225 }
1226
1227 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1228 int_params.irq_source =
1229 dc_interrupt_to_irq_source(dc, i, 0);
1230
1231 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1232
1233 c_irq_params->adev = adev;
1234 c_irq_params->irq_src = int_params.irq_source;
1235
1236 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1237 dm_crtc_high_irq, c_irq_params);
1238 }
1239
1240 /* Use GRPH_PFLIP interrupt */
1241 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
1242 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
1243 i++) {
3760f76c 1244 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
ff5ef992
AD		 1245 if (r) {
1246 DRM_ERROR("Failed to add page flip irq id!\n");
1247 return r;
1248 }
1249
1250 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1251 int_params.irq_source =
1252 dc_interrupt_to_irq_source(dc, i, 0);
1253
1254 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1255
1256 c_irq_params->adev = adev;
1257 c_irq_params->irq_src = int_params.irq_source;
1258
1259 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1260 dm_pflip_high_irq, c_irq_params);
1261
1262 }
1263
1264 /* HPD */
3760f76c 1265 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
ff5ef992
AD		 1266 &adev->hpd_irq);
1267 if (r) {
1268 DRM_ERROR("Failed to add hpd irq id!\n");
1269 return r;
1270 }
1271
1272 register_hpd_handlers(adev);
1273
1274 return 0;
1275}
1276#endif
1277
4562236b
HW		 1278static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
1279{
1280 int r;
1281
1282 adev->mode_info.mode_config_initialized = true;
1283
4562236b 1284 adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
54f5499a 1285 adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
4562236b
HW		 1286
1287 adev->ddev->mode_config.max_width = 16384;
1288 adev->ddev->mode_config.max_height = 16384;
1289
1290 adev->ddev->mode_config.preferred_depth = 24;
1291 adev->ddev->mode_config.prefer_shadow = 1;
1292 /* indicate support of immediate flip */
1293 adev->ddev->mode_config.async_page_flip = true;
1294
770d13b1 1295 adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
4562236b 1296
3dc9b1ce 1297 r = amdgpu_display_modeset_create_props(adev);
4562236b
HW		 1298 if (r)
1299 return r;
1300
1301 return 0;
1302}
1303
1304#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1305 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1306
1307static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
1308{
1309 struct amdgpu_display_manager *dm = bl_get_data(bd);
1310
1311 if (dc_link_set_backlight_level(dm->backlight_link,
1312 bd->props.brightness, 0, 0))
1313 return 0;
1314 else
1315 return 1;
1316}
1317
1318static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
1319{
1320 return bd->props.brightness;
1321}
1322
1323static const struct backlight_ops amdgpu_dm_backlight_ops = {
1324 .get_brightness = amdgpu_dm_backlight_get_brightness,
1325 .update_status = amdgpu_dm_backlight_update_status,
1326};
1327
7578ecda
AD		 1328static void
1329amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
4562236b
HW		 1330{
1331 char bl_name[16];
1332 struct backlight_properties props = { 0 };
1333
1334 props.max_brightness = AMDGPU_MAX_BL_LEVEL;
1335 props.type = BACKLIGHT_RAW;
1336
1337 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
1338 dm->adev->ddev->primary->index);
1339
1340 dm->backlight_dev = backlight_device_register(bl_name,
1341 dm->adev->ddev->dev,
1342 dm,
1343 &amdgpu_dm_backlight_ops,
1344 &props);
1345
74baea42 1346 if (IS_ERR(dm->backlight_dev))
4562236b
HW		 1347 DRM_ERROR("DM: Backlight registration failed!\n");
1348 else
f1ad2f5e 1349 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4562236b
HW		 1350}
1351
1352#endif
1353
df534fff
S		 1354static int initialize_plane(struct amdgpu_display_manager *dm,
1355 struct amdgpu_mode_info *mode_info,
1356 int plane_id)
1357{
1358 struct amdgpu_plane *plane;
1359 unsigned long possible_crtcs;
1360 int ret = 0;
1361
1362 plane = kzalloc(sizeof(struct amdgpu_plane), GFP_KERNEL);
1363 mode_info->planes[plane_id] = plane;
1364
1365 if (!plane) {
1366 DRM_ERROR("KMS: Failed to allocate plane\n");
1367 return -ENOMEM;
1368 }
1369 plane->base.type = mode_info->plane_type[plane_id];
1370
1371 /*
1372 * HACK: IGT tests expect that each plane can only have one
1373 * one possible CRTC. For now, set one CRTC for each
1374 * plane that is not an underlay, but still allow multiple
1375 * CRTCs for underlay planes.
1376 */
1377 possible_crtcs = 1 << plane_id;
1378 if (plane_id >= dm->dc->caps.max_streams)
1379 possible_crtcs = 0xff;
1380
1381 ret = amdgpu_dm_plane_init(dm, mode_info->planes[plane_id], possible_crtcs);
1382
1383 if (ret) {
1384 DRM_ERROR("KMS: Failed to initialize plane\n");
1385 return ret;
1386 }
1387
1388 return ret;
1389}
1390
89fc8d4e
HW		 1391
1392static void register_backlight_device(struct amdgpu_display_manager *dm,
1393 struct dc_link *link)
1394{
1395#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1396 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1397
1398 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
1399 link->type != dc_connection_none) {
1400 /* Event if registration failed, we should continue with
1401 * DM initialization because not having a backlight control
1402 * is better then a black screen.
1403 */
1404 amdgpu_dm_register_backlight_device(dm);
1405
1406 if (dm->backlight_dev)
1407 dm->backlight_link = link;
1408 }
1409#endif
1410}
1411
1412
4562236b
HW		 1413/* In this architecture, the association
1414 * connector -> encoder -> crtc
1415 * id not really requried. The crtc and connector will hold the
1416 * display_index as an abstraction to use with DAL component
1417 *
1418 * Returns 0 on success
1419 */
7578ecda 1420static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4562236b
HW		 1421{
1422 struct amdgpu_display_manager *dm = &adev->dm;
df534fff 1423 int32_t i;
c84dec2f 1424 struct amdgpu_dm_connector *aconnector = NULL;
f2a0f5e6 1425 struct amdgpu_encoder *aencoder = NULL;
d4e13b0d 1426 struct amdgpu_mode_info *mode_info = &adev->mode_info;
4562236b 1427 uint32_t link_cnt;
df534fff 1428 int32_t total_overlay_planes, total_primary_planes;
4562236b
HW		 1429
1430 link_cnt = dm->dc->caps.max_links;
4562236b
HW		 1431 if (amdgpu_dm_mode_config_init(dm->adev)) {
1432 DRM_ERROR("DM: Failed to initialize mode config\n");
f2a0f5e6 1433 return -1;
4562236b
HW		 1434 }
1435
df534fff
S		 1436 /* Identify the number of planes to be initialized */
1437 total_overlay_planes = dm->dc->caps.max_slave_planes;
1438 total_primary_planes = dm->dc->caps.max_planes - dm->dc->caps.max_slave_planes;
efa6a8b7 1439
df534fff
S		 1440 /* First initialize overlay planes, index starting after primary planes */
1441 for (i = (total_overlay_planes - 1); i >= 0; i--) {
1442 if (initialize_plane(dm, mode_info, (total_primary_planes + i))) {
1443 DRM_ERROR("KMS: Failed to initialize overlay plane\n");
cd8a2ae8 1444 goto fail;
d4e13b0d 1445 }
df534fff 1446 }
92f3ac40 1447
df534fff
S		 1448 /* Initialize primary planes */
1449 for (i = (total_primary_planes - 1); i >= 0; i--) {
1450 if (initialize_plane(dm, mode_info, i)) {
1451 DRM_ERROR("KMS: Failed to initialize primary plane\n");
cd8a2ae8 1452 goto fail;
d4e13b0d
AD		 1453 }
1454 }
4562236b 1455
d4e13b0d
AD		 1456 for (i = 0; i < dm->dc->caps.max_streams; i++)
1457 if (amdgpu_dm_crtc_init(dm, &mode_info->planes[i]->base, i)) {
4562236b 1458 DRM_ERROR("KMS: Failed to initialize crtc\n");
cd8a2ae8 1459 goto fail;
4562236b 1460 }
4562236b 1461
ab2541b6 1462 dm->display_indexes_num = dm->dc->caps.max_streams;
4562236b
HW		 1463
1464 /* loops over all connectors on the board */
1465 for (i = 0; i < link_cnt; i++) {
89fc8d4e 1466 struct dc_link *link = NULL;
4562236b
HW		 1467
1468 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
1469 DRM_ERROR(
1470 "KMS: Cannot support more than %d display indexes\n",
1471 AMDGPU_DM_MAX_DISPLAY_INDEX);
1472 continue;
1473 }
1474
1475 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
1476 if (!aconnector)
cd8a2ae8 1477 goto fail;
4562236b
HW		 1478
1479 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
8440c304 1480 if (!aencoder)
cd8a2ae8 1481 goto fail;
4562236b
HW		 1482
1483 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
1484 DRM_ERROR("KMS: Failed to initialize encoder\n");
cd8a2ae8 1485 goto fail;
4562236b
HW		 1486 }
1487
1488 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
1489 DRM_ERROR("KMS: Failed to initialize connector\n");
cd8a2ae8 1490 goto fail;
4562236b
HW		 1491 }
1492
89fc8d4e
HW		 1493 link = dc_get_link_at_index(dm->dc, i);
1494
1495 if (dc_link_detect(link, DETECT_REASON_BOOT)) {
4562236b 1496 amdgpu_dm_update_connector_after_detect(aconnector);
89fc8d4e
HW		 1497 register_backlight_device(dm, link);
1498 }
1499
1500
4562236b
HW		 1501 }
1502
1503 /* Software is initialized. Now we can register interrupt handlers. */
1504 switch (adev->asic_type) {
1505 case CHIP_BONAIRE:
1506 case CHIP_HAWAII:
cd4b356f
AD		 1507 case CHIP_KAVERI:
1508 case CHIP_KABINI:
1509 case CHIP_MULLINS:
4562236b
HW		 1510 case CHIP_TONGA:
1511 case CHIP_FIJI:
1512 case CHIP_CARRIZO:
1513 case CHIP_STONEY:
1514 case CHIP_POLARIS11:
1515 case CHIP_POLARIS10:
b264d345 1516 case CHIP_POLARIS12:
7737de91 1517 case CHIP_VEGAM:
2c8ad2d5 1518 case CHIP_VEGA10:
2325ff30 1519 case CHIP_VEGA12:
1fe6bf2f 1520 case CHIP_VEGA20:
4562236b
HW		 1521 if (dce110_register_irq_handlers(dm->adev)) {
1522 DRM_ERROR("DM: Failed to initialize IRQ\n");
cd8a2ae8 1523 goto fail;
4562236b
HW		 1524 }
1525 break;
ff5ef992
AD		 1526#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1527 case CHIP_RAVEN:
1528 if (dcn10_register_irq_handlers(dm->adev)) {
1529 DRM_ERROR("DM: Failed to initialize IRQ\n");
cd8a2ae8 1530 goto fail;
ff5ef992 1531 }
79c24086
BL		 1532 /*
1533 * Temporary disable until pplib/smu interaction is implemented
1534 */
1535 dm->dc->debug.disable_stutter = true;
ff5ef992
AD		 1536 break;
1537#endif
4562236b 1538 default:
e63f8673 1539 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
cd8a2ae8 1540 goto fail;
4562236b
HW		 1541 }
1542
4562236b 1543 return 0;
cd8a2ae8 1544fail:
4562236b 1545 kfree(aencoder);
4562236b 1546 kfree(aconnector);
3be5262e 1547 for (i = 0; i < dm->dc->caps.max_planes; i++)
d4e13b0d 1548 kfree(mode_info->planes[i]);
4562236b
HW		 1549 return -1;
1550}
1551
7578ecda 1552static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4562236b
HW		 1553{
1554 drm_mode_config_cleanup(dm->ddev);
1555 return;
1556}
1557
1558/******************************************************************************
1559 * amdgpu_display_funcs functions
1560 *****************************************************************************/
1561
1562/**
1563 * dm_bandwidth_update - program display watermarks
1564 *
1565 * @adev: amdgpu_device pointer
1566 *
1567 * Calculate and program the display watermarks and line buffer allocation.
1568 */
1569static void dm_bandwidth_update(struct amdgpu_device *adev)
1570{
49c07a99 1571 /* TODO: implement later */
4562236b
HW		 1572}
1573
1574static void dm_set_backlight_level(struct amdgpu_encoder *amdgpu_encoder,
1575 u8 level)
1576{
1577 /* TODO: translate amdgpu_encoder to display_index and call DAL */
4562236b
HW		 1578}
1579
1580static u8 dm_get_backlight_level(struct amdgpu_encoder *amdgpu_encoder)
1581{
1582 /* TODO: translate amdgpu_encoder to display_index and call DAL */
4562236b
HW		 1583 return 0;
1584}
1585
4562236b
HW		 1586static int amdgpu_notify_freesync(struct drm_device *dev, void *data,
1587 struct drm_file *filp)
1588{
1589 struct mod_freesync_params freesync_params;
ab2541b6 1590 uint8_t num_streams;
4562236b 1591 uint8_t i;
4562236b
HW		 1592
1593 struct amdgpu_device *adev = dev->dev_private;
1594 int r = 0;
1595
1596 /* Get freesync enable flag from DRM */
1597
ab2541b6 1598 num_streams = dc_get_current_stream_count(adev->dm.dc);
4562236b 1599
ab2541b6 1600 for (i = 0; i < num_streams; i++) {
0971c40e 1601 struct dc_stream_state *stream;
ab2541b6 1602 stream = dc_get_stream_at_index(adev->dm.dc, i);
4562236b
HW		 1603
1604 mod_freesync_update_state(adev->dm.freesync_module,
ab2541b6 1605 &stream, 1, &freesync_params);
4562236b
HW		 1606 }
1607
1608 return r;
1609}
1610
39cc5be2 1611static const struct amdgpu_display_funcs dm_display_funcs = {
4562236b
HW		 1612 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
1613 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
4562236b
HW		 1614 .backlight_set_level =
1615 dm_set_backlight_level,/* called unconditionally */
1616 .backlight_get_level =
1617 dm_get_backlight_level,/* called unconditionally */
1618 .hpd_sense = NULL,/* called unconditionally */
1619 .hpd_set_polarity = NULL, /* called unconditionally */
1620 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4562236b
HW		 1621 .page_flip_get_scanoutpos =
1622 dm_crtc_get_scanoutpos,/* called unconditionally */
1623 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
1624 .add_connector = NULL, /* VBIOS parsing. DAL does it. */
1625 .notify_freesync = amdgpu_notify_freesync,
1626
1627};
1628
1629#if defined(CONFIG_DEBUG_KERNEL_DC)
1630
3ee6b26b
AD		 1631static ssize_t s3_debug_store(struct device *device,
1632 struct device_attribute *attr,
1633 const char *buf,
1634 size_t count)
4562236b
HW		 1635{
1636 int ret;
1637 int s3_state;
1638 struct pci_dev *pdev = to_pci_dev(device);
1639 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1640 struct amdgpu_device *adev = drm_dev->dev_private;
1641
1642 ret = kstrtoint(buf, 0, &s3_state);
1643
1644 if (ret == 0) {
1645 if (s3_state) {
1646 dm_resume(adev);
4562236b
HW		 1647 drm_kms_helper_hotplug_event(adev->ddev);
1648 } else
1649 dm_suspend(adev);
1650 }
1651
1652 return ret == 0 ? count : 0;
1653}
1654
1655DEVICE_ATTR_WO(s3_debug);
1656
1657#endif
1658
1659static int dm_early_init(void *handle)
1660{
1661 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1662
4562236b
HW		 1663 switch (adev->asic_type) {
1664 case CHIP_BONAIRE:
1665 case CHIP_HAWAII:
1666 adev->mode_info.num_crtc = 6;
1667 adev->mode_info.num_hpd = 6;
1668 adev->mode_info.num_dig = 6;
3be5262e 1669 adev->mode_info.plane_type = dm_plane_type_default;
4562236b 1670 break;
cd4b356f
AD		 1671 case CHIP_KAVERI:
1672 adev->mode_info.num_crtc = 4;
1673 adev->mode_info.num_hpd = 6;
1674 adev->mode_info.num_dig = 7;
1675 adev->mode_info.plane_type = dm_plane_type_default;
1676 break;
1677 case CHIP_KABINI:
1678 case CHIP_MULLINS:
1679 adev->mode_info.num_crtc = 2;
1680 adev->mode_info.num_hpd = 6;
1681 adev->mode_info.num_dig = 6;
1682 adev->mode_info.plane_type = dm_plane_type_default;
1683 break;
4562236b
HW		 1684 case CHIP_FIJI:
1685 case CHIP_TONGA:
1686 adev->mode_info.num_crtc = 6;
1687 adev->mode_info.num_hpd = 6;
1688 adev->mode_info.num_dig = 7;
3be5262e 1689 adev->mode_info.plane_type = dm_plane_type_default;
4562236b
HW		 1690 break;
1691 case CHIP_CARRIZO:
1692 adev->mode_info.num_crtc = 3;
1693 adev->mode_info.num_hpd = 6;
1694 adev->mode_info.num_dig = 9;
3be5262e 1695 adev->mode_info.plane_type = dm_plane_type_carizzo;
4562236b
HW		 1696 break;
1697 case CHIP_STONEY:
1698 adev->mode_info.num_crtc = 2;
1699 adev->mode_info.num_hpd = 6;
1700 adev->mode_info.num_dig = 9;
3be5262e 1701 adev->mode_info.plane_type = dm_plane_type_stoney;
4562236b
HW		 1702 break;
1703 case CHIP_POLARIS11:
b264d345 1704 case CHIP_POLARIS12:
4562236b
HW		 1705 adev->mode_info.num_crtc = 5;
1706 adev->mode_info.num_hpd = 5;
1707 adev->mode_info.num_dig = 5;
3be5262e 1708 adev->mode_info.plane_type = dm_plane_type_default;
4562236b
HW		 1709 break;
1710 case CHIP_POLARIS10:
7737de91 1711 case CHIP_VEGAM:
4562236b
HW		 1712 adev->mode_info.num_crtc = 6;
1713 adev->mode_info.num_hpd = 6;
1714 adev->mode_info.num_dig = 6;
3be5262e 1715 adev->mode_info.plane_type = dm_plane_type_default;
4562236b 1716 break;
2c8ad2d5 1717 case CHIP_VEGA10:
2325ff30 1718 case CHIP_VEGA12:
1fe6bf2f 1719 case CHIP_VEGA20:
2c8ad2d5
AD		 1720 adev->mode_info.num_crtc = 6;
1721 adev->mode_info.num_hpd = 6;
1722 adev->mode_info.num_dig = 6;
3be5262e 1723 adev->mode_info.plane_type = dm_plane_type_default;
2c8ad2d5 1724 break;
ff5ef992
AD		 1725#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1726 case CHIP_RAVEN:
1727 adev->mode_info.num_crtc = 4;
1728 adev->mode_info.num_hpd = 4;
1729 adev->mode_info.num_dig = 4;
3be5262e 1730 adev->mode_info.plane_type = dm_plane_type_default;
ff5ef992
AD		 1731 break;
1732#endif
4562236b 1733 default:
e63f8673 1734 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
4562236b
HW		 1735 return -EINVAL;
1736 }
1737
c8dd5715
MD		 1738 amdgpu_dm_set_irq_funcs(adev);
1739
39cc5be2
AD		 1740 if (adev->mode_info.funcs == NULL)
1741 adev->mode_info.funcs = &dm_display_funcs;
1742
4562236b
HW		 1743 /* Note: Do NOT change adev->audio_endpt_rreg and
1744 * adev->audio_endpt_wreg because they are initialised in
1745 * amdgpu_device_init() */
1746#if defined(CONFIG_DEBUG_KERNEL_DC)
1747 device_create_file(
1748 adev->ddev->dev,
1749 &dev_attr_s3_debug);
1750#endif
1751
1752 return 0;
1753}
1754
9b690ef3 1755static bool modeset_required(struct drm_crtc_state *crtc_state,
0971c40e
HW		 1756 struct dc_stream_state *new_stream,
1757 struct dc_stream_state *old_stream)
9b690ef3 1758{
e7b07cee
HW		 1759 if (!drm_atomic_crtc_needs_modeset(crtc_state))
1760 return false;
1761
1762 if (!crtc_state->enable)
1763 return false;
1764
1765 return crtc_state->active;
1766}
1767
1768static bool modereset_required(struct drm_crtc_state *crtc_state)
1769{
1770 if (!drm_atomic_crtc_needs_modeset(crtc_state))
1771 return false;
1772
1773 return !crtc_state->enable || !crtc_state->active;
1774}
1775
7578ecda 1776static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
e7b07cee
HW		 1777{
1778 drm_encoder_cleanup(encoder);
1779 kfree(encoder);
1780}
1781
1782static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
1783 .destroy = amdgpu_dm_encoder_destroy,
1784};
1785
3ee6b26b
AD		 1786static bool fill_rects_from_plane_state(const struct drm_plane_state *state,
1787 struct dc_plane_state *plane_state)
e7b07cee 1788{
3be5262e
HW		 1789 plane_state->src_rect.x = state->src_x >> 16;
1790 plane_state->src_rect.y = state->src_y >> 16;
e7b07cee 1791 /*we ignore for now mantissa and do not to deal with floating pixels :(*/
3be5262e 1792 plane_state->src_rect.width = state->src_w >> 16;
e7b07cee 1793
3be5262e 1794 if (plane_state->src_rect.width == 0)
e7b07cee
HW		 1795 return false;
1796
3be5262e
HW		 1797 plane_state->src_rect.height = state->src_h >> 16;
1798 if (plane_state->src_rect.height == 0)
e7b07cee
HW		 1799 return false;
1800
3be5262e
HW		 1801 plane_state->dst_rect.x = state->crtc_x;
1802 plane_state->dst_rect.y = state->crtc_y;
e7b07cee
HW		 1803
1804 if (state->crtc_w == 0)
1805 return false;
1806
3be5262e 1807 plane_state->dst_rect.width = state->crtc_w;
e7b07cee
HW		 1808
1809 if (state->crtc_h == 0)
1810 return false;
1811
3be5262e 1812 plane_state->dst_rect.height = state->crtc_h;
e7b07cee 1813
3be5262e 1814 plane_state->clip_rect = plane_state->dst_rect;
e7b07cee
HW		 1815
1816 switch (state->rotation & DRM_MODE_ROTATE_MASK) {
1817 case DRM_MODE_ROTATE_0:
3be5262e 1818 plane_state->rotation = ROTATION_ANGLE_0;
e7b07cee
HW		 1819 break;
1820 case DRM_MODE_ROTATE_90:
3be5262e 1821 plane_state->rotation = ROTATION_ANGLE_90;
e7b07cee
HW		 1822 break;
1823 case DRM_MODE_ROTATE_180:
3be5262e 1824 plane_state->rotation = ROTATION_ANGLE_180;
e7b07cee
HW		 1825 break;
1826 case DRM_MODE_ROTATE_270:
3be5262e 1827 plane_state->rotation = ROTATION_ANGLE_270;
e7b07cee
HW		 1828 break;
1829 default:
3be5262e 1830 plane_state->rotation = ROTATION_ANGLE_0;
e7b07cee
HW		 1831 break;
1832 }
1833
4562236b
HW		 1834 return true;
1835}
3ee6b26b 1836static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
9817d5f5 1837 uint64_t *tiling_flags)
e7b07cee 1838{
e68d14dd 1839 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
e7b07cee 1840 int r = amdgpu_bo_reserve(rbo, false);
b830ebc9 1841
e7b07cee 1842 if (unlikely(r)) {
9bbc3031
JZ		 1843 // Don't show error msg. when return -ERESTARTSYS
1844 if (r != -ERESTARTSYS)
1845 DRM_ERROR("Unable to reserve buffer: %d\n", r);
e7b07cee
HW		 1846 return r;
1847 }
1848
e7b07cee
HW		 1849 if (tiling_flags)
1850 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
1851
1852 amdgpu_bo_unreserve(rbo);
1853
1854 return r;
1855}
1856
3ee6b26b
AD		 1857static int fill_plane_attributes_from_fb(struct amdgpu_device *adev,
1858 struct dc_plane_state *plane_state,
9817d5f5 1859 const struct amdgpu_framebuffer *amdgpu_fb)
e7b07cee
HW		 1860{
1861 uint64_t tiling_flags;
e7b07cee
HW		 1862 unsigned int awidth;
1863 const struct drm_framebuffer *fb = &amdgpu_fb->base;
1864 int ret = 0;
1865 struct drm_format_name_buf format_name;
1866
1867 ret = get_fb_info(
1868 amdgpu_fb,
9817d5f5 1869 &tiling_flags);
e7b07cee
HW		 1870
1871 if (ret)
1872 return ret;
1873
1874 switch (fb->format->format) {
1875 case DRM_FORMAT_C8:
3be5262e 1876 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
e7b07cee
HW		 1877 break;
1878 case DRM_FORMAT_RGB565:
3be5262e 1879 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
e7b07cee
HW		 1880 break;
1881 case DRM_FORMAT_XRGB8888:
1882 case DRM_FORMAT_ARGB8888:
3be5262e 1883 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
e7b07cee
HW		 1884 break;
1885 case DRM_FORMAT_XRGB2101010:
1886 case DRM_FORMAT_ARGB2101010:
3be5262e 1887 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
e7b07cee
HW		 1888 break;
1889 case DRM_FORMAT_XBGR2101010:
1890 case DRM_FORMAT_ABGR2101010:
3be5262e 1891 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
e7b07cee
HW		 1892 break;
1893 case DRM_FORMAT_NV21:
3be5262e 1894 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
e7b07cee
HW		 1895 break;
1896 case DRM_FORMAT_NV12:
3be5262e 1897 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
e7b07cee
HW		 1898 break;
1899 default:
1900 DRM_ERROR("Unsupported screen format %s\n",
1ecfc3da 1901 drm_get_format_name(fb->format->format, &format_name));
e7b07cee
HW		 1902 return -EINVAL;
1903 }
1904
3be5262e
HW		 1905 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
1906 plane_state->address.type = PLN_ADDR_TYPE_GRAPHICS;
3be5262e
HW		 1907 plane_state->plane_size.grph.surface_size.x = 0;
1908 plane_state->plane_size.grph.surface_size.y = 0;
1909 plane_state->plane_size.grph.surface_size.width = fb->width;
1910 plane_state->plane_size.grph.surface_size.height = fb->height;
1911 plane_state->plane_size.grph.surface_pitch =
e7b07cee
HW		 1912 fb->pitches[0] / fb->format->cpp[0];
1913 /* TODO: unhardcode */
3be5262e 1914 plane_state->color_space = COLOR_SPACE_SRGB;
e7b07cee
HW		 1915
1916 } else {
1917 awidth = ALIGN(fb->width, 64);
3be5262e 1918 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
3be5262e
HW		 1919 plane_state->plane_size.video.luma_size.x = 0;
1920 plane_state->plane_size.video.luma_size.y = 0;
1921 plane_state->plane_size.video.luma_size.width = awidth;
1922 plane_state->plane_size.video.luma_size.height = fb->height;
e7b07cee 1923 /* TODO: unhardcode */
3be5262e 1924 plane_state->plane_size.video.luma_pitch = awidth;
e7b07cee 1925
3be5262e
HW		 1926 plane_state->plane_size.video.chroma_size.x = 0;
1927 plane_state->plane_size.video.chroma_size.y = 0;
1928 plane_state->plane_size.video.chroma_size.width = awidth;
1929 plane_state->plane_size.video.chroma_size.height = fb->height;
1930 plane_state->plane_size.video.chroma_pitch = awidth / 2;
e7b07cee
HW		 1931
1932 /* TODO: unhardcode */
3be5262e 1933 plane_state->color_space = COLOR_SPACE_YCBCR709;
e7b07cee
HW		 1934 }
1935
3be5262e 1936 memset(&plane_state->tiling_info, 0, sizeof(plane_state->tiling_info));
e7b07cee 1937
b830ebc9
HW		 1938 /* Fill GFX8 params */
1939 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
1940 unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
e7b07cee
HW		 1941
1942 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1943 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1944 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1945 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1946 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1947
1948 /* XXX fix me for VI */
3be5262e
HW		 1949 plane_state->tiling_info.gfx8.num_banks = num_banks;
1950 plane_state->tiling_info.gfx8.array_mode =
e7b07cee 1951 DC_ARRAY_2D_TILED_THIN1;
3be5262e
HW		 1952 plane_state->tiling_info.gfx8.tile_split = tile_split;
1953 plane_state->tiling_info.gfx8.bank_width = bankw;
1954 plane_state->tiling_info.gfx8.bank_height = bankh;
1955 plane_state->tiling_info.gfx8.tile_aspect = mtaspect;
1956 plane_state->tiling_info.gfx8.tile_mode =
e7b07cee
HW		 1957 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
1958 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
1959 == DC_ARRAY_1D_TILED_THIN1) {
3be5262e 1960 plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
e7b07cee
HW		 1961 }
1962
3be5262e 1963 plane_state->tiling_info.gfx8.pipe_config =
e7b07cee
HW		 1964 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1965
1966 if (adev->asic_type == CHIP_VEGA10 ||
2325ff30 1967 adev->asic_type == CHIP_VEGA12 ||
1fe6bf2f 1968 adev->asic_type == CHIP_VEGA20 ||
e7b07cee
HW		 1969 adev->asic_type == CHIP_RAVEN) {
1970 /* Fill GFX9 params */
3be5262e 1971 plane_state->tiling_info.gfx9.num_pipes =
e7b07cee 1972 adev->gfx.config.gb_addr_config_fields.num_pipes;
3be5262e 1973 plane_state->tiling_info.gfx9.num_banks =
e7b07cee 1974 adev->gfx.config.gb_addr_config_fields.num_banks;
3be5262e 1975 plane_state->tiling_info.gfx9.pipe_interleave =
e7b07cee 1976 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
3be5262e 1977 plane_state->tiling_info.gfx9.num_shader_engines =
e7b07cee 1978 adev->gfx.config.gb_addr_config_fields.num_se;
3be5262e 1979 plane_state->tiling_info.gfx9.max_compressed_frags =
e7b07cee 1980 adev->gfx.config.gb_addr_config_fields.max_compress_frags;
3be5262e 1981 plane_state->tiling_info.gfx9.num_rb_per_se =
e7b07cee 1982 adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
3be5262e 1983 plane_state->tiling_info.gfx9.swizzle =
e7b07cee 1984 AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
3be5262e 1985 plane_state->tiling_info.gfx9.shaderEnable = 1;
e7b07cee
HW		 1986 }
1987
3be5262e
HW		 1988 plane_state->visible = true;
1989 plane_state->scaling_quality.h_taps_c = 0;
1990 plane_state->scaling_quality.v_taps_c = 0;
e7b07cee 1991
3be5262e
HW		 1992 /* is this needed? is plane_state zeroed at allocation? */
1993 plane_state->scaling_quality.h_taps = 0;
1994 plane_state->scaling_quality.v_taps = 0;
1995 plane_state->stereo_format = PLANE_STEREO_FORMAT_NONE;
e7b07cee
HW		 1996
1997 return ret;
1998
1999}
2000
3ee6b26b
AD		 2001static int fill_plane_attributes(struct amdgpu_device *adev,
2002 struct dc_plane_state *dc_plane_state,
2003 struct drm_plane_state *plane_state,
9817d5f5 2004 struct drm_crtc_state *crtc_state)
e7b07cee
HW		 2005{
2006 const struct amdgpu_framebuffer *amdgpu_fb =
2007 to_amdgpu_framebuffer(plane_state->fb);
2008 const struct drm_crtc *crtc = plane_state->crtc;
e7b07cee
HW		 2009 int ret = 0;
2010
3be5262e 2011 if (!fill_rects_from_plane_state(plane_state, dc_plane_state))
e7b07cee
HW		 2012 return -EINVAL;
2013
2014 ret = fill_plane_attributes_from_fb(
2015 crtc->dev->dev_private,
3be5262e 2016 dc_plane_state,
9817d5f5 2017 amdgpu_fb);
e7b07cee
HW		 2018
2019 if (ret)
2020 return ret;
2021
e277adc5
LSL		 2022 /*
2023 * Always set input transfer function, since plane state is refreshed
2024 * every time.
2025 */
2026 ret = amdgpu_dm_set_degamma_lut(crtc_state, dc_plane_state);
8c45c5db
LSL		 2027 if (ret) {
2028 dc_transfer_func_release(dc_plane_state->in_transfer_func);
2029 dc_plane_state->in_transfer_func = NULL;
2030 }
e7b07cee
HW		 2031
2032 return ret;
2033}
2034
2035/*****************************************************************************/
2036
3ee6b26b
AD		 2037static void update_stream_scaling_settings(const struct drm_display_mode *mode,
2038 const struct dm_connector_state *dm_state,
2039 struct dc_stream_state *stream)
e7b07cee
HW		 2040{
2041 enum amdgpu_rmx_type rmx_type;
2042
2043 struct rect src = { 0 }; /* viewport in composition space*/
2044 struct rect dst = { 0 }; /* stream addressable area */
2045
2046 /* no mode. nothing to be done */
2047 if (!mode)
2048 return;
2049
2050 /* Full screen scaling by default */
2051 src.width = mode->hdisplay;
2052 src.height = mode->vdisplay;
2053 dst.width = stream->timing.h_addressable;
2054 dst.height = stream->timing.v_addressable;
2055
f4791779
HW		 2056 if (dm_state) {
2057 rmx_type = dm_state->scaling;
2058 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
2059 if (src.width * dst.height <
2060 src.height * dst.width) {
2061 /* height needs less upscaling/more downscaling */
2062 dst.width = src.width *
2063 dst.height / src.height;
2064 } else {
2065 /* width needs less upscaling/more downscaling */
2066 dst.height = src.height *
2067 dst.width / src.width;
2068 }
2069 } else if (rmx_type == RMX_CENTER) {
2070 dst = src;
e7b07cee 2071 }
e7b07cee 2072
f4791779
HW		 2073 dst.x = (stream->timing.h_addressable - dst.width) / 2;
2074 dst.y = (stream->timing.v_addressable - dst.height) / 2;
e7b07cee 2075
f4791779
HW		 2076 if (dm_state->underscan_enable) {
2077 dst.x += dm_state->underscan_hborder / 2;
2078 dst.y += dm_state->underscan_vborder / 2;
2079 dst.width -= dm_state->underscan_hborder;
2080 dst.height -= dm_state->underscan_vborder;
2081 }
e7b07cee
HW		 2082 }
2083
2084 stream->src = src;
2085 stream->dst = dst;
2086
f1ad2f5e 2087 DRM_DEBUG_DRIVER("Destination Rectangle x:%d y:%d width:%d height:%d\n",
e7b07cee
HW		 2088 dst.x, dst.y, dst.width, dst.height);
2089
2090}
2091
3ee6b26b
AD		 2092static enum dc_color_depth
2093convert_color_depth_from_display_info(const struct drm_connector *connector)
e7b07cee
HW		 2094{
2095 uint32_t bpc = connector->display_info.bpc;
2096
e7b07cee
HW		 2097 switch (bpc) {
2098 case 0:
2099 /* Temporary Work around, DRM don't parse color depth for
2100 * EDID revision before 1.4
2101 * TODO: Fix edid parsing
2102 */
2103 return COLOR_DEPTH_888;
2104 case 6:
2105 return COLOR_DEPTH_666;
2106 case 8:
2107 return COLOR_DEPTH_888;
2108 case 10:
2109 return COLOR_DEPTH_101010;
2110 case 12:
2111 return COLOR_DEPTH_121212;
2112 case 14:
2113 return COLOR_DEPTH_141414;
2114 case 16:
2115 return COLOR_DEPTH_161616;
2116 default:
2117 return COLOR_DEPTH_UNDEFINED;
2118 }
2119}
2120
3ee6b26b
AD		 2121static enum dc_aspect_ratio
2122get_aspect_ratio(const struct drm_display_mode *mode_in)
e7b07cee
HW		 2123{
2124 int32_t width = mode_in->crtc_hdisplay * 9;
2125 int32_t height = mode_in->crtc_vdisplay * 16;
b830ebc9 2126
e7b07cee
HW		 2127 if ((width - height) < 10 && (width - height) > -10)
2128 return ASPECT_RATIO_16_9;
2129 else
2130 return ASPECT_RATIO_4_3;
2131}
2132
3ee6b26b
AD		 2133static enum dc_color_space
2134get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
e7b07cee
HW		 2135{
2136 enum dc_color_space color_space = COLOR_SPACE_SRGB;
2137
2138 switch (dc_crtc_timing->pixel_encoding) {
2139 case PIXEL_ENCODING_YCBCR422:
2140 case PIXEL_ENCODING_YCBCR444:
2141 case PIXEL_ENCODING_YCBCR420:
2142 {
2143 /*
2144 * 27030khz is the separation point between HDTV and SDTV
2145 * according to HDMI spec, we use YCbCr709 and YCbCr601
2146 * respectively
2147 */
2148 if (dc_crtc_timing->pix_clk_khz > 27030) {
2149 if (dc_crtc_timing->flags.Y_ONLY)
2150 color_space =
2151 COLOR_SPACE_YCBCR709_LIMITED;
2152 else
2153 color_space = COLOR_SPACE_YCBCR709;
2154 } else {
2155 if (dc_crtc_timing->flags.Y_ONLY)
2156 color_space =
2157 COLOR_SPACE_YCBCR601_LIMITED;
2158 else
2159 color_space = COLOR_SPACE_YCBCR601;
2160 }
2161
2162 }
2163 break;
2164 case PIXEL_ENCODING_RGB:
2165 color_space = COLOR_SPACE_SRGB;
2166 break;
2167
2168 default:
2169 WARN_ON(1);
2170 break;
2171 }
2172
2173 return color_space;
2174}
2175
2176/*****************************************************************************/
2177
3ee6b26b
AD		 2178static void
2179fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream,
2180 const struct drm_display_mode *mode_in,
2181 const struct drm_connector *connector)
e7b07cee
HW		 2182{
2183 struct dc_crtc_timing *timing_out = &stream->timing;
b830ebc9 2184
e7b07cee
HW		 2185 memset(timing_out, 0, sizeof(struct dc_crtc_timing));
2186
2187 timing_out->h_border_left = 0;
2188 timing_out->h_border_right = 0;
2189 timing_out->v_border_top = 0;
2190 timing_out->v_border_bottom = 0;
2191 /* TODO: un-hardcode */
2192
2193 if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
2194 && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
2195 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
2196 else
2197 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
2198
2199 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
2200 timing_out->display_color_depth = convert_color_depth_from_display_info(
2201 connector);
2202 timing_out->scan_type = SCANNING_TYPE_NODATA;
2203 timing_out->hdmi_vic = 0;
2204 timing_out->vic = drm_match_cea_mode(mode_in);
2205
2206 timing_out->h_addressable = mode_in->crtc_hdisplay;
2207 timing_out->h_total = mode_in->crtc_htotal;
2208 timing_out->h_sync_width =
2209 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
2210 timing_out->h_front_porch =
2211 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
2212 timing_out->v_total = mode_in->crtc_vtotal;
2213 timing_out->v_addressable = mode_in->crtc_vdisplay;
2214 timing_out->v_front_porch =
2215 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
2216 timing_out->v_sync_width =
2217 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
2218 timing_out->pix_clk_khz = mode_in->crtc_clock;
2219 timing_out->aspect_ratio = get_aspect_ratio(mode_in);
2220 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
2221 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
2222 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
2223 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
2224
2225 stream->output_color_space = get_output_color_space(timing_out);
2226
e43a432c
AK		 2227 stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
2228 stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
e7b07cee
HW		 2229}
2230
3ee6b26b
AD		 2231static void fill_audio_info(struct audio_info *audio_info,
2232 const struct drm_connector *drm_connector,
2233 const struct dc_sink *dc_sink)
e7b07cee
HW		 2234{
2235 int i = 0;
2236 int cea_revision = 0;
2237 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
2238
2239 audio_info->manufacture_id = edid_caps->manufacturer_id;
2240 audio_info->product_id = edid_caps->product_id;
2241
2242 cea_revision = drm_connector->display_info.cea_rev;
2243
d2b2562c
TSD		 2244 strncpy(audio_info->display_name,
2245 edid_caps->display_name,
2246 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS - 1);
e7b07cee 2247
b830ebc9 2248 if (cea_revision >= 3) {
e7b07cee
HW		 2249 audio_info->mode_count = edid_caps->audio_mode_count;
2250
2251 for (i = 0; i < audio_info->mode_count; ++i) {
2252 audio_info->modes[i].format_code =
2253 (enum audio_format_code)
2254 (edid_caps->audio_modes[i].format_code);
2255 audio_info->modes[i].channel_count =
2256 edid_caps->audio_modes[i].channel_count;
2257 audio_info->modes[i].sample_rates.all =
2258 edid_caps->audio_modes[i].sample_rate;
2259 audio_info->modes[i].sample_size =
2260 edid_caps->audio_modes[i].sample_size;
2261 }
2262 }
2263
2264 audio_info->flags.all = edid_caps->speaker_flags;
2265
2266 /* TODO: We only check for the progressive mode, check for interlace mode too */
b830ebc9 2267 if (drm_connector->latency_present[0]) {
e7b07cee
HW		 2268 audio_info->video_latency = drm_connector->video_latency[0];
2269 audio_info->audio_latency = drm_connector->audio_latency[0];
2270 }
2271
2272 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
2273
2274}
2275
3ee6b26b
AD		 2276static void
2277copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
2278 struct drm_display_mode *dst_mode)
e7b07cee
HW		 2279{
2280 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
2281 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
2282 dst_mode->crtc_clock = src_mode->crtc_clock;
2283 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
2284 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
b830ebc9 2285 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start;
e7b07cee
HW		 2286 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
2287 dst_mode->crtc_htotal = src_mode->crtc_htotal;
2288 dst_mode->crtc_hskew = src_mode->crtc_hskew;
2289 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
2290 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
2291 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
2292 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
2293 dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
2294}
2295
3ee6b26b
AD		 2296static void
2297decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
2298 const struct drm_display_mode *native_mode,
2299 bool scale_enabled)
e7b07cee
HW		 2300{
2301 if (scale_enabled) {
2302 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2303 } else if (native_mode->clock == drm_mode->clock &&
2304 native_mode->htotal == drm_mode->htotal &&
2305 native_mode->vtotal == drm_mode->vtotal) {
2306 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2307 } else {
2308 /* no scaling nor amdgpu inserted, no need to patch */
2309 }
2310}
2311
aed15309
ML		 2312static struct dc_sink *
2313create_fake_sink(struct amdgpu_dm_connector *aconnector)
2e0ac3d6 2314{
2e0ac3d6 2315 struct dc_sink_init_data sink_init_data = { 0 };
aed15309 2316 struct dc_sink *sink = NULL;
2e0ac3d6
HW		 2317 sink_init_data.link = aconnector->dc_link;
2318 sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
2319
2320 sink = dc_sink_create(&sink_init_data);
423788c7 2321 if (!sink) {
2e0ac3d6 2322 DRM_ERROR("Failed to create sink!\n");
aed15309 2323 return NULL;
423788c7 2324 }
2e0ac3d6 2325 sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
423788c7 2326
aed15309 2327 return sink;
2e0ac3d6
HW		 2328}
2329
fa2123db
ML		 2330static void set_multisync_trigger_params(
2331 struct dc_stream_state *stream)
2332{
2333 if (stream->triggered_crtc_reset.enabled) {
2334 stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING;
2335 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE;
2336 }
2337}
2338
2339static void set_master_stream(struct dc_stream_state *stream_set[],
2340 int stream_count)
2341{
2342 int j, highest_rfr = 0, master_stream = 0;
2343
2344 for (j = 0; j < stream_count; j++) {
2345 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
2346 int refresh_rate = 0;
2347
2348 refresh_rate = (stream_set[j]->timing.pix_clk_khz*1000)/
2349 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
2350 if (refresh_rate > highest_rfr) {
2351 highest_rfr = refresh_rate;
2352 master_stream = j;
2353 }
2354 }
2355 }
2356 for (j = 0; j < stream_count; j++) {
03736f4c 2357 if (stream_set[j])
fa2123db
ML		 2358 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
2359 }
2360}
2361
2362static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
2363{
2364 int i = 0;
2365
2366 if (context->stream_count < 2)
2367 return;
2368 for (i = 0; i < context->stream_count ; i++) {
2369 if (!context->streams[i])
2370 continue;
2371 /* TODO: add a function to read AMD VSDB bits and will set
2372 * crtc_sync_master.multi_sync_enabled flag
2373 * For now its set to false
2374 */
2375 set_multisync_trigger_params(context->streams[i]);
2376 }
2377 set_master_stream(context->streams, context->stream_count);
2378}
2379
3ee6b26b
AD		 2380static struct dc_stream_state *
2381create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
2382 const struct drm_display_mode *drm_mode,
2383 const struct dm_connector_state *dm_state)
e7b07cee
HW		 2384{
2385 struct drm_display_mode *preferred_mode = NULL;
391ef035 2386 struct drm_connector *drm_connector;
0971c40e 2387 struct dc_stream_state *stream = NULL;
e7b07cee
HW		 2388 struct drm_display_mode mode = *drm_mode;
2389 bool native_mode_found = false;
aed15309 2390 struct dc_sink *sink = NULL;
b830ebc9 2391 if (aconnector == NULL) {
e7b07cee 2392 DRM_ERROR("aconnector is NULL!\n");
64245fa7 2393 return stream;
e7b07cee
HW		 2394 }
2395
e7b07cee 2396 drm_connector = &aconnector->base;
2e0ac3d6 2397
f4ac176e
JZ		 2398 if (!aconnector->dc_sink) {
2399 /*
391ef035
JFZ		 2400 * Create dc_sink when necessary to MST
2401 * Don't apply fake_sink to MST
f4ac176e 2402 */
391ef035
JFZ		 2403 if (aconnector->mst_port) {
2404 dm_dp_mst_dc_sink_create(drm_connector);
64245fa7 2405 return stream;
391ef035 2406 }
f4ac176e 2407
aed15309
ML		 2408 sink = create_fake_sink(aconnector);
2409 if (!sink)
64245fa7 2410 return stream;
aed15309
ML		 2411 } else {
2412 sink = aconnector->dc_sink;
f4ac176e 2413 }
2e0ac3d6 2414
aed15309 2415 stream = dc_create_stream_for_sink(sink);
4562236b 2416
b830ebc9 2417 if (stream == NULL) {
e7b07cee 2418 DRM_ERROR("Failed to create stream for sink!\n");
aed15309 2419 goto finish;
e7b07cee
HW		 2420 }
2421
2422 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
2423 /* Search for preferred mode */
2424 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
2425 native_mode_found = true;
2426 break;
2427 }
2428 }
2429 if (!native_mode_found)
2430 preferred_mode = list_first_entry_or_null(
2431 &aconnector->base.modes,
2432 struct drm_display_mode,
2433 head);
2434
b830ebc9 2435 if (preferred_mode == NULL) {
e7b07cee
HW		 2436 /* This may not be an error, the use case is when we we have no
2437 * usermode calls to reset and set mode upon hotplug. In this
2438 * case, we call set mode ourselves to restore the previous mode
2439 * and the modelist may not be filled in in time.
2440 */
f1ad2f5e 2441 DRM_DEBUG_DRIVER("No preferred mode found\n");
e7b07cee
HW		 2442 } else {
2443 decide_crtc_timing_for_drm_display_mode(
2444 &mode, preferred_mode,
f4791779 2445 dm_state ? (dm_state->scaling != RMX_OFF) : false);
e7b07cee
HW		 2446 }
2447
f783577c
JFZ		 2448 if (!dm_state)
2449 drm_mode_set_crtcinfo(&mode, 0);
2450
e7b07cee
HW		 2451 fill_stream_properties_from_drm_display_mode(stream,
2452 &mode, &aconnector->base);
2453 update_stream_scaling_settings(&mode, dm_state, stream);
2454
2455 fill_audio_info(
2456 &stream->audio_info,
2457 drm_connector,
aed15309 2458 sink);
e7b07cee 2459
9182b4cb
HW		 2460 update_stream_signal(stream);
2461
9e3efe3e
HW		 2462 if (dm_state && dm_state->freesync_capable)
2463 stream->ignore_msa_timing_param = true;
aed15309
ML		 2464finish:
2465 if (sink && sink->sink_signal == SIGNAL_TYPE_VIRTUAL)
2466 dc_sink_release(sink);
9e3efe3e 2467
e7b07cee
HW		 2468 return stream;
2469}
2470
7578ecda 2471static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
e7b07cee
HW		 2472{
2473 drm_crtc_cleanup(crtc);
2474 kfree(crtc);
2475}
2476
2477static void dm_crtc_destroy_state(struct drm_crtc *crtc,
3ee6b26b 2478 struct drm_crtc_state *state)
e7b07cee
HW		 2479{
2480 struct dm_crtc_state *cur = to_dm_crtc_state(state);
2481
2482 /* TODO Destroy dc_stream objects are stream object is flattened */
2483 if (cur->stream)
2484 dc_stream_release(cur->stream);
2485
2486
2487 __drm_atomic_helper_crtc_destroy_state(state);
2488
2489
2490 kfree(state);
2491}
2492
2493static void dm_crtc_reset_state(struct drm_crtc *crtc)
2494{
2495 struct dm_crtc_state *state;
2496
2497 if (crtc->state)
2498 dm_crtc_destroy_state(crtc, crtc->state);
2499
2500 state = kzalloc(sizeof(*state), GFP_KERNEL);
2501 if (WARN_ON(!state))
2502 return;
2503
2504 crtc->state = &state->base;
2505 crtc->state->crtc = crtc;
2506
2507}
2508
2509static struct drm_crtc_state *
2510dm_crtc_duplicate_state(struct drm_crtc *crtc)
2511{
2512 struct dm_crtc_state *state, *cur;
2513
2514 cur = to_dm_crtc_state(crtc->state);
2515
2516 if (WARN_ON(!crtc->state))
2517 return NULL;
2518
2004f45e 2519 state = kzalloc(sizeof(*state), GFP_KERNEL);
2a55f096
ES		 2520 if (!state)
2521 return NULL;
e7b07cee
HW		 2522
2523 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
2524
2525 if (cur->stream) {
2526 state->stream = cur->stream;
2527 dc_stream_retain(state->stream);
2528 }
2529
2530 /* TODO Duplicate dc_stream after objects are stream object is flattened */
2531
2532 return &state->base;
2533}
2534
589d2739
HW		 2535
2536static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
2537{
2538 enum dc_irq_source irq_source;
2539 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2540 struct amdgpu_device *adev = crtc->dev->dev_private;
2541
2542 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
a0e30392 2543 return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
589d2739
HW		 2544}
2545
2546static int dm_enable_vblank(struct drm_crtc *crtc)
2547{
2548 return dm_set_vblank(crtc, true);
2549}
2550
2551static void dm_disable_vblank(struct drm_crtc *crtc)
2552{
2553 dm_set_vblank(crtc, false);
2554}
2555
e7b07cee
HW		 2556/* Implemented only the options currently availible for the driver */
2557static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
2558 .reset = dm_crtc_reset_state,
2559 .destroy = amdgpu_dm_crtc_destroy,
2560 .gamma_set = drm_atomic_helper_legacy_gamma_set,
2561 .set_config = drm_atomic_helper_set_config,
2562 .page_flip = drm_atomic_helper_page_flip,
2563 .atomic_duplicate_state = dm_crtc_duplicate_state,
2564 .atomic_destroy_state = dm_crtc_destroy_state,
31aec354 2565 .set_crc_source = amdgpu_dm_crtc_set_crc_source,
589d2739
HW		 2566 .enable_vblank = dm_enable_vblank,
2567 .disable_vblank = dm_disable_vblank,
e7b07cee
HW		 2568};
2569
2570static enum drm_connector_status
2571amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
2572{
2573 bool connected;
c84dec2f 2574 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 2575
2576 /* Notes:
2577 * 1. This interface is NOT called in context of HPD irq.
2578 * 2. This interface *is called* in context of user-mode ioctl. Which
2579 * makes it a bad place for *any* MST-related activit. */
2580
8580d60b
HW		 2581 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
2582 !aconnector->fake_enable)
e7b07cee
HW		 2583 connected = (aconnector->dc_sink != NULL);
2584 else
2585 connected = (aconnector->base.force == DRM_FORCE_ON);
2586
2587 return (connected ? connector_status_connected :
2588 connector_status_disconnected);
2589}
2590
3ee6b26b
AD		 2591int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
2592 struct drm_connector_state *connector_state,
2593 struct drm_property *property,
2594 uint64_t val)
e7b07cee
HW		 2595{
2596 struct drm_device *dev = connector->dev;
2597 struct amdgpu_device *adev = dev->dev_private;
2598 struct dm_connector_state *dm_old_state =
2599 to_dm_connector_state(connector->state);
2600 struct dm_connector_state *dm_new_state =
2601 to_dm_connector_state(connector_state);
2602
2603 int ret = -EINVAL;
2604
2605 if (property == dev->mode_config.scaling_mode_property) {
2606 enum amdgpu_rmx_type rmx_type;
2607
2608 switch (val) {
2609 case DRM_MODE_SCALE_CENTER:
2610 rmx_type = RMX_CENTER;
2611 break;
2612 case DRM_MODE_SCALE_ASPECT:
2613 rmx_type = RMX_ASPECT;
2614 break;
2615 case DRM_MODE_SCALE_FULLSCREEN:
2616 rmx_type = RMX_FULL;
2617 break;
2618 case DRM_MODE_SCALE_NONE:
2619 default:
2620 rmx_type = RMX_OFF;
2621 break;
2622 }
2623
2624 if (dm_old_state->scaling == rmx_type)
2625 return 0;
2626
2627 dm_new_state->scaling = rmx_type;
2628 ret = 0;
2629 } else if (property == adev->mode_info.underscan_hborder_property) {
2630 dm_new_state->underscan_hborder = val;
2631 ret = 0;
2632 } else if (property == adev->mode_info.underscan_vborder_property) {
2633 dm_new_state->underscan_vborder = val;
2634 ret = 0;
2635 } else if (property == adev->mode_info.underscan_property) {
2636 dm_new_state->underscan_enable = val;
2637 ret = 0;
2638 }
2639
2640 return ret;
2641}
2642
3ee6b26b
AD		 2643int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
2644 const struct drm_connector_state *state,
2645 struct drm_property *property,
2646 uint64_t *val)
e7b07cee
HW		 2647{
2648 struct drm_device *dev = connector->dev;
2649 struct amdgpu_device *adev = dev->dev_private;
2650 struct dm_connector_state *dm_state =
2651 to_dm_connector_state(state);
2652 int ret = -EINVAL;
2653
2654 if (property == dev->mode_config.scaling_mode_property) {
2655 switch (dm_state->scaling) {
2656 case RMX_CENTER:
2657 *val = DRM_MODE_SCALE_CENTER;
2658 break;
2659 case RMX_ASPECT:
2660 *val = DRM_MODE_SCALE_ASPECT;
2661 break;
2662 case RMX_FULL:
2663 *val = DRM_MODE_SCALE_FULLSCREEN;
2664 break;
2665 case RMX_OFF:
2666 default:
2667 *val = DRM_MODE_SCALE_NONE;
2668 break;
2669 }
2670 ret = 0;
2671 } else if (property == adev->mode_info.underscan_hborder_property) {
2672 *val = dm_state->underscan_hborder;
2673 ret = 0;
2674 } else if (property == adev->mode_info.underscan_vborder_property) {
2675 *val = dm_state->underscan_vborder;
2676 ret = 0;
2677 } else if (property == adev->mode_info.underscan_property) {
2678 *val = dm_state->underscan_enable;
2679 ret = 0;
2680 }
2681 return ret;
2682}
2683
7578ecda 2684static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
e7b07cee 2685{
c84dec2f 2686 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 2687 const struct dc_link *link = aconnector->dc_link;
2688 struct amdgpu_device *adev = connector->dev->dev_private;
2689 struct amdgpu_display_manager *dm = &adev->dm;
ada8ce15 2690
e7b07cee
HW		 2691#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
2692 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
2693
89fc8d4e 2694 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
5cd29ed0
HW		 2695 link->type != dc_connection_none &&
2696 dm->backlight_dev) {
2697 backlight_device_unregister(dm->backlight_dev);
2698 dm->backlight_dev = NULL;
e7b07cee
HW		 2699 }
2700#endif
2701 drm_connector_unregister(connector);
2702 drm_connector_cleanup(connector);
2703 kfree(connector);
2704}
2705
2706void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
2707{
2708 struct dm_connector_state *state =
2709 to_dm_connector_state(connector->state);
2710
df099b9b
LSL		 2711 if (connector->state)
2712 __drm_atomic_helper_connector_destroy_state(connector->state);
2713
e7b07cee
HW		 2714 kfree(state);
2715
2716 state = kzalloc(sizeof(*state), GFP_KERNEL);
2717
2718 if (state) {
2719 state->scaling = RMX_OFF;
2720 state->underscan_enable = false;
2721 state->underscan_hborder = 0;
2722 state->underscan_vborder = 0;
2723
df099b9b 2724 __drm_atomic_helper_connector_reset(connector, &state->base);
e7b07cee
HW		 2725 }
2726}
2727
3ee6b26b
AD		 2728struct drm_connector_state *
2729amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
e7b07cee
HW		 2730{
2731 struct dm_connector_state *state =
2732 to_dm_connector_state(connector->state);
2733
2734 struct dm_connector_state *new_state =
2735 kmemdup(state, sizeof(*state), GFP_KERNEL);
2736
2737 if (new_state) {
2738 __drm_atomic_helper_connector_duplicate_state(connector,
1ecfc3da 2739 &new_state->base);
e7b07cee
HW		 2740 return &new_state->base;
2741 }
2742
2743 return NULL;
2744}
2745
2746static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
2747 .reset = amdgpu_dm_connector_funcs_reset,
2748 .detect = amdgpu_dm_connector_detect,
2749 .fill_modes = drm_helper_probe_single_connector_modes,
2750 .destroy = amdgpu_dm_connector_destroy,
2751 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
2752 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2753 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
2754 .atomic_get_property = amdgpu_dm_connector_atomic_get_property
2755};
2756
2757static struct drm_encoder *best_encoder(struct drm_connector *connector)
2758{
2759 int enc_id = connector->encoder_ids[0];
2760 struct drm_mode_object *obj;
2761 struct drm_encoder *encoder;
2762
f1ad2f5e 2763 DRM_DEBUG_DRIVER("Finding the best encoder\n");
e7b07cee
HW		 2764
2765 /* pick the encoder ids */
2766 if (enc_id) {
bd21a37d 2767 obj = drm_mode_object_find(connector->dev, NULL, enc_id, DRM_MODE_OBJECT_ENCODER);
e7b07cee
HW		 2768 if (!obj) {
2769 DRM_ERROR("Couldn't find a matching encoder for our connector\n");
2770 return NULL;
2771 }
2772 encoder = obj_to_encoder(obj);
2773 return encoder;
2774 }
2775 DRM_ERROR("No encoder id\n");
2776 return NULL;
2777}
2778
2779static int get_modes(struct drm_connector *connector)
2780{
2781 return amdgpu_dm_connector_get_modes(connector);
2782}
2783
c84dec2f 2784static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 2785{
2786 struct dc_sink_init_data init_params = {
2787 .link = aconnector->dc_link,
2788 .sink_signal = SIGNAL_TYPE_VIRTUAL
2789 };
70e8ffc5 2790 struct edid *edid;
e7b07cee 2791
a89ff457 2792 if (!aconnector->base.edid_blob_ptr) {
e7b07cee
HW		 2793 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
2794 aconnector->base.name);
2795
2796 aconnector->base.force = DRM_FORCE_OFF;
2797 aconnector->base.override_edid = false;
2798 return;
2799 }
2800
70e8ffc5
HW		 2801 edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
2802
e7b07cee
HW		 2803 aconnector->edid = edid;
2804
2805 aconnector->dc_em_sink = dc_link_add_remote_sink(
2806 aconnector->dc_link,
2807 (uint8_t *)edid,
2808 (edid->extensions + 1) * EDID_LENGTH,
2809 &init_params);
2810
a68d90e7 2811 if (aconnector->base.force == DRM_FORCE_ON)
e7b07cee
HW		 2812 aconnector->dc_sink = aconnector->dc_link->local_sink ?
2813 aconnector->dc_link->local_sink :
2814 aconnector->dc_em_sink;
2815}
2816
c84dec2f 2817static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 2818{
2819 struct dc_link *link = (struct dc_link *)aconnector->dc_link;
2820
2821 /* In case of headless boot with force on for DP managed connector
2822 * Those settings have to be != 0 to get initial modeset
2823 */
2824 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
2825 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
2826 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
2827 }
2828
2829
2830 aconnector->base.override_edid = true;
2831 create_eml_sink(aconnector);
2832}
2833
ba9ca088 2834enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
3ee6b26b 2835 struct drm_display_mode *mode)
e7b07cee
HW		 2836{
2837 int result = MODE_ERROR;
2838 struct dc_sink *dc_sink;
2839 struct amdgpu_device *adev = connector->dev->dev_private;
2840 /* TODO: Unhardcode stream count */
0971c40e 2841 struct dc_stream_state *stream;
c84dec2f 2842 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
a39438f0 2843 enum dc_status dc_result = DC_OK;
e7b07cee
HW		 2844
2845 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
2846 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
2847 return result;
2848
2849 /* Only run this the first time mode_valid is called to initilialize
2850 * EDID mgmt
2851 */
2852 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
2853 !aconnector->dc_em_sink)
2854 handle_edid_mgmt(aconnector);
2855
c84dec2f 2856 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
e7b07cee 2857
b830ebc9 2858 if (dc_sink == NULL) {
e7b07cee
HW		 2859 DRM_ERROR("dc_sink is NULL!\n");
2860 goto fail;
2861 }
2862
f4791779 2863 stream = create_stream_for_sink(aconnector, mode, NULL);
b830ebc9 2864 if (stream == NULL) {
e7b07cee
HW		 2865 DRM_ERROR("Failed to create stream for sink!\n");
2866 goto fail;
2867 }
2868
a39438f0
HW		 2869 dc_result = dc_validate_stream(adev->dm.dc, stream);
2870
2871 if (dc_result == DC_OK)
e7b07cee 2872 result = MODE_OK;
a39438f0 2873 else
9f921b14 2874 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d\n",
a39438f0
HW		 2875 mode->vdisplay,
2876 mode->hdisplay,
9f921b14
HW		 2877 mode->clock,
2878 dc_result);
e7b07cee
HW		 2879
2880 dc_stream_release(stream);
2881
2882fail:
2883 /* TODO: error handling*/
2884 return result;
2885}
2886
2887static const struct drm_connector_helper_funcs
2888amdgpu_dm_connector_helper_funcs = {
2889 /*
b830ebc9
HW		 2890 * If hotplug a second bigger display in FB Con mode, bigger resolution
2891 * modes will be filtered by drm_mode_validate_size(), and those modes
2892 * is missing after user start lightdm. So we need to renew modes list.
2893 * in get_modes call back, not just return the modes count
2894 */
e7b07cee
HW		 2895 .get_modes = get_modes,
2896 .mode_valid = amdgpu_dm_connector_mode_valid,
2897 .best_encoder = best_encoder
2898};
2899
2900static void dm_crtc_helper_disable(struct drm_crtc *crtc)
2901{
2902}
2903
3ee6b26b
AD		 2904static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
2905 struct drm_crtc_state *state)
e7b07cee
HW		 2906{
2907 struct amdgpu_device *adev = crtc->dev->dev_private;
2908 struct dc *dc = adev->dm.dc;
2909 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state);
2910 int ret = -EINVAL;
2911
9b690ef3
BL		 2912 if (unlikely(!dm_crtc_state->stream &&
2913 modeset_required(state, NULL, dm_crtc_state->stream))) {
e7b07cee
HW		 2914 WARN_ON(1);
2915 return ret;
2916 }
2917
2918 /* In some use cases, like reset, no stream is attached */
2919 if (!dm_crtc_state->stream)
2920 return 0;
2921
62c933f9 2922 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
e7b07cee
HW		 2923 return 0;
2924
2925 return ret;
2926}
2927
3ee6b26b
AD		 2928static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
2929 const struct drm_display_mode *mode,
2930 struct drm_display_mode *adjusted_mode)
e7b07cee
HW		 2931{
2932 return true;
2933}
2934
2935static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
2936 .disable = dm_crtc_helper_disable,
2937 .atomic_check = dm_crtc_helper_atomic_check,
2938 .mode_fixup = dm_crtc_helper_mode_fixup
2939};
2940
2941static void dm_encoder_helper_disable(struct drm_encoder *encoder)
2942{
2943
2944}
2945
3ee6b26b
AD		 2946static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
2947 struct drm_crtc_state *crtc_state,
2948 struct drm_connector_state *conn_state)
e7b07cee
HW		 2949{
2950 return 0;
2951}
2952
2953const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
2954 .disable = dm_encoder_helper_disable,
2955 .atomic_check = dm_encoder_helper_atomic_check
2956};
2957
2958static void dm_drm_plane_reset(struct drm_plane *plane)
2959{
2960 struct dm_plane_state *amdgpu_state = NULL;
2961
2962 if (plane->state)
2963 plane->funcs->atomic_destroy_state(plane, plane->state);
2964
2965 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
f922237d
TSD		 2966 WARN_ON(amdgpu_state == NULL);
2967
e7b07cee
HW		 2968 if (amdgpu_state) {
2969 plane->state = &amdgpu_state->base;
2970 plane->state->plane = plane;
2971 plane->state->rotation = DRM_MODE_ROTATE_0;
f922237d 2972 }
e7b07cee
HW		 2973}
2974
2975static struct drm_plane_state *
2976dm_drm_plane_duplicate_state(struct drm_plane *plane)
2977{
2978 struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
2979
2980 old_dm_plane_state = to_dm_plane_state(plane->state);
2981 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
2982 if (!dm_plane_state)
2983 return NULL;
2984
2985 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
2986
3be5262e
HW		 2987 if (old_dm_plane_state->dc_state) {
2988 dm_plane_state->dc_state = old_dm_plane_state->dc_state;
2989 dc_plane_state_retain(dm_plane_state->dc_state);
e7b07cee
HW		 2990 }
2991
2992 return &dm_plane_state->base;
2993}
2994
2995void dm_drm_plane_destroy_state(struct drm_plane *plane,
3ee6b26b 2996 struct drm_plane_state *state)
e7b07cee
HW		 2997{
2998 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
2999
3be5262e
HW		 3000 if (dm_plane_state->dc_state)
3001 dc_plane_state_release(dm_plane_state->dc_state);
e7b07cee 3002
0627bbd3 3003 drm_atomic_helper_plane_destroy_state(plane, state);
e7b07cee
HW		 3004}
3005
3006static const struct drm_plane_funcs dm_plane_funcs = {
3007 .update_plane = drm_atomic_helper_update_plane,
3008 .disable_plane = drm_atomic_helper_disable_plane,
3009 .destroy = drm_plane_cleanup,
3010 .reset = dm_drm_plane_reset,
3011 .atomic_duplicate_state = dm_drm_plane_duplicate_state,
3012 .atomic_destroy_state = dm_drm_plane_destroy_state,
3013};
3014
3ee6b26b
AD		 3015static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
3016 struct drm_plane_state *new_state)
e7b07cee
HW		 3017{
3018 struct amdgpu_framebuffer *afb;
3019 struct drm_gem_object *obj;
5d43be0c 3020 struct amdgpu_device *adev;
e7b07cee 3021 struct amdgpu_bo *rbo;
56087b31 3022 uint64_t chroma_addr = 0;
e7b07cee
HW		 3023 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
3024 unsigned int awidth;
5d43be0c
CK		 3025 uint32_t domain;
3026 int r;
e7b07cee
HW		 3027
3028 dm_plane_state_old = to_dm_plane_state(plane->state);
3029 dm_plane_state_new = to_dm_plane_state(new_state);
3030
3031 if (!new_state->fb) {
f1ad2f5e 3032 DRM_DEBUG_DRIVER("No FB bound\n");
e7b07cee
HW		 3033 return 0;
3034 }
3035
3036 afb = to_amdgpu_framebuffer(new_state->fb);
e68d14dd 3037 obj = new_state->fb->obj[0];
e7b07cee 3038 rbo = gem_to_amdgpu_bo(obj);
5d43be0c 3039 adev = amdgpu_ttm_adev(rbo->tbo.bdev);
e7b07cee
HW		 3040 r = amdgpu_bo_reserve(rbo, false);
3041 if (unlikely(r != 0))
3042 return r;
3043
5d43be0c 3044 if (plane->type != DRM_PLANE_TYPE_CURSOR)
1d2361e5 3045 domain = amdgpu_display_supported_domains(adev);
5d43be0c
CK		 3046 else
3047 domain = AMDGPU_GEM_DOMAIN_VRAM;
e7b07cee 3048
5d43be0c 3049 r = amdgpu_bo_pin(rbo, domain, &afb->address);
e7b07cee
HW		 3050 amdgpu_bo_unreserve(rbo);
3051
3052 if (unlikely(r != 0)) {
30b7c614
HW		 3053 if (r != -ERESTARTSYS)
3054 DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
e7b07cee
HW		 3055 return r;
3056 }
3057
3058 amdgpu_bo_ref(rbo);
3059
3be5262e
HW		 3060 if (dm_plane_state_new->dc_state &&
3061 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
3062 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;
e7b07cee 3063
3be5262e
HW		 3064 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
3065 plane_state->address.grph.addr.low_part = lower_32_bits(afb->address);
3066 plane_state->address.grph.addr.high_part = upper_32_bits(afb->address);
e7b07cee
HW		 3067 } else {
3068 awidth = ALIGN(new_state->fb->width, 64);
56087b31 3069 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
3be5262e 3070 plane_state->address.video_progressive.luma_addr.low_part
e7b07cee 3071 = lower_32_bits(afb->address);
56087b31
S		 3072 plane_state->address.video_progressive.luma_addr.high_part
3073 = upper_32_bits(afb->address);
35888630 3074 chroma_addr = afb->address + (u64)awidth * new_state->fb->height;
3be5262e 3075 plane_state->address.video_progressive.chroma_addr.low_part
56087b31
S		 3076 = lower_32_bits(chroma_addr);
3077 plane_state->address.video_progressive.chroma_addr.high_part
3078 = upper_32_bits(chroma_addr);
e7b07cee
HW		 3079 }
3080 }
3081
e7b07cee
HW		 3082 return 0;
3083}
3084
3ee6b26b
AD		 3085static void dm_plane_helper_cleanup_fb(struct drm_plane *plane,
3086 struct drm_plane_state *old_state)
e7b07cee
HW		 3087{
3088 struct amdgpu_bo *rbo;
e7b07cee
HW		 3089 int r;
3090
3091 if (!old_state->fb)
3092 return;
3093
e68d14dd 3094 rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]);
e7b07cee
HW		 3095 r = amdgpu_bo_reserve(rbo, false);
3096 if (unlikely(r)) {
3097 DRM_ERROR("failed to reserve rbo before unpin\n");
3098 return;
b830ebc9
HW		 3099 }
3100
3101 amdgpu_bo_unpin(rbo);
3102 amdgpu_bo_unreserve(rbo);
3103 amdgpu_bo_unref(&rbo);
e7b07cee
HW		 3104}
3105
7578ecda
AD		 3106static int dm_plane_atomic_check(struct drm_plane *plane,
3107 struct drm_plane_state *state)
cbd19488
AG		 3108{
3109 struct amdgpu_device *adev = plane->dev->dev_private;
3110 struct dc *dc = adev->dm.dc;
3111 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
3112
3be5262e 3113 if (!dm_plane_state->dc_state)
9a3329b1 3114 return 0;
cbd19488 3115
a05bcff1
S		 3116 if (!fill_rects_from_plane_state(state, dm_plane_state->dc_state))
3117 return -EINVAL;
3118
62c933f9 3119 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
cbd19488
AG		 3120 return 0;
3121
3122 return -EINVAL;
3123}
3124
e7b07cee
HW		 3125static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
3126 .prepare_fb = dm_plane_helper_prepare_fb,
3127 .cleanup_fb = dm_plane_helper_cleanup_fb,
cbd19488 3128 .atomic_check = dm_plane_atomic_check,
e7b07cee
HW		 3129};
3130
3131/*
3132 * TODO: these are currently initialized to rgb formats only.
3133 * For future use cases we should either initialize them dynamically based on
3134 * plane capabilities, or initialize this array to all formats, so internal drm
3135 * check will succeed, and let DC to implement proper check
3136 */
d90371b0 3137static const uint32_t rgb_formats[] = {
e7b07cee
HW		 3138 DRM_FORMAT_RGB888,
3139 DRM_FORMAT_XRGB8888,
3140 DRM_FORMAT_ARGB8888,
3141 DRM_FORMAT_RGBA8888,
3142 DRM_FORMAT_XRGB2101010,
3143 DRM_FORMAT_XBGR2101010,
3144 DRM_FORMAT_ARGB2101010,
3145 DRM_FORMAT_ABGR2101010,
3146};
3147
99d1abf8 3148static const uint32_t yuv_formats[] = {
e7b07cee
HW		 3149 DRM_FORMAT_NV12,
3150 DRM_FORMAT_NV21,
3151};
3152
3153static const u32 cursor_formats[] = {
3154 DRM_FORMAT_ARGB8888
3155};
3156
7578ecda
AD		 3157static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
3158 struct amdgpu_plane *aplane,
3159 unsigned long possible_crtcs)
e7b07cee
HW		 3160{
3161 int res = -EPERM;
3162
3163 switch (aplane->base.type) {
3164 case DRM_PLANE_TYPE_PRIMARY:
e7b07cee
HW		 3165 res = drm_universal_plane_init(
3166 dm->adev->ddev,
3167 &aplane->base,
3168 possible_crtcs,
3169 &dm_plane_funcs,
3170 rgb_formats,
3171 ARRAY_SIZE(rgb_formats),
3172 NULL, aplane->base.type, NULL);
3173 break;
3174 case DRM_PLANE_TYPE_OVERLAY:
3175 res = drm_universal_plane_init(
3176 dm->adev->ddev,
3177 &aplane->base,
3178 possible_crtcs,
3179 &dm_plane_funcs,
3180 yuv_formats,
3181 ARRAY_SIZE(yuv_formats),
3182 NULL, aplane->base.type, NULL);
3183 break;
3184 case DRM_PLANE_TYPE_CURSOR:
3185 res = drm_universal_plane_init(
3186 dm->adev->ddev,
3187 &aplane->base,
3188 possible_crtcs,
3189 &dm_plane_funcs,
3190 cursor_formats,
3191 ARRAY_SIZE(cursor_formats),
3192 NULL, aplane->base.type, NULL);
3193 break;
3194 }
3195
3196 drm_plane_helper_add(&aplane->base, &dm_plane_helper_funcs);
3197
96719c54
HW		 3198 /* Create (reset) the plane state */
3199 if (aplane->base.funcs->reset)
3200 aplane->base.funcs->reset(&aplane->base);
3201
3202
e7b07cee
HW		 3203 return res;
3204}
3205
7578ecda
AD		 3206static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
3207 struct drm_plane *plane,
3208 uint32_t crtc_index)
e7b07cee
HW		 3209{
3210 struct amdgpu_crtc *acrtc = NULL;
3211 struct amdgpu_plane *cursor_plane;
3212
3213 int res = -ENOMEM;
3214
3215 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
3216 if (!cursor_plane)
3217 goto fail;
3218
3219 cursor_plane->base.type = DRM_PLANE_TYPE_CURSOR;
3220 res = amdgpu_dm_plane_init(dm, cursor_plane, 0);
3221
3222 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
3223 if (!acrtc)
3224 goto fail;
3225
3226 res = drm_crtc_init_with_planes(
3227 dm->ddev,
3228 &acrtc->base,
3229 plane,
3230 &cursor_plane->base,
3231 &amdgpu_dm_crtc_funcs, NULL);
3232
3233 if (res)
3234 goto fail;
3235
3236 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
3237
96719c54
HW		 3238 /* Create (reset) the plane state */
3239 if (acrtc->base.funcs->reset)
3240 acrtc->base.funcs->reset(&acrtc->base);
3241
e7b07cee
HW		 3242 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
3243 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
3244
3245 acrtc->crtc_id = crtc_index;
3246 acrtc->base.enabled = false;
3247
3248 dm->adev->mode_info.crtcs[crtc_index] = acrtc;
236d0e4f
LSL		 3249 drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES,
3250 true, MAX_COLOR_LUT_ENTRIES);
086247a4 3251 drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
e7b07cee
HW		 3252
3253 return 0;
3254
3255fail:
b830ebc9
HW		 3256 kfree(acrtc);
3257 kfree(cursor_plane);
e7b07cee
HW		 3258 return res;
3259}
3260
3261
3262static int to_drm_connector_type(enum signal_type st)
3263{
3264 switch (st) {
3265 case SIGNAL_TYPE_HDMI_TYPE_A:
3266 return DRM_MODE_CONNECTOR_HDMIA;
3267 case SIGNAL_TYPE_EDP:
3268 return DRM_MODE_CONNECTOR_eDP;
3269 case SIGNAL_TYPE_RGB:
3270 return DRM_MODE_CONNECTOR_VGA;
3271 case SIGNAL_TYPE_DISPLAY_PORT:
3272 case SIGNAL_TYPE_DISPLAY_PORT_MST:
3273 return DRM_MODE_CONNECTOR_DisplayPort;
3274 case SIGNAL_TYPE_DVI_DUAL_LINK:
3275 case SIGNAL_TYPE_DVI_SINGLE_LINK:
3276 return DRM_MODE_CONNECTOR_DVID;
3277 case SIGNAL_TYPE_VIRTUAL:
3278 return DRM_MODE_CONNECTOR_VIRTUAL;
3279
3280 default:
3281 return DRM_MODE_CONNECTOR_Unknown;
3282 }
3283}
3284
3285static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
3286{
3287 const struct drm_connector_helper_funcs *helper =
3288 connector->helper_private;
3289 struct drm_encoder *encoder;
3290 struct amdgpu_encoder *amdgpu_encoder;
3291
3292 encoder = helper->best_encoder(connector);
3293
3294 if (encoder == NULL)
3295 return;
3296
3297 amdgpu_encoder = to_amdgpu_encoder(encoder);
3298
3299 amdgpu_encoder->native_mode.clock = 0;
3300
3301 if (!list_empty(&connector->probed_modes)) {
3302 struct drm_display_mode *preferred_mode = NULL;
b830ebc9 3303
e7b07cee 3304 list_for_each_entry(preferred_mode,
b830ebc9
HW		 3305 &connector->probed_modes,
3306 head) {
3307 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
3308 amdgpu_encoder->native_mode = *preferred_mode;
3309
e7b07cee
HW		 3310 break;
3311 }
3312
3313 }
3314}
3315
3ee6b26b
AD		 3316static struct drm_display_mode *
3317amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
3318 char *name,
3319 int hdisplay, int vdisplay)
e7b07cee
HW		 3320{
3321 struct drm_device *dev = encoder->dev;
3322 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3323 struct drm_display_mode *mode = NULL;
3324 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
3325
3326 mode = drm_mode_duplicate(dev, native_mode);
3327
b830ebc9 3328 if (mode == NULL)
e7b07cee
HW		 3329 return NULL;
3330
3331 mode->hdisplay = hdisplay;
3332 mode->vdisplay = vdisplay;
3333 mode->type &= ~DRM_MODE_TYPE_PREFERRED;
3334 strncpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
3335
3336 return mode;
3337
3338}
3339
3340static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
3ee6b26b 3341 struct drm_connector *connector)
e7b07cee
HW		 3342{
3343 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3344 struct drm_display_mode *mode = NULL;
3345 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
c84dec2f
HW		 3346 struct amdgpu_dm_connector *amdgpu_dm_connector =
3347 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 3348 int i;
3349 int n;
3350 struct mode_size {
3351 char name[DRM_DISPLAY_MODE_LEN];
3352 int w;
3353 int h;
b830ebc9 3354 } common_modes[] = {
e7b07cee
HW		 3355 { "640x480", 640, 480},
3356 { "800x600", 800, 600},
3357 { "1024x768", 1024, 768},
3358 { "1280x720", 1280, 720},
3359 { "1280x800", 1280, 800},
3360 {"1280x1024", 1280, 1024},
3361 { "1440x900", 1440, 900},
3362 {"1680x1050", 1680, 1050},
3363 {"1600x1200", 1600, 1200},
3364 {"1920x1080", 1920, 1080},
3365 {"1920x1200", 1920, 1200}
3366 };
3367
b830ebc9 3368 n = ARRAY_SIZE(common_modes);
e7b07cee
HW		 3369
3370 for (i = 0; i < n; i++) {
3371 struct drm_display_mode *curmode = NULL;
3372 bool mode_existed = false;
3373
3374 if (common_modes[i].w > native_mode->hdisplay ||
b830ebc9
HW		 3375 common_modes[i].h > native_mode->vdisplay ||
3376 (common_modes[i].w == native_mode->hdisplay &&
3377 common_modes[i].h == native_mode->vdisplay))
3378 continue;
e7b07cee
HW		 3379
3380 list_for_each_entry(curmode, &connector->probed_modes, head) {
3381 if (common_modes[i].w == curmode->hdisplay &&
b830ebc9 3382 common_modes[i].h == curmode->vdisplay) {
e7b07cee
HW		 3383 mode_existed = true;
3384 break;
3385 }
3386 }
3387
3388 if (mode_existed)
3389 continue;
3390
3391 mode = amdgpu_dm_create_common_mode(encoder,
3392 common_modes[i].name, common_modes[i].w,
3393 common_modes[i].h);
3394 drm_mode_probed_add(connector, mode);
c84dec2f 3395 amdgpu_dm_connector->num_modes++;
e7b07cee
HW		 3396 }
3397}
3398
3ee6b26b
AD		 3399static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
3400 struct edid *edid)
e7b07cee 3401{
c84dec2f
HW		 3402 struct amdgpu_dm_connector *amdgpu_dm_connector =
3403 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 3404
3405 if (edid) {
3406 /* empty probed_modes */
3407 INIT_LIST_HEAD(&connector->probed_modes);
c84dec2f 3408 amdgpu_dm_connector->num_modes =
e7b07cee
HW		 3409 drm_add_edid_modes(connector, edid);
3410
e7b07cee 3411 amdgpu_dm_get_native_mode(connector);
a8d8d3dc 3412 } else {
c84dec2f 3413 amdgpu_dm_connector->num_modes = 0;
a8d8d3dc 3414 }
e7b07cee
HW		 3415}
3416
7578ecda 3417static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
e7b07cee
HW		 3418{
3419 const struct drm_connector_helper_funcs *helper =
3420 connector->helper_private;
c84dec2f
HW		 3421 struct amdgpu_dm_connector *amdgpu_dm_connector =
3422 to_amdgpu_dm_connector(connector);
e7b07cee 3423 struct drm_encoder *encoder;
c84dec2f 3424 struct edid *edid = amdgpu_dm_connector->edid;
e7b07cee
HW		 3425
3426 encoder = helper->best_encoder(connector);
3e332d3a 3427
85ee15d6
ML		 3428 if (!edid || !drm_edid_is_valid(edid)) {
3429 drm_add_modes_noedid(connector, 640, 480);
3430 } else {
3431 amdgpu_dm_connector_ddc_get_modes(connector, edid);
3432 amdgpu_dm_connector_add_common_modes(encoder, connector);
3433 }
3e332d3a 3434 amdgpu_dm_fbc_init(connector);
5099114b 3435
c84dec2f 3436 return amdgpu_dm_connector->num_modes;
e7b07cee
HW		 3437}
3438
3ee6b26b
AD		 3439void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
3440 struct amdgpu_dm_connector *aconnector,
3441 int connector_type,
3442 struct dc_link *link,
3443 int link_index)
e7b07cee
HW		 3444{
3445 struct amdgpu_device *adev = dm->ddev->dev_private;
3446
3447 aconnector->connector_id = link_index;
3448 aconnector->dc_link = link;
3449 aconnector->base.interlace_allowed = false;
3450 aconnector->base.doublescan_allowed = false;
3451 aconnector->base.stereo_allowed = false;
3452 aconnector->base.dpms = DRM_MODE_DPMS_OFF;
3453 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
3454
3455 mutex_init(&aconnector->hpd_lock);
3456
b830ebc9
HW		 3457 /* configure support HPD hot plug connector_>polled default value is 0
3458 * which means HPD hot plug not supported
3459 */
e7b07cee
HW		 3460 switch (connector_type) {
3461 case DRM_MODE_CONNECTOR_HDMIA:
3462 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3463 break;
3464 case DRM_MODE_CONNECTOR_DisplayPort:
3465 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3466 break;
3467 case DRM_MODE_CONNECTOR_DVID:
3468 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3469 break;
3470 default:
3471 break;
3472 }
3473
3474 drm_object_attach_property(&aconnector->base.base,
3475 dm->ddev->mode_config.scaling_mode_property,
3476 DRM_MODE_SCALE_NONE);
3477
3478 drm_object_attach_property(&aconnector->base.base,
3479 adev->mode_info.underscan_property,
3480 UNDERSCAN_OFF);
3481 drm_object_attach_property(&aconnector->base.base,
3482 adev->mode_info.underscan_hborder_property,
3483 0);
3484 drm_object_attach_property(&aconnector->base.base,
3485 adev->mode_info.underscan_vborder_property,
3486 0);
3487
3488}
3489
7578ecda
AD		 3490static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
3491 struct i2c_msg *msgs, int num)
e7b07cee
HW		 3492{
3493 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
3494 struct ddc_service *ddc_service = i2c->ddc_service;
3495 struct i2c_command cmd;
3496 int i;
3497 int result = -EIO;
3498
b830ebc9 3499 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
e7b07cee
HW		 3500
3501 if (!cmd.payloads)
3502 return result;
3503
3504 cmd.number_of_payloads = num;
3505 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
3506 cmd.speed = 100;
3507
3508 for (i = 0; i < num; i++) {
3509 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
3510 cmd.payloads[i].address = msgs[i].addr;
3511 cmd.payloads[i].length = msgs[i].len;
3512 cmd.payloads[i].data = msgs[i].buf;
3513 }
3514
3515 if (dal_i2caux_submit_i2c_command(
3516 ddc_service->ctx->i2caux,
3517 ddc_service->ddc_pin,
3518 &cmd))
3519 result = num;
3520
3521 kfree(cmd.payloads);
3522 return result;
3523}
3524
7578ecda 3525static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
e7b07cee
HW		 3526{
3527 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
3528}
3529
3530static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
3531 .master_xfer = amdgpu_dm_i2c_xfer,
3532 .functionality = amdgpu_dm_i2c_func,
3533};
3534
3ee6b26b
AD		 3535static struct amdgpu_i2c_adapter *
3536create_i2c(struct ddc_service *ddc_service,
3537 int link_index,
3538 int *res)
e7b07cee
HW		 3539{
3540 struct amdgpu_device *adev = ddc_service->ctx->driver_context;
3541 struct amdgpu_i2c_adapter *i2c;
3542
b830ebc9 3543 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
2a55f096
ES		 3544 if (!i2c)
3545 return NULL;
e7b07cee
HW		 3546 i2c->base.owner = THIS_MODULE;
3547 i2c->base.class = I2C_CLASS_DDC;
3548 i2c->base.dev.parent = &adev->pdev->dev;
3549 i2c->base.algo = &amdgpu_dm_i2c_algo;
b830ebc9 3550 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
e7b07cee
HW		 3551 i2c_set_adapdata(&i2c->base, i2c);
3552 i2c->ddc_service = ddc_service;
3553
3554 return i2c;
3555}
3556
89fc8d4e 3557
e7b07cee 3558/* Note: this function assumes that dc_link_detect() was called for the
b830ebc9
HW		 3559 * dc_link which will be represented by this aconnector.
3560 */
7578ecda
AD		 3561static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
3562 struct amdgpu_dm_connector *aconnector,
3563 uint32_t link_index,
3564 struct amdgpu_encoder *aencoder)
e7b07cee
HW		 3565{
3566 int res = 0;
3567 int connector_type;
3568 struct dc *dc = dm->dc;
3569 struct dc_link *link = dc_get_link_at_index(dc, link_index);
3570 struct amdgpu_i2c_adapter *i2c;
9a227d26
TSD		 3571
3572 link->priv = aconnector;
e7b07cee 3573
f1ad2f5e 3574 DRM_DEBUG_DRIVER("%s()\n", __func__);
e7b07cee
HW		 3575
3576 i2c = create_i2c(link->ddc, link->link_index, &res);
2a55f096
ES		 3577 if (!i2c) {
3578 DRM_ERROR("Failed to create i2c adapter data\n");
3579 return -ENOMEM;
3580 }
3581
e7b07cee
HW		 3582 aconnector->i2c = i2c;
3583 res = i2c_add_adapter(&i2c->base);
3584
3585 if (res) {
3586 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
3587 goto out_free;
3588 }
3589
3590 connector_type = to_drm_connector_type(link->connector_signal);
3591
3592 res = drm_connector_init(
3593 dm->ddev,
3594 &aconnector->base,
3595 &amdgpu_dm_connector_funcs,
3596 connector_type);
3597
3598 if (res) {
3599 DRM_ERROR("connector_init failed\n");
3600 aconnector->connector_id = -1;
3601 goto out_free;
3602 }
3603
3604 drm_connector_helper_add(
3605 &aconnector->base,
3606 &amdgpu_dm_connector_helper_funcs);
3607
96719c54
HW		 3608 if (aconnector->base.funcs->reset)
3609 aconnector->base.funcs->reset(&aconnector->base);
3610
e7b07cee
HW		 3611 amdgpu_dm_connector_init_helper(
3612 dm,
3613 aconnector,
3614 connector_type,
3615 link,
3616 link_index);
3617
cde4c44d 3618 drm_connector_attach_encoder(
e7b07cee
HW		 3619 &aconnector->base, &aencoder->base);
3620
3621 drm_connector_register(&aconnector->base);
3622
3623 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
3624 || connector_type == DRM_MODE_CONNECTOR_eDP)
3625 amdgpu_dm_initialize_dp_connector(dm, aconnector);
3626
e7b07cee
HW		 3627out_free:
3628 if (res) {
3629 kfree(i2c);
3630 aconnector->i2c = NULL;
3631 }
3632 return res;
3633}
3634
3635int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
3636{
3637 switch (adev->mode_info.num_crtc) {
3638 case 1:
3639 return 0x1;
3640 case 2:
3641 return 0x3;
3642 case 3:
3643 return 0x7;
3644 case 4:
3645 return 0xf;
3646 case 5:
3647 return 0x1f;
3648 case 6:
3649 default:
3650 return 0x3f;
3651 }
3652}
3653
7578ecda
AD		 3654static int amdgpu_dm_encoder_init(struct drm_device *dev,
3655 struct amdgpu_encoder *aencoder,
3656 uint32_t link_index)
e7b07cee
HW		 3657{
3658 struct amdgpu_device *adev = dev->dev_private;
3659
3660 int res = drm_encoder_init(dev,
3661 &aencoder->base,
3662 &amdgpu_dm_encoder_funcs,
3663 DRM_MODE_ENCODER_TMDS,
3664 NULL);
3665
3666 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
3667
3668 if (!res)
3669 aencoder->encoder_id = link_index;
3670 else
3671 aencoder->encoder_id = -1;
3672
3673 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
3674
3675 return res;
3676}
3677
3ee6b26b
AD		 3678static void manage_dm_interrupts(struct amdgpu_device *adev,
3679 struct amdgpu_crtc *acrtc,
3680 bool enable)
e7b07cee
HW		 3681{
3682 /*
3683 * this is not correct translation but will work as soon as VBLANK
3684 * constant is the same as PFLIP
3685 */
3686 int irq_type =
734dd01d 3687 amdgpu_display_crtc_idx_to_irq_type(
e7b07cee
HW		 3688 adev,
3689 acrtc->crtc_id);
3690
3691 if (enable) {
3692 drm_crtc_vblank_on(&acrtc->base);
3693 amdgpu_irq_get(
3694 adev,
3695 &adev->pageflip_irq,
3696 irq_type);
3697 } else {
3698
3699 amdgpu_irq_put(
3700 adev,
3701 &adev->pageflip_irq,
3702 irq_type);
3703 drm_crtc_vblank_off(&acrtc->base);
3704 }
3705}
3706
3ee6b26b
AD		 3707static bool
3708is_scaling_state_different(const struct dm_connector_state *dm_state,
3709 const struct dm_connector_state *old_dm_state)
e7b07cee
HW		 3710{
3711 if (dm_state->scaling != old_dm_state->scaling)
3712 return true;
3713 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
3714 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
3715 return true;
3716 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
3717 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
3718 return true;
b830ebc9
HW		 3719 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
3720 dm_state->underscan_vborder != old_dm_state->underscan_vborder)
3721 return true;
e7b07cee
HW		 3722 return false;
3723}
3724
3ee6b26b
AD		 3725static void remove_stream(struct amdgpu_device *adev,
3726 struct amdgpu_crtc *acrtc,
3727 struct dc_stream_state *stream)
e7b07cee
HW		 3728{
3729 /* this is the update mode case */
3730 if (adev->dm.freesync_module)
3731 mod_freesync_remove_stream(adev->dm.freesync_module, stream);
3732
3733 acrtc->otg_inst = -1;
3734 acrtc->enabled = false;
3735}
3736
7578ecda
AD		 3737static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
3738 struct dc_cursor_position *position)
2a8f6ccb 3739{
f4c2cc43 3740 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2a8f6ccb
HW		 3741 int x, y;
3742 int xorigin = 0, yorigin = 0;
3743
3744 if (!crtc || !plane->state->fb) {
3745 position->enable = false;
3746 position->x = 0;
3747 position->y = 0;
3748 return 0;
3749 }
3750
3751 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
3752 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
3753 DRM_ERROR("%s: bad cursor width or height %d x %d\n",
3754 __func__,
3755 plane->state->crtc_w,
3756 plane->state->crtc_h);
3757 return -EINVAL;
3758 }
3759
3760 x = plane->state->crtc_x;
3761 y = plane->state->crtc_y;
3762 /* avivo cursor are offset into the total surface */
3763 x += crtc->primary->state->src_x >> 16;
3764 y += crtc->primary->state->src_y >> 16;
3765 if (x < 0) {
3766 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
3767 x = 0;
3768 }
3769 if (y < 0) {
3770 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
3771 y = 0;
3772 }
3773 position->enable = true;
3774 position->x = x;
3775 position->y = y;
3776 position->x_hotspot = xorigin;
3777 position->y_hotspot = yorigin;
3778
3779 return 0;
3780}
3781
3ee6b26b
AD		 3782static void handle_cursor_update(struct drm_plane *plane,
3783 struct drm_plane_state *old_plane_state)
e7b07cee 3784{
2a8f6ccb
HW		 3785 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);
3786 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
3787 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
3788 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
3789 uint64_t address = afb ? afb->address : 0;
3790 struct dc_cursor_position position;
3791 struct dc_cursor_attributes attributes;
3792 int ret;
3793
e7b07cee
HW		 3794 if (!plane->state->fb && !old_plane_state->fb)
3795 return;
3796
f1ad2f5e 3797 DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n",
c12a7ba5
HW		 3798 __func__,
3799 amdgpu_crtc->crtc_id,
3800 plane->state->crtc_w,
3801 plane->state->crtc_h);
2a8f6ccb
HW		 3802
3803 ret = get_cursor_position(plane, crtc, &position);
3804 if (ret)
3805 return;
3806
3807 if (!position.enable) {
3808 /* turn off cursor */
3809 if (crtc_state && crtc_state->stream)
3810 dc_stream_set_cursor_position(crtc_state->stream,
3811 &position);
3812 return;
e7b07cee 3813 }
e7b07cee 3814
2a8f6ccb
HW		 3815 amdgpu_crtc->cursor_width = plane->state->crtc_w;
3816 amdgpu_crtc->cursor_height = plane->state->crtc_h;
3817
3818 attributes.address.high_part = upper_32_bits(address);
3819 attributes.address.low_part = lower_32_bits(address);
3820 attributes.width = plane->state->crtc_w;
3821 attributes.height = plane->state->crtc_h;
3822 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
3823 attributes.rotation_angle = 0;
3824 attributes.attribute_flags.value = 0;
3825
3826 attributes.pitch = attributes.width;
3827
886daac9
JZ		 3828 if (crtc_state->stream) {
3829 if (!dc_stream_set_cursor_attributes(crtc_state->stream,
3830 &attributes))
3831 DRM_ERROR("DC failed to set cursor attributes\n");
2a8f6ccb 3832
2a8f6ccb
HW		 3833 if (!dc_stream_set_cursor_position(crtc_state->stream,
3834 &position))
3835 DRM_ERROR("DC failed to set cursor position\n");
886daac9 3836 }
2a8f6ccb 3837}
e7b07cee
HW		 3838
3839static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
3840{
3841
3842 assert_spin_locked(&acrtc->base.dev->event_lock);
3843 WARN_ON(acrtc->event);
3844
3845 acrtc->event = acrtc->base.state->event;
3846
3847 /* Set the flip status */
3848 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
3849
3850 /* Mark this event as consumed */
3851 acrtc->base.state->event = NULL;
3852
3853 DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
3854 acrtc->crtc_id);
3855}
3856
3857/*
3858 * Executes flip
3859 *
3860 * Waits on all BO's fences and for proper vblank count
3861 */
3ee6b26b
AD		 3862static void amdgpu_dm_do_flip(struct drm_crtc *crtc,
3863 struct drm_framebuffer *fb,
bc6828e0
BL		 3864 uint32_t target,
3865 struct dc_state *state)
e7b07cee
HW		 3866{
3867 unsigned long flags;
3868 uint32_t target_vblank;
3869 int r, vpos, hpos;
3870 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3871 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
e68d14dd 3872 struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]);
e7b07cee 3873 struct amdgpu_device *adev = crtc->dev->dev_private;
aac6a07e 3874 bool async_flip = (crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
e7b07cee 3875 struct dc_flip_addrs addr = { {0} };
3be5262e 3876 /* TODO eliminate or rename surface_update */
e7b07cee
HW		 3877 struct dc_surface_update surface_updates[1] = { {0} };
3878 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
3879
3880
3881 /* Prepare wait for target vblank early - before the fence-waits */
23effc11 3882 target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
e7b07cee
HW		 3883 amdgpu_get_vblank_counter_kms(crtc->dev, acrtc->crtc_id);
3884
b830ebc9 3885 /* TODO This might fail and hence better not used, wait
e7b07cee
HW		 3886 * explicitly on fences instead
3887 * and in general should be called for
3888 * blocking commit to as per framework helpers
b830ebc9 3889 */
e7b07cee
HW		 3890 r = amdgpu_bo_reserve(abo, true);
3891 if (unlikely(r != 0)) {
3892 DRM_ERROR("failed to reserve buffer before flip\n");
3893 WARN_ON(1);
3894 }
3895
3896 /* Wait for all fences on this FB */
3897 WARN_ON(reservation_object_wait_timeout_rcu(abo->tbo.resv, true, false,
3898 MAX_SCHEDULE_TIMEOUT) < 0);
3899
3900 amdgpu_bo_unreserve(abo);
3901
3902 /* Wait until we're out of the vertical blank period before the one
3903 * targeted by the flip
3904 */
3905 while ((acrtc->enabled &&
aa8e286a
SL		 3906 (amdgpu_display_get_crtc_scanoutpos(adev->ddev, acrtc->crtc_id,
3907 0, &vpos, &hpos, NULL,
3908 NULL, &crtc->hwmode)
e7b07cee
HW		 3909 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
3910 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
3911 (int)(target_vblank -
3912 amdgpu_get_vblank_counter_kms(adev->ddev, acrtc->crtc_id)) > 0)) {
3913 usleep_range(1000, 1100);
3914 }
3915
3916 /* Flip */
3917 spin_lock_irqsave(&crtc->dev->event_lock, flags);
e7b07cee
HW		 3918
3919 WARN_ON(acrtc->pflip_status != AMDGPU_FLIP_NONE);
3920 WARN_ON(!acrtc_state->stream);
3921
3922 addr.address.grph.addr.low_part = lower_32_bits(afb->address);
3923 addr.address.grph.addr.high_part = upper_32_bits(afb->address);
3924 addr.flip_immediate = async_flip;
3925
3926
3927 if (acrtc->base.state->event)
3928 prepare_flip_isr(acrtc);
3929
4de9f38b
S		 3930 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
3931
3be5262e 3932 surface_updates->surface = dc_stream_get_status(acrtc_state->stream)->plane_states[0];
e7b07cee
HW		 3933 surface_updates->flip_addr = &addr;
3934
bc6828e0
BL		 3935 dc_commit_updates_for_stream(adev->dm.dc,
3936 surface_updates,
3937 1,
3938 acrtc_state->stream,
3939 NULL,
3940 &surface_updates->surface,
3941 state);
e7b07cee
HW		 3942
3943 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n",
3944 __func__,
3945 addr.address.grph.addr.high_part,
3946 addr.address.grph.addr.low_part);
e7b07cee
HW		 3947}
3948
44d09c6a
HW		 3949/*
3950 * TODO this whole function needs to go
3951 *
3952 * dc_surface_update is needlessly complex. See if we can just replace this
3953 * with a dc_plane_state and follow the atomic model a bit more closely here.
3954 */
3955static bool commit_planes_to_stream(
3956 struct dc *dc,
3957 struct dc_plane_state **plane_states,
3958 uint8_t new_plane_count,
3959 struct dm_crtc_state *dm_new_crtc_state,
3960 struct dm_crtc_state *dm_old_crtc_state,
3961 struct dc_state *state)
3962{
3963 /* no need to dynamically allocate this. it's pretty small */
3964 struct dc_surface_update updates[MAX_SURFACES];
3965 struct dc_flip_addrs *flip_addr;
3966 struct dc_plane_info *plane_info;
3967 struct dc_scaling_info *scaling_info;
3968 int i;
3969 struct dc_stream_state *dc_stream = dm_new_crtc_state->stream;
3970 struct dc_stream_update *stream_update =
3971 kzalloc(sizeof(struct dc_stream_update), GFP_KERNEL);
3972
3973 if (!stream_update) {
3974 BREAK_TO_DEBUGGER();
3975 return false;
3976 }
3977
3978 flip_addr = kcalloc(MAX_SURFACES, sizeof(struct dc_flip_addrs),
3979 GFP_KERNEL);
3980 plane_info = kcalloc(MAX_SURFACES, sizeof(struct dc_plane_info),
3981 GFP_KERNEL);
3982 scaling_info = kcalloc(MAX_SURFACES, sizeof(struct dc_scaling_info),
3983 GFP_KERNEL);
3984
3985 if (!flip_addr || !plane_info || !scaling_info) {
3986 kfree(flip_addr);
3987 kfree(plane_info);
3988 kfree(scaling_info);
3989 kfree(stream_update);
3990 return false;
3991 }
3992
3993 memset(updates, 0, sizeof(updates));
3994
3995 stream_update->src = dc_stream->src;
3996 stream_update->dst = dc_stream->dst;
3997 stream_update->out_transfer_func = dc_stream->out_transfer_func;
3998
3999 for (i = 0; i < new_plane_count; i++) {
4000 updates[i].surface = plane_states[i];
4001 updates[i].gamma =
4002 (struct dc_gamma *)plane_states[i]->gamma_correction;
4003 updates[i].in_transfer_func = plane_states[i]->in_transfer_func;
4004 flip_addr[i].address = plane_states[i]->address;
4005 flip_addr[i].flip_immediate = plane_states[i]->flip_immediate;
4006 plane_info[i].color_space = plane_states[i]->color_space;
44d09c6a
HW		 4007 plane_info[i].format = plane_states[i]->format;
4008 plane_info[i].plane_size = plane_states[i]->plane_size;
4009 plane_info[i].rotation = plane_states[i]->rotation;
4010 plane_info[i].horizontal_mirror = plane_states[i]->horizontal_mirror;
4011 plane_info[i].stereo_format = plane_states[i]->stereo_format;
4012 plane_info[i].tiling_info = plane_states[i]->tiling_info;
4013 plane_info[i].visible = plane_states[i]->visible;
4014 plane_info[i].per_pixel_alpha = plane_states[i]->per_pixel_alpha;
4015 plane_info[i].dcc = plane_states[i]->dcc;
4016 scaling_info[i].scaling_quality = plane_states[i]->scaling_quality;
4017 scaling_info[i].src_rect = plane_states[i]->src_rect;
4018 scaling_info[i].dst_rect = plane_states[i]->dst_rect;
4019 scaling_info[i].clip_rect = plane_states[i]->clip_rect;
4020
4021 updates[i].flip_addr = &flip_addr[i];
4022 updates[i].plane_info = &plane_info[i];
4023 updates[i].scaling_info = &scaling_info[i];
4024 }
4025
4026 dc_commit_updates_for_stream(
4027 dc,
4028 updates,
4029 new_plane_count,
4030 dc_stream, stream_update, plane_states, state);
4031
4032 kfree(flip_addr);
4033 kfree(plane_info);
4034 kfree(scaling_info);
4035 kfree(stream_update);
4036 return true;
4037}
4038
3be5262e 4039static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
3ee6b26b
AD		 4040 struct drm_device *dev,
4041 struct amdgpu_display_manager *dm,
4042 struct drm_crtc *pcrtc,
4043 bool *wait_for_vblank)
e7b07cee
HW		 4044{
4045 uint32_t i;
4046 struct drm_plane *plane;
0bc9706d 4047 struct drm_plane_state *old_plane_state, *new_plane_state;
0971c40e 4048 struct dc_stream_state *dc_stream_attach;
3be5262e 4049 struct dc_plane_state *plane_states_constructed[MAX_SURFACES];
e7b07cee 4050 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
0bc9706d
LSL		 4051 struct drm_crtc_state *new_pcrtc_state =
4052 drm_atomic_get_new_crtc_state(state, pcrtc);
4053 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
44d09c6a
HW		 4054 struct dm_crtc_state *dm_old_crtc_state =
4055 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
bc6828e0 4056 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
e7b07cee
HW		 4057 int planes_count = 0;
4058 unsigned long flags;
4059
4060 /* update planes when needed */
0bc9706d
LSL		 4061 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
4062 struct drm_crtc *crtc = new_plane_state->crtc;
f5ba60fe 4063 struct drm_crtc_state *new_crtc_state;
0bc9706d 4064 struct drm_framebuffer *fb = new_plane_state->fb;
e7b07cee 4065 bool pflip_needed;
54d76575 4066 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
e7b07cee
HW		 4067
4068 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
4069 handle_cursor_update(plane, old_plane_state);
4070 continue;
4071 }
4072
f5ba60fe
DD		 4073 if (!fb || !crtc || pcrtc != crtc)
4074 continue;
4075
4076 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
4077 if (!new_crtc_state->active)
e7b07cee
HW		 4078 continue;
4079
4080 pflip_needed = !state->allow_modeset;
4081
4082 spin_lock_irqsave(&crtc->dev->event_lock, flags);
4083 if (acrtc_attach->pflip_status != AMDGPU_FLIP_NONE) {
3be5262e
HW		 4084 DRM_ERROR("%s: acrtc %d, already busy\n",
4085 __func__,
4086 acrtc_attach->crtc_id);
b830ebc9 4087 /* In commit tail framework this cannot happen */
e7b07cee
HW		 4088 WARN_ON(1);
4089 }
4090 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
4091
a2a330ad 4092 if (!pflip_needed || plane->type == DRM_PLANE_TYPE_OVERLAY) {
54d76575 4093 WARN_ON(!dm_new_plane_state->dc_state);
e7b07cee 4094
54d76575 4095 plane_states_constructed[planes_count] = dm_new_plane_state->dc_state;
e7b07cee
HW		 4096
4097 dc_stream_attach = acrtc_state->stream;
4098 planes_count++;
4099
0bc9706d 4100 } else if (new_crtc_state->planes_changed) {
e7b07cee
HW		 4101 /* Assume even ONE crtc with immediate flip means
4102 * entire can't wait for VBLANK
4103 * TODO Check if it's correct
4104 */
4105 *wait_for_vblank =
0bc9706d 4106 new_pcrtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC ?
e7b07cee
HW		 4107 false : true;
4108
4109 /* TODO: Needs rework for multiplane flip */
4110 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
4111 drm_crtc_vblank_get(crtc);
4112
4113 amdgpu_dm_do_flip(
4114 crtc,
4115 fb,
23effc11 4116 (uint32_t)drm_crtc_vblank_count(crtc) + *wait_for_vblank,
bc6828e0 4117 dm_state->context);
e7b07cee
HW		 4118 }
4119
4120 }
4121
4122 if (planes_count) {
4123 unsigned long flags;
4124
0bc9706d 4125 if (new_pcrtc_state->event) {
e7b07cee
HW		 4126
4127 drm_crtc_vblank_get(pcrtc);
4128
4129 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
4130 prepare_flip_isr(acrtc_attach);
4131 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
4132 }
4133
44d09c6a
HW		 4134
4135 if (false == commit_planes_to_stream(dm->dc,
3be5262e
HW		 4136 plane_states_constructed,
4137 planes_count,
44d09c6a
HW		 4138 acrtc_state,
4139 dm_old_crtc_state,
bc6828e0 4140 dm_state->context))
3be5262e 4141 dm_error("%s: Failed to attach plane!\n", __func__);
e7b07cee
HW		 4142 } else {
4143 /*TODO BUG Here should go disable planes on CRTC. */
4144 }
4145}
4146
27b3f4fc
LSL		 4147/**
4148 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
4149 * @crtc_state: the DRM CRTC state
4150 * @stream_state: the DC stream state.
4151 *
4152 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
4153 * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
4154 */
4155static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
4156 struct dc_stream_state *stream_state)
4157{
4158 stream_state->mode_changed = crtc_state->mode_changed;
4159}
e7b07cee 4160
7578ecda
AD		 4161static int amdgpu_dm_atomic_commit(struct drm_device *dev,
4162 struct drm_atomic_state *state,
4163 bool nonblock)
e7b07cee
HW		 4164{
4165 struct drm_crtc *crtc;
c2cea706 4166 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
e7b07cee
HW		 4167 struct amdgpu_device *adev = dev->dev_private;
4168 int i;
4169
4170 /*
4171 * We evade vblanks and pflips on crtc that
4172 * should be changed. We do it here to flush & disable
4173 * interrupts before drm_swap_state is called in drm_atomic_helper_commit
4174 * it will update crtc->dm_crtc_state->stream pointer which is used in
4175 * the ISRs.
4176 */
c2cea706 4177 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
54d76575 4178 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
e7b07cee
HW		 4179 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4180
54d76575 4181 if (drm_atomic_crtc_needs_modeset(new_crtc_state) && dm_old_crtc_state->stream)
e7b07cee
HW		 4182 manage_dm_interrupts(adev, acrtc, false);
4183 }
fc9e9920
S		 4184 /* Add check here for SoC's that support hardware cursor plane, to
4185 * unset legacy_cursor_update */
e7b07cee
HW		 4186
4187 return drm_atomic_helper_commit(dev, state, nonblock);
4188
4189 /*TODO Handle EINTR, reenable IRQ*/
4190}
4191
7578ecda 4192static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
e7b07cee
HW		 4193{
4194 struct drm_device *dev = state->dev;
4195 struct amdgpu_device *adev = dev->dev_private;
4196 struct amdgpu_display_manager *dm = &adev->dm;
4197 struct dm_atomic_state *dm_state;
4198 uint32_t i, j;
5cc6dcbd 4199 struct drm_crtc *crtc;
0bc9706d 4200 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
e7b07cee
HW		 4201 unsigned long flags;
4202 bool wait_for_vblank = true;
4203 struct drm_connector *connector;
c2cea706 4204 struct drm_connector_state *old_con_state, *new_con_state;
54d76575 4205 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
fe2a1965 4206 int crtc_disable_count = 0;
e7b07cee
HW		 4207
4208 drm_atomic_helper_update_legacy_modeset_state(dev, state);
4209
4210 dm_state = to_dm_atomic_state(state);
4211
4212 /* update changed items */
0bc9706d 4213 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
e7b07cee 4214 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 4215
54d76575
LSL		 4216 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4217 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
e7b07cee 4218
f1ad2f5e 4219 DRM_DEBUG_DRIVER(
e7b07cee
HW		 4220 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
4221 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
4222 "connectors_changed:%d\n",
4223 acrtc->crtc_id,
0bc9706d
LSL		 4224 new_crtc_state->enable,
4225 new_crtc_state->active,
4226 new_crtc_state->planes_changed,
4227 new_crtc_state->mode_changed,
4228 new_crtc_state->active_changed,
4229 new_crtc_state->connectors_changed);
e7b07cee 4230
27b3f4fc
LSL		 4231 /* Copy all transient state flags into dc state */
4232 if (dm_new_crtc_state->stream) {
4233 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
4234 dm_new_crtc_state->stream);
4235 }
4236
e7b07cee
HW		 4237 /* handles headless hotplug case, updating new_state and
4238 * aconnector as needed
4239 */
4240
54d76575 4241 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
e7b07cee 4242
f1ad2f5e 4243 DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
e7b07cee 4244
54d76575 4245 if (!dm_new_crtc_state->stream) {
e7b07cee 4246 /*
b830ebc9
HW		 4247 * this could happen because of issues with
4248 * userspace notifications delivery.
4249 * In this case userspace tries to set mode on
4250 * display which is disconnect in fact.
4251 * dc_sink in NULL in this case on aconnector.
4252 * We expect reset mode will come soon.
4253 *
4254 * This can also happen when unplug is done
4255 * during resume sequence ended
4256 *
4257 * In this case, we want to pretend we still
4258 * have a sink to keep the pipe running so that
4259 * hw state is consistent with the sw state
4260 */
f1ad2f5e 4261 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
e7b07cee
HW		 4262 __func__, acrtc->base.base.id);
4263 continue;
4264 }
4265
54d76575
LSL		 4266 if (dm_old_crtc_state->stream)
4267 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
e7b07cee 4268
97028037
LP		 4269 pm_runtime_get_noresume(dev->dev);
4270
e7b07cee 4271 acrtc->enabled = true;
0bc9706d
LSL		 4272 acrtc->hw_mode = new_crtc_state->mode;
4273 crtc->hwmode = new_crtc_state->mode;
4274 } else if (modereset_required(new_crtc_state)) {
f1ad2f5e 4275 DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
e7b07cee
HW		 4276
4277 /* i.e. reset mode */
54d76575
LSL		 4278 if (dm_old_crtc_state->stream)
4279 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
e7b07cee
HW		 4280 }
4281 } /* for_each_crtc_in_state() */
4282
4283 /*
4284 * Add streams after required streams from new and replaced streams
4285 * are removed from freesync module
4286 */
4287 if (adev->dm.freesync_module) {
8b8f27f9
LSL		 4288 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
4289 new_crtc_state, i) {
c84dec2f 4290 struct amdgpu_dm_connector *aconnector = NULL;
f01a2cf0
LSL		 4291 struct dm_connector_state *dm_new_con_state = NULL;
4292 struct amdgpu_crtc *acrtc = NULL;
1c77d4ee 4293 bool modeset_needed;
b830ebc9 4294
54d76575 4295 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
1c77d4ee
LSL		 4296 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4297 modeset_needed = modeset_required(
4298 new_crtc_state,
4299 dm_new_crtc_state->stream,
4300 dm_old_crtc_state->stream);
4301 /* We add stream to freesync if:
4302 * 1. Said stream is not null, and
4303 * 2. A modeset is requested. This means that the
4304 * stream was removed previously, and needs to be
4305 * replaced.
4306 */
4307 if (dm_new_crtc_state->stream == NULL ||
4308 !modeset_needed)
4309 continue;
4310
f01a2cf0 4311 acrtc = to_amdgpu_crtc(crtc);
e7b07cee 4312
f01a2cf0
LSL		 4313 aconnector =
4314 amdgpu_dm_find_first_crtc_matching_connector(
4315 state, crtc);
e7b07cee 4316 if (!aconnector) {
8b8f27f9
LSL		 4317 DRM_DEBUG_DRIVER("Atomic commit: Failed to "
4318 "find connector for acrtc "
4319 "id:%d skipping freesync "
4320 "init\n",
4321 acrtc->crtc_id);
e7b07cee
HW		 4322 continue;
4323 }
4324
4325 mod_freesync_add_stream(adev->dm.freesync_module,
f01a2cf0
LSL		 4326 dm_new_crtc_state->stream,
4327 &aconnector->caps);
4328 new_con_state = drm_atomic_get_new_connector_state(
4329 state, &aconnector->base);
4330 dm_new_con_state = to_dm_connector_state(new_con_state);
4331
1c77d4ee
LSL		 4332 mod_freesync_set_user_enable(adev->dm.freesync_module,
4333 &dm_new_crtc_state->stream,
4334 1,
4335 &dm_new_con_state->user_enable);
bfe1708c 4336 }
e7b07cee
HW		 4337 }
4338
fa2123db
ML		 4339 if (dm_state->context) {
4340 dm_enable_per_frame_crtc_master_sync(dm_state->context);
608ac7bb 4341 WARN_ON(!dc_commit_state(dm->dc, dm_state->context));
fa2123db 4342 }
e7b07cee 4343
0bc9706d 4344 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 4345 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 4346
54d76575 4347 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 4348
54d76575 4349 if (dm_new_crtc_state->stream != NULL) {
e7b07cee 4350 const struct dc_stream_status *status =
54d76575 4351 dc_stream_get_status(dm_new_crtc_state->stream);
e7b07cee
HW		 4352
4353 if (!status)
54d76575 4354 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
e7b07cee
HW		 4355 else
4356 acrtc->otg_inst = status->primary_otg_inst;
4357 }
4358 }
4359
ebdd27e1 4360 /* Handle scaling and underscan changes*/
c2cea706 4361 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 4362 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
4363 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
4364 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
e7b07cee
HW		 4365 struct dc_stream_status *status = NULL;
4366
44d09c6a 4367 if (acrtc) {
0bc9706d 4368 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
44d09c6a
HW		 4369 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
4370 }
0bc9706d 4371
e7b07cee 4372 /* Skip any modesets/resets */
0bc9706d 4373 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
e7b07cee
HW		 4374 continue;
4375
4376 /* Skip any thing not scale or underscan changes */
54d76575 4377 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
e7b07cee
HW		 4378 continue;
4379
54d76575 4380 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 4381
54d76575
LSL		 4382 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
4383 dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream);
e7b07cee 4384
70e8ffc5
HW		 4385 if (!dm_new_crtc_state->stream)
4386 continue;
4387
54d76575 4388 status = dc_stream_get_status(dm_new_crtc_state->stream);
e7b07cee 4389 WARN_ON(!status);
3be5262e 4390 WARN_ON(!status->plane_count);
e7b07cee 4391
e7b07cee 4392 /*TODO How it works with MPO ?*/
44d09c6a 4393 if (!commit_planes_to_stream(
e7b07cee 4394 dm->dc,
3be5262e
HW		 4395 status->plane_states,
4396 status->plane_count,
44d09c6a
HW		 4397 dm_new_crtc_state,
4398 to_dm_crtc_state(old_crtc_state),
bc6828e0 4399 dm_state->context))
e7b07cee
HW		 4400 dm_error("%s: Failed to update stream scaling!\n", __func__);
4401 }
4402
e1fc2dca
LSL		 4403 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
4404 new_crtc_state, i) {
e7b07cee
HW		 4405 /*
4406 * loop to enable interrupts on newly arrived crtc
4407 */
e1fc2dca
LSL		 4408 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4409 bool modeset_needed;
b830ebc9 4410
fe2a1965
LP		 4411 if (old_crtc_state->active && !new_crtc_state->active)
4412 crtc_disable_count++;
4413
54d76575 4414 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e1fc2dca
LSL		 4415 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4416 modeset_needed = modeset_required(
4417 new_crtc_state,
4418 dm_new_crtc_state->stream,
4419 dm_old_crtc_state->stream);
4420
4421 if (dm_new_crtc_state->stream == NULL || !modeset_needed)
4422 continue;
e7b07cee
HW		 4423
4424 if (adev->dm.freesync_module)
4425 mod_freesync_notify_mode_change(
e1fc2dca
LSL		 4426 adev->dm.freesync_module,
4427 &dm_new_crtc_state->stream, 1);
e7b07cee
HW		 4428
4429 manage_dm_interrupts(adev, acrtc, true);
4430 }
4431
4432 /* update planes when needed per crtc*/
5cc6dcbd 4433 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
54d76575 4434 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 4435
54d76575 4436 if (dm_new_crtc_state->stream)
5cc6dcbd 4437 amdgpu_dm_commit_planes(state, dev, dm, crtc, &wait_for_vblank);
e7b07cee
HW		 4438 }
4439
4440
4441 /*
4442 * send vblank event on all events not handled in flip and
4443 * mark consumed event for drm_atomic_helper_commit_hw_done
4444 */
4445 spin_lock_irqsave(&adev->ddev->event_lock, flags);
0bc9706d 4446 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 4447
0bc9706d
LSL		 4448 if (new_crtc_state->event)
4449 drm_send_event_locked(dev, &new_crtc_state->event->base);
e7b07cee 4450
0bc9706d 4451 new_crtc_state->event = NULL;
e7b07cee
HW		 4452 }
4453 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
4454
4455 /* Signal HW programming completion */
4456 drm_atomic_helper_commit_hw_done(state);
4457
4458 if (wait_for_vblank)
320a1274 4459 drm_atomic_helper_wait_for_flip_done(dev, state);
e7b07cee
HW		 4460
4461 drm_atomic_helper_cleanup_planes(dev, state);
97028037
LP		 4462
4463 /* Finally, drop a runtime PM reference for each newly disabled CRTC,
4464 * so we can put the GPU into runtime suspend if we're not driving any
4465 * displays anymore
4466 */
fe2a1965
LP		 4467 for (i = 0; i < crtc_disable_count; i++)
4468 pm_runtime_put_autosuspend(dev->dev);
97028037 4469 pm_runtime_mark_last_busy(dev->dev);
e7b07cee
HW		 4470}
4471
4472
4473static int dm_force_atomic_commit(struct drm_connector *connector)
4474{
4475 int ret = 0;
4476 struct drm_device *ddev = connector->dev;
4477 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
4478 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
4479 struct drm_plane *plane = disconnected_acrtc->base.primary;
4480 struct drm_connector_state *conn_state;
4481 struct drm_crtc_state *crtc_state;
4482 struct drm_plane_state *plane_state;
4483
4484 if (!state)
4485 return -ENOMEM;
4486
4487 state->acquire_ctx = ddev->mode_config.acquire_ctx;
4488
4489 /* Construct an atomic state to restore previous display setting */
4490
4491 /*
4492 * Attach connectors to drm_atomic_state
4493 */
4494 conn_state = drm_atomic_get_connector_state(state, connector);
4495
4496 ret = PTR_ERR_OR_ZERO(conn_state);
4497 if (ret)
4498 goto err;
4499
4500 /* Attach crtc to drm_atomic_state*/
4501 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
4502
4503 ret = PTR_ERR_OR_ZERO(crtc_state);
4504 if (ret)
4505 goto err;
4506
4507 /* force a restore */
4508 crtc_state->mode_changed = true;
4509
4510 /* Attach plane to drm_atomic_state */
4511 plane_state = drm_atomic_get_plane_state(state, plane);
4512
4513 ret = PTR_ERR_OR_ZERO(plane_state);
4514 if (ret)
4515 goto err;
4516
4517
4518 /* Call commit internally with the state we just constructed */
4519 ret = drm_atomic_commit(state);
4520 if (!ret)
4521 return 0;
4522
4523err:
4524 DRM_ERROR("Restoring old state failed with %i\n", ret);
4525 drm_atomic_state_put(state);
4526
4527 return ret;
4528}
4529
4530/*
4531 * This functions handle all cases when set mode does not come upon hotplug.
4532 * This include when the same display is unplugged then plugged back into the
4533 * same port and when we are running without usermode desktop manager supprot
4534 */
3ee6b26b
AD		 4535void dm_restore_drm_connector_state(struct drm_device *dev,
4536 struct drm_connector *connector)
e7b07cee 4537{
c84dec2f 4538 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 4539 struct amdgpu_crtc *disconnected_acrtc;
4540 struct dm_crtc_state *acrtc_state;
4541
4542 if (!aconnector->dc_sink || !connector->state || !connector->encoder)
4543 return;
4544
4545 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
70e8ffc5
HW		 4546 if (!disconnected_acrtc)
4547 return;
e7b07cee 4548
70e8ffc5
HW		 4549 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
4550 if (!acrtc_state->stream)
e7b07cee
HW		 4551 return;
4552
4553 /*
4554 * If the previous sink is not released and different from the current,
4555 * we deduce we are in a state where we can not rely on usermode call
4556 * to turn on the display, so we do it here
4557 */
4558 if (acrtc_state->stream->sink != aconnector->dc_sink)
4559 dm_force_atomic_commit(&aconnector->base);
4560}
4561
e7b07cee
HW		 4562/*`
4563 * Grabs all modesetting locks to serialize against any blocking commits,
4564 * Waits for completion of all non blocking commits.
4565 */
3ee6b26b
AD		 4566static int do_aquire_global_lock(struct drm_device *dev,
4567 struct drm_atomic_state *state)
e7b07cee
HW		 4568{
4569 struct drm_crtc *crtc;
4570 struct drm_crtc_commit *commit;
4571 long ret;
4572
4573 /* Adding all modeset locks to aquire_ctx will
4574 * ensure that when the framework release it the
4575 * extra locks we are locking here will get released to
4576 */
4577 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
4578 if (ret)
4579 return ret;
4580
4581 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4582 spin_lock(&crtc->commit_lock);
4583 commit = list_first_entry_or_null(&crtc->commit_list,
4584 struct drm_crtc_commit, commit_entry);
4585 if (commit)
4586 drm_crtc_commit_get(commit);
4587 spin_unlock(&crtc->commit_lock);
4588
4589 if (!commit)
4590 continue;
4591
4592 /* Make sure all pending HW programming completed and
4593 * page flips done
4594 */
4595 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
4596
4597 if (ret > 0)
4598 ret = wait_for_completion_interruptible_timeout(
4599 &commit->flip_done, 10*HZ);
4600
4601 if (ret == 0)
4602 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
b830ebc9 4603 "timed out\n", crtc->base.id, crtc->name);
e7b07cee
HW		 4604
4605 drm_crtc_commit_put(commit);
4606 }
4607
4608 return ret < 0 ? ret : 0;
4609}
4610
3ee6b26b
AD		 4611static int dm_update_crtcs_state(struct dc *dc,
4612 struct drm_atomic_state *state,
4613 bool enable,
4614 bool *lock_and_validation_needed)
e7b07cee 4615{
e7b07cee 4616 struct drm_crtc *crtc;
c2cea706 4617 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
62f55537 4618 int i;
54d76575 4619 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
1dc90497 4620 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
9635b754 4621 struct dc_stream_state *new_stream;
62f55537 4622 int ret = 0;
d4d4a645 4623
62f55537
AG		 4624 /*TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set */
4625 /* update changed items */
c2cea706 4626 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
62f55537 4627 struct amdgpu_crtc *acrtc = NULL;
c84dec2f 4628 struct amdgpu_dm_connector *aconnector = NULL;
a9e8d275
DF		 4629 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
4630 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
f2877656 4631 struct drm_plane_state *new_plane_state = NULL;
e7b07cee 4632
9635b754
DS		 4633 new_stream = NULL;
4634
54d76575
LSL		 4635 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4636 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
62f55537 4637 acrtc = to_amdgpu_crtc(crtc);
e7b07cee 4638
f2877656
HW		 4639 new_plane_state = drm_atomic_get_new_plane_state(state, new_crtc_state->crtc->primary);
4640
4641 if (new_crtc_state->enable && new_plane_state && !new_plane_state->fb) {
4642 ret = -EINVAL;
4643 goto fail;
4644 }
4645
1daf8c63 4646 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
19f89e23 4647
62f55537 4648 /* TODO This hack should go away */
f4ac176e
JZ		 4649 if (aconnector && enable) {
4650 // Make sure fake sink is created in plug-in scenario
a9e8d275 4651 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
c2cea706 4652 &aconnector->base);
a9e8d275
DF		 4653 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
4654 &aconnector->base);
19f89e23 4655
a9e8d275
DF		 4656 if (IS_ERR(drm_new_conn_state)) {
4657 ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
62f55537
AG		 4658 break;
4659 }
19f89e23 4660
a9e8d275
DF		 4661 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
4662 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
19f89e23 4663
62f55537 4664 new_stream = create_stream_for_sink(aconnector,
c2cea706 4665 &new_crtc_state->mode,
a9e8d275 4666 dm_new_conn_state);
19f89e23 4667
62f55537
AG		 4668 /*
4669 * we can have no stream on ACTION_SET if a display
4670 * was disconnected during S3, in this case it not and
4671 * error, the OS will be updated after detection, and
4672 * do the right thing on next atomic commit
4673 */
19f89e23 4674
62f55537 4675 if (!new_stream) {
f1ad2f5e 4676 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
62f55537
AG		 4677 __func__, acrtc->base.base.id);
4678 break;
19f89e23 4679 }
e7b07cee 4680
a97599a4
LSL		 4681 if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
4682 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
4683 new_crtc_state->mode_changed = false;
4684 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
4685 new_crtc_state->mode_changed);
4686 }
62f55537 4687 }
b830ebc9 4688
c2cea706 4689 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9635b754 4690 goto next_crtc;
e7b07cee 4691
f1ad2f5e 4692 DRM_DEBUG_DRIVER(
e7b07cee
HW		 4693 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
4694 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
4695 "connectors_changed:%d\n",
4696 acrtc->crtc_id,
c2cea706
LSL		 4697 new_crtc_state->enable,
4698 new_crtc_state->active,
4699 new_crtc_state->planes_changed,
4700 new_crtc_state->mode_changed,
4701 new_crtc_state->active_changed,
4702 new_crtc_state->connectors_changed);
e7b07cee 4703
62f55537
AG		 4704 /* Remove stream for any changed/disabled CRTC */
4705 if (!enable) {
4706
54d76575 4707 if (!dm_old_crtc_state->stream)
9635b754 4708 goto next_crtc;
62f55537 4709
f1ad2f5e 4710 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
62f55537 4711 crtc->base.id);
e7b07cee 4712
1dc90497 4713 /* i.e. reset mode */
62c933f9 4714 if (dc_remove_stream_from_ctx(
62f55537
AG		 4715 dc,
4716 dm_state->context,
62c933f9 4717 dm_old_crtc_state->stream) != DC_OK) {
62f55537 4718 ret = -EINVAL;
9635b754 4719 goto fail;
62f55537
AG		 4720 }
4721
54d76575
LSL		 4722 dc_stream_release(dm_old_crtc_state->stream);
4723 dm_new_crtc_state->stream = NULL;
62f55537
AG		 4724
4725 *lock_and_validation_needed = true;
4726
4727 } else {/* Add stream for any updated/enabled CRTC */
fc17235f
JZ		 4728 /*
4729 * Quick fix to prevent NULL pointer on new_stream when
4730 * added MST connectors not found in existing crtc_state in the chained mode
4731 * TODO: need to dig out the root cause of that
4732 */
4733 if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port))
1bed4d09 4734 goto next_crtc;
62f55537 4735
c2cea706 4736 if (modereset_required(new_crtc_state))
9635b754 4737 goto next_crtc;
62f55537 4738
c2cea706 4739 if (modeset_required(new_crtc_state, new_stream,
54d76575 4740 dm_old_crtc_state->stream)) {
62f55537 4741
54d76575 4742 WARN_ON(dm_new_crtc_state->stream);
62f55537 4743
54d76575 4744 dm_new_crtc_state->stream = new_stream;
27b3f4fc 4745
62f55537
AG		 4746 dc_stream_retain(new_stream);
4747
f1ad2f5e 4748 DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n",
62f55537 4749 crtc->base.id);
1dc90497 4750
13ab1b44 4751 if (dc_add_stream_to_ctx(
1dc90497
AG		 4752 dc,
4753 dm_state->context,
13ab1b44 4754 dm_new_crtc_state->stream) != DC_OK) {
1dc90497 4755 ret = -EINVAL;
9635b754 4756 goto fail;
1dc90497
AG		 4757 }
4758
62f55537 4759 *lock_and_validation_needed = true;
9b690ef3 4760 }
62f55537 4761 }
9b690ef3 4762
9635b754 4763next_crtc:
62f55537
AG		 4764 /* Release extra reference */
4765 if (new_stream)
4766 dc_stream_release(new_stream);
e277adc5
LSL		 4767
4768 /*
4769 * We want to do dc stream updates that do not require a
4770 * full modeset below.
4771 */
20fa2ff0
LSL		 4772 if (!(enable && aconnector && new_crtc_state->enable &&
4773 new_crtc_state->active))
e277adc5
LSL		 4774 continue;
4775 /*
4776 * Given above conditions, the dc state cannot be NULL because:
20fa2ff0
LSL		 4777 * 1. We're in the process of enabling CRTCs (just been added
4778 * to the dc context, or already is on the context)
4779 * 2. Has a valid connector attached, and
4780 * 3. Is currently active and enabled.
4781 * => The dc stream state currently exists.
e277adc5
LSL		 4782 */
4783 BUG_ON(dm_new_crtc_state->stream == NULL);
4784
a9e8d275
DF		 4785 /* Scaling or underscan settings */
4786 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state))
4787 update_stream_scaling_settings(
4788 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
4789
bc13f2f8
LSL		 4790 /*
4791 * Color management settings. We also update color properties
4792 * when a modeset is needed, to ensure it gets reprogrammed.
4793 */
4794 if (dm_new_crtc_state->base.color_mgmt_changed ||
4795 drm_atomic_crtc_needs_modeset(new_crtc_state)) {
e277adc5
LSL		 4796 ret = amdgpu_dm_set_regamma_lut(dm_new_crtc_state);
4797 if (ret)
4798 goto fail;
4799 amdgpu_dm_set_ctm(dm_new_crtc_state);
4800 }
62f55537 4801 }
e7b07cee 4802
62f55537 4803 return ret;
9635b754
DS		 4804
4805fail:
4806 if (new_stream)
4807 dc_stream_release(new_stream);
4808 return ret;
62f55537 4809}
9b690ef3 4810
3ee6b26b
AD		 4811static int dm_update_planes_state(struct dc *dc,
4812 struct drm_atomic_state *state,
4813 bool enable,
4814 bool *lock_and_validation_needed)
62f55537
AG		 4815{
4816 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
0bc9706d 4817 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
62f55537
AG		 4818 struct drm_plane *plane;
4819 struct drm_plane_state *old_plane_state, *new_plane_state;
54d76575 4820 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
62f55537 4821 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
54d76575 4822 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
62f55537
AG		 4823 int i ;
4824 /* TODO return page_flip_needed() function */
4825 bool pflip_needed = !state->allow_modeset;
4826 int ret = 0;
e7b07cee 4827
9b690ef3 4828
df534fff
S		 4829 /* Add new planes, in reverse order as DC expectation */
4830 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
62f55537
AG		 4831 new_plane_crtc = new_plane_state->crtc;
4832 old_plane_crtc = old_plane_state->crtc;
54d76575
LSL		 4833 dm_new_plane_state = to_dm_plane_state(new_plane_state);
4834 dm_old_plane_state = to_dm_plane_state(old_plane_state);
62f55537
AG		 4835
4836 /*TODO Implement atomic check for cursor plane */
4837 if (plane->type == DRM_PLANE_TYPE_CURSOR)
4838 continue;
9b690ef3 4839
62f55537
AG		 4840 /* Remove any changed/removed planes */
4841 if (!enable) {
a2a330ad
S		 4842 if (pflip_needed &&
4843 plane->type != DRM_PLANE_TYPE_OVERLAY)
c21b68c5 4844 continue;
a7b06724 4845
62f55537
AG		 4846 if (!old_plane_crtc)
4847 continue;
4848
0bc9706d
LSL		 4849 old_crtc_state = drm_atomic_get_old_crtc_state(
4850 state, old_plane_crtc);
54d76575 4851 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9b690ef3 4852
54d76575 4853 if (!dm_old_crtc_state->stream)
62f55537
AG		 4854 continue;
4855
f2877656 4856 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
62f55537 4857 plane->base.id, old_plane_crtc->base.id);
9b690ef3 4858
62f55537
AG		 4859 if (!dc_remove_plane_from_context(
4860 dc,
54d76575
LSL		 4861 dm_old_crtc_state->stream,
4862 dm_old_plane_state->dc_state,
62f55537
AG		 4863 dm_state->context)) {
4864
4865 ret = EINVAL;
4866 return ret;
e7b07cee
HW		 4867 }
4868
9b690ef3 4869
54d76575
LSL		 4870 dc_plane_state_release(dm_old_plane_state->dc_state);
4871 dm_new_plane_state->dc_state = NULL;
1dc90497 4872
62f55537 4873 *lock_and_validation_needed = true;
1dc90497 4874
62f55537 4875 } else { /* Add new planes */
8c45c5db 4876 struct dc_plane_state *dc_new_plane_state;
1dc90497 4877
62f55537
AG		 4878 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
4879 continue;
e7b07cee 4880
62f55537
AG		 4881 if (!new_plane_crtc)
4882 continue;
e7b07cee 4883
62f55537 4884 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
54d76575 4885 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
1dc90497 4886
54d76575 4887 if (!dm_new_crtc_state->stream)
62f55537
AG		 4888 continue;
4889
a2a330ad
S		 4890 if (pflip_needed &&
4891 plane->type != DRM_PLANE_TYPE_OVERLAY)
c21b68c5 4892 continue;
62f55537 4893
54d76575 4894 WARN_ON(dm_new_plane_state->dc_state);
9b690ef3 4895
8c45c5db 4896 dc_new_plane_state = dc_create_plane_state(dc);
d5400aab
LSL		 4897 if (!dc_new_plane_state)
4898 return -ENOMEM;
62f55537 4899
8c45c5db
LSL		 4900 DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
4901 plane->base.id, new_plane_crtc->base.id);
4902
62f55537
AG		 4903 ret = fill_plane_attributes(
4904 new_plane_crtc->dev->dev_private,
8c45c5db 4905 dc_new_plane_state,
62f55537 4906 new_plane_state,
9817d5f5 4907 new_crtc_state);
8c45c5db
LSL		 4908 if (ret) {
4909 dc_plane_state_release(dc_new_plane_state);
62f55537 4910 return ret;
8c45c5db 4911 }
62f55537 4912
8c45c5db
LSL		 4913 /*
4914 * Any atomic check errors that occur after this will
4915 * not need a release. The plane state will be attached
4916 * to the stream, and therefore part of the atomic
4917 * state. It'll be released when the atomic state is
4918 * cleaned.
4919 */
62f55537
AG		 4920 if (!dc_add_plane_to_context(
4921 dc,
54d76575 4922 dm_new_crtc_state->stream,
8c45c5db 4923 dc_new_plane_state,
62f55537
AG		 4924 dm_state->context)) {
4925
8c45c5db 4926 dc_plane_state_release(dc_new_plane_state);
d5400aab 4927 return -EINVAL;
e7b07cee 4928 }
62f55537 4929
8c45c5db
LSL		 4930 dm_new_plane_state->dc_state = dc_new_plane_state;
4931
000b59ea
LSL		 4932 /* Tell DC to do a full surface update every time there
4933 * is a plane change. Inefficient, but works for now.
4934 */
4935 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
4936
62f55537 4937 *lock_and_validation_needed = true;
e7b07cee 4938 }
62f55537 4939 }
e7b07cee
HW		 4940
4941
62f55537
AG		 4942 return ret;
4943}
4944
7578ecda
AD		 4945static int amdgpu_dm_atomic_check(struct drm_device *dev,
4946 struct drm_atomic_state *state)
62f55537 4947{
62f55537
AG		 4948 struct amdgpu_device *adev = dev->dev_private;
4949 struct dc *dc = adev->dm.dc;
4950 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
4951 struct drm_connector *connector;
c2cea706 4952 struct drm_connector_state *old_con_state, *new_con_state;
62f55537 4953 struct drm_crtc *crtc;
fc9e9920 4954 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
1e88ad0a 4955 int ret, i;
e7b07cee 4956
62f55537
AG		 4957 /*
4958 * This bool will be set for true for any modeset/reset
4959 * or plane update which implies non fast surface update.
4960 */
4961 bool lock_and_validation_needed = false;
4962
4963 ret = drm_atomic_helper_check_modeset(dev, state);
01e28f9c
MD		 4964 if (ret)
4965 goto fail;
62f55537 4966
1e88ad0a
S		 4967 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
4968 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
4969 !new_crtc_state->color_mgmt_changed)
4970 continue;
7bef1af3 4971
1e88ad0a
S		 4972 if (!new_crtc_state->enable)
4973 continue;
fc9e9920 4974
1e88ad0a
S		 4975 ret = drm_atomic_add_affected_connectors(state, crtc);
4976 if (ret)
4977 return ret;
fc9e9920 4978
1e88ad0a
S		 4979 ret = drm_atomic_add_affected_planes(state, crtc);
4980 if (ret)
4981 goto fail;
e7b07cee
HW		 4982 }
4983
62f55537
AG		 4984 dm_state->context = dc_create_state();
4985 ASSERT(dm_state->context);
f36cc577 4986 dc_resource_state_copy_construct_current(dc, dm_state->context);
62f55537
AG		 4987
4988 /* Remove exiting planes if they are modified */
4989 ret = dm_update_planes_state(dc, state, false, &lock_and_validation_needed);
4990 if (ret) {
4991 goto fail;
4992 }
4993
4994 /* Disable all crtcs which require disable */
4995 ret = dm_update_crtcs_state(dc, state, false, &lock_and_validation_needed);
4996 if (ret) {
4997 goto fail;
4998 }
4999
5000 /* Enable all crtcs which require enable */
5001 ret = dm_update_crtcs_state(dc, state, true, &lock_and_validation_needed);
5002 if (ret) {
5003 goto fail;
5004 }
5005
5006 /* Add new/modified planes */
5007 ret = dm_update_planes_state(dc, state, true, &lock_and_validation_needed);
5008 if (ret) {
5009 goto fail;
5010 }
5011
b349f76e
ES		 5012 /* Run this here since we want to validate the streams we created */
5013 ret = drm_atomic_helper_check_planes(dev, state);
5014 if (ret)
5015 goto fail;
62f55537 5016
ebdd27e1 5017 /* Check scaling and underscan changes*/
e7b07cee
HW		 5018 /*TODO Removed scaling changes validation due to inability to commit
5019 * new stream into context w\o causing full reset. Need to
5020 * decide how to handle.
5021 */
c2cea706 5022 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 5023 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
5024 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
5025 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
e7b07cee
HW		 5026
5027 /* Skip any modesets/resets */
0bc9706d
LSL		 5028 if (!acrtc || drm_atomic_crtc_needs_modeset(
5029 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
e7b07cee
HW		 5030 continue;
5031
b830ebc9 5032 /* Skip any thing not scale or underscan changes */
54d76575 5033 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
e7b07cee
HW		 5034 continue;
5035
5036 lock_and_validation_needed = true;
5037 }
5038
e7b07cee
HW		 5039 /*
5040 * For full updates case when
5041 * removing/adding/updating streams on once CRTC while flipping
5042 * on another CRTC,
5043 * acquiring global lock will guarantee that any such full
5044 * update commit
5045 * will wait for completion of any outstanding flip using DRMs
5046 * synchronization events.
5047 */
5048
5049 if (lock_and_validation_needed) {
5050
5051 ret = do_aquire_global_lock(dev, state);
5052 if (ret)
5053 goto fail;
1dc90497 5054
e750d56d 5055 if (dc_validate_global_state(dc, dm_state->context) != DC_OK) {
e7b07cee
HW		 5056 ret = -EINVAL;
5057 goto fail;
5058 }
5059 }
5060
5061 /* Must be success */
5062 WARN_ON(ret);
5063 return ret;
5064
5065fail:
5066 if (ret == -EDEADLK)
01e28f9c 5067 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
e7b07cee 5068 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
01e28f9c 5069 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
e7b07cee 5070 else
01e28f9c 5071 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
e7b07cee
HW		 5072
5073 return ret;
5074}
5075
3ee6b26b
AD		 5076static bool is_dp_capable_without_timing_msa(struct dc *dc,
5077 struct amdgpu_dm_connector *amdgpu_dm_connector)
e7b07cee
HW		 5078{
5079 uint8_t dpcd_data;
5080 bool capable = false;
5081
c84dec2f 5082 if (amdgpu_dm_connector->dc_link &&
e7b07cee
HW		 5083 dm_helpers_dp_read_dpcd(
5084 NULL,
c84dec2f 5085 amdgpu_dm_connector->dc_link,
e7b07cee
HW		 5086 DP_DOWN_STREAM_PORT_COUNT,
5087 &dpcd_data,
5088 sizeof(dpcd_data))) {
5089 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
5090 }
5091
5092 return capable;
5093}
3ee6b26b
AD		 5094void amdgpu_dm_add_sink_to_freesync_module(struct drm_connector *connector,
5095 struct edid *edid)
e7b07cee
HW		 5096{
5097 int i;
e7b07cee
HW		 5098 bool edid_check_required;
5099 struct detailed_timing *timing;
5100 struct detailed_non_pixel *data;
5101 struct detailed_data_monitor_range *range;
c84dec2f
HW		 5102 struct amdgpu_dm_connector *amdgpu_dm_connector =
5103 to_amdgpu_dm_connector(connector);
8218d7f1 5104 struct dm_connector_state *dm_con_state;
e7b07cee
HW		 5105
5106 struct drm_device *dev = connector->dev;
5107 struct amdgpu_device *adev = dev->dev_private;
b830ebc9 5108
8218d7f1
HW		 5109 if (!connector->state) {
5110 DRM_ERROR("%s - Connector has no state", __func__);
5111 return;
5112 }
5113
5114 dm_con_state = to_dm_connector_state(connector->state);
5115
e7b07cee 5116 edid_check_required = false;
c84dec2f 5117 if (!amdgpu_dm_connector->dc_sink) {
e7b07cee
HW		 5118 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
5119 return;
5120 }
5121 if (!adev->dm.freesync_module)
5122 return;
5123 /*
5124 * if edid non zero restrict freesync only for dp and edp
5125 */
5126 if (edid) {
c84dec2f
HW		 5127 if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
5128 || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
e7b07cee
HW		 5129 edid_check_required = is_dp_capable_without_timing_msa(
5130 adev->dm.dc,
c84dec2f 5131 amdgpu_dm_connector);
e7b07cee
HW		 5132 }
5133 }
8218d7f1 5134 dm_con_state->freesync_capable = false;
e7b07cee
HW		 5135 if (edid_check_required == true && (edid->version > 1 ||
5136 (edid->version == 1 && edid->revision > 1))) {
5137 for (i = 0; i < 4; i++) {
5138
5139 timing = &edid->detailed_timings[i];
5140 data = &timing->data.other_data;
5141 range = &data->data.range;
5142 /*
5143 * Check if monitor has continuous frequency mode
5144 */
5145 if (data->type != EDID_DETAIL_MONITOR_RANGE)
5146 continue;
5147 /*
5148 * Check for flag range limits only. If flag == 1 then
5149 * no additional timing information provided.
5150 * Default GTF, GTF Secondary curve and CVT are not
5151 * supported
5152 */
5153 if (range->flags != 1)
5154 continue;
5155
c84dec2f
HW		 5156 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
5157 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
5158 amdgpu_dm_connector->pixel_clock_mhz =
e7b07cee
HW		 5159 range->pixel_clock_mhz * 10;
5160 break;
5161 }
5162
c84dec2f
HW		 5163 if (amdgpu_dm_connector->max_vfreq -
5164 amdgpu_dm_connector->min_vfreq > 10) {
5165 amdgpu_dm_connector->caps.supported = true;
5166 amdgpu_dm_connector->caps.min_refresh_in_micro_hz =
5167 amdgpu_dm_connector->min_vfreq * 1000000;
5168 amdgpu_dm_connector->caps.max_refresh_in_micro_hz =
5169 amdgpu_dm_connector->max_vfreq * 1000000;
8218d7f1 5170 dm_con_state->freesync_capable = true;
e7b07cee
HW		 5171 }
5172 }
5173
5174 /*
5175 * TODO figure out how to notify user-mode or DRM of freesync caps
5176 * once we figure out how to deal with freesync in an upstreamable
5177 * fashion
5178 */
5179
5180}
5181
3ee6b26b 5182void amdgpu_dm_remove_sink_from_freesync_module(struct drm_connector *connector)
e7b07cee
HW		 5183{
5184 /*
5185 * TODO fill in once we figure out how to deal with freesync in
5186 * an upstreamable fashion
5187 */
5188}
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