[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / display / amdgpu_dm / amdgpu_dm.h

/*
 * Copyright 2015 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */

#ifndef __AMDGPU_DM_H__
#define __AMDGPU_DM_H__

#include <drm/drmP.h>
#include <drm/drm_atomic.h>
#include "dc.h"

/*
 * This file contains the definition for amdgpu_display_manager
 * and its API for amdgpu driver's use.
 * This component provides all the display related functionality
 * and this is the only component that calls DAL API.
 * The API contained here intended for amdgpu driver use.
 * The API that is called directly from KMS framework is located
 * in amdgpu_dm_kms.h file
 */

#define AMDGPU_DM_MAX_DISPLAY_INDEX 31
/*
#include "include/amdgpu_dal_power_if.h"
#include "amdgpu_dm_irq.h"
*/

#include "irq_types.h"
#include "signal_types.h"

/* Forward declarations */
struct amdgpu_device;
struct drm_device;
struct amdgpu_dm_irq_handler_data;

struct amdgpu_dm_prev_state {
	struct drm_framebuffer *fb;
	int32_t x;
	int32_t y;
	struct drm_display_mode mode;
};

struct common_irq_params {
	struct amdgpu_device *adev;
	enum dc_irq_source irq_src;
};

struct irq_list_head {
	struct list_head head;
	/* In case this interrupt needs post-processing, 'work' will be queued*/
	struct work_struct work;
};

#ifdef ENABLE_FBC
struct dm_comressor_info {
	void *cpu_addr;
	struct amdgpu_bo *bo_ptr;
	uint64_t gpu_addr;
};
#endif


struct amdgpu_display_manager {
	struct dal *dal;
	struct dc *dc;
	struct cgs_device *cgs_device;
	/* lock to be used when DAL is called from SYNC IRQ context */
	spinlock_t dal_lock;

	struct amdgpu_device *adev;	/*AMD base driver*/
	struct drm_device *ddev;	/*DRM base driver*/
	u16 display_indexes_num;

	struct amdgpu_dm_prev_state prev_state;

	/*
	 * 'irq_source_handler_table' holds a list of handlers
	 * per (DAL) IRQ source.
	 *
	 * Each IRQ source may need to be handled at different contexts.
	 * By 'context' we mean, for example:
	 * - The ISR context, which is the direct interrupt handler.
	 * - The 'deferred' context - this is the post-processing of the
	 *	interrupt, but at a lower priority.
	 *
	 * Note that handlers are called in the same order as they were
	 * registered (FIFO).
	 */
	struct irq_list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER];
	struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER];

	struct common_irq_params
	pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1];

	struct common_irq_params
	vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1];

	/* this spin lock synchronizes access to 'irq_handler_list_table' */
	spinlock_t irq_handler_list_table_lock;

	/* Timer-related data. */
	struct list_head timer_handler_list;
	struct workqueue_struct *timer_workqueue;

	/* Use dal_mutex for any activity which is NOT syncronized by
	 * DRM mode setting locks.
	 * For example: amdgpu_dm_hpd_low_irq() calls into DAL *without*
	 * DRM mode setting locks being acquired. This is where dal_mutex
	 * is acquired before calling into DAL. */
	struct mutex dal_mutex;

	struct backlight_device *backlight_dev;

	const struct dc_link *backlight_link;

	struct work_struct mst_hotplug_work;

	struct mod_freesync *freesync_module;

	/**
	 * Caches device atomic state for suspend/resume
	 */
	struct drm_atomic_state *cached_state;
#ifdef ENABLE_FBC
	struct dm_comressor_info compressor;
#endif
};

struct amdgpu_dm_connector {

	struct drm_connector base;
	uint32_t connector_id;

	/* we need to mind the EDID between detect
	   and get modes due to analog/digital/tvencoder */
	struct edid *edid;

	/* shared with amdgpu */
	struct amdgpu_hpd hpd;

	/* number of modes generated from EDID at 'dc_sink' */
	int num_modes;

	/* The 'old' sink - before an HPD.
	 * The 'current' sink is in dc_link->sink. */
	struct dc_sink *dc_sink;
	struct dc_link *dc_link;
	struct dc_sink *dc_em_sink;

	/* DM only */
	struct drm_dp_mst_topology_mgr mst_mgr;
	struct amdgpu_dm_dp_aux dm_dp_aux;
	struct drm_dp_mst_port *port;
	struct amdgpu_dm_connector *mst_port;
	struct amdgpu_encoder *mst_encoder;

	/* TODO see if we can merge with ddc_bus or make a dm_connector */
	struct amdgpu_i2c_adapter *i2c;

	/* Monitor range limits */
	int min_vfreq ;
	int max_vfreq ;
	int pixel_clock_mhz;

	/*freesync caps*/
	struct mod_freesync_caps caps;

	struct mutex hpd_lock;

	bool fake_enable;
};

#define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base)

/* basic init/fini API */
int amdgpu_dm_init(struct amdgpu_device *adev);

void amdgpu_dm_fini(struct amdgpu_device *adev);

void amdgpu_dm_destroy(void);

/* initializes drm_device display related structures, based on the information
 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
 * drm_encoder, drm_mode_config
 *
 * Returns 0 on success
 */
int amdgpu_dm_initialize_drm_device(
	struct amdgpu_device *adev);

/* removes and deallocates the drm structures, created by the above function */
void amdgpu_dm_destroy_drm_device(
	struct amdgpu_display_manager *dm);

/* Locking/Mutex */
bool amdgpu_dm_acquire_dal_lock(struct amdgpu_display_manager *dm);

bool amdgpu_dm_release_dal_lock(struct amdgpu_display_manager *dm);

/* Register "Backlight device" accessible by user-mode. */
void amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm);

extern const struct amdgpu_ip_block_version dm_ip_block;

void amdgpu_dm_update_connector_after_detect(
	struct amdgpu_dm_connector *aconnector);

struct amdgpu_dm_connector *amdgpu_dm_find_first_crct_matching_connector(
	struct drm_atomic_state *state,
	struct drm_crtc *crtc,
	bool from_state_var);


struct amdgpu_framebuffer;
struct amdgpu_display_manager;
struct dc_validation_set;
struct dc_plane_state;
/* TODO rename to dc_stream_state */
struct  dc_stream;

struct dm_plane_state {
	struct drm_plane_state base;
	struct dc_plane_state *dc_state;
};

struct dm_crtc_state {
	struct drm_crtc_state base;
	struct dc_stream_state *stream;
};

#define to_dm_crtc_state(x)    container_of(x, struct dm_crtc_state, base)

struct dm_atomic_state {
	struct drm_atomic_state base;

	struct dc_state *context;
};

#define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base)


/*TODO Jodan Hersen use the one in amdgpu_dm*/
int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
			struct amdgpu_plane *aplane,
			unsigned long possible_crtcs);
int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
			struct drm_plane *plane,
			uint32_t link_index);
int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
			struct amdgpu_dm_connector *amdgpu_dm_connector,
			uint32_t link_index,
			struct amdgpu_encoder *amdgpu_encoder);
int amdgpu_dm_encoder_init(
	struct drm_device *dev,
	struct amdgpu_encoder *aencoder,
	uint32_t link_index);

void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc);
void amdgpu_dm_connector_destroy(struct drm_connector *connector);
void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder);

int amdgpu_dm_connector_get_modes(struct drm_connector *connector);

int amdgpu_dm_atomic_commit(
		struct drm_device *dev,
		struct drm_atomic_state *state,
		bool nonblock);

void amdgpu_dm_atomic_commit_tail(
	struct drm_atomic_state *state);

int amdgpu_dm_atomic_check(struct drm_device *dev,
				struct drm_atomic_state *state);

void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector);
struct drm_connector_state *amdgpu_dm_connector_atomic_duplicate_state(
	struct drm_connector *connector);
int amdgpu_dm_connector_atomic_set_property(
	struct drm_connector *connector,
	struct drm_connector_state *state,
	struct drm_property *property,
	uint64_t val);

int amdgpu_dm_connector_atomic_get_property(
	struct drm_connector *connector,
	const struct drm_connector_state *state,
	struct drm_property *property,
	uint64_t *val);

int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev);

void amdgpu_dm_connector_init_helper(
	struct amdgpu_display_manager *dm,
	struct amdgpu_dm_connector *aconnector,
	int connector_type,
	struct dc_link *link,
	int link_index);

int amdgpu_dm_connector_mode_valid(
	struct drm_connector *connector,
	struct drm_display_mode *mode);

void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector *connector);

void amdgpu_dm_add_sink_to_freesync_module(
		struct drm_connector *connector,
		struct edid *edid);

void amdgpu_dm_remove_sink_from_freesync_module(
		struct drm_connector *connector);

extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs;

#endif /* __AMDGPU_DM_H__ */
Commit	Line	Data
4562236b HW	1	/*
	2	* Copyright 2015 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: AMD
	23	*
	24	*/
	25
	26	#ifndef __AMDGPU_DM_H__
	27	#define __AMDGPU_DM_H__
	28
e7b07cee HW	29	#include <drm/drmP.h>
	30	#include <drm/drm_atomic.h>
	31	#include "dc.h"
4562236b HW	32
	33	/*
	34	* This file contains the definition for amdgpu_display_manager
	35	* and its API for amdgpu driver's use.
	36	* This component provides all the display related functionality
	37	* and this is the only component that calls DAL API.
	38	* The API contained here intended for amdgpu driver use.
	39	* The API that is called directly from KMS framework is located
	40	* in amdgpu_dm_kms.h file
	41	*/
	42
	43	#define AMDGPU_DM_MAX_DISPLAY_INDEX 31
	44	/*
	45	#include "include/amdgpu_dal_power_if.h"
	46	#include "amdgpu_dm_irq.h"
	47	*/
	48
	49	#include "irq_types.h"
	50	#include "signal_types.h"
	51
	52	/* Forward declarations */
	53	struct amdgpu_device;
	54	struct drm_device;
	55	struct amdgpu_dm_irq_handler_data;
	56
	57	struct amdgpu_dm_prev_state {
	58	struct drm_framebuffer *fb;
	59	int32_t x;
	60	int32_t y;
	61	struct drm_display_mode mode;
	62	};
	63
	64	struct common_irq_params {
	65	struct amdgpu_device *adev;
	66	enum dc_irq_source irq_src;
	67	};
	68
	69	struct irq_list_head {
	70	struct list_head head;
	71	/* In case this interrupt needs post-processing, 'work' will be queued*/
	72	struct work_struct work;
	73	};
	74
a32e24b4 RL	75	#ifdef ENABLE_FBC
	76	struct dm_comressor_info {
	77	void *cpu_addr;
	78	struct amdgpu_bo *bo_ptr;
	79	uint64_t gpu_addr;
	80	};
	81	#endif
	82
	83
4562236b HW	84	struct amdgpu_display_manager {
	85	struct dal *dal;
	86	struct dc *dc;
	87	struct cgs_device *cgs_device;
	88	/* lock to be used when DAL is called from SYNC IRQ context */
	89	spinlock_t dal_lock;
	90
	91	struct amdgpu_device adev; /AMD base driver*/
	92	struct drm_device ddev; /DRM base driver*/
	93	u16 display_indexes_num;
	94
	95	struct amdgpu_dm_prev_state prev_state;
	96
	97	/*
	98	* 'irq_source_handler_table' holds a list of handlers
	99	* per (DAL) IRQ source.
	100	*
	101	* Each IRQ source may need to be handled at different contexts.
	102	* By 'context' we mean, for example:
	103	* - The ISR context, which is the direct interrupt handler.
	104	* - The 'deferred' context - this is the post-processing of the
	105	* interrupt, but at a lower priority.
	106	*
	107	* Note that handlers are called in the same order as they were
	108	* registered (FIFO).
	109	*/
	110	struct irq_list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER];
	111	struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER];
	112
	113	struct common_irq_params
	114	pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1];
	115
	116	struct common_irq_params
b57de80a	117	vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1];
4562236b HW	118
	119	/* this spin lock synchronizes access to 'irq_handler_list_table' */
	120	spinlock_t irq_handler_list_table_lock;
	121
	122	/* Timer-related data. */
	123	struct list_head timer_handler_list;
	124	struct workqueue_struct *timer_workqueue;
	125
	126	/* Use dal_mutex for any activity which is NOT syncronized by
	127	* DRM mode setting locks.
	128	* For example: amdgpu_dm_hpd_low_irq() calls into DAL without
	129	* DRM mode setting locks being acquired. This is where dal_mutex
	130	* is acquired before calling into DAL. */
	131	struct mutex dal_mutex;
	132
	133	struct backlight_device *backlight_dev;
	134
	135	const struct dc_link *backlight_link;
	136
	137	struct work_struct mst_hotplug_work;
	138
	139	struct mod_freesync *freesync_module;
a3621485 AG	140
	141	/**
	142	* Caches device atomic state for suspend/resume
	143	*/
	144	struct drm_atomic_state *cached_state;
a32e24b4 RL	145	#ifdef ENABLE_FBC
	146	struct dm_comressor_info compressor;
	147	#endif
4562236b HW	148	};
4562236b HW	149
c84dec2f HW	150	struct amdgpu_dm_connector {
	151
	152	struct drm_connector base;
	153	uint32_t connector_id;
	154
	155	/* we need to mind the EDID between detect
	156	and get modes due to analog/digital/tvencoder */
	157	struct edid *edid;
	158
	159	/* shared with amdgpu */
	160	struct amdgpu_hpd hpd;
	161
	162	/* number of modes generated from EDID at 'dc_sink' */
	163	int num_modes;
	164
	165	/* The 'old' sink - before an HPD.
	166	* The 'current' sink is in dc_link->sink. */
	167	struct dc_sink *dc_sink;
	168	struct dc_link *dc_link;
	169	struct dc_sink *dc_em_sink;
	170
	171	/* DM only */
	172	struct drm_dp_mst_topology_mgr mst_mgr;
	173	struct amdgpu_dm_dp_aux dm_dp_aux;
	174	struct drm_dp_mst_port *port;
	175	struct amdgpu_dm_connector *mst_port;
	176	struct amdgpu_encoder *mst_encoder;
	177
	178	/* TODO see if we can merge with ddc_bus or make a dm_connector */
	179	struct amdgpu_i2c_adapter *i2c;
	180
	181	/* Monitor range limits */
	182	int min_vfreq ;
	183	int max_vfreq ;
	184	int pixel_clock_mhz;
	185
	186	/freesync caps/
	187	struct mod_freesync_caps caps;
	188
	189	struct mutex hpd_lock;
2e0ac3d6 HW	190
2e0ac3d6 HW	191	bool fake_enable;
c84dec2f HW	192	};
	193
	194	#define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base)
	195
4562236b HW	196	/* basic init/fini API */
	197	int amdgpu_dm_init(struct amdgpu_device *adev);
	198
	199	void amdgpu_dm_fini(struct amdgpu_device *adev);
	200
	201	void amdgpu_dm_destroy(void);
	202
	203	/* initializes drm_device display related structures, based on the information
	204	* provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
	205	* drm_encoder, drm_mode_config
	206	*
	207	* Returns 0 on success
	208	*/
	209	int amdgpu_dm_initialize_drm_device(
	210	struct amdgpu_device *adev);
	211
	212	/* removes and deallocates the drm structures, created by the above function */
	213	void amdgpu_dm_destroy_drm_device(
	214	struct amdgpu_display_manager *dm);
	215
	216	/* Locking/Mutex */
	217	bool amdgpu_dm_acquire_dal_lock(struct amdgpu_display_manager *dm);
	218
	219	bool amdgpu_dm_release_dal_lock(struct amdgpu_display_manager *dm);
	220
	221	/* Register "Backlight device" accessible by user-mode. */
	222	void amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm);
	223
	224	extern const struct amdgpu_ip_block_version dm_ip_block;
	225
	226	void amdgpu_dm_update_connector_after_detect(
c84dec2f	227	struct amdgpu_dm_connector *aconnector);
4562236b	228
c84dec2f	229	struct amdgpu_dm_connector *amdgpu_dm_find_first_crct_matching_connector(
4562236b HW	230	struct drm_atomic_state *state,
	231	struct drm_crtc *crtc,
	232	bool from_state_var);
	233
e7b07cee HW	234
	235	struct amdgpu_framebuffer;
	236	struct amdgpu_display_manager;
	237	struct dc_validation_set;
c9614aeb	238	struct dc_plane_state;
e7b07cee HW	239	/* TODO rename to dc_stream_state */
	240	struct dc_stream;
	241
e7b07cee HW	242	struct dm_plane_state {
e7b07cee HW	243	struct drm_plane_state base;
3be5262e	244	struct dc_plane_state *dc_state;
e7b07cee HW	245	};
	246
	247	struct dm_crtc_state {
	248	struct drm_crtc_state base;
0971c40e	249	struct dc_stream_state *stream;
e7b07cee HW	250	};
	251
	252	#define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base)
	253
	254	struct dm_atomic_state {
	255	struct drm_atomic_state base;
	256
608ac7bb	257	struct dc_state *context;
e7b07cee HW	258	};
	259
	260	#define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base)
	261
	262
	263	/TODO Jodan Hersen use the one in amdgpu_dm/
	264	int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
	265	struct amdgpu_plane *aplane,
	266	unsigned long possible_crtcs);
	267	int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
	268	struct drm_plane *plane,
	269	uint32_t link_index);
	270	int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
c84dec2f	271	struct amdgpu_dm_connector *amdgpu_dm_connector,
e7b07cee HW	272	uint32_t link_index,
	273	struct amdgpu_encoder *amdgpu_encoder);
	274	int amdgpu_dm_encoder_init(
	275	struct drm_device *dev,
	276	struct amdgpu_encoder *aencoder,
	277	uint32_t link_index);
	278
	279	void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc);
	280	void amdgpu_dm_connector_destroy(struct drm_connector *connector);
	281	void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder);
	282
	283	int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
	284
	285	int amdgpu_dm_atomic_commit(
	286	struct drm_device *dev,
	287	struct drm_atomic_state *state,
	288	bool nonblock);
	289
	290	void amdgpu_dm_atomic_commit_tail(
	291	struct drm_atomic_state *state);
	292
	293	int amdgpu_dm_atomic_check(struct drm_device *dev,
	294	struct drm_atomic_state *state);
	295
	296	void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector);
	297	struct drm_connector_state *amdgpu_dm_connector_atomic_duplicate_state(
	298	struct drm_connector *connector);
	299	int amdgpu_dm_connector_atomic_set_property(
	300	struct drm_connector *connector,
	301	struct drm_connector_state *state,
	302	struct drm_property *property,
	303	uint64_t val);
	304
	305	int amdgpu_dm_connector_atomic_get_property(
	306	struct drm_connector *connector,
	307	const struct drm_connector_state *state,
	308	struct drm_property *property,
	309	uint64_t *val);
	310
	311	int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev);
	312
	313	void amdgpu_dm_connector_init_helper(
	314	struct amdgpu_display_manager *dm,
c84dec2f	315	struct amdgpu_dm_connector *aconnector,
e7b07cee HW	316	int connector_type,
	317	struct dc_link *link,
	318	int link_index);
	319
	320	int amdgpu_dm_connector_mode_valid(
	321	struct drm_connector *connector,
	322	struct drm_display_mode *mode);
	323
	324	void dm_restore_drm_connector_state(struct drm_device dev, struct drm_connector connector);
	325
	326	void amdgpu_dm_add_sink_to_freesync_module(
	327	struct drm_connector *connector,
	328	struct edid *edid);
	329
	330	void amdgpu_dm_remove_sink_from_freesync_module(
	331	struct drm_connector *connector);
	332
	333	extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs;
	334
4562236b	335	#endif /* __AMDGPU_DM_H__ */