[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / display / amdgpu_dm / amdgpu_dm.h

/*
 * Copyright 2015 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */

#ifndef __AMDGPU_DM_H__
#define __AMDGPU_DM_H__

#include <drm/drmP.h>
#include <drm/drm_atomic.h>
#include "dc.h"

/*
 * This file contains the definition for amdgpu_display_manager
 * and its API for amdgpu driver's use.
 * This component provides all the display related functionality
 * and this is the only component that calls DAL API.
 * The API contained here intended for amdgpu driver use.
 * The API that is called directly from KMS framework is located
 * in amdgpu_dm_kms.h file
 */

#define AMDGPU_DM_MAX_DISPLAY_INDEX 31
/*
#include "include/amdgpu_dal_power_if.h"
#include "amdgpu_dm_irq.h"
*/

#include "irq_types.h"
#include "signal_types.h"

/* Forward declarations */
struct amdgpu_device;
struct drm_device;
struct amdgpu_dm_irq_handler_data;

struct amdgpu_dm_prev_state {
	struct drm_framebuffer *fb;
	int32_t x;
	int32_t y;
	struct drm_display_mode mode;
};

struct common_irq_params {
	struct amdgpu_device *adev;
	enum dc_irq_source irq_src;
};

struct irq_list_head {
	struct list_head head;
	/* In case this interrupt needs post-processing, 'work' will be queued*/
	struct work_struct work;
};

#ifdef ENABLE_FBC
struct dm_comressor_info {
	void *cpu_addr;
	struct amdgpu_bo *bo_ptr;
	uint64_t gpu_addr;
};
#endif


struct amdgpu_display_manager {
	struct dal *dal;
	struct dc *dc;
	struct cgs_device *cgs_device;
	/* lock to be used when DAL is called from SYNC IRQ context */
	spinlock_t dal_lock;

	struct amdgpu_device *adev;	/*AMD base driver*/
	struct drm_device *ddev;	/*DRM base driver*/
	u16 display_indexes_num;

	struct amdgpu_dm_prev_state prev_state;

	/*
	 * 'irq_source_handler_table' holds a list of handlers
	 * per (DAL) IRQ source.
	 *
	 * Each IRQ source may need to be handled at different contexts.
	 * By 'context' we mean, for example:
	 * - The ISR context, which is the direct interrupt handler.
	 * - The 'deferred' context - this is the post-processing of the
	 *	interrupt, but at a lower priority.
	 *
	 * Note that handlers are called in the same order as they were
	 * registered (FIFO).
	 */
	struct irq_list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER];
	struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER];

	struct common_irq_params
	pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1];

	struct common_irq_params
	vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1];

	/* this spin lock synchronizes access to 'irq_handler_list_table' */
	spinlock_t irq_handler_list_table_lock;

	/* Timer-related data. */
	struct list_head timer_handler_list;
	struct workqueue_struct *timer_workqueue;

	/* Use dal_mutex for any activity which is NOT syncronized by
	 * DRM mode setting locks.
	 * For example: amdgpu_dm_hpd_low_irq() calls into DAL *without*
	 * DRM mode setting locks being acquired. This is where dal_mutex
	 * is acquired before calling into DAL. */
	struct mutex dal_mutex;

	struct backlight_device *backlight_dev;

	const struct dc_link *backlight_link;

	struct work_struct mst_hotplug_work;

	struct mod_freesync *freesync_module;

	/**
	 * Caches device atomic state for suspend/resume
	 */
	struct drm_atomic_state *cached_state;
#ifdef ENABLE_FBC
	struct dm_comressor_info compressor;
#endif
};

/* basic init/fini API */
int amdgpu_dm_init(struct amdgpu_device *adev);

void amdgpu_dm_fini(struct amdgpu_device *adev);

void amdgpu_dm_destroy(void);

/* initializes drm_device display related structures, based on the information
 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
 * drm_encoder, drm_mode_config
 *
 * Returns 0 on success
 */
int amdgpu_dm_initialize_drm_device(
	struct amdgpu_device *adev);

/* removes and deallocates the drm structures, created by the above function */
void amdgpu_dm_destroy_drm_device(
	struct amdgpu_display_manager *dm);

/* Locking/Mutex */
bool amdgpu_dm_acquire_dal_lock(struct amdgpu_display_manager *dm);

bool amdgpu_dm_release_dal_lock(struct amdgpu_display_manager *dm);

/* Register "Backlight device" accessible by user-mode. */
void amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm);

extern const struct amdgpu_ip_block_version dm_ip_block;

void amdgpu_dm_update_connector_after_detect(
	struct amdgpu_connector *aconnector);

struct amdgpu_connector *amdgpu_dm_find_first_crct_matching_connector(
	struct drm_atomic_state *state,
	struct drm_crtc *crtc,
	bool from_state_var);


struct amdgpu_framebuffer;
struct amdgpu_display_manager;
struct dc_validation_set;
struct dc_plane_state;
/* TODO rename to dc_stream_state */
struct  dc_stream;


struct dm_plane_state {
	struct drm_plane_state base;
	struct dc_plane_state *dc_state;
};

struct dm_crtc_state {
	struct drm_crtc_state base;
	struct dc_stream_state *stream;
};

#define to_dm_crtc_state(x)    container_of(x, struct dm_crtc_state, base)

struct dm_atomic_state {
	struct drm_atomic_state base;

	struct validate_context *context;
};

#define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base)


/*TODO Jodan Hersen use the one in amdgpu_dm*/
int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
			struct amdgpu_plane *aplane,
			unsigned long possible_crtcs);
int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
			struct drm_plane *plane,
			uint32_t link_index);
int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
			struct amdgpu_connector *amdgpu_connector,
			uint32_t link_index,
			struct amdgpu_encoder *amdgpu_encoder);
int amdgpu_dm_encoder_init(
	struct drm_device *dev,
	struct amdgpu_encoder *aencoder,
	uint32_t link_index);

void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc);
void amdgpu_dm_connector_destroy(struct drm_connector *connector);
void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder);

int amdgpu_dm_connector_get_modes(struct drm_connector *connector);

int amdgpu_dm_atomic_commit(
		struct drm_device *dev,
		struct drm_atomic_state *state,
		bool nonblock);

void amdgpu_dm_atomic_commit_tail(
	struct drm_atomic_state *state);

int amdgpu_dm_atomic_check(struct drm_device *dev,
				struct drm_atomic_state *state);

void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector);
struct drm_connector_state *amdgpu_dm_connector_atomic_duplicate_state(
	struct drm_connector *connector);
int amdgpu_dm_connector_atomic_set_property(
	struct drm_connector *connector,
	struct drm_connector_state *state,
	struct drm_property *property,
	uint64_t val);

int amdgpu_dm_connector_atomic_get_property(
	struct drm_connector *connector,
	const struct drm_connector_state *state,
	struct drm_property *property,
	uint64_t *val);

int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev);

void amdgpu_dm_connector_init_helper(
	struct amdgpu_display_manager *dm,
	struct amdgpu_connector *aconnector,
	int connector_type,
	struct dc_link *link,
	int link_index);

int amdgpu_dm_connector_mode_valid(
	struct drm_connector *connector,
	struct drm_display_mode *mode);

void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector *connector);

void amdgpu_dm_add_sink_to_freesync_module(
		struct drm_connector *connector,
		struct edid *edid);

void amdgpu_dm_remove_sink_from_freesync_module(
		struct drm_connector *connector);

extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs;

#endif /* __AMDGPU_DM_H__ */
Commit	Line	Data
4562236b HW	1	/*
	2	* Copyright 2015 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: AMD
	23	*
	24	*/
	25
	26	#ifndef __AMDGPU_DM_H__
	27	#define __AMDGPU_DM_H__
	28
e7b07cee HW	29	#include <drm/drmP.h>
	30	#include <drm/drm_atomic.h>
	31	#include "dc.h"
4562236b HW	32
	33	/*
	34	* This file contains the definition for amdgpu_display_manager
	35	* and its API for amdgpu driver's use.
	36	* This component provides all the display related functionality
	37	* and this is the only component that calls DAL API.
	38	* The API contained here intended for amdgpu driver use.
	39	* The API that is called directly from KMS framework is located
	40	* in amdgpu_dm_kms.h file
	41	*/
	42
	43	#define AMDGPU_DM_MAX_DISPLAY_INDEX 31
	44	/*
	45	#include "include/amdgpu_dal_power_if.h"
	46	#include "amdgpu_dm_irq.h"
	47	*/
	48
	49	#include "irq_types.h"
	50	#include "signal_types.h"
	51
	52	/* Forward declarations */
	53	struct amdgpu_device;
	54	struct drm_device;
	55	struct amdgpu_dm_irq_handler_data;
	56
	57	struct amdgpu_dm_prev_state {
	58	struct drm_framebuffer *fb;
	59	int32_t x;
	60	int32_t y;
	61	struct drm_display_mode mode;
	62	};
	63
	64	struct common_irq_params {
	65	struct amdgpu_device *adev;
	66	enum dc_irq_source irq_src;
	67	};
	68
	69	struct irq_list_head {
	70	struct list_head head;
	71	/* In case this interrupt needs post-processing, 'work' will be queued*/
	72	struct work_struct work;
	73	};
	74
a32e24b4 RL	75	#ifdef ENABLE_FBC
	76	struct dm_comressor_info {
	77	void *cpu_addr;
	78	struct amdgpu_bo *bo_ptr;
	79	uint64_t gpu_addr;
	80	};
	81	#endif
	82
	83
4562236b HW	84	struct amdgpu_display_manager {
	85	struct dal *dal;
	86	struct dc *dc;
	87	struct cgs_device *cgs_device;
	88	/* lock to be used when DAL is called from SYNC IRQ context */
	89	spinlock_t dal_lock;
	90
	91	struct amdgpu_device adev; /AMD base driver*/
	92	struct drm_device ddev; /DRM base driver*/
	93	u16 display_indexes_num;
	94
	95	struct amdgpu_dm_prev_state prev_state;
	96
	97	/*
	98	* 'irq_source_handler_table' holds a list of handlers
	99	* per (DAL) IRQ source.
	100	*
	101	* Each IRQ source may need to be handled at different contexts.
	102	* By 'context' we mean, for example:
	103	* - The ISR context, which is the direct interrupt handler.
	104	* - The 'deferred' context - this is the post-processing of the
	105	* interrupt, but at a lower priority.
	106	*
	107	* Note that handlers are called in the same order as they were
	108	* registered (FIFO).
	109	*/
	110	struct irq_list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER];
	111	struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER];
	112
	113	struct common_irq_params
	114	pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1];
	115
	116	struct common_irq_params
b57de80a	117	vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1];
4562236b HW	118
	119	/* this spin lock synchronizes access to 'irq_handler_list_table' */
	120	spinlock_t irq_handler_list_table_lock;
	121
	122	/* Timer-related data. */
	123	struct list_head timer_handler_list;
	124	struct workqueue_struct *timer_workqueue;
	125
	126	/* Use dal_mutex for any activity which is NOT syncronized by
	127	* DRM mode setting locks.
	128	* For example: amdgpu_dm_hpd_low_irq() calls into DAL without
	129	* DRM mode setting locks being acquired. This is where dal_mutex
	130	* is acquired before calling into DAL. */
	131	struct mutex dal_mutex;
	132
	133	struct backlight_device *backlight_dev;
	134
	135	const struct dc_link *backlight_link;
	136
	137	struct work_struct mst_hotplug_work;
	138
	139	struct mod_freesync *freesync_module;
a3621485 AG	140
	141	/**
	142	* Caches device atomic state for suspend/resume
	143	*/
	144	struct drm_atomic_state *cached_state;
a32e24b4 RL	145	#ifdef ENABLE_FBC
	146	struct dm_comressor_info compressor;
	147	#endif
4562236b HW	148	};
	149
	150	/* basic init/fini API */
	151	int amdgpu_dm_init(struct amdgpu_device *adev);
	152
	153	void amdgpu_dm_fini(struct amdgpu_device *adev);
	154
	155	void amdgpu_dm_destroy(void);
	156
	157	/* initializes drm_device display related structures, based on the information
	158	* provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
	159	* drm_encoder, drm_mode_config
	160	*
	161	* Returns 0 on success
	162	*/
	163	int amdgpu_dm_initialize_drm_device(
	164	struct amdgpu_device *adev);
	165
	166	/* removes and deallocates the drm structures, created by the above function */
	167	void amdgpu_dm_destroy_drm_device(
	168	struct amdgpu_display_manager *dm);
	169
	170	/* Locking/Mutex */
	171	bool amdgpu_dm_acquire_dal_lock(struct amdgpu_display_manager *dm);
	172
	173	bool amdgpu_dm_release_dal_lock(struct amdgpu_display_manager *dm);
	174
	175	/* Register "Backlight device" accessible by user-mode. */
	176	void amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm);
	177
	178	extern const struct amdgpu_ip_block_version dm_ip_block;
	179
	180	void amdgpu_dm_update_connector_after_detect(
	181	struct amdgpu_connector *aconnector);
	182
	183	struct amdgpu_connector *amdgpu_dm_find_first_crct_matching_connector(
	184	struct drm_atomic_state *state,
	185	struct drm_crtc *crtc,
	186	bool from_state_var);
	187
e7b07cee HW	188
	189	struct amdgpu_framebuffer;
	190	struct amdgpu_display_manager;
	191	struct dc_validation_set;
c9614aeb	192	struct dc_plane_state;
e7b07cee HW	193	/* TODO rename to dc_stream_state */
	194	struct dc_stream;
	195
	196
	197	struct dm_plane_state {
	198	struct drm_plane_state base;
3be5262e	199	struct dc_plane_state *dc_state;
e7b07cee HW	200	};
	201
	202	struct dm_crtc_state {
	203	struct drm_crtc_state base;
0971c40e	204	struct dc_stream_state *stream;
e7b07cee HW	205	};
	206
	207	#define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base)
	208
	209	struct dm_atomic_state {
	210	struct drm_atomic_state base;
	211
	212	struct validate_context *context;
	213	};
	214
	215	#define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base)
	216
	217
	218	/TODO Jodan Hersen use the one in amdgpu_dm/
	219	int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
	220	struct amdgpu_plane *aplane,
	221	unsigned long possible_crtcs);
	222	int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
	223	struct drm_plane *plane,
	224	uint32_t link_index);
	225	int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
	226	struct amdgpu_connector *amdgpu_connector,
	227	uint32_t link_index,
	228	struct amdgpu_encoder *amdgpu_encoder);
	229	int amdgpu_dm_encoder_init(
	230	struct drm_device *dev,
	231	struct amdgpu_encoder *aencoder,
	232	uint32_t link_index);
	233
	234	void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc);
	235	void amdgpu_dm_connector_destroy(struct drm_connector *connector);
	236	void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder);
	237
	238	int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
	239
	240	int amdgpu_dm_atomic_commit(
	241	struct drm_device *dev,
	242	struct drm_atomic_state *state,
	243	bool nonblock);
	244
	245	void amdgpu_dm_atomic_commit_tail(
	246	struct drm_atomic_state *state);
	247
	248	int amdgpu_dm_atomic_check(struct drm_device *dev,
	249	struct drm_atomic_state *state);
	250
	251	void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector);
	252	struct drm_connector_state *amdgpu_dm_connector_atomic_duplicate_state(
	253	struct drm_connector *connector);
	254	int amdgpu_dm_connector_atomic_set_property(
	255	struct drm_connector *connector,
	256	struct drm_connector_state *state,
	257	struct drm_property *property,
	258	uint64_t val);
	259
	260	int amdgpu_dm_connector_atomic_get_property(
	261	struct drm_connector *connector,
	262	const struct drm_connector_state *state,
	263	struct drm_property *property,
	264	uint64_t *val);
	265
	266	int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev);
	267
	268	void amdgpu_dm_connector_init_helper(
269	struct amdgpu_display_manager *dm,
270	struct amdgpu_connector *aconnector,
271	int connector_type,
272	struct dc_link *link,
273	int link_index);
274
275	int amdgpu_dm_connector_mode_valid(
276	struct drm_connector *connector,
277	struct drm_display_mode *mode);
278
279	void dm_restore_drm_connector_state(struct drm_device dev, struct drm_connector connector);
280
281	void amdgpu_dm_add_sink_to_freesync_module(
282	struct drm_connector *connector,
283	struct edid *edid);
284
285	void amdgpu_dm_remove_sink_from_freesync_module(
286	struct drm_connector *connector);
287
288	extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs;
289
4562236b	290	#endif /* __AMDGPU_DM_H__ */