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drm/amd/display: Rename firmware_info to dc_firmware_info
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / display / amdgpu_dm / amdgpu_dm_types.c
CommitLineData
4562236b
HW		 1/*
2 * Copyright 2012-13 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include <linux/types.h>
27#include <linux/version.h>
28
29#include <drm/drmP.h>
30#include <drm/drm_atomic_helper.h>
31#include <drm/drm_fb_helper.h>
32#include <drm/drm_atomic.h>
33#include <drm/drm_edid.h>
34
209a885b 35
4562236b
HW		 36#include "amdgpu.h"
37#include "amdgpu_pm.h"
209a885b 38#include "dm_helpers.h"
4562236b
HW		 39#include "dm_services_types.h"
40
41// We need to #undef FRAME_SIZE and DEPRECATED because they conflict
42// with ptrace-abi.h's #define's of them.
43#undef FRAME_SIZE
44#undef DEPRECATED
45
46#include "dc.h"
47
48#include "amdgpu_dm_types.h"
49#include "amdgpu_dm_mst_types.h"
50
51#include "modules/inc/mod_freesync.h"
52
46df790c
AG		 53#include "i2caux_interface.h"
54
4562236b
HW		 55struct dm_connector_state {
56 struct drm_connector_state base;
57
58 enum amdgpu_rmx_type scaling;
59 uint8_t underscan_vborder;
60 uint8_t underscan_hborder;
61 bool underscan_enable;
62};
63
64#define to_dm_connector_state(x)\
65 container_of((x), struct dm_connector_state, base)
66
4017fcdf
AG		 67static bool modeset_required(struct drm_crtc_state *crtc_state)
68{
69 if (!drm_atomic_crtc_needs_modeset(crtc_state))
70 return false;
71
72 if (!crtc_state->enable)
73 return false;
74
75 return crtc_state->active;
76}
77
78static bool modereset_required(struct drm_crtc_state *crtc_state)
79{
80 if (!drm_atomic_crtc_needs_modeset(crtc_state))
81 return false;
82
83 return !crtc_state->enable || !crtc_state->active;
84}
4562236b
HW		 85
86void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
87{
88 drm_encoder_cleanup(encoder);
89 kfree(encoder);
90}
91
92static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
93 .destroy = amdgpu_dm_encoder_destroy,
94};
95
96static void dm_set_cursor(
97 struct amdgpu_crtc *amdgpu_crtc,
98 uint64_t gpu_addr,
99 uint32_t width,
100 uint32_t height)
101{
102 struct dc_cursor_attributes attributes;
cf388c0d
AN		 103 struct dc_cursor_position position;
104 struct drm_crtc *crtc = &amdgpu_crtc->base;
105 int x, y;
106 int xorigin = 0, yorigin = 0;
da5c47f6 107 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
cf388c0d 108
4562236b
HW		 109 amdgpu_crtc->cursor_width = width;
110 amdgpu_crtc->cursor_height = height;
111
112 attributes.address.high_part = upper_32_bits(gpu_addr);
113 attributes.address.low_part = lower_32_bits(gpu_addr);
114 attributes.width = width;
115 attributes.height = height;
4562236b
HW		 116 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
117 attributes.rotation_angle = 0;
118 attributes.attribute_flags.value = 0;
119
0702a01f
AG		 120 attributes.pitch = attributes.width;
121
cf388c0d
AN		 122 x = amdgpu_crtc->cursor_x;
123 y = amdgpu_crtc->cursor_y;
124
125 /* avivo cursor are offset into the total surface */
126 x += crtc->primary->state->src_x >> 16;
127 y += crtc->primary->state->src_y >> 16;
128
129 if (x < 0) {
130 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
131 x = 0;
132 }
133 if (y < 0) {
134 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
135 y = 0;
136 }
137
138 position.enable = true;
139 position.x = x;
140 position.y = y;
141
cf388c0d
AN		 142 position.x_hotspot = xorigin;
143 position.y_hotspot = yorigin;
144
ab2541b6 145 if (!dc_stream_set_cursor_attributes(
da5c47f6 146 acrtc_state->stream,
4562236b
HW		 147 &attributes)) {
148 DRM_ERROR("DC failed to set cursor attributes\n");
149 }
cf388c0d 150
ab2541b6 151 if (!dc_stream_set_cursor_position(
da5c47f6 152 acrtc_state->stream,
cf388c0d
AN		 153 &position)) {
154 DRM_ERROR("DC failed to set cursor position\n");
155 }
4562236b
HW		 156}
157
4562236b
HW		 158static int dm_crtc_cursor_set(
159 struct drm_crtc *crtc,
2ea5e9a8 160 uint64_t address,
4562236b
HW		 161 uint32_t width,
162 uint32_t height)
163{
4562236b 164 struct dc_cursor_position position;
da5c47f6 165 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
4562236b
HW		 166
167 int ret;
168
169 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
4562236b 170 ret = EINVAL;
4562236b
HW		 171
172 DRM_DEBUG_KMS(
2ea5e9a8 173 "%s: crtc_id=%d with size %d to %d \n",
4562236b
HW		 174 __func__,
175 amdgpu_crtc->crtc_id,
4562236b 176 width,
2ea5e9a8 177 height);
4562236b 178
2ea5e9a8 179 if (!address) {
4562236b
HW		 180 /* turn off cursor */
181 position.enable = false;
182 position.x = 0;
183 position.y = 0;
4562236b 184
da5c47f6 185 if (acrtc_state->stream) {
4562236b 186 /*set cursor visible false*/
ab2541b6 187 dc_stream_set_cursor_position(
da5c47f6 188 acrtc_state->stream,
4562236b
HW		 189 &position);
190 }
4562236b
HW		 191 goto release;
192
193 }
194
195 if ((width > amdgpu_crtc->max_cursor_width) ||
196 (height > amdgpu_crtc->max_cursor_height)) {
197 DRM_ERROR(
198 "%s: bad cursor width or height %d x %d\n",
199 __func__,
200 width,
201 height);
202 goto release;
203 }
4562236b
HW		 204
205 /*program new cursor bo to hardware*/
2ea5e9a8 206 dm_set_cursor(amdgpu_crtc, address, width, height);
4562236b
HW		 207
208release:
209 return ret;
210
211}
212
213static int dm_crtc_cursor_move(struct drm_crtc *crtc,
214 int x, int y)
215{
216 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
217 int xorigin = 0, yorigin = 0;
218 struct dc_cursor_position position;
da5c47f6 219 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
4562236b 220
cf388c0d
AN		 221 amdgpu_crtc->cursor_x = x;
222 amdgpu_crtc->cursor_y = y;
223
4562236b
HW		 224 /* avivo cursor are offset into the total surface */
225 x += crtc->primary->state->src_x >> 16;
226 y += crtc->primary->state->src_y >> 16;
227
228 /*
229 * TODO: for cursor debugging unguard the following
230 */
231#if 0
232 DRM_DEBUG_KMS(
233 "%s: x %d y %d c->x %d c->y %d\n",
234 __func__,
235 x,
236 y,
237 crtc->x,
238 crtc->y);
239#endif
240
241 if (x < 0) {
242 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
243 x = 0;
244 }
245 if (y < 0) {
246 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
247 y = 0;
248 }
249
250 position.enable = true;
251 position.x = x;
252 position.y = y;
253
4562236b
HW		 254 position.x_hotspot = xorigin;
255 position.y_hotspot = yorigin;
256
da5c47f6 257 if (acrtc_state->stream) {
ab2541b6 258 if (!dc_stream_set_cursor_position(
da5c47f6 259 acrtc_state->stream,
4562236b
HW		 260 &position)) {
261 DRM_ERROR("DC failed to set cursor position\n");
262 return -EINVAL;
263 }
264 }
265
266 return 0;
267}
268
4562236b
HW		 269static bool fill_rects_from_plane_state(
270 const struct drm_plane_state *state,
271 struct dc_surface *surface)
272{
273 surface->src_rect.x = state->src_x >> 16;
274 surface->src_rect.y = state->src_y >> 16;
275 /*we ignore for now mantissa and do not to deal with floating pixels :(*/
276 surface->src_rect.width = state->src_w >> 16;
277
278 if (surface->src_rect.width == 0)
279 return false;
280
281 surface->src_rect.height = state->src_h >> 16;
282 if (surface->src_rect.height == 0)
283 return false;
284
285 surface->dst_rect.x = state->crtc_x;
286 surface->dst_rect.y = state->crtc_y;
287
288 if (state->crtc_w == 0)
289 return false;
290
291 surface->dst_rect.width = state->crtc_w;
292
293 if (state->crtc_h == 0)
294 return false;
295
296 surface->dst_rect.height = state->crtc_h;
297
298 surface->clip_rect = surface->dst_rect;
299
300 switch (state->rotation & DRM_MODE_ROTATE_MASK) {
301 case DRM_MODE_ROTATE_0:
302 surface->rotation = ROTATION_ANGLE_0;
303 break;
304 case DRM_MODE_ROTATE_90:
305 surface->rotation = ROTATION_ANGLE_90;
306 break;
307 case DRM_MODE_ROTATE_180:
308 surface->rotation = ROTATION_ANGLE_180;
309 break;
310 case DRM_MODE_ROTATE_270:
311 surface->rotation = ROTATION_ANGLE_270;
312 break;
313 default:
314 surface->rotation = ROTATION_ANGLE_0;
315 break;
316 }
317
318 return true;
319}
d7e3316c 320static int get_fb_info(
4562236b
HW		 321 const struct amdgpu_framebuffer *amdgpu_fb,
322 uint64_t *tiling_flags,
323 uint64_t *fb_location)
324{
325 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
326 int r = amdgpu_bo_reserve(rbo, false);
d7e3316c 327 if (unlikely(r)) {
4562236b 328 DRM_ERROR("Unable to reserve buffer\n");
d7e3316c 329 return r;
4562236b
HW		 330 }
331
332 if (fb_location)
333 *fb_location = amdgpu_bo_gpu_offset(rbo);
334
335 if (tiling_flags)
336 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
337
338 amdgpu_bo_unreserve(rbo);
339
d7e3316c 340 return r;
4562236b 341}
d7e3316c
AG		 342
343static int fill_plane_attributes_from_fb(
6a1f8cab 344 struct amdgpu_device *adev,
4562236b
HW		 345 struct dc_surface *surface,
346 const struct amdgpu_framebuffer *amdgpu_fb, bool addReq)
347{
348 uint64_t tiling_flags;
349 uint64_t fb_location = 0;
f0c16087 350 unsigned int awidth;
4562236b 351 const struct drm_framebuffer *fb = &amdgpu_fb->base;
d7e3316c 352 int ret = 0;
4562236b
HW		 353 struct drm_format_name_buf format_name;
354
d7e3316c 355 ret = get_fb_info(
4562236b
HW		 356 amdgpu_fb,
357 &tiling_flags,
358 addReq == true ? &fb_location:NULL);
359
d7e3316c
AG		 360 if (ret)
361 return ret;
4562236b
HW		 362
363 switch (fb->format->format) {
364 case DRM_FORMAT_C8:
365 surface->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
366 break;
367 case DRM_FORMAT_RGB565:
368 surface->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
369 break;
370 case DRM_FORMAT_XRGB8888:
371 case DRM_FORMAT_ARGB8888:
372 surface->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
373 break;
374 case DRM_FORMAT_XRGB2101010:
375 case DRM_FORMAT_ARGB2101010:
376 surface->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
377 break;
378 case DRM_FORMAT_XBGR2101010:
379 case DRM_FORMAT_ABGR2101010:
380 surface->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
381 break;
f0c16087 382 case DRM_FORMAT_NV21:
e6fbd5df
S		 383 surface->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
384 break;
f0c16087 385 case DRM_FORMAT_NV12:
e6fbd5df
S		 386 surface->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
387 break;
4562236b
HW		 388 default:
389 DRM_ERROR("Unsupported screen format %s\n",
390 drm_get_format_name(fb->format->format, &format_name));
d7e3316c 391 return -EINVAL;
4562236b
HW		 392 }
393
e6fbd5df
S		 394 if (surface->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
395 surface->address.type = PLN_ADDR_TYPE_GRAPHICS;
396 surface->address.grph.addr.low_part = lower_32_bits(fb_location);
397 surface->address.grph.addr.high_part = upper_32_bits(fb_location);
398 surface->plane_size.grph.surface_size.x = 0;
399 surface->plane_size.grph.surface_size.y = 0;
400 surface->plane_size.grph.surface_size.width = fb->width;
401 surface->plane_size.grph.surface_size.height = fb->height;
402 surface->plane_size.grph.surface_pitch =
403 fb->pitches[0] / fb->format->cpp[0];
404 /* TODO: unhardcode */
405 surface->color_space = COLOR_SPACE_SRGB;
406
407 } else {
f0c16087 408 awidth = ALIGN(fb->width, 64);
e6fbd5df
S		 409 surface->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
410 surface->address.video_progressive.luma_addr.low_part
411 = lower_32_bits(fb_location);
110ff543
S		 412 surface->address.video_progressive.chroma_addr.low_part
413 = lower_32_bits(fb_location) +
f0c16087 414 (awidth * fb->height);
e6fbd5df
S		 415 surface->plane_size.video.luma_size.x = 0;
416 surface->plane_size.video.luma_size.y = 0;
f0c16087 417 surface->plane_size.video.luma_size.width = awidth;
e6fbd5df
S		 418 surface->plane_size.video.luma_size.height = fb->height;
419 /* TODO: unhardcode */
f0c16087 420 surface->plane_size.video.luma_pitch = awidth;
e6fbd5df
S		 421
422 surface->plane_size.video.chroma_size.x = 0;
423 surface->plane_size.video.chroma_size.y = 0;
f0c16087
S		 424 surface->plane_size.video.chroma_size.width = awidth;
425 surface->plane_size.video.chroma_size.height = fb->height;
426 surface->plane_size.video.chroma_pitch = awidth / 2;
e6fbd5df
S		 427
428 /* TODO: unhardcode */
429 surface->color_space = COLOR_SPACE_YCBCR709;
430 }
431
4562236b
HW		 432 memset(&surface->tiling_info, 0, sizeof(surface->tiling_info));
433
2c8ad2d5 434 /* Fill GFX params */
4562236b
HW		 435 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1)
436 {
437 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
438
439 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
440 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
441 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
442 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
443 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
444
445 /* XXX fix me for VI */
446 surface->tiling_info.gfx8.num_banks = num_banks;
447 surface->tiling_info.gfx8.array_mode =
448 DC_ARRAY_2D_TILED_THIN1;
449 surface->tiling_info.gfx8.tile_split = tile_split;
450 surface->tiling_info.gfx8.bank_width = bankw;
451 surface->tiling_info.gfx8.bank_height = bankh;
452 surface->tiling_info.gfx8.tile_aspect = mtaspect;
453 surface->tiling_info.gfx8.tile_mode =
454 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
455 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
456 == DC_ARRAY_1D_TILED_THIN1) {
457 surface->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
458 }
459
460 surface->tiling_info.gfx8.pipe_config =
461 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
462
ff5ef992
AD		 463 if (adev->asic_type == CHIP_VEGA10 ||
464 adev->asic_type == CHIP_RAVEN) {
2c8ad2d5
AD		 465 /* Fill GFX9 params */
466 surface->tiling_info.gfx9.num_pipes =
467 adev->gfx.config.gb_addr_config_fields.num_pipes;
468 surface->tiling_info.gfx9.num_banks =
469 adev->gfx.config.gb_addr_config_fields.num_banks;
470 surface->tiling_info.gfx9.pipe_interleave =
471 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
472 surface->tiling_info.gfx9.num_shader_engines =
473 adev->gfx.config.gb_addr_config_fields.num_se;
474 surface->tiling_info.gfx9.max_compressed_frags =
475 adev->gfx.config.gb_addr_config_fields.max_compress_frags;
d092bf65
AG		 476 surface->tiling_info.gfx9.num_rb_per_se =
477 adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
2c8ad2d5
AD		 478 surface->tiling_info.gfx9.swizzle =
479 AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
480 surface->tiling_info.gfx9.shaderEnable = 1;
481 }
2c8ad2d5 482
4562236b
HW		 483 surface->visible = true;
484 surface->scaling_quality.h_taps_c = 0;
485 surface->scaling_quality.v_taps_c = 0;
486
4562236b
HW		 487 /* is this needed? is surface zeroed at allocation? */
488 surface->scaling_quality.h_taps = 0;
489 surface->scaling_quality.v_taps = 0;
490 surface->stereo_format = PLANE_STEREO_FORMAT_NONE;
491
d7e3316c
AG		 492 return ret;
493
4562236b
HW		 494}
495
496#define NUM_OF_RAW_GAMMA_RAMP_RGB_256 256
497
d7e3316c
AG		 498static void fill_gamma_from_crtc_state(
499 const struct drm_crtc_state *crtc_state,
4562236b
HW		 500 struct dc_surface *dc_surface)
501{
502 int i;
503 struct dc_gamma *gamma;
d7e3316c 504 struct drm_color_lut *lut = (struct drm_color_lut *) crtc_state->gamma_lut->data;
4562236b
HW		 505
506 gamma = dc_create_gamma();
507
d7e3316c
AG		 508 if (gamma == NULL) {
509 WARN_ON(1);
4562236b 510 return;
d7e3316c 511 }
4562236b
HW		 512
513 for (i = 0; i < NUM_OF_RAW_GAMMA_RAMP_RGB_256; i++) {
d7194cf6
AC		 514 gamma->red[i] = lut[i].red;
515 gamma->green[i] = lut[i].green;
516 gamma->blue[i] = lut[i].blue;
4562236b
HW		 517 }
518
4562236b
HW		 519 dc_surface->gamma_correction = gamma;
520}
521
d7e3316c 522static int fill_plane_attributes(
6a1f8cab 523 struct amdgpu_device *adev,
4562236b 524 struct dc_surface *surface,
d7e3316c
AG		 525 struct drm_plane_state *plane_state,
526 struct drm_crtc_state *crtc_state,
527 bool addrReq)
4562236b
HW		 528{
529 const struct amdgpu_framebuffer *amdgpu_fb =
d7e3316c
AG		 530 to_amdgpu_framebuffer(plane_state->fb);
531 const struct drm_crtc *crtc = plane_state->crtc;
18f39f2d 532 struct dc_transfer_func *input_tf;
d7e3316c
AG		 533 int ret = 0;
534
535 if (!fill_rects_from_plane_state(plane_state, surface))
536 return -EINVAL;
4562236b 537
d7e3316c 538 ret = fill_plane_attributes_from_fb(
6a1f8cab 539 crtc->dev->dev_private,
4562236b
HW		 540 surface,
541 amdgpu_fb,
542 addrReq);
543
d7e3316c
AG		 544 if (ret)
545 return ret;
546
18f39f2d
RL		 547 input_tf = dc_create_transfer_func();
548
549 if (input_tf == NULL)
d7e3316c 550 return -ENOMEM;
18f39f2d
RL		 551
552 input_tf->type = TF_TYPE_PREDEFINED;
553 input_tf->tf = TRANSFER_FUNCTION_SRGB;
554
555 surface->in_transfer_func = input_tf;
556
4562236b 557 /* In case of gamma set, update gamma value */
d7e3316c
AG		 558 if (crtc_state->gamma_lut)
559 fill_gamma_from_crtc_state(crtc_state, surface);
560
561 return ret;
4562236b
HW		 562}
563
564/*****************************************************************************/
565
566struct amdgpu_connector *aconnector_from_drm_crtc_id(
567 const struct drm_crtc *crtc)
568{
569 struct drm_device *dev = crtc->dev;
570 struct drm_connector *connector;
571 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
572 struct amdgpu_connector *aconnector;
573
574 list_for_each_entry(connector,
575 &dev->mode_config.connector_list, head) {
576
577 aconnector = to_amdgpu_connector(connector);
578
579 if (aconnector->base.state->crtc != &acrtc->base)
580 continue;
581
582 /* Found the connector */
583 return aconnector;
584 }
585
586 /* If we get here, not found. */
587 return NULL;
588}
589
590static void update_stream_scaling_settings(
591 const struct drm_display_mode *mode,
592 const struct dm_connector_state *dm_state,
ccaa7389 593 struct dc_stream *stream)
4562236b 594{
4562236b
HW		 595 enum amdgpu_rmx_type rmx_type;
596
ab2541b6 597 struct rect src = { 0 }; /* viewport in composition space*/
4562236b
HW		 598 struct rect dst = { 0 }; /* stream addressable area */
599
f7f3cfee
HW		 600 /* no mode. nothing to be done */
601 if (!mode)
602 return;
603
4562236b
HW		 604 /* Full screen scaling by default */
605 src.width = mode->hdisplay;
606 src.height = mode->vdisplay;
607 dst.width = stream->timing.h_addressable;
608 dst.height = stream->timing.v_addressable;
609
610 rmx_type = dm_state->scaling;
611 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
612 if (src.width * dst.height <
613 src.height * dst.width) {
614 /* height needs less upscaling/more downscaling */
615 dst.width = src.width *
616 dst.height / src.height;
617 } else {
618 /* width needs less upscaling/more downscaling */
619 dst.height = src.height *
620 dst.width / src.width;
621 }
622 } else if (rmx_type == RMX_CENTER) {
623 dst = src;
624 }
625
626 dst.x = (stream->timing.h_addressable - dst.width) / 2;
627 dst.y = (stream->timing.v_addressable - dst.height) / 2;
628
629 if (dm_state->underscan_enable) {
630 dst.x += dm_state->underscan_hborder / 2;
631 dst.y += dm_state->underscan_vborder / 2;
632 dst.width -= dm_state->underscan_hborder;
633 dst.height -= dm_state->underscan_vborder;
634 }
635
ccaa7389
AG		 636 stream->src = src;
637 stream->dst = dst;
4562236b
HW		 638
639 DRM_DEBUG_KMS("Destination Rectangle x:%d y:%d width:%d height:%d\n",
640 dst.x, dst.y, dst.width, dst.height);
641
642}
643
4562236b
HW		 644static enum dc_color_depth convert_color_depth_from_display_info(
645 const struct drm_connector *connector)
646{
647 uint32_t bpc = connector->display_info.bpc;
648
649 /* Limited color depth to 8bit
650 * TODO: Still need to handle deep color*/
651 if (bpc > 8)
652 bpc = 8;
653
654 switch (bpc) {
655 case 0:
656 /* Temporary Work around, DRM don't parse color depth for
657 * EDID revision before 1.4
658 * TODO: Fix edid parsing
659 */
660 return COLOR_DEPTH_888;
661 case 6:
662 return COLOR_DEPTH_666;
663 case 8:
664 return COLOR_DEPTH_888;
665 case 10:
666 return COLOR_DEPTH_101010;
667 case 12:
668 return COLOR_DEPTH_121212;
669 case 14:
670 return COLOR_DEPTH_141414;
671 case 16:
672 return COLOR_DEPTH_161616;
673 default:
674 return COLOR_DEPTH_UNDEFINED;
675 }
676}
677
678static enum dc_aspect_ratio get_aspect_ratio(
679 const struct drm_display_mode *mode_in)
680{
681 int32_t width = mode_in->crtc_hdisplay * 9;
682 int32_t height = mode_in->crtc_vdisplay * 16;
683 if ((width - height) < 10 && (width - height) > -10)
684 return ASPECT_RATIO_16_9;
685 else
686 return ASPECT_RATIO_4_3;
687}
688
689static enum dc_color_space get_output_color_space(
690 const struct dc_crtc_timing *dc_crtc_timing)
691{
692 enum dc_color_space color_space = COLOR_SPACE_SRGB;
693
694 switch (dc_crtc_timing->pixel_encoding) {
695 case PIXEL_ENCODING_YCBCR422:
696 case PIXEL_ENCODING_YCBCR444:
697 case PIXEL_ENCODING_YCBCR420:
698 {
699 /*
700 * 27030khz is the separation point between HDTV and SDTV
701 * according to HDMI spec, we use YCbCr709 and YCbCr601
702 * respectively
703 */
704 if (dc_crtc_timing->pix_clk_khz > 27030) {
705 if (dc_crtc_timing->flags.Y_ONLY)
706 color_space =
707 COLOR_SPACE_YCBCR709_LIMITED;
708 else
709 color_space = COLOR_SPACE_YCBCR709;
710 } else {
711 if (dc_crtc_timing->flags.Y_ONLY)
712 color_space =
713 COLOR_SPACE_YCBCR601_LIMITED;
714 else
715 color_space = COLOR_SPACE_YCBCR601;
716 }
717
718 }
719 break;
720 case PIXEL_ENCODING_RGB:
721 color_space = COLOR_SPACE_SRGB;
722 break;
723
724 default:
725 WARN_ON(1);
726 break;
727 }
728
729 return color_space;
730}
731
732/*****************************************************************************/
733
734static void fill_stream_properties_from_drm_display_mode(
735 struct dc_stream *stream,
736 const struct drm_display_mode *mode_in,
737 const struct drm_connector *connector)
738{
739 struct dc_crtc_timing *timing_out = &stream->timing;
740 memset(timing_out, 0, sizeof(struct dc_crtc_timing));
741
742 timing_out->h_border_left = 0;
743 timing_out->h_border_right = 0;
744 timing_out->v_border_top = 0;
745 timing_out->v_border_bottom = 0;
746 /* TODO: un-hardcode */
747
748 if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
749 && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
750 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
751 else
752 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
753
754 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
755 timing_out->display_color_depth = convert_color_depth_from_display_info(
756 connector);
757 timing_out->scan_type = SCANNING_TYPE_NODATA;
758 timing_out->hdmi_vic = 0;
759 timing_out->vic = drm_match_cea_mode(mode_in);
760
761 timing_out->h_addressable = mode_in->crtc_hdisplay;
762 timing_out->h_total = mode_in->crtc_htotal;
763 timing_out->h_sync_width =
764 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
765 timing_out->h_front_porch =
766 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
767 timing_out->v_total = mode_in->crtc_vtotal;
768 timing_out->v_addressable = mode_in->crtc_vdisplay;
769 timing_out->v_front_porch =
770 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
771 timing_out->v_sync_width =
772 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
773 timing_out->pix_clk_khz = mode_in->crtc_clock;
774 timing_out->aspect_ratio = get_aspect_ratio(mode_in);
775 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
776 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
777 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
778 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
779
780 stream->output_color_space = get_output_color_space(timing_out);
781
d7194cf6
AC		 782 {
783 struct dc_transfer_func *tf = dc_create_transfer_func();
784 tf->type = TF_TYPE_PREDEFINED;
785 tf->tf = TRANSFER_FUNCTION_SRGB;
786 stream->out_transfer_func = tf;
787 }
4562236b
HW		 788}
789
790static void fill_audio_info(
791 struct audio_info *audio_info,
792 const struct drm_connector *drm_connector,
793 const struct dc_sink *dc_sink)
794{
795 int i = 0;
796 int cea_revision = 0;
797 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
798
799 audio_info->manufacture_id = edid_caps->manufacturer_id;
800 audio_info->product_id = edid_caps->product_id;
801
802 cea_revision = drm_connector->display_info.cea_rev;
803
804 while (i < AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS &&
805 edid_caps->display_name[i]) {
806 audio_info->display_name[i] = edid_caps->display_name[i];
807 i++;
808 }
809
810 if(cea_revision >= 3) {
811 audio_info->mode_count = edid_caps->audio_mode_count;
812
813 for (i = 0; i < audio_info->mode_count; ++i) {
814 audio_info->modes[i].format_code =
815 (enum audio_format_code)
816 (edid_caps->audio_modes[i].format_code);
817 audio_info->modes[i].channel_count =
818 edid_caps->audio_modes[i].channel_count;
819 audio_info->modes[i].sample_rates.all =
820 edid_caps->audio_modes[i].sample_rate;
821 audio_info->modes[i].sample_size =
822 edid_caps->audio_modes[i].sample_size;
823 }
824 }
825
826 audio_info->flags.all = edid_caps->speaker_flags;
827
828 /* TODO: We only check for the progressive mode, check for interlace mode too */
829 if(drm_connector->latency_present[0]) {
830 audio_info->video_latency = drm_connector->video_latency[0];
831 audio_info->audio_latency = drm_connector->audio_latency[0];
832 }
833
834 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
835
836}
837
838static void copy_crtc_timing_for_drm_display_mode(
839 const struct drm_display_mode *src_mode,
840 struct drm_display_mode *dst_mode)
841{
842 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
843 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
844 dst_mode->crtc_clock = src_mode->crtc_clock;
845 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
846 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
847 dst_mode->crtc_hsync_start= src_mode->crtc_hsync_start;
848 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
849 dst_mode->crtc_htotal = src_mode->crtc_htotal;
850 dst_mode->crtc_hskew = src_mode->crtc_hskew;
5866e7cf
JL		 851 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
852 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
853 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
854 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
855 dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
4562236b
HW		 856}
857
858static void decide_crtc_timing_for_drm_display_mode(
859 struct drm_display_mode *drm_mode,
860 const struct drm_display_mode *native_mode,
861 bool scale_enabled)
862{
863 if (scale_enabled) {
864 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
865 } else if (native_mode->clock == drm_mode->clock &&
866 native_mode->htotal == drm_mode->htotal &&
867 native_mode->vtotal == drm_mode->vtotal) {
868 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
869 } else {
870 /* no scaling nor amdgpu inserted, no need to patch */
871 }
872}
873
ab2541b6 874static struct dc_stream *create_stream_for_sink(
0d70570f 875 struct amdgpu_connector *aconnector,
4562236b
HW		 876 const struct drm_display_mode *drm_mode,
877 const struct dm_connector_state *dm_state)
878{
879 struct drm_display_mode *preferred_mode = NULL;
880 const struct drm_connector *drm_connector;
ab2541b6 881 struct dc_stream *stream = NULL;
4562236b
HW		 882 struct drm_display_mode mode = *drm_mode;
883 bool native_mode_found = false;
884
885 if (NULL == aconnector) {
886 DRM_ERROR("aconnector is NULL!\n");
887 goto drm_connector_null;
888 }
889
890 if (NULL == dm_state) {
891 DRM_ERROR("dm_state is NULL!\n");
892 goto dm_state_null;
893 }
894
895 drm_connector = &aconnector->base;
896 stream = dc_create_stream_for_sink(aconnector->dc_sink);
897
898 if (NULL == stream) {
899 DRM_ERROR("Failed to create stream for sink!\n");
900 goto stream_create_fail;
901 }
902
903 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
904 /* Search for preferred mode */
905 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
906 native_mode_found = true;
907 break;
908 }
909 }
910 if (!native_mode_found)
911 preferred_mode = list_first_entry_or_null(
912 &aconnector->base.modes,
913 struct drm_display_mode,
914 head);
915
916 if (NULL == preferred_mode) {
917 /* This may not be an error, the use case is when we we have no
918 * usermode calls to reset and set mode upon hotplug. In this
919 * case, we call set mode ourselves to restore the previous mode
920 * and the modelist may not be filled in in time.
921 */
922 DRM_INFO("No preferred mode found\n");
923 } else {
924 decide_crtc_timing_for_drm_display_mode(
925 &mode, preferred_mode,
926 dm_state->scaling != RMX_OFF);
927 }
928
929 fill_stream_properties_from_drm_display_mode(stream,
930 &mode, &aconnector->base);
931 update_stream_scaling_settings(&mode, dm_state, stream);
932
933 fill_audio_info(
934 &stream->audio_info,
935 drm_connector,
936 aconnector->dc_sink);
937
ab2541b6 938stream_create_fail:
4562236b
HW		 939dm_state_null:
940drm_connector_null:
ab2541b6 941 return stream;
4562236b
HW		 942}
943
944void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
945{
946 drm_crtc_cleanup(crtc);
947 kfree(crtc);
948}
949
ba6bf832
AG		 950static void dm_crtc_destroy_state(struct drm_crtc *crtc,
951 struct drm_crtc_state *state)
952{
953 struct dm_crtc_state *cur = to_dm_crtc_state(state);
954
da5c47f6
AG		 955 /* TODO Destroy dc_stream objects are stream object is flattened */
956 if (cur->stream)
957 dc_stream_release(cur->stream);
958
ba6bf832
AG		 959
960 __drm_atomic_helper_crtc_destroy_state(state);
961
962
963 kfree(state);
964}
965
966static void dm_crtc_reset_state(struct drm_crtc *crtc)
967{
968 struct dm_crtc_state *state;
969
970 if (crtc->state)
971 dm_crtc_destroy_state(crtc, crtc->state);
972
973 state = kzalloc(sizeof(*state), GFP_KERNEL);
974 if (WARN_ON(!state))
975 return;
976
ba6bf832
AG		 977 crtc->state = &state->base;
978 crtc->state->crtc = crtc;
979
ba6bf832
AG		 980}
981
982static struct drm_crtc_state *
983dm_crtc_duplicate_state(struct drm_crtc *crtc)
984{
985 struct dm_crtc_state *state, *cur;
ba6bf832
AG		 986
987 cur = to_dm_crtc_state(crtc->state);
ba6bf832 988
da5c47f6 989 if (WARN_ON(!crtc->state))
ba6bf832
AG		 990 return NULL;
991
992 state = dm_alloc(sizeof(*state));
ba6bf832
AG		 993
994 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
995
da5c47f6
AG		 996 if (cur->stream) {
997 state->stream = cur->stream;
998 dc_stream_retain(state->stream);
999 }
ba6bf832
AG		 1000
1001 /* TODO Duplicate dc_stream after objects are stream object is flattened */
1002
1003 return &state->base;
1004}
1005
4562236b
HW		 1006/* Implemented only the options currently availible for the driver */
1007static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
ba6bf832 1008 .reset = dm_crtc_reset_state,
4562236b
HW		 1009 .destroy = amdgpu_dm_crtc_destroy,
1010 .gamma_set = drm_atomic_helper_legacy_gamma_set,
1011 .set_config = drm_atomic_helper_set_config,
1012 .page_flip = drm_atomic_helper_page_flip,
ba6bf832
AG		 1013 .atomic_duplicate_state = dm_crtc_duplicate_state,
1014 .atomic_destroy_state = dm_crtc_destroy_state,
4562236b
HW		 1015};
1016
1017static enum drm_connector_status
1018amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
1019{
1020 bool connected;
1021 struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
1022
1023 /* Notes:
1024 * 1. This interface is NOT called in context of HPD irq.
1025 * 2. This interface *is called* in context of user-mode ioctl. Which
1026 * makes it a bad place for *any* MST-related activit. */
1027
1028 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
1029 connected = (aconnector->dc_sink != NULL);
1030 else
1031 connected = (aconnector->base.force == DRM_FORCE_ON);
1032
1033 return (connected ? connector_status_connected :
1034 connector_status_disconnected);
1035}
1036
1037int amdgpu_dm_connector_atomic_set_property(
1038 struct drm_connector *connector,
1039 struct drm_connector_state *connector_state,
1040 struct drm_property *property,
1041 uint64_t val)
1042{
1043 struct drm_device *dev = connector->dev;
1044 struct amdgpu_device *adev = dev->dev_private;
1045 struct dm_connector_state *dm_old_state =
1046 to_dm_connector_state(connector->state);
1047 struct dm_connector_state *dm_new_state =
1048 to_dm_connector_state(connector_state);
1049
4562236b
HW		 1050 int ret = -EINVAL;
1051
1052 if (property == dev->mode_config.scaling_mode_property) {
1053 enum amdgpu_rmx_type rmx_type;
1054
1055 switch (val) {
1056 case DRM_MODE_SCALE_CENTER:
1057 rmx_type = RMX_CENTER;
1058 break;
1059 case DRM_MODE_SCALE_ASPECT:
1060 rmx_type = RMX_ASPECT;
1061 break;
1062 case DRM_MODE_SCALE_FULLSCREEN:
1063 rmx_type = RMX_FULL;
1064 break;
1065 case DRM_MODE_SCALE_NONE:
1066 default:
1067 rmx_type = RMX_OFF;
1068 break;
1069 }
1070
1071 if (dm_old_state->scaling == rmx_type)
1072 return 0;
1073
1074 dm_new_state->scaling = rmx_type;
1075 ret = 0;
1076 } else if (property == adev->mode_info.underscan_hborder_property) {
1077 dm_new_state->underscan_hborder = val;
1078 ret = 0;
1079 } else if (property == adev->mode_info.underscan_vborder_property) {
1080 dm_new_state->underscan_vborder = val;
1081 ret = 0;
1082 } else if (property == adev->mode_info.underscan_property) {
1083 dm_new_state->underscan_enable = val;
1084 ret = 0;
1085 }
1086
4562236b
HW		 1087 return ret;
1088}
1089
32a1892a
PV		 1090int amdgpu_dm_connector_atomic_get_property(
1091 struct drm_connector *connector,
1092 const struct drm_connector_state *state,
1093 struct drm_property *property,
1094 uint64_t *val)
1095{
1096 struct drm_device *dev = connector->dev;
1097 struct amdgpu_device *adev = dev->dev_private;
1098 struct dm_connector_state *dm_state =
1099 to_dm_connector_state(state);
1100 int ret = -EINVAL;
1101
1102 if (property == dev->mode_config.scaling_mode_property) {
1103 switch (dm_state->scaling) {
1104 case RMX_CENTER:
1105 *val = DRM_MODE_SCALE_CENTER;
1106 break;
1107 case RMX_ASPECT:
1108 *val = DRM_MODE_SCALE_ASPECT;
1109 break;
1110 case RMX_FULL:
1111 *val = DRM_MODE_SCALE_FULLSCREEN;
1112 break;
1113 case RMX_OFF:
1114 default:
1115 *val = DRM_MODE_SCALE_NONE;
1116 break;
1117 }
1118 ret = 0;
1119 } else if (property == adev->mode_info.underscan_hborder_property) {
1120 *val = dm_state->underscan_hborder;
1121 ret = 0;
1122 } else if (property == adev->mode_info.underscan_vborder_property) {
1123 *val = dm_state->underscan_vborder;
1124 ret = 0;
1125 } else if (property == adev->mode_info.underscan_property) {
1126 *val = dm_state->underscan_enable;
1127 ret = 0;
1128 }
1129 return ret;
1130}
1131
4562236b
HW		 1132void amdgpu_dm_connector_destroy(struct drm_connector *connector)
1133{
1134 struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
1135 const struct dc_link *link = aconnector->dc_link;
1136 struct amdgpu_device *adev = connector->dev->dev_private;
1137 struct amdgpu_display_manager *dm = &adev->dm;
1138#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1139 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1140
1141 if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) {
1142 amdgpu_dm_register_backlight_device(dm);
1143
1144 if (dm->backlight_dev) {
1145 backlight_device_unregister(dm->backlight_dev);
1146 dm->backlight_dev = NULL;
1147 }
1148
1149 }
1150#endif
1151 drm_connector_unregister(connector);
1152 drm_connector_cleanup(connector);
1153 kfree(connector);
1154}
1155
1156void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
1157{
1158 struct dm_connector_state *state =
1159 to_dm_connector_state(connector->state);
1160
1161 kfree(state);
1162
1163 state = kzalloc(sizeof(*state), GFP_KERNEL);
1164
1165 if (state) {
1166 state->scaling = RMX_OFF;
1167 state->underscan_enable = false;
1168 state->underscan_hborder = 0;
1169 state->underscan_vborder = 0;
1170
1171 connector->state = &state->base;
1172 connector->state->connector = connector;
1173 }
1174}
1175
1176struct drm_connector_state *amdgpu_dm_connector_atomic_duplicate_state(
1177 struct drm_connector *connector)
1178{
1179 struct dm_connector_state *state =
1180 to_dm_connector_state(connector->state);
1181
1182 struct dm_connector_state *new_state =
1183 kmemdup(state, sizeof(*state), GFP_KERNEL);
1184
1185 if (new_state) {
1186 __drm_atomic_helper_connector_duplicate_state(connector,
1187 &new_state->base);
1188 return &new_state->base;
1189 }
1190
1191 return NULL;
1192}
1193
1194static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
1195 .reset = amdgpu_dm_connector_funcs_reset,
1196 .detect = amdgpu_dm_connector_detect,
1197 .fill_modes = drm_helper_probe_single_connector_modes,
1198 .destroy = amdgpu_dm_connector_destroy,
1199 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
1200 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
664a2ed1 1201 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
32a1892a 1202 .atomic_get_property = amdgpu_dm_connector_atomic_get_property
4562236b
HW		 1203};
1204
1205static struct drm_encoder *best_encoder(struct drm_connector *connector)
1206{
1207 int enc_id = connector->encoder_ids[0];
1208 struct drm_mode_object *obj;
1209 struct drm_encoder *encoder;
1210
1211 DRM_DEBUG_KMS("Finding the best encoder\n");
1212
1213 /* pick the encoder ids */
1214 if (enc_id) {
1215 obj = drm_mode_object_find(connector->dev, enc_id, DRM_MODE_OBJECT_ENCODER);
1216 if (!obj) {
1217 DRM_ERROR("Couldn't find a matching encoder for our connector\n");
1218 return NULL;
1219 }
1220 encoder = obj_to_encoder(obj);
1221 return encoder;
1222 }
1223 DRM_ERROR("No encoder id\n");
1224 return NULL;
1225}
1226
1227static int get_modes(struct drm_connector *connector)
1228{
1229 return amdgpu_dm_connector_get_modes(connector);
1230}
1231
1232static void create_eml_sink(struct amdgpu_connector *aconnector)
1233{
1234 struct dc_sink_init_data init_params = {
1235 .link = aconnector->dc_link,
1236 .sink_signal = SIGNAL_TYPE_VIRTUAL
1237 };
1238 struct edid *edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
1239
1240 if (!aconnector->base.edid_blob_ptr ||
1241 !aconnector->base.edid_blob_ptr->data) {
1242 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
1243 aconnector->base.name);
1244
1245 aconnector->base.force = DRM_FORCE_OFF;
1246 aconnector->base.override_edid = false;
1247 return;
1248 }
1249
1250 aconnector->edid = edid;
1251
1252 aconnector->dc_em_sink = dc_link_add_remote_sink(
1253 aconnector->dc_link,
1254 (uint8_t *)edid,
1255 (edid->extensions + 1) * EDID_LENGTH,
1256 &init_params);
1257
1258 if (aconnector->base.force
1259 == DRM_FORCE_ON)
1260 aconnector->dc_sink = aconnector->dc_link->local_sink ?
1261 aconnector->dc_link->local_sink :
1262 aconnector->dc_em_sink;
1263}
1264
1265static void handle_edid_mgmt(struct amdgpu_connector *aconnector)
1266{
1267 struct dc_link *link = (struct dc_link *)aconnector->dc_link;
1268
1269 /* In case of headless boot with force on for DP managed connector
1270 * Those settings have to be != 0 to get initial modeset
1271 */
1272 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
1273 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
1274 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
1275 }
1276
1277
1278 aconnector->base.override_edid = true;
1279 create_eml_sink(aconnector);
1280}
1281
1282int amdgpu_dm_connector_mode_valid(
1283 struct drm_connector *connector,
1284 struct drm_display_mode *mode)
1285{
1286 int result = MODE_ERROR;
b73a22d3 1287 struct dc_sink *dc_sink;
4562236b 1288 struct amdgpu_device *adev = connector->dev->dev_private;
4562236b 1289 /* TODO: Unhardcode stream count */
ab2541b6 1290 struct dc_stream *stream;
4562236b
HW		 1291 struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
1292
1293 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1294 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
1295 return result;
1296
1297 /* Only run this the first time mode_valid is called to initilialize
1298 * EDID mgmt
1299 */
1300 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
1301 !aconnector->dc_em_sink)
1302 handle_edid_mgmt(aconnector);
1303
1304 dc_sink = to_amdgpu_connector(connector)->dc_sink;
1305
1306 if (NULL == dc_sink) {
1307 DRM_ERROR("dc_sink is NULL!\n");
4017fcdf 1308 goto fail;
4562236b
HW		 1309 }
1310
ab2541b6
AC		 1311 stream = dc_create_stream_for_sink(dc_sink);
1312 if (NULL == stream) {
4562236b 1313 DRM_ERROR("Failed to create stream for sink!\n");
4017fcdf 1314 goto fail;
4562236b
HW		 1315 }
1316
1317 drm_mode_set_crtcinfo(mode, 0);
ab2541b6 1318 fill_stream_properties_from_drm_display_mode(stream, mode, connector);
4562236b 1319
ab2541b6
AC		 1320 stream->src.width = mode->hdisplay;
1321 stream->src.height = mode->vdisplay;
1322 stream->dst = stream->src;
4562236b 1323
4017fcdf 1324 if (dc_validate_stream(adev->dm.dc, stream))
4562236b
HW		 1325 result = MODE_OK;
1326
ab2541b6
AC		 1327 dc_stream_release(stream);
1328
4017fcdf 1329fail:
4562236b
HW		 1330 /* TODO: error handling*/
1331 return result;
1332}
1333
1334static const struct drm_connector_helper_funcs
1335amdgpu_dm_connector_helper_funcs = {
1336 /*
1337 * If hotplug a second bigger display in FB Con mode, bigger resolution
1338 * modes will be filtered by drm_mode_validate_size(), and those modes
1339 * is missing after user start lightdm. So we need to renew modes list.
1340 * in get_modes call back, not just return the modes count
1341 */
1342 .get_modes = get_modes,
1343 .mode_valid = amdgpu_dm_connector_mode_valid,
1344 .best_encoder = best_encoder
1345};
1346
1347static void dm_crtc_helper_disable(struct drm_crtc *crtc)
1348{
1349}
1350
1351static int dm_crtc_helper_atomic_check(
1352 struct drm_crtc *crtc,
1353 struct drm_crtc_state *state)
1354{
4017fcdf
AG		 1355 struct amdgpu_device *adev = crtc->dev->dev_private;
1356 struct dc *dc = adev->dm.dc;
1357 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state);
1358 int ret = -EINVAL;
1359
1360 if (unlikely(!dm_crtc_state->stream && modeset_required(state))) {
1361 WARN_ON(1);
1362 return ret;
1363 }
1364
1365 /* In some use cases, like reset, no stream is attached */
1366 if (!dm_crtc_state->stream)
1367 return 0;
1368
1369 if (dc_validate_stream(dc, dm_crtc_state->stream))
1370 return 0;
1371
1372 return ret;
4562236b
HW		 1373}
1374
1375static bool dm_crtc_helper_mode_fixup(
1376 struct drm_crtc *crtc,
1377 const struct drm_display_mode *mode,
1378 struct drm_display_mode *adjusted_mode)
1379{
1380 return true;
1381}
1382
1383static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
1384 .disable = dm_crtc_helper_disable,
1385 .atomic_check = dm_crtc_helper_atomic_check,
1386 .mode_fixup = dm_crtc_helper_mode_fixup
1387};
1388
1389static void dm_encoder_helper_disable(struct drm_encoder *encoder)
1390{
1391
1392}
1393
1394static int dm_encoder_helper_atomic_check(
1395 struct drm_encoder *encoder,
1396 struct drm_crtc_state *crtc_state,
1397 struct drm_connector_state *conn_state)
1398{
1399 return 0;
1400}
1401
1402const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
1403 .disable = dm_encoder_helper_disable,
1404 .atomic_check = dm_encoder_helper_atomic_check
1405};
1406
64d8b780
S		 1407static void dm_drm_plane_reset(struct drm_plane *plane)
1408{
0604b36c 1409 struct dm_plane_state *amdgpu_state = NULL;
0604b36c
AG		 1410
1411 if (plane->state)
1412 plane->funcs->atomic_destroy_state(plane, plane->state);
64d8b780
S		 1413
1414 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
0604b36c 1415
64d8b780
S		 1416 if (amdgpu_state) {
1417 plane->state = &amdgpu_state->base;
1418 plane->state->plane = plane;
0604b36c 1419 plane->state->rotation = DRM_MODE_ROTATE_0;
64d8b780 1420 }
0604b36c
AG		 1421 else
1422 WARN_ON(1);
64d8b780
S		 1423}
1424
1425static struct drm_plane_state *
1426dm_drm_plane_duplicate_state(struct drm_plane *plane)
1427{
0604b36c 1428 struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
0604b36c
AG		 1429
1430 old_dm_plane_state = to_dm_plane_state(plane->state);
1431 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
1432 if (!dm_plane_state)
1433 return NULL;
1434
3d21a662 1435 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
0604b36c 1436
d7e3316c
AG		 1437 if (old_dm_plane_state->surface) {
1438 dm_plane_state->surface = old_dm_plane_state->surface;
1439 dc_surface_retain(dm_plane_state->surface);
0604b36c 1440 }
64d8b780 1441
0604b36c 1442 return &dm_plane_state->base;
64d8b780
S		 1443}
1444
0604b36c
AG		 1445void dm_drm_plane_destroy_state(struct drm_plane *plane,
1446 struct drm_plane_state *state)
64d8b780 1447{
0604b36c
AG		 1448 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
1449
d7e3316c
AG		 1450 if (dm_plane_state->surface)
1451 dc_surface_release(dm_plane_state->surface);
0604b36c 1452
a67297d4
XY		 1453 __drm_atomic_helper_plane_destroy_state(state);
1454 kfree(dm_plane_state);
64d8b780
S		 1455}
1456
4562236b 1457static const struct drm_plane_funcs dm_plane_funcs = {
64d8b780
S		 1458 .update_plane = drm_atomic_helper_update_plane,
1459 .disable_plane = drm_atomic_helper_disable_plane,
1460 .destroy = drm_plane_cleanup,
1461 .reset = dm_drm_plane_reset,
1462 .atomic_duplicate_state = dm_drm_plane_duplicate_state,
1463 .atomic_destroy_state = dm_drm_plane_destroy_state,
4562236b
HW		 1464};
1465
4562236b
HW		 1466static int dm_plane_helper_prepare_fb(
1467 struct drm_plane *plane,
1468 struct drm_plane_state *new_state)
1469{
1470 struct amdgpu_framebuffer *afb;
1471 struct drm_gem_object *obj;
1472 struct amdgpu_bo *rbo;
1473 int r;
d7e3316c
AG		 1474 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
1475 unsigned int awidth;
1476
1477 dm_plane_state_old = to_dm_plane_state(plane->state);
1478 dm_plane_state_new = to_dm_plane_state(new_state);
4562236b
HW		 1479
1480 if (!new_state->fb) {
1481 DRM_DEBUG_KMS("No FB bound\n");
1482 return 0;
1483 }
1484
1485 afb = to_amdgpu_framebuffer(new_state->fb);
1486
1487 obj = afb->obj;
1488 rbo = gem_to_amdgpu_bo(obj);
1489 r = amdgpu_bo_reserve(rbo, false);
1490 if (unlikely(r != 0))
1491 return r;
1492
54f5499a 1493 r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &afb->address);
4562236b 1494
d7e3316c 1495
4562236b
HW		 1496 amdgpu_bo_unreserve(rbo);
1497
1498 if (unlikely(r != 0)) {
1499 DRM_ERROR("Failed to pin framebuffer\n");
1500 return r;
1501 }
1502
54f5499a 1503 amdgpu_bo_ref(rbo);
2ea5e9a8 1504
d7e3316c
AG		 1505 if (dm_plane_state_new->surface &&
1506 dm_plane_state_old->surface != dm_plane_state_new->surface) {
1507 struct dc_surface *surface = dm_plane_state_new->surface;
1508
1509 if (surface->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
1510 surface->address.grph.addr.low_part = lower_32_bits(afb->address);
1511 surface->address.grph.addr.high_part = upper_32_bits(afb->address);
1512 } else {
1513 awidth = ALIGN(new_state->fb->width, 64);
1514 surface->address.video_progressive.luma_addr.low_part
1515 = lower_32_bits(afb->address);
1516 surface->address.video_progressive.chroma_addr.low_part
1517 = lower_32_bits(afb->address) +
1518 (awidth * new_state->fb->height);
1519 }
1520 }
1521
2ea5e9a8
AG		 1522 /* It's a hack for s3 since in 4.9 kernel filter out cursor buffer
1523 * prepare and cleanup in drm_atomic_helper_prepare_planes
1524 * and drm_atomic_helper_cleanup_planes because fb doens't in s3.
1525 * IN 4.10 kernel this code should be removed and amdgpu_device_suspend
1526 * code touching fram buffers should be avoided for DC.
1527 */
1528 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
1529 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_state->crtc);
1530
1531 acrtc->cursor_bo = obj;
1532 }
4562236b
HW		 1533 return 0;
1534}
1535
1536static void dm_plane_helper_cleanup_fb(
1537 struct drm_plane *plane,
1538 struct drm_plane_state *old_state)
1539{
1540 struct amdgpu_bo *rbo;
1541 struct amdgpu_framebuffer *afb;
1542 int r;
1543
1544 if (!old_state->fb)
1545 return;
1546
1547 afb = to_amdgpu_framebuffer(old_state->fb);
1548 rbo = gem_to_amdgpu_bo(afb->obj);
1549 r = amdgpu_bo_reserve(rbo, false);
1550 if (unlikely(r)) {
1551 DRM_ERROR("failed to reserve rbo before unpin\n");
1552 return;
1553 } else {
1554 amdgpu_bo_unpin(rbo);
1555 amdgpu_bo_unreserve(rbo);
54f5499a 1556 amdgpu_bo_unref(&rbo);
3273d3bf 1557 };
4562236b
HW		 1558}
1559
ab2541b6 1560int dm_create_validation_set_for_connector(struct drm_connector *connector,
4562236b
HW		 1561 struct drm_display_mode *mode, struct dc_validation_set *val_set)
1562{
1563 int result = MODE_ERROR;
b73a22d3 1564 struct dc_sink *dc_sink =
4562236b
HW		 1565 to_amdgpu_connector(connector)->dc_sink;
1566 /* TODO: Unhardcode stream count */
ab2541b6 1567 struct dc_stream *stream;
4562236b
HW		 1568
1569 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1570 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
1571 return result;
1572
1573 if (NULL == dc_sink) {
1574 DRM_ERROR("dc_sink is NULL!\n");
1575 return result;
1576 }
1577
ab2541b6 1578 stream = dc_create_stream_for_sink(dc_sink);
4562236b 1579
ab2541b6 1580 if (NULL == stream) {
4562236b
HW		 1581 DRM_ERROR("Failed to create stream for sink!\n");
1582 return result;
1583 }
1584
1585 drm_mode_set_crtcinfo(mode, 0);
1586
ab2541b6 1587 fill_stream_properties_from_drm_display_mode(stream, mode, connector);
4562236b 1588
ab2541b6 1589 val_set->stream = stream;
4562236b 1590
ab2541b6
AC		 1591 stream->src.width = mode->hdisplay;
1592 stream->src.height = mode->vdisplay;
1593 stream->dst = stream->src;
4562236b
HW		 1594
1595 return MODE_OK;
4562236b
HW		 1596}
1597
1598static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
1599 .prepare_fb = dm_plane_helper_prepare_fb,
1600 .cleanup_fb = dm_plane_helper_cleanup_fb,
1601};
1602
1603/*
1604 * TODO: these are currently initialized to rgb formats only.
1605 * For future use cases we should either initialize them dynamically based on
1606 * plane capabilities, or initialize this array to all formats, so internal drm
1607 * check will succeed, and let DC to implement proper check
1608 */
1609static uint32_t rgb_formats[] = {
4562236b
HW		 1610 DRM_FORMAT_RGB888,
1611 DRM_FORMAT_XRGB8888,
1612 DRM_FORMAT_ARGB8888,
1613 DRM_FORMAT_RGBA8888,
1614 DRM_FORMAT_XRGB2101010,
1615 DRM_FORMAT_XBGR2101010,
1616 DRM_FORMAT_ARGB2101010,
1617 DRM_FORMAT_ABGR2101010,
1618};
1619
d4e13b0d 1620static uint32_t yuv_formats[] = {
f0c16087
S		 1621 DRM_FORMAT_NV12,
1622 DRM_FORMAT_NV21,
d4e13b0d 1623};
4562236b 1624
2ea5e9a8
AG		 1625static const u32 cursor_formats[] = {
1626 DRM_FORMAT_ARGB8888
1627};
1628
d4e13b0d
AD		 1629int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
1630 struct amdgpu_plane *aplane,
1631 unsigned long possible_crtcs)
1632{
1633 int res = -EPERM;
1634
1605b3be 1635 switch (aplane->base.type) {
d4e13b0d
AD		 1636 case DRM_PLANE_TYPE_PRIMARY:
1637 aplane->base.format_default = true;
1638
1639 res = drm_universal_plane_init(
1640 dm->adev->ddev,
1641 &aplane->base,
1642 possible_crtcs,
1643 &dm_plane_funcs,
1644 rgb_formats,
1645 ARRAY_SIZE(rgb_formats),
1605b3be 1646 NULL, aplane->base.type, NULL);
d4e13b0d
AD		 1647 break;
1648 case DRM_PLANE_TYPE_OVERLAY:
1649 res = drm_universal_plane_init(
1650 dm->adev->ddev,
1651 &aplane->base,
1652 possible_crtcs,
1653 &dm_plane_funcs,
1654 yuv_formats,
1655 ARRAY_SIZE(yuv_formats),
1605b3be 1656 NULL, aplane->base.type, NULL);
d4e13b0d
AD		 1657 break;
1658 case DRM_PLANE_TYPE_CURSOR:
2ea5e9a8
AG		 1659 res = drm_universal_plane_init(
1660 dm->adev->ddev,
1661 &aplane->base,
1662 possible_crtcs,
1663 &dm_plane_funcs,
1664 cursor_formats,
1665 ARRAY_SIZE(cursor_formats),
1605b3be 1666 NULL, aplane->base.type, NULL);
d4e13b0d
AD		 1667 break;
1668 }
4562236b 1669
d4e13b0d 1670 drm_plane_helper_add(&aplane->base, &dm_plane_helper_funcs);
4562236b 1671
d4e13b0d
AD		 1672 return res;
1673}
4562236b 1674
d4e13b0d
AD		 1675int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
1676 struct drm_plane *plane,
1677 uint32_t crtc_index)
1678{
2ea5e9a8
AG		 1679 struct amdgpu_crtc *acrtc = NULL;
1680 struct amdgpu_plane *cursor_plane;
1681
d4e13b0d 1682 int res = -ENOMEM;
4562236b 1683
2ea5e9a8
AG		 1684 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
1685 if (!cursor_plane)
1686 goto fail;
1687
1688 cursor_plane->base.type = DRM_PLANE_TYPE_CURSOR;
1689 res = amdgpu_dm_plane_init(dm, cursor_plane, 0);
1690
d4e13b0d
AD		 1691 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
1692 if (!acrtc)
1693 goto fail;
4562236b
HW		 1694
1695 res = drm_crtc_init_with_planes(
1696 dm->ddev,
1697 &acrtc->base,
d4e13b0d 1698 plane,
2ea5e9a8 1699 &cursor_plane->base,
4562236b
HW		 1700 &amdgpu_dm_crtc_funcs, NULL);
1701
1702 if (res)
1703 goto fail;
1704
1705 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
1706
10349345
AG		 1707 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
1708 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
4562236b
HW		 1709
1710 acrtc->crtc_id = crtc_index;
1711 acrtc->base.enabled = false;
1712
1713 dm->adev->mode_info.crtcs[crtc_index] = acrtc;
1714 drm_mode_crtc_set_gamma_size(&acrtc->base, 256);
1715
1716 return 0;
2ea5e9a8 1717
4562236b 1718fail:
2ea5e9a8
AG		 1719 if (acrtc)
1720 kfree(acrtc);
1721 if (cursor_plane)
1722 kfree(cursor_plane);
4562236b
HW		 1723 acrtc->crtc_id = -1;
1724 return res;
1725}
1726
2ea5e9a8 1727
4562236b
HW		 1728static int to_drm_connector_type(enum signal_type st)
1729{
1730 switch (st) {
1731 case SIGNAL_TYPE_HDMI_TYPE_A:
1732 return DRM_MODE_CONNECTOR_HDMIA;
1733 case SIGNAL_TYPE_EDP:
1734 return DRM_MODE_CONNECTOR_eDP;
1735 case SIGNAL_TYPE_RGB:
1736 return DRM_MODE_CONNECTOR_VGA;
1737 case SIGNAL_TYPE_DISPLAY_PORT:
1738 case SIGNAL_TYPE_DISPLAY_PORT_MST:
1739 return DRM_MODE_CONNECTOR_DisplayPort;
1740 case SIGNAL_TYPE_DVI_DUAL_LINK:
1741 case SIGNAL_TYPE_DVI_SINGLE_LINK:
1742 return DRM_MODE_CONNECTOR_DVID;
1743 case SIGNAL_TYPE_VIRTUAL:
1744 return DRM_MODE_CONNECTOR_VIRTUAL;
1745
1746 default:
1747 return DRM_MODE_CONNECTOR_Unknown;
1748 }
1749}
1750
1751static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
1752{
1753 const struct drm_connector_helper_funcs *helper =
1754 connector->helper_private;
1755 struct drm_encoder *encoder;
1756 struct amdgpu_encoder *amdgpu_encoder;
1757
1758 encoder = helper->best_encoder(connector);
1759
1760 if (encoder == NULL)
1761 return;
1762
1763 amdgpu_encoder = to_amdgpu_encoder(encoder);
1764
1765 amdgpu_encoder->native_mode.clock = 0;
1766
1767 if (!list_empty(&connector->probed_modes)) {
1768 struct drm_display_mode *preferred_mode = NULL;
1769 list_for_each_entry(preferred_mode,
1770 &connector->probed_modes,
1771 head) {
1772 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
1773 amdgpu_encoder->native_mode = *preferred_mode;
1774 }
1775 break;
1776 }
1777
1778 }
1779}
1780
1781static struct drm_display_mode *amdgpu_dm_create_common_mode(
1782 struct drm_encoder *encoder, char *name,
1783 int hdisplay, int vdisplay)
1784{
1785 struct drm_device *dev = encoder->dev;
1786 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1787 struct drm_display_mode *mode = NULL;
1788 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1789
1790 mode = drm_mode_duplicate(dev, native_mode);
1791
1792 if(mode == NULL)
1793 return NULL;
1794
1795 mode->hdisplay = hdisplay;
1796 mode->vdisplay = vdisplay;
1797 mode->type &= ~DRM_MODE_TYPE_PREFERRED;
1798 strncpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
1799
1800 return mode;
1801
1802}
1803
1804static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
1805 struct drm_connector *connector)
1806{
1807 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1808 struct drm_display_mode *mode = NULL;
1809 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1810 struct amdgpu_connector *amdgpu_connector =
1811 to_amdgpu_connector(connector);
1812 int i;
1813 int n;
1814 struct mode_size {
1815 char name[DRM_DISPLAY_MODE_LEN];
1816 int w;
1817 int h;
1818 }common_modes[] = {
1819 { "640x480", 640, 480},
1820 { "800x600", 800, 600},
1821 { "1024x768", 1024, 768},
1822 { "1280x720", 1280, 720},
1823 { "1280x800", 1280, 800},
1824 {"1280x1024", 1280, 1024},
1825 { "1440x900", 1440, 900},
1826 {"1680x1050", 1680, 1050},
1827 {"1600x1200", 1600, 1200},
1828 {"1920x1080", 1920, 1080},
1829 {"1920x1200", 1920, 1200}
1830 };
1831
1832 n = sizeof(common_modes) / sizeof(common_modes[0]);
1833
1834 for (i = 0; i < n; i++) {
1835 struct drm_display_mode *curmode = NULL;
1836 bool mode_existed = false;
1837
1838 if (common_modes[i].w > native_mode->hdisplay ||
1839 common_modes[i].h > native_mode->vdisplay ||
1840 (common_modes[i].w == native_mode->hdisplay &&
1841 common_modes[i].h == native_mode->vdisplay))
1842 continue;
1843
1844 list_for_each_entry(curmode, &connector->probed_modes, head) {
1845 if (common_modes[i].w == curmode->hdisplay &&
1846 common_modes[i].h == curmode->vdisplay) {
1847 mode_existed = true;
1848 break;
1849 }
1850 }
1851
1852 if (mode_existed)
1853 continue;
1854
1855 mode = amdgpu_dm_create_common_mode(encoder,
1856 common_modes[i].name, common_modes[i].w,
1857 common_modes[i].h);
1858 drm_mode_probed_add(connector, mode);
1859 amdgpu_connector->num_modes++;
1860 }
1861}
1862
1863static void amdgpu_dm_connector_ddc_get_modes(
1864 struct drm_connector *connector,
1865 struct edid *edid)
1866{
1867 struct amdgpu_connector *amdgpu_connector =
1868 to_amdgpu_connector(connector);
1869
1870 if (edid) {
1871 /* empty probed_modes */
1872 INIT_LIST_HEAD(&connector->probed_modes);
1873 amdgpu_connector->num_modes =
1874 drm_add_edid_modes(connector, edid);
1875
1876 drm_edid_to_eld(connector, edid);
1877
1878 amdgpu_dm_get_native_mode(connector);
1879 } else
1880 amdgpu_connector->num_modes = 0;
1881}
1882
1883int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
1884{
1885 const struct drm_connector_helper_funcs *helper =
1886 connector->helper_private;
1887 struct amdgpu_connector *amdgpu_connector =
1888 to_amdgpu_connector(connector);
1889 struct drm_encoder *encoder;
1890 struct edid *edid = amdgpu_connector->edid;
1891
1892 encoder = helper->best_encoder(connector);
1893
1894 amdgpu_dm_connector_ddc_get_modes(connector, edid);
1895 amdgpu_dm_connector_add_common_modes(encoder, connector);
1896 return amdgpu_connector->num_modes;
1897}
1898
1899void amdgpu_dm_connector_init_helper(
1900 struct amdgpu_display_manager *dm,
1901 struct amdgpu_connector *aconnector,
1902 int connector_type,
d0778ebf 1903 struct dc_link *link,
4562236b
HW		 1904 int link_index)
1905{
1906 struct amdgpu_device *adev = dm->ddev->dev_private;
1907
1908 aconnector->connector_id = link_index;
1909 aconnector->dc_link = link;
67a27705
HW		 1910 aconnector->base.interlace_allowed = false;
1911 aconnector->base.doublescan_allowed = false;
1912 aconnector->base.stereo_allowed = false;
4562236b
HW		 1913 aconnector->base.dpms = DRM_MODE_DPMS_OFF;
1914 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
1915
1916 mutex_init(&aconnector->hpd_lock);
1917
1918 /*configure suport HPD hot plug connector_>polled default value is 0
1919 * which means HPD hot plug not supported*/
1920 switch (connector_type) {
1921 case DRM_MODE_CONNECTOR_HDMIA:
1922 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
1923 break;
1924 case DRM_MODE_CONNECTOR_DisplayPort:
1925 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
1926 break;
1927 case DRM_MODE_CONNECTOR_DVID:
1928 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
1929 break;
1930 default:
1931 break;
1932 }
1933
1934 drm_object_attach_property(&aconnector->base.base,
1935 dm->ddev->mode_config.scaling_mode_property,
1936 DRM_MODE_SCALE_NONE);
1937
1938 drm_object_attach_property(&aconnector->base.base,
1939 adev->mode_info.underscan_property,
1940 UNDERSCAN_OFF);
1941 drm_object_attach_property(&aconnector->base.base,
1942 adev->mode_info.underscan_hborder_property,
1943 0);
1944 drm_object_attach_property(&aconnector->base.base,
1945 adev->mode_info.underscan_vborder_property,
1946 0);
1947
1948}
1949
1950int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
1951 struct i2c_msg *msgs, int num)
1952{
1953 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
46df790c 1954 struct ddc_service *ddc_service = i2c->ddc_service;
4562236b
HW		 1955 struct i2c_command cmd;
1956 int i;
1957 int result = -EIO;
1958
1959 cmd.payloads = kzalloc(num * sizeof(struct i2c_payload), GFP_KERNEL);
1960
1961 if (!cmd.payloads)
1962 return result;
1963
1964 cmd.number_of_payloads = num;
1965 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
1966 cmd.speed = 100;
1967
1968 for (i = 0; i < num; i++) {
bb01672c 1969 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
4562236b
HW		 1970 cmd.payloads[i].address = msgs[i].addr;
1971 cmd.payloads[i].length = msgs[i].len;
1972 cmd.payloads[i].data = msgs[i].buf;
1973 }
1974
46df790c
AG		 1975 if (dal_i2caux_submit_i2c_command(
1976 ddc_service->ctx->i2caux,
1977 ddc_service->ddc_pin,
1978 &cmd))
4562236b
HW		 1979 result = num;
1980
1981 kfree(cmd.payloads);
4562236b
HW		 1982 return result;
1983}
1984
1985u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
1986{
1987 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
1988}
1989
1990static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
1991 .master_xfer = amdgpu_dm_i2c_xfer,
1992 .functionality = amdgpu_dm_i2c_func,
1993};
1994
46df790c
AG		 1995static struct amdgpu_i2c_adapter *create_i2c(
1996 struct ddc_service *ddc_service,
1997 int link_index,
1998 int *res)
4562236b 1999{
46df790c 2000 struct amdgpu_device *adev = ddc_service->ctx->driver_context;
4562236b
HW		 2001 struct amdgpu_i2c_adapter *i2c;
2002
2003 i2c = kzalloc(sizeof (struct amdgpu_i2c_adapter), GFP_KERNEL);
4562236b
HW		 2004 i2c->base.owner = THIS_MODULE;
2005 i2c->base.class = I2C_CLASS_DDC;
46df790c 2006 i2c->base.dev.parent = &adev->pdev->dev;
4562236b
HW		 2007 i2c->base.algo = &amdgpu_dm_i2c_algo;
2008 snprintf(i2c->base.name, sizeof (i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
4562236b 2009 i2c_set_adapdata(&i2c->base, i2c);
46df790c 2010 i2c->ddc_service = ddc_service;
4562236b
HW		 2011
2012 return i2c;
2013}
2014
2015/* Note: this function assumes that dc_link_detect() was called for the
2016 * dc_link which will be represented by this aconnector. */
2017int amdgpu_dm_connector_init(
2018 struct amdgpu_display_manager *dm,
2019 struct amdgpu_connector *aconnector,
2020 uint32_t link_index,
2021 struct amdgpu_encoder *aencoder)
2022{
2023 int res = 0;
2024 int connector_type;
2025 struct dc *dc = dm->dc;
d0778ebf 2026 struct dc_link *link = dc_get_link_at_index(dc, link_index);
4562236b 2027 struct amdgpu_i2c_adapter *i2c;
9fb8de78 2028 ((struct dc_link *)link)->priv = aconnector;
4562236b
HW		 2029
2030 DRM_DEBUG_KMS("%s()\n", __func__);
2031
46df790c 2032 i2c = create_i2c(link->ddc, link->link_index, &res);
4562236b
HW		 2033 aconnector->i2c = i2c;
2034 res = i2c_add_adapter(&i2c->base);
2035
2036 if (res) {
2037 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
2038 goto out_free;
2039 }
2040
2041 connector_type = to_drm_connector_type(link->connector_signal);
2042
2043 res = drm_connector_init(
2044 dm->ddev,
2045 &aconnector->base,
2046 &amdgpu_dm_connector_funcs,
2047 connector_type);
2048
2049 if (res) {
2050 DRM_ERROR("connector_init failed\n");
2051 aconnector->connector_id = -1;
2052 goto out_free;
2053 }
2054
2055 drm_connector_helper_add(
2056 &aconnector->base,
2057 &amdgpu_dm_connector_helper_funcs);
2058
2059 amdgpu_dm_connector_init_helper(
2060 dm,
2061 aconnector,
2062 connector_type,
2063 link,
2064 link_index);
2065
2066 drm_mode_connector_attach_encoder(
2067 &aconnector->base, &aencoder->base);
2068
2069 drm_connector_register(&aconnector->base);
2070
2071 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
2072 || connector_type == DRM_MODE_CONNECTOR_eDP)
7c7f5b15 2073 amdgpu_dm_initialize_dp_connector(dm, aconnector);
4562236b
HW		 2074
2075#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
2076 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
2077
2078 /* NOTE: this currently will create backlight device even if a panel
2079 * is not connected to the eDP/LVDS connector.
2080 *
2081 * This is less than ideal but we don't have sink information at this
2082 * stage since detection happens after. We can't do detection earlier
2083 * since MST detection needs connectors to be created first.
2084 */
2085 if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) {
2086 /* Event if registration failed, we should continue with
2087 * DM initialization because not having a backlight control
2088 * is better then a black screen. */
2089 amdgpu_dm_register_backlight_device(dm);
2090
2091 if (dm->backlight_dev)
2092 dm->backlight_link = link;
2093 }
2094#endif
2095
2096out_free:
2097 if (res) {
2098 kfree(i2c);
2099 aconnector->i2c = NULL;
2100 }
2101 return res;
2102}
2103
2104int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
2105{
2106 switch (adev->mode_info.num_crtc) {
2107 case 1:
2108 return 0x1;
2109 case 2:
2110 return 0x3;
2111 case 3:
2112 return 0x7;
2113 case 4:
2114 return 0xf;
2115 case 5:
2116 return 0x1f;
2117 case 6:
2118 default:
2119 return 0x3f;
2120 }
2121}
2122
2123int amdgpu_dm_encoder_init(
2124 struct drm_device *dev,
2125 struct amdgpu_encoder *aencoder,
2126 uint32_t link_index)
2127{
2128 struct amdgpu_device *adev = dev->dev_private;
2129
2130 int res = drm_encoder_init(dev,
2131 &aencoder->base,
2132 &amdgpu_dm_encoder_funcs,
2133 DRM_MODE_ENCODER_TMDS,
2134 NULL);
2135
2136 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
2137
2138 if (!res)
2139 aencoder->encoder_id = link_index;
2140 else
2141 aencoder->encoder_id = -1;
2142
2143 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
2144
2145 return res;
2146}
2147
4562236b
HW		 2148static void manage_dm_interrupts(
2149 struct amdgpu_device *adev,
2150 struct amdgpu_crtc *acrtc,
2151 bool enable)
2152{
2153 /*
2154 * this is not correct translation but will work as soon as VBLANK
2155 * constant is the same as PFLIP
2156 */
2157 int irq_type =
2158 amdgpu_crtc_idx_to_irq_type(
2159 adev,
2160 acrtc->crtc_id);
2161
2162 if (enable) {
2163 drm_crtc_vblank_on(&acrtc->base);
2164 amdgpu_irq_get(
2165 adev,
2166 &adev->pageflip_irq,
2167 irq_type);
2168 } else {
4562236b
HW		 2169
2170 amdgpu_irq_put(
2171 adev,
2172 &adev->pageflip_irq,
2173 irq_type);
2174 drm_crtc_vblank_off(&acrtc->base);
2175 }
2176}
2177
4562236b
HW		 2178static bool is_scaling_state_different(
2179 const struct dm_connector_state *dm_state,
2180 const struct dm_connector_state *old_dm_state)
2181{
2182 if (dm_state->scaling != old_dm_state->scaling)
2183 return true;
2184 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
2185 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
2186 return true;
2187 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
2188 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
2189 return true;
2190 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder
2191 || dm_state->underscan_vborder != old_dm_state->underscan_vborder)
2192 return true;
2193 return false;
2194}
2195
da5c47f6
AG		 2196static void remove_stream(
2197 struct amdgpu_device *adev,
2198 struct amdgpu_crtc *acrtc,
4fa086b9 2199 struct dc_stream *stream)
4562236b 2200{
4562236b
HW		 2201 /* this is the update mode case */
2202 if (adev->dm.freesync_module)
da5c47f6 2203 mod_freesync_remove_stream(adev->dm.freesync_module, stream);
ab2541b6 2204
4562236b
HW		 2205 acrtc->otg_inst = -1;
2206 acrtc->enabled = false;
2207}
2208
2ea5e9a8
AG		 2209static void handle_cursor_update(
2210 struct drm_plane *plane,
2211 struct drm_plane_state *old_plane_state)
2212{
2213 if (!plane->state->fb && !old_plane_state->fb)
2214 return;
2215
2216 /* Check if it's a cursor on/off update or just cursor move*/
2217 if (plane->state->fb == old_plane_state->fb)
2218 dm_crtc_cursor_move(
2219 plane->state->crtc,
2220 plane->state->crtc_x,
2221 plane->state->crtc_y);
2222 else {
2223 struct amdgpu_framebuffer *afb =
2224 to_amdgpu_framebuffer(plane->state->fb);
2225 dm_crtc_cursor_set(
2226 (!!plane->state->fb) ?
2227 plane->state->crtc :
2228 old_plane_state->crtc,
2229 (!!plane->state->fb) ?
2230 afb->address :
2231 0,
2232 plane->state->crtc_w,
2233 plane->state->crtc_h);
2234 }
2235}
2236
54f5499a 2237
1159898a
AG		 2238static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
2239{
2240
2241 assert_spin_locked(&acrtc->base.dev->event_lock);
2242 WARN_ON(acrtc->event);
2243
2244 acrtc->event = acrtc->base.state->event;
2245
2246 /* Set the flip status */
2247 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
2248
2249 /* Mark this event as consumed */
2250 acrtc->base.state->event = NULL;
2251
2252 DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
2253 acrtc->crtc_id);
2254}
2255
54f5499a
AG		 2256/*
2257 * Executes flip
2258 *
2259 * Waits on all BO's fences and for proper vblank count
2260 */
2261static void amdgpu_dm_do_flip(
2262 struct drm_crtc *crtc,
2263 struct drm_framebuffer *fb,
2264 uint32_t target)
2265{
2266 unsigned long flags;
2267 uint32_t target_vblank;
2268 int r, vpos, hpos;
2269 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2270 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
2271 struct amdgpu_bo *abo = gem_to_amdgpu_bo(afb->obj);
2272 struct amdgpu_device *adev = crtc->dev->dev_private;
2273 bool async_flip = (acrtc->flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
70470154
AG		 2274 struct dc_flip_addrs addr = { {0} };
2275 struct dc_surface_update surface_updates[1] = { {0} };
da5c47f6
AG		 2276 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
2277
54f5499a 2278
00d7930c
MK		 2279 /* Prepare wait for target vblank early - before the fence-waits */
2280 target_vblank = target - drm_crtc_vblank_count(crtc) +
2281 amdgpu_get_vblank_counter_kms(crtc->dev, acrtc->crtc_id);
54f5499a
AG		 2282
2283 /*TODO This might fail and hence better not used, wait
2284 * explicitly on fences instead
2285 * and in general should be called for
2286 * blocking commit to as per framework helpers
2287 * */
2288 r = amdgpu_bo_reserve(abo, true);
2289 if (unlikely(r != 0)) {
2290 DRM_ERROR("failed to reserve buffer before flip\n");
70470154 2291 WARN_ON(1);
54f5499a
AG		 2292 }
2293
2294 /* Wait for all fences on this FB */
2295 WARN_ON(reservation_object_wait_timeout_rcu(abo->tbo.resv, true, false,
2296 MAX_SCHEDULE_TIMEOUT) < 0);
2297
2298 amdgpu_bo_unreserve(abo);
2299
54f5499a
AG		 2300 /* Wait until we're out of the vertical blank period before the one
2301 * targeted by the flip
2302 */
54f5499a
AG		 2303 while ((acrtc->enabled &&
2304 (amdgpu_get_crtc_scanoutpos(adev->ddev, acrtc->crtc_id, 0,
2305 &vpos, &hpos, NULL, NULL,
2306 &crtc->hwmode)
2307 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
2308 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
2309 (int)(target_vblank -
2310 amdgpu_get_vblank_counter_kms(adev->ddev, acrtc->crtc_id)) > 0)) {
2311 usleep_range(1000, 1100);
2312 }
2313
2314 /* Flip */
2315 spin_lock_irqsave(&crtc->dev->event_lock, flags);
2316 /* update crtc fb */
2317 crtc->primary->fb = fb;
2318
70470154 2319 WARN_ON(acrtc->pflip_status != AMDGPU_FLIP_NONE);
da5c47f6 2320 WARN_ON(!acrtc_state->stream);
70470154
AG		 2321
2322 addr.address.grph.addr.low_part = lower_32_bits(afb->address);
2323 addr.address.grph.addr.high_part = upper_32_bits(afb->address);
2324 addr.flip_immediate = async_flip;
2325
2326
1159898a
AG		 2327 if (acrtc->base.state->event)
2328 prepare_flip_isr(acrtc);
70470154 2329
da5c47f6 2330 surface_updates->surface = dc_stream_get_status(acrtc_state->stream)->surfaces[0];
70470154
AG		 2331 surface_updates->flip_addr = &addr;
2332
2333
da5c47f6 2334 dc_update_surfaces_and_stream(adev->dm.dc, surface_updates, 1, acrtc_state->stream, NULL);
70470154
AG		 2335
2336 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n",
2337 __func__,
2338 addr.address.grph.addr.high_part,
2339 addr.address.grph.addr.low_part);
2340
54f5499a
AG		 2341
2342 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
54f5499a
AG		 2343}
2344
bdc79f8e 2345static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state,
0430d52b
S		 2346 struct drm_device *dev,
2347 struct amdgpu_display_manager *dm,
bdc79f8e
AG		 2348 struct drm_crtc *pcrtc,
2349 bool *wait_for_vblank)
129eed72
HW		 2350{
2351 uint32_t i;
2352 struct drm_plane *plane;
2353 struct drm_plane_state *old_plane_state;
4fa086b9 2354 struct dc_stream *dc_stream_attach;
e12cfcb1 2355 struct dc_surface *dc_surfaces_constructed[MAX_SURFACES];
1159898a 2356 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
da5c47f6 2357 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(pcrtc->state);
0430d52b 2358 int planes_count = 0;
d7e3316c 2359 unsigned long flags;
129eed72
HW		 2360
2361 /* update planes when needed */
2362 for_each_plane_in_state(state, plane, old_plane_state, i) {
2363 struct drm_plane_state *plane_state = plane->state;
2364 struct drm_crtc *crtc = plane_state->crtc;
2365 struct drm_framebuffer *fb = plane_state->fb;
129eed72 2366 bool pflip_needed;
d7e3316c 2367 struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state);
129eed72 2368
2ea5e9a8
AG		 2369 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
2370 handle_cursor_update(plane, old_plane_state);
2371 continue;
2372 }
2373
d7e3316c
AG		 2374 if (!fb || !crtc || pcrtc != crtc || !crtc->state->active ||
2375 (!crtc->state->planes_changed &&
2376 !pcrtc->state->color_mgmt_changed))
129eed72
HW		 2377 continue;
2378
129eed72 2379 pflip_needed = !state->allow_modeset;
d7e3316c
AG		 2380
2381 spin_lock_irqsave(&crtc->dev->event_lock, flags);
2382 if (acrtc_attach->pflip_status != AMDGPU_FLIP_NONE) {
2383 DRM_ERROR("add_surface: acrtc %d, already busy\n",
2384 acrtc_attach->crtc_id);
2385 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
2386 /* In comit tail framework this cannot happen */
2387 WARN_ON(1);
2388 }
2389 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
2390
bdc79f8e 2391 if (!pflip_needed) {
d7e3316c 2392 WARN_ON(!dm_plane_state->surface);
129eed72 2393
d7e3316c 2394 dc_surfaces_constructed[planes_count] = dm_plane_state->surface;
ccaa7389 2395
da5c47f6 2396 dc_stream_attach = acrtc_state->stream;
1159898a
AG		 2397 planes_count++;
2398
bdc79f8e 2399 } else if (crtc->state->planes_changed) {
1159898a
AG		 2400 /* Assume even ONE crtc with immediate flip means
2401 * entire can't wait for VBLANK
2402 * TODO Check if it's correct
2403 */
bdc79f8e
AG		 2404 *wait_for_vblank =
2405 acrtc_attach->flip_flags & DRM_MODE_PAGE_FLIP_ASYNC ?
2406 false : true;
2407
e29088b2
LSL		 2408 /* TODO: Needs rework for multiplane flip */
2409 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
2410 drm_crtc_vblank_get(crtc);
2411
bdc79f8e
AG		 2412 amdgpu_dm_do_flip(
2413 crtc,
2414 fb,
2415 drm_crtc_vblank_count(crtc) + *wait_for_vblank);
2416
1159898a
AG		 2417 /*TODO BUG remove ASAP in 4.12 to avoid race between worker and flip IOCTL */
2418
bdc79f8e
AG		 2419 /*clean up the flags for next usage*/
2420 acrtc_attach->flip_flags = 0;
0430d52b 2421 }
bdc79f8e 2422
0430d52b 2423 }
129eed72 2424
0430d52b 2425 if (planes_count) {
1159898a
AG		 2426 unsigned long flags;
2427
2428 if (pcrtc->state->event) {
2429
2430 drm_crtc_vblank_get(pcrtc);
2431
2432 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
2433 prepare_flip_isr(acrtc_attach);
2434 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
2435 }
2436
0430d52b
S		 2437 if (false == dc_commit_surfaces_to_stream(dm->dc,
2438 dc_surfaces_constructed,
2439 planes_count,
1159898a 2440 dc_stream_attach))
0430d52b 2441 dm_error("%s: Failed to attach surface!\n", __func__);
1159898a
AG		 2442 } else {
2443 /*TODO BUG Here should go disable planes on CRTC. */
129eed72
HW		 2444 }
2445}
2446
da5c47f6
AG		 2447
2448int amdgpu_dm_atomic_commit(
2449 struct drm_device *dev,
2450 struct drm_atomic_state *state,
2451 bool nonblock)
2452{
2453 struct drm_crtc *crtc;
2454 struct drm_crtc_state *new_state;
2455 struct amdgpu_device *adev = dev->dev_private;
2456 int i;
2457
2458 /*
2459 * We evade vblanks and pflips on crtc that
2460 * should be changed. We do it here to flush & disable
2461 * interrupts before drm_swap_state is called in drm_atomic_helper_commit
2462 * it will update crtc->dm_crtc_state->stream pointer which is used in
2463 * the ISRs.
2464 */
2465 for_each_crtc_in_state(state, crtc, new_state, i) {
2466 struct dm_crtc_state *old_acrtc_state = to_dm_crtc_state(crtc->state);
2467 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2468
2469 if (drm_atomic_crtc_needs_modeset(new_state) && old_acrtc_state->stream)
2470 manage_dm_interrupts(adev, acrtc, false);
2471 }
2472
2473 return drm_atomic_helper_commit(dev, state, nonblock);
2474
2475 /*TODO Handle EINTR, reenable IRQ*/
2476}
2477
54f5499a
AG		 2478void amdgpu_dm_atomic_commit_tail(
2479 struct drm_atomic_state *state)
4562236b 2480{
54f5499a 2481 struct drm_device *dev = state->dev;
4562236b
HW		 2482 struct amdgpu_device *adev = dev->dev_private;
2483 struct amdgpu_display_manager *dm = &adev->dm;
7cf2c840 2484 struct dm_atomic_state *dm_state;
0430d52b 2485 uint32_t i, j;
4562236b 2486 uint32_t new_crtcs_count = 0;
0430d52b 2487 struct drm_crtc *crtc, *pcrtc;
4562236b 2488 struct drm_crtc_state *old_crtc_state;
ab2541b6 2489 struct amdgpu_crtc *new_crtcs[MAX_STREAMS];
4fa086b9 2490 struct dc_stream *new_stream = NULL;
54f5499a
AG		 2491 unsigned long flags;
2492 bool wait_for_vblank = true;
ccaa7389
AG		 2493 struct drm_connector *connector;
2494 struct drm_connector_state *old_conn_state;
da5c47f6 2495 struct dm_crtc_state *old_acrtc_state, *new_acrtc_state;
4562236b
HW		 2496
2497 drm_atomic_helper_update_legacy_modeset_state(dev, state);
7cf2c840
HW		 2498
2499 dm_state = to_dm_atomic_state(state);
2500
4562236b
HW		 2501 /* update changed items */
2502 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
da5c47f6 2503 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4562236b 2504 struct drm_crtc_state *new_state = crtc->state;
da5c47f6
AG		 2505 new_acrtc_state = to_dm_crtc_state(new_state);
2506 old_acrtc_state = to_dm_crtc_state(old_crtc_state);
4562236b 2507
4c92c92d
AG		 2508 DRM_DEBUG_KMS(
2509 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
2510 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
2511 "connectors_changed:%d\n",
2512 acrtc->crtc_id,
2513 new_state->enable,
2514 new_state->active,
2515 new_state->planes_changed,
2516 new_state->mode_changed,
2517 new_state->active_changed,
2518 new_state->connectors_changed);
2519
4562236b
HW		 2520 /* handles headless hotplug case, updating new_state and
2521 * aconnector as needed
2522 */
2523
4c92c92d 2524 if (modeset_required(new_state)) {
4562236b
HW		 2525
2526 DRM_INFO("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
2527
da5c47f6 2528 if (!new_acrtc_state->stream) {
4562236b 2529 /*
da5c47f6
AG		 2530 * this could happen because of issues with
2531 * userspace notifications delivery.
2532 * In this case userspace tries to set mode on
2533 * display which is disconnect in fact.
2534 * dc_sink in NULL in this case on aconnector.
2535 * We expect reset mode will come soon.
2536 *
2537 * This can also happen when unplug is done
2538 * during resume sequence ended
2539 *
2540 * In this case, we want to pretend we still
2541 * have a sink to keep the pipe running so that
2542 * hw state is consistent with the sw state
2543 */
ab2541b6 2544 DRM_DEBUG_KMS("%s: Failed to create new stream for crtc %d\n",
4562236b 2545 __func__, acrtc->base.base.id);
da5c47f6 2546 continue;
4562236b
HW		 2547 }
2548
4562236b 2549
da5c47f6
AG		 2550 if (old_acrtc_state->stream)
2551 remove_stream(adev, acrtc, old_acrtc_state->stream);
2552
e2c7bb12 2553
4562236b
HW		 2554 /*
2555 * this loop saves set mode crtcs
2556 * we needed to enable vblanks once all
ab2541b6 2557 * resources acquired in dc after dc_commit_streams
4562236b 2558 */
da5c47f6
AG		 2559
2560 /*TODO move all this into dm_crtc_state, get rid of
2561 * new_crtcs array and use old and new atomic states
2562 * instead
2563 */
4562236b
HW		 2564 new_crtcs[new_crtcs_count] = acrtc;
2565 new_crtcs_count++;
2566
4562236b
HW		 2567 acrtc->enabled = true;
2568 acrtc->hw_mode = crtc->state->mode;
2569 crtc->hwmode = crtc->state->mode;
4c92c92d 2570 } else if (modereset_required(new_state)) {
4562236b 2571 DRM_INFO("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
da5c47f6 2572
4562236b 2573 /* i.e. reset mode */
da5c47f6
AG		 2574 if (old_acrtc_state->stream)
2575 remove_stream(adev, acrtc, old_acrtc_state->stream);
4c92c92d 2576 }
4562236b
HW		 2577 } /* for_each_crtc_in_state() */
2578
4562236b 2579 /*
ab2541b6 2580 * Add streams after required streams from new and replaced streams
4562236b
HW		 2581 * are removed from freesync module
2582 */
2583 if (adev->dm.freesync_module) {
2584 for (i = 0; i < new_crtcs_count; i++) {
2585 struct amdgpu_connector *aconnector = NULL;
da5c47f6
AG		 2586 new_acrtc_state = to_dm_crtc_state(new_crtcs[i]->base.state);
2587
2588 new_stream = new_acrtc_state->stream;
4562236b
HW		 2589 aconnector =
2590 amdgpu_dm_find_first_crct_matching_connector(
2591 state,
2592 &new_crtcs[i]->base,
2593 false);
2594 if (!aconnector) {
2595 DRM_INFO(
2596 "Atomic commit: Failed to find connector for acrtc id:%d "
2597 "skipping freesync init\n",
2598 new_crtcs[i]->crtc_id);
2599 continue;
2600 }
2601
ab2541b6
AC		 2602 mod_freesync_add_stream(adev->dm.freesync_module,
2603 new_stream, &aconnector->caps);
4562236b
HW		 2604 }
2605 }
2606
3b42a1c0
AG		 2607 if (dm_state->context)
2608 WARN_ON(!dc_commit_context(dm->dc, dm_state->context));
4562236b 2609
89a1fc59 2610
4562236b
HW		 2611 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2612 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
da5c47f6 2613 new_acrtc_state = to_dm_crtc_state(crtc->state);
4562236b 2614
da5c47f6
AG		 2615 if (new_acrtc_state->stream != NULL) {
2616 const struct dc_stream_status *status =
2617 dc_stream_get_status(new_acrtc_state->stream);
e2c7bb12
HW		 2618
2619 if (!status)
da5c47f6 2620 DC_ERR("got no status for stream %p on acrtc%p\n", new_acrtc_state->stream, acrtc);
e2c7bb12
HW		 2621 else
2622 acrtc->otg_inst = status->primary_otg_inst;
2623 }
4562236b
HW		 2624 }
2625
da5c47f6
AG		 2626 /* Handle scaling and undersacn changes*/
2627 for_each_connector_in_state(state, connector, old_conn_state, i) {
2628 struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
2629 struct dm_connector_state *con_new_state =
2630 to_dm_connector_state(aconnector->base.state);
2631 struct dm_connector_state *con_old_state =
2632 to_dm_connector_state(old_conn_state);
2633 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(con_new_state->base.crtc);
e12cfcb1 2634 struct dc_stream_status *status = NULL;
da5c47f6
AG		 2635
2636 /* Skip any modesets/resets */
2637 if (!acrtc || drm_atomic_crtc_needs_modeset(acrtc->base.state))
2638 continue;
2639
2640 /* Skip any thing not scale or underscan changes */
2641 if (!is_scaling_state_different(con_new_state, con_old_state))
2642 continue;
2643
2644 new_acrtc_state = to_dm_crtc_state(acrtc->base.state);
2645
2646 update_stream_scaling_settings(&con_new_state->base.crtc->mode,
2647 con_new_state, (struct dc_stream *)new_acrtc_state->stream);
2648
2649 status = dc_stream_get_status(new_acrtc_state->stream);
2650 WARN_ON(!status);
2651 WARN_ON(!status->surface_count);
2652
2653 if (!new_acrtc_state->stream)
2654 continue;
2655
2656 /*TODO How it works with MPO ?*/
2657 if (!dc_commit_surfaces_to_stream(
2658 dm->dc,
e12cfcb1 2659 status->surfaces,
da5c47f6
AG		 2660 status->surface_count,
2661 new_acrtc_state->stream))
2662 dm_error("%s: Failed to update stream scaling!\n", __func__);
2663 }
2664
4562236b
HW		 2665 for (i = 0; i < new_crtcs_count; i++) {
2666 /*
2667 * loop to enable interrupts on newly arrived crtc
2668 */
2669 struct amdgpu_crtc *acrtc = new_crtcs[i];
da5c47f6 2670 new_acrtc_state = to_dm_crtc_state(acrtc->base.state);
4562236b 2671
ab2541b6
AC		 2672 if (adev->dm.freesync_module)
2673 mod_freesync_notify_mode_change(
da5c47f6 2674 adev->dm.freesync_module, &new_acrtc_state->stream, 1);
4562236b
HW		 2675
2676 manage_dm_interrupts(adev, acrtc, true);
4562236b
HW		 2677 }
2678
1159898a
AG		 2679 /* update planes when needed per crtc*/
2680 for_each_crtc_in_state(state, pcrtc, old_crtc_state, j) {
da5c47f6 2681 new_acrtc_state = to_dm_crtc_state(pcrtc->state);
1159898a 2682
da5c47f6 2683 if (new_acrtc_state->stream)
1159898a
AG		 2684 amdgpu_dm_commit_surfaces(state, dev, dm, pcrtc, &wait_for_vblank);
2685 }
2686
4562236b 2687
1159898a
AG		 2688 /*
2689 * send vblank event on all events not handled in flip and
2690 * mark consumed event for drm_atomic_helper_commit_hw_done
54f5499a
AG		 2691 */
2692 spin_lock_irqsave(&adev->ddev->event_lock, flags);
2693 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
2694 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2695
1159898a
AG		 2696 if (acrtc->base.state->event)
2697 drm_send_event_locked(dev, &crtc->state->event->base);
2698
2699 acrtc->base.state->event = NULL;
54f5499a
AG		 2700 }
2701 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
2702
2703 /* Signal HW programming completion */
2704 drm_atomic_helper_commit_hw_done(state);
2705
2706 if (wait_for_vblank)
2707 drm_atomic_helper_wait_for_vblanks(dev, state);
2708
54f5499a 2709 drm_atomic_helper_cleanup_planes(dev, state);
4562236b 2710}
92cc37fb
AG		 2711
2712
2713static int dm_force_atomic_commit(struct drm_connector *connector)
2714{
2715 int ret = 0;
2716 struct drm_device *ddev = connector->dev;
2717 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
2718 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
2719 struct drm_plane *plane = disconnected_acrtc->base.primary;
2720 struct drm_connector_state *conn_state;
2721 struct drm_crtc_state *crtc_state;
2722 struct drm_plane_state *plane_state;
2723
2724 if (!state)
2725 return -ENOMEM;
2726
2727 state->acquire_ctx = ddev->mode_config.acquire_ctx;
2728
2729 /* Construct an atomic state to restore previous display setting */
2730
2731 /*
2732 * Attach connectors to drm_atomic_state
2733 */
2734 conn_state = drm_atomic_get_connector_state(state, connector);
2735
2736 ret = PTR_ERR_OR_ZERO(conn_state);
2737 if (ret)
2738 goto err;
2739
2740 /* Attach crtc to drm_atomic_state*/
2741 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
2742
2743 ret = PTR_ERR_OR_ZERO(crtc_state);
2744 if (ret)
2745 goto err;
2746
2747 /* force a restore */
2748 crtc_state->mode_changed = true;
2749
2750 /* Attach plane to drm_atomic_state */
2751 plane_state = drm_atomic_get_plane_state(state, plane);
2752
2753 ret = PTR_ERR_OR_ZERO(plane_state);
2754 if (ret)
2755 goto err;
2756
2757
2758 /* Call commit internally with the state we just constructed */
2759 ret = drm_atomic_commit(state);
2760 if (!ret)
2761 return 0;
2762
2763err:
2764 DRM_ERROR("Restoring old state failed with %i\n", ret);
2765 drm_atomic_state_put(state);
2766
2767 return ret;
2768}
2769
4562236b
HW		 2770/*
2771 * This functions handle all cases when set mode does not come upon hotplug.
2772 * This include when the same display is unplugged then plugged back into the
2773 * same port and when we are running without usermode desktop manager supprot
2774 */
2775void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector *connector)
2776{
4562236b
HW		 2777 struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
2778 struct amdgpu_crtc *disconnected_acrtc;
da5c47f6 2779 struct dm_crtc_state *acrtc_state;
4562236b
HW		 2780
2781 if (!aconnector->dc_sink || !connector->state || !connector->encoder)
2782 return;
2783
2784 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
da5c47f6 2785 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
4562236b 2786
da5c47f6 2787 if (!disconnected_acrtc || !acrtc_state->stream)
4562236b
HW		 2788 return;
2789
4562236b
HW		 2790 /*
2791 * If the previous sink is not released and different from the current,
2792 * we deduce we are in a state where we can not rely on usermode call
2793 * to turn on the display, so we do it here
2794 */
da5c47f6 2795 if (acrtc_state->stream->sink != aconnector->dc_sink)
92cc37fb 2796 dm_force_atomic_commit(&aconnector->base);
4562236b
HW		 2797}
2798
2799static uint32_t add_val_sets_surface(
2800 struct dc_validation_set *val_sets,
2801 uint32_t set_count,
ab2541b6 2802 const struct dc_stream *stream,
e12cfcb1 2803 struct dc_surface *surface)
4562236b 2804{
0430d52b 2805 uint32_t i = 0, j = 0;
4562236b
HW		 2806
2807 while (i < set_count) {
0430d52b
S		 2808 if (val_sets[i].stream == stream) {
2809 while (val_sets[i].surfaces[j])
2810 j++;
4562236b 2811 break;
0430d52b 2812 }
4562236b
HW		 2813 ++i;
2814 }
2815
0430d52b 2816 val_sets[i].surfaces[j] = surface;
4562236b
HW		 2817 val_sets[i].surface_count++;
2818
2819 return val_sets[i].surface_count;
2820}
2821
ab2541b6 2822static uint32_t update_in_val_sets_stream(
4562236b 2823 struct dc_validation_set *val_sets,
4562236b 2824 uint32_t set_count,
4fa086b9
LSL		 2825 struct dc_stream *old_stream,
2826 struct dc_stream *new_stream,
4562236b
HW		 2827 struct drm_crtc *crtc)
2828{
2829 uint32_t i = 0;
2830
2831 while (i < set_count) {
ab2541b6 2832 if (val_sets[i].stream == old_stream)
4562236b
HW		 2833 break;
2834 ++i;
2835 }
2836
ab2541b6 2837 val_sets[i].stream = new_stream;
4562236b 2838
da5c47f6 2839 if (i == set_count)
4562236b
HW		 2840 /* nothing found. add new one to the end */
2841 return set_count + 1;
4562236b
HW		 2842
2843 return set_count;
2844}
2845
2846static uint32_t remove_from_val_sets(
2847 struct dc_validation_set *val_sets,
2848 uint32_t set_count,
ab2541b6 2849 const struct dc_stream *stream)
4562236b
HW		 2850{
2851 int i;
2852
2853 for (i = 0; i < set_count; i++)
ab2541b6 2854 if (val_sets[i].stream == stream)
4562236b
HW		 2855 break;
2856
2857 if (i == set_count) {
2858 /* nothing found */
2859 return set_count;
2860 }
2861
2862 set_count--;
2863
2864 for (; i < set_count; i++) {
2865 val_sets[i] = val_sets[i + 1];
2866 }
2867
2868 return set_count;
2869}
2870
03c8a5fe
AG		 2871/*`
2872 * Grabs all modesetting locks to serialize against any blocking commits,
2873 * Waits for completion of all non blocking commits.
2874 */
f0129a53 2875static int do_aquire_global_lock(
03c8a5fe
AG		 2876 struct drm_device *dev,
2877 struct drm_atomic_state *state)
2878{
2879 struct drm_crtc *crtc;
2880 struct drm_crtc_commit *commit;
2881 long ret;
2882
2883 /* Adding all modeset locks to aquire_ctx will
2884 * ensure that when the framework release it the
2885 * extra locks we are locking here will get released to
2886 */
f0129a53
AG		 2887 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
2888 if (ret)
2889 return ret;
03c8a5fe
AG		 2890
2891 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2892 spin_lock(&crtc->commit_lock);
2893 commit = list_first_entry_or_null(&crtc->commit_list,
2894 struct drm_crtc_commit, commit_entry);
2895 if (commit)
2896 drm_crtc_commit_get(commit);
2897 spin_unlock(&crtc->commit_lock);
2898
2899 if (!commit)
2900 continue;
2901
2902 /* Make sure all pending HW programming completed and
2903 * page flips done
2904 */
f0129a53
AG		 2905 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
2906
2907 if (ret > 0)
2908 ret = wait_for_completion_interruptible_timeout(
2909 &commit->flip_done, 10*HZ);
2910
03c8a5fe 2911 if (ret == 0)
4c0732bf 2912 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
f0129a53
AG		 2913 "timed out\n", crtc->base.id, crtc->name);
2914
03c8a5fe
AG		 2915 drm_crtc_commit_put(commit);
2916 }
f0129a53
AG		 2917
2918 return ret < 0 ? ret : 0;
03c8a5fe
AG		 2919}
2920
4562236b
HW		 2921int amdgpu_dm_atomic_check(struct drm_device *dev,
2922 struct drm_atomic_state *state)
2923{
a6818a32 2924 struct dm_atomic_state *dm_state;
4562236b
HW		 2925 struct drm_crtc *crtc;
2926 struct drm_crtc_state *crtc_state;
2927 struct drm_plane *plane;
2928 struct drm_plane_state *plane_state;
2929 int i, j;
2930 int ret;
4562236b
HW		 2931 struct amdgpu_device *adev = dev->dev_private;
2932 struct dc *dc = adev->dm.dc;
ccaa7389
AG		 2933 struct drm_connector *connector;
2934 struct drm_connector_state *conn_state;
da5c47f6
AG		 2935 int set_count;
2936 struct dc_validation_set set[MAX_STREAMS] = { { 0 } };
2937 struct dm_crtc_state *old_acrtc_state, *new_acrtc_state;
2938
bdc79f8e
AG		 2939 /*
2940 * This bool will be set for true for any modeset/reset
3b42a1c0 2941 * or surface update which implies non fast surface update.
bdc79f8e 2942 */
3b42a1c0 2943 bool lock_and_validation_needed = false;
4562236b 2944
4017fcdf 2945 ret = drm_atomic_helper_check_modeset(dev, state);
4562236b
HW		 2946
2947 if (ret) {
d7e3316c 2948 DRM_ERROR("Atomic state validation failed with error :%d !\n", ret);
4562236b
HW		 2949 return ret;
2950 }
2951
a6818a32
HW		 2952 dm_state = to_dm_atomic_state(state);
2953
4562236b 2954 /* copy existing configuration */
da5c47f6 2955 set_count = 0;
4562236b
HW		 2956 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2957
da5c47f6 2958 old_acrtc_state = to_dm_crtc_state(crtc->state);
4562236b 2959
da5c47f6
AG		 2960 if (old_acrtc_state->stream) {
2961 dc_stream_retain(old_acrtc_state->stream);
2962 set[set_count].stream = old_acrtc_state->stream;
da5c47f6 2963 ++set_count;
4562236b
HW		 2964 }
2965 }
2966
4017fcdf 2967 /*TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set */
4562236b
HW		 2968 /* update changed items */
2969 for_each_crtc_in_state(state, crtc, crtc_state, i) {
2970 struct amdgpu_crtc *acrtc = NULL;
2971 struct amdgpu_connector *aconnector = NULL;
da5c47f6
AG		 2972 old_acrtc_state = to_dm_crtc_state(crtc->state);
2973 new_acrtc_state = to_dm_crtc_state(crtc_state);
4562236b
HW		 2974 acrtc = to_amdgpu_crtc(crtc);
2975
2976 aconnector = amdgpu_dm_find_first_crct_matching_connector(state, crtc, true);
2977
4c92c92d
AG		 2978 DRM_DEBUG_KMS(
2979 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
2980 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
2981 "connectors_changed:%d\n",
2982 acrtc->crtc_id,
2983 crtc_state->enable,
2984 crtc_state->active,
2985 crtc_state->planes_changed,
2986 crtc_state->mode_changed,
2987 crtc_state->active_changed,
2988 crtc_state->connectors_changed);
2989
2990 if (modeset_required(crtc_state)) {
4562236b 2991
ab2541b6 2992 struct dc_stream *new_stream = NULL;
4562236b 2993 struct drm_connector_state *conn_state = NULL;
a6818a32 2994 struct dm_connector_state *dm_conn_state = NULL;
4562236b
HW		 2995
2996 if (aconnector) {
2997 conn_state = drm_atomic_get_connector_state(state, &aconnector->base);
d7e3316c
AG		 2998 if (IS_ERR(conn_state)) {
2999 ret = PTR_ERR_OR_ZERO(conn_state);
eb78d83e 3000 goto fail;
d7e3316c
AG		 3001 }
3002
a6818a32 3003 dm_conn_state = to_dm_connector_state(conn_state);
4562236b
HW		 3004 }
3005
a6818a32 3006 new_stream = create_stream_for_sink(aconnector, &crtc_state->mode, dm_conn_state);
4562236b
HW		 3007
3008 /*
ab2541b6 3009 * we can have no stream on ACTION_SET if a display
4562236b
HW		 3010 * was disconnected during S3, in this case it not and
3011 * error, the OS will be updated after detection, and
3012 * do the right thing on next atomic commit
3013 */
ab2541b6
AC		 3014 if (!new_stream) {
3015 DRM_DEBUG_KMS("%s: Failed to create new stream for crtc %d\n",
4562236b
HW		 3016 __func__, acrtc->base.base.id);
3017 break;
3018 }
3019
da5c47f6
AG		 3020 if (new_acrtc_state->stream)
3021 dc_stream_release(new_acrtc_state->stream);
d7e3316c 3022
da5c47f6
AG		 3023 new_acrtc_state->stream = new_stream;
3024
3025 set_count = update_in_val_sets_stream(
3026 set,
da5c47f6
AG		 3027 set_count,
3028 old_acrtc_state->stream,
3029 new_acrtc_state->stream,
4562236b
HW		 3030 crtc);
3031
3b42a1c0 3032 lock_and_validation_needed = true;
4562236b 3033
4c92c92d
AG		 3034 } else if (modereset_required(crtc_state)) {
3035
4562236b 3036 /* i.e. reset mode */
da5c47f6
AG		 3037 if (new_acrtc_state->stream) {
3038 set_count = remove_from_val_sets(
3039 set,
3040 set_count,
3041 new_acrtc_state->stream);
3042
3043 dc_stream_release(new_acrtc_state->stream);
3044 new_acrtc_state->stream = NULL;
3045
3b42a1c0 3046 lock_and_validation_needed = true;
4562236b 3047 }
4562236b
HW		 3048 }
3049
2ea5e9a8 3050
4562236b 3051 /*
2ea5e9a8
AG		 3052 * Hack: Commit needs planes right now, specifically for gamma
3053 * TODO rework commit to check CRTC for gamma change
4562236b 3054 */
2ea5e9a8 3055 if (crtc_state->color_mgmt_changed) {
4562236b 3056
2ea5e9a8
AG		 3057 ret = drm_atomic_add_affected_planes(state, crtc);
3058 if (ret)
eb78d83e 3059 goto fail;
2ea5e9a8 3060 }
4562236b
HW		 3061 }
3062
ccaa7389 3063 /* Check scaling and undersacn changes*/
da5c47f6
AG		 3064 /*TODO Removed scaling changes validation due to inability to commit
3065 * new stream into context w\o causing full reset. Need to
3066 * decide how to handle.
3067 */
ccaa7389
AG		 3068 for_each_connector_in_state(state, connector, conn_state, i) {
3069 struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
3070 struct dm_connector_state *con_old_state =
3071 to_dm_connector_state(aconnector->base.state);
3072 struct dm_connector_state *con_new_state =
3073 to_dm_connector_state(conn_state);
3074 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(con_new_state->base.crtc);
ccaa7389
AG		 3075
3076 /* Skip any modesets/resets */
4c92c92d 3077 if (!acrtc || drm_atomic_crtc_needs_modeset(acrtc->base.state))
ccaa7389
AG		 3078 continue;
3079
3080 /* Skip any thing not scale or underscan chnages */
3081 if (!is_scaling_state_different(con_new_state, con_old_state))
3082 continue;
3083
3b42a1c0 3084 lock_and_validation_needed = true;
ccaa7389
AG		 3085 }
3086
d7e3316c
AG		 3087 for_each_crtc_in_state(state, crtc, crtc_state, i) {
3088 new_acrtc_state = to_dm_crtc_state(crtc_state);
3089
4562236b 3090 for_each_plane_in_state(state, plane, plane_state, j) {
d7e3316c 3091 struct drm_crtc *plane_crtc = plane_state->crtc;
4562236b 3092 struct drm_framebuffer *fb = plane_state->fb;
54f5499a 3093 bool pflip_needed;
d7e3316c 3094 struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state);
4562236b 3095
2ea5e9a8
AG		 3096 /*TODO Implement atomic check for cursor plane */
3097 if (plane->type == DRM_PLANE_TYPE_CURSOR)
3098 continue;
4562236b 3099
4017fcdf 3100 if (!fb || !plane_crtc || crtc != plane_crtc || !crtc_state->active)
4562236b
HW		 3101 continue;
3102
d7e3316c 3103 WARN_ON(!new_acrtc_state->stream);
4562236b 3104
2d60ded1 3105 pflip_needed = !state->allow_modeset;
83dc2117 3106 if (!pflip_needed) {
4562236b
HW		 3107 struct dc_surface *surface;
3108
4562236b 3109 surface = dc_create_surface(dc);
d7e3316c
AG		 3110
3111 ret = fill_plane_attributes(
3112 plane_crtc->dev->dev_private,
4562236b
HW		 3113 surface,
3114 plane_state,
d7e3316c 3115 crtc_state,
4562236b 3116 false);
d7e3316c 3117 if (ret)
eb78d83e 3118 goto fail;
d7e3316c
AG		 3119
3120
3121 if (dm_plane_state->surface)
3122 dc_surface_release(dm_plane_state->surface);
3123
3124 dm_plane_state->surface = surface;
4562236b 3125
da5c47f6
AG		 3126 add_val_sets_surface(set,
3127 set_count,
d7e3316c 3128 new_acrtc_state->stream,
a6818a32 3129 surface);
4562236b 3130
3b42a1c0 3131 lock_and_validation_needed = true;
4562236b
HW		 3132 }
3133 }
3134 }
3135
4017fcdf
AG		 3136 /* Run this here since we want to validate the streams we created */
3137 ret = drm_atomic_helper_check_planes(dev, state);
3138 if (ret)
3139 goto fail;
3140
d7e3316c
AG		 3141 /*
3142 * For full updates case when
3143 * removing/adding/updating streams on once CRTC while flipping
3144 * on another CRTC,
3145 * acquiring global lock will guarantee that any such full
3146 * update commit
3147 * will wait for completion of any outstanding flip using DRMs
3148 * synchronization events.
da5c47f6 3149 */
3b42a1c0
AG		 3150
3151 if (lock_and_validation_needed) {
3152
d7e3316c
AG		 3153 ret = do_aquire_global_lock(dev, state);
3154 if (ret)
eb78d83e 3155 goto fail;
0a323b84 3156 WARN_ON(dm_state->context);
3b42a1c0
AG		 3157 dm_state->context = dc_get_validate_context(dc, set, set_count);
3158 if (!dm_state->context) {
3159 ret = -EINVAL;
eb78d83e 3160 goto fail;
3b42a1c0 3161 }
d7e3316c
AG		 3162 }
3163
3164 /* Must be success */
3165 WARN_ON(ret);
3166 return ret;
3167
eb78d83e 3168fail:
d7e3316c
AG		 3169 if (ret == -EDEADLK)
3170 DRM_DEBUG_KMS("Atomic check stopped due to to deadlock.\n");
3171 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
3172 DRM_DEBUG_KMS("Atomic check stopped due to to signal.\n");
3173 else
3174 DRM_ERROR("Atomic check failed with err: %d .\n", ret);
4562236b
HW		 3175
3176 return ret;
3177}
3178
3179static bool is_dp_capable_without_timing_msa(
3180 struct dc *dc,
3181 struct amdgpu_connector *amdgpu_connector)
3182{
3183 uint8_t dpcd_data;
3184 bool capable = false;
209a885b 3185
4562236b 3186 if (amdgpu_connector->dc_link &&
209a885b
JL		 3187 dm_helpers_dp_read_dpcd(
3188 NULL,
3189 amdgpu_connector->dc_link,
3190 DP_DOWN_STREAM_PORT_COUNT,
3191 &dpcd_data,
3192 sizeof(dpcd_data))) {
d7194cf6 3193 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
209a885b 3194 }
4562236b
HW		 3195
3196 return capable;
3197}
3198void amdgpu_dm_add_sink_to_freesync_module(
3199 struct drm_connector *connector,
3200 struct edid *edid)
3201{
3202 int i;
3203 uint64_t val_capable;
3204 bool edid_check_required;
3205 struct detailed_timing *timing;
3206 struct detailed_non_pixel *data;
3207 struct detailed_data_monitor_range *range;
3208 struct amdgpu_connector *amdgpu_connector =
3209 to_amdgpu_connector(connector);
3210
3211 struct drm_device *dev = connector->dev;
3212 struct amdgpu_device *adev = dev->dev_private;
3213 edid_check_required = false;
3214 if (!amdgpu_connector->dc_sink) {
3215 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
3216 return;
3217 }
3218 if (!adev->dm.freesync_module)
3219 return;
3220 /*
3221 * if edid non zero restrict freesync only for dp and edp
3222 */
3223 if (edid) {
3224 if (amdgpu_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
3225 || amdgpu_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
3226 edid_check_required = is_dp_capable_without_timing_msa(
3227 adev->dm.dc,
3228 amdgpu_connector);
3229 }
3230 }
3231 val_capable = 0;
3232 if (edid_check_required == true && (edid->version > 1 ||
3233 (edid->version == 1 && edid->revision > 1))) {
3234 for (i = 0; i < 4; i++) {
3235
3236 timing = &edid->detailed_timings[i];
3237 data = &timing->data.other_data;
3238 range = &data->data.range;
3239 /*
3240 * Check if monitor has continuous frequency mode
3241 */
3242 if (data->type != EDID_DETAIL_MONITOR_RANGE)
3243 continue;
3244 /*
3245 * Check for flag range limits only. If flag == 1 then
3246 * no additional timing information provided.
3247 * Default GTF, GTF Secondary curve and CVT are not
3248 * supported
3249 */
3250 if (range->flags != 1)
3251 continue;
3252
3253 amdgpu_connector->min_vfreq = range->min_vfreq;
3254 amdgpu_connector->max_vfreq = range->max_vfreq;
3255 amdgpu_connector->pixel_clock_mhz =
3256 range->pixel_clock_mhz * 10;
3257 break;
3258 }
3259
3260 if (amdgpu_connector->max_vfreq -
3261 amdgpu_connector->min_vfreq > 10) {
3262 amdgpu_connector->caps.supported = true;
3263 amdgpu_connector->caps.min_refresh_in_micro_hz =
3264 amdgpu_connector->min_vfreq * 1000000;
3265 amdgpu_connector->caps.max_refresh_in_micro_hz =
3266 amdgpu_connector->max_vfreq * 1000000;
3267 val_capable = 1;
3268 }
3269 }
3270
3271 /*
3272 * TODO figure out how to notify user-mode or DRM of freesync caps
3273 * once we figure out how to deal with freesync in an upstreamable
3274 * fashion
3275 */
3276
3277}
3278
3279void amdgpu_dm_remove_sink_from_freesync_module(
3280 struct drm_connector *connector)
3281{
3282 /*
3283 * TODO fill in once we figure out how to deal with freesync in
3284 * an upstreamable fashion
3285 */
3286}
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