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drm/amd/display: Roll sink struct into core_sink
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / display / amdgpu_dm / amdgpu_dm_types.c
CommitLineData
4562236b
HW		 1/*
2 * Copyright 2012-13 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include <linux/types.h>
27#include <linux/version.h>
28
29#include <drm/drmP.h>
30#include <drm/drm_atomic_helper.h>
31#include <drm/drm_fb_helper.h>
32#include <drm/drm_atomic.h>
33#include <drm/drm_edid.h>
34
209a885b 35
4562236b
HW		 36#include "amdgpu.h"
37#include "amdgpu_pm.h"
209a885b 38#include "dm_helpers.h"
4562236b
HW		 39#include "dm_services_types.h"
40
41// We need to #undef FRAME_SIZE and DEPRECATED because they conflict
42// with ptrace-abi.h's #define's of them.
43#undef FRAME_SIZE
44#undef DEPRECATED
45
46#include "dc.h"
47
48#include "amdgpu_dm_types.h"
49#include "amdgpu_dm_mst_types.h"
50
51#include "modules/inc/mod_freesync.h"
52
46df790c
AG		 53#include "i2caux_interface.h"
54
4562236b
HW		 55struct dm_connector_state {
56 struct drm_connector_state base;
57
58 enum amdgpu_rmx_type scaling;
59 uint8_t underscan_vborder;
60 uint8_t underscan_hborder;
61 bool underscan_enable;
62};
63
64#define to_dm_connector_state(x)\
65 container_of((x), struct dm_connector_state, base)
66
67
68void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
69{
70 drm_encoder_cleanup(encoder);
71 kfree(encoder);
72}
73
74static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
75 .destroy = amdgpu_dm_encoder_destroy,
76};
77
78static void dm_set_cursor(
79 struct amdgpu_crtc *amdgpu_crtc,
80 uint64_t gpu_addr,
81 uint32_t width,
82 uint32_t height)
83{
84 struct dc_cursor_attributes attributes;
cf388c0d
AN		 85 struct dc_cursor_position position;
86 struct drm_crtc *crtc = &amdgpu_crtc->base;
87 int x, y;
88 int xorigin = 0, yorigin = 0;
da5c47f6 89 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
cf388c0d 90
4562236b
HW		 91 amdgpu_crtc->cursor_width = width;
92 amdgpu_crtc->cursor_height = height;
93
94 attributes.address.high_part = upper_32_bits(gpu_addr);
95 attributes.address.low_part = lower_32_bits(gpu_addr);
96 attributes.width = width;
97 attributes.height = height;
4562236b
HW		 98 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
99 attributes.rotation_angle = 0;
100 attributes.attribute_flags.value = 0;
101
0702a01f
AG		 102 attributes.pitch = attributes.width;
103
cf388c0d
AN		 104 x = amdgpu_crtc->cursor_x;
105 y = amdgpu_crtc->cursor_y;
106
107 /* avivo cursor are offset into the total surface */
108 x += crtc->primary->state->src_x >> 16;
109 y += crtc->primary->state->src_y >> 16;
110
111 if (x < 0) {
112 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
113 x = 0;
114 }
115 if (y < 0) {
116 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
117 y = 0;
118 }
119
120 position.enable = true;
121 position.x = x;
122 position.y = y;
123
cf388c0d
AN		 124 position.x_hotspot = xorigin;
125 position.y_hotspot = yorigin;
126
ab2541b6 127 if (!dc_stream_set_cursor_attributes(
da5c47f6 128 acrtc_state->stream,
4562236b
HW		 129 &attributes)) {
130 DRM_ERROR("DC failed to set cursor attributes\n");
131 }
cf388c0d 132
ab2541b6 133 if (!dc_stream_set_cursor_position(
da5c47f6 134 acrtc_state->stream,
cf388c0d
AN		 135 &position)) {
136 DRM_ERROR("DC failed to set cursor position\n");
137 }
4562236b
HW		 138}
139
4562236b
HW		 140static int dm_crtc_cursor_set(
141 struct drm_crtc *crtc,
2ea5e9a8 142 uint64_t address,
4562236b
HW		 143 uint32_t width,
144 uint32_t height)
145{
4562236b 146 struct dc_cursor_position position;
da5c47f6 147 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
4562236b
HW		 148
149 int ret;
150
151 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
4562236b 152 ret = EINVAL;
4562236b
HW		 153
154 DRM_DEBUG_KMS(
2ea5e9a8 155 "%s: crtc_id=%d with size %d to %d \n",
4562236b
HW		 156 __func__,
157 amdgpu_crtc->crtc_id,
4562236b 158 width,
2ea5e9a8 159 height);
4562236b 160
2ea5e9a8 161 if (!address) {
4562236b
HW		 162 /* turn off cursor */
163 position.enable = false;
164 position.x = 0;
165 position.y = 0;
4562236b 166
da5c47f6 167 if (acrtc_state->stream) {
4562236b 168 /*set cursor visible false*/
ab2541b6 169 dc_stream_set_cursor_position(
da5c47f6 170 acrtc_state->stream,
4562236b
HW		 171 &position);
172 }
4562236b
HW		 173 goto release;
174
175 }
176
177 if ((width > amdgpu_crtc->max_cursor_width) ||
178 (height > amdgpu_crtc->max_cursor_height)) {
179 DRM_ERROR(
180 "%s: bad cursor width or height %d x %d\n",
181 __func__,
182 width,
183 height);
184 goto release;
185 }
4562236b
HW		 186
187 /*program new cursor bo to hardware*/
2ea5e9a8 188 dm_set_cursor(amdgpu_crtc, address, width, height);
4562236b
HW		 189
190release:
191 return ret;
192
193}
194
195static int dm_crtc_cursor_move(struct drm_crtc *crtc,
196 int x, int y)
197{
198 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
199 int xorigin = 0, yorigin = 0;
200 struct dc_cursor_position position;
da5c47f6 201 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
4562236b 202
cf388c0d
AN		 203 amdgpu_crtc->cursor_x = x;
204 amdgpu_crtc->cursor_y = y;
205
4562236b
HW		 206 /* avivo cursor are offset into the total surface */
207 x += crtc->primary->state->src_x >> 16;
208 y += crtc->primary->state->src_y >> 16;
209
210 /*
211 * TODO: for cursor debugging unguard the following
212 */
213#if 0
214 DRM_DEBUG_KMS(
215 "%s: x %d y %d c->x %d c->y %d\n",
216 __func__,
217 x,
218 y,
219 crtc->x,
220 crtc->y);
221#endif
222
223 if (x < 0) {
224 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
225 x = 0;
226 }
227 if (y < 0) {
228 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
229 y = 0;
230 }
231
232 position.enable = true;
233 position.x = x;
234 position.y = y;
235
4562236b
HW		 236 position.x_hotspot = xorigin;
237 position.y_hotspot = yorigin;
238
da5c47f6 239 if (acrtc_state->stream) {
ab2541b6 240 if (!dc_stream_set_cursor_position(
da5c47f6 241 acrtc_state->stream,
4562236b
HW		 242 &position)) {
243 DRM_ERROR("DC failed to set cursor position\n");
244 return -EINVAL;
245 }
246 }
247
248 return 0;
249}
250
4562236b
HW		 251static bool fill_rects_from_plane_state(
252 const struct drm_plane_state *state,
253 struct dc_surface *surface)
254{
255 surface->src_rect.x = state->src_x >> 16;
256 surface->src_rect.y = state->src_y >> 16;
257 /*we ignore for now mantissa and do not to deal with floating pixels :(*/
258 surface->src_rect.width = state->src_w >> 16;
259
260 if (surface->src_rect.width == 0)
261 return false;
262
263 surface->src_rect.height = state->src_h >> 16;
264 if (surface->src_rect.height == 0)
265 return false;
266
267 surface->dst_rect.x = state->crtc_x;
268 surface->dst_rect.y = state->crtc_y;
269
270 if (state->crtc_w == 0)
271 return false;
272
273 surface->dst_rect.width = state->crtc_w;
274
275 if (state->crtc_h == 0)
276 return false;
277
278 surface->dst_rect.height = state->crtc_h;
279
280 surface->clip_rect = surface->dst_rect;
281
282 switch (state->rotation & DRM_MODE_ROTATE_MASK) {
283 case DRM_MODE_ROTATE_0:
284 surface->rotation = ROTATION_ANGLE_0;
285 break;
286 case DRM_MODE_ROTATE_90:
287 surface->rotation = ROTATION_ANGLE_90;
288 break;
289 case DRM_MODE_ROTATE_180:
290 surface->rotation = ROTATION_ANGLE_180;
291 break;
292 case DRM_MODE_ROTATE_270:
293 surface->rotation = ROTATION_ANGLE_270;
294 break;
295 default:
296 surface->rotation = ROTATION_ANGLE_0;
297 break;
298 }
299
300 return true;
301}
d7e3316c 302static int get_fb_info(
4562236b
HW		 303 const struct amdgpu_framebuffer *amdgpu_fb,
304 uint64_t *tiling_flags,
305 uint64_t *fb_location)
306{
307 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
308 int r = amdgpu_bo_reserve(rbo, false);
d7e3316c 309 if (unlikely(r)) {
4562236b 310 DRM_ERROR("Unable to reserve buffer\n");
d7e3316c 311 return r;
4562236b
HW		 312 }
313
314 if (fb_location)
315 *fb_location = amdgpu_bo_gpu_offset(rbo);
316
317 if (tiling_flags)
318 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
319
320 amdgpu_bo_unreserve(rbo);
321
d7e3316c 322 return r;
4562236b 323}
d7e3316c
AG		 324
325static int fill_plane_attributes_from_fb(
6a1f8cab 326 struct amdgpu_device *adev,
4562236b
HW		 327 struct dc_surface *surface,
328 const struct amdgpu_framebuffer *amdgpu_fb, bool addReq)
329{
330 uint64_t tiling_flags;
331 uint64_t fb_location = 0;
f0c16087 332 unsigned int awidth;
4562236b 333 const struct drm_framebuffer *fb = &amdgpu_fb->base;
d7e3316c 334 int ret = 0;
4562236b
HW		 335 struct drm_format_name_buf format_name;
336
d7e3316c 337 ret = get_fb_info(
4562236b
HW		 338 amdgpu_fb,
339 &tiling_flags,
340 addReq == true ? &fb_location:NULL);
341
d7e3316c
AG		 342 if (ret)
343 return ret;
4562236b
HW		 344
345 switch (fb->format->format) {
346 case DRM_FORMAT_C8:
347 surface->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
348 break;
349 case DRM_FORMAT_RGB565:
350 surface->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
351 break;
352 case DRM_FORMAT_XRGB8888:
353 case DRM_FORMAT_ARGB8888:
354 surface->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
355 break;
356 case DRM_FORMAT_XRGB2101010:
357 case DRM_FORMAT_ARGB2101010:
358 surface->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
359 break;
360 case DRM_FORMAT_XBGR2101010:
361 case DRM_FORMAT_ABGR2101010:
362 surface->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
363 break;
f0c16087 364 case DRM_FORMAT_NV21:
e6fbd5df
S		 365 surface->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
366 break;
f0c16087 367 case DRM_FORMAT_NV12:
e6fbd5df
S		 368 surface->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
369 break;
4562236b
HW		 370 default:
371 DRM_ERROR("Unsupported screen format %s\n",
372 drm_get_format_name(fb->format->format, &format_name));
d7e3316c 373 return -EINVAL;
4562236b
HW		 374 }
375
e6fbd5df
S		 376 if (surface->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
377 surface->address.type = PLN_ADDR_TYPE_GRAPHICS;
378 surface->address.grph.addr.low_part = lower_32_bits(fb_location);
379 surface->address.grph.addr.high_part = upper_32_bits(fb_location);
380 surface->plane_size.grph.surface_size.x = 0;
381 surface->plane_size.grph.surface_size.y = 0;
382 surface->plane_size.grph.surface_size.width = fb->width;
383 surface->plane_size.grph.surface_size.height = fb->height;
384 surface->plane_size.grph.surface_pitch =
385 fb->pitches[0] / fb->format->cpp[0];
386 /* TODO: unhardcode */
387 surface->color_space = COLOR_SPACE_SRGB;
388
389 } else {
f0c16087 390 awidth = ALIGN(fb->width, 64);
e6fbd5df
S		 391 surface->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
392 surface->address.video_progressive.luma_addr.low_part
393 = lower_32_bits(fb_location);
110ff543
S		 394 surface->address.video_progressive.chroma_addr.low_part
395 = lower_32_bits(fb_location) +
f0c16087 396 (awidth * fb->height);
e6fbd5df
S		 397 surface->plane_size.video.luma_size.x = 0;
398 surface->plane_size.video.luma_size.y = 0;
f0c16087 399 surface->plane_size.video.luma_size.width = awidth;
e6fbd5df
S		 400 surface->plane_size.video.luma_size.height = fb->height;
401 /* TODO: unhardcode */
f0c16087 402 surface->plane_size.video.luma_pitch = awidth;
e6fbd5df
S		 403
404 surface->plane_size.video.chroma_size.x = 0;
405 surface->plane_size.video.chroma_size.y = 0;
f0c16087
S		 406 surface->plane_size.video.chroma_size.width = awidth;
407 surface->plane_size.video.chroma_size.height = fb->height;
408 surface->plane_size.video.chroma_pitch = awidth / 2;
e6fbd5df
S		 409
410 /* TODO: unhardcode */
411 surface->color_space = COLOR_SPACE_YCBCR709;
412 }
413
4562236b
HW		 414 memset(&surface->tiling_info, 0, sizeof(surface->tiling_info));
415
2c8ad2d5 416 /* Fill GFX params */
4562236b
HW		 417 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1)
418 {
419 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
420
421 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
422 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
423 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
424 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
425 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
426
427 /* XXX fix me for VI */
428 surface->tiling_info.gfx8.num_banks = num_banks;
429 surface->tiling_info.gfx8.array_mode =
430 DC_ARRAY_2D_TILED_THIN1;
431 surface->tiling_info.gfx8.tile_split = tile_split;
432 surface->tiling_info.gfx8.bank_width = bankw;
433 surface->tiling_info.gfx8.bank_height = bankh;
434 surface->tiling_info.gfx8.tile_aspect = mtaspect;
435 surface->tiling_info.gfx8.tile_mode =
436 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
437 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
438 == DC_ARRAY_1D_TILED_THIN1) {
439 surface->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
440 }
441
442 surface->tiling_info.gfx8.pipe_config =
443 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
444
ff5ef992
AD		 445 if (adev->asic_type == CHIP_VEGA10 ||
446 adev->asic_type == CHIP_RAVEN) {
2c8ad2d5
AD		 447 /* Fill GFX9 params */
448 surface->tiling_info.gfx9.num_pipes =
449 adev->gfx.config.gb_addr_config_fields.num_pipes;
450 surface->tiling_info.gfx9.num_banks =
451 adev->gfx.config.gb_addr_config_fields.num_banks;
452 surface->tiling_info.gfx9.pipe_interleave =
453 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
454 surface->tiling_info.gfx9.num_shader_engines =
455 adev->gfx.config.gb_addr_config_fields.num_se;
456 surface->tiling_info.gfx9.max_compressed_frags =
457 adev->gfx.config.gb_addr_config_fields.max_compress_frags;
d092bf65
AG		 458 surface->tiling_info.gfx9.num_rb_per_se =
459 adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
2c8ad2d5
AD		 460 surface->tiling_info.gfx9.swizzle =
461 AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
462 surface->tiling_info.gfx9.shaderEnable = 1;
463 }
2c8ad2d5 464
4562236b
HW		 465 surface->visible = true;
466 surface->scaling_quality.h_taps_c = 0;
467 surface->scaling_quality.v_taps_c = 0;
468
4562236b
HW		 469 /* is this needed? is surface zeroed at allocation? */
470 surface->scaling_quality.h_taps = 0;
471 surface->scaling_quality.v_taps = 0;
472 surface->stereo_format = PLANE_STEREO_FORMAT_NONE;
473
d7e3316c
AG		 474 return ret;
475
4562236b
HW		 476}
477
478#define NUM_OF_RAW_GAMMA_RAMP_RGB_256 256
479
d7e3316c
AG		 480static void fill_gamma_from_crtc_state(
481 const struct drm_crtc_state *crtc_state,
4562236b
HW		 482 struct dc_surface *dc_surface)
483{
484 int i;
485 struct dc_gamma *gamma;
d7e3316c 486 struct drm_color_lut *lut = (struct drm_color_lut *) crtc_state->gamma_lut->data;
4562236b
HW		 487
488 gamma = dc_create_gamma();
489
d7e3316c
AG		 490 if (gamma == NULL) {
491 WARN_ON(1);
4562236b 492 return;
d7e3316c 493 }
4562236b
HW		 494
495 for (i = 0; i < NUM_OF_RAW_GAMMA_RAMP_RGB_256; i++) {
d7194cf6
AC		 496 gamma->red[i] = lut[i].red;
497 gamma->green[i] = lut[i].green;
498 gamma->blue[i] = lut[i].blue;
4562236b
HW		 499 }
500
4562236b
HW		 501 dc_surface->gamma_correction = gamma;
502}
503
d7e3316c 504static int fill_plane_attributes(
6a1f8cab 505 struct amdgpu_device *adev,
4562236b 506 struct dc_surface *surface,
d7e3316c
AG		 507 struct drm_plane_state *plane_state,
508 struct drm_crtc_state *crtc_state,
509 bool addrReq)
4562236b
HW		 510{
511 const struct amdgpu_framebuffer *amdgpu_fb =
d7e3316c
AG		 512 to_amdgpu_framebuffer(plane_state->fb);
513 const struct drm_crtc *crtc = plane_state->crtc;
18f39f2d 514 struct dc_transfer_func *input_tf;
d7e3316c
AG		 515 int ret = 0;
516
517 if (!fill_rects_from_plane_state(plane_state, surface))
518 return -EINVAL;
4562236b 519
d7e3316c 520 ret = fill_plane_attributes_from_fb(
6a1f8cab 521 crtc->dev->dev_private,
4562236b
HW		 522 surface,
523 amdgpu_fb,
524 addrReq);
525
d7e3316c
AG		 526 if (ret)
527 return ret;
528
18f39f2d
RL		 529 input_tf = dc_create_transfer_func();
530
531 if (input_tf == NULL)
d7e3316c 532 return -ENOMEM;
18f39f2d
RL		 533
534 input_tf->type = TF_TYPE_PREDEFINED;
535 input_tf->tf = TRANSFER_FUNCTION_SRGB;
536
537 surface->in_transfer_func = input_tf;
538
4562236b 539 /* In case of gamma set, update gamma value */
d7e3316c
AG		 540 if (crtc_state->gamma_lut)
541 fill_gamma_from_crtc_state(crtc_state, surface);
542
543 return ret;
4562236b
HW		 544}
545
546/*****************************************************************************/
547
548struct amdgpu_connector *aconnector_from_drm_crtc_id(
549 const struct drm_crtc *crtc)
550{
551 struct drm_device *dev = crtc->dev;
552 struct drm_connector *connector;
553 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
554 struct amdgpu_connector *aconnector;
555
556 list_for_each_entry(connector,
557 &dev->mode_config.connector_list, head) {
558
559 aconnector = to_amdgpu_connector(connector);
560
561 if (aconnector->base.state->crtc != &acrtc->base)
562 continue;
563
564 /* Found the connector */
565 return aconnector;
566 }
567
568 /* If we get here, not found. */
569 return NULL;
570}
571
572static void update_stream_scaling_settings(
573 const struct drm_display_mode *mode,
574 const struct dm_connector_state *dm_state,
ccaa7389 575 struct dc_stream *stream)
4562236b 576{
4562236b
HW		 577 enum amdgpu_rmx_type rmx_type;
578
ab2541b6 579 struct rect src = { 0 }; /* viewport in composition space*/
4562236b
HW		 580 struct rect dst = { 0 }; /* stream addressable area */
581
f7f3cfee
HW		 582 /* no mode. nothing to be done */
583 if (!mode)
584 return;
585
4562236b
HW		 586 /* Full screen scaling by default */
587 src.width = mode->hdisplay;
588 src.height = mode->vdisplay;
589 dst.width = stream->timing.h_addressable;
590 dst.height = stream->timing.v_addressable;
591
592 rmx_type = dm_state->scaling;
593 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
594 if (src.width * dst.height <
595 src.height * dst.width) {
596 /* height needs less upscaling/more downscaling */
597 dst.width = src.width *
598 dst.height / src.height;
599 } else {
600 /* width needs less upscaling/more downscaling */
601 dst.height = src.height *
602 dst.width / src.width;
603 }
604 } else if (rmx_type == RMX_CENTER) {
605 dst = src;
606 }
607
608 dst.x = (stream->timing.h_addressable - dst.width) / 2;
609 dst.y = (stream->timing.v_addressable - dst.height) / 2;
610
611 if (dm_state->underscan_enable) {
612 dst.x += dm_state->underscan_hborder / 2;
613 dst.y += dm_state->underscan_vborder / 2;
614 dst.width -= dm_state->underscan_hborder;
615 dst.height -= dm_state->underscan_vborder;
616 }
617
ccaa7389
AG		 618 stream->src = src;
619 stream->dst = dst;
4562236b
HW		 620
621 DRM_DEBUG_KMS("Destination Rectangle x:%d y:%d width:%d height:%d\n",
622 dst.x, dst.y, dst.width, dst.height);
623
624}
625
4562236b
HW		 626static enum dc_color_depth convert_color_depth_from_display_info(
627 const struct drm_connector *connector)
628{
629 uint32_t bpc = connector->display_info.bpc;
630
631 /* Limited color depth to 8bit
632 * TODO: Still need to handle deep color*/
633 if (bpc > 8)
634 bpc = 8;
635
636 switch (bpc) {
637 case 0:
638 /* Temporary Work around, DRM don't parse color depth for
639 * EDID revision before 1.4
640 * TODO: Fix edid parsing
641 */
642 return COLOR_DEPTH_888;
643 case 6:
644 return COLOR_DEPTH_666;
645 case 8:
646 return COLOR_DEPTH_888;
647 case 10:
648 return COLOR_DEPTH_101010;
649 case 12:
650 return COLOR_DEPTH_121212;
651 case 14:
652 return COLOR_DEPTH_141414;
653 case 16:
654 return COLOR_DEPTH_161616;
655 default:
656 return COLOR_DEPTH_UNDEFINED;
657 }
658}
659
660static enum dc_aspect_ratio get_aspect_ratio(
661 const struct drm_display_mode *mode_in)
662{
663 int32_t width = mode_in->crtc_hdisplay * 9;
664 int32_t height = mode_in->crtc_vdisplay * 16;
665 if ((width - height) < 10 && (width - height) > -10)
666 return ASPECT_RATIO_16_9;
667 else
668 return ASPECT_RATIO_4_3;
669}
670
671static enum dc_color_space get_output_color_space(
672 const struct dc_crtc_timing *dc_crtc_timing)
673{
674 enum dc_color_space color_space = COLOR_SPACE_SRGB;
675
676 switch (dc_crtc_timing->pixel_encoding) {
677 case PIXEL_ENCODING_YCBCR422:
678 case PIXEL_ENCODING_YCBCR444:
679 case PIXEL_ENCODING_YCBCR420:
680 {
681 /*
682 * 27030khz is the separation point between HDTV and SDTV
683 * according to HDMI spec, we use YCbCr709 and YCbCr601
684 * respectively
685 */
686 if (dc_crtc_timing->pix_clk_khz > 27030) {
687 if (dc_crtc_timing->flags.Y_ONLY)
688 color_space =
689 COLOR_SPACE_YCBCR709_LIMITED;
690 else
691 color_space = COLOR_SPACE_YCBCR709;
692 } else {
693 if (dc_crtc_timing->flags.Y_ONLY)
694 color_space =
695 COLOR_SPACE_YCBCR601_LIMITED;
696 else
697 color_space = COLOR_SPACE_YCBCR601;
698 }
699
700 }
701 break;
702 case PIXEL_ENCODING_RGB:
703 color_space = COLOR_SPACE_SRGB;
704 break;
705
706 default:
707 WARN_ON(1);
708 break;
709 }
710
711 return color_space;
712}
713
714/*****************************************************************************/
715
716static void fill_stream_properties_from_drm_display_mode(
717 struct dc_stream *stream,
718 const struct drm_display_mode *mode_in,
719 const struct drm_connector *connector)
720{
721 struct dc_crtc_timing *timing_out = &stream->timing;
722 memset(timing_out, 0, sizeof(struct dc_crtc_timing));
723
724 timing_out->h_border_left = 0;
725 timing_out->h_border_right = 0;
726 timing_out->v_border_top = 0;
727 timing_out->v_border_bottom = 0;
728 /* TODO: un-hardcode */
729
730 if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
731 && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
732 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
733 else
734 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
735
736 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
737 timing_out->display_color_depth = convert_color_depth_from_display_info(
738 connector);
739 timing_out->scan_type = SCANNING_TYPE_NODATA;
740 timing_out->hdmi_vic = 0;
741 timing_out->vic = drm_match_cea_mode(mode_in);
742
743 timing_out->h_addressable = mode_in->crtc_hdisplay;
744 timing_out->h_total = mode_in->crtc_htotal;
745 timing_out->h_sync_width =
746 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
747 timing_out->h_front_porch =
748 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
749 timing_out->v_total = mode_in->crtc_vtotal;
750 timing_out->v_addressable = mode_in->crtc_vdisplay;
751 timing_out->v_front_porch =
752 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
753 timing_out->v_sync_width =
754 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
755 timing_out->pix_clk_khz = mode_in->crtc_clock;
756 timing_out->aspect_ratio = get_aspect_ratio(mode_in);
757 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
758 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
759 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
760 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
761
762 stream->output_color_space = get_output_color_space(timing_out);
763
d7194cf6
AC		 764 {
765 struct dc_transfer_func *tf = dc_create_transfer_func();
766 tf->type = TF_TYPE_PREDEFINED;
767 tf->tf = TRANSFER_FUNCTION_SRGB;
768 stream->out_transfer_func = tf;
769 }
4562236b
HW		 770}
771
772static void fill_audio_info(
773 struct audio_info *audio_info,
774 const struct drm_connector *drm_connector,
775 const struct dc_sink *dc_sink)
776{
777 int i = 0;
778 int cea_revision = 0;
779 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
780
781 audio_info->manufacture_id = edid_caps->manufacturer_id;
782 audio_info->product_id = edid_caps->product_id;
783
784 cea_revision = drm_connector->display_info.cea_rev;
785
786 while (i < AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS &&
787 edid_caps->display_name[i]) {
788 audio_info->display_name[i] = edid_caps->display_name[i];
789 i++;
790 }
791
792 if(cea_revision >= 3) {
793 audio_info->mode_count = edid_caps->audio_mode_count;
794
795 for (i = 0; i < audio_info->mode_count; ++i) {
796 audio_info->modes[i].format_code =
797 (enum audio_format_code)
798 (edid_caps->audio_modes[i].format_code);
799 audio_info->modes[i].channel_count =
800 edid_caps->audio_modes[i].channel_count;
801 audio_info->modes[i].sample_rates.all =
802 edid_caps->audio_modes[i].sample_rate;
803 audio_info->modes[i].sample_size =
804 edid_caps->audio_modes[i].sample_size;
805 }
806 }
807
808 audio_info->flags.all = edid_caps->speaker_flags;
809
810 /* TODO: We only check for the progressive mode, check for interlace mode too */
811 if(drm_connector->latency_present[0]) {
812 audio_info->video_latency = drm_connector->video_latency[0];
813 audio_info->audio_latency = drm_connector->audio_latency[0];
814 }
815
816 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
817
818}
819
820static void copy_crtc_timing_for_drm_display_mode(
821 const struct drm_display_mode *src_mode,
822 struct drm_display_mode *dst_mode)
823{
824 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
825 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
826 dst_mode->crtc_clock = src_mode->crtc_clock;
827 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
828 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
829 dst_mode->crtc_hsync_start= src_mode->crtc_hsync_start;
830 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
831 dst_mode->crtc_htotal = src_mode->crtc_htotal;
832 dst_mode->crtc_hskew = src_mode->crtc_hskew;
5866e7cf
JL		 833 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
834 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
835 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
836 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
837 dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
4562236b
HW		 838}
839
840static void decide_crtc_timing_for_drm_display_mode(
841 struct drm_display_mode *drm_mode,
842 const struct drm_display_mode *native_mode,
843 bool scale_enabled)
844{
845 if (scale_enabled) {
846 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
847 } else if (native_mode->clock == drm_mode->clock &&
848 native_mode->htotal == drm_mode->htotal &&
849 native_mode->vtotal == drm_mode->vtotal) {
850 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
851 } else {
852 /* no scaling nor amdgpu inserted, no need to patch */
853 }
854}
855
ab2541b6 856static struct dc_stream *create_stream_for_sink(
0d70570f 857 struct amdgpu_connector *aconnector,
4562236b
HW		 858 const struct drm_display_mode *drm_mode,
859 const struct dm_connector_state *dm_state)
860{
861 struct drm_display_mode *preferred_mode = NULL;
862 const struct drm_connector *drm_connector;
ab2541b6 863 struct dc_stream *stream = NULL;
4562236b
HW		 864 struct drm_display_mode mode = *drm_mode;
865 bool native_mode_found = false;
866
867 if (NULL == aconnector) {
868 DRM_ERROR("aconnector is NULL!\n");
869 goto drm_connector_null;
870 }
871
872 if (NULL == dm_state) {
873 DRM_ERROR("dm_state is NULL!\n");
874 goto dm_state_null;
875 }
876
877 drm_connector = &aconnector->base;
878 stream = dc_create_stream_for_sink(aconnector->dc_sink);
879
880 if (NULL == stream) {
881 DRM_ERROR("Failed to create stream for sink!\n");
882 goto stream_create_fail;
883 }
884
885 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
886 /* Search for preferred mode */
887 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
888 native_mode_found = true;
889 break;
890 }
891 }
892 if (!native_mode_found)
893 preferred_mode = list_first_entry_or_null(
894 &aconnector->base.modes,
895 struct drm_display_mode,
896 head);
897
898 if (NULL == preferred_mode) {
899 /* This may not be an error, the use case is when we we have no
900 * usermode calls to reset and set mode upon hotplug. In this
901 * case, we call set mode ourselves to restore the previous mode
902 * and the modelist may not be filled in in time.
903 */
904 DRM_INFO("No preferred mode found\n");
905 } else {
906 decide_crtc_timing_for_drm_display_mode(
907 &mode, preferred_mode,
908 dm_state->scaling != RMX_OFF);
909 }
910
911 fill_stream_properties_from_drm_display_mode(stream,
912 &mode, &aconnector->base);
913 update_stream_scaling_settings(&mode, dm_state, stream);
914
915 fill_audio_info(
916 &stream->audio_info,
917 drm_connector,
918 aconnector->dc_sink);
919
ab2541b6 920stream_create_fail:
4562236b
HW		 921dm_state_null:
922drm_connector_null:
ab2541b6 923 return stream;
4562236b
HW		 924}
925
926void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
927{
928 drm_crtc_cleanup(crtc);
929 kfree(crtc);
930}
931
ba6bf832
AG		 932static void dm_crtc_destroy_state(struct drm_crtc *crtc,
933 struct drm_crtc_state *state)
934{
935 struct dm_crtc_state *cur = to_dm_crtc_state(state);
936
da5c47f6
AG		 937 /* TODO Destroy dc_stream objects are stream object is flattened */
938 if (cur->stream)
939 dc_stream_release(cur->stream);
940
ba6bf832
AG		 941
942 __drm_atomic_helper_crtc_destroy_state(state);
943
944
945 kfree(state);
946}
947
948static void dm_crtc_reset_state(struct drm_crtc *crtc)
949{
950 struct dm_crtc_state *state;
951
952 if (crtc->state)
953 dm_crtc_destroy_state(crtc, crtc->state);
954
955 state = kzalloc(sizeof(*state), GFP_KERNEL);
956 if (WARN_ON(!state))
957 return;
958
ba6bf832
AG		 959 crtc->state = &state->base;
960 crtc->state->crtc = crtc;
961
ba6bf832
AG		 962}
963
964static struct drm_crtc_state *
965dm_crtc_duplicate_state(struct drm_crtc *crtc)
966{
967 struct dm_crtc_state *state, *cur;
ba6bf832
AG		 968
969 cur = to_dm_crtc_state(crtc->state);
ba6bf832 970
da5c47f6 971 if (WARN_ON(!crtc->state))
ba6bf832
AG		 972 return NULL;
973
974 state = dm_alloc(sizeof(*state));
ba6bf832
AG		 975
976 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
977
da5c47f6
AG		 978 if (cur->stream) {
979 state->stream = cur->stream;
980 dc_stream_retain(state->stream);
981 }
ba6bf832
AG		 982
983 /* TODO Duplicate dc_stream after objects are stream object is flattened */
984
985 return &state->base;
986}
987
4562236b
HW		 988/* Implemented only the options currently availible for the driver */
989static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
ba6bf832 990 .reset = dm_crtc_reset_state,
4562236b
HW		 991 .destroy = amdgpu_dm_crtc_destroy,
992 .gamma_set = drm_atomic_helper_legacy_gamma_set,
993 .set_config = drm_atomic_helper_set_config,
994 .page_flip = drm_atomic_helper_page_flip,
ba6bf832
AG		 995 .atomic_duplicate_state = dm_crtc_duplicate_state,
996 .atomic_destroy_state = dm_crtc_destroy_state,
4562236b
HW		 997};
998
999static enum drm_connector_status
1000amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
1001{
1002 bool connected;
1003 struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
1004
1005 /* Notes:
1006 * 1. This interface is NOT called in context of HPD irq.
1007 * 2. This interface *is called* in context of user-mode ioctl. Which
1008 * makes it a bad place for *any* MST-related activit. */
1009
1010 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
1011 connected = (aconnector->dc_sink != NULL);
1012 else
1013 connected = (aconnector->base.force == DRM_FORCE_ON);
1014
1015 return (connected ? connector_status_connected :
1016 connector_status_disconnected);
1017}
1018
1019int amdgpu_dm_connector_atomic_set_property(
1020 struct drm_connector *connector,
1021 struct drm_connector_state *connector_state,
1022 struct drm_property *property,
1023 uint64_t val)
1024{
1025 struct drm_device *dev = connector->dev;
1026 struct amdgpu_device *adev = dev->dev_private;
1027 struct dm_connector_state *dm_old_state =
1028 to_dm_connector_state(connector->state);
1029 struct dm_connector_state *dm_new_state =
1030 to_dm_connector_state(connector_state);
1031
4562236b
HW		 1032 int ret = -EINVAL;
1033
1034 if (property == dev->mode_config.scaling_mode_property) {
1035 enum amdgpu_rmx_type rmx_type;
1036
1037 switch (val) {
1038 case DRM_MODE_SCALE_CENTER:
1039 rmx_type = RMX_CENTER;
1040 break;
1041 case DRM_MODE_SCALE_ASPECT:
1042 rmx_type = RMX_ASPECT;
1043 break;
1044 case DRM_MODE_SCALE_FULLSCREEN:
1045 rmx_type = RMX_FULL;
1046 break;
1047 case DRM_MODE_SCALE_NONE:
1048 default:
1049 rmx_type = RMX_OFF;
1050 break;
1051 }
1052
1053 if (dm_old_state->scaling == rmx_type)
1054 return 0;
1055
1056 dm_new_state->scaling = rmx_type;
1057 ret = 0;
1058 } else if (property == adev->mode_info.underscan_hborder_property) {
1059 dm_new_state->underscan_hborder = val;
1060 ret = 0;
1061 } else if (property == adev->mode_info.underscan_vborder_property) {
1062 dm_new_state->underscan_vborder = val;
1063 ret = 0;
1064 } else if (property == adev->mode_info.underscan_property) {
1065 dm_new_state->underscan_enable = val;
1066 ret = 0;
1067 }
1068
4562236b
HW		 1069 return ret;
1070}
1071
32a1892a
PV		 1072int amdgpu_dm_connector_atomic_get_property(
1073 struct drm_connector *connector,
1074 const struct drm_connector_state *state,
1075 struct drm_property *property,
1076 uint64_t *val)
1077{
1078 struct drm_device *dev = connector->dev;
1079 struct amdgpu_device *adev = dev->dev_private;
1080 struct dm_connector_state *dm_state =
1081 to_dm_connector_state(state);
1082 int ret = -EINVAL;
1083
1084 if (property == dev->mode_config.scaling_mode_property) {
1085 switch (dm_state->scaling) {
1086 case RMX_CENTER:
1087 *val = DRM_MODE_SCALE_CENTER;
1088 break;
1089 case RMX_ASPECT:
1090 *val = DRM_MODE_SCALE_ASPECT;
1091 break;
1092 case RMX_FULL:
1093 *val = DRM_MODE_SCALE_FULLSCREEN;
1094 break;
1095 case RMX_OFF:
1096 default:
1097 *val = DRM_MODE_SCALE_NONE;
1098 break;
1099 }
1100 ret = 0;
1101 } else if (property == adev->mode_info.underscan_hborder_property) {
1102 *val = dm_state->underscan_hborder;
1103 ret = 0;
1104 } else if (property == adev->mode_info.underscan_vborder_property) {
1105 *val = dm_state->underscan_vborder;
1106 ret = 0;
1107 } else if (property == adev->mode_info.underscan_property) {
1108 *val = dm_state->underscan_enable;
1109 ret = 0;
1110 }
1111 return ret;
1112}
1113
4562236b
HW		 1114void amdgpu_dm_connector_destroy(struct drm_connector *connector)
1115{
1116 struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
1117 const struct dc_link *link = aconnector->dc_link;
1118 struct amdgpu_device *adev = connector->dev->dev_private;
1119 struct amdgpu_display_manager *dm = &adev->dm;
1120#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1121 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1122
1123 if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) {
1124 amdgpu_dm_register_backlight_device(dm);
1125
1126 if (dm->backlight_dev) {
1127 backlight_device_unregister(dm->backlight_dev);
1128 dm->backlight_dev = NULL;
1129 }
1130
1131 }
1132#endif
1133 drm_connector_unregister(connector);
1134 drm_connector_cleanup(connector);
1135 kfree(connector);
1136}
1137
1138void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
1139{
1140 struct dm_connector_state *state =
1141 to_dm_connector_state(connector->state);
1142
1143 kfree(state);
1144
1145 state = kzalloc(sizeof(*state), GFP_KERNEL);
1146
1147 if (state) {
1148 state->scaling = RMX_OFF;
1149 state->underscan_enable = false;
1150 state->underscan_hborder = 0;
1151 state->underscan_vborder = 0;
1152
1153 connector->state = &state->base;
1154 connector->state->connector = connector;
1155 }
1156}
1157
1158struct drm_connector_state *amdgpu_dm_connector_atomic_duplicate_state(
1159 struct drm_connector *connector)
1160{
1161 struct dm_connector_state *state =
1162 to_dm_connector_state(connector->state);
1163
1164 struct dm_connector_state *new_state =
1165 kmemdup(state, sizeof(*state), GFP_KERNEL);
1166
1167 if (new_state) {
1168 __drm_atomic_helper_connector_duplicate_state(connector,
1169 &new_state->base);
1170 return &new_state->base;
1171 }
1172
1173 return NULL;
1174}
1175
1176static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
1177 .reset = amdgpu_dm_connector_funcs_reset,
1178 .detect = amdgpu_dm_connector_detect,
1179 .fill_modes = drm_helper_probe_single_connector_modes,
1180 .destroy = amdgpu_dm_connector_destroy,
1181 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
1182 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
664a2ed1 1183 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
32a1892a 1184 .atomic_get_property = amdgpu_dm_connector_atomic_get_property
4562236b
HW		 1185};
1186
1187static struct drm_encoder *best_encoder(struct drm_connector *connector)
1188{
1189 int enc_id = connector->encoder_ids[0];
1190 struct drm_mode_object *obj;
1191 struct drm_encoder *encoder;
1192
1193 DRM_DEBUG_KMS("Finding the best encoder\n");
1194
1195 /* pick the encoder ids */
1196 if (enc_id) {
1197 obj = drm_mode_object_find(connector->dev, enc_id, DRM_MODE_OBJECT_ENCODER);
1198 if (!obj) {
1199 DRM_ERROR("Couldn't find a matching encoder for our connector\n");
1200 return NULL;
1201 }
1202 encoder = obj_to_encoder(obj);
1203 return encoder;
1204 }
1205 DRM_ERROR("No encoder id\n");
1206 return NULL;
1207}
1208
1209static int get_modes(struct drm_connector *connector)
1210{
1211 return amdgpu_dm_connector_get_modes(connector);
1212}
1213
1214static void create_eml_sink(struct amdgpu_connector *aconnector)
1215{
1216 struct dc_sink_init_data init_params = {
1217 .link = aconnector->dc_link,
1218 .sink_signal = SIGNAL_TYPE_VIRTUAL
1219 };
1220 struct edid *edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
1221
1222 if (!aconnector->base.edid_blob_ptr ||
1223 !aconnector->base.edid_blob_ptr->data) {
1224 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
1225 aconnector->base.name);
1226
1227 aconnector->base.force = DRM_FORCE_OFF;
1228 aconnector->base.override_edid = false;
1229 return;
1230 }
1231
1232 aconnector->edid = edid;
1233
1234 aconnector->dc_em_sink = dc_link_add_remote_sink(
1235 aconnector->dc_link,
1236 (uint8_t *)edid,
1237 (edid->extensions + 1) * EDID_LENGTH,
1238 &init_params);
1239
1240 if (aconnector->base.force
1241 == DRM_FORCE_ON)
1242 aconnector->dc_sink = aconnector->dc_link->local_sink ?
1243 aconnector->dc_link->local_sink :
1244 aconnector->dc_em_sink;
1245}
1246
1247static void handle_edid_mgmt(struct amdgpu_connector *aconnector)
1248{
1249 struct dc_link *link = (struct dc_link *)aconnector->dc_link;
1250
1251 /* In case of headless boot with force on for DP managed connector
1252 * Those settings have to be != 0 to get initial modeset
1253 */
1254 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
1255 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
1256 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
1257 }
1258
1259
1260 aconnector->base.override_edid = true;
1261 create_eml_sink(aconnector);
1262}
1263
1264int amdgpu_dm_connector_mode_valid(
1265 struct drm_connector *connector,
1266 struct drm_display_mode *mode)
1267{
1268 int result = MODE_ERROR;
1269 const struct dc_sink *dc_sink;
1270 struct amdgpu_device *adev = connector->dev->dev_private;
1271 struct dc_validation_set val_set = { 0 };
1272 /* TODO: Unhardcode stream count */
ab2541b6 1273 struct dc_stream *stream;
4562236b 1274 struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
07d72b39 1275 struct validate_context *context;
4562236b
HW		 1276
1277 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1278 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
1279 return result;
1280
1281 /* Only run this the first time mode_valid is called to initilialize
1282 * EDID mgmt
1283 */
1284 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
1285 !aconnector->dc_em_sink)
1286 handle_edid_mgmt(aconnector);
1287
1288 dc_sink = to_amdgpu_connector(connector)->dc_sink;
1289
1290 if (NULL == dc_sink) {
1291 DRM_ERROR("dc_sink is NULL!\n");
ab2541b6 1292 goto null_sink;
4562236b
HW		 1293 }
1294
ab2541b6
AC		 1295 stream = dc_create_stream_for_sink(dc_sink);
1296 if (NULL == stream) {
4562236b
HW		 1297 DRM_ERROR("Failed to create stream for sink!\n");
1298 goto stream_create_fail;
1299 }
1300
1301 drm_mode_set_crtcinfo(mode, 0);
ab2541b6 1302 fill_stream_properties_from_drm_display_mode(stream, mode, connector);
4562236b 1303
ab2541b6 1304 val_set.stream = stream;
4562236b 1305 val_set.surface_count = 0;
ab2541b6
AC		 1306 stream->src.width = mode->hdisplay;
1307 stream->src.height = mode->vdisplay;
1308 stream->dst = stream->src;
4562236b 1309
07d72b39
HW		 1310 context = dc_get_validate_context(adev->dm.dc, &val_set, 1);
1311
1312 if (context) {
4562236b 1313 result = MODE_OK;
3b42a1c0 1314 dc_release_validate_context(context);
07d72b39 1315 }
4562236b 1316
ab2541b6
AC		 1317 dc_stream_release(stream);
1318
4562236b 1319stream_create_fail:
ab2541b6 1320null_sink:
4562236b
HW		 1321 /* TODO: error handling*/
1322 return result;
1323}
1324
1325static const struct drm_connector_helper_funcs
1326amdgpu_dm_connector_helper_funcs = {
1327 /*
1328 * If hotplug a second bigger display in FB Con mode, bigger resolution
1329 * modes will be filtered by drm_mode_validate_size(), and those modes
1330 * is missing after user start lightdm. So we need to renew modes list.
1331 * in get_modes call back, not just return the modes count
1332 */
1333 .get_modes = get_modes,
1334 .mode_valid = amdgpu_dm_connector_mode_valid,
1335 .best_encoder = best_encoder
1336};
1337
1338static void dm_crtc_helper_disable(struct drm_crtc *crtc)
1339{
1340}
1341
1342static int dm_crtc_helper_atomic_check(
1343 struct drm_crtc *crtc,
1344 struct drm_crtc_state *state)
1345{
1346 return 0;
1347}
1348
1349static bool dm_crtc_helper_mode_fixup(
1350 struct drm_crtc *crtc,
1351 const struct drm_display_mode *mode,
1352 struct drm_display_mode *adjusted_mode)
1353{
1354 return true;
1355}
1356
1357static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
1358 .disable = dm_crtc_helper_disable,
1359 .atomic_check = dm_crtc_helper_atomic_check,
1360 .mode_fixup = dm_crtc_helper_mode_fixup
1361};
1362
1363static void dm_encoder_helper_disable(struct drm_encoder *encoder)
1364{
1365
1366}
1367
1368static int dm_encoder_helper_atomic_check(
1369 struct drm_encoder *encoder,
1370 struct drm_crtc_state *crtc_state,
1371 struct drm_connector_state *conn_state)
1372{
1373 return 0;
1374}
1375
1376const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
1377 .disable = dm_encoder_helper_disable,
1378 .atomic_check = dm_encoder_helper_atomic_check
1379};
1380
64d8b780
S		 1381static void dm_drm_plane_reset(struct drm_plane *plane)
1382{
0604b36c 1383 struct dm_plane_state *amdgpu_state = NULL;
0604b36c
AG		 1384
1385 if (plane->state)
1386 plane->funcs->atomic_destroy_state(plane, plane->state);
64d8b780
S		 1387
1388 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
0604b36c 1389
64d8b780
S		 1390 if (amdgpu_state) {
1391 plane->state = &amdgpu_state->base;
1392 plane->state->plane = plane;
0604b36c 1393 plane->state->rotation = DRM_MODE_ROTATE_0;
64d8b780 1394 }
0604b36c
AG		 1395 else
1396 WARN_ON(1);
64d8b780
S		 1397}
1398
1399static struct drm_plane_state *
1400dm_drm_plane_duplicate_state(struct drm_plane *plane)
1401{
0604b36c 1402 struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
0604b36c
AG		 1403
1404 old_dm_plane_state = to_dm_plane_state(plane->state);
1405 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
1406 if (!dm_plane_state)
1407 return NULL;
1408
3d21a662 1409 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
0604b36c 1410
d7e3316c
AG		 1411 if (old_dm_plane_state->surface) {
1412 dm_plane_state->surface = old_dm_plane_state->surface;
1413 dc_surface_retain(dm_plane_state->surface);
0604b36c 1414 }
64d8b780 1415
0604b36c 1416 return &dm_plane_state->base;
64d8b780
S		 1417}
1418
0604b36c
AG		 1419void dm_drm_plane_destroy_state(struct drm_plane *plane,
1420 struct drm_plane_state *state)
64d8b780 1421{
0604b36c
AG		 1422 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
1423
d7e3316c
AG		 1424 if (dm_plane_state->surface)
1425 dc_surface_release(dm_plane_state->surface);
0604b36c 1426
a67297d4
XY		 1427 __drm_atomic_helper_plane_destroy_state(state);
1428 kfree(dm_plane_state);
64d8b780
S		 1429}
1430
4562236b 1431static const struct drm_plane_funcs dm_plane_funcs = {
64d8b780
S		 1432 .update_plane = drm_atomic_helper_update_plane,
1433 .disable_plane = drm_atomic_helper_disable_plane,
1434 .destroy = drm_plane_cleanup,
1435 .reset = dm_drm_plane_reset,
1436 .atomic_duplicate_state = dm_drm_plane_duplicate_state,
1437 .atomic_destroy_state = dm_drm_plane_destroy_state,
4562236b
HW		 1438};
1439
4562236b
HW		 1440static int dm_plane_helper_prepare_fb(
1441 struct drm_plane *plane,
1442 struct drm_plane_state *new_state)
1443{
1444 struct amdgpu_framebuffer *afb;
1445 struct drm_gem_object *obj;
1446 struct amdgpu_bo *rbo;
1447 int r;
d7e3316c
AG		 1448 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
1449 unsigned int awidth;
1450
1451 dm_plane_state_old = to_dm_plane_state(plane->state);
1452 dm_plane_state_new = to_dm_plane_state(new_state);
4562236b
HW		 1453
1454 if (!new_state->fb) {
1455 DRM_DEBUG_KMS("No FB bound\n");
1456 return 0;
1457 }
1458
1459 afb = to_amdgpu_framebuffer(new_state->fb);
1460
1461 obj = afb->obj;
1462 rbo = gem_to_amdgpu_bo(obj);
1463 r = amdgpu_bo_reserve(rbo, false);
1464 if (unlikely(r != 0))
1465 return r;
1466
54f5499a 1467 r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &afb->address);
4562236b 1468
d7e3316c 1469
4562236b
HW		 1470 amdgpu_bo_unreserve(rbo);
1471
1472 if (unlikely(r != 0)) {
1473 DRM_ERROR("Failed to pin framebuffer\n");
1474 return r;
1475 }
1476
54f5499a 1477 amdgpu_bo_ref(rbo);
2ea5e9a8 1478
d7e3316c
AG		 1479 if (dm_plane_state_new->surface &&
1480 dm_plane_state_old->surface != dm_plane_state_new->surface) {
1481 struct dc_surface *surface = dm_plane_state_new->surface;
1482
1483 if (surface->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
1484 surface->address.grph.addr.low_part = lower_32_bits(afb->address);
1485 surface->address.grph.addr.high_part = upper_32_bits(afb->address);
1486 } else {
1487 awidth = ALIGN(new_state->fb->width, 64);
1488 surface->address.video_progressive.luma_addr.low_part
1489 = lower_32_bits(afb->address);
1490 surface->address.video_progressive.chroma_addr.low_part
1491 = lower_32_bits(afb->address) +
1492 (awidth * new_state->fb->height);
1493 }
1494 }
1495
2ea5e9a8
AG		 1496 /* It's a hack for s3 since in 4.9 kernel filter out cursor buffer
1497 * prepare and cleanup in drm_atomic_helper_prepare_planes
1498 * and drm_atomic_helper_cleanup_planes because fb doens't in s3.
1499 * IN 4.10 kernel this code should be removed and amdgpu_device_suspend
1500 * code touching fram buffers should be avoided for DC.
1501 */
1502 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
1503 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_state->crtc);
1504
1505 acrtc->cursor_bo = obj;
1506 }
4562236b
HW		 1507 return 0;
1508}
1509
1510static void dm_plane_helper_cleanup_fb(
1511 struct drm_plane *plane,
1512 struct drm_plane_state *old_state)
1513{
1514 struct amdgpu_bo *rbo;
1515 struct amdgpu_framebuffer *afb;
1516 int r;
1517
1518 if (!old_state->fb)
1519 return;
1520
1521 afb = to_amdgpu_framebuffer(old_state->fb);
1522 rbo = gem_to_amdgpu_bo(afb->obj);
1523 r = amdgpu_bo_reserve(rbo, false);
1524 if (unlikely(r)) {
1525 DRM_ERROR("failed to reserve rbo before unpin\n");
1526 return;
1527 } else {
1528 amdgpu_bo_unpin(rbo);
1529 amdgpu_bo_unreserve(rbo);
54f5499a 1530 amdgpu_bo_unref(&rbo);
3273d3bf 1531 };
4562236b
HW		 1532}
1533
ab2541b6 1534int dm_create_validation_set_for_connector(struct drm_connector *connector,
4562236b
HW		 1535 struct drm_display_mode *mode, struct dc_validation_set *val_set)
1536{
1537 int result = MODE_ERROR;
1538 const struct dc_sink *dc_sink =
1539 to_amdgpu_connector(connector)->dc_sink;
1540 /* TODO: Unhardcode stream count */
ab2541b6 1541 struct dc_stream *stream;
4562236b
HW		 1542
1543 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1544 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
1545 return result;
1546
1547 if (NULL == dc_sink) {
1548 DRM_ERROR("dc_sink is NULL!\n");
1549 return result;
1550 }
1551
ab2541b6 1552 stream = dc_create_stream_for_sink(dc_sink);
4562236b 1553
ab2541b6 1554 if (NULL == stream) {
4562236b
HW		 1555 DRM_ERROR("Failed to create stream for sink!\n");
1556 return result;
1557 }
1558
1559 drm_mode_set_crtcinfo(mode, 0);
1560
ab2541b6 1561 fill_stream_properties_from_drm_display_mode(stream, mode, connector);
4562236b 1562
ab2541b6 1563 val_set->stream = stream;
4562236b 1564
ab2541b6
AC		 1565 stream->src.width = mode->hdisplay;
1566 stream->src.height = mode->vdisplay;
1567 stream->dst = stream->src;
4562236b
HW		 1568
1569 return MODE_OK;
4562236b
HW		 1570}
1571
1572static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
1573 .prepare_fb = dm_plane_helper_prepare_fb,
1574 .cleanup_fb = dm_plane_helper_cleanup_fb,
1575};
1576
1577/*
1578 * TODO: these are currently initialized to rgb formats only.
1579 * For future use cases we should either initialize them dynamically based on
1580 * plane capabilities, or initialize this array to all formats, so internal drm
1581 * check will succeed, and let DC to implement proper check
1582 */
1583static uint32_t rgb_formats[] = {
4562236b
HW		 1584 DRM_FORMAT_RGB888,
1585 DRM_FORMAT_XRGB8888,
1586 DRM_FORMAT_ARGB8888,
1587 DRM_FORMAT_RGBA8888,
1588 DRM_FORMAT_XRGB2101010,
1589 DRM_FORMAT_XBGR2101010,
1590 DRM_FORMAT_ARGB2101010,
1591 DRM_FORMAT_ABGR2101010,
1592};
1593
d4e13b0d 1594static uint32_t yuv_formats[] = {
f0c16087
S		 1595 DRM_FORMAT_NV12,
1596 DRM_FORMAT_NV21,
d4e13b0d 1597};
4562236b 1598
2ea5e9a8
AG		 1599static const u32 cursor_formats[] = {
1600 DRM_FORMAT_ARGB8888
1601};
1602
d4e13b0d
AD		 1603int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
1604 struct amdgpu_plane *aplane,
1605 unsigned long possible_crtcs)
1606{
1607 int res = -EPERM;
1608
1605b3be 1609 switch (aplane->base.type) {
d4e13b0d
AD		 1610 case DRM_PLANE_TYPE_PRIMARY:
1611 aplane->base.format_default = true;
1612
1613 res = drm_universal_plane_init(
1614 dm->adev->ddev,
1615 &aplane->base,
1616 possible_crtcs,
1617 &dm_plane_funcs,
1618 rgb_formats,
1619 ARRAY_SIZE(rgb_formats),
1605b3be 1620 NULL, aplane->base.type, NULL);
d4e13b0d
AD		 1621 break;
1622 case DRM_PLANE_TYPE_OVERLAY:
1623 res = drm_universal_plane_init(
1624 dm->adev->ddev,
1625 &aplane->base,
1626 possible_crtcs,
1627 &dm_plane_funcs,
1628 yuv_formats,
1629 ARRAY_SIZE(yuv_formats),
1605b3be 1630 NULL, aplane->base.type, NULL);
d4e13b0d
AD		 1631 break;
1632 case DRM_PLANE_TYPE_CURSOR:
2ea5e9a8
AG		 1633 res = drm_universal_plane_init(
1634 dm->adev->ddev,
1635 &aplane->base,
1636 possible_crtcs,
1637 &dm_plane_funcs,
1638 cursor_formats,
1639 ARRAY_SIZE(cursor_formats),
1605b3be 1640 NULL, aplane->base.type, NULL);
d4e13b0d
AD		 1641 break;
1642 }
4562236b 1643
d4e13b0d 1644 drm_plane_helper_add(&aplane->base, &dm_plane_helper_funcs);
4562236b 1645
d4e13b0d
AD		 1646 return res;
1647}
4562236b 1648
d4e13b0d
AD		 1649int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
1650 struct drm_plane *plane,
1651 uint32_t crtc_index)
1652{
2ea5e9a8
AG		 1653 struct amdgpu_crtc *acrtc = NULL;
1654 struct amdgpu_plane *cursor_plane;
1655
d4e13b0d 1656 int res = -ENOMEM;
4562236b 1657
2ea5e9a8
AG		 1658 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
1659 if (!cursor_plane)
1660 goto fail;
1661
1662 cursor_plane->base.type = DRM_PLANE_TYPE_CURSOR;
1663 res = amdgpu_dm_plane_init(dm, cursor_plane, 0);
1664
d4e13b0d
AD		 1665 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
1666 if (!acrtc)
1667 goto fail;
4562236b
HW		 1668
1669 res = drm_crtc_init_with_planes(
1670 dm->ddev,
1671 &acrtc->base,
d4e13b0d 1672 plane,
2ea5e9a8 1673 &cursor_plane->base,
4562236b
HW		 1674 &amdgpu_dm_crtc_funcs, NULL);
1675
1676 if (res)
1677 goto fail;
1678
1679 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
1680
10349345
AG		 1681 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
1682 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
4562236b
HW		 1683
1684 acrtc->crtc_id = crtc_index;
1685 acrtc->base.enabled = false;
1686
1687 dm->adev->mode_info.crtcs[crtc_index] = acrtc;
1688 drm_mode_crtc_set_gamma_size(&acrtc->base, 256);
1689
1690 return 0;
2ea5e9a8 1691
4562236b 1692fail:
2ea5e9a8
AG		 1693 if (acrtc)
1694 kfree(acrtc);
1695 if (cursor_plane)
1696 kfree(cursor_plane);
4562236b
HW		 1697 acrtc->crtc_id = -1;
1698 return res;
1699}
1700
2ea5e9a8 1701
4562236b
HW		 1702static int to_drm_connector_type(enum signal_type st)
1703{
1704 switch (st) {
1705 case SIGNAL_TYPE_HDMI_TYPE_A:
1706 return DRM_MODE_CONNECTOR_HDMIA;
1707 case SIGNAL_TYPE_EDP:
1708 return DRM_MODE_CONNECTOR_eDP;
1709 case SIGNAL_TYPE_RGB:
1710 return DRM_MODE_CONNECTOR_VGA;
1711 case SIGNAL_TYPE_DISPLAY_PORT:
1712 case SIGNAL_TYPE_DISPLAY_PORT_MST:
1713 return DRM_MODE_CONNECTOR_DisplayPort;
1714 case SIGNAL_TYPE_DVI_DUAL_LINK:
1715 case SIGNAL_TYPE_DVI_SINGLE_LINK:
1716 return DRM_MODE_CONNECTOR_DVID;
1717 case SIGNAL_TYPE_VIRTUAL:
1718 return DRM_MODE_CONNECTOR_VIRTUAL;
1719
1720 default:
1721 return DRM_MODE_CONNECTOR_Unknown;
1722 }
1723}
1724
1725static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
1726{
1727 const struct drm_connector_helper_funcs *helper =
1728 connector->helper_private;
1729 struct drm_encoder *encoder;
1730 struct amdgpu_encoder *amdgpu_encoder;
1731
1732 encoder = helper->best_encoder(connector);
1733
1734 if (encoder == NULL)
1735 return;
1736
1737 amdgpu_encoder = to_amdgpu_encoder(encoder);
1738
1739 amdgpu_encoder->native_mode.clock = 0;
1740
1741 if (!list_empty(&connector->probed_modes)) {
1742 struct drm_display_mode *preferred_mode = NULL;
1743 list_for_each_entry(preferred_mode,
1744 &connector->probed_modes,
1745 head) {
1746 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
1747 amdgpu_encoder->native_mode = *preferred_mode;
1748 }
1749 break;
1750 }
1751
1752 }
1753}
1754
1755static struct drm_display_mode *amdgpu_dm_create_common_mode(
1756 struct drm_encoder *encoder, char *name,
1757 int hdisplay, int vdisplay)
1758{
1759 struct drm_device *dev = encoder->dev;
1760 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1761 struct drm_display_mode *mode = NULL;
1762 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1763
1764 mode = drm_mode_duplicate(dev, native_mode);
1765
1766 if(mode == NULL)
1767 return NULL;
1768
1769 mode->hdisplay = hdisplay;
1770 mode->vdisplay = vdisplay;
1771 mode->type &= ~DRM_MODE_TYPE_PREFERRED;
1772 strncpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
1773
1774 return mode;
1775
1776}
1777
1778static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
1779 struct drm_connector *connector)
1780{
1781 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1782 struct drm_display_mode *mode = NULL;
1783 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1784 struct amdgpu_connector *amdgpu_connector =
1785 to_amdgpu_connector(connector);
1786 int i;
1787 int n;
1788 struct mode_size {
1789 char name[DRM_DISPLAY_MODE_LEN];
1790 int w;
1791 int h;
1792 }common_modes[] = {
1793 { "640x480", 640, 480},
1794 { "800x600", 800, 600},
1795 { "1024x768", 1024, 768},
1796 { "1280x720", 1280, 720},
1797 { "1280x800", 1280, 800},
1798 {"1280x1024", 1280, 1024},
1799 { "1440x900", 1440, 900},
1800 {"1680x1050", 1680, 1050},
1801 {"1600x1200", 1600, 1200},
1802 {"1920x1080", 1920, 1080},
1803 {"1920x1200", 1920, 1200}
1804 };
1805
1806 n = sizeof(common_modes) / sizeof(common_modes[0]);
1807
1808 for (i = 0; i < n; i++) {
1809 struct drm_display_mode *curmode = NULL;
1810 bool mode_existed = false;
1811
1812 if (common_modes[i].w > native_mode->hdisplay ||
1813 common_modes[i].h > native_mode->vdisplay ||
1814 (common_modes[i].w == native_mode->hdisplay &&
1815 common_modes[i].h == native_mode->vdisplay))
1816 continue;
1817
1818 list_for_each_entry(curmode, &connector->probed_modes, head) {
1819 if (common_modes[i].w == curmode->hdisplay &&
1820 common_modes[i].h == curmode->vdisplay) {
1821 mode_existed = true;
1822 break;
1823 }
1824 }
1825
1826 if (mode_existed)
1827 continue;
1828
1829 mode = amdgpu_dm_create_common_mode(encoder,
1830 common_modes[i].name, common_modes[i].w,
1831 common_modes[i].h);
1832 drm_mode_probed_add(connector, mode);
1833 amdgpu_connector->num_modes++;
1834 }
1835}
1836
1837static void amdgpu_dm_connector_ddc_get_modes(
1838 struct drm_connector *connector,
1839 struct edid *edid)
1840{
1841 struct amdgpu_connector *amdgpu_connector =
1842 to_amdgpu_connector(connector);
1843
1844 if (edid) {
1845 /* empty probed_modes */
1846 INIT_LIST_HEAD(&connector->probed_modes);
1847 amdgpu_connector->num_modes =
1848 drm_add_edid_modes(connector, edid);
1849
1850 drm_edid_to_eld(connector, edid);
1851
1852 amdgpu_dm_get_native_mode(connector);
1853 } else
1854 amdgpu_connector->num_modes = 0;
1855}
1856
1857int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
1858{
1859 const struct drm_connector_helper_funcs *helper =
1860 connector->helper_private;
1861 struct amdgpu_connector *amdgpu_connector =
1862 to_amdgpu_connector(connector);
1863 struct drm_encoder *encoder;
1864 struct edid *edid = amdgpu_connector->edid;
1865
1866 encoder = helper->best_encoder(connector);
1867
1868 amdgpu_dm_connector_ddc_get_modes(connector, edid);
1869 amdgpu_dm_connector_add_common_modes(encoder, connector);
1870 return amdgpu_connector->num_modes;
1871}
1872
1873void amdgpu_dm_connector_init_helper(
1874 struct amdgpu_display_manager *dm,
1875 struct amdgpu_connector *aconnector,
1876 int connector_type,
d0778ebf 1877 struct dc_link *link,
4562236b
HW		 1878 int link_index)
1879{
1880 struct amdgpu_device *adev = dm->ddev->dev_private;
1881
1882 aconnector->connector_id = link_index;
1883 aconnector->dc_link = link;
67a27705
HW		 1884 aconnector->base.interlace_allowed = false;
1885 aconnector->base.doublescan_allowed = false;
1886 aconnector->base.stereo_allowed = false;
4562236b
HW		 1887 aconnector->base.dpms = DRM_MODE_DPMS_OFF;
1888 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
1889
1890 mutex_init(&aconnector->hpd_lock);
1891
1892 /*configure suport HPD hot plug connector_>polled default value is 0
1893 * which means HPD hot plug not supported*/
1894 switch (connector_type) {
1895 case DRM_MODE_CONNECTOR_HDMIA:
1896 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
1897 break;
1898 case DRM_MODE_CONNECTOR_DisplayPort:
1899 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
1900 break;
1901 case DRM_MODE_CONNECTOR_DVID:
1902 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
1903 break;
1904 default:
1905 break;
1906 }
1907
1908 drm_object_attach_property(&aconnector->base.base,
1909 dm->ddev->mode_config.scaling_mode_property,
1910 DRM_MODE_SCALE_NONE);
1911
1912 drm_object_attach_property(&aconnector->base.base,
1913 adev->mode_info.underscan_property,
1914 UNDERSCAN_OFF);
1915 drm_object_attach_property(&aconnector->base.base,
1916 adev->mode_info.underscan_hborder_property,
1917 0);
1918 drm_object_attach_property(&aconnector->base.base,
1919 adev->mode_info.underscan_vborder_property,
1920 0);
1921
1922}
1923
1924int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
1925 struct i2c_msg *msgs, int num)
1926{
1927 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
46df790c 1928 struct ddc_service *ddc_service = i2c->ddc_service;
4562236b
HW		 1929 struct i2c_command cmd;
1930 int i;
1931 int result = -EIO;
1932
1933 cmd.payloads = kzalloc(num * sizeof(struct i2c_payload), GFP_KERNEL);
1934
1935 if (!cmd.payloads)
1936 return result;
1937
1938 cmd.number_of_payloads = num;
1939 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
1940 cmd.speed = 100;
1941
1942 for (i = 0; i < num; i++) {
bb01672c 1943 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
4562236b
HW		 1944 cmd.payloads[i].address = msgs[i].addr;
1945 cmd.payloads[i].length = msgs[i].len;
1946 cmd.payloads[i].data = msgs[i].buf;
1947 }
1948
46df790c
AG		 1949 if (dal_i2caux_submit_i2c_command(
1950 ddc_service->ctx->i2caux,
1951 ddc_service->ddc_pin,
1952 &cmd))
4562236b
HW		 1953 result = num;
1954
1955 kfree(cmd.payloads);
4562236b
HW		 1956 return result;
1957}
1958
1959u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
1960{
1961 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
1962}
1963
1964static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
1965 .master_xfer = amdgpu_dm_i2c_xfer,
1966 .functionality = amdgpu_dm_i2c_func,
1967};
1968
46df790c
AG		 1969static struct amdgpu_i2c_adapter *create_i2c(
1970 struct ddc_service *ddc_service,
1971 int link_index,
1972 int *res)
4562236b 1973{
46df790c 1974 struct amdgpu_device *adev = ddc_service->ctx->driver_context;
4562236b
HW		 1975 struct amdgpu_i2c_adapter *i2c;
1976
1977 i2c = kzalloc(sizeof (struct amdgpu_i2c_adapter), GFP_KERNEL);
4562236b
HW		 1978 i2c->base.owner = THIS_MODULE;
1979 i2c->base.class = I2C_CLASS_DDC;
46df790c 1980 i2c->base.dev.parent = &adev->pdev->dev;
4562236b
HW		 1981 i2c->base.algo = &amdgpu_dm_i2c_algo;
1982 snprintf(i2c->base.name, sizeof (i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
4562236b 1983 i2c_set_adapdata(&i2c->base, i2c);
46df790c 1984 i2c->ddc_service = ddc_service;
4562236b
HW		 1985
1986 return i2c;
1987}
1988
1989/* Note: this function assumes that dc_link_detect() was called for the
1990 * dc_link which will be represented by this aconnector. */
1991int amdgpu_dm_connector_init(
1992 struct amdgpu_display_manager *dm,
1993 struct amdgpu_connector *aconnector,
1994 uint32_t link_index,
1995 struct amdgpu_encoder *aencoder)
1996{
1997 int res = 0;
1998 int connector_type;
1999 struct dc *dc = dm->dc;
d0778ebf 2000 struct dc_link *link = dc_get_link_at_index(dc, link_index);
4562236b 2001 struct amdgpu_i2c_adapter *i2c;
9fb8de78 2002 ((struct dc_link *)link)->priv = aconnector;
4562236b
HW		 2003
2004 DRM_DEBUG_KMS("%s()\n", __func__);
2005
46df790c 2006 i2c = create_i2c(link->ddc, link->link_index, &res);
4562236b
HW		 2007 aconnector->i2c = i2c;
2008 res = i2c_add_adapter(&i2c->base);
2009
2010 if (res) {
2011 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
2012 goto out_free;
2013 }
2014
2015 connector_type = to_drm_connector_type(link->connector_signal);
2016
2017 res = drm_connector_init(
2018 dm->ddev,
2019 &aconnector->base,
2020 &amdgpu_dm_connector_funcs,
2021 connector_type);
2022
2023 if (res) {
2024 DRM_ERROR("connector_init failed\n");
2025 aconnector->connector_id = -1;
2026 goto out_free;
2027 }
2028
2029 drm_connector_helper_add(
2030 &aconnector->base,
2031 &amdgpu_dm_connector_helper_funcs);
2032
2033 amdgpu_dm_connector_init_helper(
2034 dm,
2035 aconnector,
2036 connector_type,
2037 link,
2038 link_index);
2039
2040 drm_mode_connector_attach_encoder(
2041 &aconnector->base, &aencoder->base);
2042
2043 drm_connector_register(&aconnector->base);
2044
2045 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
2046 || connector_type == DRM_MODE_CONNECTOR_eDP)
7c7f5b15 2047 amdgpu_dm_initialize_dp_connector(dm, aconnector);
4562236b
HW		 2048
2049#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
2050 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
2051
2052 /* NOTE: this currently will create backlight device even if a panel
2053 * is not connected to the eDP/LVDS connector.
2054 *
2055 * This is less than ideal but we don't have sink information at this
2056 * stage since detection happens after. We can't do detection earlier
2057 * since MST detection needs connectors to be created first.
2058 */
2059 if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) {
2060 /* Event if registration failed, we should continue with
2061 * DM initialization because not having a backlight control
2062 * is better then a black screen. */
2063 amdgpu_dm_register_backlight_device(dm);
2064
2065 if (dm->backlight_dev)
2066 dm->backlight_link = link;
2067 }
2068#endif
2069
2070out_free:
2071 if (res) {
2072 kfree(i2c);
2073 aconnector->i2c = NULL;
2074 }
2075 return res;
2076}
2077
2078int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
2079{
2080 switch (adev->mode_info.num_crtc) {
2081 case 1:
2082 return 0x1;
2083 case 2:
2084 return 0x3;
2085 case 3:
2086 return 0x7;
2087 case 4:
2088 return 0xf;
2089 case 5:
2090 return 0x1f;
2091 case 6:
2092 default:
2093 return 0x3f;
2094 }
2095}
2096
2097int amdgpu_dm_encoder_init(
2098 struct drm_device *dev,
2099 struct amdgpu_encoder *aencoder,
2100 uint32_t link_index)
2101{
2102 struct amdgpu_device *adev = dev->dev_private;
2103
2104 int res = drm_encoder_init(dev,
2105 &aencoder->base,
2106 &amdgpu_dm_encoder_funcs,
2107 DRM_MODE_ENCODER_TMDS,
2108 NULL);
2109
2110 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
2111
2112 if (!res)
2113 aencoder->encoder_id = link_index;
2114 else
2115 aencoder->encoder_id = -1;
2116
2117 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
2118
2119 return res;
2120}
2121
4c92c92d 2122static bool modeset_required(struct drm_crtc_state *crtc_state)
4562236b 2123{
4c92c92d
AG		 2124 if (!drm_atomic_crtc_needs_modeset(crtc_state))
2125 return false;
4562236b 2126
4c92c92d
AG		 2127 if (!crtc_state->enable)
2128 return false;
4562236b 2129
4c92c92d
AG		 2130 return crtc_state->active;
2131}
4562236b 2132
4c92c92d
AG		 2133static bool modereset_required(struct drm_crtc_state *crtc_state)
2134{
2135 if (!drm_atomic_crtc_needs_modeset(crtc_state))
2136 return false;
4562236b 2137
4c92c92d 2138 return !crtc_state->enable || !crtc_state->active;
4562236b
HW		 2139}
2140
4562236b
HW		 2141static void manage_dm_interrupts(
2142 struct amdgpu_device *adev,
2143 struct amdgpu_crtc *acrtc,
2144 bool enable)
2145{
2146 /*
2147 * this is not correct translation but will work as soon as VBLANK
2148 * constant is the same as PFLIP
2149 */
2150 int irq_type =
2151 amdgpu_crtc_idx_to_irq_type(
2152 adev,
2153 acrtc->crtc_id);
2154
2155 if (enable) {
2156 drm_crtc_vblank_on(&acrtc->base);
2157 amdgpu_irq_get(
2158 adev,
2159 &adev->pageflip_irq,
2160 irq_type);
2161 } else {
4562236b
HW		 2162
2163 amdgpu_irq_put(
2164 adev,
2165 &adev->pageflip_irq,
2166 irq_type);
2167 drm_crtc_vblank_off(&acrtc->base);
2168 }
2169}
2170
4562236b
HW		 2171static bool is_scaling_state_different(
2172 const struct dm_connector_state *dm_state,
2173 const struct dm_connector_state *old_dm_state)
2174{
2175 if (dm_state->scaling != old_dm_state->scaling)
2176 return true;
2177 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
2178 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
2179 return true;
2180 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
2181 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
2182 return true;
2183 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder
2184 || dm_state->underscan_vborder != old_dm_state->underscan_vborder)
2185 return true;
2186 return false;
2187}
2188
da5c47f6
AG		 2189static void remove_stream(
2190 struct amdgpu_device *adev,
2191 struct amdgpu_crtc *acrtc,
2192 const struct dc_stream *stream)
4562236b 2193{
4562236b
HW		 2194 /* this is the update mode case */
2195 if (adev->dm.freesync_module)
da5c47f6 2196 mod_freesync_remove_stream(adev->dm.freesync_module, stream);
ab2541b6 2197
4562236b
HW		 2198 acrtc->otg_inst = -1;
2199 acrtc->enabled = false;
2200}
2201
2ea5e9a8
AG		 2202static void handle_cursor_update(
2203 struct drm_plane *plane,
2204 struct drm_plane_state *old_plane_state)
2205{
2206 if (!plane->state->fb && !old_plane_state->fb)
2207 return;
2208
2209 /* Check if it's a cursor on/off update or just cursor move*/
2210 if (plane->state->fb == old_plane_state->fb)
2211 dm_crtc_cursor_move(
2212 plane->state->crtc,
2213 plane->state->crtc_x,
2214 plane->state->crtc_y);
2215 else {
2216 struct amdgpu_framebuffer *afb =
2217 to_amdgpu_framebuffer(plane->state->fb);
2218 dm_crtc_cursor_set(
2219 (!!plane->state->fb) ?
2220 plane->state->crtc :
2221 old_plane_state->crtc,
2222 (!!plane->state->fb) ?
2223 afb->address :
2224 0,
2225 plane->state->crtc_w,
2226 plane->state->crtc_h);
2227 }
2228}
2229
54f5499a 2230
1159898a
AG		 2231static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
2232{
2233
2234 assert_spin_locked(&acrtc->base.dev->event_lock);
2235 WARN_ON(acrtc->event);
2236
2237 acrtc->event = acrtc->base.state->event;
2238
2239 /* Set the flip status */
2240 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
2241
2242 /* Mark this event as consumed */
2243 acrtc->base.state->event = NULL;
2244
2245 DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
2246 acrtc->crtc_id);
2247}
2248
54f5499a
AG		 2249/*
2250 * Executes flip
2251 *
2252 * Waits on all BO's fences and for proper vblank count
2253 */
2254static void amdgpu_dm_do_flip(
2255 struct drm_crtc *crtc,
2256 struct drm_framebuffer *fb,
2257 uint32_t target)
2258{
2259 unsigned long flags;
2260 uint32_t target_vblank;
2261 int r, vpos, hpos;
2262 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2263 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
2264 struct amdgpu_bo *abo = gem_to_amdgpu_bo(afb->obj);
2265 struct amdgpu_device *adev = crtc->dev->dev_private;
2266 bool async_flip = (acrtc->flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
70470154
AG		 2267 struct dc_flip_addrs addr = { {0} };
2268 struct dc_surface_update surface_updates[1] = { {0} };
da5c47f6
AG		 2269 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
2270
54f5499a 2271
00d7930c
MK		 2272 /* Prepare wait for target vblank early - before the fence-waits */
2273 target_vblank = target - drm_crtc_vblank_count(crtc) +
2274 amdgpu_get_vblank_counter_kms(crtc->dev, acrtc->crtc_id);
54f5499a
AG		 2275
2276 /*TODO This might fail and hence better not used, wait
2277 * explicitly on fences instead
2278 * and in general should be called for
2279 * blocking commit to as per framework helpers
2280 * */
2281 r = amdgpu_bo_reserve(abo, true);
2282 if (unlikely(r != 0)) {
2283 DRM_ERROR("failed to reserve buffer before flip\n");
70470154 2284 WARN_ON(1);
54f5499a
AG		 2285 }
2286
2287 /* Wait for all fences on this FB */
2288 WARN_ON(reservation_object_wait_timeout_rcu(abo->tbo.resv, true, false,
2289 MAX_SCHEDULE_TIMEOUT) < 0);
2290
2291 amdgpu_bo_unreserve(abo);
2292
54f5499a
AG		 2293 /* Wait until we're out of the vertical blank period before the one
2294 * targeted by the flip
2295 */
54f5499a
AG		 2296 while ((acrtc->enabled &&
2297 (amdgpu_get_crtc_scanoutpos(adev->ddev, acrtc->crtc_id, 0,
2298 &vpos, &hpos, NULL, NULL,
2299 &crtc->hwmode)
2300 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
2301 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
2302 (int)(target_vblank -
2303 amdgpu_get_vblank_counter_kms(adev->ddev, acrtc->crtc_id)) > 0)) {
2304 usleep_range(1000, 1100);
2305 }
2306
2307 /* Flip */
2308 spin_lock_irqsave(&crtc->dev->event_lock, flags);
2309 /* update crtc fb */
2310 crtc->primary->fb = fb;
2311
70470154 2312 WARN_ON(acrtc->pflip_status != AMDGPU_FLIP_NONE);
da5c47f6 2313 WARN_ON(!acrtc_state->stream);
70470154
AG		 2314
2315 addr.address.grph.addr.low_part = lower_32_bits(afb->address);
2316 addr.address.grph.addr.high_part = upper_32_bits(afb->address);
2317 addr.flip_immediate = async_flip;
2318
2319
1159898a
AG		 2320 if (acrtc->base.state->event)
2321 prepare_flip_isr(acrtc);
70470154 2322
da5c47f6 2323 surface_updates->surface = dc_stream_get_status(acrtc_state->stream)->surfaces[0];
70470154
AG		 2324 surface_updates->flip_addr = &addr;
2325
2326
da5c47f6 2327 dc_update_surfaces_and_stream(adev->dm.dc, surface_updates, 1, acrtc_state->stream, NULL);
70470154
AG		 2328
2329 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n",
2330 __func__,
2331 addr.address.grph.addr.high_part,
2332 addr.address.grph.addr.low_part);
2333
54f5499a
AG		 2334
2335 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
54f5499a
AG		 2336}
2337
bdc79f8e 2338static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state,
0430d52b
S		 2339 struct drm_device *dev,
2340 struct amdgpu_display_manager *dm,
bdc79f8e
AG		 2341 struct drm_crtc *pcrtc,
2342 bool *wait_for_vblank)
129eed72
HW		 2343{
2344 uint32_t i;
2345 struct drm_plane *plane;
2346 struct drm_plane_state *old_plane_state;
0430d52b 2347 const struct dc_stream *dc_stream_attach;
e12cfcb1 2348 struct dc_surface *dc_surfaces_constructed[MAX_SURFACES];
1159898a 2349 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
da5c47f6 2350 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(pcrtc->state);
0430d52b 2351 int planes_count = 0;
d7e3316c 2352 unsigned long flags;
129eed72
HW		 2353
2354 /* update planes when needed */
2355 for_each_plane_in_state(state, plane, old_plane_state, i) {
2356 struct drm_plane_state *plane_state = plane->state;
2357 struct drm_crtc *crtc = plane_state->crtc;
2358 struct drm_framebuffer *fb = plane_state->fb;
129eed72 2359 bool pflip_needed;
d7e3316c 2360 struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state);
129eed72 2361
2ea5e9a8
AG		 2362 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
2363 handle_cursor_update(plane, old_plane_state);
2364 continue;
2365 }
2366
d7e3316c
AG		 2367 if (!fb || !crtc || pcrtc != crtc || !crtc->state->active ||
2368 (!crtc->state->planes_changed &&
2369 !pcrtc->state->color_mgmt_changed))
129eed72
HW		 2370 continue;
2371
129eed72 2372 pflip_needed = !state->allow_modeset;
d7e3316c
AG		 2373
2374 spin_lock_irqsave(&crtc->dev->event_lock, flags);
2375 if (acrtc_attach->pflip_status != AMDGPU_FLIP_NONE) {
2376 DRM_ERROR("add_surface: acrtc %d, already busy\n",
2377 acrtc_attach->crtc_id);
2378 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
2379 /* In comit tail framework this cannot happen */
2380 WARN_ON(1);
2381 }
2382 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
2383
bdc79f8e 2384 if (!pflip_needed) {
d7e3316c 2385 WARN_ON(!dm_plane_state->surface);
129eed72 2386
d7e3316c 2387 dc_surfaces_constructed[planes_count] = dm_plane_state->surface;
ccaa7389 2388
da5c47f6 2389 dc_stream_attach = acrtc_state->stream;
1159898a
AG		 2390 planes_count++;
2391
bdc79f8e 2392 } else if (crtc->state->planes_changed) {
1159898a
AG		 2393 /* Assume even ONE crtc with immediate flip means
2394 * entire can't wait for VBLANK
2395 * TODO Check if it's correct
2396 */
bdc79f8e
AG		 2397 *wait_for_vblank =
2398 acrtc_attach->flip_flags & DRM_MODE_PAGE_FLIP_ASYNC ?
2399 false : true;
2400
e29088b2
LSL		 2401 /* TODO: Needs rework for multiplane flip */
2402 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
2403 drm_crtc_vblank_get(crtc);
2404
bdc79f8e
AG		 2405 amdgpu_dm_do_flip(
2406 crtc,
2407 fb,
2408 drm_crtc_vblank_count(crtc) + *wait_for_vblank);
2409
1159898a
AG		 2410 /*TODO BUG remove ASAP in 4.12 to avoid race between worker and flip IOCTL */
2411
bdc79f8e
AG		 2412 /*clean up the flags for next usage*/
2413 acrtc_attach->flip_flags = 0;
0430d52b 2414 }
bdc79f8e 2415
0430d52b 2416 }
129eed72 2417
0430d52b 2418 if (planes_count) {
1159898a
AG		 2419 unsigned long flags;
2420
2421 if (pcrtc->state->event) {
2422
2423 drm_crtc_vblank_get(pcrtc);
2424
2425 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
2426 prepare_flip_isr(acrtc_attach);
2427 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
2428 }
2429
0430d52b
S		 2430 if (false == dc_commit_surfaces_to_stream(dm->dc,
2431 dc_surfaces_constructed,
2432 planes_count,
1159898a 2433 dc_stream_attach))
0430d52b 2434 dm_error("%s: Failed to attach surface!\n", __func__);
1159898a
AG		 2435 } else {
2436 /*TODO BUG Here should go disable planes on CRTC. */
129eed72
HW		 2437 }
2438}
2439
da5c47f6
AG		 2440
2441int amdgpu_dm_atomic_commit(
2442 struct drm_device *dev,
2443 struct drm_atomic_state *state,
2444 bool nonblock)
2445{
2446 struct drm_crtc *crtc;
2447 struct drm_crtc_state *new_state;
2448 struct amdgpu_device *adev = dev->dev_private;
2449 int i;
2450
2451 /*
2452 * We evade vblanks and pflips on crtc that
2453 * should be changed. We do it here to flush & disable
2454 * interrupts before drm_swap_state is called in drm_atomic_helper_commit
2455 * it will update crtc->dm_crtc_state->stream pointer which is used in
2456 * the ISRs.
2457 */
2458 for_each_crtc_in_state(state, crtc, new_state, i) {
2459 struct dm_crtc_state *old_acrtc_state = to_dm_crtc_state(crtc->state);
2460 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2461
2462 if (drm_atomic_crtc_needs_modeset(new_state) && old_acrtc_state->stream)
2463 manage_dm_interrupts(adev, acrtc, false);
2464 }
2465
2466 return drm_atomic_helper_commit(dev, state, nonblock);
2467
2468 /*TODO Handle EINTR, reenable IRQ*/
2469}
2470
54f5499a
AG		 2471void amdgpu_dm_atomic_commit_tail(
2472 struct drm_atomic_state *state)
4562236b 2473{
54f5499a 2474 struct drm_device *dev = state->dev;
4562236b
HW		 2475 struct amdgpu_device *adev = dev->dev_private;
2476 struct amdgpu_display_manager *dm = &adev->dm;
7cf2c840 2477 struct dm_atomic_state *dm_state;
0430d52b 2478 uint32_t i, j;
4562236b 2479 uint32_t new_crtcs_count = 0;
0430d52b 2480 struct drm_crtc *crtc, *pcrtc;
4562236b 2481 struct drm_crtc_state *old_crtc_state;
ab2541b6
AC		 2482 struct amdgpu_crtc *new_crtcs[MAX_STREAMS];
2483 const struct dc_stream *new_stream;
54f5499a
AG		 2484 unsigned long flags;
2485 bool wait_for_vblank = true;
ccaa7389
AG		 2486 struct drm_connector *connector;
2487 struct drm_connector_state *old_conn_state;
da5c47f6 2488 struct dm_crtc_state *old_acrtc_state, *new_acrtc_state;
4562236b
HW		 2489
2490 drm_atomic_helper_update_legacy_modeset_state(dev, state);
7cf2c840
HW		 2491
2492 dm_state = to_dm_atomic_state(state);
2493
4562236b
HW		 2494 /* update changed items */
2495 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
da5c47f6 2496 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4562236b 2497 struct drm_crtc_state *new_state = crtc->state;
da5c47f6
AG		 2498 new_acrtc_state = to_dm_crtc_state(new_state);
2499 old_acrtc_state = to_dm_crtc_state(old_crtc_state);
4562236b 2500
4c92c92d
AG		 2501 DRM_DEBUG_KMS(
2502 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
2503 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
2504 "connectors_changed:%d\n",
2505 acrtc->crtc_id,
2506 new_state->enable,
2507 new_state->active,
2508 new_state->planes_changed,
2509 new_state->mode_changed,
2510 new_state->active_changed,
2511 new_state->connectors_changed);
2512
4562236b
HW		 2513 /* handles headless hotplug case, updating new_state and
2514 * aconnector as needed
2515 */
2516
4c92c92d 2517 if (modeset_required(new_state)) {
4562236b
HW		 2518
2519 DRM_INFO("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
2520
da5c47f6 2521 if (!new_acrtc_state->stream) {
4562236b 2522 /*
da5c47f6
AG		 2523 * this could happen because of issues with
2524 * userspace notifications delivery.
2525 * In this case userspace tries to set mode on
2526 * display which is disconnect in fact.
2527 * dc_sink in NULL in this case on aconnector.
2528 * We expect reset mode will come soon.
2529 *
2530 * This can also happen when unplug is done
2531 * during resume sequence ended
2532 *
2533 * In this case, we want to pretend we still
2534 * have a sink to keep the pipe running so that
2535 * hw state is consistent with the sw state
2536 */
ab2541b6 2537 DRM_DEBUG_KMS("%s: Failed to create new stream for crtc %d\n",
4562236b 2538 __func__, acrtc->base.base.id);
da5c47f6 2539 continue;
4562236b
HW		 2540 }
2541
4562236b 2542
da5c47f6
AG		 2543 if (old_acrtc_state->stream)
2544 remove_stream(adev, acrtc, old_acrtc_state->stream);
2545
e2c7bb12 2546
4562236b
HW		 2547 /*
2548 * this loop saves set mode crtcs
2549 * we needed to enable vblanks once all
ab2541b6 2550 * resources acquired in dc after dc_commit_streams
4562236b 2551 */
da5c47f6
AG		 2552
2553 /*TODO move all this into dm_crtc_state, get rid of
2554 * new_crtcs array and use old and new atomic states
2555 * instead
2556 */
4562236b
HW		 2557 new_crtcs[new_crtcs_count] = acrtc;
2558 new_crtcs_count++;
2559
4562236b
HW		 2560 acrtc->enabled = true;
2561 acrtc->hw_mode = crtc->state->mode;
2562 crtc->hwmode = crtc->state->mode;
4c92c92d 2563 } else if (modereset_required(new_state)) {
4562236b 2564 DRM_INFO("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
da5c47f6 2565
4562236b 2566 /* i.e. reset mode */
da5c47f6
AG		 2567 if (old_acrtc_state->stream)
2568 remove_stream(adev, acrtc, old_acrtc_state->stream);
4c92c92d 2569 }
4562236b
HW		 2570 } /* for_each_crtc_in_state() */
2571
4562236b 2572 /*
ab2541b6 2573 * Add streams after required streams from new and replaced streams
4562236b
HW		 2574 * are removed from freesync module
2575 */
2576 if (adev->dm.freesync_module) {
2577 for (i = 0; i < new_crtcs_count; i++) {
2578 struct amdgpu_connector *aconnector = NULL;
da5c47f6
AG		 2579 new_acrtc_state = to_dm_crtc_state(new_crtcs[i]->base.state);
2580
2581 new_stream = new_acrtc_state->stream;
4562236b
HW		 2582 aconnector =
2583 amdgpu_dm_find_first_crct_matching_connector(
2584 state,
2585 &new_crtcs[i]->base,
2586 false);
2587 if (!aconnector) {
2588 DRM_INFO(
2589 "Atomic commit: Failed to find connector for acrtc id:%d "
2590 "skipping freesync init\n",
2591 new_crtcs[i]->crtc_id);
2592 continue;
2593 }
2594
ab2541b6
AC		 2595 mod_freesync_add_stream(adev->dm.freesync_module,
2596 new_stream, &aconnector->caps);
4562236b
HW		 2597 }
2598 }
2599
3b42a1c0
AG		 2600 if (dm_state->context)
2601 WARN_ON(!dc_commit_context(dm->dc, dm_state->context));
4562236b 2602
89a1fc59 2603
4562236b
HW		 2604 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2605 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
da5c47f6 2606 new_acrtc_state = to_dm_crtc_state(crtc->state);
4562236b 2607
da5c47f6
AG		 2608 if (new_acrtc_state->stream != NULL) {
2609 const struct dc_stream_status *status =
2610 dc_stream_get_status(new_acrtc_state->stream);
e2c7bb12
HW		 2611
2612 if (!status)
da5c47f6 2613 DC_ERR("got no status for stream %p on acrtc%p\n", new_acrtc_state->stream, acrtc);
e2c7bb12
HW		 2614 else
2615 acrtc->otg_inst = status->primary_otg_inst;
2616 }
4562236b
HW		 2617 }
2618
da5c47f6
AG		 2619 /* Handle scaling and undersacn changes*/
2620 for_each_connector_in_state(state, connector, old_conn_state, i) {
2621 struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
2622 struct dm_connector_state *con_new_state =
2623 to_dm_connector_state(aconnector->base.state);
2624 struct dm_connector_state *con_old_state =
2625 to_dm_connector_state(old_conn_state);
2626 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(con_new_state->base.crtc);
e12cfcb1 2627 struct dc_stream_status *status = NULL;
da5c47f6
AG		 2628
2629 /* Skip any modesets/resets */
2630 if (!acrtc || drm_atomic_crtc_needs_modeset(acrtc->base.state))
2631 continue;
2632
2633 /* Skip any thing not scale or underscan changes */
2634 if (!is_scaling_state_different(con_new_state, con_old_state))
2635 continue;
2636
2637 new_acrtc_state = to_dm_crtc_state(acrtc->base.state);
2638
2639 update_stream_scaling_settings(&con_new_state->base.crtc->mode,
2640 con_new_state, (struct dc_stream *)new_acrtc_state->stream);
2641
2642 status = dc_stream_get_status(new_acrtc_state->stream);
2643 WARN_ON(!status);
2644 WARN_ON(!status->surface_count);
2645
2646 if (!new_acrtc_state->stream)
2647 continue;
2648
2649 /*TODO How it works with MPO ?*/
2650 if (!dc_commit_surfaces_to_stream(
2651 dm->dc,
e12cfcb1 2652 status->surfaces,
da5c47f6
AG		 2653 status->surface_count,
2654 new_acrtc_state->stream))
2655 dm_error("%s: Failed to update stream scaling!\n", __func__);
2656 }
2657
4562236b
HW		 2658 for (i = 0; i < new_crtcs_count; i++) {
2659 /*
2660 * loop to enable interrupts on newly arrived crtc
2661 */
2662 struct amdgpu_crtc *acrtc = new_crtcs[i];
da5c47f6 2663 new_acrtc_state = to_dm_crtc_state(acrtc->base.state);
4562236b 2664
ab2541b6
AC		 2665 if (adev->dm.freesync_module)
2666 mod_freesync_notify_mode_change(
da5c47f6 2667 adev->dm.freesync_module, &new_acrtc_state->stream, 1);
4562236b
HW		 2668
2669 manage_dm_interrupts(adev, acrtc, true);
4562236b
HW		 2670 }
2671
1159898a
AG		 2672 /* update planes when needed per crtc*/
2673 for_each_crtc_in_state(state, pcrtc, old_crtc_state, j) {
da5c47f6 2674 new_acrtc_state = to_dm_crtc_state(pcrtc->state);
1159898a 2675
da5c47f6 2676 if (new_acrtc_state->stream)
1159898a
AG		 2677 amdgpu_dm_commit_surfaces(state, dev, dm, pcrtc, &wait_for_vblank);
2678 }
2679
4562236b 2680
1159898a
AG		 2681 /*
2682 * send vblank event on all events not handled in flip and
2683 * mark consumed event for drm_atomic_helper_commit_hw_done
54f5499a
AG		 2684 */
2685 spin_lock_irqsave(&adev->ddev->event_lock, flags);
2686 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
2687 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2688
1159898a
AG		 2689 if (acrtc->base.state->event)
2690 drm_send_event_locked(dev, &crtc->state->event->base);
2691
2692 acrtc->base.state->event = NULL;
54f5499a
AG		 2693 }
2694 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
2695
2696 /* Signal HW programming completion */
2697 drm_atomic_helper_commit_hw_done(state);
2698
2699 if (wait_for_vblank)
2700 drm_atomic_helper_wait_for_vblanks(dev, state);
2701
54f5499a 2702 drm_atomic_helper_cleanup_planes(dev, state);
4562236b 2703}
92cc37fb
AG		 2704
2705
2706static int dm_force_atomic_commit(struct drm_connector *connector)
2707{
2708 int ret = 0;
2709 struct drm_device *ddev = connector->dev;
2710 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
2711 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
2712 struct drm_plane *plane = disconnected_acrtc->base.primary;
2713 struct drm_connector_state *conn_state;
2714 struct drm_crtc_state *crtc_state;
2715 struct drm_plane_state *plane_state;
2716
2717 if (!state)
2718 return -ENOMEM;
2719
2720 state->acquire_ctx = ddev->mode_config.acquire_ctx;
2721
2722 /* Construct an atomic state to restore previous display setting */
2723
2724 /*
2725 * Attach connectors to drm_atomic_state
2726 */
2727 conn_state = drm_atomic_get_connector_state(state, connector);
2728
2729 ret = PTR_ERR_OR_ZERO(conn_state);
2730 if (ret)
2731 goto err;
2732
2733 /* Attach crtc to drm_atomic_state*/
2734 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
2735
2736 ret = PTR_ERR_OR_ZERO(crtc_state);
2737 if (ret)
2738 goto err;
2739
2740 /* force a restore */
2741 crtc_state->mode_changed = true;
2742
2743 /* Attach plane to drm_atomic_state */
2744 plane_state = drm_atomic_get_plane_state(state, plane);
2745
2746 ret = PTR_ERR_OR_ZERO(plane_state);
2747 if (ret)
2748 goto err;
2749
2750
2751 /* Call commit internally with the state we just constructed */
2752 ret = drm_atomic_commit(state);
2753 if (!ret)
2754 return 0;
2755
2756err:
2757 DRM_ERROR("Restoring old state failed with %i\n", ret);
2758 drm_atomic_state_put(state);
2759
2760 return ret;
2761}
2762
4562236b
HW		 2763/*
2764 * This functions handle all cases when set mode does not come upon hotplug.
2765 * This include when the same display is unplugged then plugged back into the
2766 * same port and when we are running without usermode desktop manager supprot
2767 */
2768void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector *connector)
2769{
4562236b
HW		 2770 struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
2771 struct amdgpu_crtc *disconnected_acrtc;
da5c47f6 2772 struct dm_crtc_state *acrtc_state;
4562236b
HW		 2773
2774 if (!aconnector->dc_sink || !connector->state || !connector->encoder)
2775 return;
2776
2777 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
da5c47f6 2778 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
4562236b 2779
da5c47f6 2780 if (!disconnected_acrtc || !acrtc_state->stream)
4562236b
HW		 2781 return;
2782
4562236b
HW		 2783 /*
2784 * If the previous sink is not released and different from the current,
2785 * we deduce we are in a state where we can not rely on usermode call
2786 * to turn on the display, so we do it here
2787 */
da5c47f6 2788 if (acrtc_state->stream->sink != aconnector->dc_sink)
92cc37fb 2789 dm_force_atomic_commit(&aconnector->base);
4562236b
HW		 2790}
2791
2792static uint32_t add_val_sets_surface(
2793 struct dc_validation_set *val_sets,
2794 uint32_t set_count,
ab2541b6 2795 const struct dc_stream *stream,
e12cfcb1 2796 struct dc_surface *surface)
4562236b 2797{
0430d52b 2798 uint32_t i = 0, j = 0;
4562236b
HW		 2799
2800 while (i < set_count) {
0430d52b
S		 2801 if (val_sets[i].stream == stream) {
2802 while (val_sets[i].surfaces[j])
2803 j++;
4562236b 2804 break;
0430d52b 2805 }
4562236b
HW		 2806 ++i;
2807 }
2808
0430d52b 2809 val_sets[i].surfaces[j] = surface;
4562236b
HW		 2810 val_sets[i].surface_count++;
2811
2812 return val_sets[i].surface_count;
2813}
2814
ab2541b6 2815static uint32_t update_in_val_sets_stream(
4562236b 2816 struct dc_validation_set *val_sets,
4562236b 2817 uint32_t set_count,
ab2541b6
AC		 2818 const struct dc_stream *old_stream,
2819 const struct dc_stream *new_stream,
4562236b
HW		 2820 struct drm_crtc *crtc)
2821{
2822 uint32_t i = 0;
2823
2824 while (i < set_count) {
ab2541b6 2825 if (val_sets[i].stream == old_stream)
4562236b
HW		 2826 break;
2827 ++i;
2828 }
2829
ab2541b6 2830 val_sets[i].stream = new_stream;
4562236b 2831
da5c47f6 2832 if (i == set_count)
4562236b
HW		 2833 /* nothing found. add new one to the end */
2834 return set_count + 1;
4562236b
HW		 2835
2836 return set_count;
2837}
2838
2839static uint32_t remove_from_val_sets(
2840 struct dc_validation_set *val_sets,
2841 uint32_t set_count,
ab2541b6 2842 const struct dc_stream *stream)
4562236b
HW		 2843{
2844 int i;
2845
2846 for (i = 0; i < set_count; i++)
ab2541b6 2847 if (val_sets[i].stream == stream)
4562236b
HW		 2848 break;
2849
2850 if (i == set_count) {
2851 /* nothing found */
2852 return set_count;
2853 }
2854
2855 set_count--;
2856
2857 for (; i < set_count; i++) {
2858 val_sets[i] = val_sets[i + 1];
2859 }
2860
2861 return set_count;
2862}
2863
03c8a5fe
AG		 2864/*`
2865 * Grabs all modesetting locks to serialize against any blocking commits,
2866 * Waits for completion of all non blocking commits.
2867 */
f0129a53 2868static int do_aquire_global_lock(
03c8a5fe
AG		 2869 struct drm_device *dev,
2870 struct drm_atomic_state *state)
2871{
2872 struct drm_crtc *crtc;
2873 struct drm_crtc_commit *commit;
2874 long ret;
2875
2876 /* Adding all modeset locks to aquire_ctx will
2877 * ensure that when the framework release it the
2878 * extra locks we are locking here will get released to
2879 */
f0129a53
AG		 2880 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
2881 if (ret)
2882 return ret;
03c8a5fe
AG		 2883
2884 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2885 spin_lock(&crtc->commit_lock);
2886 commit = list_first_entry_or_null(&crtc->commit_list,
2887 struct drm_crtc_commit, commit_entry);
2888 if (commit)
2889 drm_crtc_commit_get(commit);
2890 spin_unlock(&crtc->commit_lock);
2891
2892 if (!commit)
2893 continue;
2894
2895 /* Make sure all pending HW programming completed and
2896 * page flips done
2897 */
f0129a53
AG		 2898 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
2899
2900 if (ret > 0)
2901 ret = wait_for_completion_interruptible_timeout(
2902 &commit->flip_done, 10*HZ);
2903
03c8a5fe 2904 if (ret == 0)
4c0732bf 2905 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
f0129a53
AG		 2906 "timed out\n", crtc->base.id, crtc->name);
2907
03c8a5fe
AG		 2908 drm_crtc_commit_put(commit);
2909 }
f0129a53
AG		 2910
2911 return ret < 0 ? ret : 0;
03c8a5fe
AG		 2912}
2913
4562236b
HW		 2914int amdgpu_dm_atomic_check(struct drm_device *dev,
2915 struct drm_atomic_state *state)
2916{
a6818a32 2917 struct dm_atomic_state *dm_state;
4562236b
HW		 2918 struct drm_crtc *crtc;
2919 struct drm_crtc_state *crtc_state;
2920 struct drm_plane *plane;
2921 struct drm_plane_state *plane_state;
2922 int i, j;
2923 int ret;
4562236b
HW		 2924 struct amdgpu_device *adev = dev->dev_private;
2925 struct dc *dc = adev->dm.dc;
ccaa7389
AG		 2926 struct drm_connector *connector;
2927 struct drm_connector_state *conn_state;
da5c47f6
AG		 2928 int set_count;
2929 struct dc_validation_set set[MAX_STREAMS] = { { 0 } };
2930 struct dm_crtc_state *old_acrtc_state, *new_acrtc_state;
2931
bdc79f8e
AG		 2932 /*
2933 * This bool will be set for true for any modeset/reset
3b42a1c0 2934 * or surface update which implies non fast surface update.
bdc79f8e 2935 */
3b42a1c0 2936 bool lock_and_validation_needed = false;
4562236b
HW		 2937
2938 ret = drm_atomic_helper_check(dev, state);
2939
2940 if (ret) {
d7e3316c 2941 DRM_ERROR("Atomic state validation failed with error :%d !\n", ret);
4562236b
HW		 2942 return ret;
2943 }
2944
a6818a32
HW		 2945 dm_state = to_dm_atomic_state(state);
2946
4562236b 2947 /* copy existing configuration */
da5c47f6 2948 set_count = 0;
4562236b
HW		 2949 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2950
da5c47f6 2951 old_acrtc_state = to_dm_crtc_state(crtc->state);
4562236b 2952
da5c47f6
AG		 2953 if (old_acrtc_state->stream) {
2954 dc_stream_retain(old_acrtc_state->stream);
2955 set[set_count].stream = old_acrtc_state->stream;
da5c47f6 2956 ++set_count;
4562236b
HW		 2957 }
2958 }
2959
2960 /* update changed items */
2961 for_each_crtc_in_state(state, crtc, crtc_state, i) {
2962 struct amdgpu_crtc *acrtc = NULL;
2963 struct amdgpu_connector *aconnector = NULL;
da5c47f6
AG		 2964 old_acrtc_state = to_dm_crtc_state(crtc->state);
2965 new_acrtc_state = to_dm_crtc_state(crtc_state);
4562236b
HW		 2966 acrtc = to_amdgpu_crtc(crtc);
2967
2968 aconnector = amdgpu_dm_find_first_crct_matching_connector(state, crtc, true);
2969
4c92c92d
AG		 2970 DRM_DEBUG_KMS(
2971 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
2972 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
2973 "connectors_changed:%d\n",
2974 acrtc->crtc_id,
2975 crtc_state->enable,
2976 crtc_state->active,
2977 crtc_state->planes_changed,
2978 crtc_state->mode_changed,
2979 crtc_state->active_changed,
2980 crtc_state->connectors_changed);
2981
2982 if (modeset_required(crtc_state)) {
4562236b 2983
ab2541b6 2984 struct dc_stream *new_stream = NULL;
4562236b 2985 struct drm_connector_state *conn_state = NULL;
a6818a32 2986 struct dm_connector_state *dm_conn_state = NULL;
4562236b
HW		 2987
2988 if (aconnector) {
2989 conn_state = drm_atomic_get_connector_state(state, &aconnector->base);
d7e3316c
AG		 2990 if (IS_ERR(conn_state)) {
2991 ret = PTR_ERR_OR_ZERO(conn_state);
eb78d83e 2992 goto fail;
d7e3316c
AG		 2993 }
2994
a6818a32 2995 dm_conn_state = to_dm_connector_state(conn_state);
4562236b
HW		 2996 }
2997
a6818a32 2998 new_stream = create_stream_for_sink(aconnector, &crtc_state->mode, dm_conn_state);
4562236b
HW		 2999
3000 /*
ab2541b6 3001 * we can have no stream on ACTION_SET if a display
4562236b
HW		 3002 * was disconnected during S3, in this case it not and
3003 * error, the OS will be updated after detection, and
3004 * do the right thing on next atomic commit
3005 */
ab2541b6
AC		 3006 if (!new_stream) {
3007 DRM_DEBUG_KMS("%s: Failed to create new stream for crtc %d\n",
4562236b
HW		 3008 __func__, acrtc->base.base.id);
3009 break;
3010 }
3011
da5c47f6
AG		 3012 if (new_acrtc_state->stream)
3013 dc_stream_release(new_acrtc_state->stream);
d7e3316c 3014
da5c47f6
AG		 3015 new_acrtc_state->stream = new_stream;
3016
3017 set_count = update_in_val_sets_stream(
3018 set,
da5c47f6
AG		 3019 set_count,
3020 old_acrtc_state->stream,
3021 new_acrtc_state->stream,
4562236b
HW		 3022 crtc);
3023
3b42a1c0 3024 lock_and_validation_needed = true;
4562236b 3025
4c92c92d
AG		 3026 } else if (modereset_required(crtc_state)) {
3027
4562236b 3028 /* i.e. reset mode */
da5c47f6
AG		 3029 if (new_acrtc_state->stream) {
3030 set_count = remove_from_val_sets(
3031 set,
3032 set_count,
3033 new_acrtc_state->stream);
3034
3035 dc_stream_release(new_acrtc_state->stream);
3036 new_acrtc_state->stream = NULL;
3037
3b42a1c0 3038 lock_and_validation_needed = true;
4562236b 3039 }
4562236b
HW		 3040 }
3041
2ea5e9a8 3042
4562236b 3043 /*
2ea5e9a8
AG		 3044 * Hack: Commit needs planes right now, specifically for gamma
3045 * TODO rework commit to check CRTC for gamma change
4562236b 3046 */
2ea5e9a8 3047 if (crtc_state->color_mgmt_changed) {
4562236b 3048
2ea5e9a8
AG		 3049 ret = drm_atomic_add_affected_planes(state, crtc);
3050 if (ret)
eb78d83e 3051 goto fail;
2ea5e9a8 3052 }
4562236b
HW		 3053 }
3054
ccaa7389 3055 /* Check scaling and undersacn changes*/
da5c47f6
AG		 3056 /*TODO Removed scaling changes validation due to inability to commit
3057 * new stream into context w\o causing full reset. Need to
3058 * decide how to handle.
3059 */
ccaa7389
AG		 3060 for_each_connector_in_state(state, connector, conn_state, i) {
3061 struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
3062 struct dm_connector_state *con_old_state =
3063 to_dm_connector_state(aconnector->base.state);
3064 struct dm_connector_state *con_new_state =
3065 to_dm_connector_state(conn_state);
3066 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(con_new_state->base.crtc);
ccaa7389
AG		 3067
3068 /* Skip any modesets/resets */
4c92c92d 3069 if (!acrtc || drm_atomic_crtc_needs_modeset(acrtc->base.state))
ccaa7389
AG		 3070 continue;
3071
3072 /* Skip any thing not scale or underscan chnages */
3073 if (!is_scaling_state_different(con_new_state, con_old_state))
3074 continue;
3075
3b42a1c0 3076 lock_and_validation_needed = true;
ccaa7389
AG		 3077 }
3078
d7e3316c
AG		 3079 for_each_crtc_in_state(state, crtc, crtc_state, i) {
3080 new_acrtc_state = to_dm_crtc_state(crtc_state);
3081
4562236b 3082 for_each_plane_in_state(state, plane, plane_state, j) {
d7e3316c 3083 struct drm_crtc *plane_crtc = plane_state->crtc;
4562236b 3084 struct drm_framebuffer *fb = plane_state->fb;
54f5499a 3085 bool pflip_needed;
d7e3316c 3086 struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state);
4562236b 3087
2ea5e9a8
AG		 3088 /*TODO Implement atomic check for cursor plane */
3089 if (plane->type == DRM_PLANE_TYPE_CURSOR)
3090 continue;
4562236b 3091
d7e3316c
AG		 3092 if (!fb || !plane_crtc || crtc != plane_crtc ||
3093 (!crtc_state->planes_changed &&
3094 !crtc_state->color_mgmt_changed) ||
3095 !crtc_state->active)
4562236b
HW		 3096 continue;
3097
d7e3316c 3098 WARN_ON(!new_acrtc_state->stream);
4562236b 3099
2d60ded1 3100 pflip_needed = !state->allow_modeset;
83dc2117 3101 if (!pflip_needed) {
4562236b
HW		 3102 struct dc_surface *surface;
3103
4562236b 3104 surface = dc_create_surface(dc);
d7e3316c
AG		 3105
3106 ret = fill_plane_attributes(
3107 plane_crtc->dev->dev_private,
4562236b
HW		 3108 surface,
3109 plane_state,
d7e3316c 3110 crtc_state,
4562236b 3111 false);
d7e3316c 3112 if (ret)
eb78d83e 3113 goto fail;
d7e3316c
AG		 3114
3115
3116 if (dm_plane_state->surface)
3117 dc_surface_release(dm_plane_state->surface);
3118
3119 dm_plane_state->surface = surface;
4562236b 3120
da5c47f6
AG		 3121 add_val_sets_surface(set,
3122 set_count,
d7e3316c 3123 new_acrtc_state->stream,
a6818a32 3124 surface);
4562236b 3125
3b42a1c0 3126 lock_and_validation_needed = true;
4562236b
HW		 3127 }
3128 }
3129 }
3130
d7e3316c
AG		 3131 /*
3132 * For full updates case when
3133 * removing/adding/updating streams on once CRTC while flipping
3134 * on another CRTC,
3135 * acquiring global lock will guarantee that any such full
3136 * update commit
3137 * will wait for completion of any outstanding flip using DRMs
3138 * synchronization events.
da5c47f6 3139 */
3b42a1c0
AG		 3140
3141 if (lock_and_validation_needed) {
3142
d7e3316c
AG		 3143 ret = do_aquire_global_lock(dev, state);
3144 if (ret)
eb78d83e 3145 goto fail;
0a323b84 3146 WARN_ON(dm_state->context);
3b42a1c0
AG		 3147 dm_state->context = dc_get_validate_context(dc, set, set_count);
3148 if (!dm_state->context) {
3149 ret = -EINVAL;
eb78d83e 3150 goto fail;
3b42a1c0 3151 }
d7e3316c
AG		 3152 }
3153
3154 /* Must be success */
3155 WARN_ON(ret);
3156 return ret;
3157
eb78d83e 3158fail:
d7e3316c
AG		 3159 if (ret == -EDEADLK)
3160 DRM_DEBUG_KMS("Atomic check stopped due to to deadlock.\n");
3161 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
3162 DRM_DEBUG_KMS("Atomic check stopped due to to signal.\n");
3163 else
3164 DRM_ERROR("Atomic check failed with err: %d .\n", ret);
4562236b
HW		 3165
3166 return ret;
3167}
3168
3169static bool is_dp_capable_without_timing_msa(
3170 struct dc *dc,
3171 struct amdgpu_connector *amdgpu_connector)
3172{
3173 uint8_t dpcd_data;
3174 bool capable = false;
209a885b 3175
4562236b 3176 if (amdgpu_connector->dc_link &&
209a885b
JL		 3177 dm_helpers_dp_read_dpcd(
3178 NULL,
3179 amdgpu_connector->dc_link,
3180 DP_DOWN_STREAM_PORT_COUNT,
3181 &dpcd_data,
3182 sizeof(dpcd_data))) {
d7194cf6 3183 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
209a885b 3184 }
4562236b
HW		 3185
3186 return capable;
3187}
3188void amdgpu_dm_add_sink_to_freesync_module(
3189 struct drm_connector *connector,
3190 struct edid *edid)
3191{
3192 int i;
3193 uint64_t val_capable;
3194 bool edid_check_required;
3195 struct detailed_timing *timing;
3196 struct detailed_non_pixel *data;
3197 struct detailed_data_monitor_range *range;
3198 struct amdgpu_connector *amdgpu_connector =
3199 to_amdgpu_connector(connector);
3200
3201 struct drm_device *dev = connector->dev;
3202 struct amdgpu_device *adev = dev->dev_private;
3203 edid_check_required = false;
3204 if (!amdgpu_connector->dc_sink) {
3205 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
3206 return;
3207 }
3208 if (!adev->dm.freesync_module)
3209 return;
3210 /*
3211 * if edid non zero restrict freesync only for dp and edp
3212 */
3213 if (edid) {
3214 if (amdgpu_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
3215 || amdgpu_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
3216 edid_check_required = is_dp_capable_without_timing_msa(
3217 adev->dm.dc,
3218 amdgpu_connector);
3219 }
3220 }
3221 val_capable = 0;
3222 if (edid_check_required == true && (edid->version > 1 ||
3223 (edid->version == 1 && edid->revision > 1))) {
3224 for (i = 0; i < 4; i++) {
3225
3226 timing = &edid->detailed_timings[i];
3227 data = &timing->data.other_data;
3228 range = &data->data.range;
3229 /*
3230 * Check if monitor has continuous frequency mode
3231 */
3232 if (data->type != EDID_DETAIL_MONITOR_RANGE)
3233 continue;
3234 /*
3235 * Check for flag range limits only. If flag == 1 then
3236 * no additional timing information provided.
3237 * Default GTF, GTF Secondary curve and CVT are not
3238 * supported
3239 */
3240 if (range->flags != 1)
3241 continue;
3242
3243 amdgpu_connector->min_vfreq = range->min_vfreq;
3244 amdgpu_connector->max_vfreq = range->max_vfreq;
3245 amdgpu_connector->pixel_clock_mhz =
3246 range->pixel_clock_mhz * 10;
3247 break;
3248 }
3249
3250 if (amdgpu_connector->max_vfreq -
3251 amdgpu_connector->min_vfreq > 10) {
3252 amdgpu_connector->caps.supported = true;
3253 amdgpu_connector->caps.min_refresh_in_micro_hz =
3254 amdgpu_connector->min_vfreq * 1000000;
3255 amdgpu_connector->caps.max_refresh_in_micro_hz =
3256 amdgpu_connector->max_vfreq * 1000000;
3257 val_capable = 1;
3258 }
3259 }
3260
3261 /*
3262 * TODO figure out how to notify user-mode or DRM of freesync caps
3263 * once we figure out how to deal with freesync in an upstreamable
3264 * fashion
3265 */
3266
3267}
3268
3269void amdgpu_dm_remove_sink_from_freesync_module(
3270 struct drm_connector *connector)
3271{
3272 /*
3273 * TODO fill in once we figure out how to deal with freesync in
3274 * an upstreamable fashion
3275 */
3276}
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