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drm/amd/display: initialize YUV plane capabilities
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / display / amdgpu_dm / amdgpu_dm_types.c
CommitLineData
4562236b
HW		 1/*
2 * Copyright 2012-13 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include <linux/types.h>
27#include <linux/version.h>
28
29#include <drm/drmP.h>
30#include <drm/drm_atomic_helper.h>
31#include <drm/drm_fb_helper.h>
32#include <drm/drm_atomic.h>
33#include <drm/drm_edid.h>
34
209a885b 35
4562236b
HW		 36#include "amdgpu.h"
37#include "amdgpu_pm.h"
209a885b 38#include "dm_helpers.h"
4562236b
HW		 39#include "dm_services_types.h"
40
41// We need to #undef FRAME_SIZE and DEPRECATED because they conflict
42// with ptrace-abi.h's #define's of them.
43#undef FRAME_SIZE
44#undef DEPRECATED
45
46#include "dc.h"
47
48#include "amdgpu_dm_types.h"
49#include "amdgpu_dm_mst_types.h"
50
51#include "modules/inc/mod_freesync.h"
52
53struct dm_connector_state {
54 struct drm_connector_state base;
55
56 enum amdgpu_rmx_type scaling;
57 uint8_t underscan_vborder;
58 uint8_t underscan_hborder;
59 bool underscan_enable;
60};
61
62#define to_dm_connector_state(x)\
63 container_of((x), struct dm_connector_state, base)
64
65
66void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
67{
68 drm_encoder_cleanup(encoder);
69 kfree(encoder);
70}
71
72static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
73 .destroy = amdgpu_dm_encoder_destroy,
74};
75
76static void dm_set_cursor(
77 struct amdgpu_crtc *amdgpu_crtc,
78 uint64_t gpu_addr,
79 uint32_t width,
80 uint32_t height)
81{
82 struct dc_cursor_attributes attributes;
cf388c0d
AN		 83 struct dc_cursor_position position;
84 struct drm_crtc *crtc = &amdgpu_crtc->base;
85 int x, y;
86 int xorigin = 0, yorigin = 0;
87
4562236b
HW		 88 amdgpu_crtc->cursor_width = width;
89 amdgpu_crtc->cursor_height = height;
90
91 attributes.address.high_part = upper_32_bits(gpu_addr);
92 attributes.address.low_part = lower_32_bits(gpu_addr);
93 attributes.width = width;
94 attributes.height = height;
4562236b
HW		 95 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
96 attributes.rotation_angle = 0;
97 attributes.attribute_flags.value = 0;
98
0702a01f
AG		 99 attributes.pitch = attributes.width;
100
cf388c0d
AN		 101 x = amdgpu_crtc->cursor_x;
102 y = amdgpu_crtc->cursor_y;
103
104 /* avivo cursor are offset into the total surface */
105 x += crtc->primary->state->src_x >> 16;
106 y += crtc->primary->state->src_y >> 16;
107
108 if (x < 0) {
109 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
110 x = 0;
111 }
112 if (y < 0) {
113 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
114 y = 0;
115 }
116
117 position.enable = true;
118 position.x = x;
119 position.y = y;
120
cf388c0d
AN		 121 position.x_hotspot = xorigin;
122 position.y_hotspot = yorigin;
123
ab2541b6
AC		 124 if (!dc_stream_set_cursor_attributes(
125 amdgpu_crtc->stream,
4562236b
HW		 126 &attributes)) {
127 DRM_ERROR("DC failed to set cursor attributes\n");
128 }
cf388c0d 129
ab2541b6
AC		 130 if (!dc_stream_set_cursor_position(
131 amdgpu_crtc->stream,
cf388c0d
AN		 132 &position)) {
133 DRM_ERROR("DC failed to set cursor position\n");
134 }
4562236b
HW		 135}
136
137static int dm_crtc_unpin_cursor_bo_old(
138 struct amdgpu_crtc *amdgpu_crtc)
139{
140 struct amdgpu_bo *robj;
141 int ret = 0;
142
143 if (NULL != amdgpu_crtc && NULL != amdgpu_crtc->cursor_bo) {
144 robj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
145
146 ret = amdgpu_bo_reserve(robj, false);
147
148 if (likely(ret == 0)) {
149 ret = amdgpu_bo_unpin(robj);
150
151 if (unlikely(ret != 0)) {
152 DRM_ERROR(
153 "%s: unpin failed (ret=%d), bo %p\n",
154 __func__,
155 ret,
156 amdgpu_crtc->cursor_bo);
157 }
158
159 amdgpu_bo_unreserve(robj);
160 } else {
161 DRM_ERROR(
162 "%s: reserve failed (ret=%d), bo %p\n",
163 __func__,
164 ret,
165 amdgpu_crtc->cursor_bo);
166 }
167
168 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
169 amdgpu_crtc->cursor_bo = NULL;
170 }
171
172 return ret;
173}
174
175static int dm_crtc_pin_cursor_bo_new(
176 struct drm_crtc *crtc,
177 struct drm_file *file_priv,
178 uint32_t handle,
179 struct amdgpu_bo **ret_obj)
180{
181 struct amdgpu_crtc *amdgpu_crtc;
182 struct amdgpu_bo *robj;
183 struct drm_gem_object *obj;
184 int ret = -EINVAL;
185
186 if (NULL != crtc) {
187 struct drm_device *dev = crtc->dev;
188 struct amdgpu_device *adev = dev->dev_private;
189 uint64_t gpu_addr;
190
191 amdgpu_crtc = to_amdgpu_crtc(crtc);
192
193 obj = drm_gem_object_lookup(file_priv, handle);
194
195 if (!obj) {
196 DRM_ERROR(
197 "Cannot find cursor object %x for crtc %d\n",
198 handle,
199 amdgpu_crtc->crtc_id);
200 goto release;
201 }
202 robj = gem_to_amdgpu_bo(obj);
203
204 ret = amdgpu_bo_reserve(robj, false);
205
206 if (unlikely(ret != 0)) {
207 drm_gem_object_unreference_unlocked(obj);
208 DRM_ERROR("dm_crtc_pin_cursor_bo_new ret %x, handle %x\n",
209 ret, handle);
210 goto release;
211 }
212
213 ret = amdgpu_bo_pin_restricted(robj, AMDGPU_GEM_DOMAIN_VRAM, 0,
214 adev->mc.visible_vram_size,
215 &gpu_addr);
216
217 if (ret == 0) {
218 amdgpu_crtc->cursor_addr = gpu_addr;
219 *ret_obj = robj;
220 }
221 amdgpu_bo_unreserve(robj);
222 if (ret)
223 drm_gem_object_unreference_unlocked(obj);
224
225 }
226release:
227
228 return ret;
229}
230
231static int dm_crtc_cursor_set(
232 struct drm_crtc *crtc,
233 struct drm_file *file_priv,
234 uint32_t handle,
235 uint32_t width,
236 uint32_t height)
237{
238 struct amdgpu_bo *new_cursor_bo;
239 struct dc_cursor_position position;
240
241 int ret;
242
243 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
244
245 ret = EINVAL;
246 new_cursor_bo = NULL;
247
248 DRM_DEBUG_KMS(
249 "%s: crtc_id=%d with handle %d and size %d to %d, bo_object %p\n",
250 __func__,
251 amdgpu_crtc->crtc_id,
252 handle,
253 width,
254 height,
255 amdgpu_crtc->cursor_bo);
256
257 if (!handle) {
258 /* turn off cursor */
259 position.enable = false;
260 position.x = 0;
261 position.y = 0;
4562236b 262
ab2541b6 263 if (amdgpu_crtc->stream) {
4562236b 264 /*set cursor visible false*/
ab2541b6
AC		 265 dc_stream_set_cursor_position(
266 amdgpu_crtc->stream,
4562236b
HW		 267 &position);
268 }
269 /*unpin old cursor buffer and update cache*/
270 ret = dm_crtc_unpin_cursor_bo_old(amdgpu_crtc);
271 goto release;
272
273 }
274
275 if ((width > amdgpu_crtc->max_cursor_width) ||
276 (height > amdgpu_crtc->max_cursor_height)) {
277 DRM_ERROR(
278 "%s: bad cursor width or height %d x %d\n",
279 __func__,
280 width,
281 height);
282 goto release;
283 }
284 /*try to pin new cursor bo*/
285 ret = dm_crtc_pin_cursor_bo_new(crtc, file_priv, handle, &new_cursor_bo);
286 /*if map not successful then return an error*/
287 if (ret)
288 goto release;
289
290 /*program new cursor bo to hardware*/
291 dm_set_cursor(amdgpu_crtc, amdgpu_crtc->cursor_addr, width, height);
292
293 /*un map old, not used anymore cursor bo ,
294 * return memory and mapping back */
295 dm_crtc_unpin_cursor_bo_old(amdgpu_crtc);
296
297 /*assign new cursor bo to our internal cache*/
298 amdgpu_crtc->cursor_bo = &new_cursor_bo->gem_base;
299
300release:
301 return ret;
302
303}
304
305static int dm_crtc_cursor_move(struct drm_crtc *crtc,
306 int x, int y)
307{
308 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
309 int xorigin = 0, yorigin = 0;
310 struct dc_cursor_position position;
311
cf388c0d
AN		 312 amdgpu_crtc->cursor_x = x;
313 amdgpu_crtc->cursor_y = y;
314
4562236b
HW		 315 /* avivo cursor are offset into the total surface */
316 x += crtc->primary->state->src_x >> 16;
317 y += crtc->primary->state->src_y >> 16;
318
319 /*
320 * TODO: for cursor debugging unguard the following
321 */
322#if 0
323 DRM_DEBUG_KMS(
324 "%s: x %d y %d c->x %d c->y %d\n",
325 __func__,
326 x,
327 y,
328 crtc->x,
329 crtc->y);
330#endif
331
332 if (x < 0) {
333 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
334 x = 0;
335 }
336 if (y < 0) {
337 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
338 y = 0;
339 }
340
341 position.enable = true;
342 position.x = x;
343 position.y = y;
344
4562236b
HW		 345 position.x_hotspot = xorigin;
346 position.y_hotspot = yorigin;
347
ab2541b6
AC		 348 if (amdgpu_crtc->stream) {
349 if (!dc_stream_set_cursor_position(
350 amdgpu_crtc->stream,
4562236b
HW		 351 &position)) {
352 DRM_ERROR("DC failed to set cursor position\n");
353 return -EINVAL;
354 }
355 }
356
357 return 0;
358}
359
360static void dm_crtc_cursor_reset(struct drm_crtc *crtc)
361{
362 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
363
364 DRM_DEBUG_KMS(
365 "%s: with cursor_bo %p\n",
366 __func__,
367 amdgpu_crtc->cursor_bo);
368
ab2541b6 369 if (amdgpu_crtc->cursor_bo && amdgpu_crtc->stream) {
4562236b
HW		 370 dm_set_cursor(
371 amdgpu_crtc,
372 amdgpu_crtc->cursor_addr,
373 amdgpu_crtc->cursor_width,
374 amdgpu_crtc->cursor_height);
375 }
376}
377static bool fill_rects_from_plane_state(
378 const struct drm_plane_state *state,
379 struct dc_surface *surface)
380{
381 surface->src_rect.x = state->src_x >> 16;
382 surface->src_rect.y = state->src_y >> 16;
383 /*we ignore for now mantissa and do not to deal with floating pixels :(*/
384 surface->src_rect.width = state->src_w >> 16;
385
386 if (surface->src_rect.width == 0)
387 return false;
388
389 surface->src_rect.height = state->src_h >> 16;
390 if (surface->src_rect.height == 0)
391 return false;
392
393 surface->dst_rect.x = state->crtc_x;
394 surface->dst_rect.y = state->crtc_y;
395
396 if (state->crtc_w == 0)
397 return false;
398
399 surface->dst_rect.width = state->crtc_w;
400
401 if (state->crtc_h == 0)
402 return false;
403
404 surface->dst_rect.height = state->crtc_h;
405
406 surface->clip_rect = surface->dst_rect;
407
408 switch (state->rotation & DRM_MODE_ROTATE_MASK) {
409 case DRM_MODE_ROTATE_0:
410 surface->rotation = ROTATION_ANGLE_0;
411 break;
412 case DRM_MODE_ROTATE_90:
413 surface->rotation = ROTATION_ANGLE_90;
414 break;
415 case DRM_MODE_ROTATE_180:
416 surface->rotation = ROTATION_ANGLE_180;
417 break;
418 case DRM_MODE_ROTATE_270:
419 surface->rotation = ROTATION_ANGLE_270;
420 break;
421 default:
422 surface->rotation = ROTATION_ANGLE_0;
423 break;
424 }
425
426 return true;
427}
428static bool get_fb_info(
429 const struct amdgpu_framebuffer *amdgpu_fb,
430 uint64_t *tiling_flags,
431 uint64_t *fb_location)
432{
433 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
434 int r = amdgpu_bo_reserve(rbo, false);
435 if (unlikely(r != 0)){
436 DRM_ERROR("Unable to reserve buffer\n");
437 return false;
438 }
439
440 if (fb_location)
441 *fb_location = amdgpu_bo_gpu_offset(rbo);
442
443 if (tiling_flags)
444 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
445
446 amdgpu_bo_unreserve(rbo);
447
448 return true;
449}
450static void fill_plane_attributes_from_fb(
6a1f8cab 451 struct amdgpu_device *adev,
4562236b
HW		 452 struct dc_surface *surface,
453 const struct amdgpu_framebuffer *amdgpu_fb, bool addReq)
454{
455 uint64_t tiling_flags;
456 uint64_t fb_location = 0;
457 const struct drm_framebuffer *fb = &amdgpu_fb->base;
458 struct drm_format_name_buf format_name;
459
460 get_fb_info(
461 amdgpu_fb,
462 &tiling_flags,
463 addReq == true ? &fb_location:NULL);
464
4562236b
HW		 465
466 switch (fb->format->format) {
467 case DRM_FORMAT_C8:
468 surface->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
469 break;
470 case DRM_FORMAT_RGB565:
471 surface->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
472 break;
473 case DRM_FORMAT_XRGB8888:
474 case DRM_FORMAT_ARGB8888:
475 surface->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
476 break;
477 case DRM_FORMAT_XRGB2101010:
478 case DRM_FORMAT_ARGB2101010:
479 surface->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
480 break;
481 case DRM_FORMAT_XBGR2101010:
482 case DRM_FORMAT_ABGR2101010:
483 surface->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
484 break;
e6fbd5df
S		 485 case DRM_FORMAT_YUV420:
486 surface->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
487 break;
488 case DRM_FORMAT_YVU420:
489 surface->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
490 break;
4562236b
HW		 491 default:
492 DRM_ERROR("Unsupported screen format %s\n",
493 drm_get_format_name(fb->format->format, &format_name));
494 return;
495 }
496
e6fbd5df
S		 497 if (surface->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
498 surface->address.type = PLN_ADDR_TYPE_GRAPHICS;
499 surface->address.grph.addr.low_part = lower_32_bits(fb_location);
500 surface->address.grph.addr.high_part = upper_32_bits(fb_location);
501 surface->plane_size.grph.surface_size.x = 0;
502 surface->plane_size.grph.surface_size.y = 0;
503 surface->plane_size.grph.surface_size.width = fb->width;
504 surface->plane_size.grph.surface_size.height = fb->height;
505 surface->plane_size.grph.surface_pitch =
506 fb->pitches[0] / fb->format->cpp[0];
507 /* TODO: unhardcode */
508 surface->color_space = COLOR_SPACE_SRGB;
509
510 } else {
511 surface->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
512 surface->address.video_progressive.luma_addr.low_part
513 = lower_32_bits(fb_location);
514 surface->address.video_progressive.chroma_addr.high_part
515 = upper_32_bits(fb_location);
516 surface->plane_size.video.luma_size.x = 0;
517 surface->plane_size.video.luma_size.y = 0;
518 surface->plane_size.video.luma_size.width = fb->width;
519 surface->plane_size.video.luma_size.height = fb->height;
520 /* TODO: unhardcode */
521 surface->plane_size.video.luma_pitch = fb->pitches[0] / 4;
522
523 surface->plane_size.video.chroma_size.x = 0;
524 surface->plane_size.video.chroma_size.y = 0;
525 surface->plane_size.video.chroma_size.width = fb->width;
526 surface->plane_size.video.chroma_size.height = fb->height;
527 surface->plane_size.video.chroma_pitch =
528 fb->pitches[0] / 4;
529
530 /* TODO: unhardcode */
531 surface->color_space = COLOR_SPACE_YCBCR709;
532 }
533
4562236b
HW		 534 memset(&surface->tiling_info, 0, sizeof(surface->tiling_info));
535
2c8ad2d5 536 /* Fill GFX params */
4562236b
HW		 537 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1)
538 {
539 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
540
541 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
542 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
543 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
544 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
545 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
546
547 /* XXX fix me for VI */
548 surface->tiling_info.gfx8.num_banks = num_banks;
549 surface->tiling_info.gfx8.array_mode =
550 DC_ARRAY_2D_TILED_THIN1;
551 surface->tiling_info.gfx8.tile_split = tile_split;
552 surface->tiling_info.gfx8.bank_width = bankw;
553 surface->tiling_info.gfx8.bank_height = bankh;
554 surface->tiling_info.gfx8.tile_aspect = mtaspect;
555 surface->tiling_info.gfx8.tile_mode =
556 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
557 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
558 == DC_ARRAY_1D_TILED_THIN1) {
559 surface->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
560 }
561
562 surface->tiling_info.gfx8.pipe_config =
563 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
564
2c8ad2d5
AD		 565 if (adev->asic_type == CHIP_VEGA10) {
566 /* Fill GFX9 params */
567 surface->tiling_info.gfx9.num_pipes =
568 adev->gfx.config.gb_addr_config_fields.num_pipes;
569 surface->tiling_info.gfx9.num_banks =
570 adev->gfx.config.gb_addr_config_fields.num_banks;
571 surface->tiling_info.gfx9.pipe_interleave =
572 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
573 surface->tiling_info.gfx9.num_shader_engines =
574 adev->gfx.config.gb_addr_config_fields.num_se;
575 surface->tiling_info.gfx9.max_compressed_frags =
576 adev->gfx.config.gb_addr_config_fields.max_compress_frags;
d092bf65
AG		 577 surface->tiling_info.gfx9.num_rb_per_se =
578 adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
2c8ad2d5
AD		 579 surface->tiling_info.gfx9.swizzle =
580 AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
581 surface->tiling_info.gfx9.shaderEnable = 1;
582 }
2c8ad2d5 583
4562236b
HW		 584 surface->visible = true;
585 surface->scaling_quality.h_taps_c = 0;
586 surface->scaling_quality.v_taps_c = 0;
587
4562236b
HW		 588 /* is this needed? is surface zeroed at allocation? */
589 surface->scaling_quality.h_taps = 0;
590 surface->scaling_quality.v_taps = 0;
591 surface->stereo_format = PLANE_STEREO_FORMAT_NONE;
592
593}
594
595#define NUM_OF_RAW_GAMMA_RAMP_RGB_256 256
596
597static void fill_gamma_from_crtc(
598 const struct drm_crtc *crtc,
599 struct dc_surface *dc_surface)
600{
601 int i;
602 struct dc_gamma *gamma;
603 struct drm_crtc_state *state = crtc->state;
604 struct drm_color_lut *lut = (struct drm_color_lut *) state->gamma_lut->data;
605
606 gamma = dc_create_gamma();
607
608 if (gamma == NULL)
609 return;
610
611 for (i = 0; i < NUM_OF_RAW_GAMMA_RAMP_RGB_256; i++) {
d7194cf6
AC		 612 gamma->red[i] = lut[i].red;
613 gamma->green[i] = lut[i].green;
614 gamma->blue[i] = lut[i].blue;
4562236b
HW		 615 }
616
4562236b
HW		 617 dc_surface->gamma_correction = gamma;
618}
619
620static void fill_plane_attributes(
6a1f8cab 621 struct amdgpu_device *adev,
4562236b
HW		 622 struct dc_surface *surface,
623 struct drm_plane_state *state, bool addrReq)
624{
625 const struct amdgpu_framebuffer *amdgpu_fb =
626 to_amdgpu_framebuffer(state->fb);
627 const struct drm_crtc *crtc = state->crtc;
18f39f2d 628 struct dc_transfer_func *input_tf;
4562236b
HW		 629
630 fill_rects_from_plane_state(state, surface);
631 fill_plane_attributes_from_fb(
6a1f8cab 632 crtc->dev->dev_private,
4562236b
HW		 633 surface,
634 amdgpu_fb,
635 addrReq);
636
18f39f2d
RL		 637 input_tf = dc_create_transfer_func();
638
639 if (input_tf == NULL)
640 return;
641
642 input_tf->type = TF_TYPE_PREDEFINED;
643 input_tf->tf = TRANSFER_FUNCTION_SRGB;
644
645 surface->in_transfer_func = input_tf;
646
4562236b
HW		 647 /* In case of gamma set, update gamma value */
648 if (state->crtc->state->gamma_lut) {
649 fill_gamma_from_crtc(crtc, surface);
650 }
651}
652
653/*****************************************************************************/
654
655struct amdgpu_connector *aconnector_from_drm_crtc_id(
656 const struct drm_crtc *crtc)
657{
658 struct drm_device *dev = crtc->dev;
659 struct drm_connector *connector;
660 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
661 struct amdgpu_connector *aconnector;
662
663 list_for_each_entry(connector,
664 &dev->mode_config.connector_list, head) {
665
666 aconnector = to_amdgpu_connector(connector);
667
668 if (aconnector->base.state->crtc != &acrtc->base)
669 continue;
670
671 /* Found the connector */
672 return aconnector;
673 }
674
675 /* If we get here, not found. */
676 return NULL;
677}
678
679static void update_stream_scaling_settings(
680 const struct drm_display_mode *mode,
681 const struct dm_connector_state *dm_state,
682 const struct dc_stream *stream)
683{
684 struct amdgpu_device *adev = dm_state->base.crtc->dev->dev_private;
685 enum amdgpu_rmx_type rmx_type;
686
ab2541b6 687 struct rect src = { 0 }; /* viewport in composition space*/
4562236b
HW		 688 struct rect dst = { 0 }; /* stream addressable area */
689
f7f3cfee
HW		 690 /* no mode. nothing to be done */
691 if (!mode)
692 return;
693
4562236b
HW		 694 /* Full screen scaling by default */
695 src.width = mode->hdisplay;
696 src.height = mode->vdisplay;
697 dst.width = stream->timing.h_addressable;
698 dst.height = stream->timing.v_addressable;
699
700 rmx_type = dm_state->scaling;
701 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
702 if (src.width * dst.height <
703 src.height * dst.width) {
704 /* height needs less upscaling/more downscaling */
705 dst.width = src.width *
706 dst.height / src.height;
707 } else {
708 /* width needs less upscaling/more downscaling */
709 dst.height = src.height *
710 dst.width / src.width;
711 }
712 } else if (rmx_type == RMX_CENTER) {
713 dst = src;
714 }
715
716 dst.x = (stream->timing.h_addressable - dst.width) / 2;
717 dst.y = (stream->timing.v_addressable - dst.height) / 2;
718
719 if (dm_state->underscan_enable) {
720 dst.x += dm_state->underscan_hborder / 2;
721 dst.y += dm_state->underscan_vborder / 2;
722 dst.width -= dm_state->underscan_hborder;
723 dst.height -= dm_state->underscan_vborder;
724 }
725
726 adev->dm.dc->stream_funcs.stream_update_scaling(adev->dm.dc, stream, &src, &dst);
727
728 DRM_DEBUG_KMS("Destination Rectangle x:%d y:%d width:%d height:%d\n",
729 dst.x, dst.y, dst.width, dst.height);
730
731}
732
733static void dm_dc_surface_commit(
734 struct dc *dc,
735 struct drm_crtc *crtc)
736{
737 struct dc_surface *dc_surface;
738 const struct dc_surface *dc_surfaces[1];
54f5499a 739 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
ab2541b6 740 const struct dc_stream *dc_stream = acrtc->stream;
54f5499a
AG		 741 unsigned long flags;
742
743 spin_lock_irqsave(&crtc->dev->event_lock, flags);
744 if (acrtc->pflip_status != AMDGPU_FLIP_NONE) {
745 DRM_ERROR("dm_dc_surface_commit: acrtc %d, already busy\n", acrtc->crtc_id);
746 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
747 /* In comit tail framework this cannot happen */
748 BUG_ON(0);
749 }
750 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
4562236b 751
ab2541b6 752 if (!dc_stream) {
4562236b 753 dm_error(
ab2541b6 754 "%s: Failed to obtain stream on crtc (%d)!\n",
4562236b
HW		 755 __func__,
756 acrtc->crtc_id);
757 goto fail;
758 }
759
760 dc_surface = dc_create_surface(dc);
761
762 if (!dc_surface) {
763 dm_error(
764 "%s: Failed to create a surface!\n",
765 __func__);
766 goto fail;
767 }
768
769 /* Surface programming */
6a1f8cab
AG		 770 fill_plane_attributes(
771 crtc->dev->dev_private,
772 dc_surface,
773 crtc->primary->state,
774 true);
4562236b
HW		 775
776 dc_surfaces[0] = dc_surface;
777
ab2541b6 778 if (false == dc_commit_surfaces_to_stream(
4562236b
HW		 779 dc,
780 dc_surfaces,
781 1,
ab2541b6 782 dc_stream)) {
4562236b
HW		 783 dm_error(
784 "%s: Failed to attach surface!\n",
785 __func__);
786 }
787
788 dc_surface_release(dc_surface);
789fail:
790 return;
791}
792
793static enum dc_color_depth convert_color_depth_from_display_info(
794 const struct drm_connector *connector)
795{
796 uint32_t bpc = connector->display_info.bpc;
797
798 /* Limited color depth to 8bit
799 * TODO: Still need to handle deep color*/
800 if (bpc > 8)
801 bpc = 8;
802
803 switch (bpc) {
804 case 0:
805 /* Temporary Work around, DRM don't parse color depth for
806 * EDID revision before 1.4
807 * TODO: Fix edid parsing
808 */
809 return COLOR_DEPTH_888;
810 case 6:
811 return COLOR_DEPTH_666;
812 case 8:
813 return COLOR_DEPTH_888;
814 case 10:
815 return COLOR_DEPTH_101010;
816 case 12:
817 return COLOR_DEPTH_121212;
818 case 14:
819 return COLOR_DEPTH_141414;
820 case 16:
821 return COLOR_DEPTH_161616;
822 default:
823 return COLOR_DEPTH_UNDEFINED;
824 }
825}
826
827static enum dc_aspect_ratio get_aspect_ratio(
828 const struct drm_display_mode *mode_in)
829{
830 int32_t width = mode_in->crtc_hdisplay * 9;
831 int32_t height = mode_in->crtc_vdisplay * 16;
832 if ((width - height) < 10 && (width - height) > -10)
833 return ASPECT_RATIO_16_9;
834 else
835 return ASPECT_RATIO_4_3;
836}
837
838static enum dc_color_space get_output_color_space(
839 const struct dc_crtc_timing *dc_crtc_timing)
840{
841 enum dc_color_space color_space = COLOR_SPACE_SRGB;
842
843 switch (dc_crtc_timing->pixel_encoding) {
844 case PIXEL_ENCODING_YCBCR422:
845 case PIXEL_ENCODING_YCBCR444:
846 case PIXEL_ENCODING_YCBCR420:
847 {
848 /*
849 * 27030khz is the separation point between HDTV and SDTV
850 * according to HDMI spec, we use YCbCr709 and YCbCr601
851 * respectively
852 */
853 if (dc_crtc_timing->pix_clk_khz > 27030) {
854 if (dc_crtc_timing->flags.Y_ONLY)
855 color_space =
856 COLOR_SPACE_YCBCR709_LIMITED;
857 else
858 color_space = COLOR_SPACE_YCBCR709;
859 } else {
860 if (dc_crtc_timing->flags.Y_ONLY)
861 color_space =
862 COLOR_SPACE_YCBCR601_LIMITED;
863 else
864 color_space = COLOR_SPACE_YCBCR601;
865 }
866
867 }
868 break;
869 case PIXEL_ENCODING_RGB:
870 color_space = COLOR_SPACE_SRGB;
871 break;
872
873 default:
874 WARN_ON(1);
875 break;
876 }
877
878 return color_space;
879}
880
881/*****************************************************************************/
882
883static void fill_stream_properties_from_drm_display_mode(
884 struct dc_stream *stream,
885 const struct drm_display_mode *mode_in,
886 const struct drm_connector *connector)
887{
888 struct dc_crtc_timing *timing_out = &stream->timing;
889 memset(timing_out, 0, sizeof(struct dc_crtc_timing));
890
891 timing_out->h_border_left = 0;
892 timing_out->h_border_right = 0;
893 timing_out->v_border_top = 0;
894 timing_out->v_border_bottom = 0;
895 /* TODO: un-hardcode */
896
897 if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
898 && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
899 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
900 else
901 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
902
903 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
904 timing_out->display_color_depth = convert_color_depth_from_display_info(
905 connector);
906 timing_out->scan_type = SCANNING_TYPE_NODATA;
907 timing_out->hdmi_vic = 0;
908 timing_out->vic = drm_match_cea_mode(mode_in);
909
910 timing_out->h_addressable = mode_in->crtc_hdisplay;
911 timing_out->h_total = mode_in->crtc_htotal;
912 timing_out->h_sync_width =
913 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
914 timing_out->h_front_porch =
915 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
916 timing_out->v_total = mode_in->crtc_vtotal;
917 timing_out->v_addressable = mode_in->crtc_vdisplay;
918 timing_out->v_front_porch =
919 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
920 timing_out->v_sync_width =
921 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
922 timing_out->pix_clk_khz = mode_in->crtc_clock;
923 timing_out->aspect_ratio = get_aspect_ratio(mode_in);
924 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
925 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
926 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
927 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
928
929 stream->output_color_space = get_output_color_space(timing_out);
930
d7194cf6
AC		 931 {
932 struct dc_transfer_func *tf = dc_create_transfer_func();
933 tf->type = TF_TYPE_PREDEFINED;
934 tf->tf = TRANSFER_FUNCTION_SRGB;
935 stream->out_transfer_func = tf;
936 }
4562236b
HW		 937}
938
939static void fill_audio_info(
940 struct audio_info *audio_info,
941 const struct drm_connector *drm_connector,
942 const struct dc_sink *dc_sink)
943{
944 int i = 0;
945 int cea_revision = 0;
946 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
947
948 audio_info->manufacture_id = edid_caps->manufacturer_id;
949 audio_info->product_id = edid_caps->product_id;
950
951 cea_revision = drm_connector->display_info.cea_rev;
952
953 while (i < AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS &&
954 edid_caps->display_name[i]) {
955 audio_info->display_name[i] = edid_caps->display_name[i];
956 i++;
957 }
958
959 if(cea_revision >= 3) {
960 audio_info->mode_count = edid_caps->audio_mode_count;
961
962 for (i = 0; i < audio_info->mode_count; ++i) {
963 audio_info->modes[i].format_code =
964 (enum audio_format_code)
965 (edid_caps->audio_modes[i].format_code);
966 audio_info->modes[i].channel_count =
967 edid_caps->audio_modes[i].channel_count;
968 audio_info->modes[i].sample_rates.all =
969 edid_caps->audio_modes[i].sample_rate;
970 audio_info->modes[i].sample_size =
971 edid_caps->audio_modes[i].sample_size;
972 }
973 }
974
975 audio_info->flags.all = edid_caps->speaker_flags;
976
977 /* TODO: We only check for the progressive mode, check for interlace mode too */
978 if(drm_connector->latency_present[0]) {
979 audio_info->video_latency = drm_connector->video_latency[0];
980 audio_info->audio_latency = drm_connector->audio_latency[0];
981 }
982
983 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
984
985}
986
987static void copy_crtc_timing_for_drm_display_mode(
988 const struct drm_display_mode *src_mode,
989 struct drm_display_mode *dst_mode)
990{
991 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
992 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
993 dst_mode->crtc_clock = src_mode->crtc_clock;
994 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
995 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
996 dst_mode->crtc_hsync_start= src_mode->crtc_hsync_start;
997 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
998 dst_mode->crtc_htotal = src_mode->crtc_htotal;
999 dst_mode->crtc_hskew = src_mode->crtc_hskew;
5866e7cf
JL		 1000 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
1001 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
1002 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
1003 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
1004 dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
4562236b
HW		 1005}
1006
1007static void decide_crtc_timing_for_drm_display_mode(
1008 struct drm_display_mode *drm_mode,
1009 const struct drm_display_mode *native_mode,
1010 bool scale_enabled)
1011{
1012 if (scale_enabled) {
1013 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
1014 } else if (native_mode->clock == drm_mode->clock &&
1015 native_mode->htotal == drm_mode->htotal &&
1016 native_mode->vtotal == drm_mode->vtotal) {
1017 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
1018 } else {
1019 /* no scaling nor amdgpu inserted, no need to patch */
1020 }
1021}
1022
ab2541b6 1023static struct dc_stream *create_stream_for_sink(
0d70570f 1024 struct amdgpu_connector *aconnector,
4562236b
HW		 1025 const struct drm_display_mode *drm_mode,
1026 const struct dm_connector_state *dm_state)
1027{
1028 struct drm_display_mode *preferred_mode = NULL;
1029 const struct drm_connector *drm_connector;
ab2541b6 1030 struct dc_stream *stream = NULL;
4562236b
HW		 1031 struct drm_display_mode mode = *drm_mode;
1032 bool native_mode_found = false;
1033
1034 if (NULL == aconnector) {
1035 DRM_ERROR("aconnector is NULL!\n");
1036 goto drm_connector_null;
1037 }
1038
1039 if (NULL == dm_state) {
1040 DRM_ERROR("dm_state is NULL!\n");
1041 goto dm_state_null;
1042 }
1043
1044 drm_connector = &aconnector->base;
1045 stream = dc_create_stream_for_sink(aconnector->dc_sink);
1046
1047 if (NULL == stream) {
1048 DRM_ERROR("Failed to create stream for sink!\n");
1049 goto stream_create_fail;
1050 }
1051
1052 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
1053 /* Search for preferred mode */
1054 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
1055 native_mode_found = true;
1056 break;
1057 }
1058 }
1059 if (!native_mode_found)
1060 preferred_mode = list_first_entry_or_null(
1061 &aconnector->base.modes,
1062 struct drm_display_mode,
1063 head);
1064
1065 if (NULL == preferred_mode) {
1066 /* This may not be an error, the use case is when we we have no
1067 * usermode calls to reset and set mode upon hotplug. In this
1068 * case, we call set mode ourselves to restore the previous mode
1069 * and the modelist may not be filled in in time.
1070 */
1071 DRM_INFO("No preferred mode found\n");
1072 } else {
1073 decide_crtc_timing_for_drm_display_mode(
1074 &mode, preferred_mode,
1075 dm_state->scaling != RMX_OFF);
1076 }
1077
1078 fill_stream_properties_from_drm_display_mode(stream,
1079 &mode, &aconnector->base);
1080 update_stream_scaling_settings(&mode, dm_state, stream);
1081
1082 fill_audio_info(
1083 &stream->audio_info,
1084 drm_connector,
1085 aconnector->dc_sink);
1086
ab2541b6 1087stream_create_fail:
4562236b
HW		 1088dm_state_null:
1089drm_connector_null:
ab2541b6 1090 return stream;
4562236b
HW		 1091}
1092
1093void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
1094{
1095 drm_crtc_cleanup(crtc);
1096 kfree(crtc);
1097}
1098
1099/* Implemented only the options currently availible for the driver */
1100static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
1101 .reset = drm_atomic_helper_crtc_reset,
1102 .cursor_set = dm_crtc_cursor_set,
1103 .cursor_move = dm_crtc_cursor_move,
1104 .destroy = amdgpu_dm_crtc_destroy,
1105 .gamma_set = drm_atomic_helper_legacy_gamma_set,
1106 .set_config = drm_atomic_helper_set_config,
1107 .page_flip = drm_atomic_helper_page_flip,
1108 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
1109 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
1110};
1111
1112static enum drm_connector_status
1113amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
1114{
1115 bool connected;
1116 struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
1117
1118 /* Notes:
1119 * 1. This interface is NOT called in context of HPD irq.
1120 * 2. This interface *is called* in context of user-mode ioctl. Which
1121 * makes it a bad place for *any* MST-related activit. */
1122
1123 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
1124 connected = (aconnector->dc_sink != NULL);
1125 else
1126 connected = (aconnector->base.force == DRM_FORCE_ON);
1127
1128 return (connected ? connector_status_connected :
1129 connector_status_disconnected);
1130}
1131
1132int amdgpu_dm_connector_atomic_set_property(
1133 struct drm_connector *connector,
1134 struct drm_connector_state *connector_state,
1135 struct drm_property *property,
1136 uint64_t val)
1137{
1138 struct drm_device *dev = connector->dev;
1139 struct amdgpu_device *adev = dev->dev_private;
1140 struct dm_connector_state *dm_old_state =
1141 to_dm_connector_state(connector->state);
1142 struct dm_connector_state *dm_new_state =
1143 to_dm_connector_state(connector_state);
1144
1145 struct drm_crtc_state *new_crtc_state;
1146 struct drm_crtc *crtc;
1147 int i;
1148 int ret = -EINVAL;
1149
1150 if (property == dev->mode_config.scaling_mode_property) {
1151 enum amdgpu_rmx_type rmx_type;
1152
1153 switch (val) {
1154 case DRM_MODE_SCALE_CENTER:
1155 rmx_type = RMX_CENTER;
1156 break;
1157 case DRM_MODE_SCALE_ASPECT:
1158 rmx_type = RMX_ASPECT;
1159 break;
1160 case DRM_MODE_SCALE_FULLSCREEN:
1161 rmx_type = RMX_FULL;
1162 break;
1163 case DRM_MODE_SCALE_NONE:
1164 default:
1165 rmx_type = RMX_OFF;
1166 break;
1167 }
1168
1169 if (dm_old_state->scaling == rmx_type)
1170 return 0;
1171
1172 dm_new_state->scaling = rmx_type;
1173 ret = 0;
1174 } else if (property == adev->mode_info.underscan_hborder_property) {
1175 dm_new_state->underscan_hborder = val;
1176 ret = 0;
1177 } else if (property == adev->mode_info.underscan_vborder_property) {
1178 dm_new_state->underscan_vborder = val;
1179 ret = 0;
1180 } else if (property == adev->mode_info.underscan_property) {
1181 dm_new_state->underscan_enable = val;
1182 ret = 0;
1183 }
1184
1185 for_each_crtc_in_state(
1186 connector_state->state,
1187 crtc,
1188 new_crtc_state,
1189 i) {
1190
1191 if (crtc == connector_state->crtc) {
1192 struct drm_plane_state *plane_state;
1193
1194 /*
1195 * Bit of magic done here. We need to ensure
1196 * that planes get update after mode is set.
1197 * So, we need to add primary plane to state,
1198 * and this way atomic_update would be called
1199 * for it
1200 */
1201 plane_state =
1202 drm_atomic_get_plane_state(
1203 connector_state->state,
1204 crtc->primary);
1205
1206 if (!plane_state)
1207 return -EINVAL;
1208 }
1209 }
1210
1211 return ret;
1212}
1213
32a1892a
PV		 1214int amdgpu_dm_connector_atomic_get_property(
1215 struct drm_connector *connector,
1216 const struct drm_connector_state *state,
1217 struct drm_property *property,
1218 uint64_t *val)
1219{
1220 struct drm_device *dev = connector->dev;
1221 struct amdgpu_device *adev = dev->dev_private;
1222 struct dm_connector_state *dm_state =
1223 to_dm_connector_state(state);
1224 int ret = -EINVAL;
1225
1226 if (property == dev->mode_config.scaling_mode_property) {
1227 switch (dm_state->scaling) {
1228 case RMX_CENTER:
1229 *val = DRM_MODE_SCALE_CENTER;
1230 break;
1231 case RMX_ASPECT:
1232 *val = DRM_MODE_SCALE_ASPECT;
1233 break;
1234 case RMX_FULL:
1235 *val = DRM_MODE_SCALE_FULLSCREEN;
1236 break;
1237 case RMX_OFF:
1238 default:
1239 *val = DRM_MODE_SCALE_NONE;
1240 break;
1241 }
1242 ret = 0;
1243 } else if (property == adev->mode_info.underscan_hborder_property) {
1244 *val = dm_state->underscan_hborder;
1245 ret = 0;
1246 } else if (property == adev->mode_info.underscan_vborder_property) {
1247 *val = dm_state->underscan_vborder;
1248 ret = 0;
1249 } else if (property == adev->mode_info.underscan_property) {
1250 *val = dm_state->underscan_enable;
1251 ret = 0;
1252 }
1253 return ret;
1254}
1255
4562236b
HW		 1256void amdgpu_dm_connector_destroy(struct drm_connector *connector)
1257{
1258 struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
1259 const struct dc_link *link = aconnector->dc_link;
1260 struct amdgpu_device *adev = connector->dev->dev_private;
1261 struct amdgpu_display_manager *dm = &adev->dm;
1262#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1263 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1264
1265 if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) {
1266 amdgpu_dm_register_backlight_device(dm);
1267
1268 if (dm->backlight_dev) {
1269 backlight_device_unregister(dm->backlight_dev);
1270 dm->backlight_dev = NULL;
1271 }
1272
1273 }
1274#endif
1275 drm_connector_unregister(connector);
1276 drm_connector_cleanup(connector);
1277 kfree(connector);
1278}
1279
1280void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
1281{
1282 struct dm_connector_state *state =
1283 to_dm_connector_state(connector->state);
1284
1285 kfree(state);
1286
1287 state = kzalloc(sizeof(*state), GFP_KERNEL);
1288
1289 if (state) {
1290 state->scaling = RMX_OFF;
1291 state->underscan_enable = false;
1292 state->underscan_hborder = 0;
1293 state->underscan_vborder = 0;
1294
1295 connector->state = &state->base;
1296 connector->state->connector = connector;
1297 }
1298}
1299
1300struct drm_connector_state *amdgpu_dm_connector_atomic_duplicate_state(
1301 struct drm_connector *connector)
1302{
1303 struct dm_connector_state *state =
1304 to_dm_connector_state(connector->state);
1305
1306 struct dm_connector_state *new_state =
1307 kmemdup(state, sizeof(*state), GFP_KERNEL);
1308
1309 if (new_state) {
1310 __drm_atomic_helper_connector_duplicate_state(connector,
1311 &new_state->base);
1312 return &new_state->base;
1313 }
1314
1315 return NULL;
1316}
1317
1318static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
1319 .reset = amdgpu_dm_connector_funcs_reset,
1320 .detect = amdgpu_dm_connector_detect,
1321 .fill_modes = drm_helper_probe_single_connector_modes,
1322 .destroy = amdgpu_dm_connector_destroy,
1323 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
1324 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
664a2ed1 1325 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
32a1892a 1326 .atomic_get_property = amdgpu_dm_connector_atomic_get_property
4562236b
HW		 1327};
1328
1329static struct drm_encoder *best_encoder(struct drm_connector *connector)
1330{
1331 int enc_id = connector->encoder_ids[0];
1332 struct drm_mode_object *obj;
1333 struct drm_encoder *encoder;
1334
1335 DRM_DEBUG_KMS("Finding the best encoder\n");
1336
1337 /* pick the encoder ids */
1338 if (enc_id) {
1339 obj = drm_mode_object_find(connector->dev, enc_id, DRM_MODE_OBJECT_ENCODER);
1340 if (!obj) {
1341 DRM_ERROR("Couldn't find a matching encoder for our connector\n");
1342 return NULL;
1343 }
1344 encoder = obj_to_encoder(obj);
1345 return encoder;
1346 }
1347 DRM_ERROR("No encoder id\n");
1348 return NULL;
1349}
1350
1351static int get_modes(struct drm_connector *connector)
1352{
1353 return amdgpu_dm_connector_get_modes(connector);
1354}
1355
1356static void create_eml_sink(struct amdgpu_connector *aconnector)
1357{
1358 struct dc_sink_init_data init_params = {
1359 .link = aconnector->dc_link,
1360 .sink_signal = SIGNAL_TYPE_VIRTUAL
1361 };
1362 struct edid *edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
1363
1364 if (!aconnector->base.edid_blob_ptr ||
1365 !aconnector->base.edid_blob_ptr->data) {
1366 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
1367 aconnector->base.name);
1368
1369 aconnector->base.force = DRM_FORCE_OFF;
1370 aconnector->base.override_edid = false;
1371 return;
1372 }
1373
1374 aconnector->edid = edid;
1375
1376 aconnector->dc_em_sink = dc_link_add_remote_sink(
1377 aconnector->dc_link,
1378 (uint8_t *)edid,
1379 (edid->extensions + 1) * EDID_LENGTH,
1380 &init_params);
1381
1382 if (aconnector->base.force
1383 == DRM_FORCE_ON)
1384 aconnector->dc_sink = aconnector->dc_link->local_sink ?
1385 aconnector->dc_link->local_sink :
1386 aconnector->dc_em_sink;
1387}
1388
1389static void handle_edid_mgmt(struct amdgpu_connector *aconnector)
1390{
1391 struct dc_link *link = (struct dc_link *)aconnector->dc_link;
1392
1393 /* In case of headless boot with force on for DP managed connector
1394 * Those settings have to be != 0 to get initial modeset
1395 */
1396 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
1397 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
1398 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
1399 }
1400
1401
1402 aconnector->base.override_edid = true;
1403 create_eml_sink(aconnector);
1404}
1405
1406int amdgpu_dm_connector_mode_valid(
1407 struct drm_connector *connector,
1408 struct drm_display_mode *mode)
1409{
1410 int result = MODE_ERROR;
1411 const struct dc_sink *dc_sink;
1412 struct amdgpu_device *adev = connector->dev->dev_private;
1413 struct dc_validation_set val_set = { 0 };
1414 /* TODO: Unhardcode stream count */
ab2541b6 1415 struct dc_stream *stream;
4562236b 1416 struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
07d72b39 1417 struct validate_context *context;
4562236b
HW		 1418
1419 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1420 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
1421 return result;
1422
1423 /* Only run this the first time mode_valid is called to initilialize
1424 * EDID mgmt
1425 */
1426 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
1427 !aconnector->dc_em_sink)
1428 handle_edid_mgmt(aconnector);
1429
1430 dc_sink = to_amdgpu_connector(connector)->dc_sink;
1431
1432 if (NULL == dc_sink) {
1433 DRM_ERROR("dc_sink is NULL!\n");
ab2541b6 1434 goto null_sink;
4562236b
HW		 1435 }
1436
ab2541b6
AC		 1437 stream = dc_create_stream_for_sink(dc_sink);
1438 if (NULL == stream) {
4562236b
HW		 1439 DRM_ERROR("Failed to create stream for sink!\n");
1440 goto stream_create_fail;
1441 }
1442
1443 drm_mode_set_crtcinfo(mode, 0);
ab2541b6 1444 fill_stream_properties_from_drm_display_mode(stream, mode, connector);
4562236b 1445
ab2541b6 1446 val_set.stream = stream;
4562236b 1447 val_set.surface_count = 0;
ab2541b6
AC		 1448 stream->src.width = mode->hdisplay;
1449 stream->src.height = mode->vdisplay;
1450 stream->dst = stream->src;
4562236b 1451
07d72b39
HW		 1452 context = dc_get_validate_context(adev->dm.dc, &val_set, 1);
1453
1454 if (context) {
4562236b 1455 result = MODE_OK;
07d72b39
HW		 1456 dc_resource_validate_ctx_destruct(context);
1457 dm_free(context);
1458 }
4562236b 1459
ab2541b6
AC		 1460 dc_stream_release(stream);
1461
4562236b 1462stream_create_fail:
ab2541b6 1463null_sink:
4562236b
HW		 1464 /* TODO: error handling*/
1465 return result;
1466}
1467
1468static const struct drm_connector_helper_funcs
1469amdgpu_dm_connector_helper_funcs = {
1470 /*
1471 * If hotplug a second bigger display in FB Con mode, bigger resolution
1472 * modes will be filtered by drm_mode_validate_size(), and those modes
1473 * is missing after user start lightdm. So we need to renew modes list.
1474 * in get_modes call back, not just return the modes count
1475 */
1476 .get_modes = get_modes,
1477 .mode_valid = amdgpu_dm_connector_mode_valid,
1478 .best_encoder = best_encoder
1479};
1480
1481static void dm_crtc_helper_disable(struct drm_crtc *crtc)
1482{
1483}
1484
1485static int dm_crtc_helper_atomic_check(
1486 struct drm_crtc *crtc,
1487 struct drm_crtc_state *state)
1488{
1489 return 0;
1490}
1491
1492static bool dm_crtc_helper_mode_fixup(
1493 struct drm_crtc *crtc,
1494 const struct drm_display_mode *mode,
1495 struct drm_display_mode *adjusted_mode)
1496{
1497 return true;
1498}
1499
1500static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
1501 .disable = dm_crtc_helper_disable,
1502 .atomic_check = dm_crtc_helper_atomic_check,
1503 .mode_fixup = dm_crtc_helper_mode_fixup
1504};
1505
1506static void dm_encoder_helper_disable(struct drm_encoder *encoder)
1507{
1508
1509}
1510
1511static int dm_encoder_helper_atomic_check(
1512 struct drm_encoder *encoder,
1513 struct drm_crtc_state *crtc_state,
1514 struct drm_connector_state *conn_state)
1515{
1516 return 0;
1517}
1518
1519const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
1520 .disable = dm_encoder_helper_disable,
1521 .atomic_check = dm_encoder_helper_atomic_check
1522};
1523
64d8b780
S		 1524static void dm_drm_plane_reset(struct drm_plane *plane)
1525{
1526 struct amdgpu_drm_plane_state *amdgpu_state;
1527
1528 if (plane->state) {
1529 amdgpu_state = to_amdgpu_plane_state(plane->state);
1530 if (amdgpu_state->base.fb)
1531 drm_framebuffer_unreference(amdgpu_state->base.fb);
1532 kfree(amdgpu_state);
1533 plane->state = NULL;
1534 }
1535
1536 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
1537 if (amdgpu_state) {
1538 plane->state = &amdgpu_state->base;
1539 plane->state->plane = plane;
1540 }
1541}
1542
1543static struct drm_plane_state *
1544dm_drm_plane_duplicate_state(struct drm_plane *plane)
1545{
1546 struct amdgpu_drm_plane_state *amdgpu_state;
1547 struct amdgpu_drm_plane_state *copy;
1548
1549 amdgpu_state = to_amdgpu_plane_state(plane->state);
1550 copy = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
1551 if (!copy)
1552 return NULL;
1553
1554 __drm_atomic_helper_plane_duplicate_state(plane, &copy->base);
1555 return &copy->base;
1556}
1557
1558static void dm_drm_plane_destroy_state(struct drm_plane *plane,
1559 struct drm_plane_state *old_state)
1560{
1561 struct amdgpu_drm_plane_state *old_amdgpu_state =
1562 to_amdgpu_plane_state(old_state);
1563 __drm_atomic_helper_plane_destroy_state(old_state);
1564 kfree(old_amdgpu_state);
1565}
1566
4562236b 1567static const struct drm_plane_funcs dm_plane_funcs = {
64d8b780
S		 1568 .update_plane = drm_atomic_helper_update_plane,
1569 .disable_plane = drm_atomic_helper_disable_plane,
1570 .destroy = drm_plane_cleanup,
1571 .reset = dm_drm_plane_reset,
1572 .atomic_duplicate_state = dm_drm_plane_duplicate_state,
1573 .atomic_destroy_state = dm_drm_plane_destroy_state,
4562236b
HW		 1574};
1575
4562236b
HW		 1576static int dm_plane_helper_prepare_fb(
1577 struct drm_plane *plane,
1578 struct drm_plane_state *new_state)
1579{
1580 struct amdgpu_framebuffer *afb;
1581 struct drm_gem_object *obj;
1582 struct amdgpu_bo *rbo;
1583 int r;
1584
1585 if (!new_state->fb) {
1586 DRM_DEBUG_KMS("No FB bound\n");
1587 return 0;
1588 }
1589
1590 afb = to_amdgpu_framebuffer(new_state->fb);
1591
1592 obj = afb->obj;
1593 rbo = gem_to_amdgpu_bo(obj);
1594 r = amdgpu_bo_reserve(rbo, false);
1595 if (unlikely(r != 0))
1596 return r;
1597
54f5499a 1598 r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &afb->address);
4562236b
HW		 1599
1600 amdgpu_bo_unreserve(rbo);
1601
1602 if (unlikely(r != 0)) {
1603 DRM_ERROR("Failed to pin framebuffer\n");
1604 return r;
1605 }
1606
54f5499a 1607 amdgpu_bo_ref(rbo);
4562236b
HW		 1608 return 0;
1609}
1610
1611static void dm_plane_helper_cleanup_fb(
1612 struct drm_plane *plane,
1613 struct drm_plane_state *old_state)
1614{
1615 struct amdgpu_bo *rbo;
1616 struct amdgpu_framebuffer *afb;
1617 int r;
1618
1619 if (!old_state->fb)
1620 return;
1621
1622 afb = to_amdgpu_framebuffer(old_state->fb);
1623 rbo = gem_to_amdgpu_bo(afb->obj);
1624 r = amdgpu_bo_reserve(rbo, false);
1625 if (unlikely(r)) {
1626 DRM_ERROR("failed to reserve rbo before unpin\n");
1627 return;
1628 } else {
1629 amdgpu_bo_unpin(rbo);
1630 amdgpu_bo_unreserve(rbo);
54f5499a 1631 amdgpu_bo_unref(&rbo);
4562236b 1632 }
54f5499a
AG		 1633
1634 afb->address = 0;
4562236b
HW		 1635}
1636
ab2541b6 1637int dm_create_validation_set_for_connector(struct drm_connector *connector,
4562236b
HW		 1638 struct drm_display_mode *mode, struct dc_validation_set *val_set)
1639{
1640 int result = MODE_ERROR;
1641 const struct dc_sink *dc_sink =
1642 to_amdgpu_connector(connector)->dc_sink;
1643 /* TODO: Unhardcode stream count */
ab2541b6 1644 struct dc_stream *stream;
4562236b
HW		 1645
1646 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1647 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
1648 return result;
1649
1650 if (NULL == dc_sink) {
1651 DRM_ERROR("dc_sink is NULL!\n");
1652 return result;
1653 }
1654
ab2541b6 1655 stream = dc_create_stream_for_sink(dc_sink);
4562236b 1656
ab2541b6 1657 if (NULL == stream) {
4562236b
HW		 1658 DRM_ERROR("Failed to create stream for sink!\n");
1659 return result;
1660 }
1661
1662 drm_mode_set_crtcinfo(mode, 0);
1663
ab2541b6 1664 fill_stream_properties_from_drm_display_mode(stream, mode, connector);
4562236b 1665
ab2541b6 1666 val_set->stream = stream;
4562236b 1667
ab2541b6
AC		 1668 stream->src.width = mode->hdisplay;
1669 stream->src.height = mode->vdisplay;
1670 stream->dst = stream->src;
4562236b
HW		 1671
1672 return MODE_OK;
4562236b
HW		 1673}
1674
1675static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
1676 .prepare_fb = dm_plane_helper_prepare_fb,
1677 .cleanup_fb = dm_plane_helper_cleanup_fb,
1678};
1679
1680/*
1681 * TODO: these are currently initialized to rgb formats only.
1682 * For future use cases we should either initialize them dynamically based on
1683 * plane capabilities, or initialize this array to all formats, so internal drm
1684 * check will succeed, and let DC to implement proper check
1685 */
1686static uint32_t rgb_formats[] = {
1687 DRM_FORMAT_XRGB4444,
1688 DRM_FORMAT_ARGB4444,
1689 DRM_FORMAT_RGBA4444,
1690 DRM_FORMAT_ARGB1555,
1691 DRM_FORMAT_RGB565,
1692 DRM_FORMAT_RGB888,
1693 DRM_FORMAT_XRGB8888,
1694 DRM_FORMAT_ARGB8888,
1695 DRM_FORMAT_RGBA8888,
1696 DRM_FORMAT_XRGB2101010,
1697 DRM_FORMAT_XBGR2101010,
1698 DRM_FORMAT_ARGB2101010,
1699 DRM_FORMAT_ABGR2101010,
1700};
1701
d4e13b0d 1702static uint32_t yuv_formats[] = {
e6fbd5df
S		 1703 DRM_FORMAT_YUV420,
1704 DRM_FORMAT_YVU420,
d4e13b0d 1705};
4562236b 1706
d4e13b0d
AD		 1707int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
1708 struct amdgpu_plane *aplane,
1709 unsigned long possible_crtcs)
1710{
1711 int res = -EPERM;
1712
1713 switch (aplane->plane_type) {
1714 case DRM_PLANE_TYPE_PRIMARY:
1715 aplane->base.format_default = true;
1716
1717 res = drm_universal_plane_init(
1718 dm->adev->ddev,
1719 &aplane->base,
1720 possible_crtcs,
1721 &dm_plane_funcs,
1722 rgb_formats,
1723 ARRAY_SIZE(rgb_formats),
1724 NULL, aplane->plane_type, NULL);
1725 break;
1726 case DRM_PLANE_TYPE_OVERLAY:
1727 res = drm_universal_plane_init(
1728 dm->adev->ddev,
1729 &aplane->base,
1730 possible_crtcs,
1731 &dm_plane_funcs,
1732 yuv_formats,
1733 ARRAY_SIZE(yuv_formats),
1734 NULL, aplane->plane_type, NULL);
1735 break;
1736 case DRM_PLANE_TYPE_CURSOR:
1737 DRM_ERROR("KMS: Cursor plane not implemented.");
1738 break;
1739 }
4562236b 1740
d4e13b0d 1741 drm_plane_helper_add(&aplane->base, &dm_plane_helper_funcs);
4562236b 1742
d4e13b0d
AD		 1743 return res;
1744}
4562236b 1745
d4e13b0d
AD		 1746int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
1747 struct drm_plane *plane,
1748 uint32_t crtc_index)
1749{
1750 struct amdgpu_crtc *acrtc;
1751 int res = -ENOMEM;
4562236b 1752
d4e13b0d
AD		 1753 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
1754 if (!acrtc)
1755 goto fail;
4562236b
HW		 1756
1757 res = drm_crtc_init_with_planes(
1758 dm->ddev,
1759 &acrtc->base,
d4e13b0d 1760 plane,
4562236b
HW		 1761 NULL,
1762 &amdgpu_dm_crtc_funcs, NULL);
1763
1764 if (res)
1765 goto fail;
1766
1767 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
1768
10349345
AG		 1769 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
1770 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
4562236b
HW		 1771
1772 acrtc->crtc_id = crtc_index;
1773 acrtc->base.enabled = false;
1774
1775 dm->adev->mode_info.crtcs[crtc_index] = acrtc;
1776 drm_mode_crtc_set_gamma_size(&acrtc->base, 256);
1777
1778 return 0;
1779fail:
d4e13b0d 1780 kfree(acrtc);
4562236b
HW		 1781 acrtc->crtc_id = -1;
1782 return res;
1783}
1784
1785static int to_drm_connector_type(enum signal_type st)
1786{
1787 switch (st) {
1788 case SIGNAL_TYPE_HDMI_TYPE_A:
1789 return DRM_MODE_CONNECTOR_HDMIA;
1790 case SIGNAL_TYPE_EDP:
1791 return DRM_MODE_CONNECTOR_eDP;
1792 case SIGNAL_TYPE_RGB:
1793 return DRM_MODE_CONNECTOR_VGA;
1794 case SIGNAL_TYPE_DISPLAY_PORT:
1795 case SIGNAL_TYPE_DISPLAY_PORT_MST:
1796 return DRM_MODE_CONNECTOR_DisplayPort;
1797 case SIGNAL_TYPE_DVI_DUAL_LINK:
1798 case SIGNAL_TYPE_DVI_SINGLE_LINK:
1799 return DRM_MODE_CONNECTOR_DVID;
1800 case SIGNAL_TYPE_VIRTUAL:
1801 return DRM_MODE_CONNECTOR_VIRTUAL;
1802
1803 default:
1804 return DRM_MODE_CONNECTOR_Unknown;
1805 }
1806}
1807
1808static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
1809{
1810 const struct drm_connector_helper_funcs *helper =
1811 connector->helper_private;
1812 struct drm_encoder *encoder;
1813 struct amdgpu_encoder *amdgpu_encoder;
1814
1815 encoder = helper->best_encoder(connector);
1816
1817 if (encoder == NULL)
1818 return;
1819
1820 amdgpu_encoder = to_amdgpu_encoder(encoder);
1821
1822 amdgpu_encoder->native_mode.clock = 0;
1823
1824 if (!list_empty(&connector->probed_modes)) {
1825 struct drm_display_mode *preferred_mode = NULL;
1826 list_for_each_entry(preferred_mode,
1827 &connector->probed_modes,
1828 head) {
1829 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
1830 amdgpu_encoder->native_mode = *preferred_mode;
1831 }
1832 break;
1833 }
1834
1835 }
1836}
1837
1838static struct drm_display_mode *amdgpu_dm_create_common_mode(
1839 struct drm_encoder *encoder, char *name,
1840 int hdisplay, int vdisplay)
1841{
1842 struct drm_device *dev = encoder->dev;
1843 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1844 struct drm_display_mode *mode = NULL;
1845 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1846
1847 mode = drm_mode_duplicate(dev, native_mode);
1848
1849 if(mode == NULL)
1850 return NULL;
1851
1852 mode->hdisplay = hdisplay;
1853 mode->vdisplay = vdisplay;
1854 mode->type &= ~DRM_MODE_TYPE_PREFERRED;
1855 strncpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
1856
1857 return mode;
1858
1859}
1860
1861static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
1862 struct drm_connector *connector)
1863{
1864 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1865 struct drm_display_mode *mode = NULL;
1866 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1867 struct amdgpu_connector *amdgpu_connector =
1868 to_amdgpu_connector(connector);
1869 int i;
1870 int n;
1871 struct mode_size {
1872 char name[DRM_DISPLAY_MODE_LEN];
1873 int w;
1874 int h;
1875 }common_modes[] = {
1876 { "640x480", 640, 480},
1877 { "800x600", 800, 600},
1878 { "1024x768", 1024, 768},
1879 { "1280x720", 1280, 720},
1880 { "1280x800", 1280, 800},
1881 {"1280x1024", 1280, 1024},
1882 { "1440x900", 1440, 900},
1883 {"1680x1050", 1680, 1050},
1884 {"1600x1200", 1600, 1200},
1885 {"1920x1080", 1920, 1080},
1886 {"1920x1200", 1920, 1200}
1887 };
1888
1889 n = sizeof(common_modes) / sizeof(common_modes[0]);
1890
1891 for (i = 0; i < n; i++) {
1892 struct drm_display_mode *curmode = NULL;
1893 bool mode_existed = false;
1894
1895 if (common_modes[i].w > native_mode->hdisplay ||
1896 common_modes[i].h > native_mode->vdisplay ||
1897 (common_modes[i].w == native_mode->hdisplay &&
1898 common_modes[i].h == native_mode->vdisplay))
1899 continue;
1900
1901 list_for_each_entry(curmode, &connector->probed_modes, head) {
1902 if (common_modes[i].w == curmode->hdisplay &&
1903 common_modes[i].h == curmode->vdisplay) {
1904 mode_existed = true;
1905 break;
1906 }
1907 }
1908
1909 if (mode_existed)
1910 continue;
1911
1912 mode = amdgpu_dm_create_common_mode(encoder,
1913 common_modes[i].name, common_modes[i].w,
1914 common_modes[i].h);
1915 drm_mode_probed_add(connector, mode);
1916 amdgpu_connector->num_modes++;
1917 }
1918}
1919
1920static void amdgpu_dm_connector_ddc_get_modes(
1921 struct drm_connector *connector,
1922 struct edid *edid)
1923{
1924 struct amdgpu_connector *amdgpu_connector =
1925 to_amdgpu_connector(connector);
1926
1927 if (edid) {
1928 /* empty probed_modes */
1929 INIT_LIST_HEAD(&connector->probed_modes);
1930 amdgpu_connector->num_modes =
1931 drm_add_edid_modes(connector, edid);
1932
1933 drm_edid_to_eld(connector, edid);
1934
1935 amdgpu_dm_get_native_mode(connector);
1936 } else
1937 amdgpu_connector->num_modes = 0;
1938}
1939
1940int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
1941{
1942 const struct drm_connector_helper_funcs *helper =
1943 connector->helper_private;
1944 struct amdgpu_connector *amdgpu_connector =
1945 to_amdgpu_connector(connector);
1946 struct drm_encoder *encoder;
1947 struct edid *edid = amdgpu_connector->edid;
1948
1949 encoder = helper->best_encoder(connector);
1950
1951 amdgpu_dm_connector_ddc_get_modes(connector, edid);
1952 amdgpu_dm_connector_add_common_modes(encoder, connector);
1953 return amdgpu_connector->num_modes;
1954}
1955
1956void amdgpu_dm_connector_init_helper(
1957 struct amdgpu_display_manager *dm,
1958 struct amdgpu_connector *aconnector,
1959 int connector_type,
1960 const struct dc_link *link,
1961 int link_index)
1962{
1963 struct amdgpu_device *adev = dm->ddev->dev_private;
1964
1965 aconnector->connector_id = link_index;
1966 aconnector->dc_link = link;
67a27705
HW		 1967 aconnector->base.interlace_allowed = false;
1968 aconnector->base.doublescan_allowed = false;
1969 aconnector->base.stereo_allowed = false;
4562236b
HW		 1970 aconnector->base.dpms = DRM_MODE_DPMS_OFF;
1971 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
1972
1973 mutex_init(&aconnector->hpd_lock);
1974
1975 /*configure suport HPD hot plug connector_>polled default value is 0
1976 * which means HPD hot plug not supported*/
1977 switch (connector_type) {
1978 case DRM_MODE_CONNECTOR_HDMIA:
1979 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
1980 break;
1981 case DRM_MODE_CONNECTOR_DisplayPort:
1982 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
1983 break;
1984 case DRM_MODE_CONNECTOR_DVID:
1985 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
1986 break;
1987 default:
1988 break;
1989 }
1990
1991 drm_object_attach_property(&aconnector->base.base,
1992 dm->ddev->mode_config.scaling_mode_property,
1993 DRM_MODE_SCALE_NONE);
1994
1995 drm_object_attach_property(&aconnector->base.base,
1996 adev->mode_info.underscan_property,
1997 UNDERSCAN_OFF);
1998 drm_object_attach_property(&aconnector->base.base,
1999 adev->mode_info.underscan_hborder_property,
2000 0);
2001 drm_object_attach_property(&aconnector->base.base,
2002 adev->mode_info.underscan_vborder_property,
2003 0);
2004
2005}
2006
2007int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
2008 struct i2c_msg *msgs, int num)
2009{
2010 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
2011 struct i2c_command cmd;
2012 int i;
2013 int result = -EIO;
2014
2015 cmd.payloads = kzalloc(num * sizeof(struct i2c_payload), GFP_KERNEL);
2016
2017 if (!cmd.payloads)
2018 return result;
2019
2020 cmd.number_of_payloads = num;
2021 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
2022 cmd.speed = 100;
2023
2024 for (i = 0; i < num; i++) {
bb01672c 2025 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
4562236b
HW		 2026 cmd.payloads[i].address = msgs[i].addr;
2027 cmd.payloads[i].length = msgs[i].len;
2028 cmd.payloads[i].data = msgs[i].buf;
2029 }
2030
2031 if (dc_submit_i2c(i2c->dm->dc, i2c->link_index, &cmd))
2032 result = num;
2033
2034 kfree(cmd.payloads);
2035
2036 return result;
2037}
2038
2039u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
2040{
2041 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2042}
2043
2044static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
2045 .master_xfer = amdgpu_dm_i2c_xfer,
2046 .functionality = amdgpu_dm_i2c_func,
2047};
2048
2049struct amdgpu_i2c_adapter *create_i2c(unsigned int link_index, struct amdgpu_display_manager *dm, int *res)
2050{
2051 struct amdgpu_i2c_adapter *i2c;
2052
2053 i2c = kzalloc(sizeof (struct amdgpu_i2c_adapter), GFP_KERNEL);
2054 i2c->dm = dm;
2055 i2c->base.owner = THIS_MODULE;
2056 i2c->base.class = I2C_CLASS_DDC;
2057 i2c->base.dev.parent = &dm->adev->pdev->dev;
2058 i2c->base.algo = &amdgpu_dm_i2c_algo;
2059 snprintf(i2c->base.name, sizeof (i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
2060 i2c->link_index = link_index;
2061 i2c_set_adapdata(&i2c->base, i2c);
2062
2063 return i2c;
2064}
2065
2066/* Note: this function assumes that dc_link_detect() was called for the
2067 * dc_link which will be represented by this aconnector. */
2068int amdgpu_dm_connector_init(
2069 struct amdgpu_display_manager *dm,
2070 struct amdgpu_connector *aconnector,
2071 uint32_t link_index,
2072 struct amdgpu_encoder *aencoder)
2073{
2074 int res = 0;
2075 int connector_type;
2076 struct dc *dc = dm->dc;
2077 const struct dc_link *link = dc_get_link_at_index(dc, link_index);
2078 struct amdgpu_i2c_adapter *i2c;
9fb8de78 2079 ((struct dc_link *)link)->priv = aconnector;
4562236b
HW		 2080
2081 DRM_DEBUG_KMS("%s()\n", __func__);
2082
2083 i2c = create_i2c(link->link_index, dm, &res);
2084 aconnector->i2c = i2c;
2085 res = i2c_add_adapter(&i2c->base);
2086
2087 if (res) {
2088 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
2089 goto out_free;
2090 }
2091
2092 connector_type = to_drm_connector_type(link->connector_signal);
2093
2094 res = drm_connector_init(
2095 dm->ddev,
2096 &aconnector->base,
2097 &amdgpu_dm_connector_funcs,
2098 connector_type);
2099
2100 if (res) {
2101 DRM_ERROR("connector_init failed\n");
2102 aconnector->connector_id = -1;
2103 goto out_free;
2104 }
2105
2106 drm_connector_helper_add(
2107 &aconnector->base,
2108 &amdgpu_dm_connector_helper_funcs);
2109
2110 amdgpu_dm_connector_init_helper(
2111 dm,
2112 aconnector,
2113 connector_type,
2114 link,
2115 link_index);
2116
2117 drm_mode_connector_attach_encoder(
2118 &aconnector->base, &aencoder->base);
2119
2120 drm_connector_register(&aconnector->base);
2121
2122 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
2123 || connector_type == DRM_MODE_CONNECTOR_eDP)
7c7f5b15 2124 amdgpu_dm_initialize_dp_connector(dm, aconnector);
4562236b
HW		 2125
2126#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
2127 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
2128
2129 /* NOTE: this currently will create backlight device even if a panel
2130 * is not connected to the eDP/LVDS connector.
2131 *
2132 * This is less than ideal but we don't have sink information at this
2133 * stage since detection happens after. We can't do detection earlier
2134 * since MST detection needs connectors to be created first.
2135 */
2136 if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) {
2137 /* Event if registration failed, we should continue with
2138 * DM initialization because not having a backlight control
2139 * is better then a black screen. */
2140 amdgpu_dm_register_backlight_device(dm);
2141
2142 if (dm->backlight_dev)
2143 dm->backlight_link = link;
2144 }
2145#endif
2146
2147out_free:
2148 if (res) {
2149 kfree(i2c);
2150 aconnector->i2c = NULL;
2151 }
2152 return res;
2153}
2154
2155int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
2156{
2157 switch (adev->mode_info.num_crtc) {
2158 case 1:
2159 return 0x1;
2160 case 2:
2161 return 0x3;
2162 case 3:
2163 return 0x7;
2164 case 4:
2165 return 0xf;
2166 case 5:
2167 return 0x1f;
2168 case 6:
2169 default:
2170 return 0x3f;
2171 }
2172}
2173
2174int amdgpu_dm_encoder_init(
2175 struct drm_device *dev,
2176 struct amdgpu_encoder *aencoder,
2177 uint32_t link_index)
2178{
2179 struct amdgpu_device *adev = dev->dev_private;
2180
2181 int res = drm_encoder_init(dev,
2182 &aencoder->base,
2183 &amdgpu_dm_encoder_funcs,
2184 DRM_MODE_ENCODER_TMDS,
2185 NULL);
2186
2187 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
2188
2189 if (!res)
2190 aencoder->encoder_id = link_index;
2191 else
2192 aencoder->encoder_id = -1;
2193
2194 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
2195
2196 return res;
2197}
2198
2199enum dm_commit_action {
2200 DM_COMMIT_ACTION_NOTHING,
2201 DM_COMMIT_ACTION_RESET,
2202 DM_COMMIT_ACTION_DPMS_ON,
2203 DM_COMMIT_ACTION_DPMS_OFF,
2204 DM_COMMIT_ACTION_SET
2205};
2206
2207static enum dm_commit_action get_dm_commit_action(struct drm_crtc_state *state)
2208{
2209 /* mode changed means either actually mode changed or enabled changed */
2210 /* active changed means dpms changed */
2211
2212 DRM_DEBUG_KMS("crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n",
2213 state->enable,
2214 state->active,
2215 state->planes_changed,
2216 state->mode_changed,
2217 state->active_changed,
2218 state->connectors_changed);
2219
2220 if (state->mode_changed) {
2221 /* if it is got disabled - call reset mode */
2222 if (!state->enable)
2223 return DM_COMMIT_ACTION_RESET;
2224
2225 if (state->active)
2226 return DM_COMMIT_ACTION_SET;
2227 else
2228 return DM_COMMIT_ACTION_RESET;
2229 } else {
2230 /* ! mode_changed */
2231
2232 /* if it is remain disable - skip it */
2233 if (!state->enable)
2234 return DM_COMMIT_ACTION_NOTHING;
2235
2236 if (state->active && state->connectors_changed)
2237 return DM_COMMIT_ACTION_SET;
2238
2239 if (state->active_changed) {
2240 if (state->active) {
2241 return DM_COMMIT_ACTION_DPMS_ON;
2242 } else {
2243 return DM_COMMIT_ACTION_DPMS_OFF;
2244 }
2245 } else {
2246 /* ! active_changed */
2247 return DM_COMMIT_ACTION_NOTHING;
2248 }
2249 }
2250}
2251
4562236b
HW		 2252static void manage_dm_interrupts(
2253 struct amdgpu_device *adev,
2254 struct amdgpu_crtc *acrtc,
2255 bool enable)
2256{
2257 /*
2258 * this is not correct translation but will work as soon as VBLANK
2259 * constant is the same as PFLIP
2260 */
2261 int irq_type =
2262 amdgpu_crtc_idx_to_irq_type(
2263 adev,
2264 acrtc->crtc_id);
2265
2266 if (enable) {
2267 drm_crtc_vblank_on(&acrtc->base);
2268 amdgpu_irq_get(
2269 adev,
2270 &adev->pageflip_irq,
2271 irq_type);
2272 } else {
4562236b
HW		 2273
2274 amdgpu_irq_put(
2275 adev,
2276 &adev->pageflip_irq,
2277 irq_type);
2278 drm_crtc_vblank_off(&acrtc->base);
2279 }
2280}
2281
4562236b
HW		 2282static bool is_scaling_state_different(
2283 const struct dm_connector_state *dm_state,
2284 const struct dm_connector_state *old_dm_state)
2285{
2286 if (dm_state->scaling != old_dm_state->scaling)
2287 return true;
2288 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
2289 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
2290 return true;
2291 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
2292 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
2293 return true;
2294 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder
2295 || dm_state->underscan_vborder != old_dm_state->underscan_vborder)
2296 return true;
2297 return false;
2298}
2299
ab2541b6 2300static void remove_stream(struct amdgpu_device *adev, struct amdgpu_crtc *acrtc)
4562236b 2301{
4562236b
HW		 2302 /*
2303 * we evade vblanks and pflips on crtc that
2304 * should be changed
2305 */
2306 manage_dm_interrupts(adev, acrtc, false);
ab2541b6 2307
4562236b
HW		 2308 /* this is the update mode case */
2309 if (adev->dm.freesync_module)
ab2541b6
AC		 2310 mod_freesync_remove_stream(adev->dm.freesync_module,
2311 acrtc->stream);
2312
2313 dc_stream_release(acrtc->stream);
2314 acrtc->stream = NULL;
4562236b
HW		 2315 acrtc->otg_inst = -1;
2316 acrtc->enabled = false;
2317}
2318
54f5499a
AG		 2319
2320/*
2321 * Executes flip
2322 *
2323 * Waits on all BO's fences and for proper vblank count
2324 */
2325static void amdgpu_dm_do_flip(
2326 struct drm_crtc *crtc,
2327 struct drm_framebuffer *fb,
2328 uint32_t target)
2329{
2330 unsigned long flags;
2331 uint32_t target_vblank;
2332 int r, vpos, hpos;
2333 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2334 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
2335 struct amdgpu_bo *abo = gem_to_amdgpu_bo(afb->obj);
2336 struct amdgpu_device *adev = crtc->dev->dev_private;
2337 bool async_flip = (acrtc->flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
2338
00d7930c
MK		 2339 /* Prepare wait for target vblank early - before the fence-waits */
2340 target_vblank = target - drm_crtc_vblank_count(crtc) +
2341 amdgpu_get_vblank_counter_kms(crtc->dev, acrtc->crtc_id);
54f5499a
AG		 2342
2343 /*TODO This might fail and hence better not used, wait
2344 * explicitly on fences instead
2345 * and in general should be called for
2346 * blocking commit to as per framework helpers
2347 * */
2348 r = amdgpu_bo_reserve(abo, true);
2349 if (unlikely(r != 0)) {
2350 DRM_ERROR("failed to reserve buffer before flip\n");
2351 BUG_ON(0);
2352 }
2353
2354 /* Wait for all fences on this FB */
2355 WARN_ON(reservation_object_wait_timeout_rcu(abo->tbo.resv, true, false,
2356 MAX_SCHEDULE_TIMEOUT) < 0);
2357
2358 amdgpu_bo_unreserve(abo);
2359
54f5499a
AG		 2360 /* Wait until we're out of the vertical blank period before the one
2361 * targeted by the flip
2362 */
54f5499a
AG		 2363 while ((acrtc->enabled &&
2364 (amdgpu_get_crtc_scanoutpos(adev->ddev, acrtc->crtc_id, 0,
2365 &vpos, &hpos, NULL, NULL,
2366 &crtc->hwmode)
2367 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
2368 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
2369 (int)(target_vblank -
2370 amdgpu_get_vblank_counter_kms(adev->ddev, acrtc->crtc_id)) > 0)) {
2371 usleep_range(1000, 1100);
2372 }
2373
2374 /* Flip */
2375 spin_lock_irqsave(&crtc->dev->event_lock, flags);
2376 /* update crtc fb */
2377 crtc->primary->fb = fb;
2378
2379 /* Do the flip (mmio) */
2380 adev->mode_info.funcs->page_flip(adev, acrtc->crtc_id, afb->address, async_flip);
2381
2382 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
2383 DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
2384 acrtc->crtc_id);
2385}
2386
129eed72
HW		 2387void dc_commit_surfaces(struct drm_atomic_state *state,
2388 struct drm_device *dev, struct amdgpu_display_manager *dm)
2389{
2390 uint32_t i;
2391 struct drm_plane *plane;
2392 struct drm_plane_state *old_plane_state;
2393
2394 /* update planes when needed */
2395 for_each_plane_in_state(state, plane, old_plane_state, i) {
2396 struct drm_plane_state *plane_state = plane->state;
2397 struct drm_crtc *crtc = plane_state->crtc;
2398 struct drm_framebuffer *fb = plane_state->fb;
2399 struct drm_connector *connector;
2400 struct dm_connector_state *dm_state = NULL;
2401 enum dm_commit_action action;
2402 bool pflip_needed;
2403
2404 if (!fb || !crtc || !crtc->state->active)
2405 continue;
2406
2407 action = get_dm_commit_action(crtc->state);
2408
2409 /* Surfaces are created under two scenarios:
2410 * 1. This commit is not a page flip.
2411 * 2. This commit is a page flip, and streams are created.
2412 */
2413 pflip_needed = !state->allow_modeset;
2414 if (!pflip_needed || action == DM_COMMIT_ACTION_DPMS_ON
2415 || action == DM_COMMIT_ACTION_SET) {
2416 list_for_each_entry(connector,
2417 &dev->mode_config.connector_list,
2418 head) {
2419 if (connector->state->crtc == crtc) {
2420 dm_state = to_dm_connector_state(
2421 connector->state);
2422 break;
2423 }
2424 }
2425
2426 /*
2427 * This situation happens in the following case:
2428 * we are about to get set mode for connector who's only
2429 * possible crtc (in encoder crtc mask) is used by
2430 * another connector, that is why it will try to
2431 * re-assing crtcs in order to make configuration
2432 * supported. For our implementation we need to make all
2433 * encoders support all crtcs, then this issue will
2434 * never arise again. But to guard code from this issue
2435 * check is left.
2436 *
2437 * Also it should be needed when used with actual
2438 * drm_atomic_commit ioctl in future
2439 */
2440 if (!dm_state)
2441 continue;
2442
2443 dm_dc_surface_commit(dm->dc, crtc);
2444 }
2445 }
2446}
2447
54f5499a
AG		 2448void amdgpu_dm_atomic_commit_tail(
2449 struct drm_atomic_state *state)
4562236b 2450{
54f5499a 2451 struct drm_device *dev = state->dev;
4562236b
HW		 2452 struct amdgpu_device *adev = dev->dev_private;
2453 struct amdgpu_display_manager *dm = &adev->dm;
2454 struct drm_plane *plane;
4562236b 2455 struct drm_plane_state *old_plane_state;
ab2541b6 2456 uint32_t i;
ab2541b6 2457 uint32_t commit_streams_count = 0;
4562236b 2458 uint32_t new_crtcs_count = 0;
4562236b
HW		 2459 struct drm_crtc *crtc;
2460 struct drm_crtc_state *old_crtc_state;
ab2541b6
AC		 2461 const struct dc_stream *commit_streams[MAX_STREAMS];
2462 struct amdgpu_crtc *new_crtcs[MAX_STREAMS];
2463 const struct dc_stream *new_stream;
54f5499a
AG		 2464 unsigned long flags;
2465 bool wait_for_vblank = true;
4562236b 2466
4562236b
HW		 2467
2468 drm_atomic_helper_update_legacy_modeset_state(dev, state);
2469
2470 /* update changed items */
2471 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
2472 struct amdgpu_crtc *acrtc;
2473 struct amdgpu_connector *aconnector = NULL;
2474 enum dm_commit_action action;
2475 struct drm_crtc_state *new_state = crtc->state;
2476
2477 acrtc = to_amdgpu_crtc(crtc);
2478
2479 aconnector =
2480 amdgpu_dm_find_first_crct_matching_connector(
2481 state,
2482 crtc,
2483 false);
2484
2485 /* handles headless hotplug case, updating new_state and
2486 * aconnector as needed
2487 */
2488
2489 action = get_dm_commit_action(new_state);
2490
2491 switch (action) {
2492 case DM_COMMIT_ACTION_DPMS_ON:
2493 case DM_COMMIT_ACTION_SET: {
2494 struct dm_connector_state *dm_state = NULL;
ab2541b6 2495 new_stream = NULL;
4562236b
HW		 2496
2497 if (aconnector)
2498 dm_state = to_dm_connector_state(aconnector->base.state);
2499
ab2541b6 2500 new_stream = create_stream_for_sink(
4562236b
HW		 2501 aconnector,
2502 &crtc->state->mode,
2503 dm_state);
2504
2505 DRM_INFO("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
2506
ab2541b6 2507 if (!new_stream) {
4562236b
HW		 2508 /*
2509 * this could happen because of issues with
2510 * userspace notifications delivery.
2511 * In this case userspace tries to set mode on
2512 * display which is disconnect in fact.
2513 * dc_sink in NULL in this case on aconnector.
2514 * We expect reset mode will come soon.
2515 *
2516 * This can also happen when unplug is done
2517 * during resume sequence ended
2518 *
2519 * In this case, we want to pretend we still
2520 * have a sink to keep the pipe running so that
2521 * hw state is consistent with the sw state
2522 */
ab2541b6 2523 DRM_DEBUG_KMS("%s: Failed to create new stream for crtc %d\n",
4562236b
HW		 2524 __func__, acrtc->base.base.id);
2525 break;
2526 }
2527
ab2541b6
AC		 2528 if (acrtc->stream)
2529 remove_stream(adev, acrtc);
4562236b
HW		 2530
2531 /*
2532 * this loop saves set mode crtcs
2533 * we needed to enable vblanks once all
ab2541b6 2534 * resources acquired in dc after dc_commit_streams
4562236b
HW		 2535 */
2536 new_crtcs[new_crtcs_count] = acrtc;
2537 new_crtcs_count++;
2538
ab2541b6 2539 acrtc->stream = new_stream;
4562236b
HW		 2540 acrtc->enabled = true;
2541 acrtc->hw_mode = crtc->state->mode;
2542 crtc->hwmode = crtc->state->mode;
2543
2544 break;
2545 }
2546
2547 case DM_COMMIT_ACTION_NOTHING: {
2548 struct dm_connector_state *dm_state = NULL;
2549
2550 if (!aconnector)
2551 break;
2552
2553 dm_state = to_dm_connector_state(aconnector->base.state);
2554
2555 /* Scaling update */
ab2541b6
AC		 2556 update_stream_scaling_settings(&crtc->state->mode,
2557 dm_state, acrtc->stream);
4562236b
HW		 2558
2559 break;
2560 }
2561 case DM_COMMIT_ACTION_DPMS_OFF:
2562 case DM_COMMIT_ACTION_RESET:
2563 DRM_INFO("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
2564 /* i.e. reset mode */
ab2541b6
AC		 2565 if (acrtc->stream)
2566 remove_stream(adev, acrtc);
4562236b
HW		 2567 break;
2568 } /* switch() */
2569 } /* for_each_crtc_in_state() */
2570
2571 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2572
2573 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2574
ab2541b6
AC		 2575 if (acrtc->stream) {
2576 commit_streams[commit_streams_count] = acrtc->stream;
2577 ++commit_streams_count;
4562236b
HW		 2578 }
2579 }
2580
2581 /*
ab2541b6 2582 * Add streams after required streams from new and replaced streams
4562236b
HW		 2583 * are removed from freesync module
2584 */
2585 if (adev->dm.freesync_module) {
2586 for (i = 0; i < new_crtcs_count; i++) {
2587 struct amdgpu_connector *aconnector = NULL;
ab2541b6 2588 new_stream = new_crtcs[i]->stream;
4562236b
HW		 2589 aconnector =
2590 amdgpu_dm_find_first_crct_matching_connector(
2591 state,
2592 &new_crtcs[i]->base,
2593 false);
2594 if (!aconnector) {
2595 DRM_INFO(
2596 "Atomic commit: Failed to find connector for acrtc id:%d "
2597 "skipping freesync init\n",
2598 new_crtcs[i]->crtc_id);
2599 continue;
2600 }
2601
ab2541b6
AC		 2602 mod_freesync_add_stream(adev->dm.freesync_module,
2603 new_stream, &aconnector->caps);
4562236b
HW		 2604 }
2605 }
2606
ab2541b6 2607 /* DC is optimized not to do anything if 'streams' didn't change. */
53d35dc6 2608 WARN_ON(!dc_commit_streams(dm->dc, commit_streams, commit_streams_count));
4562236b
HW		 2609
2610 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2611 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2612
ab2541b6 2613 if (acrtc->stream != NULL)
4562236b 2614 acrtc->otg_inst =
ab2541b6 2615 dc_stream_get_status(acrtc->stream)->primary_otg_inst;
4562236b
HW		 2616 }
2617
2618 /* update planes when needed */
129eed72 2619 dc_commit_surfaces(state, dev, dm);
4562236b
HW		 2620
2621 for (i = 0; i < new_crtcs_count; i++) {
2622 /*
2623 * loop to enable interrupts on newly arrived crtc
2624 */
2625 struct amdgpu_crtc *acrtc = new_crtcs[i];
2626
ab2541b6
AC		 2627 if (adev->dm.freesync_module)
2628 mod_freesync_notify_mode_change(
2629 adev->dm.freesync_module, &acrtc->stream, 1);
4562236b
HW		 2630
2631 manage_dm_interrupts(adev, acrtc, true);
2632 dm_crtc_cursor_reset(&acrtc->base);
2633
2634 }
2635
4562236b
HW		 2636 for_each_plane_in_state(state, plane, old_plane_state, i) {
2637 struct drm_plane_state *plane_state = plane->state;
2638 struct drm_crtc *crtc = plane_state->crtc;
2639 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2640 struct drm_framebuffer *fb = plane_state->fb;
54f5499a 2641 bool pflip_needed;
4562236b
HW		 2642
2643 if (!fb || !crtc || !crtc->state->planes_changed ||
2644 !crtc->state->active)
2645 continue;
2d60ded1 2646 pflip_needed = !state->allow_modeset;
54f5499a
AG		 2647
2648 if (pflip_needed) {
00d7930c
MK		 2649 wait_for_vblank =
2650 acrtc->flip_flags & DRM_MODE_PAGE_FLIP_ASYNC ?
2651 false : true;
2652
54f5499a 2653 amdgpu_dm_do_flip(
00d7930c
MK		 2654 crtc,
2655 fb,
2656 drm_crtc_vblank_count(crtc) + wait_for_vblank);
54f5499a 2657
4562236b
HW		 2658 /*clean up the flags for next usage*/
2659 acrtc->flip_flags = 0;
2660 }
2661 }
2662
4562236b 2663
54f5499a
AG		 2664 /*TODO mark consumed event on all crtc assigned event
2665 * in drm_atomic_helper_setup_commit just to signal completion
2666 */
2667 spin_lock_irqsave(&adev->ddev->event_lock, flags);
2668 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
2669 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2670
2671 if (acrtc->base.state->event &&
2672 acrtc->base.state->event->event.base.type != DRM_EVENT_FLIP_COMPLETE) {
2673 acrtc->event = acrtc->base.state->event;
2674 acrtc->base.state->event = NULL;
2675 }
2676 }
2677 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
2678
2679 /* Signal HW programming completion */
2680 drm_atomic_helper_commit_hw_done(state);
2681
2682 if (wait_for_vblank)
2683 drm_atomic_helper_wait_for_vblanks(dev, state);
2684
2685 /*TODO send vblank event on all crtc assigned event
2686 * in drm_atomic_helper_setup_commit just to signal completion
2687 */
2688 spin_lock_irqsave(&adev->ddev->event_lock, flags);
2689 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
2690 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4562236b 2691
54f5499a
AG		 2692 if (acrtc->event &&
2693 acrtc->event->event.base.type != DRM_EVENT_FLIP_COMPLETE) {
2694 drm_send_event_locked(dev, &acrtc->event->base);
2695 acrtc->event = NULL;
2696 }
2697 }
2698 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
4562236b 2699
54f5499a
AG		 2700 /*TODO Is it to early if actual flip haven't happened yet ?*/
2701 /* Release old FB */
2702 drm_atomic_helper_cleanup_planes(dev, state);
4562236b 2703}
92cc37fb
AG		 2704
2705
2706static int dm_force_atomic_commit(struct drm_connector *connector)
2707{
2708 int ret = 0;
2709 struct drm_device *ddev = connector->dev;
2710 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
2711 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
2712 struct drm_plane *plane = disconnected_acrtc->base.primary;
2713 struct drm_connector_state *conn_state;
2714 struct drm_crtc_state *crtc_state;
2715 struct drm_plane_state *plane_state;
2716
2717 if (!state)
2718 return -ENOMEM;
2719
2720 state->acquire_ctx = ddev->mode_config.acquire_ctx;
2721
2722 /* Construct an atomic state to restore previous display setting */
2723
2724 /*
2725 * Attach connectors to drm_atomic_state
2726 */
2727 conn_state = drm_atomic_get_connector_state(state, connector);
2728
2729 ret = PTR_ERR_OR_ZERO(conn_state);
2730 if (ret)
2731 goto err;
2732
2733 /* Attach crtc to drm_atomic_state*/
2734 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
2735
2736 ret = PTR_ERR_OR_ZERO(crtc_state);
2737 if (ret)
2738 goto err;
2739
2740 /* force a restore */
2741 crtc_state->mode_changed = true;
2742
2743 /* Attach plane to drm_atomic_state */
2744 plane_state = drm_atomic_get_plane_state(state, plane);
2745
2746 ret = PTR_ERR_OR_ZERO(plane_state);
2747 if (ret)
2748 goto err;
2749
2750
2751 /* Call commit internally with the state we just constructed */
2752 ret = drm_atomic_commit(state);
2753 if (!ret)
2754 return 0;
2755
2756err:
2757 DRM_ERROR("Restoring old state failed with %i\n", ret);
2758 drm_atomic_state_put(state);
2759
2760 return ret;
2761}
2762
4562236b
HW		 2763/*
2764 * This functions handle all cases when set mode does not come upon hotplug.
2765 * This include when the same display is unplugged then plugged back into the
2766 * same port and when we are running without usermode desktop manager supprot
2767 */
2768void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector *connector)
2769{
4562236b
HW		 2770 struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
2771 struct amdgpu_crtc *disconnected_acrtc;
4562236b
HW		 2772
2773 if (!aconnector->dc_sink || !connector->state || !connector->encoder)
2774 return;
2775
2776 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
2777
ab2541b6 2778 if (!disconnected_acrtc || !disconnected_acrtc->stream)
4562236b
HW		 2779 return;
2780
4562236b
HW		 2781 /*
2782 * If the previous sink is not released and different from the current,
2783 * we deduce we are in a state where we can not rely on usermode call
2784 * to turn on the display, so we do it here
2785 */
92cc37fb
AG		 2786 if (disconnected_acrtc->stream->sink != aconnector->dc_sink)
2787 dm_force_atomic_commit(&aconnector->base);
4562236b
HW		 2788}
2789
2790static uint32_t add_val_sets_surface(
2791 struct dc_validation_set *val_sets,
2792 uint32_t set_count,
ab2541b6 2793 const struct dc_stream *stream,
4562236b
HW		 2794 const struct dc_surface *surface)
2795{
2796 uint32_t i = 0;
2797
2798 while (i < set_count) {
ab2541b6 2799 if (val_sets[i].stream == stream)
4562236b
HW		 2800 break;
2801 ++i;
2802 }
2803
2804 val_sets[i].surfaces[val_sets[i].surface_count] = surface;
2805 val_sets[i].surface_count++;
2806
2807 return val_sets[i].surface_count;
2808}
2809
ab2541b6 2810static uint32_t update_in_val_sets_stream(
4562236b
HW		 2811 struct dc_validation_set *val_sets,
2812 struct drm_crtc **crtcs,
2813 uint32_t set_count,
ab2541b6
AC		 2814 const struct dc_stream *old_stream,
2815 const struct dc_stream *new_stream,
4562236b
HW		 2816 struct drm_crtc *crtc)
2817{
2818 uint32_t i = 0;
2819
2820 while (i < set_count) {
ab2541b6 2821 if (val_sets[i].stream == old_stream)
4562236b
HW		 2822 break;
2823 ++i;
2824 }
2825
ab2541b6 2826 val_sets[i].stream = new_stream;
4562236b
HW		 2827 crtcs[i] = crtc;
2828
2829 if (i == set_count) {
2830 /* nothing found. add new one to the end */
2831 return set_count + 1;
2832 }
2833
2834 return set_count;
2835}
2836
2837static uint32_t remove_from_val_sets(
2838 struct dc_validation_set *val_sets,
2839 uint32_t set_count,
ab2541b6 2840 const struct dc_stream *stream)
4562236b
HW		 2841{
2842 int i;
2843
2844 for (i = 0; i < set_count; i++)
ab2541b6 2845 if (val_sets[i].stream == stream)
4562236b
HW		 2846 break;
2847
2848 if (i == set_count) {
2849 /* nothing found */
2850 return set_count;
2851 }
2852
2853 set_count--;
2854
2855 for (; i < set_count; i++) {
2856 val_sets[i] = val_sets[i + 1];
2857 }
2858
2859 return set_count;
2860}
2861
2862int amdgpu_dm_atomic_check(struct drm_device *dev,
2863 struct drm_atomic_state *state)
2864{
2865 struct drm_crtc *crtc;
2866 struct drm_crtc_state *crtc_state;
2867 struct drm_plane *plane;
2868 struct drm_plane_state *plane_state;
2869 int i, j;
2870 int ret;
2871 int set_count;
ab2541b6
AC		 2872 int new_stream_count;
2873 struct dc_validation_set set[MAX_STREAMS] = {{ 0 }};
2874 struct dc_stream *new_streams[MAX_STREAMS] = { 0 };
2875 struct drm_crtc *crtc_set[MAX_STREAMS] = { 0 };
4562236b
HW		 2876 struct amdgpu_device *adev = dev->dev_private;
2877 struct dc *dc = adev->dm.dc;
2878 bool need_to_validate = false;
07d72b39 2879 struct validate_context *context;
4562236b
HW		 2880
2881 ret = drm_atomic_helper_check(dev, state);
2882
2883 if (ret) {
2884 DRM_ERROR("Atomic state validation failed with error :%d !\n",
2885 ret);
2886 return ret;
2887 }
2888
2889 ret = -EINVAL;
2890
2891 /* copy existing configuration */
ab2541b6 2892 new_stream_count = 0;
4562236b
HW		 2893 set_count = 0;
2894 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2895
2896 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2897
ab2541b6
AC		 2898 if (acrtc->stream) {
2899 set[set_count].stream = acrtc->stream;
4562236b
HW		 2900 crtc_set[set_count] = crtc;
2901 ++set_count;
2902 }
2903 }
2904
2905 /* update changed items */
2906 for_each_crtc_in_state(state, crtc, crtc_state, i) {
2907 struct amdgpu_crtc *acrtc = NULL;
2908 struct amdgpu_connector *aconnector = NULL;
2909 enum dm_commit_action action;
2910
2911 acrtc = to_amdgpu_crtc(crtc);
2912
2913 aconnector = amdgpu_dm_find_first_crct_matching_connector(state, crtc, true);
2914
2915 action = get_dm_commit_action(crtc_state);
2916
2917 switch (action) {
2918 case DM_COMMIT_ACTION_DPMS_ON:
2919 case DM_COMMIT_ACTION_SET: {
ab2541b6 2920 struct dc_stream *new_stream = NULL;
4562236b
HW		 2921 struct drm_connector_state *conn_state = NULL;
2922 struct dm_connector_state *dm_state = NULL;
2923
2924 if (aconnector) {
2925 conn_state = drm_atomic_get_connector_state(state, &aconnector->base);
2926 if (IS_ERR(conn_state))
2927 return ret;
2928 dm_state = to_dm_connector_state(conn_state);
2929 }
2930
ab2541b6 2931 new_stream = create_stream_for_sink(aconnector, &crtc_state->mode, dm_state);
4562236b
HW		 2932
2933 /*
ab2541b6 2934 * we can have no stream on ACTION_SET if a display
4562236b
HW		 2935 * was disconnected during S3, in this case it not and
2936 * error, the OS will be updated after detection, and
2937 * do the right thing on next atomic commit
2938 */
ab2541b6
AC		 2939 if (!new_stream) {
2940 DRM_DEBUG_KMS("%s: Failed to create new stream for crtc %d\n",
4562236b
HW		 2941 __func__, acrtc->base.base.id);
2942 break;
2943 }
2944
ab2541b6
AC		 2945 new_streams[new_stream_count] = new_stream;
2946 set_count = update_in_val_sets_stream(
4562236b
HW		 2947 set,
2948 crtc_set,
2949 set_count,
ab2541b6
AC		 2950 acrtc->stream,
2951 new_stream,
4562236b
HW		 2952 crtc);
2953
ab2541b6 2954 new_stream_count++;
4562236b
HW		 2955 need_to_validate = true;
2956 break;
2957 }
2958
2959 case DM_COMMIT_ACTION_NOTHING: {
2960 const struct drm_connector *drm_connector = NULL;
2961 struct drm_connector_state *conn_state = NULL;
2962 struct dm_connector_state *dm_state = NULL;
2963 struct dm_connector_state *old_dm_state = NULL;
ab2541b6 2964 struct dc_stream *new_stream;
4562236b
HW		 2965
2966 if (!aconnector)
2967 break;
2968
2969 for_each_connector_in_state(
2970 state, drm_connector, conn_state, j) {
2971 if (&aconnector->base == drm_connector)
2972 break;
2973 }
2974
2975 old_dm_state = to_dm_connector_state(drm_connector->state);
2976 dm_state = to_dm_connector_state(conn_state);
2977
2978 /* Support underscan adjustment*/
2979 if (!is_scaling_state_different(dm_state, old_dm_state))
2980 break;
2981
ab2541b6 2982 new_stream = create_stream_for_sink(aconnector, &crtc_state->mode, dm_state);
4562236b 2983
ab2541b6
AC		 2984 if (!new_stream) {
2985 DRM_ERROR("%s: Failed to create new stream for crtc %d\n",
4562236b
HW		 2986 __func__, acrtc->base.base.id);
2987 break;
2988 }
2989
ab2541b6
AC		 2990 new_streams[new_stream_count] = new_stream;
2991 set_count = update_in_val_sets_stream(
4562236b
HW		 2992 set,
2993 crtc_set,
2994 set_count,
ab2541b6
AC		 2995 acrtc->stream,
2996 new_stream,
4562236b
HW		 2997 crtc);
2998
ab2541b6 2999 new_stream_count++;
4562236b
HW		 3000 need_to_validate = true;
3001
3002 break;
3003 }
3004 case DM_COMMIT_ACTION_DPMS_OFF:
3005 case DM_COMMIT_ACTION_RESET:
3006 /* i.e. reset mode */
ab2541b6 3007 if (acrtc->stream) {
4562236b
HW		 3008 set_count = remove_from_val_sets(
3009 set,
3010 set_count,
ab2541b6 3011 acrtc->stream);
4562236b
HW		 3012 }
3013 break;
3014 }
3015
3016 /*
3017 * TODO revisit when removing commit action
3018 * and looking at atomic flags directly
3019 */
3020
3021 /* commit needs planes right now (for gamma, eg.) */
3022 /* TODO rework commit to chack crtc for gamma change */
3023 ret = drm_atomic_add_affected_planes(state, crtc);
3024 if (ret)
3025 return ret;
53d35dc6
AG		 3026
3027 ret = -EINVAL;
4562236b
HW		 3028 }
3029
3030 for (i = 0; i < set_count; i++) {
3031 for_each_plane_in_state(state, plane, plane_state, j) {
4562236b
HW		 3032 struct drm_crtc *crtc = plane_state->crtc;
3033 struct drm_framebuffer *fb = plane_state->fb;
3034 struct drm_connector *connector;
3035 struct dm_connector_state *dm_state = NULL;
3036 enum dm_commit_action action;
3037 struct drm_crtc_state *crtc_state;
54f5499a 3038 bool pflip_needed;
4562236b
HW		 3039
3040
3041 if (!fb || !crtc || crtc_set[i] != crtc ||
3042 !crtc->state->planes_changed || !crtc->state->active)
3043 continue;
3044
3045 action = get_dm_commit_action(crtc->state);
3046
3047 /* Surfaces are created under two scenarios:
3048 * 1. This commit is not a page flip.
ab2541b6 3049 * 2. This commit is a page flip, and streams are created.
4562236b
HW		 3050 */
3051 crtc_state = drm_atomic_get_crtc_state(state, crtc);
2d60ded1 3052 pflip_needed = !state->allow_modeset;
54f5499a
AG		 3053 if (!pflip_needed ||
3054 action == DM_COMMIT_ACTION_DPMS_ON ||
3055 action == DM_COMMIT_ACTION_SET) {
4562236b
HW		 3056 struct dc_surface *surface;
3057
3058 list_for_each_entry(connector,
3059 &dev->mode_config.connector_list, head) {
3060 if (connector->state->crtc == crtc) {
3061 dm_state = to_dm_connector_state(
3062 connector->state);
3063 break;
3064 }
3065 }
3066
3067 /*
3068 * This situation happens in the following case:
3069 * we are about to get set mode for connector who's only
3070 * possible crtc (in encoder crtc mask) is used by
3071 * another connector, that is why it will try to
3072 * re-assing crtcs in order to make configuration
3073 * supported. For our implementation we need to make all
3074 * encoders support all crtcs, then this issue will
3075 * never arise again. But to guard code from this issue
3076 * check is left.
3077 *
3078 * Also it should be needed when used with actual
3079 * drm_atomic_commit ioctl in future
3080 */
3081 if (!dm_state)
3082 continue;
3083
3084 surface = dc_create_surface(dc);
3085 fill_plane_attributes(
6a1f8cab 3086 crtc->dev->dev_private,
4562236b
HW		 3087 surface,
3088 plane_state,
3089 false);
3090
3091 add_val_sets_surface(
3092 set,
3093 set_count,
ab2541b6 3094 set[i].stream,
4562236b
HW		 3095 surface);
3096
3097 need_to_validate = true;
3098 }
3099 }
3100 }
3101
07d72b39
HW		 3102 context = dc_get_validate_context(dc, set, set_count);
3103
3104 if (need_to_validate == false || set_count == 0 || context)
4562236b
HW		 3105 ret = 0;
3106
07d72b39
HW		 3107 if (context) {
3108 dc_resource_validate_ctx_destruct(context);
3109 dm_free(context);
4562236b 3110 }
07d72b39
HW		 3111
3112 for (i = 0; i < set_count; i++)
3113 for (j = 0; j < set[i].surface_count; j++)
3114 dc_surface_release(set[i].surfaces[j]);
3115
ab2541b6
AC		 3116 for (i = 0; i < new_stream_count; i++)
3117 dc_stream_release(new_streams[i]);
4562236b
HW		 3118
3119 if (ret != 0)
3120 DRM_ERROR("Atomic check failed.\n");
3121
3122 return ret;
3123}
3124
3125static bool is_dp_capable_without_timing_msa(
3126 struct dc *dc,
3127 struct amdgpu_connector *amdgpu_connector)
3128{
3129 uint8_t dpcd_data;
3130 bool capable = false;
209a885b 3131
4562236b 3132 if (amdgpu_connector->dc_link &&
209a885b
JL		 3133 dm_helpers_dp_read_dpcd(
3134 NULL,
3135 amdgpu_connector->dc_link,
3136 DP_DOWN_STREAM_PORT_COUNT,
3137 &dpcd_data,
3138 sizeof(dpcd_data))) {
d7194cf6 3139 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
209a885b 3140 }
4562236b
HW		 3141
3142 return capable;
3143}
3144void amdgpu_dm_add_sink_to_freesync_module(
3145 struct drm_connector *connector,
3146 struct edid *edid)
3147{
3148 int i;
3149 uint64_t val_capable;
3150 bool edid_check_required;
3151 struct detailed_timing *timing;
3152 struct detailed_non_pixel *data;
3153 struct detailed_data_monitor_range *range;
3154 struct amdgpu_connector *amdgpu_connector =
3155 to_amdgpu_connector(connector);
3156
3157 struct drm_device *dev = connector->dev;
3158 struct amdgpu_device *adev = dev->dev_private;
3159 edid_check_required = false;
3160 if (!amdgpu_connector->dc_sink) {
3161 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
3162 return;
3163 }
3164 if (!adev->dm.freesync_module)
3165 return;
3166 /*
3167 * if edid non zero restrict freesync only for dp and edp
3168 */
3169 if (edid) {
3170 if (amdgpu_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
3171 || amdgpu_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
3172 edid_check_required = is_dp_capable_without_timing_msa(
3173 adev->dm.dc,
3174 amdgpu_connector);
3175 }
3176 }
3177 val_capable = 0;
3178 if (edid_check_required == true && (edid->version > 1 ||
3179 (edid->version == 1 && edid->revision > 1))) {
3180 for (i = 0; i < 4; i++) {
3181
3182 timing = &edid->detailed_timings[i];
3183 data = &timing->data.other_data;
3184 range = &data->data.range;
3185 /*
3186 * Check if monitor has continuous frequency mode
3187 */
3188 if (data->type != EDID_DETAIL_MONITOR_RANGE)
3189 continue;
3190 /*
3191 * Check for flag range limits only. If flag == 1 then
3192 * no additional timing information provided.
3193 * Default GTF, GTF Secondary curve and CVT are not
3194 * supported
3195 */
3196 if (range->flags != 1)
3197 continue;
3198
3199 amdgpu_connector->min_vfreq = range->min_vfreq;
3200 amdgpu_connector->max_vfreq = range->max_vfreq;
3201 amdgpu_connector->pixel_clock_mhz =
3202 range->pixel_clock_mhz * 10;
3203 break;
3204 }
3205
3206 if (amdgpu_connector->max_vfreq -
3207 amdgpu_connector->min_vfreq > 10) {
3208 amdgpu_connector->caps.supported = true;
3209 amdgpu_connector->caps.min_refresh_in_micro_hz =
3210 amdgpu_connector->min_vfreq * 1000000;
3211 amdgpu_connector->caps.max_refresh_in_micro_hz =
3212 amdgpu_connector->max_vfreq * 1000000;
3213 val_capable = 1;
3214 }
3215 }
3216
3217 /*
3218 * TODO figure out how to notify user-mode or DRM of freesync caps
3219 * once we figure out how to deal with freesync in an upstreamable
3220 * fashion
3221 */
3222
3223}
3224
3225void amdgpu_dm_remove_sink_from_freesync_module(
3226 struct drm_connector *connector)
3227{
3228 /*
3229 * TODO fill in once we figure out how to deal with freesync in
3230 * an upstreamable fashion
3231 */
3232}
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