]>
Commit | Line | Data |
---|---|---|
4562236b HW |
1 | /* |
2 | * Copyright 2015 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: AMD | |
23 | */ | |
24 | ||
25 | #include "dm_services.h" | |
26 | ||
27 | #include "dc.h" | |
28 | ||
29 | #include "core_status.h" | |
30 | #include "core_types.h" | |
31 | #include "hw_sequencer.h" | |
32 | ||
33 | #include "resource.h" | |
34 | ||
35 | #include "clock_source.h" | |
36 | #include "dc_bios_types.h" | |
37 | ||
5e141de4 | 38 | #include "dce_calcs.h" |
4562236b HW |
39 | #include "bios_parser_interface.h" |
40 | #include "include/irq_service_interface.h" | |
41 | #include "transform.h" | |
42 | #include "timing_generator.h" | |
43 | #include "virtual/virtual_link_encoder.h" | |
44 | ||
45 | #include "link_hwss.h" | |
46 | #include "link_encoder.h" | |
47 | ||
48 | #include "dc_link_ddc.h" | |
49 | #include "dm_helpers.h" | |
50 | #include "mem_input.h" | |
51 | ||
4562236b HW |
52 | /******************************************************************************* |
53 | * Private functions | |
54 | ******************************************************************************/ | |
55 | static void destroy_links(struct core_dc *dc) | |
56 | { | |
57 | uint32_t i; | |
58 | ||
59 | for (i = 0; i < dc->link_count; i++) { | |
60 | if (NULL != dc->links[i]) | |
61 | link_destroy(&dc->links[i]); | |
62 | } | |
63 | } | |
64 | ||
65 | static bool create_links( | |
66 | struct core_dc *dc, | |
67 | uint32_t num_virtual_links) | |
68 | { | |
69 | int i; | |
70 | int connectors_num; | |
71 | struct dc_bios *bios = dc->ctx->dc_bios; | |
72 | ||
73 | dc->link_count = 0; | |
74 | ||
75 | connectors_num = bios->funcs->get_connectors_number(bios); | |
76 | ||
77 | if (connectors_num > ENUM_ID_COUNT) { | |
78 | dm_error( | |
79 | "DC: Number of connectors %d exceeds maximum of %d!\n", | |
80 | connectors_num, | |
81 | ENUM_ID_COUNT); | |
82 | return false; | |
83 | } | |
84 | ||
85 | if (connectors_num == 0 && num_virtual_links == 0) { | |
86 | dm_error("DC: Number of connectors is zero!\n"); | |
87 | } | |
88 | ||
89 | dm_output_to_console( | |
90 | "DC: %s: connectors_num: physical:%d, virtual:%d\n", | |
91 | __func__, | |
92 | connectors_num, | |
93 | num_virtual_links); | |
94 | ||
95 | for (i = 0; i < connectors_num; i++) { | |
96 | struct link_init_data link_init_params = {0}; | |
97 | struct core_link *link; | |
98 | ||
99 | link_init_params.ctx = dc->ctx; | |
100 | link_init_params.connector_index = i; | |
101 | link_init_params.link_index = dc->link_count; | |
102 | link_init_params.dc = dc; | |
103 | link = link_create(&link_init_params); | |
104 | ||
105 | if (link) { | |
106 | dc->links[dc->link_count] = link; | |
107 | link->dc = dc; | |
108 | ++dc->link_count; | |
109 | } else { | |
110 | dm_error("DC: failed to create link!\n"); | |
111 | } | |
112 | } | |
113 | ||
114 | for (i = 0; i < num_virtual_links; i++) { | |
115 | struct core_link *link = dm_alloc(sizeof(*link)); | |
116 | struct encoder_init_data enc_init = {0}; | |
117 | ||
118 | if (link == NULL) { | |
119 | BREAK_TO_DEBUGGER(); | |
120 | goto failed_alloc; | |
121 | } | |
122 | ||
123 | link->ctx = dc->ctx; | |
124 | link->dc = dc; | |
125 | link->public.connector_signal = SIGNAL_TYPE_VIRTUAL; | |
126 | link->link_id.type = OBJECT_TYPE_CONNECTOR; | |
127 | link->link_id.id = CONNECTOR_ID_VIRTUAL; | |
128 | link->link_id.enum_id = ENUM_ID_1; | |
129 | link->link_enc = dm_alloc(sizeof(*link->link_enc)); | |
130 | ||
131 | enc_init.ctx = dc->ctx; | |
132 | enc_init.channel = CHANNEL_ID_UNKNOWN; | |
133 | enc_init.hpd_source = HPD_SOURCEID_UNKNOWN; | |
134 | enc_init.transmitter = TRANSMITTER_UNKNOWN; | |
135 | enc_init.connector = link->link_id; | |
136 | enc_init.encoder.type = OBJECT_TYPE_ENCODER; | |
137 | enc_init.encoder.id = ENCODER_ID_INTERNAL_VIRTUAL; | |
138 | enc_init.encoder.enum_id = ENUM_ID_1; | |
139 | virtual_link_encoder_construct(link->link_enc, &enc_init); | |
140 | ||
141 | link->public.link_index = dc->link_count; | |
142 | dc->links[dc->link_count] = link; | |
143 | dc->link_count++; | |
144 | } | |
145 | ||
146 | return true; | |
147 | ||
148 | failed_alloc: | |
149 | return false; | |
150 | } | |
151 | ||
152 | static bool stream_adjust_vmin_vmax(struct dc *dc, | |
153 | const struct dc_stream **stream, int num_streams, | |
154 | int vmin, int vmax) | |
155 | { | |
156 | /* TODO: Support multiple streams */ | |
157 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
158 | struct core_stream *core_stream = DC_STREAM_TO_CORE(stream[0]); | |
159 | int i = 0; | |
160 | bool ret = false; | |
4562236b HW |
161 | |
162 | for (i = 0; i < MAX_PIPES; i++) { | |
6680b6a1 | 163 | struct pipe_ctx *pipe = &core_dc->current_context->res_ctx.pipe_ctx[i]; |
4562236b | 164 | |
6680b6a1 YS |
165 | if (pipe->stream == core_stream && pipe->stream_enc) { |
166 | core_dc->hwss.set_drr(&pipe, 1, vmin, vmax); | |
4562236b HW |
167 | |
168 | /* build and update the info frame */ | |
6680b6a1 YS |
169 | resource_build_info_frame(pipe); |
170 | core_dc->hwss.update_info_frame(pipe); | |
4562236b HW |
171 | |
172 | ret = true; | |
173 | } | |
174 | } | |
4562236b HW |
175 | return ret; |
176 | } | |
177 | ||
72ada5f7 EC |
178 | static bool stream_get_crtc_position(struct dc *dc, |
179 | const struct dc_stream **stream, int num_streams, | |
180 | unsigned int *v_pos, unsigned int *nom_v_pos) | |
181 | { | |
182 | /* TODO: Support multiple streams */ | |
183 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
184 | struct core_stream *core_stream = DC_STREAM_TO_CORE(stream[0]); | |
185 | int i = 0; | |
186 | bool ret = false; | |
187 | struct crtc_position position; | |
188 | ||
189 | for (i = 0; i < MAX_PIPES; i++) { | |
190 | struct pipe_ctx *pipe = | |
191 | &core_dc->current_context->res_ctx.pipe_ctx[i]; | |
192 | ||
193 | if (pipe->stream == core_stream && pipe->stream_enc) { | |
194 | core_dc->hwss.get_position(&pipe, 1, &position); | |
195 | ||
196 | *v_pos = position.vertical_count; | |
197 | *nom_v_pos = position.nominal_vcount; | |
198 | ret = true; | |
199 | } | |
200 | } | |
201 | return ret; | |
202 | } | |
4562236b | 203 | |
f46661dd | 204 | static bool set_gamut_remap(struct dc *dc, const struct dc_stream *stream) |
4562236b HW |
205 | { |
206 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
f46661dd | 207 | struct core_stream *core_stream = DC_STREAM_TO_CORE(stream); |
4562236b HW |
208 | int i = 0; |
209 | bool ret = false; | |
210 | struct pipe_ctx *pipes; | |
211 | ||
212 | for (i = 0; i < MAX_PIPES; i++) { | |
213 | if (core_dc->current_context->res_ctx.pipe_ctx[i].stream | |
214 | == core_stream) { | |
215 | ||
216 | pipes = &core_dc->current_context->res_ctx.pipe_ctx[i]; | |
217 | core_dc->hwss.set_plane_config(core_dc, pipes, | |
218 | &core_dc->current_context->res_ctx); | |
219 | ret = true; | |
220 | } | |
221 | } | |
222 | ||
223 | return ret; | |
224 | } | |
225 | ||
94267b3d ST |
226 | static void set_static_screen_events(struct dc *dc, |
227 | const struct dc_stream **stream, | |
228 | int num_streams, | |
229 | const struct dc_static_screen_events *events) | |
230 | { | |
231 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
232 | int i = 0; | |
233 | int j = 0; | |
234 | struct pipe_ctx *pipes_affected[MAX_PIPES]; | |
235 | int num_pipes_affected = 0; | |
236 | ||
237 | for (i = 0; i < num_streams; i++) { | |
238 | struct core_stream *core_stream = DC_STREAM_TO_CORE(stream[i]); | |
239 | ||
240 | for (j = 0; j < MAX_PIPES; j++) { | |
241 | if (core_dc->current_context->res_ctx.pipe_ctx[j].stream | |
242 | == core_stream) { | |
243 | pipes_affected[num_pipes_affected++] = | |
244 | &core_dc->current_context->res_ctx.pipe_ctx[j]; | |
245 | } | |
246 | } | |
247 | } | |
248 | ||
249 | core_dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, events); | |
250 | } | |
251 | ||
4562236b HW |
252 | /* This function is not expected to fail, proper implementation of |
253 | * validation will prevent this from ever being called for unsupported | |
254 | * configurations. | |
255 | */ | |
256 | static void stream_update_scaling( | |
257 | const struct dc *dc, | |
258 | const struct dc_stream *dc_stream, | |
259 | const struct rect *src, | |
260 | const struct rect *dst) | |
261 | { | |
262 | struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); | |
263 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
264 | struct validate_context *cur_ctx = core_dc->current_context; | |
ab2541b6 | 265 | int i; |
4562236b HW |
266 | |
267 | if (src) | |
268 | stream->public.src = *src; | |
269 | ||
270 | if (dst) | |
271 | stream->public.dst = *dst; | |
272 | ||
ab2541b6 AC |
273 | for (i = 0; i < cur_ctx->stream_count; i++) { |
274 | struct core_stream *cur_stream = cur_ctx->streams[i]; | |
4562236b | 275 | |
ab2541b6 AC |
276 | if (stream == cur_stream) { |
277 | struct dc_stream_status *status = &cur_ctx->stream_status[i]; | |
4562236b HW |
278 | |
279 | if (status->surface_count) | |
ab2541b6 | 280 | if (!dc_commit_surfaces_to_stream( |
4562236b HW |
281 | &core_dc->public, |
282 | status->surfaces, | |
283 | status->surface_count, | |
ab2541b6 | 284 | &cur_stream->public)) |
4562236b HW |
285 | /* Need to debug validation */ |
286 | BREAK_TO_DEBUGGER(); | |
287 | ||
288 | return; | |
289 | } | |
290 | } | |
291 | } | |
292 | ||
4562236b | 293 | static void set_drive_settings(struct dc *dc, |
bf5cda33 HW |
294 | struct link_training_settings *lt_settings, |
295 | const struct dc_link *link) | |
4562236b HW |
296 | { |
297 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
298 | int i; | |
299 | ||
bf5cda33 HW |
300 | for (i = 0; i < core_dc->link_count; i++) { |
301 | if (&core_dc->links[i]->public == link) | |
302 | break; | |
303 | } | |
304 | ||
305 | if (i >= core_dc->link_count) | |
306 | ASSERT_CRITICAL(false); | |
307 | ||
308 | dc_link_dp_set_drive_settings(&core_dc->links[i]->public, lt_settings); | |
4562236b HW |
309 | } |
310 | ||
311 | static void perform_link_training(struct dc *dc, | |
312 | struct dc_link_settings *link_setting, | |
313 | bool skip_video_pattern) | |
314 | { | |
315 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
316 | int i; | |
317 | ||
318 | for (i = 0; i < core_dc->link_count; i++) | |
319 | dc_link_dp_perform_link_training( | |
320 | &core_dc->links[i]->public, | |
321 | link_setting, | |
322 | skip_video_pattern); | |
323 | } | |
324 | ||
325 | static void set_preferred_link_settings(struct dc *dc, | |
88639168 ZF |
326 | struct dc_link_settings *link_setting, |
327 | const struct dc_link *link) | |
4562236b | 328 | { |
88639168 | 329 | struct core_link *core_link = DC_LINK_TO_CORE(link); |
4562236b | 330 | |
88639168 | 331 | core_link->public.verified_link_cap.lane_count = |
4562236b | 332 | link_setting->lane_count; |
88639168 | 333 | core_link->public.verified_link_cap.link_rate = |
4562236b | 334 | link_setting->link_rate; |
73c72602 | 335 | dp_retrain_link_dp_test(core_link, link_setting, false); |
4562236b HW |
336 | } |
337 | ||
338 | static void enable_hpd(const struct dc_link *link) | |
339 | { | |
340 | dc_link_dp_enable_hpd(link); | |
341 | } | |
342 | ||
343 | static void disable_hpd(const struct dc_link *link) | |
344 | { | |
345 | dc_link_dp_disable_hpd(link); | |
346 | } | |
347 | ||
348 | ||
349 | static void set_test_pattern( | |
350 | const struct dc_link *link, | |
351 | enum dp_test_pattern test_pattern, | |
352 | const struct link_training_settings *p_link_settings, | |
353 | const unsigned char *p_custom_pattern, | |
354 | unsigned int cust_pattern_size) | |
355 | { | |
356 | if (link != NULL) | |
357 | dc_link_dp_set_test_pattern( | |
358 | link, | |
359 | test_pattern, | |
360 | p_link_settings, | |
361 | p_custom_pattern, | |
362 | cust_pattern_size); | |
363 | } | |
364 | ||
529cad0f DW |
365 | void set_dither_option(const struct dc_stream *dc_stream, |
366 | enum dc_dither_option option) | |
367 | { | |
368 | struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); | |
369 | struct bit_depth_reduction_params params; | |
370 | struct core_link *core_link = DC_LINK_TO_CORE(stream->status.link); | |
371 | struct pipe_ctx *pipes = | |
372 | core_link->dc->current_context->res_ctx.pipe_ctx; | |
373 | ||
374 | memset(¶ms, 0, sizeof(params)); | |
375 | if (!stream) | |
376 | return; | |
377 | if (option > DITHER_OPTION_MAX) | |
378 | return; | |
379 | if (option == DITHER_OPTION_DEFAULT) { | |
380 | switch (stream->public.timing.display_color_depth) { | |
381 | case COLOR_DEPTH_666: | |
382 | stream->public.dither_option = DITHER_OPTION_SPATIAL6; | |
383 | break; | |
384 | case COLOR_DEPTH_888: | |
385 | stream->public.dither_option = DITHER_OPTION_SPATIAL8; | |
386 | break; | |
387 | case COLOR_DEPTH_101010: | |
388 | stream->public.dither_option = DITHER_OPTION_SPATIAL10; | |
389 | break; | |
390 | default: | |
391 | option = DITHER_OPTION_DISABLE; | |
392 | } | |
393 | } else { | |
394 | stream->public.dither_option = option; | |
395 | } | |
396 | resource_build_bit_depth_reduction_params(stream, | |
397 | ¶ms); | |
398 | stream->bit_depth_params = params; | |
399 | pipes->opp->funcs-> | |
400 | opp_program_bit_depth_reduction(pipes->opp, ¶ms); | |
401 | } | |
402 | ||
4562236b HW |
403 | static void allocate_dc_stream_funcs(struct core_dc *core_dc) |
404 | { | |
405 | core_dc->public.stream_funcs.stream_update_scaling = stream_update_scaling; | |
406 | if (core_dc->hwss.set_drr != NULL) { | |
407 | core_dc->public.stream_funcs.adjust_vmin_vmax = | |
408 | stream_adjust_vmin_vmax; | |
409 | } | |
410 | ||
94267b3d ST |
411 | core_dc->public.stream_funcs.set_static_screen_events = |
412 | set_static_screen_events; | |
413 | ||
72ada5f7 EC |
414 | core_dc->public.stream_funcs.get_crtc_position = |
415 | stream_get_crtc_position; | |
416 | ||
4562236b HW |
417 | core_dc->public.stream_funcs.set_gamut_remap = |
418 | set_gamut_remap; | |
419 | ||
529cad0f DW |
420 | core_dc->public.stream_funcs.set_dither_option = |
421 | set_dither_option; | |
422 | ||
4562236b HW |
423 | core_dc->public.link_funcs.set_drive_settings = |
424 | set_drive_settings; | |
425 | ||
426 | core_dc->public.link_funcs.perform_link_training = | |
427 | perform_link_training; | |
428 | ||
429 | core_dc->public.link_funcs.set_preferred_link_settings = | |
430 | set_preferred_link_settings; | |
431 | ||
432 | core_dc->public.link_funcs.enable_hpd = | |
433 | enable_hpd; | |
434 | ||
435 | core_dc->public.link_funcs.disable_hpd = | |
436 | disable_hpd; | |
437 | ||
438 | core_dc->public.link_funcs.set_test_pattern = | |
439 | set_test_pattern; | |
440 | } | |
441 | ||
442 | static void destruct(struct core_dc *dc) | |
443 | { | |
8122a253 | 444 | dc_resource_validate_ctx_destruct(dc->current_context); |
4562236b | 445 | |
4562236b HW |
446 | destroy_links(dc); |
447 | ||
448 | dc_destroy_resource_pool(dc); | |
449 | ||
450 | if (dc->ctx->gpio_service) | |
451 | dal_gpio_service_destroy(&dc->ctx->gpio_service); | |
452 | ||
453 | if (dc->ctx->i2caux) | |
454 | dal_i2caux_destroy(&dc->ctx->i2caux); | |
455 | ||
456 | if (dc->ctx->created_bios) | |
457 | dal_bios_parser_destroy(&dc->ctx->dc_bios); | |
458 | ||
459 | if (dc->ctx->logger) | |
460 | dal_logger_destroy(&dc->ctx->logger); | |
461 | ||
462 | dm_free(dc->current_context); | |
463 | dc->current_context = NULL; | |
464 | ||
465 | dm_free(dc->ctx); | |
466 | dc->ctx = NULL; | |
467 | } | |
468 | ||
469 | static bool construct(struct core_dc *dc, | |
470 | const struct dc_init_data *init_params) | |
471 | { | |
472 | struct dal_logger *logger; | |
473 | struct dc_context *dc_ctx = dm_alloc(sizeof(*dc_ctx)); | |
474 | enum dce_version dc_version = DCE_VERSION_UNKNOWN; | |
475 | ||
476 | if (!dc_ctx) { | |
477 | dm_error("%s: failed to create ctx\n", __func__); | |
478 | goto ctx_fail; | |
479 | } | |
480 | ||
481 | dc->current_context = dm_alloc(sizeof(*dc->current_context)); | |
4562236b | 482 | |
6d9501e4 | 483 | if (!dc->current_context) { |
4562236b HW |
484 | dm_error("%s: failed to create validate ctx\n", __func__); |
485 | goto val_ctx_fail; | |
486 | } | |
487 | ||
488 | dc_ctx->cgs_device = init_params->cgs_device; | |
489 | dc_ctx->driver_context = init_params->driver; | |
490 | dc_ctx->dc = &dc->public; | |
491 | dc_ctx->asic_id = init_params->asic_id; | |
492 | ||
493 | /* Create logger */ | |
494 | logger = dal_logger_create(dc_ctx); | |
495 | ||
496 | if (!logger) { | |
497 | /* can *not* call logger. call base driver 'print error' */ | |
498 | dm_error("%s: failed to create Logger!\n", __func__); | |
499 | goto logger_fail; | |
500 | } | |
501 | dc_ctx->logger = logger; | |
502 | dc->ctx = dc_ctx; | |
503 | dc->ctx->dce_environment = init_params->dce_environment; | |
504 | ||
505 | dc_version = resource_parse_asic_id(init_params->asic_id); | |
506 | dc->ctx->dce_version = dc_version; | |
507 | ||
508 | /* Resource should construct all asic specific resources. | |
509 | * This should be the only place where we need to parse the asic id | |
510 | */ | |
511 | if (init_params->vbios_override) | |
512 | dc_ctx->dc_bios = init_params->vbios_override; | |
513 | else { | |
514 | /* Create BIOS parser */ | |
515 | struct bp_init_data bp_init_data; | |
e8c963d6 | 516 | |
4562236b HW |
517 | bp_init_data.ctx = dc_ctx; |
518 | bp_init_data.bios = init_params->asic_id.atombios_base_address; | |
519 | ||
520 | dc_ctx->dc_bios = dal_bios_parser_create( | |
521 | &bp_init_data, dc_version); | |
522 | ||
523 | if (!dc_ctx->dc_bios) { | |
524 | ASSERT_CRITICAL(false); | |
525 | goto bios_fail; | |
526 | } | |
527 | ||
528 | dc_ctx->created_bios = true; | |
e8c963d6 | 529 | } |
4562236b HW |
530 | |
531 | /* Create I2C AUX */ | |
532 | dc_ctx->i2caux = dal_i2caux_create(dc_ctx); | |
533 | ||
534 | if (!dc_ctx->i2caux) { | |
535 | ASSERT_CRITICAL(false); | |
536 | goto failed_to_create_i2caux; | |
537 | } | |
538 | ||
539 | /* Create GPIO service */ | |
540 | dc_ctx->gpio_service = dal_gpio_service_create( | |
541 | dc_version, | |
542 | dc_ctx->dce_environment, | |
543 | dc_ctx); | |
544 | ||
545 | if (!dc_ctx->gpio_service) { | |
546 | ASSERT_CRITICAL(false); | |
547 | goto gpio_fail; | |
548 | } | |
549 | ||
550 | dc->res_pool = dc_create_resource_pool( | |
551 | dc, | |
552 | init_params->num_virtual_links, | |
553 | dc_version, | |
554 | init_params->asic_id); | |
555 | if (!dc->res_pool) | |
556 | goto create_resource_fail; | |
557 | ||
558 | if (!create_links(dc, init_params->num_virtual_links)) | |
559 | goto create_links_fail; | |
560 | ||
561 | allocate_dc_stream_funcs(dc); | |
562 | ||
563 | return true; | |
564 | ||
565 | /**** error handling here ****/ | |
566 | create_links_fail: | |
567 | create_resource_fail: | |
568 | gpio_fail: | |
569 | failed_to_create_i2caux: | |
570 | bios_fail: | |
571 | logger_fail: | |
572 | val_ctx_fail: | |
573 | ctx_fail: | |
574 | destruct(dc); | |
575 | return false; | |
576 | } | |
577 | ||
578 | /* | |
579 | void ProgramPixelDurationV(unsigned int pixelClockInKHz ) | |
580 | { | |
581 | fixed31_32 pixel_duration = Fixed31_32(100000000, pixelClockInKHz) * 10; | |
582 | unsigned int pixDurationInPico = round(pixel_duration); | |
583 | ||
584 | DPG_PIPE_ARBITRATION_CONTROL1 arb_control; | |
585 | ||
586 | arb_control.u32All = ReadReg (mmDPGV0_PIPE_ARBITRATION_CONTROL1); | |
587 | arb_control.bits.PIXEL_DURATION = pixDurationInPico; | |
588 | WriteReg (mmDPGV0_PIPE_ARBITRATION_CONTROL1, arb_control.u32All); | |
589 | ||
590 | arb_control.u32All = ReadReg (mmDPGV1_PIPE_ARBITRATION_CONTROL1); | |
591 | arb_control.bits.PIXEL_DURATION = pixDurationInPico; | |
592 | WriteReg (mmDPGV1_PIPE_ARBITRATION_CONTROL1, arb_control.u32All); | |
593 | ||
594 | WriteReg (mmDPGV0_PIPE_ARBITRATION_CONTROL2, 0x4000800); | |
595 | WriteReg (mmDPGV0_REPEATER_PROGRAM, 0x11); | |
596 | ||
597 | WriteReg (mmDPGV1_PIPE_ARBITRATION_CONTROL2, 0x4000800); | |
598 | WriteReg (mmDPGV1_REPEATER_PROGRAM, 0x11); | |
599 | } | |
600 | */ | |
601 | ||
602 | /******************************************************************************* | |
603 | * Public functions | |
604 | ******************************************************************************/ | |
605 | ||
606 | struct dc *dc_create(const struct dc_init_data *init_params) | |
607 | { | |
608 | struct core_dc *core_dc = dm_alloc(sizeof(*core_dc)); | |
609 | unsigned int full_pipe_count; | |
610 | ||
611 | if (NULL == core_dc) | |
612 | goto alloc_fail; | |
613 | ||
614 | if (false == construct(core_dc, init_params)) | |
615 | goto construct_fail; | |
616 | ||
617 | /*TODO: separate HW and SW initialization*/ | |
618 | core_dc->hwss.init_hw(core_dc); | |
619 | ||
620 | full_pipe_count = core_dc->res_pool->pipe_count; | |
f0e3db90 | 621 | if (core_dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE) |
4562236b | 622 | full_pipe_count--; |
ab2541b6 | 623 | core_dc->public.caps.max_streams = min( |
4562236b HW |
624 | full_pipe_count, |
625 | core_dc->res_pool->stream_enc_count); | |
626 | ||
627 | core_dc->public.caps.max_links = core_dc->link_count; | |
628 | core_dc->public.caps.max_audios = core_dc->res_pool->audio_count; | |
629 | ||
630 | core_dc->public.config = init_params->flags; | |
631 | ||
632 | dm_logger_write(core_dc->ctx->logger, LOG_DC, | |
633 | "Display Core initialized\n"); | |
634 | ||
635 | ||
636 | /* TODO: missing feature to be enabled */ | |
637 | core_dc->public.debug.disable_dfs_bypass = true; | |
638 | ||
639 | return &core_dc->public; | |
640 | ||
641 | construct_fail: | |
642 | dm_free(core_dc); | |
643 | ||
644 | alloc_fail: | |
645 | return NULL; | |
646 | } | |
647 | ||
648 | void dc_destroy(struct dc **dc) | |
649 | { | |
650 | struct core_dc *core_dc = DC_TO_CORE(*dc); | |
651 | destruct(core_dc); | |
652 | dm_free(core_dc); | |
653 | *dc = NULL; | |
654 | } | |
655 | ||
07d72b39 | 656 | struct validate_context *dc_get_validate_context( |
4562236b HW |
657 | const struct dc *dc, |
658 | const struct dc_validation_set set[], | |
659 | uint8_t set_count) | |
660 | { | |
661 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
662 | enum dc_status result = DC_ERROR_UNEXPECTED; | |
663 | struct validate_context *context; | |
664 | ||
4562236b HW |
665 | context = dm_alloc(sizeof(struct validate_context)); |
666 | if(context == NULL) | |
667 | goto context_alloc_fail; | |
668 | ||
669 | result = core_dc->res_pool->funcs->validate_with_context( | |
430ef426 | 670 | core_dc, set, set_count, context, NULL); |
4562236b | 671 | |
4562236b HW |
672 | context_alloc_fail: |
673 | if (result != DC_OK) { | |
674 | dm_logger_write(core_dc->ctx->logger, LOG_WARNING, | |
675 | "%s:resource validation failed, dc_status:%d\n", | |
676 | __func__, | |
677 | result); | |
07d72b39 HW |
678 | |
679 | dc_resource_validate_ctx_destruct(context); | |
680 | dm_free(context); | |
681 | context = NULL; | |
4562236b HW |
682 | } |
683 | ||
07d72b39 HW |
684 | return context; |
685 | ||
686 | } | |
4562236b | 687 | |
07d72b39 HW |
688 | bool dc_validate_resources( |
689 | const struct dc *dc, | |
690 | const struct dc_validation_set set[], | |
691 | uint8_t set_count) | |
692 | { | |
693 | struct validate_context *ctx; | |
694 | ||
695 | ctx = dc_get_validate_context(dc, set, set_count); | |
696 | if (ctx) { | |
697 | dc_resource_validate_ctx_destruct(ctx); | |
698 | dm_free(ctx); | |
699 | return true; | |
700 | } | |
701 | ||
702 | return false; | |
4562236b HW |
703 | } |
704 | ||
705 | bool dc_validate_guaranteed( | |
706 | const struct dc *dc, | |
ab2541b6 | 707 | const struct dc_stream *stream) |
4562236b HW |
708 | { |
709 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
710 | enum dc_status result = DC_ERROR_UNEXPECTED; | |
711 | struct validate_context *context; | |
712 | ||
713 | context = dm_alloc(sizeof(struct validate_context)); | |
714 | if (context == NULL) | |
715 | goto context_alloc_fail; | |
716 | ||
717 | result = core_dc->res_pool->funcs->validate_guaranteed( | |
ab2541b6 | 718 | core_dc, stream, context); |
4562236b | 719 | |
8122a253 | 720 | dc_resource_validate_ctx_destruct(context); |
4562236b HW |
721 | dm_free(context); |
722 | ||
723 | context_alloc_fail: | |
724 | if (result != DC_OK) { | |
725 | dm_logger_write(core_dc->ctx->logger, LOG_WARNING, | |
726 | "%s:guaranteed validation failed, dc_status:%d\n", | |
727 | __func__, | |
728 | result); | |
729 | } | |
730 | ||
731 | return (result == DC_OK); | |
732 | } | |
733 | ||
734 | static void program_timing_sync( | |
735 | struct core_dc *core_dc, | |
736 | struct validate_context *ctx) | |
737 | { | |
738 | int i, j; | |
739 | int group_index = 0; | |
a2b8659d | 740 | int pipe_count = core_dc->res_pool->pipe_count; |
4562236b HW |
741 | struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL }; |
742 | ||
743 | for (i = 0; i < pipe_count; i++) { | |
744 | if (!ctx->res_ctx.pipe_ctx[i].stream || ctx->res_ctx.pipe_ctx[i].top_pipe) | |
745 | continue; | |
746 | ||
747 | unsynced_pipes[i] = &ctx->res_ctx.pipe_ctx[i]; | |
748 | } | |
749 | ||
750 | for (i = 0; i < pipe_count; i++) { | |
751 | int group_size = 1; | |
752 | struct pipe_ctx *pipe_set[MAX_PIPES]; | |
753 | ||
754 | if (!unsynced_pipes[i]) | |
755 | continue; | |
756 | ||
757 | pipe_set[0] = unsynced_pipes[i]; | |
758 | unsynced_pipes[i] = NULL; | |
759 | ||
760 | /* Add tg to the set, search rest of the tg's for ones with | |
761 | * same timing, add all tgs with same timing to the group | |
762 | */ | |
763 | for (j = i + 1; j < pipe_count; j++) { | |
764 | if (!unsynced_pipes[j]) | |
765 | continue; | |
766 | ||
767 | if (resource_are_streams_timing_synchronizable( | |
768 | unsynced_pipes[j]->stream, | |
769 | pipe_set[0]->stream)) { | |
770 | pipe_set[group_size] = unsynced_pipes[j]; | |
771 | unsynced_pipes[j] = NULL; | |
772 | group_size++; | |
773 | } | |
774 | } | |
775 | ||
776 | /* set first unblanked pipe as master */ | |
777 | for (j = 0; j < group_size; j++) { | |
778 | struct pipe_ctx *temp; | |
779 | ||
780 | if (!pipe_set[j]->tg->funcs->is_blanked(pipe_set[j]->tg)) { | |
781 | if (j == 0) | |
782 | break; | |
783 | ||
784 | temp = pipe_set[0]; | |
785 | pipe_set[0] = pipe_set[j]; | |
786 | pipe_set[j] = temp; | |
787 | break; | |
788 | } | |
789 | } | |
790 | ||
791 | /* remove any other unblanked pipes as they have already been synced */ | |
792 | for (j = j + 1; j < group_size; j++) { | |
793 | if (!pipe_set[j]->tg->funcs->is_blanked(pipe_set[j]->tg)) { | |
794 | group_size--; | |
795 | pipe_set[j] = pipe_set[group_size]; | |
796 | j--; | |
797 | } | |
798 | } | |
799 | ||
800 | if (group_size > 1) { | |
801 | core_dc->hwss.enable_timing_synchronization( | |
802 | core_dc, group_index, group_size, pipe_set); | |
803 | group_index++; | |
804 | } | |
805 | } | |
806 | } | |
807 | ||
ab2541b6 | 808 | static bool streams_changed( |
4562236b | 809 | struct core_dc *dc, |
ab2541b6 AC |
810 | const struct dc_stream *streams[], |
811 | uint8_t stream_count) | |
4562236b HW |
812 | { |
813 | uint8_t i; | |
814 | ||
ab2541b6 | 815 | if (stream_count != dc->current_context->stream_count) |
4562236b HW |
816 | return true; |
817 | ||
ab2541b6 AC |
818 | for (i = 0; i < dc->current_context->stream_count; i++) { |
819 | if (&dc->current_context->streams[i]->public != streams[i]) | |
4562236b HW |
820 | return true; |
821 | } | |
822 | ||
823 | return false; | |
824 | } | |
825 | ||
ab2541b6 | 826 | bool dc_commit_streams( |
4562236b | 827 | struct dc *dc, |
ab2541b6 AC |
828 | const struct dc_stream *streams[], |
829 | uint8_t stream_count) | |
4562236b HW |
830 | { |
831 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
832 | struct dc_bios *dcb = core_dc->ctx->dc_bios; | |
833 | enum dc_status result = DC_ERROR_UNEXPECTED; | |
834 | struct validate_context *context; | |
e72f0acd | 835 | struct dc_validation_set set[MAX_STREAMS] = { {0, {0} } }; |
f196f080 | 836 | int i, j; |
4562236b | 837 | |
ab2541b6 | 838 | if (false == streams_changed(core_dc, streams, stream_count)) |
4562236b HW |
839 | return DC_OK; |
840 | ||
ab2541b6 AC |
841 | dm_logger_write(core_dc->ctx->logger, LOG_DC, "%s: %d streams\n", |
842 | __func__, stream_count); | |
4562236b | 843 | |
ab2541b6 AC |
844 | for (i = 0; i < stream_count; i++) { |
845 | const struct dc_stream *stream = streams[i]; | |
f84a8161 TC |
846 | const struct dc_stream_status *status = dc_stream_get_status(stream); |
847 | int j; | |
4562236b | 848 | |
ab2541b6 | 849 | dc_stream_log(stream, |
4562236b HW |
850 | core_dc->ctx->logger, |
851 | LOG_DC); | |
852 | ||
ab2541b6 | 853 | set[i].stream = stream; |
f84a8161 TC |
854 | |
855 | if (status) { | |
856 | set[i].surface_count = status->surface_count; | |
857 | for (j = 0; j < status->surface_count; j++) | |
858 | set[i].surfaces[j] = status->surfaces[j]; | |
859 | } | |
4562236b HW |
860 | |
861 | } | |
862 | ||
863 | context = dm_alloc(sizeof(struct validate_context)); | |
864 | if (context == NULL) | |
865 | goto context_alloc_fail; | |
866 | ||
430ef426 DL |
867 | result = core_dc->res_pool->funcs->validate_with_context( |
868 | core_dc, set, stream_count, context, core_dc->current_context); | |
4562236b HW |
869 | if (result != DC_OK){ |
870 | dm_logger_write(core_dc->ctx->logger, LOG_ERROR, | |
871 | "%s: Context validation failed! dc_status:%d\n", | |
872 | __func__, | |
873 | result); | |
874 | BREAK_TO_DEBUGGER(); | |
8122a253 | 875 | dc_resource_validate_ctx_destruct(context); |
4562236b HW |
876 | goto fail; |
877 | } | |
878 | ||
879 | if (!dcb->funcs->is_accelerated_mode(dcb)) { | |
880 | core_dc->hwss.enable_accelerated_mode(core_dc); | |
881 | } | |
882 | ||
883 | if (result == DC_OK) { | |
884 | result = core_dc->hwss.apply_ctx_to_hw(core_dc, context); | |
885 | } | |
886 | ||
887 | program_timing_sync(core_dc, context); | |
888 | ||
ab2541b6 AC |
889 | for (i = 0; i < context->stream_count; i++) { |
890 | const struct core_sink *sink = context->streams[i]->sink; | |
4562236b | 891 | |
ab2541b6 | 892 | for (j = 0; j < context->stream_status[i].surface_count; j++) { |
f196f080 YS |
893 | struct core_surface *surface = |
894 | DC_SURFACE_TO_CORE(context->stream_status[i].surfaces[j]); | |
4562236b | 895 | |
f196f080 | 896 | core_dc->hwss.apply_ctx_for_surface(core_dc, surface, context); |
4562236b HW |
897 | } |
898 | ||
899 | CONN_MSG_MODE(sink->link, "{%dx%d, %dx%d@%dKhz}", | |
ab2541b6 AC |
900 | context->streams[i]->public.timing.h_addressable, |
901 | context->streams[i]->public.timing.v_addressable, | |
902 | context->streams[i]->public.timing.h_total, | |
903 | context->streams[i]->public.timing.v_total, | |
904 | context->streams[i]->public.timing.pix_clk_khz); | |
4562236b HW |
905 | } |
906 | ||
8122a253 | 907 | dc_resource_validate_ctx_destruct(core_dc->current_context); |
6d9501e4 | 908 | dm_free(core_dc->current_context); |
4562236b | 909 | |
4562236b HW |
910 | core_dc->current_context = context; |
911 | ||
912 | return (result == DC_OK); | |
913 | ||
914 | fail: | |
915 | dm_free(context); | |
916 | ||
917 | context_alloc_fail: | |
918 | return (result == DC_OK); | |
919 | } | |
920 | ||
ab2541b6 | 921 | bool dc_pre_update_surfaces_to_stream( |
4562236b HW |
922 | struct dc *dc, |
923 | const struct dc_surface *const *new_surfaces, | |
924 | uint8_t new_surface_count, | |
ab2541b6 | 925 | const struct dc_stream *dc_stream) |
4562236b | 926 | { |
745cc746 | 927 | return true; |
4562236b HW |
928 | } |
929 | ||
ab2541b6 | 930 | bool dc_post_update_surfaces_to_stream(struct dc *dc) |
4562236b | 931 | { |
4562236b | 932 | int i; |
45209ef7 | 933 | struct core_dc *core_dc = DC_TO_CORE(dc); |
9037d802 | 934 | struct validate_context *context = core_dc->current_context; |
4562236b HW |
935 | |
936 | post_surface_trace(dc); | |
de37e273 | 937 | |
a2b8659d | 938 | for (i = 0; i < core_dc->res_pool->pipe_count; i++) |
45209ef7 DL |
939 | if (context->res_ctx.pipe_ctx[i].stream == NULL) { |
940 | context->res_ctx.pipe_ctx[i].pipe_idx = i; | |
4562236b | 941 | core_dc->hwss.power_down_front_end( |
45209ef7 | 942 | core_dc, &context->res_ctx.pipe_ctx[i]); |
bb9042da | 943 | } |
4562236b | 944 | |
cf437593 | 945 | core_dc->hwss.set_bandwidth(core_dc, context, true); |
45209ef7 | 946 | |
de37e273 | 947 | return true; |
4562236b HW |
948 | } |
949 | ||
ab2541b6 | 950 | bool dc_commit_surfaces_to_stream( |
4562236b HW |
951 | struct dc *dc, |
952 | const struct dc_surface **new_surfaces, | |
953 | uint8_t new_surface_count, | |
ab2541b6 | 954 | const struct dc_stream *dc_stream) |
4562236b | 955 | { |
ab2541b6 AC |
956 | struct dc_surface_update updates[MAX_SURFACES]; |
957 | struct dc_flip_addrs flip_addr[MAX_SURFACES]; | |
958 | struct dc_plane_info plane_info[MAX_SURFACES]; | |
959 | struct dc_scaling_info scaling_info[MAX_SURFACES]; | |
4562236b HW |
960 | int i; |
961 | ||
ab2541b6 AC |
962 | memset(updates, 0, sizeof(updates)); |
963 | memset(flip_addr, 0, sizeof(flip_addr)); | |
964 | memset(plane_info, 0, sizeof(plane_info)); | |
965 | memset(scaling_info, 0, sizeof(scaling_info)); | |
966 | ||
4562236b HW |
967 | for (i = 0; i < new_surface_count; i++) { |
968 | updates[i].surface = new_surfaces[i]; | |
89e89630 AZ |
969 | updates[i].gamma = |
970 | (struct dc_gamma *)new_surfaces[i]->gamma_correction; | |
4562236b HW |
971 | flip_addr[i].address = new_surfaces[i]->address; |
972 | flip_addr[i].flip_immediate = new_surfaces[i]->flip_immediate; | |
973 | plane_info[i].color_space = new_surfaces[i]->color_space; | |
974 | plane_info[i].format = new_surfaces[i]->format; | |
975 | plane_info[i].plane_size = new_surfaces[i]->plane_size; | |
976 | plane_info[i].rotation = new_surfaces[i]->rotation; | |
977 | plane_info[i].horizontal_mirror = new_surfaces[i]->horizontal_mirror; | |
978 | plane_info[i].stereo_format = new_surfaces[i]->stereo_format; | |
979 | plane_info[i].tiling_info = new_surfaces[i]->tiling_info; | |
980 | plane_info[i].visible = new_surfaces[i]->visible; | |
5c1879b6 | 981 | plane_info[i].dcc = new_surfaces[i]->dcc; |
4562236b HW |
982 | scaling_info[i].scaling_quality = new_surfaces[i]->scaling_quality; |
983 | scaling_info[i].src_rect = new_surfaces[i]->src_rect; | |
984 | scaling_info[i].dst_rect = new_surfaces[i]->dst_rect; | |
985 | scaling_info[i].clip_rect = new_surfaces[i]->clip_rect; | |
986 | ||
987 | updates[i].flip_addr = &flip_addr[i]; | |
988 | updates[i].plane_info = &plane_info[i]; | |
989 | updates[i].scaling_info = &scaling_info[i]; | |
990 | } | |
ab2541b6 | 991 | dc_update_surfaces_for_stream(dc, updates, new_surface_count, dc_stream); |
4562236b | 992 | |
ab2541b6 | 993 | return dc_post_update_surfaces_to_stream(dc); |
4562236b HW |
994 | } |
995 | ||
e72f0acd TC |
996 | static bool is_surface_in_context( |
997 | const struct validate_context *context, | |
998 | const struct dc_surface *surface) | |
4562236b | 999 | { |
e72f0acd | 1000 | int j; |
4562236b | 1001 | |
a2b8659d | 1002 | for (j = 0; j < MAX_PIPES; j++) { |
e72f0acd | 1003 | const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; |
4562236b | 1004 | |
e72f0acd TC |
1005 | if (surface == &pipe_ctx->surface->public) { |
1006 | return true; | |
1007 | } | |
1008 | } | |
4562236b | 1009 | |
e72f0acd TC |
1010 | return false; |
1011 | } | |
4562236b | 1012 | |
5869b0f6 LE |
1013 | static unsigned int pixel_format_to_bpp(enum surface_pixel_format format) |
1014 | { | |
1015 | switch (format) { | |
0e12c3f6 DL |
1016 | case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: |
1017 | case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: | |
1018 | return 12; | |
5869b0f6 LE |
1019 | case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: |
1020 | case SURFACE_PIXEL_FORMAT_GRPH_RGB565: | |
0e12c3f6 DL |
1021 | case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: |
1022 | case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: | |
5869b0f6 LE |
1023 | return 16; |
1024 | case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: | |
1025 | case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: | |
1026 | case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: | |
1027 | case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: | |
1028 | return 32; | |
1029 | case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: | |
1030 | case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: | |
1031 | case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: | |
1032 | return 64; | |
1033 | default: | |
1034 | ASSERT_CRITICAL(false); | |
1035 | return -1; | |
1036 | } | |
1037 | } | |
1038 | ||
1039 | static enum surface_update_type get_plane_info_update_type( | |
fb9611d2 YS |
1040 | const struct dc_surface_update *u, |
1041 | int surface_index) | |
5869b0f6 LE |
1042 | { |
1043 | struct dc_plane_info temp_plane_info = { { { { 0 } } } }; | |
1044 | ||
1045 | if (!u->plane_info) | |
1046 | return UPDATE_TYPE_FAST; | |
1047 | ||
1048 | /* Copy all parameters that will cause a full update | |
1049 | * from current surface, the rest of the parameters | |
1050 | * from provided plane configuration. | |
1051 | * Perform memory compare and special validation | |
1052 | * for those that can cause fast/medium updates | |
1053 | */ | |
1054 | ||
1055 | /* Full update parameters */ | |
1056 | temp_plane_info.color_space = u->surface->color_space; | |
1057 | temp_plane_info.dcc = u->surface->dcc; | |
1058 | temp_plane_info.horizontal_mirror = u->surface->horizontal_mirror; | |
1059 | temp_plane_info.plane_size = u->surface->plane_size; | |
1060 | temp_plane_info.rotation = u->surface->rotation; | |
1061 | temp_plane_info.stereo_format = u->surface->stereo_format; | |
1062 | temp_plane_info.tiling_info = u->surface->tiling_info; | |
5869b0f6 LE |
1063 | |
1064 | /* Special Validation parameters */ | |
1065 | temp_plane_info.format = u->plane_info->format; | |
fb9611d2 YS |
1066 | |
1067 | if (surface_index == 0) | |
1068 | temp_plane_info.visible = u->plane_info->visible; | |
1069 | else | |
1070 | temp_plane_info.visible = u->surface->visible; | |
5869b0f6 LE |
1071 | |
1072 | if (memcmp(u->plane_info, &temp_plane_info, | |
1073 | sizeof(struct dc_plane_info)) != 0) | |
1074 | return UPDATE_TYPE_FULL; | |
1075 | ||
1076 | if (pixel_format_to_bpp(u->plane_info->format) != | |
1077 | pixel_format_to_bpp(u->surface->format)) { | |
1078 | return UPDATE_TYPE_FULL; | |
1079 | } else { | |
1080 | return UPDATE_TYPE_MED; | |
1081 | } | |
1082 | } | |
1083 | ||
1084 | static enum surface_update_type get_scaling_info_update_type( | |
1085 | const struct dc_surface_update *u) | |
1086 | { | |
5869b0f6 LE |
1087 | if (!u->scaling_info) |
1088 | return UPDATE_TYPE_FAST; | |
1089 | ||
b71a0618 DL |
1090 | if (u->scaling_info->src_rect.width != u->surface->src_rect.width |
1091 | || u->scaling_info->src_rect.height != u->surface->src_rect.height | |
1092 | || u->scaling_info->clip_rect.width != u->surface->clip_rect.width | |
1093 | || u->scaling_info->clip_rect.height != u->surface->clip_rect.height | |
1094 | || u->scaling_info->dst_rect.width != u->surface->dst_rect.width | |
1095 | || u->scaling_info->dst_rect.height != u->surface->dst_rect.height) | |
5869b0f6 LE |
1096 | return UPDATE_TYPE_FULL; |
1097 | ||
b71a0618 DL |
1098 | if (u->scaling_info->src_rect.x != u->surface->src_rect.x |
1099 | || u->scaling_info->src_rect.y != u->surface->src_rect.y | |
1100 | || u->scaling_info->clip_rect.x != u->surface->clip_rect.x | |
1101 | || u->scaling_info->clip_rect.y != u->surface->clip_rect.y | |
1102 | || u->scaling_info->dst_rect.x != u->surface->dst_rect.x | |
1103 | || u->scaling_info->dst_rect.y != u->surface->dst_rect.y) | |
1104 | return UPDATE_TYPE_MED; | |
5869b0f6 LE |
1105 | |
1106 | return UPDATE_TYPE_FAST; | |
1107 | } | |
4562236b | 1108 | |
e72f0acd TC |
1109 | static enum surface_update_type det_surface_update( |
1110 | const struct core_dc *dc, | |
fb9611d2 YS |
1111 | const struct dc_surface_update *u, |
1112 | int surface_index) | |
e72f0acd TC |
1113 | { |
1114 | const struct validate_context *context = dc->current_context; | |
5869b0f6 LE |
1115 | enum surface_update_type type = UPDATE_TYPE_FAST; |
1116 | enum surface_update_type overall_type = UPDATE_TYPE_FAST; | |
4562236b | 1117 | |
e72f0acd TC |
1118 | if (!is_surface_in_context(context, u->surface)) |
1119 | return UPDATE_TYPE_FULL; | |
4562236b | 1120 | |
fb9611d2 | 1121 | type = get_plane_info_update_type(u, surface_index); |
5869b0f6 LE |
1122 | if (overall_type < type) |
1123 | overall_type = type; | |
1124 | ||
1125 | type = get_scaling_info_update_type(u); | |
1126 | if (overall_type < type) | |
1127 | overall_type = type; | |
1128 | ||
e72f0acd | 1129 | if (u->in_transfer_func || |
5869b0f6 LE |
1130 | u->hdr_static_metadata) { |
1131 | if (overall_type < UPDATE_TYPE_MED) | |
1132 | overall_type = UPDATE_TYPE_MED; | |
1133 | } | |
1c4e6bce | 1134 | |
5869b0f6 | 1135 | return overall_type; |
e72f0acd | 1136 | } |
4562236b | 1137 | |
5869b0f6 LE |
1138 | enum surface_update_type dc_check_update_surfaces_for_stream( |
1139 | struct dc *dc, | |
e72f0acd TC |
1140 | struct dc_surface_update *updates, |
1141 | int surface_count, | |
ee8f63e1 | 1142 | struct dc_stream_update *stream_update, |
e72f0acd TC |
1143 | const struct dc_stream_status *stream_status) |
1144 | { | |
5869b0f6 | 1145 | struct core_dc *core_dc = DC_TO_CORE(dc); |
e72f0acd TC |
1146 | int i; |
1147 | enum surface_update_type overall_type = UPDATE_TYPE_FAST; | |
1148 | ||
1ce71fcd | 1149 | if (stream_status == NULL || stream_status->surface_count != surface_count) |
e72f0acd TC |
1150 | return UPDATE_TYPE_FULL; |
1151 | ||
ee8f63e1 LE |
1152 | if (stream_update) |
1153 | return UPDATE_TYPE_FULL; | |
1154 | ||
e72f0acd TC |
1155 | for (i = 0 ; i < surface_count; i++) { |
1156 | enum surface_update_type type = | |
fb9611d2 | 1157 | det_surface_update(core_dc, &updates[i], i); |
e72f0acd TC |
1158 | |
1159 | if (type == UPDATE_TYPE_FULL) | |
1160 | return type; | |
1c4e6bce | 1161 | |
e72f0acd TC |
1162 | if (overall_type < type) |
1163 | overall_type = type; | |
4562236b HW |
1164 | } |
1165 | ||
e72f0acd TC |
1166 | return overall_type; |
1167 | } | |
4562236b | 1168 | |
ee8f63e1 | 1169 | void dc_update_surfaces_for_stream(struct dc *dc, |
a783e7b5 | 1170 | struct dc_surface_update *surface_updates, int surface_count, |
ee8f63e1 | 1171 | const struct dc_stream *dc_stream) |
a783e7b5 | 1172 | { |
ee8f63e1 LE |
1173 | dc_update_surfaces_and_stream(dc, surface_updates, surface_count, |
1174 | dc_stream, NULL); | |
a783e7b5 LE |
1175 | } |
1176 | ||
e72f0acd | 1177 | enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL; |
4562236b | 1178 | |
ee8f63e1 LE |
1179 | void dc_update_surfaces_and_stream(struct dc *dc, |
1180 | struct dc_surface_update *srf_updates, int surface_count, | |
1181 | const struct dc_stream *dc_stream, | |
1182 | struct dc_stream_update *stream_update) | |
e72f0acd TC |
1183 | { |
1184 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
1185 | struct validate_context *context; | |
1186 | int i, j; | |
e72f0acd TC |
1187 | enum surface_update_type update_type; |
1188 | const struct dc_stream_status *stream_status; | |
ee8f63e1 | 1189 | struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); |
e72f0acd TC |
1190 | |
1191 | stream_status = dc_stream_get_status(dc_stream); | |
1192 | ASSERT(stream_status); | |
1193 | if (!stream_status) | |
1194 | return; /* Cannot commit surface to stream that is not committed */ | |
1195 | ||
5869b0f6 | 1196 | update_type = dc_check_update_surfaces_for_stream( |
ee8f63e1 | 1197 | dc, srf_updates, surface_count, stream_update, stream_status); |
4562236b | 1198 | |
e72f0acd | 1199 | if (update_type >= update_surface_trace_level) |
ee8f63e1 | 1200 | update_surface_trace(dc, srf_updates, surface_count); |
e72f0acd TC |
1201 | |
1202 | if (update_type >= UPDATE_TYPE_FULL) { | |
1203 | const struct dc_surface *new_surfaces[MAX_SURFACES] = { 0 }; | |
1204 | ||
1205 | for (i = 0; i < surface_count; i++) | |
ee8f63e1 | 1206 | new_surfaces[i] = srf_updates[i].surface; |
e72f0acd TC |
1207 | |
1208 | /* initialize scratch memory for building context */ | |
6d9501e4 | 1209 | context = dm_alloc(sizeof(*context)); |
8122a253 | 1210 | dc_resource_validate_ctx_copy_construct( |
e72f0acd TC |
1211 | core_dc->current_context, context); |
1212 | ||
1213 | /* add surface to context */ | |
4562236b | 1214 | if (!resource_attach_surfaces_to_context( |
a2b8659d TC |
1215 | new_surfaces, surface_count, dc_stream, |
1216 | context, core_dc->res_pool)) { | |
4562236b | 1217 | BREAK_TO_DEBUGGER(); |
6d9501e4 | 1218 | goto fail; |
4562236b | 1219 | } |
e72f0acd TC |
1220 | } else { |
1221 | context = core_dc->current_context; | |
4562236b | 1222 | } |
ee8f63e1 LE |
1223 | |
1224 | /* update current stream with the new updates */ | |
1225 | if (stream_update) { | |
f46661dd AZ |
1226 | if ((stream_update->src.height != 0) && |
1227 | (stream_update->src.width != 0)) | |
1228 | stream->public.src = stream_update->src; | |
1229 | ||
1230 | if ((stream_update->dst.height != 0) && | |
1231 | (stream_update->dst.width != 0)) | |
1232 | stream->public.dst = stream_update->dst; | |
1233 | ||
1234 | if (stream_update->out_transfer_func && | |
1235 | stream_update->out_transfer_func != | |
1236 | dc_stream->out_transfer_func) { | |
1237 | if (stream_update->out_transfer_func->type != | |
1238 | TF_TYPE_UNKNOWN) { | |
1239 | if (dc_stream->out_transfer_func != NULL) | |
1240 | dc_transfer_func_release | |
1241 | (dc_stream->out_transfer_func); | |
1242 | dc_transfer_func_retain(stream_update-> | |
1243 | out_transfer_func); | |
1244 | stream->public.out_transfer_func = | |
1245 | stream_update->out_transfer_func; | |
1246 | } | |
1247 | } | |
ee8f63e1 LE |
1248 | } |
1249 | ||
1250 | /* save update parameters into surface */ | |
4562236b | 1251 | for (i = 0; i < surface_count; i++) { |
ee8f63e1 LE |
1252 | struct core_surface *surface = |
1253 | DC_SURFACE_TO_CORE(srf_updates[i].surface); | |
4562236b | 1254 | |
ee8f63e1 LE |
1255 | if (srf_updates[i].flip_addr) { |
1256 | surface->public.address = srf_updates[i].flip_addr->address; | |
e72f0acd | 1257 | surface->public.flip_immediate = |
ee8f63e1 | 1258 | srf_updates[i].flip_addr->flip_immediate; |
e72f0acd TC |
1259 | } |
1260 | ||
ee8f63e1 | 1261 | if (srf_updates[i].scaling_info) { |
e72f0acd | 1262 | surface->public.scaling_quality = |
ee8f63e1 | 1263 | srf_updates[i].scaling_info->scaling_quality; |
e72f0acd | 1264 | surface->public.dst_rect = |
ee8f63e1 | 1265 | srf_updates[i].scaling_info->dst_rect; |
e72f0acd | 1266 | surface->public.src_rect = |
ee8f63e1 | 1267 | srf_updates[i].scaling_info->src_rect; |
e72f0acd | 1268 | surface->public.clip_rect = |
ee8f63e1 | 1269 | srf_updates[i].scaling_info->clip_rect; |
e72f0acd TC |
1270 | } |
1271 | ||
ee8f63e1 | 1272 | if (srf_updates[i].plane_info) { |
e72f0acd | 1273 | surface->public.color_space = |
ee8f63e1 | 1274 | srf_updates[i].plane_info->color_space; |
e72f0acd | 1275 | surface->public.format = |
ee8f63e1 | 1276 | srf_updates[i].plane_info->format; |
e72f0acd | 1277 | surface->public.plane_size = |
ee8f63e1 | 1278 | srf_updates[i].plane_info->plane_size; |
e72f0acd | 1279 | surface->public.rotation = |
ee8f63e1 | 1280 | srf_updates[i].plane_info->rotation; |
e72f0acd | 1281 | surface->public.horizontal_mirror = |
ee8f63e1 | 1282 | srf_updates[i].plane_info->horizontal_mirror; |
e72f0acd | 1283 | surface->public.stereo_format = |
ee8f63e1 | 1284 | srf_updates[i].plane_info->stereo_format; |
e72f0acd | 1285 | surface->public.tiling_info = |
ee8f63e1 | 1286 | srf_updates[i].plane_info->tiling_info; |
e72f0acd | 1287 | surface->public.visible = |
ee8f63e1 | 1288 | srf_updates[i].plane_info->visible; |
e72f0acd | 1289 | surface->public.dcc = |
ee8f63e1 | 1290 | srf_updates[i].plane_info->dcc; |
e72f0acd TC |
1291 | } |
1292 | ||
e61a04f1 | 1293 | if (update_type >= UPDATE_TYPE_MED) { |
a2b8659d | 1294 | for (j = 0; j < core_dc->res_pool->pipe_count; j++) { |
ed151940 | 1295 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; |
4562236b | 1296 | |
ed151940 YS |
1297 | if (pipe_ctx->surface != surface) |
1298 | continue; | |
4562236b | 1299 | |
b2d0a103 | 1300 | resource_build_scaling_params(pipe_ctx); |
4562236b | 1301 | } |
e72f0acd | 1302 | } |
89e89630 | 1303 | |
ee8f63e1 LE |
1304 | if (srf_updates[i].gamma && |
1305 | srf_updates[i].gamma != surface->public.gamma_correction) { | |
e72f0acd TC |
1306 | if (surface->public.gamma_correction != NULL) |
1307 | dc_gamma_release(&surface->public. | |
1308 | gamma_correction); | |
89e89630 | 1309 | |
ee8f63e1 | 1310 | dc_gamma_retain(srf_updates[i].gamma); |
e72f0acd | 1311 | surface->public.gamma_correction = |
ee8f63e1 | 1312 | srf_updates[i].gamma; |
e72f0acd | 1313 | } |
fb735a9f | 1314 | |
ee8f63e1 LE |
1315 | if (srf_updates[i].in_transfer_func && |
1316 | srf_updates[i].in_transfer_func != surface->public.in_transfer_func) { | |
e72f0acd TC |
1317 | if (surface->public.in_transfer_func != NULL) |
1318 | dc_transfer_func_release( | |
1319 | surface->public. | |
1320 | in_transfer_func); | |
1321 | ||
1322 | dc_transfer_func_retain( | |
ee8f63e1 | 1323 | srf_updates[i].in_transfer_func); |
e72f0acd | 1324 | surface->public.in_transfer_func = |
ee8f63e1 | 1325 | srf_updates[i].in_transfer_func; |
e72f0acd | 1326 | } |
fb735a9f | 1327 | |
ee8f63e1 | 1328 | if (srf_updates[i].hdr_static_metadata) |
e72f0acd | 1329 | surface->public.hdr_static_ctx = |
ee8f63e1 | 1330 | *(srf_updates[i].hdr_static_metadata); |
4562236b HW |
1331 | } |
1332 | ||
745cc746 DL |
1333 | if (update_type == UPDATE_TYPE_FULL) { |
1334 | if (!core_dc->res_pool->funcs->validate_bandwidth(core_dc, context)) { | |
1335 | BREAK_TO_DEBUGGER(); | |
6d9501e4 | 1336 | goto fail; |
745cc746 DL |
1337 | } else |
1338 | core_dc->hwss.set_bandwidth(core_dc, context, false); | |
45209ef7 | 1339 | } |
e72f0acd TC |
1340 | |
1341 | if (!surface_count) /* reset */ | |
1342 | core_dc->hwss.apply_ctx_for_surface(core_dc, NULL, context); | |
1343 | ||
00f02019 | 1344 | /* Lock pipes for provided surfaces */ |
4562236b | 1345 | for (i = 0; i < surface_count; i++) { |
ee8f63e1 | 1346 | struct core_surface *surface = DC_SURFACE_TO_CORE(srf_updates[i].surface); |
4562236b | 1347 | |
a2b8659d | 1348 | for (j = 0; j < core_dc->res_pool->pipe_count; j++) { |
f0828115 | 1349 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; |
92a65e32 | 1350 | |
f0828115 CL |
1351 | if (pipe_ctx->surface != surface) |
1352 | continue; | |
d98e5cc2 | 1353 | if (!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) { |
f0828115 CL |
1354 | core_dc->hwss.pipe_control_lock( |
1355 | core_dc, | |
1356 | pipe_ctx, | |
e72f0acd TC |
1357 | true); |
1358 | } | |
00f02019 LE |
1359 | } |
1360 | } | |
1361 | ||
1362 | /* Perform requested Updates */ | |
1363 | for (i = 0; i < surface_count; i++) { | |
1364 | struct core_surface *surface = DC_SURFACE_TO_CORE(srf_updates[i].surface); | |
1365 | ||
1366 | if (update_type >= UPDATE_TYPE_MED) { | |
1367 | core_dc->hwss.apply_ctx_for_surface( | |
1368 | core_dc, surface, context); | |
1369 | context_timing_trace(dc, &context->res_ctx); | |
1370 | } | |
1371 | ||
a2b8659d | 1372 | for (j = 0; j < core_dc->res_pool->pipe_count; j++) { |
00f02019 LE |
1373 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; |
1374 | struct pipe_ctx *cur_pipe_ctx; | |
1375 | bool is_new_pipe_surface = true; | |
1376 | ||
1377 | if (pipe_ctx->surface != surface) | |
1378 | continue; | |
4562236b | 1379 | |
ee8f63e1 | 1380 | if (srf_updates[i].flip_addr) |
e72f0acd | 1381 | core_dc->hwss.update_plane_addr(core_dc, pipe_ctx); |
4562236b | 1382 | |
e72f0acd TC |
1383 | if (update_type == UPDATE_TYPE_FAST) |
1384 | continue; | |
1385 | ||
1386 | cur_pipe_ctx = &core_dc->current_context->res_ctx.pipe_ctx[j]; | |
1387 | if (cur_pipe_ctx->surface == pipe_ctx->surface) | |
1388 | is_new_pipe_surface = false; | |
1389 | ||
e72f0acd | 1390 | if (is_new_pipe_surface || |
ee8f63e1 | 1391 | srf_updates[i].in_transfer_func) |
90e508ba AK |
1392 | core_dc->hwss.set_input_transfer_func( |
1393 | pipe_ctx, pipe_ctx->surface); | |
1394 | ||
e72f0acd | 1395 | if (is_new_pipe_surface || |
f46661dd AZ |
1396 | (stream_update != NULL && |
1397 | stream_update->out_transfer_func != | |
1398 | NULL)) { | |
90e508ba | 1399 | core_dc->hwss.set_output_transfer_func( |
f46661dd AZ |
1400 | pipe_ctx, pipe_ctx->stream); |
1401 | } | |
90e508ba | 1402 | |
ee8f63e1 | 1403 | if (srf_updates[i].hdr_static_metadata) { |
fcd2f4bf AZ |
1404 | resource_build_info_frame(pipe_ctx); |
1405 | core_dc->hwss.update_info_frame(pipe_ctx); | |
1406 | } | |
9474980a | 1407 | } |
4562236b HW |
1408 | } |
1409 | ||
00f02019 | 1410 | /* Unlock pipes */ |
a2b8659d | 1411 | for (i = core_dc->res_pool->pipe_count - 1; i >= 0; i--) { |
4562236b HW |
1412 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; |
1413 | ||
1414 | for (j = 0; j < surface_count; j++) { | |
ee8f63e1 | 1415 | if (srf_updates[j].surface == &pipe_ctx->surface->public) { |
4562236b HW |
1416 | if (!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) { |
1417 | core_dc->hwss.pipe_control_lock( | |
f0828115 CL |
1418 | core_dc, |
1419 | pipe_ctx, | |
4562236b HW |
1420 | false); |
1421 | } | |
1422 | break; | |
1423 | } | |
1424 | } | |
1425 | } | |
1426 | ||
e72f0acd | 1427 | if (core_dc->current_context != context) { |
8122a253 | 1428 | dc_resource_validate_ctx_destruct(core_dc->current_context); |
6d9501e4 | 1429 | dm_free(core_dc->current_context); |
e72f0acd TC |
1430 | |
1431 | core_dc->current_context = context; | |
1432 | } | |
6d9501e4 HW |
1433 | return; |
1434 | ||
1435 | fail: | |
de37e273 DL |
1436 | dc_resource_validate_ctx_destruct(context); |
1437 | dm_free(context); | |
4562236b HW |
1438 | } |
1439 | ||
ab2541b6 | 1440 | uint8_t dc_get_current_stream_count(const struct dc *dc) |
4562236b HW |
1441 | { |
1442 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
ab2541b6 | 1443 | return core_dc->current_context->stream_count; |
4562236b HW |
1444 | } |
1445 | ||
ab2541b6 | 1446 | struct dc_stream *dc_get_stream_at_index(const struct dc *dc, uint8_t i) |
4562236b HW |
1447 | { |
1448 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
ab2541b6 AC |
1449 | if (i < core_dc->current_context->stream_count) |
1450 | return &(core_dc->current_context->streams[i]->public); | |
4562236b HW |
1451 | return NULL; |
1452 | } | |
1453 | ||
1454 | const struct dc_link *dc_get_link_at_index(const struct dc *dc, uint32_t link_index) | |
1455 | { | |
1456 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
1457 | return &core_dc->links[link_index]->public; | |
1458 | } | |
1459 | ||
1460 | const struct graphics_object_id dc_get_link_id_at_index( | |
1461 | struct dc *dc, uint32_t link_index) | |
1462 | { | |
1463 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
1464 | return core_dc->links[link_index]->link_id; | |
1465 | } | |
1466 | ||
4562236b HW |
1467 | enum dc_irq_source dc_get_hpd_irq_source_at_index( |
1468 | struct dc *dc, uint32_t link_index) | |
1469 | { | |
1470 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
1471 | return core_dc->links[link_index]->public.irq_source_hpd; | |
1472 | } | |
1473 | ||
1474 | const struct audio **dc_get_audios(struct dc *dc) | |
1475 | { | |
1476 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
1477 | return (const struct audio **)core_dc->res_pool->audios; | |
1478 | } | |
1479 | ||
4562236b HW |
1480 | enum dc_irq_source dc_interrupt_to_irq_source( |
1481 | struct dc *dc, | |
1482 | uint32_t src_id, | |
1483 | uint32_t ext_id) | |
1484 | { | |
1485 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
1486 | return dal_irq_service_to_irq_source(core_dc->res_pool->irqs, src_id, ext_id); | |
1487 | } | |
1488 | ||
1489 | void dc_interrupt_set(const struct dc *dc, enum dc_irq_source src, bool enable) | |
1490 | { | |
1491 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
1492 | dal_irq_service_set(core_dc->res_pool->irqs, src, enable); | |
1493 | } | |
1494 | ||
1495 | void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src) | |
1496 | { | |
1497 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
1498 | dal_irq_service_ack(core_dc->res_pool->irqs, src); | |
1499 | } | |
1500 | ||
1501 | void dc_set_power_state( | |
1502 | struct dc *dc, | |
a3621485 | 1503 | enum dc_acpi_cm_power_state power_state) |
4562236b HW |
1504 | { |
1505 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
1506 | ||
4562236b HW |
1507 | switch (power_state) { |
1508 | case DC_ACPI_CM_POWER_STATE_D0: | |
1509 | core_dc->hwss.init_hw(core_dc); | |
1510 | break; | |
1511 | default: | |
4562236b HW |
1512 | |
1513 | core_dc->hwss.power_down(core_dc); | |
1514 | ||
1515 | /* Zero out the current context so that on resume we start with | |
1516 | * clean state, and dc hw programming optimizations will not | |
1517 | * cause any trouble. | |
1518 | */ | |
1519 | memset(core_dc->current_context, 0, | |
1520 | sizeof(*core_dc->current_context)); | |
1521 | ||
4562236b HW |
1522 | break; |
1523 | } | |
1524 | ||
1525 | } | |
1526 | ||
1527 | void dc_resume(const struct dc *dc) | |
1528 | { | |
1529 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
1530 | ||
1531 | uint32_t i; | |
1532 | ||
1533 | for (i = 0; i < core_dc->link_count; i++) | |
1534 | core_link_resume(core_dc->links[i]); | |
1535 | } | |
1536 | ||
7c7f5b15 | 1537 | bool dc_read_aux_dpcd( |
4562236b HW |
1538 | struct dc *dc, |
1539 | uint32_t link_index, | |
1540 | uint32_t address, | |
1541 | uint8_t *data, | |
1542 | uint32_t size) | |
1543 | { | |
1544 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
1545 | ||
1546 | struct core_link *link = core_dc->links[link_index]; | |
1547 | enum ddc_result r = dal_ddc_service_read_dpcd_data( | |
46df790c | 1548 | link->public.ddc, |
7c7f5b15 AG |
1549 | false, |
1550 | I2C_MOT_UNDEF, | |
4562236b HW |
1551 | address, |
1552 | data, | |
1553 | size); | |
1554 | return r == DDC_RESULT_SUCESSFULL; | |
1555 | } | |
1556 | ||
7c7f5b15 | 1557 | bool dc_write_aux_dpcd( |
2b230ea3 ZF |
1558 | struct dc *dc, |
1559 | uint32_t link_index, | |
1560 | uint32_t address, | |
7c7f5b15 AG |
1561 | const uint8_t *data, |
1562 | uint32_t size) | |
1563 | { | |
2b230ea3 | 1564 | struct core_dc *core_dc = DC_TO_CORE(dc); |
2b230ea3 ZF |
1565 | struct core_link *link = core_dc->links[link_index]; |
1566 | ||
7c7f5b15 | 1567 | enum ddc_result r = dal_ddc_service_write_dpcd_data( |
46df790c | 1568 | link->public.ddc, |
7c7f5b15 AG |
1569 | false, |
1570 | I2C_MOT_UNDEF, | |
2b230ea3 | 1571 | address, |
7c7f5b15 AG |
1572 | data, |
1573 | size); | |
1574 | return r == DDC_RESULT_SUCESSFULL; | |
2b230ea3 ZF |
1575 | } |
1576 | ||
7c7f5b15 AG |
1577 | bool dc_read_aux_i2c( |
1578 | struct dc *dc, | |
1579 | uint32_t link_index, | |
1580 | enum i2c_mot_mode mot, | |
1581 | uint32_t address, | |
1582 | uint8_t *data, | |
1583 | uint32_t size) | |
1584 | { | |
1585 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
2b230ea3 | 1586 | |
7c7f5b15 AG |
1587 | struct core_link *link = core_dc->links[link_index]; |
1588 | enum ddc_result r = dal_ddc_service_read_dpcd_data( | |
46df790c | 1589 | link->public.ddc, |
7c7f5b15 AG |
1590 | true, |
1591 | mot, | |
1592 | address, | |
1593 | data, | |
1594 | size); | |
1595 | return r == DDC_RESULT_SUCESSFULL; | |
1596 | } | |
1597 | ||
1598 | bool dc_write_aux_i2c( | |
4562236b HW |
1599 | struct dc *dc, |
1600 | uint32_t link_index, | |
7c7f5b15 | 1601 | enum i2c_mot_mode mot, |
4562236b HW |
1602 | uint32_t address, |
1603 | const uint8_t *data, | |
1604 | uint32_t size) | |
1605 | { | |
1606 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
4562236b HW |
1607 | struct core_link *link = core_dc->links[link_index]; |
1608 | ||
1609 | enum ddc_result r = dal_ddc_service_write_dpcd_data( | |
46df790c | 1610 | link->public.ddc, |
7c7f5b15 AG |
1611 | true, |
1612 | mot, | |
4562236b HW |
1613 | address, |
1614 | data, | |
1615 | size); | |
1616 | return r == DDC_RESULT_SUCESSFULL; | |
1617 | } | |
1618 | ||
7c7f5b15 AG |
1619 | bool dc_query_ddc_data( |
1620 | struct dc *dc, | |
1621 | uint32_t link_index, | |
1622 | uint32_t address, | |
1623 | uint8_t *write_buf, | |
1624 | uint32_t write_size, | |
1625 | uint8_t *read_buf, | |
1626 | uint32_t read_size) { | |
1627 | ||
1628 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
1629 | ||
1630 | struct core_link *link = core_dc->links[link_index]; | |
1631 | ||
1632 | bool result = dal_ddc_service_query_ddc_data( | |
46df790c | 1633 | link->public.ddc, |
7c7f5b15 AG |
1634 | address, |
1635 | write_buf, | |
1636 | write_size, | |
1637 | read_buf, | |
1638 | read_size); | |
1639 | ||
1640 | return result; | |
1641 | } | |
1642 | ||
4562236b HW |
1643 | bool dc_submit_i2c( |
1644 | struct dc *dc, | |
1645 | uint32_t link_index, | |
1646 | struct i2c_command *cmd) | |
1647 | { | |
1648 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
1649 | ||
1650 | struct core_link *link = core_dc->links[link_index]; | |
46df790c | 1651 | struct ddc_service *ddc = link->public.ddc; |
4562236b HW |
1652 | |
1653 | return dal_i2caux_submit_i2c_command( | |
1654 | ddc->ctx->i2caux, | |
1655 | ddc->ddc_pin, | |
1656 | cmd); | |
1657 | } | |
1658 | ||
1659 | static bool link_add_remote_sink_helper(struct core_link *core_link, struct dc_sink *sink) | |
1660 | { | |
1661 | struct dc_link *dc_link = &core_link->public; | |
1662 | ||
1663 | if (dc_link->sink_count >= MAX_SINKS_PER_LINK) { | |
1664 | BREAK_TO_DEBUGGER(); | |
1665 | return false; | |
1666 | } | |
1667 | ||
1668 | dc_sink_retain(sink); | |
1669 | ||
1670 | dc_link->remote_sinks[dc_link->sink_count] = sink; | |
1671 | dc_link->sink_count++; | |
1672 | ||
1673 | return true; | |
1674 | } | |
1675 | ||
1676 | struct dc_sink *dc_link_add_remote_sink( | |
1677 | const struct dc_link *link, | |
1678 | const uint8_t *edid, | |
1679 | int len, | |
1680 | struct dc_sink_init_data *init_data) | |
1681 | { | |
1682 | struct dc_sink *dc_sink; | |
1683 | enum dc_edid_status edid_status; | |
1684 | struct core_link *core_link = DC_LINK_TO_LINK(link); | |
1685 | ||
1686 | if (len > MAX_EDID_BUFFER_SIZE) { | |
1687 | dm_error("Max EDID buffer size breached!\n"); | |
1688 | return NULL; | |
1689 | } | |
1690 | ||
1691 | if (!init_data) { | |
1692 | BREAK_TO_DEBUGGER(); | |
1693 | return NULL; | |
1694 | } | |
1695 | ||
1696 | if (!init_data->link) { | |
1697 | BREAK_TO_DEBUGGER(); | |
1698 | return NULL; | |
1699 | } | |
1700 | ||
1701 | dc_sink = dc_sink_create(init_data); | |
1702 | ||
1703 | if (!dc_sink) | |
1704 | return NULL; | |
1705 | ||
1706 | memmove(dc_sink->dc_edid.raw_edid, edid, len); | |
1707 | dc_sink->dc_edid.length = len; | |
1708 | ||
1709 | if (!link_add_remote_sink_helper( | |
1710 | core_link, | |
1711 | dc_sink)) | |
1712 | goto fail_add_sink; | |
1713 | ||
1714 | edid_status = dm_helpers_parse_edid_caps( | |
1715 | core_link->ctx, | |
1716 | &dc_sink->dc_edid, | |
1717 | &dc_sink->edid_caps); | |
1718 | ||
1719 | if (edid_status != EDID_OK) | |
1720 | goto fail; | |
1721 | ||
1722 | return dc_sink; | |
1723 | fail: | |
1724 | dc_link_remove_remote_sink(link, dc_sink); | |
1725 | fail_add_sink: | |
1726 | dc_sink_release(dc_sink); | |
1727 | return NULL; | |
1728 | } | |
1729 | ||
1730 | void dc_link_set_sink(const struct dc_link *link, struct dc_sink *sink) | |
1731 | { | |
1732 | struct core_link *core_link = DC_LINK_TO_LINK(link); | |
1733 | struct dc_link *dc_link = &core_link->public; | |
1734 | ||
1735 | dc_link->local_sink = sink; | |
1736 | ||
1737 | if (sink == NULL) { | |
1738 | dc_link->type = dc_connection_none; | |
1739 | } else { | |
1740 | dc_link->type = dc_connection_single; | |
1741 | } | |
1742 | } | |
1743 | ||
1744 | void dc_link_remove_remote_sink(const struct dc_link *link, const struct dc_sink *sink) | |
1745 | { | |
1746 | int i; | |
1747 | struct core_link *core_link = DC_LINK_TO_LINK(link); | |
1748 | struct dc_link *dc_link = &core_link->public; | |
1749 | ||
1750 | if (!link->sink_count) { | |
1751 | BREAK_TO_DEBUGGER(); | |
1752 | return; | |
1753 | } | |
1754 | ||
1755 | for (i = 0; i < dc_link->sink_count; i++) { | |
1756 | if (dc_link->remote_sinks[i] == sink) { | |
1757 | dc_sink_release(sink); | |
1758 | dc_link->remote_sinks[i] = NULL; | |
1759 | ||
1760 | /* shrink array to remove empty place */ | |
1761 | while (i < dc_link->sink_count - 1) { | |
1762 | dc_link->remote_sinks[i] = dc_link->remote_sinks[i+1]; | |
1763 | i++; | |
1764 | } | |
b64875fe | 1765 | dc_link->remote_sinks[i] = NULL; |
4562236b HW |
1766 | dc_link->sink_count--; |
1767 | return; | |
1768 | } | |
1769 | } | |
1770 | } | |
1771 | ||
2c8ad2d5 AD |
1772 | bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data) |
1773 | { | |
1774 | int i; | |
1775 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
1776 | struct mem_input *mi = NULL; | |
1777 | ||
1778 | for (i = 0; i < core_dc->res_pool->pipe_count; i++) { | |
1779 | if (core_dc->res_pool->mis[i] != NULL) { | |
1780 | mi = core_dc->res_pool->mis[i]; | |
1781 | break; | |
1782 | } | |
1783 | } | |
1784 | if (mi == NULL) { | |
1785 | dm_error("no mem_input!\n"); | |
1786 | return false; | |
1787 | } | |
1788 | ||
1789 | if (mi->funcs->mem_input_update_dchub) | |
1790 | mi->funcs->mem_input_update_dchub(mi, dh_data); | |
1791 | else | |
1792 | ASSERT(mi->funcs->mem_input_update_dchub); | |
1793 | ||
1794 | ||
1795 | return true; | |
1796 | ||
1797 | } | |
2c8ad2d5 | 1798 |