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4562236b HW |
1 | /* |
2 | * Copyright 2015 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: AMD | |
23 | */ | |
24 | ||
25 | #include "dm_services.h" | |
26 | ||
27 | #include "dc.h" | |
28 | ||
29 | #include "core_status.h" | |
30 | #include "core_types.h" | |
31 | #include "hw_sequencer.h" | |
32 | ||
33 | #include "resource.h" | |
34 | ||
35 | #include "clock_source.h" | |
36 | #include "dc_bios_types.h" | |
37 | ||
5e141de4 | 38 | #include "dce_calcs.h" |
4562236b HW |
39 | #include "bios_parser_interface.h" |
40 | #include "include/irq_service_interface.h" | |
41 | #include "transform.h" | |
42 | #include "timing_generator.h" | |
43 | #include "virtual/virtual_link_encoder.h" | |
44 | ||
45 | #include "link_hwss.h" | |
46 | #include "link_encoder.h" | |
47 | ||
48 | #include "dc_link_ddc.h" | |
49 | #include "dm_helpers.h" | |
50 | #include "mem_input.h" | |
51 | ||
4562236b HW |
52 | /******************************************************************************* |
53 | * Private functions | |
54 | ******************************************************************************/ | |
55 | static void destroy_links(struct core_dc *dc) | |
56 | { | |
57 | uint32_t i; | |
58 | ||
59 | for (i = 0; i < dc->link_count; i++) { | |
60 | if (NULL != dc->links[i]) | |
61 | link_destroy(&dc->links[i]); | |
62 | } | |
63 | } | |
64 | ||
65 | static bool create_links( | |
66 | struct core_dc *dc, | |
67 | uint32_t num_virtual_links) | |
68 | { | |
69 | int i; | |
70 | int connectors_num; | |
71 | struct dc_bios *bios = dc->ctx->dc_bios; | |
72 | ||
73 | dc->link_count = 0; | |
74 | ||
75 | connectors_num = bios->funcs->get_connectors_number(bios); | |
76 | ||
77 | if (connectors_num > ENUM_ID_COUNT) { | |
78 | dm_error( | |
79 | "DC: Number of connectors %d exceeds maximum of %d!\n", | |
80 | connectors_num, | |
81 | ENUM_ID_COUNT); | |
82 | return false; | |
83 | } | |
84 | ||
85 | if (connectors_num == 0 && num_virtual_links == 0) { | |
86 | dm_error("DC: Number of connectors is zero!\n"); | |
87 | } | |
88 | ||
89 | dm_output_to_console( | |
90 | "DC: %s: connectors_num: physical:%d, virtual:%d\n", | |
91 | __func__, | |
92 | connectors_num, | |
93 | num_virtual_links); | |
94 | ||
95 | for (i = 0; i < connectors_num; i++) { | |
96 | struct link_init_data link_init_params = {0}; | |
97 | struct core_link *link; | |
98 | ||
99 | link_init_params.ctx = dc->ctx; | |
100 | link_init_params.connector_index = i; | |
101 | link_init_params.link_index = dc->link_count; | |
102 | link_init_params.dc = dc; | |
103 | link = link_create(&link_init_params); | |
104 | ||
105 | if (link) { | |
106 | dc->links[dc->link_count] = link; | |
107 | link->dc = dc; | |
108 | ++dc->link_count; | |
109 | } else { | |
110 | dm_error("DC: failed to create link!\n"); | |
111 | } | |
112 | } | |
113 | ||
114 | for (i = 0; i < num_virtual_links; i++) { | |
115 | struct core_link *link = dm_alloc(sizeof(*link)); | |
116 | struct encoder_init_data enc_init = {0}; | |
117 | ||
118 | if (link == NULL) { | |
119 | BREAK_TO_DEBUGGER(); | |
120 | goto failed_alloc; | |
121 | } | |
122 | ||
123 | link->ctx = dc->ctx; | |
124 | link->dc = dc; | |
125 | link->public.connector_signal = SIGNAL_TYPE_VIRTUAL; | |
126 | link->link_id.type = OBJECT_TYPE_CONNECTOR; | |
127 | link->link_id.id = CONNECTOR_ID_VIRTUAL; | |
128 | link->link_id.enum_id = ENUM_ID_1; | |
129 | link->link_enc = dm_alloc(sizeof(*link->link_enc)); | |
130 | ||
131 | enc_init.ctx = dc->ctx; | |
132 | enc_init.channel = CHANNEL_ID_UNKNOWN; | |
133 | enc_init.hpd_source = HPD_SOURCEID_UNKNOWN; | |
134 | enc_init.transmitter = TRANSMITTER_UNKNOWN; | |
135 | enc_init.connector = link->link_id; | |
136 | enc_init.encoder.type = OBJECT_TYPE_ENCODER; | |
137 | enc_init.encoder.id = ENCODER_ID_INTERNAL_VIRTUAL; | |
138 | enc_init.encoder.enum_id = ENUM_ID_1; | |
139 | virtual_link_encoder_construct(link->link_enc, &enc_init); | |
140 | ||
141 | link->public.link_index = dc->link_count; | |
142 | dc->links[dc->link_count] = link; | |
143 | dc->link_count++; | |
144 | } | |
145 | ||
146 | return true; | |
147 | ||
148 | failed_alloc: | |
149 | return false; | |
150 | } | |
151 | ||
152 | static bool stream_adjust_vmin_vmax(struct dc *dc, | |
153 | const struct dc_stream **stream, int num_streams, | |
154 | int vmin, int vmax) | |
155 | { | |
156 | /* TODO: Support multiple streams */ | |
157 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
158 | struct core_stream *core_stream = DC_STREAM_TO_CORE(stream[0]); | |
159 | int i = 0; | |
160 | bool ret = false; | |
4562236b HW |
161 | |
162 | for (i = 0; i < MAX_PIPES; i++) { | |
6680b6a1 | 163 | struct pipe_ctx *pipe = &core_dc->current_context->res_ctx.pipe_ctx[i]; |
4562236b | 164 | |
6680b6a1 YS |
165 | if (pipe->stream == core_stream && pipe->stream_enc) { |
166 | core_dc->hwss.set_drr(&pipe, 1, vmin, vmax); | |
4562236b HW |
167 | |
168 | /* build and update the info frame */ | |
6680b6a1 YS |
169 | resource_build_info_frame(pipe); |
170 | core_dc->hwss.update_info_frame(pipe); | |
4562236b HW |
171 | |
172 | ret = true; | |
173 | } | |
174 | } | |
4562236b HW |
175 | return ret; |
176 | } | |
177 | ||
178 | ||
179 | static bool set_gamut_remap(struct dc *dc, | |
180 | const struct dc_stream **stream, int num_streams) | |
181 | { | |
182 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
183 | struct core_stream *core_stream = DC_STREAM_TO_CORE(stream[0]); | |
184 | int i = 0; | |
185 | bool ret = false; | |
186 | struct pipe_ctx *pipes; | |
187 | ||
188 | for (i = 0; i < MAX_PIPES; i++) { | |
189 | if (core_dc->current_context->res_ctx.pipe_ctx[i].stream | |
190 | == core_stream) { | |
191 | ||
192 | pipes = &core_dc->current_context->res_ctx.pipe_ctx[i]; | |
193 | core_dc->hwss.set_plane_config(core_dc, pipes, | |
194 | &core_dc->current_context->res_ctx); | |
195 | ret = true; | |
196 | } | |
197 | } | |
198 | ||
199 | return ret; | |
200 | } | |
201 | ||
202 | /* This function is not expected to fail, proper implementation of | |
203 | * validation will prevent this from ever being called for unsupported | |
204 | * configurations. | |
205 | */ | |
206 | static void stream_update_scaling( | |
207 | const struct dc *dc, | |
208 | const struct dc_stream *dc_stream, | |
209 | const struct rect *src, | |
210 | const struct rect *dst) | |
211 | { | |
212 | struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); | |
213 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
214 | struct validate_context *cur_ctx = core_dc->current_context; | |
ab2541b6 | 215 | int i; |
4562236b HW |
216 | |
217 | if (src) | |
218 | stream->public.src = *src; | |
219 | ||
220 | if (dst) | |
221 | stream->public.dst = *dst; | |
222 | ||
ab2541b6 AC |
223 | for (i = 0; i < cur_ctx->stream_count; i++) { |
224 | struct core_stream *cur_stream = cur_ctx->streams[i]; | |
4562236b | 225 | |
ab2541b6 AC |
226 | if (stream == cur_stream) { |
227 | struct dc_stream_status *status = &cur_ctx->stream_status[i]; | |
4562236b HW |
228 | |
229 | if (status->surface_count) | |
ab2541b6 | 230 | if (!dc_commit_surfaces_to_stream( |
4562236b HW |
231 | &core_dc->public, |
232 | status->surfaces, | |
233 | status->surface_count, | |
ab2541b6 | 234 | &cur_stream->public)) |
4562236b HW |
235 | /* Need to debug validation */ |
236 | BREAK_TO_DEBUGGER(); | |
237 | ||
238 | return; | |
239 | } | |
240 | } | |
241 | } | |
242 | ||
4562236b HW |
243 | static bool set_psr_enable(struct dc *dc, bool enable) |
244 | { | |
245 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
246 | int i; | |
247 | ||
248 | for (i = 0; i < core_dc->link_count; i++) | |
249 | dc_link_set_psr_enable(&core_dc->links[i]->public, | |
250 | enable); | |
251 | ||
252 | return true; | |
253 | } | |
254 | ||
255 | ||
256 | static bool setup_psr(struct dc *dc, const struct dc_stream *stream) | |
257 | { | |
258 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
259 | struct core_stream *core_stream = DC_STREAM_TO_CORE(stream); | |
260 | struct pipe_ctx *pipes; | |
261 | int i; | |
262 | unsigned int underlay_idx = core_dc->res_pool->underlay_pipe_index; | |
263 | ||
264 | for (i = 0; i < core_dc->link_count; i++) { | |
265 | if (core_stream->sink->link == core_dc->links[i]) | |
266 | dc_link_setup_psr(&core_dc->links[i]->public, | |
267 | stream); | |
268 | } | |
269 | ||
270 | for (i = 0; i < MAX_PIPES; i++) { | |
271 | if (core_dc->current_context->res_ctx.pipe_ctx[i].stream | |
272 | == core_stream && i != underlay_idx) { | |
273 | pipes = &core_dc->current_context->res_ctx.pipe_ctx[i]; | |
274 | core_dc->hwss.set_static_screen_control(&pipes, 1, | |
275 | 0x182); | |
276 | } | |
277 | } | |
278 | ||
279 | return true; | |
280 | } | |
281 | ||
282 | static void set_drive_settings(struct dc *dc, | |
bf5cda33 HW |
283 | struct link_training_settings *lt_settings, |
284 | const struct dc_link *link) | |
4562236b HW |
285 | { |
286 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
287 | int i; | |
288 | ||
bf5cda33 HW |
289 | for (i = 0; i < core_dc->link_count; i++) { |
290 | if (&core_dc->links[i]->public == link) | |
291 | break; | |
292 | } | |
293 | ||
294 | if (i >= core_dc->link_count) | |
295 | ASSERT_CRITICAL(false); | |
296 | ||
297 | dc_link_dp_set_drive_settings(&core_dc->links[i]->public, lt_settings); | |
4562236b HW |
298 | } |
299 | ||
300 | static void perform_link_training(struct dc *dc, | |
301 | struct dc_link_settings *link_setting, | |
302 | bool skip_video_pattern) | |
303 | { | |
304 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
305 | int i; | |
306 | ||
307 | for (i = 0; i < core_dc->link_count; i++) | |
308 | dc_link_dp_perform_link_training( | |
309 | &core_dc->links[i]->public, | |
310 | link_setting, | |
311 | skip_video_pattern); | |
312 | } | |
313 | ||
314 | static void set_preferred_link_settings(struct dc *dc, | |
88639168 ZF |
315 | struct dc_link_settings *link_setting, |
316 | const struct dc_link *link) | |
4562236b | 317 | { |
88639168 | 318 | struct core_link *core_link = DC_LINK_TO_CORE(link); |
4562236b | 319 | |
88639168 | 320 | core_link->public.verified_link_cap.lane_count = |
4562236b | 321 | link_setting->lane_count; |
88639168 | 322 | core_link->public.verified_link_cap.link_rate = |
4562236b | 323 | link_setting->link_rate; |
73c72602 | 324 | dp_retrain_link_dp_test(core_link, link_setting, false); |
4562236b HW |
325 | } |
326 | ||
327 | static void enable_hpd(const struct dc_link *link) | |
328 | { | |
329 | dc_link_dp_enable_hpd(link); | |
330 | } | |
331 | ||
332 | static void disable_hpd(const struct dc_link *link) | |
333 | { | |
334 | dc_link_dp_disable_hpd(link); | |
335 | } | |
336 | ||
337 | ||
338 | static void set_test_pattern( | |
339 | const struct dc_link *link, | |
340 | enum dp_test_pattern test_pattern, | |
341 | const struct link_training_settings *p_link_settings, | |
342 | const unsigned char *p_custom_pattern, | |
343 | unsigned int cust_pattern_size) | |
344 | { | |
345 | if (link != NULL) | |
346 | dc_link_dp_set_test_pattern( | |
347 | link, | |
348 | test_pattern, | |
349 | p_link_settings, | |
350 | p_custom_pattern, | |
351 | cust_pattern_size); | |
352 | } | |
353 | ||
354 | static void allocate_dc_stream_funcs(struct core_dc *core_dc) | |
355 | { | |
356 | core_dc->public.stream_funcs.stream_update_scaling = stream_update_scaling; | |
357 | if (core_dc->hwss.set_drr != NULL) { | |
358 | core_dc->public.stream_funcs.adjust_vmin_vmax = | |
359 | stream_adjust_vmin_vmax; | |
360 | } | |
361 | ||
362 | core_dc->public.stream_funcs.set_gamut_remap = | |
363 | set_gamut_remap; | |
364 | ||
4562236b HW |
365 | core_dc->public.stream_funcs.set_psr_enable = |
366 | set_psr_enable; | |
367 | ||
368 | core_dc->public.stream_funcs.setup_psr = | |
369 | setup_psr; | |
370 | ||
371 | core_dc->public.link_funcs.set_drive_settings = | |
372 | set_drive_settings; | |
373 | ||
374 | core_dc->public.link_funcs.perform_link_training = | |
375 | perform_link_training; | |
376 | ||
377 | core_dc->public.link_funcs.set_preferred_link_settings = | |
378 | set_preferred_link_settings; | |
379 | ||
380 | core_dc->public.link_funcs.enable_hpd = | |
381 | enable_hpd; | |
382 | ||
383 | core_dc->public.link_funcs.disable_hpd = | |
384 | disable_hpd; | |
385 | ||
386 | core_dc->public.link_funcs.set_test_pattern = | |
387 | set_test_pattern; | |
388 | } | |
389 | ||
390 | static void destruct(struct core_dc *dc) | |
391 | { | |
392 | resource_validate_ctx_destruct(dc->current_context); | |
393 | ||
4562236b HW |
394 | destroy_links(dc); |
395 | ||
396 | dc_destroy_resource_pool(dc); | |
397 | ||
398 | if (dc->ctx->gpio_service) | |
399 | dal_gpio_service_destroy(&dc->ctx->gpio_service); | |
400 | ||
401 | if (dc->ctx->i2caux) | |
402 | dal_i2caux_destroy(&dc->ctx->i2caux); | |
403 | ||
404 | if (dc->ctx->created_bios) | |
405 | dal_bios_parser_destroy(&dc->ctx->dc_bios); | |
406 | ||
407 | if (dc->ctx->logger) | |
408 | dal_logger_destroy(&dc->ctx->logger); | |
409 | ||
410 | dm_free(dc->current_context); | |
411 | dc->current_context = NULL; | |
412 | ||
413 | dm_free(dc->ctx); | |
414 | dc->ctx = NULL; | |
415 | } | |
416 | ||
417 | static bool construct(struct core_dc *dc, | |
418 | const struct dc_init_data *init_params) | |
419 | { | |
420 | struct dal_logger *logger; | |
421 | struct dc_context *dc_ctx = dm_alloc(sizeof(*dc_ctx)); | |
422 | enum dce_version dc_version = DCE_VERSION_UNKNOWN; | |
423 | ||
424 | if (!dc_ctx) { | |
425 | dm_error("%s: failed to create ctx\n", __func__); | |
426 | goto ctx_fail; | |
427 | } | |
428 | ||
429 | dc->current_context = dm_alloc(sizeof(*dc->current_context)); | |
4562236b | 430 | |
6d9501e4 | 431 | if (!dc->current_context) { |
4562236b HW |
432 | dm_error("%s: failed to create validate ctx\n", __func__); |
433 | goto val_ctx_fail; | |
434 | } | |
435 | ||
436 | dc_ctx->cgs_device = init_params->cgs_device; | |
437 | dc_ctx->driver_context = init_params->driver; | |
438 | dc_ctx->dc = &dc->public; | |
439 | dc_ctx->asic_id = init_params->asic_id; | |
440 | ||
441 | /* Create logger */ | |
442 | logger = dal_logger_create(dc_ctx); | |
443 | ||
444 | if (!logger) { | |
445 | /* can *not* call logger. call base driver 'print error' */ | |
446 | dm_error("%s: failed to create Logger!\n", __func__); | |
447 | goto logger_fail; | |
448 | } | |
449 | dc_ctx->logger = logger; | |
450 | dc->ctx = dc_ctx; | |
451 | dc->ctx->dce_environment = init_params->dce_environment; | |
452 | ||
453 | dc_version = resource_parse_asic_id(init_params->asic_id); | |
454 | dc->ctx->dce_version = dc_version; | |
455 | ||
456 | /* Resource should construct all asic specific resources. | |
457 | * This should be the only place where we need to parse the asic id | |
458 | */ | |
459 | if (init_params->vbios_override) | |
460 | dc_ctx->dc_bios = init_params->vbios_override; | |
461 | else { | |
462 | /* Create BIOS parser */ | |
463 | struct bp_init_data bp_init_data; | |
e8c963d6 | 464 | |
4562236b HW |
465 | bp_init_data.ctx = dc_ctx; |
466 | bp_init_data.bios = init_params->asic_id.atombios_base_address; | |
467 | ||
468 | dc_ctx->dc_bios = dal_bios_parser_create( | |
469 | &bp_init_data, dc_version); | |
470 | ||
471 | if (!dc_ctx->dc_bios) { | |
472 | ASSERT_CRITICAL(false); | |
473 | goto bios_fail; | |
474 | } | |
475 | ||
476 | dc_ctx->created_bios = true; | |
e8c963d6 | 477 | } |
4562236b HW |
478 | |
479 | /* Create I2C AUX */ | |
480 | dc_ctx->i2caux = dal_i2caux_create(dc_ctx); | |
481 | ||
482 | if (!dc_ctx->i2caux) { | |
483 | ASSERT_CRITICAL(false); | |
484 | goto failed_to_create_i2caux; | |
485 | } | |
486 | ||
487 | /* Create GPIO service */ | |
488 | dc_ctx->gpio_service = dal_gpio_service_create( | |
489 | dc_version, | |
490 | dc_ctx->dce_environment, | |
491 | dc_ctx); | |
492 | ||
493 | if (!dc_ctx->gpio_service) { | |
494 | ASSERT_CRITICAL(false); | |
495 | goto gpio_fail; | |
496 | } | |
497 | ||
498 | dc->res_pool = dc_create_resource_pool( | |
499 | dc, | |
500 | init_params->num_virtual_links, | |
501 | dc_version, | |
502 | init_params->asic_id); | |
503 | if (!dc->res_pool) | |
504 | goto create_resource_fail; | |
505 | ||
506 | if (!create_links(dc, init_params->num_virtual_links)) | |
507 | goto create_links_fail; | |
508 | ||
509 | allocate_dc_stream_funcs(dc); | |
510 | ||
511 | return true; | |
512 | ||
513 | /**** error handling here ****/ | |
514 | create_links_fail: | |
515 | create_resource_fail: | |
516 | gpio_fail: | |
517 | failed_to_create_i2caux: | |
518 | bios_fail: | |
519 | logger_fail: | |
520 | val_ctx_fail: | |
521 | ctx_fail: | |
522 | destruct(dc); | |
523 | return false; | |
524 | } | |
525 | ||
526 | /* | |
527 | void ProgramPixelDurationV(unsigned int pixelClockInKHz ) | |
528 | { | |
529 | fixed31_32 pixel_duration = Fixed31_32(100000000, pixelClockInKHz) * 10; | |
530 | unsigned int pixDurationInPico = round(pixel_duration); | |
531 | ||
532 | DPG_PIPE_ARBITRATION_CONTROL1 arb_control; | |
533 | ||
534 | arb_control.u32All = ReadReg (mmDPGV0_PIPE_ARBITRATION_CONTROL1); | |
535 | arb_control.bits.PIXEL_DURATION = pixDurationInPico; | |
536 | WriteReg (mmDPGV0_PIPE_ARBITRATION_CONTROL1, arb_control.u32All); | |
537 | ||
538 | arb_control.u32All = ReadReg (mmDPGV1_PIPE_ARBITRATION_CONTROL1); | |
539 | arb_control.bits.PIXEL_DURATION = pixDurationInPico; | |
540 | WriteReg (mmDPGV1_PIPE_ARBITRATION_CONTROL1, arb_control.u32All); | |
541 | ||
542 | WriteReg (mmDPGV0_PIPE_ARBITRATION_CONTROL2, 0x4000800); | |
543 | WriteReg (mmDPGV0_REPEATER_PROGRAM, 0x11); | |
544 | ||
545 | WriteReg (mmDPGV1_PIPE_ARBITRATION_CONTROL2, 0x4000800); | |
546 | WriteReg (mmDPGV1_REPEATER_PROGRAM, 0x11); | |
547 | } | |
548 | */ | |
549 | ||
550 | /******************************************************************************* | |
551 | * Public functions | |
552 | ******************************************************************************/ | |
553 | ||
554 | struct dc *dc_create(const struct dc_init_data *init_params) | |
555 | { | |
556 | struct core_dc *core_dc = dm_alloc(sizeof(*core_dc)); | |
557 | unsigned int full_pipe_count; | |
558 | ||
559 | if (NULL == core_dc) | |
560 | goto alloc_fail; | |
561 | ||
562 | if (false == construct(core_dc, init_params)) | |
563 | goto construct_fail; | |
564 | ||
565 | /*TODO: separate HW and SW initialization*/ | |
566 | core_dc->hwss.init_hw(core_dc); | |
567 | ||
568 | full_pipe_count = core_dc->res_pool->pipe_count; | |
f0e3db90 | 569 | if (core_dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE) |
4562236b | 570 | full_pipe_count--; |
ab2541b6 | 571 | core_dc->public.caps.max_streams = min( |
4562236b HW |
572 | full_pipe_count, |
573 | core_dc->res_pool->stream_enc_count); | |
574 | ||
575 | core_dc->public.caps.max_links = core_dc->link_count; | |
576 | core_dc->public.caps.max_audios = core_dc->res_pool->audio_count; | |
577 | ||
578 | core_dc->public.config = init_params->flags; | |
579 | ||
580 | dm_logger_write(core_dc->ctx->logger, LOG_DC, | |
581 | "Display Core initialized\n"); | |
582 | ||
583 | ||
584 | /* TODO: missing feature to be enabled */ | |
585 | core_dc->public.debug.disable_dfs_bypass = true; | |
586 | ||
587 | return &core_dc->public; | |
588 | ||
589 | construct_fail: | |
590 | dm_free(core_dc); | |
591 | ||
592 | alloc_fail: | |
593 | return NULL; | |
594 | } | |
595 | ||
596 | void dc_destroy(struct dc **dc) | |
597 | { | |
598 | struct core_dc *core_dc = DC_TO_CORE(*dc); | |
599 | destruct(core_dc); | |
600 | dm_free(core_dc); | |
601 | *dc = NULL; | |
602 | } | |
603 | ||
604 | static bool is_validation_required( | |
605 | const struct core_dc *dc, | |
606 | const struct dc_validation_set set[], | |
607 | int set_count) | |
608 | { | |
609 | const struct validate_context *context = dc->current_context; | |
610 | int i, j; | |
611 | ||
ab2541b6 | 612 | if (context->stream_count != set_count) |
4562236b HW |
613 | return true; |
614 | ||
615 | for (i = 0; i < set_count; i++) { | |
616 | ||
ab2541b6 | 617 | if (set[i].surface_count != context->stream_status[i].surface_count) |
4562236b | 618 | return true; |
ab2541b6 | 619 | if (!is_stream_unchanged(DC_STREAM_TO_CORE(set[i].stream), context->streams[i])) |
4562236b HW |
620 | return true; |
621 | ||
622 | for (j = 0; j < set[i].surface_count; j++) { | |
623 | struct dc_surface temp_surf = { 0 }; | |
624 | ||
ab2541b6 | 625 | temp_surf = *context->stream_status[i].surfaces[j]; |
4562236b HW |
626 | temp_surf.clip_rect = set[i].surfaces[j]->clip_rect; |
627 | temp_surf.dst_rect.x = set[i].surfaces[j]->dst_rect.x; | |
628 | temp_surf.dst_rect.y = set[i].surfaces[j]->dst_rect.y; | |
629 | ||
630 | if (memcmp(&temp_surf, set[i].surfaces[j], sizeof(temp_surf)) != 0) | |
631 | return true; | |
632 | } | |
633 | } | |
634 | ||
635 | return false; | |
636 | } | |
637 | ||
638 | bool dc_validate_resources( | |
639 | const struct dc *dc, | |
640 | const struct dc_validation_set set[], | |
641 | uint8_t set_count) | |
642 | { | |
643 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
644 | enum dc_status result = DC_ERROR_UNEXPECTED; | |
645 | struct validate_context *context; | |
646 | ||
647 | if (!is_validation_required(core_dc, set, set_count)) | |
648 | return true; | |
649 | ||
650 | context = dm_alloc(sizeof(struct validate_context)); | |
651 | if(context == NULL) | |
652 | goto context_alloc_fail; | |
653 | ||
654 | result = core_dc->res_pool->funcs->validate_with_context( | |
655 | core_dc, set, set_count, context); | |
656 | ||
657 | resource_validate_ctx_destruct(context); | |
658 | dm_free(context); | |
659 | ||
660 | context_alloc_fail: | |
661 | if (result != DC_OK) { | |
662 | dm_logger_write(core_dc->ctx->logger, LOG_WARNING, | |
663 | "%s:resource validation failed, dc_status:%d\n", | |
664 | __func__, | |
665 | result); | |
666 | } | |
667 | ||
668 | return (result == DC_OK); | |
669 | ||
670 | } | |
671 | ||
672 | bool dc_validate_guaranteed( | |
673 | const struct dc *dc, | |
ab2541b6 | 674 | const struct dc_stream *stream) |
4562236b HW |
675 | { |
676 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
677 | enum dc_status result = DC_ERROR_UNEXPECTED; | |
678 | struct validate_context *context; | |
679 | ||
680 | context = dm_alloc(sizeof(struct validate_context)); | |
681 | if (context == NULL) | |
682 | goto context_alloc_fail; | |
683 | ||
684 | result = core_dc->res_pool->funcs->validate_guaranteed( | |
ab2541b6 | 685 | core_dc, stream, context); |
4562236b HW |
686 | |
687 | resource_validate_ctx_destruct(context); | |
688 | dm_free(context); | |
689 | ||
690 | context_alloc_fail: | |
691 | if (result != DC_OK) { | |
692 | dm_logger_write(core_dc->ctx->logger, LOG_WARNING, | |
693 | "%s:guaranteed validation failed, dc_status:%d\n", | |
694 | __func__, | |
695 | result); | |
696 | } | |
697 | ||
698 | return (result == DC_OK); | |
699 | } | |
700 | ||
701 | static void program_timing_sync( | |
702 | struct core_dc *core_dc, | |
703 | struct validate_context *ctx) | |
704 | { | |
705 | int i, j; | |
706 | int group_index = 0; | |
707 | int pipe_count = ctx->res_ctx.pool->pipe_count; | |
708 | struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL }; | |
709 | ||
710 | for (i = 0; i < pipe_count; i++) { | |
711 | if (!ctx->res_ctx.pipe_ctx[i].stream || ctx->res_ctx.pipe_ctx[i].top_pipe) | |
712 | continue; | |
713 | ||
714 | unsynced_pipes[i] = &ctx->res_ctx.pipe_ctx[i]; | |
715 | } | |
716 | ||
717 | for (i = 0; i < pipe_count; i++) { | |
718 | int group_size = 1; | |
719 | struct pipe_ctx *pipe_set[MAX_PIPES]; | |
720 | ||
721 | if (!unsynced_pipes[i]) | |
722 | continue; | |
723 | ||
724 | pipe_set[0] = unsynced_pipes[i]; | |
725 | unsynced_pipes[i] = NULL; | |
726 | ||
727 | /* Add tg to the set, search rest of the tg's for ones with | |
728 | * same timing, add all tgs with same timing to the group | |
729 | */ | |
730 | for (j = i + 1; j < pipe_count; j++) { | |
731 | if (!unsynced_pipes[j]) | |
732 | continue; | |
733 | ||
734 | if (resource_are_streams_timing_synchronizable( | |
735 | unsynced_pipes[j]->stream, | |
736 | pipe_set[0]->stream)) { | |
737 | pipe_set[group_size] = unsynced_pipes[j]; | |
738 | unsynced_pipes[j] = NULL; | |
739 | group_size++; | |
740 | } | |
741 | } | |
742 | ||
743 | /* set first unblanked pipe as master */ | |
744 | for (j = 0; j < group_size; j++) { | |
745 | struct pipe_ctx *temp; | |
746 | ||
747 | if (!pipe_set[j]->tg->funcs->is_blanked(pipe_set[j]->tg)) { | |
748 | if (j == 0) | |
749 | break; | |
750 | ||
751 | temp = pipe_set[0]; | |
752 | pipe_set[0] = pipe_set[j]; | |
753 | pipe_set[j] = temp; | |
754 | break; | |
755 | } | |
756 | } | |
757 | ||
758 | /* remove any other unblanked pipes as they have already been synced */ | |
759 | for (j = j + 1; j < group_size; j++) { | |
760 | if (!pipe_set[j]->tg->funcs->is_blanked(pipe_set[j]->tg)) { | |
761 | group_size--; | |
762 | pipe_set[j] = pipe_set[group_size]; | |
763 | j--; | |
764 | } | |
765 | } | |
766 | ||
767 | if (group_size > 1) { | |
768 | core_dc->hwss.enable_timing_synchronization( | |
769 | core_dc, group_index, group_size, pipe_set); | |
770 | group_index++; | |
771 | } | |
772 | } | |
773 | } | |
774 | ||
ab2541b6 | 775 | static bool streams_changed( |
4562236b | 776 | struct core_dc *dc, |
ab2541b6 AC |
777 | const struct dc_stream *streams[], |
778 | uint8_t stream_count) | |
4562236b HW |
779 | { |
780 | uint8_t i; | |
781 | ||
ab2541b6 | 782 | if (stream_count != dc->current_context->stream_count) |
4562236b HW |
783 | return true; |
784 | ||
ab2541b6 AC |
785 | for (i = 0; i < dc->current_context->stream_count; i++) { |
786 | if (&dc->current_context->streams[i]->public != streams[i]) | |
4562236b HW |
787 | return true; |
788 | } | |
789 | ||
790 | return false; | |
791 | } | |
792 | ||
ab2541b6 | 793 | bool dc_commit_streams( |
4562236b | 794 | struct dc *dc, |
ab2541b6 AC |
795 | const struct dc_stream *streams[], |
796 | uint8_t stream_count) | |
4562236b HW |
797 | { |
798 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
799 | struct dc_bios *dcb = core_dc->ctx->dc_bios; | |
800 | enum dc_status result = DC_ERROR_UNEXPECTED; | |
801 | struct validate_context *context; | |
e72f0acd | 802 | struct dc_validation_set set[MAX_STREAMS] = { {0, {0} } }; |
f196f080 | 803 | int i, j; |
4562236b | 804 | |
ab2541b6 | 805 | if (false == streams_changed(core_dc, streams, stream_count)) |
4562236b HW |
806 | return DC_OK; |
807 | ||
ab2541b6 AC |
808 | dm_logger_write(core_dc->ctx->logger, LOG_DC, "%s: %d streams\n", |
809 | __func__, stream_count); | |
4562236b | 810 | |
ab2541b6 AC |
811 | for (i = 0; i < stream_count; i++) { |
812 | const struct dc_stream *stream = streams[i]; | |
f84a8161 TC |
813 | const struct dc_stream_status *status = dc_stream_get_status(stream); |
814 | int j; | |
4562236b | 815 | |
ab2541b6 | 816 | dc_stream_log(stream, |
4562236b HW |
817 | core_dc->ctx->logger, |
818 | LOG_DC); | |
819 | ||
ab2541b6 | 820 | set[i].stream = stream; |
f84a8161 TC |
821 | |
822 | if (status) { | |
823 | set[i].surface_count = status->surface_count; | |
824 | for (j = 0; j < status->surface_count; j++) | |
825 | set[i].surfaces[j] = status->surfaces[j]; | |
826 | } | |
4562236b HW |
827 | |
828 | } | |
829 | ||
830 | context = dm_alloc(sizeof(struct validate_context)); | |
831 | if (context == NULL) | |
832 | goto context_alloc_fail; | |
833 | ||
ab2541b6 | 834 | result = core_dc->res_pool->funcs->validate_with_context(core_dc, set, stream_count, context); |
4562236b HW |
835 | if (result != DC_OK){ |
836 | dm_logger_write(core_dc->ctx->logger, LOG_ERROR, | |
837 | "%s: Context validation failed! dc_status:%d\n", | |
838 | __func__, | |
839 | result); | |
840 | BREAK_TO_DEBUGGER(); | |
841 | resource_validate_ctx_destruct(context); | |
842 | goto fail; | |
843 | } | |
844 | ||
845 | if (!dcb->funcs->is_accelerated_mode(dcb)) { | |
846 | core_dc->hwss.enable_accelerated_mode(core_dc); | |
847 | } | |
848 | ||
849 | if (result == DC_OK) { | |
850 | result = core_dc->hwss.apply_ctx_to_hw(core_dc, context); | |
851 | } | |
852 | ||
853 | program_timing_sync(core_dc, context); | |
854 | ||
ab2541b6 AC |
855 | for (i = 0; i < context->stream_count; i++) { |
856 | const struct core_sink *sink = context->streams[i]->sink; | |
4562236b | 857 | |
ab2541b6 | 858 | for (j = 0; j < context->stream_status[i].surface_count; j++) { |
f196f080 YS |
859 | struct core_surface *surface = |
860 | DC_SURFACE_TO_CORE(context->stream_status[i].surfaces[j]); | |
4562236b | 861 | |
f196f080 | 862 | core_dc->hwss.apply_ctx_for_surface(core_dc, surface, context); |
4562236b HW |
863 | } |
864 | ||
865 | CONN_MSG_MODE(sink->link, "{%dx%d, %dx%d@%dKhz}", | |
ab2541b6 AC |
866 | context->streams[i]->public.timing.h_addressable, |
867 | context->streams[i]->public.timing.v_addressable, | |
868 | context->streams[i]->public.timing.h_total, | |
869 | context->streams[i]->public.timing.v_total, | |
870 | context->streams[i]->public.timing.pix_clk_khz); | |
4562236b HW |
871 | } |
872 | ||
4562236b | 873 | resource_validate_ctx_destruct(core_dc->current_context); |
6d9501e4 | 874 | dm_free(core_dc->current_context); |
4562236b | 875 | |
4562236b HW |
876 | core_dc->current_context = context; |
877 | ||
878 | return (result == DC_OK); | |
879 | ||
880 | fail: | |
881 | dm_free(context); | |
882 | ||
883 | context_alloc_fail: | |
884 | return (result == DC_OK); | |
885 | } | |
886 | ||
ab2541b6 | 887 | bool dc_pre_update_surfaces_to_stream( |
4562236b HW |
888 | struct dc *dc, |
889 | const struct dc_surface *const *new_surfaces, | |
890 | uint8_t new_surface_count, | |
ab2541b6 | 891 | const struct dc_stream *dc_stream) |
4562236b | 892 | { |
745cc746 | 893 | return true; |
4562236b HW |
894 | } |
895 | ||
ab2541b6 | 896 | bool dc_post_update_surfaces_to_stream(struct dc *dc) |
4562236b | 897 | { |
4562236b | 898 | int i; |
45209ef7 DL |
899 | struct core_dc *core_dc = DC_TO_CORE(dc); |
900 | struct validate_context *context = dm_alloc(sizeof(struct validate_context)); | |
901 | ||
902 | if (!context) { | |
903 | dm_error("%s: failed to create validate ctx\n", __func__); | |
904 | return false; | |
905 | } | |
906 | resource_validate_ctx_copy_construct(core_dc->current_context, context); | |
4562236b HW |
907 | |
908 | post_surface_trace(dc); | |
45209ef7 DL |
909 | for (i = 0; i < context->res_ctx.pool->pipe_count; i++) |
910 | if (context->res_ctx.pipe_ctx[i].stream == NULL) { | |
911 | context->res_ctx.pipe_ctx[i].pipe_idx = i; | |
4562236b | 912 | core_dc->hwss.power_down_front_end( |
45209ef7 | 913 | core_dc, &context->res_ctx.pipe_ctx[i]); |
bb9042da | 914 | } |
927f6eff | 915 | |
45209ef7 DL |
916 | if (!core_dc->res_pool->funcs->validate_bandwidth(core_dc, context)) { |
917 | BREAK_TO_DEBUGGER(); | |
918 | return false; | |
919 | } | |
4562236b | 920 | |
cf437593 | 921 | core_dc->hwss.set_bandwidth(core_dc, context, true); |
45209ef7 | 922 | |
927f6eff | 923 | resource_validate_ctx_copy_construct(context, core_dc->current_context); |
68339af3 | 924 | |
927f6eff HW |
925 | resource_validate_ctx_destruct(context); |
926 | dm_free(context); | |
4562236b HW |
927 | |
928 | return true; | |
929 | } | |
930 | ||
ab2541b6 | 931 | bool dc_commit_surfaces_to_stream( |
4562236b HW |
932 | struct dc *dc, |
933 | const struct dc_surface **new_surfaces, | |
934 | uint8_t new_surface_count, | |
ab2541b6 | 935 | const struct dc_stream *dc_stream) |
4562236b | 936 | { |
ab2541b6 AC |
937 | struct dc_surface_update updates[MAX_SURFACES]; |
938 | struct dc_flip_addrs flip_addr[MAX_SURFACES]; | |
939 | struct dc_plane_info plane_info[MAX_SURFACES]; | |
940 | struct dc_scaling_info scaling_info[MAX_SURFACES]; | |
4562236b HW |
941 | int i; |
942 | ||
ab2541b6 AC |
943 | memset(updates, 0, sizeof(updates)); |
944 | memset(flip_addr, 0, sizeof(flip_addr)); | |
945 | memset(plane_info, 0, sizeof(plane_info)); | |
946 | memset(scaling_info, 0, sizeof(scaling_info)); | |
947 | ||
4562236b HW |
948 | for (i = 0; i < new_surface_count; i++) { |
949 | updates[i].surface = new_surfaces[i]; | |
89e89630 AZ |
950 | updates[i].gamma = |
951 | (struct dc_gamma *)new_surfaces[i]->gamma_correction; | |
4562236b HW |
952 | flip_addr[i].address = new_surfaces[i]->address; |
953 | flip_addr[i].flip_immediate = new_surfaces[i]->flip_immediate; | |
954 | plane_info[i].color_space = new_surfaces[i]->color_space; | |
955 | plane_info[i].format = new_surfaces[i]->format; | |
956 | plane_info[i].plane_size = new_surfaces[i]->plane_size; | |
957 | plane_info[i].rotation = new_surfaces[i]->rotation; | |
958 | plane_info[i].horizontal_mirror = new_surfaces[i]->horizontal_mirror; | |
959 | plane_info[i].stereo_format = new_surfaces[i]->stereo_format; | |
960 | plane_info[i].tiling_info = new_surfaces[i]->tiling_info; | |
961 | plane_info[i].visible = new_surfaces[i]->visible; | |
5c1879b6 | 962 | plane_info[i].dcc = new_surfaces[i]->dcc; |
4562236b HW |
963 | scaling_info[i].scaling_quality = new_surfaces[i]->scaling_quality; |
964 | scaling_info[i].src_rect = new_surfaces[i]->src_rect; | |
965 | scaling_info[i].dst_rect = new_surfaces[i]->dst_rect; | |
966 | scaling_info[i].clip_rect = new_surfaces[i]->clip_rect; | |
967 | ||
968 | updates[i].flip_addr = &flip_addr[i]; | |
969 | updates[i].plane_info = &plane_info[i]; | |
970 | updates[i].scaling_info = &scaling_info[i]; | |
971 | } | |
ab2541b6 | 972 | dc_update_surfaces_for_stream(dc, updates, new_surface_count, dc_stream); |
4562236b | 973 | |
ab2541b6 | 974 | return dc_post_update_surfaces_to_stream(dc); |
4562236b HW |
975 | } |
976 | ||
e72f0acd TC |
977 | static bool is_surface_in_context( |
978 | const struct validate_context *context, | |
979 | const struct dc_surface *surface) | |
4562236b | 980 | { |
e72f0acd | 981 | int j; |
4562236b | 982 | |
e72f0acd TC |
983 | for (j = 0; j < context->res_ctx.pool->pipe_count; j++) { |
984 | const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; | |
4562236b | 985 | |
e72f0acd TC |
986 | if (surface == &pipe_ctx->surface->public) { |
987 | return true; | |
988 | } | |
989 | } | |
4562236b | 990 | |
e72f0acd TC |
991 | return false; |
992 | } | |
4562236b | 993 | |
5869b0f6 LE |
994 | static unsigned int pixel_format_to_bpp(enum surface_pixel_format format) |
995 | { | |
996 | switch (format) { | |
997 | case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: | |
998 | case SURFACE_PIXEL_FORMAT_GRPH_RGB565: | |
999 | return 16; | |
1000 | case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: | |
1001 | case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: | |
1002 | case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: | |
1003 | case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: | |
1004 | return 32; | |
1005 | case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: | |
1006 | case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: | |
1007 | case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: | |
1008 | return 64; | |
1009 | default: | |
1010 | ASSERT_CRITICAL(false); | |
1011 | return -1; | |
1012 | } | |
1013 | } | |
1014 | ||
1015 | static enum surface_update_type get_plane_info_update_type( | |
fb9611d2 YS |
1016 | const struct dc_surface_update *u, |
1017 | int surface_index) | |
5869b0f6 LE |
1018 | { |
1019 | struct dc_plane_info temp_plane_info = { { { { 0 } } } }; | |
1020 | ||
1021 | if (!u->plane_info) | |
1022 | return UPDATE_TYPE_FAST; | |
1023 | ||
1024 | /* Copy all parameters that will cause a full update | |
1025 | * from current surface, the rest of the parameters | |
1026 | * from provided plane configuration. | |
1027 | * Perform memory compare and special validation | |
1028 | * for those that can cause fast/medium updates | |
1029 | */ | |
1030 | ||
1031 | /* Full update parameters */ | |
1032 | temp_plane_info.color_space = u->surface->color_space; | |
1033 | temp_plane_info.dcc = u->surface->dcc; | |
1034 | temp_plane_info.horizontal_mirror = u->surface->horizontal_mirror; | |
1035 | temp_plane_info.plane_size = u->surface->plane_size; | |
1036 | temp_plane_info.rotation = u->surface->rotation; | |
1037 | temp_plane_info.stereo_format = u->surface->stereo_format; | |
1038 | temp_plane_info.tiling_info = u->surface->tiling_info; | |
5869b0f6 LE |
1039 | |
1040 | /* Special Validation parameters */ | |
1041 | temp_plane_info.format = u->plane_info->format; | |
fb9611d2 YS |
1042 | |
1043 | if (surface_index == 0) | |
1044 | temp_plane_info.visible = u->plane_info->visible; | |
1045 | else | |
1046 | temp_plane_info.visible = u->surface->visible; | |
5869b0f6 LE |
1047 | |
1048 | if (memcmp(u->plane_info, &temp_plane_info, | |
1049 | sizeof(struct dc_plane_info)) != 0) | |
1050 | return UPDATE_TYPE_FULL; | |
1051 | ||
1052 | if (pixel_format_to_bpp(u->plane_info->format) != | |
1053 | pixel_format_to_bpp(u->surface->format)) { | |
1054 | return UPDATE_TYPE_FULL; | |
1055 | } else { | |
1056 | return UPDATE_TYPE_MED; | |
1057 | } | |
1058 | } | |
1059 | ||
1060 | static enum surface_update_type get_scaling_info_update_type( | |
1061 | const struct dc_surface_update *u) | |
1062 | { | |
1063 | struct dc_scaling_info temp_scaling_info = { { 0 } }; | |
1064 | ||
1065 | if (!u->scaling_info) | |
1066 | return UPDATE_TYPE_FAST; | |
1067 | ||
1068 | /* Copy all parameters that will cause a full update | |
1069 | * from current surface, the rest of the parameters | |
1070 | * from provided plane configuration. | |
1071 | * Perform memory compare and special validation | |
1072 | * for those that can cause fast/medium updates | |
1073 | */ | |
1074 | ||
1075 | /* Full Update Parameters */ | |
1076 | temp_scaling_info.dst_rect = u->surface->dst_rect; | |
1077 | temp_scaling_info.src_rect = u->surface->src_rect; | |
1078 | temp_scaling_info.scaling_quality = u->surface->scaling_quality; | |
1079 | ||
1080 | /* Special validation required */ | |
1081 | temp_scaling_info.clip_rect = u->scaling_info->clip_rect; | |
1082 | ||
1083 | if (memcmp(u->scaling_info, &temp_scaling_info, | |
1084 | sizeof(struct dc_scaling_info)) != 0) | |
1085 | return UPDATE_TYPE_FULL; | |
1086 | ||
1087 | /* Check Clip rectangles if not equal | |
1088 | * difference is in offsets == > UPDATE_TYPE_FAST | |
1089 | * difference is in dimensions == > UPDATE_TYPE_FULL | |
1090 | */ | |
1091 | if (memcmp(&u->scaling_info->clip_rect, | |
1092 | &u->surface->clip_rect, sizeof(struct rect)) != 0) { | |
1093 | if ((u->scaling_info->clip_rect.height == | |
1094 | u->surface->clip_rect.height) && | |
1095 | (u->scaling_info->clip_rect.width == | |
1096 | u->surface->clip_rect.width)) { | |
1097 | return UPDATE_TYPE_FAST; | |
1098 | } else { | |
1099 | return UPDATE_TYPE_FULL; | |
1100 | } | |
1101 | } | |
1102 | ||
1103 | return UPDATE_TYPE_FAST; | |
1104 | } | |
4562236b | 1105 | |
e72f0acd TC |
1106 | static enum surface_update_type det_surface_update( |
1107 | const struct core_dc *dc, | |
fb9611d2 YS |
1108 | const struct dc_surface_update *u, |
1109 | int surface_index) | |
e72f0acd TC |
1110 | { |
1111 | const struct validate_context *context = dc->current_context; | |
5869b0f6 LE |
1112 | enum surface_update_type type = UPDATE_TYPE_FAST; |
1113 | enum surface_update_type overall_type = UPDATE_TYPE_FAST; | |
4562236b | 1114 | |
e72f0acd TC |
1115 | if (!is_surface_in_context(context, u->surface)) |
1116 | return UPDATE_TYPE_FULL; | |
4562236b | 1117 | |
fb9611d2 | 1118 | type = get_plane_info_update_type(u, surface_index); |
5869b0f6 LE |
1119 | if (overall_type < type) |
1120 | overall_type = type; | |
1121 | ||
1122 | type = get_scaling_info_update_type(u); | |
1123 | if (overall_type < type) | |
1124 | overall_type = type; | |
1125 | ||
e72f0acd TC |
1126 | if (u->in_transfer_func || |
1127 | u->out_transfer_func || | |
5869b0f6 LE |
1128 | u->hdr_static_metadata) { |
1129 | if (overall_type < UPDATE_TYPE_MED) | |
1130 | overall_type = UPDATE_TYPE_MED; | |
1131 | } | |
1c4e6bce | 1132 | |
5869b0f6 | 1133 | return overall_type; |
e72f0acd | 1134 | } |
4562236b | 1135 | |
5869b0f6 LE |
1136 | enum surface_update_type dc_check_update_surfaces_for_stream( |
1137 | struct dc *dc, | |
e72f0acd TC |
1138 | struct dc_surface_update *updates, |
1139 | int surface_count, | |
ee8f63e1 | 1140 | struct dc_stream_update *stream_update, |
e72f0acd TC |
1141 | const struct dc_stream_status *stream_status) |
1142 | { | |
5869b0f6 | 1143 | struct core_dc *core_dc = DC_TO_CORE(dc); |
e72f0acd TC |
1144 | int i; |
1145 | enum surface_update_type overall_type = UPDATE_TYPE_FAST; | |
1146 | ||
1ce71fcd | 1147 | if (stream_status == NULL || stream_status->surface_count != surface_count) |
e72f0acd TC |
1148 | return UPDATE_TYPE_FULL; |
1149 | ||
ee8f63e1 LE |
1150 | if (stream_update) |
1151 | return UPDATE_TYPE_FULL; | |
1152 | ||
e72f0acd TC |
1153 | for (i = 0 ; i < surface_count; i++) { |
1154 | enum surface_update_type type = | |
fb9611d2 | 1155 | det_surface_update(core_dc, &updates[i], i); |
e72f0acd TC |
1156 | |
1157 | if (type == UPDATE_TYPE_FULL) | |
1158 | return type; | |
1c4e6bce | 1159 | |
e72f0acd TC |
1160 | if (overall_type < type) |
1161 | overall_type = type; | |
4562236b HW |
1162 | } |
1163 | ||
e72f0acd TC |
1164 | return overall_type; |
1165 | } | |
4562236b | 1166 | |
ee8f63e1 | 1167 | void dc_update_surfaces_for_stream(struct dc *dc, |
a783e7b5 | 1168 | struct dc_surface_update *surface_updates, int surface_count, |
ee8f63e1 | 1169 | const struct dc_stream *dc_stream) |
a783e7b5 | 1170 | { |
ee8f63e1 LE |
1171 | dc_update_surfaces_and_stream(dc, surface_updates, surface_count, |
1172 | dc_stream, NULL); | |
a783e7b5 LE |
1173 | } |
1174 | ||
e72f0acd | 1175 | enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL; |
4562236b | 1176 | |
ee8f63e1 LE |
1177 | void dc_update_surfaces_and_stream(struct dc *dc, |
1178 | struct dc_surface_update *srf_updates, int surface_count, | |
1179 | const struct dc_stream *dc_stream, | |
1180 | struct dc_stream_update *stream_update) | |
e72f0acd TC |
1181 | { |
1182 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
1183 | struct validate_context *context; | |
1184 | int i, j; | |
e72f0acd TC |
1185 | enum surface_update_type update_type; |
1186 | const struct dc_stream_status *stream_status; | |
ee8f63e1 | 1187 | struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); |
e72f0acd TC |
1188 | |
1189 | stream_status = dc_stream_get_status(dc_stream); | |
1190 | ASSERT(stream_status); | |
1191 | if (!stream_status) | |
1192 | return; /* Cannot commit surface to stream that is not committed */ | |
1193 | ||
5869b0f6 | 1194 | update_type = dc_check_update_surfaces_for_stream( |
ee8f63e1 | 1195 | dc, srf_updates, surface_count, stream_update, stream_status); |
4562236b | 1196 | |
e72f0acd | 1197 | if (update_type >= update_surface_trace_level) |
ee8f63e1 | 1198 | update_surface_trace(dc, srf_updates, surface_count); |
e72f0acd TC |
1199 | |
1200 | if (update_type >= UPDATE_TYPE_FULL) { | |
1201 | const struct dc_surface *new_surfaces[MAX_SURFACES] = { 0 }; | |
1202 | ||
1203 | for (i = 0; i < surface_count; i++) | |
ee8f63e1 | 1204 | new_surfaces[i] = srf_updates[i].surface; |
e72f0acd TC |
1205 | |
1206 | /* initialize scratch memory for building context */ | |
6d9501e4 | 1207 | context = dm_alloc(sizeof(*context)); |
e72f0acd TC |
1208 | resource_validate_ctx_copy_construct( |
1209 | core_dc->current_context, context); | |
1210 | ||
1211 | /* add surface to context */ | |
4562236b | 1212 | if (!resource_attach_surfaces_to_context( |
ab2541b6 | 1213 | new_surfaces, surface_count, dc_stream, context)) { |
4562236b | 1214 | BREAK_TO_DEBUGGER(); |
6d9501e4 | 1215 | goto fail; |
4562236b | 1216 | } |
e72f0acd TC |
1217 | } else { |
1218 | context = core_dc->current_context; | |
4562236b | 1219 | } |
ee8f63e1 LE |
1220 | |
1221 | /* update current stream with the new updates */ | |
1222 | if (stream_update) { | |
1223 | stream->public.src = stream_update->src; | |
1224 | stream->public.dst = stream_update->dst; | |
1225 | } | |
1226 | ||
1227 | /* save update parameters into surface */ | |
4562236b | 1228 | for (i = 0; i < surface_count; i++) { |
ee8f63e1 LE |
1229 | struct core_surface *surface = |
1230 | DC_SURFACE_TO_CORE(srf_updates[i].surface); | |
4562236b | 1231 | |
ee8f63e1 LE |
1232 | if (srf_updates[i].flip_addr) { |
1233 | surface->public.address = srf_updates[i].flip_addr->address; | |
e72f0acd | 1234 | surface->public.flip_immediate = |
ee8f63e1 | 1235 | srf_updates[i].flip_addr->flip_immediate; |
e72f0acd TC |
1236 | } |
1237 | ||
ee8f63e1 | 1238 | if (srf_updates[i].scaling_info) { |
e72f0acd | 1239 | surface->public.scaling_quality = |
ee8f63e1 | 1240 | srf_updates[i].scaling_info->scaling_quality; |
e72f0acd | 1241 | surface->public.dst_rect = |
ee8f63e1 | 1242 | srf_updates[i].scaling_info->dst_rect; |
e72f0acd | 1243 | surface->public.src_rect = |
ee8f63e1 | 1244 | srf_updates[i].scaling_info->src_rect; |
e72f0acd | 1245 | surface->public.clip_rect = |
ee8f63e1 | 1246 | srf_updates[i].scaling_info->clip_rect; |
e72f0acd TC |
1247 | } |
1248 | ||
ee8f63e1 | 1249 | if (srf_updates[i].plane_info) { |
e72f0acd | 1250 | surface->public.color_space = |
ee8f63e1 | 1251 | srf_updates[i].plane_info->color_space; |
e72f0acd | 1252 | surface->public.format = |
ee8f63e1 | 1253 | srf_updates[i].plane_info->format; |
e72f0acd | 1254 | surface->public.plane_size = |
ee8f63e1 | 1255 | srf_updates[i].plane_info->plane_size; |
e72f0acd | 1256 | surface->public.rotation = |
ee8f63e1 | 1257 | srf_updates[i].plane_info->rotation; |
e72f0acd | 1258 | surface->public.horizontal_mirror = |
ee8f63e1 | 1259 | srf_updates[i].plane_info->horizontal_mirror; |
e72f0acd | 1260 | surface->public.stereo_format = |
ee8f63e1 | 1261 | srf_updates[i].plane_info->stereo_format; |
e72f0acd | 1262 | surface->public.tiling_info = |
ee8f63e1 | 1263 | srf_updates[i].plane_info->tiling_info; |
e72f0acd | 1264 | surface->public.visible = |
ee8f63e1 | 1265 | srf_updates[i].plane_info->visible; |
e72f0acd | 1266 | surface->public.dcc = |
ee8f63e1 | 1267 | srf_updates[i].plane_info->dcc; |
e72f0acd TC |
1268 | } |
1269 | ||
1270 | /* not sure if we still need this */ | |
ed151940 YS |
1271 | if (update_type == UPDATE_TYPE_FULL) { |
1272 | for (j = 0; j < context->res_ctx.pool->pipe_count; j++) { | |
1273 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; | |
4562236b | 1274 | |
ed151940 YS |
1275 | if (pipe_ctx->surface != surface) |
1276 | continue; | |
4562236b | 1277 | |
b2d0a103 | 1278 | resource_build_scaling_params(pipe_ctx); |
4562236b | 1279 | } |
e72f0acd | 1280 | } |
89e89630 | 1281 | |
ee8f63e1 LE |
1282 | if (srf_updates[i].gamma && |
1283 | srf_updates[i].gamma != surface->public.gamma_correction) { | |
e72f0acd TC |
1284 | if (surface->public.gamma_correction != NULL) |
1285 | dc_gamma_release(&surface->public. | |
1286 | gamma_correction); | |
89e89630 | 1287 | |
ee8f63e1 | 1288 | dc_gamma_retain(srf_updates[i].gamma); |
e72f0acd | 1289 | surface->public.gamma_correction = |
ee8f63e1 | 1290 | srf_updates[i].gamma; |
e72f0acd | 1291 | } |
fb735a9f | 1292 | |
ee8f63e1 LE |
1293 | if (srf_updates[i].in_transfer_func && |
1294 | srf_updates[i].in_transfer_func != surface->public.in_transfer_func) { | |
e72f0acd TC |
1295 | if (surface->public.in_transfer_func != NULL) |
1296 | dc_transfer_func_release( | |
1297 | surface->public. | |
1298 | in_transfer_func); | |
1299 | ||
1300 | dc_transfer_func_retain( | |
ee8f63e1 | 1301 | srf_updates[i].in_transfer_func); |
e72f0acd | 1302 | surface->public.in_transfer_func = |
ee8f63e1 | 1303 | srf_updates[i].in_transfer_func; |
e72f0acd | 1304 | } |
fb735a9f | 1305 | |
ee8f63e1 LE |
1306 | if (srf_updates[i].out_transfer_func && |
1307 | srf_updates[i].out_transfer_func != dc_stream->out_transfer_func) { | |
e72f0acd TC |
1308 | if (dc_stream->out_transfer_func != NULL) |
1309 | dc_transfer_func_release(dc_stream->out_transfer_func); | |
ee8f63e1 LE |
1310 | dc_transfer_func_retain(srf_updates[i].out_transfer_func); |
1311 | stream->public.out_transfer_func = srf_updates[i].out_transfer_func; | |
4562236b | 1312 | } |
ee8f63e1 | 1313 | if (srf_updates[i].hdr_static_metadata) |
e72f0acd | 1314 | surface->public.hdr_static_ctx = |
ee8f63e1 | 1315 | *(srf_updates[i].hdr_static_metadata); |
4562236b HW |
1316 | } |
1317 | ||
745cc746 DL |
1318 | if (update_type == UPDATE_TYPE_FULL) { |
1319 | if (!core_dc->res_pool->funcs->validate_bandwidth(core_dc, context)) { | |
1320 | BREAK_TO_DEBUGGER(); | |
6d9501e4 | 1321 | goto fail; |
745cc746 DL |
1322 | } else |
1323 | core_dc->hwss.set_bandwidth(core_dc, context, false); | |
45209ef7 | 1324 | } |
e72f0acd TC |
1325 | |
1326 | if (!surface_count) /* reset */ | |
1327 | core_dc->hwss.apply_ctx_for_surface(core_dc, NULL, context); | |
1328 | ||
00f02019 | 1329 | /* Lock pipes for provided surfaces */ |
4562236b | 1330 | for (i = 0; i < surface_count; i++) { |
ee8f63e1 | 1331 | struct core_surface *surface = DC_SURFACE_TO_CORE(srf_updates[i].surface); |
4562236b | 1332 | |
f0828115 CL |
1333 | for (j = 0; j < context->res_ctx.pool->pipe_count; j++) { |
1334 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; | |
92a65e32 | 1335 | |
f0828115 CL |
1336 | if (pipe_ctx->surface != surface) |
1337 | continue; | |
d98e5cc2 | 1338 | if (!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) { |
f0828115 CL |
1339 | core_dc->hwss.pipe_control_lock( |
1340 | core_dc, | |
1341 | pipe_ctx, | |
e72f0acd TC |
1342 | true); |
1343 | } | |
00f02019 LE |
1344 | } |
1345 | } | |
1346 | ||
1347 | /* Perform requested Updates */ | |
1348 | for (i = 0; i < surface_count; i++) { | |
1349 | struct core_surface *surface = DC_SURFACE_TO_CORE(srf_updates[i].surface); | |
1350 | ||
1351 | if (update_type >= UPDATE_TYPE_MED) { | |
1352 | core_dc->hwss.apply_ctx_for_surface( | |
1353 | core_dc, surface, context); | |
1354 | context_timing_trace(dc, &context->res_ctx); | |
1355 | } | |
1356 | ||
1357 | for (j = 0; j < context->res_ctx.pool->pipe_count; j++) { | |
1358 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; | |
1359 | struct pipe_ctx *cur_pipe_ctx; | |
1360 | bool is_new_pipe_surface = true; | |
1361 | ||
1362 | if (pipe_ctx->surface != surface) | |
1363 | continue; | |
4562236b | 1364 | |
ee8f63e1 | 1365 | if (srf_updates[i].flip_addr) |
e72f0acd | 1366 | core_dc->hwss.update_plane_addr(core_dc, pipe_ctx); |
4562236b | 1367 | |
e72f0acd TC |
1368 | if (update_type == UPDATE_TYPE_FAST) |
1369 | continue; | |
1370 | ||
1371 | cur_pipe_ctx = &core_dc->current_context->res_ctx.pipe_ctx[j]; | |
1372 | if (cur_pipe_ctx->surface == pipe_ctx->surface) | |
1373 | is_new_pipe_surface = false; | |
1374 | ||
e72f0acd | 1375 | if (is_new_pipe_surface || |
ee8f63e1 | 1376 | srf_updates[i].in_transfer_func) |
90e508ba AK |
1377 | core_dc->hwss.set_input_transfer_func( |
1378 | pipe_ctx, pipe_ctx->surface); | |
1379 | ||
e72f0acd | 1380 | if (is_new_pipe_surface || |
ee8f63e1 | 1381 | srf_updates[i].out_transfer_func) |
90e508ba AK |
1382 | core_dc->hwss.set_output_transfer_func( |
1383 | pipe_ctx, | |
1384 | pipe_ctx->surface, | |
1385 | pipe_ctx->stream); | |
1386 | ||
ee8f63e1 | 1387 | if (srf_updates[i].hdr_static_metadata) { |
fcd2f4bf AZ |
1388 | resource_build_info_frame(pipe_ctx); |
1389 | core_dc->hwss.update_info_frame(pipe_ctx); | |
1390 | } | |
9474980a | 1391 | } |
4562236b HW |
1392 | } |
1393 | ||
00f02019 | 1394 | /* Unlock pipes */ |
4562236b HW |
1395 | for (i = context->res_ctx.pool->pipe_count - 1; i >= 0; i--) { |
1396 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; | |
1397 | ||
1398 | for (j = 0; j < surface_count; j++) { | |
ee8f63e1 | 1399 | if (srf_updates[j].surface == &pipe_ctx->surface->public) { |
4562236b HW |
1400 | if (!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) { |
1401 | core_dc->hwss.pipe_control_lock( | |
f0828115 CL |
1402 | core_dc, |
1403 | pipe_ctx, | |
4562236b HW |
1404 | false); |
1405 | } | |
1406 | break; | |
1407 | } | |
1408 | } | |
1409 | } | |
1410 | ||
e72f0acd TC |
1411 | if (core_dc->current_context != context) { |
1412 | resource_validate_ctx_destruct(core_dc->current_context); | |
6d9501e4 | 1413 | dm_free(core_dc->current_context); |
e72f0acd TC |
1414 | |
1415 | core_dc->current_context = context; | |
1416 | } | |
6d9501e4 HW |
1417 | return; |
1418 | ||
1419 | fail: | |
1420 | if (core_dc->current_context != context) { | |
1421 | resource_validate_ctx_destruct(context); | |
1422 | dm_free(context); | |
1423 | } | |
4562236b HW |
1424 | } |
1425 | ||
ab2541b6 | 1426 | uint8_t dc_get_current_stream_count(const struct dc *dc) |
4562236b HW |
1427 | { |
1428 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
ab2541b6 | 1429 | return core_dc->current_context->stream_count; |
4562236b HW |
1430 | } |
1431 | ||
ab2541b6 | 1432 | struct dc_stream *dc_get_stream_at_index(const struct dc *dc, uint8_t i) |
4562236b HW |
1433 | { |
1434 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
ab2541b6 AC |
1435 | if (i < core_dc->current_context->stream_count) |
1436 | return &(core_dc->current_context->streams[i]->public); | |
4562236b HW |
1437 | return NULL; |
1438 | } | |
1439 | ||
1440 | const struct dc_link *dc_get_link_at_index(const struct dc *dc, uint32_t link_index) | |
1441 | { | |
1442 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
1443 | return &core_dc->links[link_index]->public; | |
1444 | } | |
1445 | ||
1446 | const struct graphics_object_id dc_get_link_id_at_index( | |
1447 | struct dc *dc, uint32_t link_index) | |
1448 | { | |
1449 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
1450 | return core_dc->links[link_index]->link_id; | |
1451 | } | |
1452 | ||
1453 | const struct ddc_service *dc_get_ddc_at_index( | |
1454 | struct dc *dc, uint32_t link_index) | |
1455 | { | |
1456 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
1457 | return core_dc->links[link_index]->ddc; | |
1458 | } | |
1459 | ||
1460 | enum dc_irq_source dc_get_hpd_irq_source_at_index( | |
1461 | struct dc *dc, uint32_t link_index) | |
1462 | { | |
1463 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
1464 | return core_dc->links[link_index]->public.irq_source_hpd; | |
1465 | } | |
1466 | ||
1467 | const struct audio **dc_get_audios(struct dc *dc) | |
1468 | { | |
1469 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
1470 | return (const struct audio **)core_dc->res_pool->audios; | |
1471 | } | |
1472 | ||
1473 | void dc_flip_surface_addrs( | |
1474 | struct dc *dc, | |
1475 | const struct dc_surface *const surfaces[], | |
1476 | struct dc_flip_addrs flip_addrs[], | |
1477 | uint32_t count) | |
1478 | { | |
1479 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
1480 | int i, j; | |
1481 | ||
1482 | for (i = 0; i < count; i++) { | |
1483 | struct core_surface *surface = DC_SURFACE_TO_CORE(surfaces[i]); | |
1484 | ||
1485 | surface->public.address = flip_addrs[i].address; | |
1486 | surface->public.flip_immediate = flip_addrs[i].flip_immediate; | |
1487 | ||
1488 | for (j = 0; j < core_dc->res_pool->pipe_count; j++) { | |
1489 | struct pipe_ctx *pipe_ctx = &core_dc->current_context->res_ctx.pipe_ctx[j]; | |
1490 | ||
1491 | if (pipe_ctx->surface != surface) | |
1492 | continue; | |
1493 | ||
1494 | core_dc->hwss.update_plane_addr(core_dc, pipe_ctx); | |
1495 | } | |
1496 | } | |
1497 | } | |
1498 | ||
1499 | enum dc_irq_source dc_interrupt_to_irq_source( | |
1500 | struct dc *dc, | |
1501 | uint32_t src_id, | |
1502 | uint32_t ext_id) | |
1503 | { | |
1504 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
1505 | return dal_irq_service_to_irq_source(core_dc->res_pool->irqs, src_id, ext_id); | |
1506 | } | |
1507 | ||
1508 | void dc_interrupt_set(const struct dc *dc, enum dc_irq_source src, bool enable) | |
1509 | { | |
1510 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
1511 | dal_irq_service_set(core_dc->res_pool->irqs, src, enable); | |
1512 | } | |
1513 | ||
1514 | void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src) | |
1515 | { | |
1516 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
1517 | dal_irq_service_ack(core_dc->res_pool->irqs, src); | |
1518 | } | |
1519 | ||
1520 | void dc_set_power_state( | |
1521 | struct dc *dc, | |
a3621485 | 1522 | enum dc_acpi_cm_power_state power_state) |
4562236b HW |
1523 | { |
1524 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
1525 | ||
4562236b HW |
1526 | switch (power_state) { |
1527 | case DC_ACPI_CM_POWER_STATE_D0: | |
1528 | core_dc->hwss.init_hw(core_dc); | |
1529 | break; | |
1530 | default: | |
4562236b HW |
1531 | |
1532 | core_dc->hwss.power_down(core_dc); | |
1533 | ||
1534 | /* Zero out the current context so that on resume we start with | |
1535 | * clean state, and dc hw programming optimizations will not | |
1536 | * cause any trouble. | |
1537 | */ | |
1538 | memset(core_dc->current_context, 0, | |
1539 | sizeof(*core_dc->current_context)); | |
1540 | ||
1541 | core_dc->current_context->res_ctx.pool = core_dc->res_pool; | |
1542 | ||
1543 | break; | |
1544 | } | |
1545 | ||
1546 | } | |
1547 | ||
1548 | void dc_resume(const struct dc *dc) | |
1549 | { | |
1550 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
1551 | ||
1552 | uint32_t i; | |
1553 | ||
1554 | for (i = 0; i < core_dc->link_count; i++) | |
1555 | core_link_resume(core_dc->links[i]); | |
1556 | } | |
1557 | ||
7c7f5b15 | 1558 | bool dc_read_aux_dpcd( |
4562236b HW |
1559 | struct dc *dc, |
1560 | uint32_t link_index, | |
1561 | uint32_t address, | |
1562 | uint8_t *data, | |
1563 | uint32_t size) | |
1564 | { | |
1565 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
1566 | ||
1567 | struct core_link *link = core_dc->links[link_index]; | |
1568 | enum ddc_result r = dal_ddc_service_read_dpcd_data( | |
1569 | link->ddc, | |
7c7f5b15 AG |
1570 | false, |
1571 | I2C_MOT_UNDEF, | |
4562236b HW |
1572 | address, |
1573 | data, | |
1574 | size); | |
1575 | return r == DDC_RESULT_SUCESSFULL; | |
1576 | } | |
1577 | ||
7c7f5b15 | 1578 | bool dc_write_aux_dpcd( |
2b230ea3 ZF |
1579 | struct dc *dc, |
1580 | uint32_t link_index, | |
1581 | uint32_t address, | |
7c7f5b15 AG |
1582 | const uint8_t *data, |
1583 | uint32_t size) | |
1584 | { | |
2b230ea3 | 1585 | struct core_dc *core_dc = DC_TO_CORE(dc); |
2b230ea3 ZF |
1586 | struct core_link *link = core_dc->links[link_index]; |
1587 | ||
7c7f5b15 | 1588 | enum ddc_result r = dal_ddc_service_write_dpcd_data( |
2b230ea3 | 1589 | link->ddc, |
7c7f5b15 AG |
1590 | false, |
1591 | I2C_MOT_UNDEF, | |
2b230ea3 | 1592 | address, |
7c7f5b15 AG |
1593 | data, |
1594 | size); | |
1595 | return r == DDC_RESULT_SUCESSFULL; | |
2b230ea3 ZF |
1596 | } |
1597 | ||
7c7f5b15 AG |
1598 | bool dc_read_aux_i2c( |
1599 | struct dc *dc, | |
1600 | uint32_t link_index, | |
1601 | enum i2c_mot_mode mot, | |
1602 | uint32_t address, | |
1603 | uint8_t *data, | |
1604 | uint32_t size) | |
1605 | { | |
1606 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
2b230ea3 | 1607 | |
7c7f5b15 AG |
1608 | struct core_link *link = core_dc->links[link_index]; |
1609 | enum ddc_result r = dal_ddc_service_read_dpcd_data( | |
1610 | link->ddc, | |
1611 | true, | |
1612 | mot, | |
1613 | address, | |
1614 | data, | |
1615 | size); | |
1616 | return r == DDC_RESULT_SUCESSFULL; | |
1617 | } | |
1618 | ||
1619 | bool dc_write_aux_i2c( | |
4562236b HW |
1620 | struct dc *dc, |
1621 | uint32_t link_index, | |
7c7f5b15 | 1622 | enum i2c_mot_mode mot, |
4562236b HW |
1623 | uint32_t address, |
1624 | const uint8_t *data, | |
1625 | uint32_t size) | |
1626 | { | |
1627 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
4562236b HW |
1628 | struct core_link *link = core_dc->links[link_index]; |
1629 | ||
1630 | enum ddc_result r = dal_ddc_service_write_dpcd_data( | |
1631 | link->ddc, | |
7c7f5b15 AG |
1632 | true, |
1633 | mot, | |
4562236b HW |
1634 | address, |
1635 | data, | |
1636 | size); | |
1637 | return r == DDC_RESULT_SUCESSFULL; | |
1638 | } | |
1639 | ||
7c7f5b15 AG |
1640 | bool dc_query_ddc_data( |
1641 | struct dc *dc, | |
1642 | uint32_t link_index, | |
1643 | uint32_t address, | |
1644 | uint8_t *write_buf, | |
1645 | uint32_t write_size, | |
1646 | uint8_t *read_buf, | |
1647 | uint32_t read_size) { | |
1648 | ||
1649 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
1650 | ||
1651 | struct core_link *link = core_dc->links[link_index]; | |
1652 | ||
1653 | bool result = dal_ddc_service_query_ddc_data( | |
1654 | link->ddc, | |
1655 | address, | |
1656 | write_buf, | |
1657 | write_size, | |
1658 | read_buf, | |
1659 | read_size); | |
1660 | ||
1661 | return result; | |
1662 | } | |
1663 | ||
4562236b HW |
1664 | bool dc_submit_i2c( |
1665 | struct dc *dc, | |
1666 | uint32_t link_index, | |
1667 | struct i2c_command *cmd) | |
1668 | { | |
1669 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
1670 | ||
1671 | struct core_link *link = core_dc->links[link_index]; | |
1672 | struct ddc_service *ddc = link->ddc; | |
1673 | ||
1674 | return dal_i2caux_submit_i2c_command( | |
1675 | ddc->ctx->i2caux, | |
1676 | ddc->ddc_pin, | |
1677 | cmd); | |
1678 | } | |
1679 | ||
1680 | static bool link_add_remote_sink_helper(struct core_link *core_link, struct dc_sink *sink) | |
1681 | { | |
1682 | struct dc_link *dc_link = &core_link->public; | |
1683 | ||
1684 | if (dc_link->sink_count >= MAX_SINKS_PER_LINK) { | |
1685 | BREAK_TO_DEBUGGER(); | |
1686 | return false; | |
1687 | } | |
1688 | ||
1689 | dc_sink_retain(sink); | |
1690 | ||
1691 | dc_link->remote_sinks[dc_link->sink_count] = sink; | |
1692 | dc_link->sink_count++; | |
1693 | ||
1694 | return true; | |
1695 | } | |
1696 | ||
1697 | struct dc_sink *dc_link_add_remote_sink( | |
1698 | const struct dc_link *link, | |
1699 | const uint8_t *edid, | |
1700 | int len, | |
1701 | struct dc_sink_init_data *init_data) | |
1702 | { | |
1703 | struct dc_sink *dc_sink; | |
1704 | enum dc_edid_status edid_status; | |
1705 | struct core_link *core_link = DC_LINK_TO_LINK(link); | |
1706 | ||
1707 | if (len > MAX_EDID_BUFFER_SIZE) { | |
1708 | dm_error("Max EDID buffer size breached!\n"); | |
1709 | return NULL; | |
1710 | } | |
1711 | ||
1712 | if (!init_data) { | |
1713 | BREAK_TO_DEBUGGER(); | |
1714 | return NULL; | |
1715 | } | |
1716 | ||
1717 | if (!init_data->link) { | |
1718 | BREAK_TO_DEBUGGER(); | |
1719 | return NULL; | |
1720 | } | |
1721 | ||
1722 | dc_sink = dc_sink_create(init_data); | |
1723 | ||
1724 | if (!dc_sink) | |
1725 | return NULL; | |
1726 | ||
1727 | memmove(dc_sink->dc_edid.raw_edid, edid, len); | |
1728 | dc_sink->dc_edid.length = len; | |
1729 | ||
1730 | if (!link_add_remote_sink_helper( | |
1731 | core_link, | |
1732 | dc_sink)) | |
1733 | goto fail_add_sink; | |
1734 | ||
1735 | edid_status = dm_helpers_parse_edid_caps( | |
1736 | core_link->ctx, | |
1737 | &dc_sink->dc_edid, | |
1738 | &dc_sink->edid_caps); | |
1739 | ||
1740 | if (edid_status != EDID_OK) | |
1741 | goto fail; | |
1742 | ||
1743 | return dc_sink; | |
1744 | fail: | |
1745 | dc_link_remove_remote_sink(link, dc_sink); | |
1746 | fail_add_sink: | |
1747 | dc_sink_release(dc_sink); | |
1748 | return NULL; | |
1749 | } | |
1750 | ||
1751 | void dc_link_set_sink(const struct dc_link *link, struct dc_sink *sink) | |
1752 | { | |
1753 | struct core_link *core_link = DC_LINK_TO_LINK(link); | |
1754 | struct dc_link *dc_link = &core_link->public; | |
1755 | ||
1756 | dc_link->local_sink = sink; | |
1757 | ||
1758 | if (sink == NULL) { | |
1759 | dc_link->type = dc_connection_none; | |
1760 | } else { | |
1761 | dc_link->type = dc_connection_single; | |
1762 | } | |
1763 | } | |
1764 | ||
1765 | void dc_link_remove_remote_sink(const struct dc_link *link, const struct dc_sink *sink) | |
1766 | { | |
1767 | int i; | |
1768 | struct core_link *core_link = DC_LINK_TO_LINK(link); | |
1769 | struct dc_link *dc_link = &core_link->public; | |
1770 | ||
1771 | if (!link->sink_count) { | |
1772 | BREAK_TO_DEBUGGER(); | |
1773 | return; | |
1774 | } | |
1775 | ||
1776 | for (i = 0; i < dc_link->sink_count; i++) { | |
1777 | if (dc_link->remote_sinks[i] == sink) { | |
1778 | dc_sink_release(sink); | |
1779 | dc_link->remote_sinks[i] = NULL; | |
1780 | ||
1781 | /* shrink array to remove empty place */ | |
1782 | while (i < dc_link->sink_count - 1) { | |
1783 | dc_link->remote_sinks[i] = dc_link->remote_sinks[i+1]; | |
1784 | i++; | |
1785 | } | |
b64875fe | 1786 | dc_link->remote_sinks[i] = NULL; |
4562236b HW |
1787 | dc_link->sink_count--; |
1788 | return; | |
1789 | } | |
1790 | } | |
1791 | } | |
1792 | ||
2c8ad2d5 AD |
1793 | bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data) |
1794 | { | |
1795 | int i; | |
1796 | struct core_dc *core_dc = DC_TO_CORE(dc); | |
1797 | struct mem_input *mi = NULL; | |
1798 | ||
1799 | for (i = 0; i < core_dc->res_pool->pipe_count; i++) { | |
1800 | if (core_dc->res_pool->mis[i] != NULL) { | |
1801 | mi = core_dc->res_pool->mis[i]; | |
1802 | break; | |
1803 | } | |
1804 | } | |
1805 | if (mi == NULL) { | |
1806 | dm_error("no mem_input!\n"); | |
1807 | return false; | |
1808 | } | |
1809 | ||
1810 | if (mi->funcs->mem_input_update_dchub) | |
1811 | mi->funcs->mem_input_update_dchub(mi, dh_data); | |
1812 | else | |
1813 | ASSERT(mi->funcs->mem_input_update_dchub); | |
1814 | ||
1815 | ||
1816 | return true; | |
1817 | ||
1818 | } | |
2c8ad2d5 | 1819 |