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drm/amd/display: Filter out YCbCr420 timing if VSC SDP not supported
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / display / dc / core / dc_resource.c
CommitLineData
4562236b 1/*
9ce6aae1 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4562236b
HW		 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
4fc4dca8
SR		 25
26#include <linux/slab.h>
27
4562236b
HW		 28#include "dm_services.h"
29
30#include "resource.h"
31#include "include/irq_service_interface.h"
32#include "link_encoder.h"
33#include "stream_encoder.h"
34#include "opp.h"
35#include "timing_generator.h"
36#include "transform.h"
33d7598d
JL		 37#include "dccg.h"
38#include "dchubbub.h"
d94585a0 39#include "dpp.h"
5ac3d3c9 40#include "core_types.h"
4562236b 41#include "set_mode_types.h"
4562236b 42#include "virtual/virtual_stream_encoder.h"
3b94a400 43#include "dpcd_defs.h"
4562236b 44
683b5950
MR		 45#if defined(CONFIG_DRM_AMD_DC_SI)
46#include "dce60/dce60_resource.h"
47#endif
4562236b
HW		 48#include "dce80/dce80_resource.h"
49#include "dce100/dce100_resource.h"
50#include "dce110/dce110_resource.h"
51#include "dce112/dce112_resource.h"
cf2156e2 52#include "dce120/dce120_resource.h"
b86a1aa3 53#if defined(CONFIG_DRM_AMD_DC_DCN)
ff5ef992 54#include "dcn10/dcn10_resource.h"
7ed4e635 55#include "dcn20/dcn20_resource.h"
e22ece54 56#include "dcn21/dcn21_resource.h"
20f2ffe5
AD		 57#include "dcn30/dcn30_resource.h"
58#include "dcn301/dcn301_resource.h"
59#include "dcn302/dcn302_resource.h"
36d26912 60#endif
5d4b05dd
BL		 61
62#define DC_LOGGER_INIT(logger)
63
4562236b
HW		 64enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
65{
66 enum dce_version dc_version = DCE_VERSION_UNKNOWN;
67 switch (asic_id.chip_family) {
68
683b5950
MR		 69#if defined(CONFIG_DRM_AMD_DC_SI)
70 case FAMILY_SI:
71 if (ASIC_REV_IS_TAHITI_P(asic_id.hw_internal_rev) ||
72 ASIC_REV_IS_PITCAIRN_PM(asic_id.hw_internal_rev) ||
73 ASIC_REV_IS_CAPEVERDE_M(asic_id.hw_internal_rev))
34b0c779 74 dc_version = DCE_VERSION_6_0;
683b5950
MR		 75 else if (ASIC_REV_IS_OLAND_M(asic_id.hw_internal_rev))
76 dc_version = DCE_VERSION_6_4;
77 else
78 dc_version = DCE_VERSION_6_1;
79 break;
80#endif
4562236b 81 case FAMILY_CI:
4562236b
HW		 82 dc_version = DCE_VERSION_8_0;
83 break;
ebfdf0d0
AD		 84 case FAMILY_KV:
85 if (ASIC_REV_IS_KALINDI(asic_id.hw_internal_rev) ||
86 ASIC_REV_IS_BHAVANI(asic_id.hw_internal_rev) ||
87 ASIC_REV_IS_GODAVARI(asic_id.hw_internal_rev))
88 dc_version = DCE_VERSION_8_3;
89 else
90 dc_version = DCE_VERSION_8_1;
91 break;
4562236b
HW		 92 case FAMILY_CZ:
93 dc_version = DCE_VERSION_11_0;
94 break;
95
96 case FAMILY_VI:
97 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
98 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
99 dc_version = DCE_VERSION_10_0;
100 break;
101 }
102 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
b264d345
JL		 103 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
104 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
4562236b
HW		 105 dc_version = DCE_VERSION_11_2;
106 }
0c75d5ac
JFZ		 107 if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev))
108 dc_version = DCE_VERSION_11_22;
4562236b 109 break;
2c8ad2d5 110 case FAMILY_AI:
b8b6ce89
LL		 111 if (ASICREV_IS_VEGA20_P(asic_id.hw_internal_rev))
112 dc_version = DCE_VERSION_12_1;
113 else
114 dc_version = DCE_VERSION_12_0;
2c8ad2d5 115 break;
b86a1aa3 116#if defined(CONFIG_DRM_AMD_DC_DCN)
ff5ef992
AD		 117 case FAMILY_RV:
118 dc_version = DCN_VERSION_1_0;
0e3d73f1
BL		 119 if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev))
120 dc_version = DCN_VERSION_1_01;
e22ece54
BL		 121 if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev))
122 dc_version = DCN_VERSION_2_1;
9ba93114
RL		 123 if (ASICREV_IS_GREEN_SARDINE(asic_id.hw_internal_rev))
124 dc_version = DCN_VERSION_2_1;
ff5ef992 125 break;
7ed4e635 126
7ed4e635
HW		 127 case FAMILY_NV:
128 dc_version = DCN_VERSION_2_0;
5dba4991
BL		 129 if (ASICREV_IS_SIENNA_CICHLID_P(asic_id.hw_internal_rev))
130 dc_version = DCN_VERSION_3_0;
36d26912
BL		 131 if (ASICREV_IS_DIMGREY_CAVEFISH_P(asic_id.hw_internal_rev))
132 dc_version = DCN_VERSION_3_02;
7ed4e635 133 break;
3a83e4e6 134
3a83e4e6
RL		 135 case FAMILY_VGH:
136 dc_version = DCN_VERSION_3_01;
137 break;
138#endif
4562236b
HW		 139 default:
140 dc_version = DCE_VERSION_UNKNOWN;
141 break;
142 }
143 return dc_version;
144}
145
d9673c92
HW		 146struct resource_pool *dc_create_resource_pool(struct dc *dc,
147 const struct dc_init_data *init_data,
148 enum dce_version dc_version)
4562236b 149{
5ac3d3c9 150 struct resource_pool *res_pool = NULL;
4562236b
HW		 151
152 switch (dc_version) {
683b5950
MR		 153#if defined(CONFIG_DRM_AMD_DC_SI)
154 case DCE_VERSION_6_0:
155 res_pool = dce60_create_resource_pool(
156 init_data->num_virtual_links, dc);
157 break;
158 case DCE_VERSION_6_1:
159 res_pool = dce61_create_resource_pool(
160 init_data->num_virtual_links, dc);
161 break;
162 case DCE_VERSION_6_4:
163 res_pool = dce64_create_resource_pool(
164 init_data->num_virtual_links, dc);
165 break;
166#endif
4562236b 167 case DCE_VERSION_8_0:
7992a629 168 res_pool = dce80_create_resource_pool(
d9673c92 169 init_data->num_virtual_links, dc);
7992a629 170 break;
ebfdf0d0 171 case DCE_VERSION_8_1:
7992a629 172 res_pool = dce81_create_resource_pool(
d9673c92 173 init_data->num_virtual_links, dc);
7992a629 174 break;
ebfdf0d0 175 case DCE_VERSION_8_3:
7992a629 176 res_pool = dce83_create_resource_pool(
d9673c92 177 init_data->num_virtual_links, dc);
5ac3d3c9 178 break;
4562236b 179 case DCE_VERSION_10_0:
5ac3d3c9 180 res_pool = dce100_create_resource_pool(
d9673c92 181 init_data->num_virtual_links, dc);
5ac3d3c9 182 break;
4562236b 183 case DCE_VERSION_11_0:
5ac3d3c9 184 res_pool = dce110_create_resource_pool(
d9673c92
HW		 185 init_data->num_virtual_links, dc,
186 init_data->asic_id);
5ac3d3c9 187 break;
4562236b 188 case DCE_VERSION_11_2:
0c75d5ac 189 case DCE_VERSION_11_22:
5ac3d3c9 190 res_pool = dce112_create_resource_pool(
d9673c92 191 init_data->num_virtual_links, dc);
5ac3d3c9 192 break;
2c8ad2d5 193 case DCE_VERSION_12_0:
b8b6ce89 194 case DCE_VERSION_12_1:
2c8ad2d5 195 res_pool = dce120_create_resource_pool(
d9673c92 196 init_data->num_virtual_links, dc);
2c8ad2d5 197 break;
ff5ef992 198
b86a1aa3 199#if defined(CONFIG_DRM_AMD_DC_DCN)
ff5ef992 200 case DCN_VERSION_1_0:
0e3d73f1 201 case DCN_VERSION_1_01:
d9673c92 202 res_pool = dcn10_create_resource_pool(init_data, dc);
ff5ef992 203 break;
7ed4e635
HW		 204 case DCN_VERSION_2_0:
205 res_pool = dcn20_create_resource_pool(init_data, dc);
206 break;
e22ece54
BL		 207 case DCN_VERSION_2_1:
208 res_pool = dcn21_create_resource_pool(init_data, dc);
209 break;
5dba4991
BL		 210 case DCN_VERSION_3_0:
211 res_pool = dcn30_create_resource_pool(init_data, dc);
212 break;
3a83e4e6
RL		 213 case DCN_VERSION_3_01:
214 res_pool = dcn301_create_resource_pool(init_data, dc);
215 break;
36d26912
BL		 216 case DCN_VERSION_3_02:
217 res_pool = dcn302_create_resource_pool(init_data, dc);
218 break;
3a83e4e6 219#endif
4562236b
HW		 220 default:
221 break;
222 }
f49cfa27 223
5ac3d3c9 224 if (res_pool != NULL) {
9adc8050 225 if (dc->ctx->dc_bios->fw_info_valid) {
41a5a2a8 226 res_pool->ref_clocks.xtalin_clock_inKhz =
9adc8050 227 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
41a5a2a8 228 /* initialize with firmware data first, no all
229 * ASIC have DCCG SW component. FPGA or
230 * simulation need initialization of
231 * dccg_ref_clock_inKhz, dchub_ref_clock_inKhz
232 * with xtalin_clock_inKhz
233 */
234 res_pool->ref_clocks.dccg_ref_clock_inKhz =
235 res_pool->ref_clocks.xtalin_clock_inKhz;
236 res_pool->ref_clocks.dchub_ref_clock_inKhz =
237 res_pool->ref_clocks.xtalin_clock_inKhz;
238 } else
239 ASSERT_CRITICAL(false);
5ac3d3c9 240 }
4562236b 241
5ac3d3c9 242 return res_pool;
4562236b
HW		 243}
244
fb3466a4 245void dc_destroy_resource_pool(struct dc *dc)
4562236b
HW		 246{
247 if (dc) {
248 if (dc->res_pool)
249 dc->res_pool->funcs->destroy(&dc->res_pool);
250
d029810c 251 kfree(dc->hwseq);
4562236b
HW		 252 }
253}
254
255static void update_num_audio(
256 const struct resource_straps *straps,
257 unsigned int *num_audio,
258 struct audio_support *aud_support)
259{
b8e9eb72
CL		 260 aud_support->dp_audio = true;
261 aud_support->hdmi_audio_native = false;
262 aud_support->hdmi_audio_on_dongle = false;
263
4562236b 264 if (straps->hdmi_disable == 0) {
4562236b
HW		 265 if (straps->dc_pinstraps_audio & 0x2) {
266 aud_support->hdmi_audio_on_dongle = true;
b8e9eb72 267 aud_support->hdmi_audio_native = true;
4562236b
HW		 268 }
269 }
270
271 switch (straps->audio_stream_number) {
272 case 0: /* multi streams supported */
273 break;
274 case 1: /* multi streams not supported */
275 *num_audio = 1;
276 break;
277 default:
278 DC_ERR("DC: unexpected audio fuse!\n");
17a96033 279 }
4562236b
HW		 280}
281
282bool resource_construct(
283 unsigned int num_virtual_links,
fb3466a4 284 struct dc *dc,
4562236b
HW		 285 struct resource_pool *pool,
286 const struct resource_create_funcs *create_funcs)
287{
288 struct dc_context *ctx = dc->ctx;
289 const struct resource_caps *caps = pool->res_cap;
290 int i;
291 unsigned int num_audio = caps->num_audio;
292 struct resource_straps straps = {0};
293
294 if (create_funcs->read_dce_straps)
295 create_funcs->read_dce_straps(dc->ctx, &straps);
296
297 pool->audio_count = 0;
298 if (create_funcs->create_audio) {
299 /* find the total number of streams available via the
300 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
301 * registers (one for each pin) starting from pin 1
302 * up to the max number of audio pins.
303 * We stop on the first pin where
304 * PORT_CONNECTIVITY == 1 (as instructed by HW team).
305 */
306 update_num_audio(&straps, &num_audio, &pool->audio_support);
5feb9f07 307 for (i = 0; i < caps->num_audio; i++) {
4562236b
HW		 308 struct audio *aud = create_funcs->create_audio(ctx, i);
309
310 if (aud == NULL) {
311 DC_ERR("DC: failed to create audio!\n");
312 return false;
313 }
4562236b
HW		 314 if (!aud->funcs->endpoint_valid(aud)) {
315 aud->funcs->destroy(&aud);
316 break;
317 }
4562236b
HW		 318 pool->audios[i] = aud;
319 pool->audio_count++;
320 }
321 }
322
323 pool->stream_enc_count = 0;
324 if (create_funcs->create_stream_encoder) {
325 for (i = 0; i < caps->num_stream_encoder; i++) {
326 pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx);
327 if (pool->stream_enc[i] == NULL)
328 DC_ERR("DC: failed to create stream_encoder!\n");
329 pool->stream_enc_count++;
330 }
331 }
929c3aaa 332
20f2ffe5 333#if defined(CONFIG_DRM_AMD_DC_DCN)
5dba4991
BL		 334 for (i = 0; i < caps->num_mpc_3dlut; i++) {
335 pool->mpc_lut[i] = dc_create_3dlut_func();
336 if (pool->mpc_lut[i] == NULL)
337 DC_ERR("DC: failed to create MPC 3dlut!\n");
338 pool->mpc_shaper[i] = dc_create_transfer_func();
339 if (pool->mpc_shaper[i] == NULL)
340 DC_ERR("DC: failed to create MPC shaper!\n");
341 }
342#endif
4176664b
CL		 343 dc->caps.dynamic_audio = false;
344 if (pool->audio_count < pool->stream_enc_count) {
345 dc->caps.dynamic_audio = true;
346 }
4562236b
HW		 347 for (i = 0; i < num_virtual_links; i++) {
348 pool->stream_enc[pool->stream_enc_count] =
349 virtual_stream_encoder_create(
350 ctx, ctx->dc_bios);
351 if (pool->stream_enc[pool->stream_enc_count] == NULL) {
352 DC_ERR("DC: failed to create stream_encoder!\n");
353 return false;
354 }
355 pool->stream_enc_count++;
356 }
357
358 dc->hwseq = create_funcs->create_hwseq(ctx);
359
360 return true;
361}
ad8960a6
ML		 362static int find_matching_clock_source(
363 const struct resource_pool *pool,
364 struct clock_source *clock_source)
365{
4562236b 366
ad8960a6
ML		 367 int i;
368
369 for (i = 0; i < pool->clk_src_count; i++) {
370 if (pool->clock_sources[i] == clock_source)
371 return i;
372 }
373 return -1;
374}
4562236b 375
21e67d4d 376void resource_unreference_clock_source(
4562236b 377 struct resource_context *res_ctx,
a2b8659d 378 const struct resource_pool *pool,
4a629536 379 struct clock_source *clock_source)
4562236b 380{
ad8960a6 381 int i = find_matching_clock_source(pool, clock_source);
4562236b 382
ad8960a6 383 if (i > -1)
4562236b
HW		 384 res_ctx->clock_source_ref_count[i]--;
385
21e67d4d 386 if (pool->dp_clock_source == clock_source)
4562236b 387 res_ctx->dp_clock_source_ref_count--;
4562236b
HW		 388}
389
390void resource_reference_clock_source(
391 struct resource_context *res_ctx,
a2b8659d 392 const struct resource_pool *pool,
4562236b
HW		 393 struct clock_source *clock_source)
394{
ad8960a6 395 int i = find_matching_clock_source(pool, clock_source);
4562236b 396
ad8960a6 397 if (i > -1)
4562236b 398 res_ctx->clock_source_ref_count[i]++;
4562236b 399
a2b8659d 400 if (pool->dp_clock_source == clock_source)
4562236b
HW		 401 res_ctx->dp_clock_source_ref_count++;
402}
403
ad8960a6
ML		 404int resource_get_clock_source_reference(
405 struct resource_context *res_ctx,
406 const struct resource_pool *pool,
407 struct clock_source *clock_source)
408{
409 int i = find_matching_clock_source(pool, clock_source);
410
411 if (i > -1)
412 return res_ctx->clock_source_ref_count[i];
413
414 if (pool->dp_clock_source == clock_source)
415 return res_ctx->dp_clock_source_ref_count;
416
417 return -1;
418}
419
77a2b726
VS		 420bool resource_are_vblanks_synchronizable(
421 struct dc_stream_state *stream1,
422 struct dc_stream_state *stream2)
423{
424 uint32_t base60_refresh_rates[] = {10, 20, 5};
425 uint8_t i;
426 uint8_t rr_count = sizeof(base60_refresh_rates)/sizeof(base60_refresh_rates[0]);
783bf403 427 uint64_t frame_time_diff;
77a2b726
VS		 428
429 if (stream1->ctx->dc->config.vblank_alignment_dto_params &&
430 stream1->ctx->dc->config.vblank_alignment_max_frame_time_diff > 0 &&
431 dc_is_dp_signal(stream1->signal) &&
432 dc_is_dp_signal(stream2->signal) &&
433 false == stream1->has_non_synchronizable_pclk &&
434 false == stream2->has_non_synchronizable_pclk &&
435 stream1->timing.flags.VBLANK_SYNCHRONIZABLE &&
436 stream2->timing.flags.VBLANK_SYNCHRONIZABLE) {
437 /* disable refresh rates higher than 60Hz for now */
438 if (stream1->timing.pix_clk_100hz*100/stream1->timing.h_total/
439 stream1->timing.v_total > 60)
440 return false;
441 if (stream2->timing.pix_clk_100hz*100/stream2->timing.h_total/
442 stream2->timing.v_total > 60)
443 return false;
783bf403 444 frame_time_diff = (uint64_t)10000 *
77a2b726
VS		 445 stream1->timing.h_total *
446 stream1->timing.v_total *
783bf403
VS		 447 stream2->timing.pix_clk_100hz;
448 frame_time_diff = div_u64(frame_time_diff, stream1->timing.pix_clk_100hz);
449 frame_time_diff = div_u64(frame_time_diff, stream2->timing.h_total);
450 frame_time_diff = div_u64(frame_time_diff, stream2->timing.v_total);
77a2b726 451 for (i = 0; i < rr_count; i++) {
783bf403 452 int64_t diff = (int64_t)div_u64(frame_time_diff * base60_refresh_rates[i], 10) - 10000;
77a2b726
VS		 453
454 if (diff < 0)
455 diff = -diff;
456 if (diff < stream1->ctx->dc->config.vblank_alignment_max_frame_time_diff)
457 return true;
458 }
459 }
460 return false;
461}
462
4562236b 463bool resource_are_streams_timing_synchronizable(
0971c40e
HW		 464 struct dc_stream_state *stream1,
465 struct dc_stream_state *stream2)
4562236b 466{
4fa086b9 467 if (stream1->timing.h_total != stream2->timing.h_total)
4562236b
HW		 468 return false;
469
4fa086b9 470 if (stream1->timing.v_total != stream2->timing.v_total)
4562236b
HW		 471 return false;
472
4fa086b9
LSL		 473 if (stream1->timing.h_addressable
474 != stream2->timing.h_addressable)
4562236b
HW		 475 return false;
476
4fa086b9
LSL		 477 if (stream1->timing.v_addressable
478 != stream2->timing.v_addressable)
4562236b
HW		 479 return false;
480
8582aea2
DG		 481 if (stream1->timing.v_front_porch
482 != stream2->timing.v_front_porch)
483 return false;
484
380604e2
KC		 485 if (stream1->timing.pix_clk_100hz
486 != stream2->timing.pix_clk_100hz)
4562236b
HW		 487 return false;
488
3e27e10e
ML		 489 if (stream1->clamping.c_depth != stream2->clamping.c_depth)
490 return false;
491
4562236b 492 if (stream1->phy_pix_clk != stream2->phy_pix_clk
7e2fe319
CL		 493 && (!dc_is_dp_signal(stream1->signal)
494 || !dc_is_dp_signal(stream2->signal)))
4562236b
HW		 495 return false;
496
d77f778e
CL		 497 if (stream1->view_format != stream2->view_format)
498 return false;
499
0460f9ab
JL		 500 if (stream1->ignore_msa_timing_param || stream2->ignore_msa_timing_param)
501 return false;
502
4562236b
HW		 503 return true;
504}
3e27e10e
ML		 505static bool is_dp_and_hdmi_sharable(
506 struct dc_stream_state *stream1,
507 struct dc_stream_state *stream2)
508{
509 if (stream1->ctx->dc->caps.disable_dp_clk_share)
510 return false;
511
512 if (stream1->clamping.c_depth != COLOR_DEPTH_888 ||
d77f778e 513 stream2->clamping.c_depth != COLOR_DEPTH_888)
43fbbe89 514 return false;
3e27e10e
ML		 515
516 return true;
517
518}
4562236b
HW		 519
520static bool is_sharable_clk_src(
521 const struct pipe_ctx *pipe_with_clk_src,
522 const struct pipe_ctx *pipe)
523{
524 if (pipe_with_clk_src->clock_source == NULL)
525 return false;
526
527 if (pipe_with_clk_src->stream->signal == SIGNAL_TYPE_VIRTUAL)
528 return false;
529
3e27e10e
ML		 530 if (dc_is_dp_signal(pipe_with_clk_src->stream->signal) ||
531 (dc_is_dp_signal(pipe->stream->signal) &&
532 !is_dp_and_hdmi_sharable(pipe_with_clk_src->stream,
533 pipe->stream)))
4562236b
HW		 534 return false;
535
536 if (dc_is_hdmi_signal(pipe_with_clk_src->stream->signal)
fc69009e 537 && dc_is_dual_link_signal(pipe->stream->signal))
4562236b
HW		 538 return false;
539
540 if (dc_is_hdmi_signal(pipe->stream->signal)
fc69009e 541 && dc_is_dual_link_signal(pipe_with_clk_src->stream->signal))
4562236b
HW		 542 return false;
543
544 if (!resource_are_streams_timing_synchronizable(
545 pipe_with_clk_src->stream, pipe->stream))
546 return false;
547
548 return true;
549}
550
551struct clock_source *resource_find_used_clk_src_for_sharing(
552 struct resource_context *res_ctx,
553 struct pipe_ctx *pipe_ctx)
554{
555 int i;
556
557 for (i = 0; i < MAX_PIPES; i++) {
558 if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx))
559 return res_ctx->pipe_ctx[i].clock_source;
560 }
561
562 return NULL;
563}
564
565static enum pixel_format convert_pixel_format_to_dalsurface(
566 enum surface_pixel_format surface_pixel_format)
567{
568 enum pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
569
570 switch (surface_pixel_format) {
571 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
572 dal_pixel_format = PIXEL_FORMAT_INDEX8;
573 break;
574 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
575 dal_pixel_format = PIXEL_FORMAT_RGB565;
576 break;
577 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
578 dal_pixel_format = PIXEL_FORMAT_RGB565;
579 break;
580 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
581 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
582 break;
8693049a 583 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
4562236b
HW		 584 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
585 break;
586 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
587 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
588 break;
589 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
590 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
591 break;
592 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
593 dal_pixel_format = PIXEL_FORMAT_ARGB2101010_XRBIAS;
594 break;
595 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
596 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
597 dal_pixel_format = PIXEL_FORMAT_FP16;
598 break;
599 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
4562236b 600 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
87449a90 601 dal_pixel_format = PIXEL_FORMAT_420BPP8;
4562236b 602 break;
ffbcd19a
VP		 603 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
604 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
87449a90 605 dal_pixel_format = PIXEL_FORMAT_420BPP10;
ffbcd19a 606 break;
4562236b
HW		 607 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
608 default:
609 dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
610 break;
611 }
612 return dal_pixel_format;
613}
614
9b6067c0
DL		 615static inline void get_vp_scan_direction(
616 enum dc_rotation_angle rotation,
617 bool horizontal_mirror,
618 bool *orthogonal_rotation,
619 bool *flip_vert_scan_dir,
620 bool *flip_horz_scan_dir)
4562236b 621{
9b6067c0
DL		 622 *orthogonal_rotation = false;
623 *flip_vert_scan_dir = false;
624 *flip_horz_scan_dir = false;
625 if (rotation == ROTATION_ANGLE_180) {
626 *flip_vert_scan_dir = true;
627 *flip_horz_scan_dir = true;
628 } else if (rotation == ROTATION_ANGLE_90) {
629 *orthogonal_rotation = true;
630 *flip_horz_scan_dir = true;
631 } else if (rotation == ROTATION_ANGLE_270) {
632 *orthogonal_rotation = true;
633 *flip_vert_scan_dir = true;
634 }
635
636 if (horizontal_mirror)
637 *flip_horz_scan_dir = !*flip_horz_scan_dir;
4562236b
HW		 638}
639
570bc18c
DL		 640int get_num_mpc_splits(struct pipe_ctx *pipe)
641{
642 int mpc_split_count = 0;
643 struct pipe_ctx *other_pipe = pipe->bottom_pipe;
644
645 while (other_pipe && other_pipe->plane_state == pipe->plane_state) {
646 mpc_split_count++;
647 other_pipe = other_pipe->bottom_pipe;
648 }
649 other_pipe = pipe->top_pipe;
650 while (other_pipe && other_pipe->plane_state == pipe->plane_state) {
651 mpc_split_count++;
652 other_pipe = other_pipe->top_pipe;
653 }
654
655 return mpc_split_count;
656}
657
228a10d4
AD		 658int get_num_odm_splits(struct pipe_ctx *pipe)
659{
660 int odm_split_count = 0;
661 struct pipe_ctx *next_pipe = pipe->next_odm_pipe;
662 while (next_pipe) {
663 odm_split_count++;
664 next_pipe = next_pipe->next_odm_pipe;
665 }
666 pipe = pipe->prev_odm_pipe;
667 while (pipe) {
668 odm_split_count++;
669 pipe = pipe->prev_odm_pipe;
670 }
671 return odm_split_count;
672}
673
5bf24270
DL		 674static void calculate_split_count_and_index(struct pipe_ctx *pipe_ctx, int *split_count, int *split_idx)
675{
676 *split_count = get_num_odm_splits(pipe_ctx);
677 *split_idx = 0;
678 if (*split_count == 0) {
679 /*Check for mpc split*/
680 struct pipe_ctx *split_pipe = pipe_ctx->top_pipe;
681
570bc18c 682 *split_count = get_num_mpc_splits(pipe_ctx);
5bf24270
DL		 683 while (split_pipe && split_pipe->plane_state == pipe_ctx->plane_state) {
684 (*split_idx)++;
5bf24270
DL		 685 split_pipe = split_pipe->top_pipe;
686 }
5bf24270
DL		 687 } else {
688 /*Get odm split index*/
689 struct pipe_ctx *split_pipe = pipe_ctx->prev_odm_pipe;
690
691 while (split_pipe) {
692 (*split_idx)++;
693 split_pipe = split_pipe->prev_odm_pipe;
694 }
695 }
696}
697
b2d0a103 698static void calculate_viewport(struct pipe_ctx *pipe_ctx)
4562236b 699{
3be5262e 700 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 701 const struct dc_stream_state *stream = pipe_ctx->stream;
6702a9ac 702 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
3be5262e 703 struct rect surf_src = plane_state->src_rect;
9b6067c0 704 struct rect clip, dest;
87449a90
AK		 705 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
706 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
5bf24270
DL		 707 int split_count = 0;
708 int split_idx = 0;
9b6067c0 709 bool orthogonal_rotation, flip_y_start, flip_x_start;
83d40659 710
5bf24270
DL		 711 calculate_split_count_and_index(pipe_ctx, &split_count, &split_idx);
712
7f5c22d1
VP		 713 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE ||
714 stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) {
5bf24270
DL		 715 split_count = 0;
716 split_idx = 0;
7b779c99 717 }
86006a7f 718
4562236b
HW		 719 /* The actual clip is an intersection between stream
720 * source and surface clip
721 */
9b6067c0 722 dest = plane_state->dst_rect;
3be5262e
HW		 723 clip.x = stream->src.x > plane_state->clip_rect.x ?
724 stream->src.x : plane_state->clip_rect.x;
4562236b 725
1fbd2cfc 726 clip.width = stream->src.x + stream->src.width <
3be5262e 727 plane_state->clip_rect.x + plane_state->clip_rect.width ?
1fbd2cfc 728 stream->src.x + stream->src.width - clip.x :
3be5262e 729 plane_state->clip_rect.x + plane_state->clip_rect.width - clip.x ;
4562236b 730
3be5262e
HW		 731 clip.y = stream->src.y > plane_state->clip_rect.y ?
732 stream->src.y : plane_state->clip_rect.y;
4562236b 733
1fbd2cfc 734 clip.height = stream->src.y + stream->src.height <
3be5262e 735 plane_state->clip_rect.y + plane_state->clip_rect.height ?
1fbd2cfc 736 stream->src.y + stream->src.height - clip.y :
3be5262e 737 plane_state->clip_rect.y + plane_state->clip_rect.height - clip.y ;
4562236b 738
9b6067c0
DL		 739 /*
740 * Need to calculate how scan origin is shifted in vp space
741 * to correctly rotate clip and dst
742 */
743 get_vp_scan_direction(
744 plane_state->rotation,
745 plane_state->horizontal_mirror,
746 &orthogonal_rotation,
747 &flip_y_start,
748 &flip_x_start);
749
750 if (orthogonal_rotation) {
751 swap(clip.x, clip.y);
752 swap(clip.width, clip.height);
753 swap(dest.x, dest.y);
754 swap(dest.width, dest.height);
755 }
756 if (flip_x_start) {
757 clip.x = dest.x + dest.width - clip.x - clip.width;
758 dest.x = 0;
759 }
760 if (flip_y_start) {
761 clip.y = dest.y + dest.height - clip.y - clip.height;
762 dest.y = 0;
763 }
764
86006a7f 765 /* offset = surf_src.ofs + (clip.ofs - surface->dst_rect.ofs) * scl_ratio
4562236b
HW		 766 * num_pixels = clip.num_pix * scl_ratio
767 */
9b6067c0
DL		 768 data->viewport.x = surf_src.x + (clip.x - dest.x) * surf_src.width / dest.width;
769 data->viewport.width = clip.width * surf_src.width / dest.width;
770
771 data->viewport.y = surf_src.y + (clip.y - dest.y) * surf_src.height / dest.height;
772 data->viewport.height = clip.height * surf_src.height / dest.height;
773
774 /* Handle split */
5bf24270
DL		 775 if (split_count) {
776 /* extra pixels in the division remainder need to go to pipes after
777 * the extra pixel index minus one(epimo) defined here as:
778 */
779 int epimo = 0;
780
9b6067c0 781 if (orthogonal_rotation) {
5bf24270
DL		 782 if (flip_y_start)
783 split_idx = split_count - split_idx;
784
785 epimo = split_count - data->viewport.height % (split_count + 1);
786
787 data->viewport.y += (data->viewport.height / (split_count + 1)) * split_idx;
788 if (split_idx > epimo)
789 data->viewport.y += split_idx - epimo - 1;
790 data->viewport.height = data->viewport.height / (split_count + 1) + (split_idx > epimo ? 1 : 0);
9b6067c0 791 } else {
5bf24270
DL		 792 if (flip_x_start)
793 split_idx = split_count - split_idx;
794
795 epimo = split_count - data->viewport.width % (split_count + 1);
796
797 data->viewport.x += (data->viewport.width / (split_count + 1)) * split_idx;
798 if (split_idx > epimo)
799 data->viewport.x += split_idx - epimo - 1;
800 data->viewport.width = data->viewport.width / (split_count + 1) + (split_idx > epimo ? 1 : 0);
9b6067c0
DL		 801 }
802 }
9b5349f7 803
b2d0a103
DL		 804 /* Round down, compensate in init */
805 data->viewport_c.x = data->viewport.x / vpc_div;
806 data->viewport_c.y = data->viewport.y / vpc_div;
9b6067c0
DL		 807 data->inits.h_c = (data->viewport.x % vpc_div) != 0 ? dc_fixpt_half : dc_fixpt_zero;
808 data->inits.v_c = (data->viewport.y % vpc_div) != 0 ? dc_fixpt_half : dc_fixpt_zero;
809
b2d0a103
DL		 810 /* Round up, assume original video size always even dimensions */
811 data->viewport_c.width = (data->viewport.width + vpc_div - 1) / vpc_div;
812 data->viewport_c.height = (data->viewport.height + vpc_div - 1) / vpc_div;
fa90219a
DL		 813
814 data->viewport_unadjusted = data->viewport;
815 data->viewport_c_unadjusted = data->viewport_c;
4562236b
HW		 816}
817
9b6067c0 818static void calculate_recout(struct pipe_ctx *pipe_ctx)
4562236b 819{
3be5262e 820 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 821 const struct dc_stream_state *stream = pipe_ctx->stream;
5bf24270 822 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
3be5262e 823 struct rect surf_clip = plane_state->clip_rect;
5bf24270
DL		 824 bool pri_split_tb = pipe_ctx->bottom_pipe &&
825 pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state &&
826 stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM;
827 bool sec_split_tb = pipe_ctx->top_pipe &&
828 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state &&
829 stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM;
830 int split_count = 0;
831 int split_idx = 0;
832
833 calculate_split_count_and_index(pipe_ctx, &split_count, &split_idx);
834
05e3d830
WC		 835 /*
836 * Only the leftmost ODM pipe should be offset by a nonzero distance
837 */
25b31581 838 if (!pipe_ctx->prev_odm_pipe) {
05e3d830 839 data->recout.x = stream->dst.x;
25b31581
WC		 840 if (stream->src.x < surf_clip.x)
841 data->recout.x += (surf_clip.x - stream->src.x) * stream->dst.width
4fa086b9 842 / stream->src.width;
4562236b 843
25b31581
WC		 844 } else
845 data->recout.x = 0;
846
84aef2ab
DL		 847 if (stream->src.x > surf_clip.x)
848 surf_clip.width -= stream->src.x - surf_clip.x;
5bf24270
DL		 849 data->recout.width = surf_clip.width * stream->dst.width / stream->src.width;
850 if (data->recout.width + data->recout.x > stream->dst.x + stream->dst.width)
851 data->recout.width = stream->dst.x + stream->dst.width - data->recout.x;
4562236b 852
5bf24270 853 data->recout.y = stream->dst.y;
4fa086b9 854 if (stream->src.y < surf_clip.y)
5bf24270 855 data->recout.y += (surf_clip.y - stream->src.y) * stream->dst.height
4fa086b9 856 / stream->src.height;
84aef2ab
DL		 857 else if (stream->src.y > surf_clip.y)
858 surf_clip.height -= stream->src.y - surf_clip.y;
4562236b 859
5bf24270
DL		 860 data->recout.height = surf_clip.height * stream->dst.height / stream->src.height;
861 if (data->recout.height + data->recout.y > stream->dst.y + stream->dst.height)
862 data->recout.height = stream->dst.y + stream->dst.height - data->recout.y;
b2d0a103 863
9b6067c0 864 /* Handle h & v split, handle rotation using viewport */
5bf24270
DL		 865 if (sec_split_tb) {
866 data->recout.y += data->recout.height / 2;
0c31a821 867 /* Floor primary pipe, ceil 2ndary pipe */
5bf24270
DL		 868 data->recout.height = (data->recout.height + 1) / 2;
869 } else if (pri_split_tb)
870 data->recout.height /= 2;
871 else if (split_count) {
872 /* extra pixels in the division remainder need to go to pipes after
873 * the extra pixel index minus one(epimo) defined here as:
874 */
875 int epimo = split_count - data->recout.width % (split_count + 1);
876
877 /*no recout offset due to odm */
878 if (!pipe_ctx->next_odm_pipe && !pipe_ctx->prev_odm_pipe) {
879 data->recout.x += (data->recout.width / (split_count + 1)) * split_idx;
880 if (split_idx > epimo)
881 data->recout.x += split_idx - epimo - 1;
882 }
883 data->recout.width = data->recout.width / (split_count + 1) + (split_idx > epimo ? 1 : 0);
884 }
4562236b
HW		 885}
886
b2d0a103 887static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)
4562236b 888{
3be5262e 889 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 890 const struct dc_stream_state *stream = pipe_ctx->stream;
3be5262e 891 struct rect surf_src = plane_state->src_rect;
4fa086b9
LSL		 892 const int in_w = stream->src.width;
893 const int in_h = stream->src.height;
894 const int out_w = stream->dst.width;
895 const int out_h = stream->dst.height;
4562236b 896
9b6067c0 897 /*Swap surf_src height and width since scaling ratios are in recout rotation*/
3be5262e
HW		 898 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
899 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
9b6067c0 900 swap(surf_src.height, surf_src.width);
86006a7f 901
eb0e5154 902 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_from_fraction(
86006a7f 903 surf_src.width,
3be5262e 904 plane_state->dst_rect.width);
eb0e5154 905 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction(
86006a7f 906 surf_src.height,
3be5262e 907 plane_state->dst_rect.height);
4562236b 908
4fa086b9 909 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
6702a9ac 910 pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2;
4fa086b9 911 else if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
6702a9ac 912 pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2;
4562236b 913
6702a9ac
HW		 914 pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64(
915 pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h);
916 pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64(
917 pipe_ctx->plane_res.scl_data.ratios.horz.value * in_w, out_w);
4562236b 918
6702a9ac
HW		 919 pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz;
920 pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert;
4562236b 921
6702a9ac
HW		 922 if (pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP8
923 || pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP10) {
924 pipe_ctx->plane_res.scl_data.ratios.horz_c.value /= 2;
925 pipe_ctx->plane_res.scl_data.ratios.vert_c.value /= 2;
4562236b 926 }
0002d3ac
DL		 927 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_truncate(
928 pipe_ctx->plane_res.scl_data.ratios.horz, 19);
929 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_truncate(
930 pipe_ctx->plane_res.scl_data.ratios.vert, 19);
931 pipe_ctx->plane_res.scl_data.ratios.horz_c = dc_fixpt_truncate(
932 pipe_ctx->plane_res.scl_data.ratios.horz_c, 19);
933 pipe_ctx->plane_res.scl_data.ratios.vert_c = dc_fixpt_truncate(
934 pipe_ctx->plane_res.scl_data.ratios.vert_c, 19);
4562236b
HW		 935}
936
9b6067c0
DL		 937static inline void adjust_vp_and_init_for_seamless_clip(
938 bool flip_scan_dir,
939 int recout_skip,
940 int src_size,
941 int taps,
942 struct fixed31_32 ratio,
943 struct fixed31_32 *init,
944 int *vp_offset,
945 int *vp_size)
b2d0a103 946{
9b6067c0 947 if (!flip_scan_dir) {
9a08f51f 948 /* Adjust for viewport end clip-off */
9b6067c0
DL		 949 if ((*vp_offset + *vp_size) < src_size) {
950 int vp_clip = src_size - *vp_size - *vp_offset;
951 int int_part = dc_fixpt_floor(dc_fixpt_sub(*init, ratio));
9a08f51f
DL		 952
953 int_part = int_part > 0 ? int_part : 0;
9b6067c0 954 *vp_size += int_part < vp_clip ? int_part : vp_clip;
9a08f51f 955 }
b2d0a103 956
9a08f51f 957 /* Adjust for non-0 viewport offset */
9b6067c0 958 if (*vp_offset) {
9a08f51f
DL		 959 int int_part;
960
9b6067c0
DL		 961 *init = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_skip));
962 int_part = dc_fixpt_floor(*init) - *vp_offset;
963 if (int_part < taps) {
964 int int_adj = *vp_offset >= (taps - int_part) ?
965 (taps - int_part) : *vp_offset;
966 *vp_offset -= int_adj;
967 *vp_size += int_adj;
9a08f51f 968 int_part += int_adj;
9b6067c0
DL		 969 } else if (int_part > taps) {
970 *vp_offset += int_part - taps;
971 *vp_size -= int_part - taps;
972 int_part = taps;
9a08f51f 973 }
9b6067c0
DL		 974 init->value &= 0xffffffff;
975 *init = dc_fixpt_add_int(*init, int_part);
9a08f51f
DL		 976 }
977 } else {
978 /* Adjust for non-0 viewport offset */
9b6067c0
DL		 979 if (*vp_offset) {
980 int int_part = dc_fixpt_floor(dc_fixpt_sub(*init, ratio));
b2d0a103 981
9a08f51f 982 int_part = int_part > 0 ? int_part : 0;
9b6067c0
DL		 983 *vp_size += int_part < *vp_offset ? int_part : *vp_offset;
984 *vp_offset -= int_part < *vp_offset ? int_part : *vp_offset;
9a08f51f 985 }
b2d0a103 986
9a08f51f 987 /* Adjust for viewport end clip-off */
9b6067c0 988 if ((*vp_offset + *vp_size) < src_size) {
9a08f51f 989 int int_part;
9b6067c0 990 int end_offset = src_size - *vp_offset - *vp_size;
9a08f51f
DL		 991
992 /*
993 * this is init if vp had no offset, keep in mind this is from the
994 * right side of vp due to scan direction
995 */
9b6067c0 996 *init = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_skip));
9a08f51f
DL		 997 /*
998 * this is the difference between first pixel of viewport available to read
999 * and init position, takning into account scan direction
1000 */
9b6067c0
DL		 1001 int_part = dc_fixpt_floor(*init) - end_offset;
1002 if (int_part < taps) {
1003 int int_adj = end_offset >= (taps - int_part) ?
1004 (taps - int_part) : end_offset;
1005 *vp_size += int_adj;
9a08f51f 1006 int_part += int_adj;
9b6067c0
DL		 1007 } else if (int_part > taps) {
1008 *vp_size += int_part - taps;
1009 int_part = taps;
9a08f51f 1010 }
9b6067c0
DL		 1011 init->value &= 0xffffffff;
1012 *init = dc_fixpt_add_int(*init, int_part);
b2d0a103 1013 }
b2d0a103 1014 }
9b6067c0 1015}
9a08f51f 1016
9b6067c0
DL		 1017static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx)
1018{
1019 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1020 const struct dc_stream_state *stream = pipe_ctx->stream;
05e3d830 1021 struct pipe_ctx *odm_pipe = pipe_ctx;
9b6067c0
DL		 1022 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
1023 struct rect src = pipe_ctx->plane_state->src_rect;
1024 int recout_skip_h, recout_skip_v, surf_size_h, surf_size_v;
1025 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
1026 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
1027 bool orthogonal_rotation, flip_vert_scan_dir, flip_horz_scan_dir;
7287a675 1028 int odm_idx = 0;
9a08f51f 1029
9b6067c0
DL		 1030 /*
1031 * Need to calculate the scan direction for viewport to make adjustments
1032 */
1033 get_vp_scan_direction(
1034 plane_state->rotation,
1035 plane_state->horizontal_mirror,
1036 &orthogonal_rotation,
1037 &flip_vert_scan_dir,
1038 &flip_horz_scan_dir);
1039
1040 /* Calculate src rect rotation adjusted to recout space */
1041 surf_size_h = src.x + src.width;
1042 surf_size_v = src.y + src.height;
1043 if (flip_horz_scan_dir)
1044 src.x = 0;
1045 if (flip_vert_scan_dir)
1046 src.y = 0;
1047 if (orthogonal_rotation) {
1048 swap(src.x, src.y);
1049 swap(src.width, src.height);
1050 }
9a08f51f 1051
05e3d830
WC		 1052 /*modified recout_skip_h calculation due to odm having no recout offset*/
1053 while (odm_pipe->prev_odm_pipe) {
1054 odm_idx++;
1055 odm_pipe = odm_pipe->prev_odm_pipe;
1056 }
1057 /*odm_pipe is the leftmost pipe in the ODM group*/
1058 recout_skip_h = odm_idx * data->recout.width;
1059
9b6067c0
DL		 1060 /* Recout matching initial vp offset = recout_offset - (stream dst offset +
1061 * ((surf dst offset - stream src offset) * 1/ stream scaling ratio)
1062 * - (surf surf_src offset * 1/ full scl ratio))
1063 */
05e3d830
WC		 1064 recout_skip_h += odm_pipe->plane_res.scl_data.recout.x
1065 - (stream->dst.x + (plane_state->dst_rect.x - stream->src.x)
9b6067c0
DL		 1066 * stream->dst.width / stream->src.width -
1067 src.x * plane_state->dst_rect.width / src.width
1068 * stream->dst.width / stream->src.width);
05e3d830 1069
5bf24270 1070
9b6067c0
DL		 1071 recout_skip_v = data->recout.y - (stream->dst.y + (plane_state->dst_rect.y - stream->src.y)
1072 * stream->dst.height / stream->src.height -
1073 src.y * plane_state->dst_rect.height / src.height
1074 * stream->dst.height / stream->src.height);
1075 if (orthogonal_rotation)
1076 swap(recout_skip_h, recout_skip_v);
1077 /*
1078 * Init calculated according to formula:
1079 * init = (scaling_ratio + number_of_taps + 1) / 2
1080 * init_bot = init + scaling_ratio
1081 * init_c = init + truncated_vp_c_offset(from calculate viewport)
1082 */
1083 data->inits.h = dc_fixpt_truncate(dc_fixpt_div_int(
1084 dc_fixpt_add_int(data->ratios.horz, data->taps.h_taps + 1), 2), 19);
b2d0a103 1085
9b6067c0
DL		 1086 data->inits.h_c = dc_fixpt_truncate(dc_fixpt_add(data->inits.h_c, dc_fixpt_div_int(
1087 dc_fixpt_add_int(data->ratios.horz_c, data->taps.h_taps_c + 1), 2)), 19);
9a08f51f 1088
9b6067c0
DL		 1089 data->inits.v = dc_fixpt_truncate(dc_fixpt_div_int(
1090 dc_fixpt_add_int(data->ratios.vert, data->taps.v_taps + 1), 2), 19);
9a08f51f 1091
9b6067c0
DL		 1092 data->inits.v_c = dc_fixpt_truncate(dc_fixpt_add(data->inits.v_c, dc_fixpt_div_int(
1093 dc_fixpt_add_int(data->ratios.vert_c, data->taps.v_taps_c + 1), 2)), 19);
9a08f51f 1094
9b6067c0
DL		 1095 /*
1096 * Taps, inits and scaling ratios are in recout space need to rotate
1097 * to viewport rotation before adjustment
1098 */
1099 adjust_vp_and_init_for_seamless_clip(
1100 flip_horz_scan_dir,
1101 recout_skip_h,
1102 surf_size_h,
1103 orthogonal_rotation ? data->taps.v_taps : data->taps.h_taps,
1104 orthogonal_rotation ? data->ratios.vert : data->ratios.horz,
1105 orthogonal_rotation ? &data->inits.v : &data->inits.h,
1106 &data->viewport.x,
1107 &data->viewport.width);
1108 adjust_vp_and_init_for_seamless_clip(
1109 flip_horz_scan_dir,
1110 recout_skip_h,
1111 surf_size_h / vpc_div,
1112 orthogonal_rotation ? data->taps.v_taps_c : data->taps.h_taps_c,
1113 orthogonal_rotation ? data->ratios.vert_c : data->ratios.horz_c,
1114 orthogonal_rotation ? &data->inits.v_c : &data->inits.h_c,
1115 &data->viewport_c.x,
1116 &data->viewport_c.width);
1117 adjust_vp_and_init_for_seamless_clip(
1118 flip_vert_scan_dir,
1119 recout_skip_v,
1120 surf_size_v,
1121 orthogonal_rotation ? data->taps.h_taps : data->taps.v_taps,
1122 orthogonal_rotation ? data->ratios.horz : data->ratios.vert,
1123 orthogonal_rotation ? &data->inits.h : &data->inits.v,
1124 &data->viewport.y,
1125 &data->viewport.height);
1126 adjust_vp_and_init_for_seamless_clip(
1127 flip_vert_scan_dir,
1128 recout_skip_v,
1129 surf_size_v / vpc_div,
1130 orthogonal_rotation ? data->taps.h_taps_c : data->taps.v_taps_c,
1131 orthogonal_rotation ? data->ratios.horz_c : data->ratios.vert_c,
1132 orthogonal_rotation ? &data->inits.h_c : &data->inits.v_c,
1133 &data->viewport_c.y,
1134 &data->viewport_c.height);
b2d0a103
DL		 1135
1136 /* Interlaced inits based on final vert inits */
eb0e5154
DL		 1137 data->inits.v_bot = dc_fixpt_add(data->inits.v, data->ratios.vert);
1138 data->inits.v_c_bot = dc_fixpt_add(data->inits.v_c, data->ratios.vert_c);
1fbd2cfc 1139
b2d0a103 1140}
3b733278 1141
89d07b66
ST		 1142/*
1143 * When handling 270 rotation in mixed SLS mode, we have
1144 * stream->timing.h_border_left that is non zero. If we are doing
1145 * pipe-splitting, this h_border_left value gets added to recout.x and when it
1146 * calls calculate_inits_and_adj_vp() and
1147 * adjust_vp_and_init_for_seamless_clip(), it can cause viewport.height for a
1148 * pipe to be incorrect.
1149 *
1150 * To fix this, instead of using stream->timing.h_border_left, we can use
1151 * stream->dst.x to represent the border instead. So we will set h_border_left
1152 * to 0 and shift the appropriate amount in stream->dst.x. We will then
1153 * perform all calculations in resource_build_scaling_params() based on this
1154 * and then restore the h_border_left and stream->dst.x to their original
1155 * values.
1156 *
1157 * shift_border_left_to_dst() will shift the amount of h_border_left to
1158 * stream->dst.x and set h_border_left to 0. restore_border_left_from_dst()
1159 * will restore h_border_left and stream->dst.x back to their original values
1160 * We also need to make sure pipe_ctx->plane_res.scl_data.h_active uses the
1161 * original h_border_left value in its calculation.
1162 */
c88855f3 1163static int shift_border_left_to_dst(struct pipe_ctx *pipe_ctx)
89d07b66
ST		 1164{
1165 int store_h_border_left = pipe_ctx->stream->timing.h_border_left;
1166
1167 if (store_h_border_left) {
1168 pipe_ctx->stream->timing.h_border_left = 0;
1169 pipe_ctx->stream->dst.x += store_h_border_left;
1170 }
1171 return store_h_border_left;
1172}
1173
c88855f3
LJ		 1174static void restore_border_left_from_dst(struct pipe_ctx *pipe_ctx,
1175 int store_h_border_left)
89d07b66
ST		 1176{
1177 pipe_ctx->stream->dst.x -= store_h_border_left;
1178 pipe_ctx->stream->timing.h_border_left = store_h_border_left;
1179}
1180
b2d0a103 1181bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
4562236b 1182{
3be5262e 1183 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
4fa086b9 1184 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
b2d0a103 1185 bool res = false;
89d07b66 1186 int store_h_border_left = shift_border_left_to_dst(pipe_ctx);
5d4b05dd 1187 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
4562236b
HW		 1188 /* Important: scaling ratio calculation requires pixel format,
1189 * lb depth calculation requires recout and taps require scaling ratios.
b2d0a103 1190 * Inits require viewport, taps, ratios and recout of split pipe
4562236b 1191 */
6702a9ac 1192 pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface(
3be5262e 1193 pipe_ctx->plane_state->format);
b2d0a103
DL		 1194
1195 calculate_scaling_ratios(pipe_ctx);
4562236b 1196
b2d0a103 1197 calculate_viewport(pipe_ctx);
4562236b 1198
40d916a2
NC		 1199 if (pipe_ctx->plane_res.scl_data.viewport.height < MIN_VIEWPORT_SIZE ||
1200 pipe_ctx->plane_res.scl_data.viewport.width < MIN_VIEWPORT_SIZE) {
89d07b66
ST		 1201 if (store_h_border_left) {
1202 restore_border_left_from_dst(pipe_ctx,
1203 store_h_border_left);
1204 }
4562236b 1205 return false;
89d07b66 1206 }
4562236b 1207
9b6067c0 1208 calculate_recout(pipe_ctx);
4562236b
HW		 1209
1210 /**
1211 * Setting line buffer pixel depth to 24bpp yields banding
1212 * on certain displays, such as the Sharp 4k
1213 */
6702a9ac 1214 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
33eef72f 1215 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = plane_state->per_pixel_alpha;
4562236b 1216
199e458a 1217 pipe_ctx->plane_res.scl_data.recout.x += timing->h_border_left;
58bb0e63 1218 pipe_ctx->plane_res.scl_data.recout.y += timing->v_border_top;
199e458a 1219
89d07b66
ST		 1220 pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable +
1221 store_h_border_left + timing->h_border_right;
1222 pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable +
1223 timing->v_border_top + timing->v_border_bottom;
5bf24270
DL		 1224 if (pipe_ctx->next_odm_pipe || pipe_ctx->prev_odm_pipe)
1225 pipe_ctx->plane_res.scl_data.h_active /= get_num_odm_splits(pipe_ctx) + 1;
1b6c8067 1226
4562236b 1227 /* Taps calculations */
d94585a0
YHL		 1228 if (pipe_ctx->plane_res.xfm != NULL)
1229 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
1230 pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
1231
1232 if (pipe_ctx->plane_res.dpp != NULL)
1233 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
1234 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
f7938bc0 1235
f7938bc0 1236
4562236b
HW		 1237 if (!res) {
1238 /* Try 24 bpp linebuffer */
6702a9ac 1239 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP;
4562236b 1240
1b6c8067
BL		 1241 if (pipe_ctx->plane_res.xfm != NULL)
1242 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
1243 pipe_ctx->plane_res.xfm,
1244 &pipe_ctx->plane_res.scl_data,
1245 &plane_state->scaling_quality);
1246
1247 if (pipe_ctx->plane_res.dpp != NULL)
1248 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
1249 pipe_ctx->plane_res.dpp,
1250 &pipe_ctx->plane_res.scl_data,
1251 &plane_state->scaling_quality);
4562236b
HW		 1252 }
1253
b2d0a103 1254 if (res)
1fbd2cfc 1255 /* May need to re-check lb size after this in some obscure scenario */
9b6067c0 1256 calculate_inits_and_adj_vp(pipe_ctx);
b2d0a103 1257
3c0dcf9f
DL		 1258 DC_LOG_SCALER("%s pipe %d:\nViewport: height:%d width:%d x:%d y:%d Recout: height:%d width:%d x:%d y:%d HACTIVE:%d VACTIVE:%d\n"
1259 "src_rect: height:%d width:%d x:%d y:%d dst_rect: height:%d width:%d x:%d y:%d clip_rect: height:%d width:%d x:%d y:%d\n",
1260 __func__,
1261 pipe_ctx->pipe_idx,
1262 pipe_ctx->plane_res.scl_data.viewport.height,
1263 pipe_ctx->plane_res.scl_data.viewport.width,
1264 pipe_ctx->plane_res.scl_data.viewport.x,
1265 pipe_ctx->plane_res.scl_data.viewport.y,
1266 pipe_ctx->plane_res.scl_data.recout.height,
1267 pipe_ctx->plane_res.scl_data.recout.width,
1268 pipe_ctx->plane_res.scl_data.recout.x,
1269 pipe_ctx->plane_res.scl_data.recout.y,
1270 pipe_ctx->plane_res.scl_data.h_active,
1271 pipe_ctx->plane_res.scl_data.v_active,
1272 plane_state->src_rect.height,
1273 plane_state->src_rect.width,
1274 plane_state->src_rect.x,
1275 plane_state->src_rect.y,
1276 plane_state->dst_rect.height,
1277 plane_state->dst_rect.width,
1278 plane_state->dst_rect.x,
1279 plane_state->dst_rect.y,
1280 plane_state->clip_rect.height,
1281 plane_state->clip_rect.width,
1282 plane_state->clip_rect.x,
1283 plane_state->clip_rect.y);
4562236b 1284
89d07b66
ST		 1285 if (store_h_border_left)
1286 restore_border_left_from_dst(pipe_ctx, store_h_border_left);
1287
4562236b
HW		 1288 return res;
1289}
1290
1291
1292enum dc_status resource_build_scaling_params_for_context(
fb3466a4 1293 const struct dc *dc,
608ac7bb 1294 struct dc_state *context)
4562236b
HW		 1295{
1296 int i;
1297
1298 for (i = 0; i < MAX_PIPES; i++) {
3be5262e 1299 if (context->res_ctx.pipe_ctx[i].plane_state != NULL &&
4562236b 1300 context->res_ctx.pipe_ctx[i].stream != NULL)
b2d0a103 1301 if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i]))
f84a8161 1302 return DC_FAIL_SCALING;
4562236b
HW		 1303 }
1304
1305 return DC_OK;
1306}
1307
a2b8659d
TC		 1308struct pipe_ctx *find_idle_secondary_pipe(
1309 struct resource_context *res_ctx,
5581192d
JL		 1310 const struct resource_pool *pool,
1311 const struct pipe_ctx *primary_pipe)
4562236b
HW		 1312{
1313 int i;
1314 struct pipe_ctx *secondary_pipe = NULL;
1315
1316 /*
5581192d
JL		 1317 * We add a preferred pipe mapping to avoid the chance that
1318 * MPCCs already in use will need to be reassigned to other trees.
1319 * For example, if we went with the strict, assign backwards logic:
1320 *
1321 * (State 1)
1322 * Display A on, no surface, top pipe = 0
1323 * Display B on, no surface, top pipe = 1
1324 *
1325 * (State 2)
1326 * Display A on, no surface, top pipe = 0
1327 * Display B on, surface enable, top pipe = 1, bottom pipe = 5
1328 *
1329 * (State 3)
1330 * Display A on, surface enable, top pipe = 0, bottom pipe = 5
1331 * Display B on, surface enable, top pipe = 1, bottom pipe = 4
1332 *
1333 * The state 2->3 transition requires remapping MPCC 5 from display B
1334 * to display A.
1335 *
1336 * However, with the preferred pipe logic, state 2 would look like:
1337 *
1338 * (State 2)
1339 * Display A on, no surface, top pipe = 0
1340 * Display B on, surface enable, top pipe = 1, bottom pipe = 4
1341 *
1342 * This would then cause 2->3 to not require remapping any MPCCs.
4562236b 1343 */
5581192d
JL		 1344 if (primary_pipe) {
1345 int preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx;
1346 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
1347 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
1348 secondary_pipe->pipe_idx = preferred_pipe_idx;
4562236b
HW		 1349 }
1350 }
1351
5581192d
JL		 1352 /*
1353 * search backwards for the second pipe to keep pipe
1354 * assignment more consistent
1355 */
1356 if (!secondary_pipe)
1357 for (i = pool->pipe_count - 1; i >= 0; i--) {
1358 if (res_ctx->pipe_ctx[i].stream == NULL) {
1359 secondary_pipe = &res_ctx->pipe_ctx[i];
1360 secondary_pipe->pipe_idx = i;
1361 break;
1362 }
1363 }
4562236b
HW		 1364
1365 return secondary_pipe;
1366}
1367
1368struct pipe_ctx *resource_get_head_pipe_for_stream(
1369 struct resource_context *res_ctx,
0971c40e 1370 struct dc_stream_state *stream)
4562236b
HW		 1371{
1372 int i;
22498036 1373
a2b8659d 1374 for (i = 0; i < MAX_PIPES; i++) {
b1f6d01c
DL		 1375 if (res_ctx->pipe_ctx[i].stream == stream
1376 && !res_ctx->pipe_ctx[i].top_pipe
22498036 1377 && !res_ctx->pipe_ctx[i].prev_odm_pipe)
4562236b 1378 return &res_ctx->pipe_ctx[i];
4562236b
HW		 1379 }
1380 return NULL;
1381}
1382
b1f6d01c 1383static struct pipe_ctx *resource_get_tail_pipe(
19f89e23 1384 struct resource_context *res_ctx,
b1f6d01c 1385 struct pipe_ctx *head_pipe)
19f89e23 1386{
b1f6d01c 1387 struct pipe_ctx *tail_pipe;
19f89e23
AG		 1388
1389 tail_pipe = head_pipe->bottom_pipe;
1390
1391 while (tail_pipe) {
1392 head_pipe = tail_pipe;
1393 tail_pipe = tail_pipe->bottom_pipe;
1394 }
1395
1396 return head_pipe;
1397}
1398
4562236b 1399/*
ab2541b6
AC		 1400 * A free_pipe for a stream is defined here as a pipe
1401 * that has no surface attached yet
4562236b 1402 */
b1f6d01c 1403static struct pipe_ctx *acquire_free_pipe_for_head(
608ac7bb 1404 struct dc_state *context,
a2b8659d 1405 const struct resource_pool *pool,
b1f6d01c 1406 struct pipe_ctx *head_pipe)
4562236b
HW		 1407{
1408 int i;
745cc746 1409 struct resource_context *res_ctx = &context->res_ctx;
4562236b 1410
3be5262e 1411 if (!head_pipe->plane_state)
4562236b
HW		 1412 return head_pipe;
1413
1414 /* Re-use pipe already acquired for this stream if available*/
a2b8659d 1415 for (i = pool->pipe_count - 1; i >= 0; i--) {
b1f6d01c 1416 if (res_ctx->pipe_ctx[i].stream == head_pipe->stream &&
3be5262e 1417 !res_ctx->pipe_ctx[i].plane_state) {
4562236b
HW		 1418 return &res_ctx->pipe_ctx[i];
1419 }
1420 }
1421
1422 /*
1423 * At this point we have no re-useable pipe for this stream and we need
1424 * to acquire an idle one to satisfy the request
1425 */
1426
a2b8659d 1427 if (!pool->funcs->acquire_idle_pipe_for_layer)
4562236b
HW		 1428 return NULL;
1429
b1f6d01c 1430 return pool->funcs->acquire_idle_pipe_for_layer(context, pool, head_pipe->stream);
4562236b
HW		 1431}
1432
b86a1aa3 1433#if defined(CONFIG_DRM_AMD_DC_DCN)
0f9a536f
DL		 1434static int acquire_first_split_pipe(
1435 struct resource_context *res_ctx,
1436 const struct resource_pool *pool,
0971c40e 1437 struct dc_stream_state *stream)
0f9a536f
DL		 1438{
1439 int i;
1440
1441 for (i = 0; i < pool->pipe_count; i++) {
79592db3
DL		 1442 struct pipe_ctx *split_pipe = &res_ctx->pipe_ctx[i];
1443
b1f6d01c 1444 if (split_pipe->top_pipe &&
79592db3
DL		 1445 split_pipe->top_pipe->plane_state == split_pipe->plane_state) {
1446 split_pipe->top_pipe->bottom_pipe = split_pipe->bottom_pipe;
1447 if (split_pipe->bottom_pipe)
1448 split_pipe->bottom_pipe->top_pipe = split_pipe->top_pipe;
1449
1450 if (split_pipe->top_pipe->plane_state)
1451 resource_build_scaling_params(split_pipe->top_pipe);
1452
1453 memset(split_pipe, 0, sizeof(*split_pipe));
1454 split_pipe->stream_res.tg = pool->timing_generators[i];
1455 split_pipe->plane_res.hubp = pool->hubps[i];
1456 split_pipe->plane_res.ipp = pool->ipps[i];
1457 split_pipe->plane_res.dpp = pool->dpps[i];
1458 split_pipe->stream_res.opp = pool->opps[i];
1459 split_pipe->plane_res.mpcc_inst = pool->dpps[i]->inst;
1460 split_pipe->pipe_idx = i;
1461
1462 split_pipe->stream = stream;
0f9a536f
DL		 1463 return i;
1464 }
1465 }
1466 return -1;
1467}
1468#endif
1469
19f89e23
AG		 1470bool dc_add_plane_to_context(
1471 const struct dc *dc,
0971c40e 1472 struct dc_stream_state *stream,
19f89e23 1473 struct dc_plane_state *plane_state,
608ac7bb 1474 struct dc_state *context)
4562236b
HW		 1475{
1476 int i;
19f89e23
AG		 1477 struct resource_pool *pool = dc->res_pool;
1478 struct pipe_ctx *head_pipe, *tail_pipe, *free_pipe;
ab2541b6 1479 struct dc_stream_status *stream_status = NULL;
4562236b 1480
19f89e23
AG		 1481 for (i = 0; i < context->stream_count; i++)
1482 if (context->streams[i] == stream) {
1483 stream_status = &context->stream_status[i];
1484 break;
1485 }
1486 if (stream_status == NULL) {
1487 dm_error("Existing stream not found; failed to attach surface!\n");
1488 return false;
1489 }
1490
4562236b 1491
19f89e23
AG		 1492 if (stream_status->plane_count == MAX_SURFACE_NUM) {
1493 dm_error("Surface: can not attach plane_state %p! Maximum is: %d\n",
1494 plane_state, MAX_SURFACE_NUM);
4562236b
HW		 1495 return false;
1496 }
1497
19f89e23
AG		 1498 head_pipe = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
1499
1500 if (!head_pipe) {
1501 dm_error("Head pipe not found for stream_state %p !\n", stream);
1502 return false;
1503 }
1504
b1f6d01c
DL		 1505 /* retain new surface, but only once per stream */
1506 dc_plane_state_retain(plane_state);
00737c59 1507
b1f6d01c 1508 while (head_pipe) {
b1f6d01c 1509 free_pipe = acquire_free_pipe_for_head(context, pool, head_pipe);
19f89e23 1510
b86a1aa3 1511 #if defined(CONFIG_DRM_AMD_DC_DCN)
b1f6d01c
DL		 1512 if (!free_pipe) {
1513 int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
1514 if (pipe_idx >= 0)
1515 free_pipe = &context->res_ctx.pipe_ctx[pipe_idx];
1516 }
1517 #endif
1518 if (!free_pipe) {
1519 dc_plane_state_release(plane_state);
1520 return false;
1521 }
19f89e23 1522
b1f6d01c
DL		 1523 free_pipe->plane_state = plane_state;
1524
1525 if (head_pipe != free_pipe) {
5b5c1777
JP		 1526 tail_pipe = resource_get_tail_pipe(&context->res_ctx, head_pipe);
1527 ASSERT(tail_pipe);
b1f6d01c
DL		 1528 free_pipe->stream_res.tg = tail_pipe->stream_res.tg;
1529 free_pipe->stream_res.abm = tail_pipe->stream_res.abm;
1530 free_pipe->stream_res.opp = tail_pipe->stream_res.opp;
1531 free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc;
1532 free_pipe->stream_res.audio = tail_pipe->stream_res.audio;
1533 free_pipe->clock_source = tail_pipe->clock_source;
1534 free_pipe->top_pipe = tail_pipe;
1535 tail_pipe->bottom_pipe = free_pipe;
2e7b43e6
DL		 1536 if (!free_pipe->next_odm_pipe && tail_pipe->next_odm_pipe && tail_pipe->next_odm_pipe->bottom_pipe) {
1537 free_pipe->next_odm_pipe = tail_pipe->next_odm_pipe->bottom_pipe;
1538 tail_pipe->next_odm_pipe->bottom_pipe->prev_odm_pipe = free_pipe;
1539 }
1540 if (!free_pipe->prev_odm_pipe && tail_pipe->prev_odm_pipe && tail_pipe->prev_odm_pipe->bottom_pipe) {
1541 free_pipe->prev_odm_pipe = tail_pipe->prev_odm_pipe->bottom_pipe;
1542 tail_pipe->prev_odm_pipe->bottom_pipe->next_odm_pipe = free_pipe;
1543 }
b1f6d01c
DL		 1544 }
1545 head_pipe = head_pipe->next_odm_pipe;
1546 }
19f89e23
AG		 1547 /* assign new surfaces*/
1548 stream_status->plane_states[stream_status->plane_count] = plane_state;
1549
1550 stream_status->plane_count++;
1551
1552 return true;
1553}
1554
1555bool dc_remove_plane_from_context(
1556 const struct dc *dc,
1557 struct dc_stream_state *stream,
1558 struct dc_plane_state *plane_state,
608ac7bb 1559 struct dc_state *context)
19f89e23
AG		 1560{
1561 int i;
1562 struct dc_stream_status *stream_status = NULL;
1563 struct resource_pool *pool = dc->res_pool;
1564
ab2541b6 1565 for (i = 0; i < context->stream_count; i++)
4fa086b9 1566 if (context->streams[i] == stream) {
ab2541b6 1567 stream_status = &context->stream_status[i];
4562236b
HW		 1568 break;
1569 }
19f89e23 1570
ab2541b6 1571 if (stream_status == NULL) {
19f89e23 1572 dm_error("Existing stream not found; failed to remove plane.\n");
4562236b
HW		 1573 return false;
1574 }
1575
19f89e23
AG		 1576 /* release pipe for plane*/
1577 for (i = pool->pipe_count - 1; i >= 0; i--) {
6ffaa6fc 1578 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
4562236b 1579
6ffaa6fc 1580 if (pipe_ctx->plane_state == plane_state) {
19f89e23
AG		 1581 if (pipe_ctx->top_pipe)
1582 pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;
4562236b 1583
19f89e23
AG		 1584 /* Second condition is to avoid setting NULL to top pipe
1585 * of tail pipe making it look like head pipe in subsequent
1586 * deletes
1587 */
1588 if (pipe_ctx->bottom_pipe && pipe_ctx->top_pipe)
1589 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;
4562236b 1590
19f89e23
AG		 1591 /*
1592 * For head pipe detach surfaces from pipe for tail
1593 * pipe just zero it out
1594 */
b1f6d01c 1595 if (!pipe_ctx->top_pipe)
19f89e23 1596 pipe_ctx->plane_state = NULL;
b1f6d01c 1597 else
19f89e23 1598 memset(pipe_ctx, 0, sizeof(*pipe_ctx));
4562236b 1599 }
19f89e23 1600 }
4562236b 1601
4562236b 1602
19f89e23
AG		 1603 for (i = 0; i < stream_status->plane_count; i++) {
1604 if (stream_status->plane_states[i] == plane_state) {
1605
1606 dc_plane_state_release(stream_status->plane_states[i]);
1607 break;
4562236b 1608 }
19f89e23 1609 }
4562236b 1610
19f89e23
AG		 1611 if (i == stream_status->plane_count) {
1612 dm_error("Existing plane_state not found; failed to detach it!\n");
1613 return false;
4562236b
HW		 1614 }
1615
19f89e23 1616 stream_status->plane_count--;
4562236b 1617
abb4986e
AJ		 1618 /* Start at the plane we've just released, and move all the planes one index forward to "trim" the array */
1619 for (; i < stream_status->plane_count; i++)
19f89e23
AG		 1620 stream_status->plane_states[i] = stream_status->plane_states[i + 1];
1621
1622 stream_status->plane_states[stream_status->plane_count] = NULL;
1623
1624 return true;
1625}
1626
1627bool dc_rem_all_planes_for_stream(
1628 const struct dc *dc,
1629 struct dc_stream_state *stream,
608ac7bb 1630 struct dc_state *context)
19f89e23
AG		 1631{
1632 int i, old_plane_count;
1633 struct dc_stream_status *stream_status = NULL;
1634 struct dc_plane_state *del_planes[MAX_SURFACE_NUM] = { 0 };
1635
1636 for (i = 0; i < context->stream_count; i++)
1637 if (context->streams[i] == stream) {
1638 stream_status = &context->stream_status[i];
1639 break;
1640 }
1641
1642 if (stream_status == NULL) {
1643 dm_error("Existing stream %p not found!\n", stream);
1644 return false;
1645 }
1646
1647 old_plane_count = stream_status->plane_count;
1648
1649 for (i = 0; i < old_plane_count; i++)
1650 del_planes[i] = stream_status->plane_states[i];
1651
1652 for (i = 0; i < old_plane_count; i++)
1653 if (!dc_remove_plane_from_context(dc, stream, del_planes[i], context))
1654 return false;
1655
1656 return true;
1657}
1658
1659static bool add_all_planes_for_stream(
1660 const struct dc *dc,
1661 struct dc_stream_state *stream,
1662 const struct dc_validation_set set[],
1663 int set_count,
608ac7bb 1664 struct dc_state *context)
19f89e23
AG		 1665{
1666 int i, j;
1667
1668 for (i = 0; i < set_count; i++)
1669 if (set[i].stream == stream)
1670 break;
1671
1672 if (i == set_count) {
1673 dm_error("Stream %p not found in set!\n", stream);
1674 return false;
1675 }
4562236b 1676
19f89e23
AG		 1677 for (j = 0; j < set[i].plane_count; j++)
1678 if (!dc_add_plane_to_context(dc, stream, set[i].plane_states[j], context))
1679 return false;
4562236b
HW		 1680
1681 return true;
1682}
1683
19f89e23
AG		 1684bool dc_add_all_planes_for_stream(
1685 const struct dc *dc,
1686 struct dc_stream_state *stream,
1687 struct dc_plane_state * const *plane_states,
1688 int plane_count,
608ac7bb 1689 struct dc_state *context)
19f89e23
AG		 1690{
1691 struct dc_validation_set set;
1692 int i;
1693
1694 set.stream = stream;
1695 set.plane_count = plane_count;
1696
1697 for (i = 0; i < plane_count; i++)
1698 set.plane_states[i] = plane_states[i];
1699
1700 return add_all_planes_for_stream(dc, stream, &set, 1, context);
1701}
1702
0971c40e
HW		 1703static bool is_timing_changed(struct dc_stream_state *cur_stream,
1704 struct dc_stream_state *new_stream)
4562236b
HW		 1705{
1706 if (cur_stream == NULL)
1707 return true;
1708
4562236b 1709 /* If output color space is changed, need to reprogram info frames */
4fa086b9 1710 if (cur_stream->output_color_space != new_stream->output_color_space)
4562236b
HW		 1711 return true;
1712
1713 return memcmp(
4fa086b9
LSL		 1714 &cur_stream->timing,
1715 &new_stream->timing,
4562236b
HW		 1716 sizeof(struct dc_crtc_timing)) != 0;
1717}
1718
1719static bool are_stream_backends_same(
0971c40e 1720 struct dc_stream_state *stream_a, struct dc_stream_state *stream_b)
4562236b
HW		 1721{
1722 if (stream_a == stream_b)
1723 return true;
1724
1725 if (stream_a == NULL || stream_b == NULL)
1726 return false;
1727
1728 if (is_timing_changed(stream_a, stream_b))
1729 return false;
1730
1e7e86c4
ST		 1731 if (stream_a->dpms_off != stream_b->dpms_off)
1732 return false;
1733
4562236b
HW		 1734 return true;
1735}
1736
625a15bf 1737/*
2119aa17
DF		 1738 * dc_is_stream_unchanged() - Compare two stream states for equivalence.
1739 *
1740 * Checks if there a difference between the two states
1741 * that would require a mode change.
1742 *
1743 * Does not compare cursor position or attributes.
1744 */
d54d29db 1745bool dc_is_stream_unchanged(
0971c40e 1746 struct dc_stream_state *old_stream, struct dc_stream_state *stream)
4562236b 1747{
4562236b 1748
ab2541b6
AC		 1749 if (!are_stream_backends_same(old_stream, stream))
1750 return false;
4562236b 1751
0460f9ab
JL		 1752 if (old_stream->ignore_msa_timing_param != stream->ignore_msa_timing_param)
1753 return false;
1754
4562236b
HW		 1755 return true;
1756}
1757
625a15bf 1758/*
2119aa17
DF		 1759 * dc_is_stream_scaling_unchanged() - Compare scaling rectangles of two streams.
1760 */
9a5d9c48
LSL		 1761bool dc_is_stream_scaling_unchanged(
1762 struct dc_stream_state *old_stream, struct dc_stream_state *stream)
1763{
1764 if (old_stream == stream)
1765 return true;
1766
1767 if (old_stream == NULL || stream == NULL)
1768 return false;
1769
1770 if (memcmp(&old_stream->src,
1771 &stream->src,
1772 sizeof(struct rect)) != 0)
1773 return false;
1774
1775 if (memcmp(&old_stream->dst,
1776 &stream->dst,
1777 sizeof(struct rect)) != 0)
1778 return false;
1779
1780 return true;
1781}
1782
1dc90497 1783static void update_stream_engine_usage(
4562236b 1784 struct resource_context *res_ctx,
a2b8659d 1785 const struct resource_pool *pool,
1dc90497
AG		 1786 struct stream_encoder *stream_enc,
1787 bool acquired)
4562236b
HW		 1788{
1789 int i;
1790
a2b8659d
TC		 1791 for (i = 0; i < pool->stream_enc_count; i++) {
1792 if (pool->stream_enc[i] == stream_enc)
1dc90497 1793 res_ctx->is_stream_enc_acquired[i] = acquired;
4562236b
HW		 1794 }
1795}
1796
1797/* TODO: release audio object */
4176664b 1798void update_audio_usage(
4562236b 1799 struct resource_context *res_ctx,
a2b8659d 1800 const struct resource_pool *pool,
1dc90497
AG		 1801 struct audio *audio,
1802 bool acquired)
4562236b
HW		 1803{
1804 int i;
a2b8659d
TC		 1805 for (i = 0; i < pool->audio_count; i++) {
1806 if (pool->audios[i] == audio)
1dc90497 1807 res_ctx->is_audio_acquired[i] = acquired;
4562236b
HW		 1808 }
1809}
1810
1811static int acquire_first_free_pipe(
1812 struct resource_context *res_ctx,
a2b8659d 1813 const struct resource_pool *pool,
0971c40e 1814 struct dc_stream_state *stream)
4562236b
HW		 1815{
1816 int i;
1817
a2b8659d 1818 for (i = 0; i < pool->pipe_count; i++) {
4562236b
HW		 1819 if (!res_ctx->pipe_ctx[i].stream) {
1820 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
1821
6b670fa9 1822 pipe_ctx->stream_res.tg = pool->timing_generators[i];
86a66c4e 1823 pipe_ctx->plane_res.mi = pool->mis[i];
8feabd03 1824 pipe_ctx->plane_res.hubp = pool->hubps[i];
86a66c4e
HW		 1825 pipe_ctx->plane_res.ipp = pool->ipps[i];
1826 pipe_ctx->plane_res.xfm = pool->transforms[i];
d94585a0 1827 pipe_ctx->plane_res.dpp = pool->dpps[i];
a6a6cb34 1828 pipe_ctx->stream_res.opp = pool->opps[i];
bc373a89
RL		 1829 if (pool->dpps[i])
1830 pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst;
4562236b
HW		 1831 pipe_ctx->pipe_idx = i;
1832
ff5ef992 1833
4562236b
HW		 1834 pipe_ctx->stream = stream;
1835 return i;
1836 }
1837 }
1838 return -1;
1839}
1840
a2b8659d
TC		 1841static struct audio *find_first_free_audio(
1842 struct resource_context *res_ctx,
cfb071f7 1843 const struct resource_pool *pool,
f24b0522
PH		 1844 enum engine_id id,
1845 enum dce_version dc_version)
4562236b 1846{
b5a41620
CL		 1847 int i, available_audio_count;
1848
1849 available_audio_count = pool->audio_count;
1850
1851 for (i = 0; i < available_audio_count; i++) {
66bfd4fd 1852 if ((res_ctx->is_audio_acquired[i] == false) && (res_ctx->is_stream_enc_acquired[i] == true)) {
cfb071f7
CL		 1853 /*we have enough audio endpoint, find the matching inst*/
1854 if (id != i)
1855 continue;
66bfd4fd 1856 return pool->audios[i];
4562236b 1857 }
66bfd4fd 1858 }
5feb9f07 1859
b5a41620
CL		 1860 /* use engine id to find free audio */
1861 if ((id < available_audio_count) && (res_ctx->is_audio_acquired[id] == false)) {
5feb9f07
TM		 1862 return pool->audios[id];
1863 }
66bfd4fd 1864 /*not found the matching one, first come first serve*/
b5a41620 1865 for (i = 0; i < available_audio_count; i++) {
66bfd4fd
CL		 1866 if (res_ctx->is_audio_acquired[i] == false) {
1867 return pool->audios[i];
4176664b
CL		 1868 }
1869 }
4562236b
HW		 1870 return 0;
1871}
1872
625a15bf 1873/*
2119aa17
DF		 1874 * dc_add_stream_to_ctx() - Add a new dc_stream_state to a dc_state.
1875 */
13ab1b44 1876enum dc_status dc_add_stream_to_ctx(
1dc90497 1877 struct dc *dc,
608ac7bb 1878 struct dc_state *new_ctx,
1dc90497
AG		 1879 struct dc_stream_state *stream)
1880{
1dc90497 1881 enum dc_status res;
eb9714a2 1882 DC_LOGGER_INIT(dc->ctx->logger);
1dc90497 1883
ece4147f 1884 if (new_ctx->stream_count >= dc->res_pool->timing_generator_count) {
eb9714a2 1885 DC_LOG_WARNING("Max streams reached, can't add stream %p !\n", stream);
1dc90497
AG		 1886 return DC_ERROR_UNEXPECTED;
1887 }
1888
1889 new_ctx->streams[new_ctx->stream_count] = stream;
1890 dc_stream_retain(stream);
1891 new_ctx->stream_count++;
1892
1893 res = dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream);
1894 if (res != DC_OK)
eb9714a2 1895 DC_LOG_WARNING("Adding stream %p to context failed with err %d!\n", stream, res);
1dc90497 1896
13ab1b44 1897 return res;
1dc90497
AG		 1898}
1899
625a15bf 1900/*
2119aa17
DF		 1901 * dc_remove_stream_from_ctx() - Remove a stream from a dc_state.
1902 */
62c933f9 1903enum dc_status dc_remove_stream_from_ctx(
1dc90497 1904 struct dc *dc,
608ac7bb 1905 struct dc_state *new_ctx,
1dc90497
AG		 1906 struct dc_stream_state *stream)
1907{
19f89e23 1908 int i;
1dc90497 1909 struct dc_context *dc_ctx = dc->ctx;
22498036
DL		 1910 struct pipe_ctx *del_pipe = resource_get_head_pipe_for_stream(&new_ctx->res_ctx, stream);
1911 struct pipe_ctx *odm_pipe;
1dc90497
AG		 1912
1913 if (!del_pipe) {
1914 DC_ERROR("Pipe not found for stream %p !\n", stream);
1915 return DC_ERROR_UNEXPECTED;
1916 }
1917
22498036
DL		 1918 odm_pipe = del_pipe->next_odm_pipe;
1919
1920 /* Release primary pipe */
1921 ASSERT(del_pipe->stream_res.stream_enc);
1922 update_stream_engine_usage(
1923 &new_ctx->res_ctx,
1924 dc->res_pool,
1925 del_pipe->stream_res.stream_enc,
1926 false);
f42ef862
JK		 1927 /* Release link encoder from stream in new dc_state. */
1928 if (dc->res_pool->funcs->link_enc_unassign)
1929 dc->res_pool->funcs->link_enc_unassign(new_ctx, del_pipe->stream);
22498036
DL		 1930
1931 if (del_pipe->stream_res.audio)
1932 update_audio_usage(
1933 &new_ctx->res_ctx,
1934 dc->res_pool,
1935 del_pipe->stream_res.audio,
1936 false);
1937
1938 resource_unreference_clock_source(&new_ctx->res_ctx,
1939 dc->res_pool,
1940 del_pipe->clock_source);
1941
1942 if (dc->res_pool->funcs->remove_stream_from_ctx)
1943 dc->res_pool->funcs->remove_stream_from_ctx(dc, new_ctx, stream);
1944
1945 while (odm_pipe) {
1946 struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe;
1947
1948 memset(odm_pipe, 0, sizeof(*odm_pipe));
1949 odm_pipe = next_odm_pipe;
1950 }
1951 memset(del_pipe, 0, sizeof(*del_pipe));
1952
1dc90497
AG		 1953 for (i = 0; i < new_ctx->stream_count; i++)
1954 if (new_ctx->streams[i] == stream)
1955 break;
1956
1957 if (new_ctx->streams[i] != stream) {
1958 DC_ERROR("Context doesn't have stream %p !\n", stream);
1959 return DC_ERROR_UNEXPECTED;
1960 }
1961
1962 dc_stream_release(new_ctx->streams[i]);
1963 new_ctx->stream_count--;
1964
1dc90497
AG		 1965 /* Trim back arrays */
1966 for (; i < new_ctx->stream_count; i++) {
1967 new_ctx->streams[i] = new_ctx->streams[i + 1];
1968 new_ctx->stream_status[i] = new_ctx->stream_status[i + 1];
1969 }
1970
1971 new_ctx->streams[new_ctx->stream_count] = NULL;
1972 memset(
1973 &new_ctx->stream_status[new_ctx->stream_count],
1974 0,
1975 sizeof(new_ctx->stream_status[0]));
1976
1977 return DC_OK;
1978}
1979
0971c40e
HW		 1980static struct dc_stream_state *find_pll_sharable_stream(
1981 struct dc_stream_state *stream_needs_pll,
608ac7bb 1982 struct dc_state *context)
4562236b 1983{
ab2541b6 1984 int i;
4562236b 1985
ab2541b6 1986 for (i = 0; i < context->stream_count; i++) {
0971c40e 1987 struct dc_stream_state *stream_has_pll = context->streams[i];
4562236b 1988
ab2541b6
AC		 1989 /* We are looking for non dp, non virtual stream */
1990 if (resource_are_streams_timing_synchronizable(
1991 stream_needs_pll, stream_has_pll)
1992 && !dc_is_dp_signal(stream_has_pll->signal)
ceb3dbb4 1993 && stream_has_pll->link->connector_signal
ab2541b6
AC		 1994 != SIGNAL_TYPE_VIRTUAL)
1995 return stream_has_pll;
4562236b 1996
4562236b
HW		 1997 }
1998
1999 return NULL;
2000}
2001
2002static int get_norm_pix_clk(const struct dc_crtc_timing *timing)
2003{
380604e2 2004 uint32_t pix_clk = timing->pix_clk_100hz;
4562236b
HW		 2005 uint32_t normalized_pix_clk = pix_clk;
2006
2007 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
2008 pix_clk /= 2;
cc4d99b8
CL		 2009 if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) {
2010 switch (timing->display_color_depth) {
8897810a 2011 case COLOR_DEPTH_666:
cc4d99b8
CL		 2012 case COLOR_DEPTH_888:
2013 normalized_pix_clk = pix_clk;
2014 break;
2015 case COLOR_DEPTH_101010:
2016 normalized_pix_clk = (pix_clk * 30) / 24;
2017 break;
2018 case COLOR_DEPTH_121212:
2019 normalized_pix_clk = (pix_clk * 36) / 24;
4562236b 2020 break;
cc4d99b8
CL		 2021 case COLOR_DEPTH_161616:
2022 normalized_pix_clk = (pix_clk * 48) / 24;
4562236b 2023 break;
cc4d99b8
CL		 2024 default:
2025 ASSERT(0);
4562236b 2026 break;
cc4d99b8 2027 }
4562236b 2028 }
4562236b
HW		 2029 return normalized_pix_clk;
2030}
2031
0971c40e 2032static void calculate_phy_pix_clks(struct dc_stream_state *stream)
4562236b 2033{
9345d987
AG		 2034 /* update actual pixel clock on all streams */
2035 if (dc_is_hdmi_signal(stream->signal))
2036 stream->phy_pix_clk = get_norm_pix_clk(
380604e2 2037 &stream->timing) / 10;
9345d987
AG		 2038 else
2039 stream->phy_pix_clk =
380604e2 2040 stream->timing.pix_clk_100hz / 10;
39c03e00
CL		 2041
2042 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
2043 stream->phy_pix_clk *= 2;
4562236b
HW		 2044}
2045
d2d7885f
AK		 2046static int acquire_resource_from_hw_enabled_state(
2047 struct resource_context *res_ctx,
2048 const struct resource_pool *pool,
2049 struct dc_stream_state *stream)
2050{
2051 struct dc_link *link = stream->link;
08b66279 2052 unsigned int i, inst, tg_inst = 0;
d2d7885f
AK		 2053
2054 /* Check for enabled DIG to identify enabled display */
2055 if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
2056 return -1;
2057
5ec43eda 2058 inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
d2d7885f 2059
7f7652ee 2060 if (inst == ENGINE_ID_UNKNOWN)
75441d9d 2061 return -1;
d2d7885f 2062
7f7652ee
ML		 2063 for (i = 0; i < pool->stream_enc_count; i++) {
2064 if (pool->stream_enc[i]->id == inst) {
2065 tg_inst = pool->stream_enc[i]->funcs->dig_source_otg(
2066 pool->stream_enc[i]);
2067 break;
2068 }
2069 }
5ec43eda 2070
7f7652ee
ML		 2071 // tg_inst not found
2072 if (i == pool->stream_enc_count)
75441d9d 2073 return -1;
5ec43eda
ML		 2074
2075 if (tg_inst >= pool->timing_generator_count)
75441d9d 2076 return -1;
5ec43eda
ML		 2077
2078 if (!res_ctx->pipe_ctx[tg_inst].stream) {
2079 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[tg_inst];
2080
2081 pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];
2082 pipe_ctx->plane_res.mi = pool->mis[tg_inst];
2083 pipe_ctx->plane_res.hubp = pool->hubps[tg_inst];
2084 pipe_ctx->plane_res.ipp = pool->ipps[tg_inst];
2085 pipe_ctx->plane_res.xfm = pool->transforms[tg_inst];
2086 pipe_ctx->plane_res.dpp = pool->dpps[tg_inst];
2087 pipe_ctx->stream_res.opp = pool->opps[tg_inst];
d2d7885f 2088
ccce745c 2089 if (pool->dpps[tg_inst]) {
5ec43eda 2090 pipe_ctx->plane_res.mpcc_inst = pool->dpps[tg_inst]->inst;
ccce745c
ML		 2091
2092 // Read DPP->MPCC->OPP Pipe from HW State
2093 if (pool->mpc->funcs->read_mpcc_state) {
2094 struct mpcc_state s = {0};
2095
2096 pool->mpc->funcs->read_mpcc_state(pool->mpc, pipe_ctx->plane_res.mpcc_inst, &s);
2097
2098 if (s.dpp_id < MAX_MPCC)
2099 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].dpp_id = s.dpp_id;
2100
2101 if (s.bot_mpcc_id < MAX_MPCC)
2102 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].mpcc_bot =
2103 &pool->mpc->mpcc_array[s.bot_mpcc_id];
2104
2105 if (s.opp_id < MAX_OPP)
2106 pipe_ctx->stream_res.opp->mpc_tree_params.opp_id = s.opp_id;
2107 }
2108 }
5ec43eda 2109 pipe_ctx->pipe_idx = tg_inst;
d2d7885f
AK		 2110
2111 pipe_ctx->stream = stream;
5ec43eda 2112 return tg_inst;
d2d7885f
AK		 2113 }
2114
2115 return -1;
2116}
2117
96b5e3e1
RY		 2118static void mark_seamless_boot_stream(
2119 const struct dc *dc,
2120 struct dc_stream_state *stream)
2121{
2122 struct dc_bios *dcb = dc->ctx->dc_bios;
2123
2124 /* TODO: Check Linux */
2125 if (dc->config.allow_seamless_boot_optimization &&
2126 !dcb->funcs->is_accelerated_mode(dcb)) {
2127 if (dc_validate_seamless_boot_timing(dc, stream->sink, &stream->timing))
2128 stream->apply_seamless_boot_optimization = true;
2129 }
2130}
2131
4562236b 2132enum dc_status resource_map_pool_resources(
fb3466a4 2133 const struct dc *dc,
608ac7bb 2134 struct dc_state *context,
1dc90497 2135 struct dc_stream_state *stream)
4562236b 2136{
a2b8659d 2137 const struct resource_pool *pool = dc->res_pool;
1dc90497
AG		 2138 int i;
2139 struct dc_context *dc_ctx = dc->ctx;
2140 struct pipe_ctx *pipe_ctx = NULL;
2141 int pipe_idx = -1;
4562236b 2142
08e1c28d
YMM		 2143 calculate_phy_pix_clks(stream);
2144
96b5e3e1 2145 mark_seamless_boot_stream(dc, stream);
46570f09 2146
96b5e3e1 2147 if (stream->apply_seamless_boot_optimization) {
d2d7885f
AK		 2148 pipe_idx = acquire_resource_from_hw_enabled_state(
2149 &context->res_ctx,
2150 pool,
2151 stream);
96b5e3e1
RY		 2152 if (pipe_idx < 0)
2153 /* hw resource was assigned to other stream */
2154 stream->apply_seamless_boot_optimization = false;
2155 }
d2d7885f
AK		 2156
2157 if (pipe_idx < 0)
2158 /* acquire new resources */
2159 pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream);
8c737fcc 2160
b86a1aa3 2161#ifdef CONFIG_DRM_AMD_DC_DCN
1dc90497 2162 if (pipe_idx < 0)
13ab1b44 2163 pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
94c6d735 2164#endif
13ab1b44 2165
c5b38aec 2166 if (pipe_idx < 0 || context->res_ctx.pipe_ctx[pipe_idx].stream_res.tg == NULL)
1dc90497
AG		 2167 return DC_NO_CONTROLLER_RESOURCE;
2168
2169 pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
2170
2171 pipe_ctx->stream_res.stream_enc =
78cc70b1 2172 dc->res_pool->funcs->find_first_free_match_stream_enc_for_link(
1dc90497
AG		 2173 &context->res_ctx, pool, stream);
2174
2175 if (!pipe_ctx->stream_res.stream_enc)
38684e46 2176 return DC_NO_STREAM_ENC_RESOURCE;
1dc90497
AG		 2177
2178 update_stream_engine_usage(
2179 &context->res_ctx, pool,
2180 pipe_ctx->stream_res.stream_enc,
2181 true);
2182
2183 /* TODO: Add check if ASIC support and EDID audio */
ceb3dbb4 2184 if (!stream->converter_disable_audio &&
1dc90497 2185 dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&
ce08aad3 2186 stream->audio_info.mode_count && stream->audio_info.flags.all) {
1dc90497 2187 pipe_ctx->stream_res.audio = find_first_free_audio(
f24b0522 2188 &context->res_ctx, pool, pipe_ctx->stream_res.stream_enc->id, dc_ctx->dce_version);
1dc90497
AG		 2189
2190 /*
2191 * Audio assigned in order first come first get.
2192 * There are asics which has number of audio
2193 * resources less then number of pipes
2194 */
2195 if (pipe_ctx->stream_res.audio)
2196 update_audio_usage(&context->res_ctx, pool,
2197 pipe_ctx->stream_res.audio, true);
2198 }
268cadbd 2199
9aef1a31 2200 /* Add ABM to the resource if on EDP */
5dba4991 2201 if (pipe_ctx->stream && dc_is_embedded_signal(pipe_ctx->stream->signal)) {
20f2ffe5 2202#if defined(CONFIG_DRM_AMD_DC_DCN)
5dba4991
BL		 2203 if (pool->abm)
2204 pipe_ctx->stream_res.abm = pool->abm;
2205 else
2206 pipe_ctx->stream_res.abm = pool->multiple_abms[pipe_ctx->stream_res.tg->inst];
2207#else
9aef1a31 2208 pipe_ctx->stream_res.abm = pool->abm;
5dba4991
BL		 2209#endif
2210 }
9aef1a31 2211
1dc90497
AG		 2212 for (i = 0; i < context->stream_count; i++)
2213 if (context->streams[i] == stream) {
2214 context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst;
3f0940f8 2215 context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.stream_enc->stream_enc_inst;
5fdb7c4c
NK		 2216 context->stream_status[i].audio_inst =
2217 pipe_ctx->stream_res.audio ? pipe_ctx->stream_res.audio->inst : -1;
2218
1dc90497
AG		 2219 return DC_OK;
2220 }
4562236b 2221
1dc90497
AG		 2222 DC_ERROR("Stream %p not found in new ctx!\n", stream);
2223 return DC_ERROR_UNEXPECTED;
2224}
4562236b 2225
2119aa17
DF		 2226/**
2227 * dc_resource_state_copy_construct_current() - Creates a new dc_state from existing state
2228 * Is a shallow copy. Increments refcounts on existing streams and planes.
2229 * @dc: copy out of dc->current_state
2230 * @dst_ctx: copy into this
2231 */
f36cc577 2232void dc_resource_state_copy_construct_current(
1dc90497 2233 const struct dc *dc,
608ac7bb 2234 struct dc_state *dst_ctx)
1dc90497 2235{
f36cc577 2236 dc_resource_state_copy_construct(dc->current_state, dst_ctx);
1dc90497
AG		 2237}
2238
ab8db3e1
AG		 2239
2240void dc_resource_state_construct(
2241 const struct dc *dc,
2242 struct dc_state *dst_ctx)
2243{
dc88b4a6 2244 dst_ctx->clk_mgr = dc->clk_mgr;
ab8db3e1
AG		 2245}
2246
6d822156
NC		 2247
2248bool dc_resource_is_dsc_encoding_supported(const struct dc *dc)
2249{
2250 return dc->res_pool->res_cap->num_dsc > 0;
2251}
2252
2253
2119aa17
DF		 2254/**
2255 * dc_validate_global_state() - Determine if HW can support a given state
2256 * Checks HW resource availability and bandwidth requirement.
2257 * @dc: dc struct for this driver
2258 * @new_ctx: state to be validated
afcd526b 2259 * @fast_validate: set to true if only yes/no to support matters
2119aa17
DF		 2260 *
2261 * Return: DC_OK if the result can be programmed. Otherwise, an error code.
2262 */
e750d56d 2263enum dc_status dc_validate_global_state(
1dc90497 2264 struct dc *dc,
afcd526b
JA		 2265 struct dc_state *new_ctx,
2266 bool fast_validate)
4562236b 2267{
1dc90497 2268 enum dc_status result = DC_ERROR_UNEXPECTED;
1dc90497 2269 int i, j;
4562236b 2270
e41ab030
HW		 2271 if (!new_ctx)
2272 return DC_ERROR_UNEXPECTED;
2273
d596e5d0 2274 if (dc->res_pool->funcs->validate_global) {
ada8ce15
HW		 2275 result = dc->res_pool->funcs->validate_global(dc, new_ctx);
2276 if (result != DC_OK)
2277 return result;
d596e5d0 2278 }
4562236b 2279
e41ab030 2280 for (i = 0; i < new_ctx->stream_count; i++) {
1dc90497
AG		 2281 struct dc_stream_state *stream = new_ctx->streams[i];
2282
2283 for (j = 0; j < dc->res_pool->pipe_count; j++) {
2284 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[j];
2285
2286 if (pipe_ctx->stream != stream)
2287 continue;
2288
8d8c82b6 2289 if (dc->res_pool->funcs->patch_unknown_plane_state &&
74eac5f3
SSC		 2290 pipe_ctx->plane_state &&
2291 pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) {
8d8c82b6 2292 result = dc->res_pool->funcs->patch_unknown_plane_state(pipe_ctx->plane_state);
74eac5f3
SSC		 2293 if (result != DC_OK)
2294 return result;
2295 }
2296
1dc90497
AG		 2297 /* Switch to dp clock source only if there is
2298 * no non dp stream that shares the same timing
2299 * with the dp stream.
2300 */
2301 if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
2302 !find_pll_sharable_stream(stream, new_ctx)) {
2303
9d0dcecd 2304 resource_unreference_clock_source(
1dc90497
AG		 2305 &new_ctx->res_ctx,
2306 dc->res_pool,
9d0dcecd 2307 pipe_ctx->clock_source);
4a629536 2308
1dc90497
AG		 2309 pipe_ctx->clock_source = dc->res_pool->dp_clock_source;
2310 resource_reference_clock_source(
2311 &new_ctx->res_ctx,
2312 dc->res_pool,
2313 pipe_ctx->clock_source);
2314 }
2315 }
2316 }
2317
1dc90497
AG		 2318 result = resource_build_scaling_params_for_context(dc, new_ctx);
2319
2320 if (result == DC_OK)
afcd526b 2321 if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx, fast_validate))
1dc90497
AG		 2322 result = DC_FAIL_BANDWIDTH_VALIDATE;
2323
2324 return result;
4562236b
HW		 2325}
2326
6e4d6bee 2327static void patch_gamut_packet_checksum(
e09b6473 2328 struct dc_info_packet *gamut_packet)
4562236b 2329{
4562236b 2330 /* For gamut we recalc checksum */
6e4d6bee 2331 if (gamut_packet->valid) {
4562236b
HW		 2332 uint8_t chk_sum = 0;
2333 uint8_t *ptr;
2334 uint8_t i;
2335
4562236b 2336 /*start of the Gamut data. */
6e4d6bee 2337 ptr = &gamut_packet->sb[3];
4562236b 2338
6e4d6bee 2339 for (i = 0; i <= gamut_packet->sb[1]; i++)
4562236b
HW		 2340 chk_sum += ptr[i];
2341
6e4d6bee 2342 gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum);
1646a6fe 2343 }
4562236b
HW		 2344}
2345
2346static void set_avi_info_frame(
e09b6473 2347 struct dc_info_packet *info_packet,
4562236b
HW		 2348 struct pipe_ctx *pipe_ctx)
2349{
0971c40e 2350 struct dc_stream_state *stream = pipe_ctx->stream;
4562236b 2351 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
4562236b
HW		 2352 uint32_t pixel_encoding = 0;
2353 enum scanning_type scan_type = SCANNING_TYPE_NODATA;
2354 enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA;
2355 bool itc = false;
50e27654 2356 uint8_t itc_value = 0;
4562236b 2357 uint8_t cn0_cn1 = 0;
50e27654 2358 unsigned int cn0_cn1_value = 0;
4562236b
HW		 2359 uint8_t *check_sum = NULL;
2360 uint8_t byte_index = 0;
754e3673 2361 union hdmi_info_packet hdmi_info;
50e27654 2362 union display_content_support support = {0};
4fa086b9 2363 unsigned int vic = pipe_ctx->stream->timing.vic;
15e17335 2364 enum dc_timing_3d_format format;
4562236b 2365
754e3673
AK		 2366 memset(&hdmi_info, 0, sizeof(union hdmi_info_packet));
2367
4fa086b9 2368 color_space = pipe_ctx->stream->output_color_space;
e5f2038e 2369 if (color_space == COLOR_SPACE_UNKNOWN)
4fa086b9 2370 color_space = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ?
e5f2038e 2371 COLOR_SPACE_SRGB:COLOR_SPACE_YCBCR709;
4562236b
HW		 2372
2373 /* Initialize header */
e09b6473 2374 hdmi_info.bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI;
4562236b
HW		 2375 /* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall
2376 * not be used in HDMI 2.0 (Section 10.1) */
e09b6473
AK		 2377 hdmi_info.bits.header.version = 2;
2378 hdmi_info.bits.header.length = HDMI_AVI_INFOFRAME_SIZE;
4562236b
HW		 2379
2380 /*
2381 * IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built
2382 * according to HDMI 2.0 spec (Section 10.1)
2383 */
2384
4fa086b9 2385 switch (stream->timing.pixel_encoding) {
4562236b
HW		 2386 case PIXEL_ENCODING_YCBCR422:
2387 pixel_encoding = 1;
2388 break;
2389
2390 case PIXEL_ENCODING_YCBCR444:
2391 pixel_encoding = 2;
2392 break;
2393 case PIXEL_ENCODING_YCBCR420:
2394 pixel_encoding = 3;
2395 break;
2396
2397 case PIXEL_ENCODING_RGB:
2398 default:
2399 pixel_encoding = 0;
2400 }
2401
2402 /* Y0_Y1_Y2 : The pixel encoding */
2403 /* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */
e09b6473 2404 hdmi_info.bits.Y0_Y1_Y2 = pixel_encoding;
4562236b
HW		 2405
2406 /* A0 = 1 Active Format Information valid */
e09b6473 2407 hdmi_info.bits.A0 = ACTIVE_FORMAT_VALID;
4562236b
HW		 2408
2409 /* B0, B1 = 3; Bar info data is valid */
e09b6473 2410 hdmi_info.bits.B0_B1 = BAR_INFO_BOTH_VALID;
4562236b 2411
e09b6473 2412 hdmi_info.bits.SC0_SC1 = PICTURE_SCALING_UNIFORM;
4562236b
HW		 2413
2414 /* S0, S1 : Underscan / Overscan */
2415 /* TODO: un-hardcode scan type */
2416 scan_type = SCANNING_TYPE_UNDERSCAN;
e09b6473 2417 hdmi_info.bits.S0_S1 = scan_type;
4562236b
HW		 2418
2419 /* C0, C1 : Colorimetry */
8fde5884 2420 if (color_space == COLOR_SPACE_YCBCR709 ||
15e17335 2421 color_space == COLOR_SPACE_YCBCR709_LIMITED)
e09b6473 2422 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU709;
8fde5884
CL		 2423 else if (color_space == COLOR_SPACE_YCBCR601 ||
2424 color_space == COLOR_SPACE_YCBCR601_LIMITED)
e09b6473 2425 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU601;
8fde5884 2426 else {
e09b6473 2427 hdmi_info.bits.C0_C1 = COLORIMETRY_NO_DATA;
8fde5884 2428 }
534db198 2429 if (color_space == COLOR_SPACE_2020_RGB_FULLRANGE ||
8fde5884
CL		 2430 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE ||
2431 color_space == COLOR_SPACE_2020_YCBCR) {
e09b6473
AK		 2432 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR;
2433 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
534db198 2434 } else if (color_space == COLOR_SPACE_ADOBERGB) {
e09b6473
AK		 2435 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB;
2436 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
534db198
AZ		 2437 }
2438
4562236b 2439 /* TODO: un-hardcode aspect ratio */
4fa086b9 2440 aspect = stream->timing.aspect_ratio;
4562236b
HW		 2441
2442 switch (aspect) {
2443 case ASPECT_RATIO_4_3:
2444 case ASPECT_RATIO_16_9:
e09b6473 2445 hdmi_info.bits.M0_M1 = aspect;
4562236b
HW		 2446 break;
2447
2448 case ASPECT_RATIO_NO_DATA:
2449 case ASPECT_RATIO_64_27:
2450 case ASPECT_RATIO_256_135:
2451 default:
e09b6473 2452 hdmi_info.bits.M0_M1 = 0;
4562236b
HW		 2453 }
2454
2455 /* Active Format Aspect ratio - same as Picture Aspect Ratio. */
e09b6473 2456 hdmi_info.bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE;
4562236b
HW		 2457
2458 /* TODO: un-hardcode cn0_cn1 and itc */
50e27654 2459
4562236b 2460 cn0_cn1 = 0;
50e27654
ZF		 2461 cn0_cn1_value = 0;
2462
2463 itc = true;
2464 itc_value = 1;
2465
ceb3dbb4 2466 support = stream->content_support;
4562236b
HW		 2467
2468 if (itc) {
50e27654
ZF		 2469 if (!support.bits.valid_content_type) {
2470 cn0_cn1_value = 0;
2471 } else {
2472 if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GRAPHICS) {
2473 if (support.bits.graphics_content == 1) {
2474 cn0_cn1_value = 0;
2475 }
2476 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_PHOTO) {
2477 if (support.bits.photo_content == 1) {
2478 cn0_cn1_value = 1;
2479 } else {
2480 cn0_cn1_value = 0;
2481 itc_value = 0;
2482 }
2483 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_CINEMA) {
2484 if (support.bits.cinema_content == 1) {
2485 cn0_cn1_value = 2;
2486 } else {
2487 cn0_cn1_value = 0;
2488 itc_value = 0;
2489 }
2490 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GAME) {
2491 if (support.bits.game_content == 1) {
2492 cn0_cn1_value = 3;
2493 } else {
2494 cn0_cn1_value = 0;
2495 itc_value = 0;
2496 }
2497 }
2498 }
e09b6473
AK		 2499 hdmi_info.bits.CN0_CN1 = cn0_cn1_value;
2500 hdmi_info.bits.ITC = itc_value;
4562236b
HW		 2501 }
2502
fdf7d4f5
DV		 2503 if (stream->qs_bit == 1) {
2504 if (color_space == COLOR_SPACE_SRGB ||
2505 color_space == COLOR_SPACE_2020_RGB_FULLRANGE)
2506 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_FULL_RANGE;
2507 else if (color_space == COLOR_SPACE_SRGB_LIMITED ||
2508 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE)
2509 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_LIMITED_RANGE;
2510 else
2511 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
2512 } else
2513 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
2514
4562236b
HW		 2515 /* TODO : We should handle YCC quantization */
2516 /* but we do not have matrix calculation */
fdf7d4f5 2517 if (stream->qy_bit == 1) {
50e27654 2518 if (color_space == COLOR_SPACE_SRGB ||
fdf7d4f5 2519 color_space == COLOR_SPACE_2020_RGB_FULLRANGE)
993dca3e 2520 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
fdf7d4f5
DV		 2521 else if (color_space == COLOR_SPACE_SRGB_LIMITED ||
2522 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE)
e09b6473 2523 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
fdf7d4f5 2524 else
e09b6473 2525 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
fdf7d4f5
DV		 2526 } else
2527 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
50e27654 2528
15e17335 2529 ///VIC
4fa086b9 2530 format = stream->timing.timing_3d_format;
15e17335
CL		 2531 /*todo, add 3DStereo support*/
2532 if (format != TIMING_3D_FORMAT_NONE) {
2533 // Based on HDMI specs hdmi vic needs to be converted to cea vic when 3D is enabled
4fa086b9 2534 switch (pipe_ctx->stream->timing.hdmi_vic) {
15e17335
CL		 2535 case 1:
2536 vic = 95;
2537 break;
2538 case 2:
2539 vic = 94;
2540 break;
2541 case 3:
2542 vic = 93;
2543 break;
2544 case 4:
2545 vic = 98;
2546 break;
2547 default:
2548 break;
2549 }
2550 }
efa02336 2551 /* If VIC >= 128, the Source shall use AVI InfoFrame Version 3*/
e09b6473 2552 hdmi_info.bits.VIC0_VIC7 = vic;
efa02336
CP		 2553 if (vic >= 128)
2554 hdmi_info.bits.header.version = 3;
2555 /* If (C1, C0)=(1, 1) and (EC2, EC1, EC0)=(1, 1, 1),
2556 * the Source shall use 20 AVI InfoFrame Version 4
2557 */
2558 if (hdmi_info.bits.C0_C1 == COLORIMETRY_EXTENDED &&
2559 hdmi_info.bits.EC0_EC2 == COLORIMETRYEX_RESERVED) {
2560 hdmi_info.bits.header.version = 4;
2561 hdmi_info.bits.header.length = 14;
2562 }
4562236b
HW		 2563
2564 /* pixel repetition
2565 * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel
2566 * repetition start from 1 */
e09b6473 2567 hdmi_info.bits.PR0_PR3 = 0;
4562236b
HW		 2568
2569 /* Bar Info
2570 * barTop: Line Number of End of Top Bar.
2571 * barBottom: Line Number of Start of Bottom Bar.
2572 * barLeft: Pixel Number of End of Left Bar.
2573 * barRight: Pixel Number of Start of Right Bar. */
e09b6473
AK		 2574 hdmi_info.bits.bar_top = stream->timing.v_border_top;
2575 hdmi_info.bits.bar_bottom = (stream->timing.v_total
4fa086b9 2576 - stream->timing.v_border_bottom + 1);
e09b6473
AK		 2577 hdmi_info.bits.bar_left = stream->timing.h_border_left;
2578 hdmi_info.bits.bar_right = (stream->timing.h_total
4fa086b9 2579 - stream->timing.h_border_right + 1);
4562236b 2580
2f482c4f
CP		 2581 /* Additional Colorimetry Extension
2582 * Used in conduction with C0-C1 and EC0-EC2
2583 * 0 = DCI-P3 RGB (D65)
2584 * 1 = DCI-P3 RGB (theater)
2585 */
2586 hdmi_info.bits.ACE0_ACE3 = 0;
2587
4562236b 2588 /* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */
e09b6473 2589 check_sum = &hdmi_info.packet_raw_data.sb[0];
e8d726b7 2590
efa02336 2591 *check_sum = HDMI_INFOFRAME_TYPE_AVI + hdmi_info.bits.header.length + hdmi_info.bits.header.version;
4562236b 2592
efa02336 2593 for (byte_index = 1; byte_index <= hdmi_info.bits.header.length; byte_index++)
e09b6473 2594 *check_sum += hdmi_info.packet_raw_data.sb[byte_index];
4562236b
HW		 2595
2596 /* one byte complement */
2597 *check_sum = (uint8_t) (0x100 - *check_sum);
2598
2599 /* Store in hw_path_mode */
e09b6473
AK		 2600 info_packet->hb0 = hdmi_info.packet_raw_data.hb0;
2601 info_packet->hb1 = hdmi_info.packet_raw_data.hb1;
2602 info_packet->hb2 = hdmi_info.packet_raw_data.hb2;
4562236b 2603
e09b6473
AK		 2604 for (byte_index = 0; byte_index < sizeof(hdmi_info.packet_raw_data.sb); byte_index++)
2605 info_packet->sb[byte_index] = hdmi_info.packet_raw_data.sb[byte_index];
4562236b
HW		 2606
2607 info_packet->valid = true;
2608}
2609
6e4d6bee 2610static void set_vendor_info_packet(
e09b6473 2611 struct dc_info_packet *info_packet,
0971c40e 2612 struct dc_stream_state *stream)
4562236b 2613{
ecd0136b 2614 /* SPD info packet for FreeSync */
4562236b 2615
ecd0136b
HT		 2616 /* Check if Freesync is supported. Return if false. If true,
2617 * set the corresponding bit in the info packet
2618 */
2619 if (!stream->vsp_infopacket.valid)
4562236b
HW		 2620 return;
2621
ecd0136b 2622 *info_packet = stream->vsp_infopacket;
4562236b
HW		 2623}
2624
6e4d6bee 2625static void set_spd_info_packet(
e09b6473 2626 struct dc_info_packet *info_packet,
0971c40e 2627 struct dc_stream_state *stream)
4562236b
HW		 2628{
2629 /* SPD info packet for FreeSync */
2630
4562236b
HW		 2631 /* Check if Freesync is supported. Return if false. If true,
2632 * set the corresponding bit in the info packet
2633 */
98e6436d 2634 if (!stream->vrr_infopacket.valid)
4562236b
HW		 2635 return;
2636
98e6436d 2637 *info_packet = stream->vrr_infopacket;
4562236b
HW		 2638}
2639
1646a6fe 2640static void set_hdr_static_info_packet(
e09b6473 2641 struct dc_info_packet *info_packet,
0971c40e 2642 struct dc_stream_state *stream)
1646a6fe 2643{
0eeef690 2644 /* HDR Static Metadata info packet for HDR10 */
1646a6fe 2645
a10dc97a
KK		 2646 if (!stream->hdr_static_metadata.valid ||
2647 stream->use_dynamic_meta)
10bff005
YS		 2648 return;
2649
0eeef690 2650 *info_packet = stream->hdr_static_metadata;
1646a6fe
AW		 2651}
2652
6e4d6bee 2653static void set_vsc_info_packet(
e09b6473 2654 struct dc_info_packet *info_packet,
0971c40e 2655 struct dc_stream_state *stream)
4562236b 2656{
1336926f 2657 if (!stream->vsc_infopacket.valid)
4562236b
HW		 2658 return;
2659
1336926f 2660 *info_packet = stream->vsc_infopacket;
4562236b
HW		 2661}
2662
f36cc577 2663void dc_resource_state_destruct(struct dc_state *context)
4562236b
HW		 2664{
2665 int i, j;
2666
ab2541b6 2667 for (i = 0; i < context->stream_count; i++) {
3be5262e
HW		 2668 for (j = 0; j < context->stream_status[i].plane_count; j++)
2669 dc_plane_state_release(
2670 context->stream_status[i].plane_states[j]);
4562236b 2671
3be5262e 2672 context->stream_status[i].plane_count = 0;
4fa086b9 2673 dc_stream_release(context->streams[i]);
ab2541b6 2674 context->streams[i] = NULL;
4562236b
HW		 2675 }
2676}
2677
f36cc577 2678void dc_resource_state_copy_construct(
608ac7bb
JZ		 2679 const struct dc_state *src_ctx,
2680 struct dc_state *dst_ctx)
4562236b
HW		 2681{
2682 int i, j;
8ee5702a 2683 struct kref refcount = dst_ctx->refcount;
4562236b
HW		 2684
2685 *dst_ctx = *src_ctx;
2686
a2b8659d 2687 for (i = 0; i < MAX_PIPES; i++) {
4562236b
HW		 2688 struct pipe_ctx *cur_pipe = &dst_ctx->res_ctx.pipe_ctx[i];
2689
2690 if (cur_pipe->top_pipe)
2691 cur_pipe->top_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
2692
2693 if (cur_pipe->bottom_pipe)
2694 cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
b1f6d01c
DL		 2695
2696 if (cur_pipe->next_odm_pipe)
2697 cur_pipe->next_odm_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx];
2698
2699 if (cur_pipe->prev_odm_pipe)
2700 cur_pipe->prev_odm_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx];
4562236b
HW		 2701 }
2702
ab2541b6 2703 for (i = 0; i < dst_ctx->stream_count; i++) {
4fa086b9 2704 dc_stream_retain(dst_ctx->streams[i]);
3be5262e
HW		 2705 for (j = 0; j < dst_ctx->stream_status[i].plane_count; j++)
2706 dc_plane_state_retain(
2707 dst_ctx->stream_status[i].plane_states[j]);
4562236b 2708 }
9a3afbb3
AG		 2709
2710 /* context refcount should not be overridden */
8ee5702a 2711 dst_ctx->refcount = refcount;
9a3afbb3 2712
4562236b
HW		 2713}
2714
2715struct clock_source *dc_resource_find_first_free_pll(
a2b8659d
TC		 2716 struct resource_context *res_ctx,
2717 const struct resource_pool *pool)
4562236b
HW		 2718{
2719 int i;
2720
a2b8659d 2721 for (i = 0; i < pool->clk_src_count; ++i) {
4562236b 2722 if (res_ctx->clock_source_ref_count[i] == 0)
a2b8659d 2723 return pool->clock_sources[i];
4562236b
HW		 2724 }
2725
2726 return NULL;
2727}
2728
2729void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
2730{
2731 enum signal_type signal = SIGNAL_TYPE_NONE;
96c50c0d 2732 struct encoder_info_frame *info = &pipe_ctx->stream_res.encoder_info_frame;
4562236b
HW		 2733
2734 /* default all packets to invalid */
6e4d6bee
TC		 2735 info->avi.valid = false;
2736 info->gamut.valid = false;
2737 info->vendor.valid = false;
630e3573 2738 info->spd.valid = false;
6e4d6bee
TC		 2739 info->hdrsmd.valid = false;
2740 info->vsc.valid = false;
4562236b
HW		 2741
2742 signal = pipe_ctx->stream->signal;
2743
2744 /* HDMi and DP have different info packets*/
2745 if (dc_is_hdmi_signal(signal)) {
6e4d6bee
TC		 2746 set_avi_info_frame(&info->avi, pipe_ctx);
2747
2748 set_vendor_info_packet(&info->vendor, pipe_ctx->stream);
2749
2750 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2751
56ef6ed9 2752 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
6e4d6bee 2753
a33fa99d 2754 } else if (dc_is_dp_signal(signal)) {
6e4d6bee
TC		 2755 set_vsc_info_packet(&info->vsc, pipe_ctx->stream);
2756
2757 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2758
56ef6ed9 2759 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
a33fa99d 2760 }
4562236b 2761
6e4d6bee 2762 patch_gamut_packet_checksum(&info->gamut);
4562236b
HW		 2763}
2764
2765enum dc_status resource_map_clock_resources(
fb3466a4 2766 const struct dc *dc,
608ac7bb 2767 struct dc_state *context,
1dc90497 2768 struct dc_stream_state *stream)
4562236b 2769{
4562236b 2770 /* acquire new resources */
1dc90497
AG		 2771 const struct resource_pool *pool = dc->res_pool;
2772 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(
2773 &context->res_ctx, stream);
ab2541b6 2774
1dc90497
AG		 2775 if (!pipe_ctx)
2776 return DC_ERROR_UNEXPECTED;
4562236b 2777
1dc90497
AG		 2778 if (dc_is_dp_signal(pipe_ctx->stream->signal)
2779 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)
2780 pipe_ctx->clock_source = pool->dp_clock_source;
2781 else {
2782 pipe_ctx->clock_source = NULL;
4562236b 2783
1dc90497 2784 if (!dc->config.disable_disp_pll_sharing)
4ed4e51b 2785 pipe_ctx->clock_source = resource_find_used_clk_src_for_sharing(
1dc90497
AG		 2786 &context->res_ctx,
2787 pipe_ctx);
4562236b 2788
1dc90497
AG		 2789 if (pipe_ctx->clock_source == NULL)
2790 pipe_ctx->clock_source =
2791 dc_resource_find_first_free_pll(
2792 &context->res_ctx,
2793 pool);
2794 }
4562236b 2795
1dc90497
AG		 2796 if (pipe_ctx->clock_source == NULL)
2797 return DC_NO_CLOCK_SOURCE_RESOURCE;
4562236b 2798
1dc90497
AG		 2799 resource_reference_clock_source(
2800 &context->res_ctx, pool,
2801 pipe_ctx->clock_source);
4562236b
HW		 2802
2803 return DC_OK;
2804}
2805
2806/*
2807 * Note: We need to disable output if clock sources change,
2808 * since bios does optimization and doesn't apply if changing
2809 * PHY when not already disabled.
2810 */
2811bool pipe_need_reprogram(
2812 struct pipe_ctx *pipe_ctx_old,
2813 struct pipe_ctx *pipe_ctx)
2814{
cfe4645e
DL		 2815 if (!pipe_ctx_old->stream)
2816 return false;
2817
4562236b
HW		 2818 if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink)
2819 return true;
2820
2821 if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal)
2822 return true;
2823
afaacef4 2824 if (pipe_ctx_old->stream_res.audio != pipe_ctx->stream_res.audio)
4562236b
HW		 2825 return true;
2826
2827 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source
2828 && pipe_ctx_old->stream != pipe_ctx->stream)
2829 return true;
2830
8e9c4c8c 2831 if (pipe_ctx_old->stream_res.stream_enc != pipe_ctx->stream_res.stream_enc)
4562236b
HW		 2832 return true;
2833
2834 if (is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2835 return true;
2836
1e7e86c4
ST		 2837 if (pipe_ctx_old->stream->dpms_off != pipe_ctx->stream->dpms_off)
2838 return true;
2839
eed928dc
CL		 2840 if (false == pipe_ctx_old->stream->link->link_state_valid &&
2841 false == pipe_ctx_old->stream->dpms_off)
2842 return true;
2843
14e49bb3
NC		 2844 if (pipe_ctx_old->stream_res.dsc != pipe_ctx->stream_res.dsc)
2845 return true;
2846
f42ef862
JK		 2847 /* DIG link encoder resource assignment for stream changed. */
2848 if (pipe_ctx_old->stream->link_enc != pipe_ctx->stream->link_enc)
2849 return true;
2850
4562236b
HW		 2851 return false;
2852}
529cad0f 2853
0971c40e 2854void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream,
529cad0f
DW		 2855 struct bit_depth_reduction_params *fmt_bit_depth)
2856{
4fa086b9 2857 enum dc_dither_option option = stream->dither_option;
529cad0f 2858 enum dc_pixel_encoding pixel_encoding =
4fa086b9 2859 stream->timing.pixel_encoding;
529cad0f
DW		 2860
2861 memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth));
2862
603767f9
TC		 2863 if (option == DITHER_OPTION_DEFAULT) {
2864 switch (stream->timing.display_color_depth) {
2865 case COLOR_DEPTH_666:
2866 option = DITHER_OPTION_SPATIAL6;
2867 break;
2868 case COLOR_DEPTH_888:
2869 option = DITHER_OPTION_SPATIAL8;
2870 break;
2871 case COLOR_DEPTH_101010:
2872 option = DITHER_OPTION_SPATIAL10;
2873 break;
2874 default:
2875 option = DITHER_OPTION_DISABLE;
2876 }
2877 }
2878
529cad0f
DW		 2879 if (option == DITHER_OPTION_DISABLE)
2880 return;
2881
2882 if (option == DITHER_OPTION_TRUN6) {
2883 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2884 fmt_bit_depth->flags.TRUNCATE_DEPTH = 0;
2885 } else if (option == DITHER_OPTION_TRUN8 ||
2886 option == DITHER_OPTION_TRUN8_SPATIAL6 ||
2887 option == DITHER_OPTION_TRUN8_FM6) {
2888 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2889 fmt_bit_depth->flags.TRUNCATE_DEPTH = 1;
2890 } else if (option == DITHER_OPTION_TRUN10 ||
2891 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
2892 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
2893 option == DITHER_OPTION_TRUN10_FM8 ||
2894 option == DITHER_OPTION_TRUN10_FM6 ||
2895 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2896 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2897 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2898 }
2899
2900 /* special case - Formatter can only reduce by 4 bits at most.
2901 * When reducing from 12 to 6 bits,
2902 * HW recommends we use trunc with round mode
2903 * (if we did nothing, trunc to 10 bits would be used)
2904 * note that any 12->10 bit reduction is ignored prior to DCE8,
2905 * as the input was 10 bits.
2906 */
2907 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2908 option == DITHER_OPTION_SPATIAL6 ||
2909 option == DITHER_OPTION_FM6) {
2910 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2911 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2912 fmt_bit_depth->flags.TRUNCATE_MODE = 1;
2913 }
2914
2915 /* spatial dither
2916 * note that spatial modes 1-3 are never used
2917 */
2918 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2919 option == DITHER_OPTION_SPATIAL6 ||
2920 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
2921 option == DITHER_OPTION_TRUN8_SPATIAL6) {
2922 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2923 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 0;
2924 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2925 fmt_bit_depth->flags.RGB_RANDOM =
2926 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2927 } else if (option == DITHER_OPTION_SPATIAL8_FRAME_RANDOM ||
2928 option == DITHER_OPTION_SPATIAL8 ||
2929 option == DITHER_OPTION_SPATIAL8_FM6 ||
2930 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
2931 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2932 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2933 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 1;
2934 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2935 fmt_bit_depth->flags.RGB_RANDOM =
2936 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2937 } else if (option == DITHER_OPTION_SPATIAL10_FRAME_RANDOM ||
2938 option == DITHER_OPTION_SPATIAL10 ||
2939 option == DITHER_OPTION_SPATIAL10_FM8 ||
2940 option == DITHER_OPTION_SPATIAL10_FM6) {
2941 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2942 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 2;
2943 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2944 fmt_bit_depth->flags.RGB_RANDOM =
2945 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2946 }
2947
2948 if (option == DITHER_OPTION_SPATIAL6 ||
2949 option == DITHER_OPTION_SPATIAL8 ||
2950 option == DITHER_OPTION_SPATIAL10) {
2951 fmt_bit_depth->flags.FRAME_RANDOM = 0;
2952 } else {
2953 fmt_bit_depth->flags.FRAME_RANDOM = 1;
2954 }
2955
2956 //////////////////////
2957 //// temporal dither
2958 //////////////////////
2959 if (option == DITHER_OPTION_FM6 ||
2960 option == DITHER_OPTION_SPATIAL8_FM6 ||
2961 option == DITHER_OPTION_SPATIAL10_FM6 ||
2962 option == DITHER_OPTION_TRUN10_FM6 ||
2963 option == DITHER_OPTION_TRUN8_FM6 ||
2964 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2965 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2966 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 0;
2967 } else if (option == DITHER_OPTION_FM8 ||
2968 option == DITHER_OPTION_SPATIAL10_FM8 ||
2969 option == DITHER_OPTION_TRUN10_FM8) {
2970 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2971 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 1;
2972 } else if (option == DITHER_OPTION_FM10) {
2973 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2974 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 2;
2975 }
2976
2977 fmt_bit_depth->pixel_encoding = pixel_encoding;
2978}
9345d987 2979
62c933f9 2980enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream)
9345d987 2981{
ceb3dbb4 2982 struct dc_link *link = stream->link;
2b77dcc5 2983 struct timing_generator *tg = dc->res_pool->timing_generators[0];
9345d987
AG		 2984 enum dc_status res = DC_OK;
2985
4fa086b9 2986 calculate_phy_pix_clks(stream);
9345d987 2987
4fa086b9 2988 if (!tg->funcs->validate_timing(tg, &stream->timing))
9345d987
AG		 2989 res = DC_FAIL_CONTROLLER_VALIDATE;
2990
248cbed6 2991 if (res == DC_OK) {
9345d987 2992 if (!link->link_enc->funcs->validate_output_with_stream(
4fa086b9 2993 link->link_enc, stream))
9345d987 2994 res = DC_FAIL_ENC_VALIDATE;
248cbed6 2995 }
9345d987
AG		 2996
2997 /* TODO: validate audio ASIC caps, encoder */
2998
2999 if (res == DC_OK)
4fa086b9 3000 res = dc_link_validate_mode_timing(stream,
9345d987 3001 link,
4fa086b9 3002 &stream->timing);
9345d987 3003
62c933f9 3004 return res;
9345d987 3005}
792671d7 3006
62c933f9 3007enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state)
792671d7 3008{
62c933f9
YS		 3009 enum dc_status res = DC_OK;
3010
792671d7 3011 /* TODO For now validates pixel format only */
8e7095b9 3012 if (dc->res_pool->funcs->validate_plane)
62c933f9 3013 return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps);
792671d7 3014
62c933f9 3015 return res;
792671d7 3016}
74eac5f3
SSC		 3017
3018unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format)
3019{
3020 switch (format) {
3021 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
3022 return 8;
3023 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
3024 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
3025 return 12;
3026 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
3027 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
3028 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
3029 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
3030 return 16;
3031 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
3032 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
3033 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
3034 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
3035 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
20f2ffe5 3036#if defined(CONFIG_DRM_AMD_DC_DCN)
5dba4991
BL		 3037 case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
3038 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
3039#endif
74eac5f3
SSC		 3040 return 32;
3041 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
3042 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
3043 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
3044 return 64;
3045 default:
3046 ASSERT_CRITICAL(false);
3047 return -1;
3048 }
3049}
3ab4cc65
CL		 3050static unsigned int get_max_audio_sample_rate(struct audio_mode *modes)
3051{
3052 if (modes) {
3053 if (modes->sample_rates.rate.RATE_192)
3054 return 192000;
3055 if (modes->sample_rates.rate.RATE_176_4)
3056 return 176400;
3057 if (modes->sample_rates.rate.RATE_96)
3058 return 96000;
3059 if (modes->sample_rates.rate.RATE_88_2)
3060 return 88200;
3061 if (modes->sample_rates.rate.RATE_48)
3062 return 48000;
3063 if (modes->sample_rates.rate.RATE_44_1)
3064 return 44100;
3065 if (modes->sample_rates.rate.RATE_32)
3066 return 32000;
3067 }
3068 /*original logic when no audio info*/
3069 return 441000;
3070}
3071
3072void get_audio_check(struct audio_info *aud_modes,
3073 struct audio_check *audio_chk)
3074{
3075 unsigned int i;
3076 unsigned int max_sample_rate = 0;
3077
3078 if (aud_modes) {
3079 audio_chk->audio_packet_type = 0x2;/*audio sample packet AP = .25 for layout0, 1 for layout1*/
3080
3081 audio_chk->max_audiosample_rate = 0;
3082 for (i = 0; i < aud_modes->mode_count; i++) {
3083 max_sample_rate = get_max_audio_sample_rate(&aud_modes->modes[i]);
3084 if (audio_chk->max_audiosample_rate < max_sample_rate)
3085 audio_chk->max_audiosample_rate = max_sample_rate;
3086 /*dts takes the same as type 2: AP = 0.25*/
3087 }
3088 /*check which one take more bandwidth*/
3089 if (audio_chk->max_audiosample_rate > 192000)
3090 audio_chk->audio_packet_type = 0x9;/*AP =1*/
3091 audio_chk->acat = 0;/*not support*/
3092 }
3093}
3094
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