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drm/amdgpu/display: extend DCN guard in dal_bios_parser_init_cmd_tbl_helper2
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / display / dc / core / dc_resource.c
CommitLineData
4562236b 1/*
9ce6aae1 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4562236b
HW
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
4fc4dca8
SR
25
26#include <linux/slab.h>
27
4562236b
HW
28#include "dm_services.h"
29
30#include "resource.h"
31#include "include/irq_service_interface.h"
32#include "link_encoder.h"
33#include "stream_encoder.h"
34#include "opp.h"
35#include "timing_generator.h"
36#include "transform.h"
33d7598d
JL
37#include "dccg.h"
38#include "dchubbub.h"
d94585a0 39#include "dpp.h"
5ac3d3c9 40#include "core_types.h"
4562236b 41#include "set_mode_types.h"
4562236b 42#include "virtual/virtual_stream_encoder.h"
3b94a400 43#include "dpcd_defs.h"
4562236b
HW
44
45#include "dce80/dce80_resource.h"
46#include "dce100/dce100_resource.h"
47#include "dce110/dce110_resource.h"
48#include "dce112/dce112_resource.h"
b86a1aa3 49#if defined(CONFIG_DRM_AMD_DC_DCN)
ff5ef992
AD
50#include "dcn10/dcn10_resource.h"
51#endif
7ed4e635 52#include "dcn20/dcn20_resource.h"
e22ece54 53#include "dcn21/dcn21_resource.h"
2c8ad2d5 54#include "dce120/dce120_resource.h"
5d4b05dd
BL
55
56#define DC_LOGGER_INIT(logger)
57
4562236b
HW
58enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
59{
60 enum dce_version dc_version = DCE_VERSION_UNKNOWN;
61 switch (asic_id.chip_family) {
62
63 case FAMILY_CI:
4562236b
HW
64 dc_version = DCE_VERSION_8_0;
65 break;
ebfdf0d0
AD
66 case FAMILY_KV:
67 if (ASIC_REV_IS_KALINDI(asic_id.hw_internal_rev) ||
68 ASIC_REV_IS_BHAVANI(asic_id.hw_internal_rev) ||
69 ASIC_REV_IS_GODAVARI(asic_id.hw_internal_rev))
70 dc_version = DCE_VERSION_8_3;
71 else
72 dc_version = DCE_VERSION_8_1;
73 break;
4562236b
HW
74 case FAMILY_CZ:
75 dc_version = DCE_VERSION_11_0;
76 break;
77
78 case FAMILY_VI:
79 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
80 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
81 dc_version = DCE_VERSION_10_0;
82 break;
83 }
84 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
b264d345
JL
85 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
86 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
4562236b
HW
87 dc_version = DCE_VERSION_11_2;
88 }
0c75d5ac
JFZ
89 if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev))
90 dc_version = DCE_VERSION_11_22;
4562236b 91 break;
2c8ad2d5 92 case FAMILY_AI:
b8b6ce89
LL
93 if (ASICREV_IS_VEGA20_P(asic_id.hw_internal_rev))
94 dc_version = DCE_VERSION_12_1;
95 else
96 dc_version = DCE_VERSION_12_0;
2c8ad2d5 97 break;
b86a1aa3 98#if defined(CONFIG_DRM_AMD_DC_DCN)
ff5ef992
AD
99 case FAMILY_RV:
100 dc_version = DCN_VERSION_1_0;
0e3d73f1
BL
101 if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev))
102 dc_version = DCN_VERSION_1_01;
e22ece54
BL
103 if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev))
104 dc_version = DCN_VERSION_2_1;
ff5ef992
AD
105 break;
106#endif
7ed4e635 107
7ed4e635
HW
108 case FAMILY_NV:
109 dc_version = DCN_VERSION_2_0;
110 break;
4562236b
HW
111 default:
112 dc_version = DCE_VERSION_UNKNOWN;
113 break;
114 }
115 return dc_version;
116}
117
d9673c92
HW
118struct resource_pool *dc_create_resource_pool(struct dc *dc,
119 const struct dc_init_data *init_data,
120 enum dce_version dc_version)
4562236b 121{
5ac3d3c9 122 struct resource_pool *res_pool = NULL;
4562236b
HW
123
124 switch (dc_version) {
125 case DCE_VERSION_8_0:
7992a629 126 res_pool = dce80_create_resource_pool(
d9673c92 127 init_data->num_virtual_links, dc);
7992a629 128 break;
ebfdf0d0 129 case DCE_VERSION_8_1:
7992a629 130 res_pool = dce81_create_resource_pool(
d9673c92 131 init_data->num_virtual_links, dc);
7992a629 132 break;
ebfdf0d0 133 case DCE_VERSION_8_3:
7992a629 134 res_pool = dce83_create_resource_pool(
d9673c92 135 init_data->num_virtual_links, dc);
5ac3d3c9 136 break;
4562236b 137 case DCE_VERSION_10_0:
5ac3d3c9 138 res_pool = dce100_create_resource_pool(
d9673c92 139 init_data->num_virtual_links, dc);
5ac3d3c9 140 break;
4562236b 141 case DCE_VERSION_11_0:
5ac3d3c9 142 res_pool = dce110_create_resource_pool(
d9673c92
HW
143 init_data->num_virtual_links, dc,
144 init_data->asic_id);
5ac3d3c9 145 break;
4562236b 146 case DCE_VERSION_11_2:
0c75d5ac 147 case DCE_VERSION_11_22:
5ac3d3c9 148 res_pool = dce112_create_resource_pool(
d9673c92 149 init_data->num_virtual_links, dc);
5ac3d3c9 150 break;
2c8ad2d5 151 case DCE_VERSION_12_0:
b8b6ce89 152 case DCE_VERSION_12_1:
2c8ad2d5 153 res_pool = dce120_create_resource_pool(
d9673c92 154 init_data->num_virtual_links, dc);
2c8ad2d5 155 break;
ff5ef992 156
b86a1aa3 157#if defined(CONFIG_DRM_AMD_DC_DCN)
ff5ef992 158 case DCN_VERSION_1_0:
0e3d73f1 159 case DCN_VERSION_1_01:
d9673c92 160 res_pool = dcn10_create_resource_pool(init_data, dc);
ff5ef992 161 break;
3639fa68
ZF
162
163
7ed4e635
HW
164 case DCN_VERSION_2_0:
165 res_pool = dcn20_create_resource_pool(init_data, dc);
166 break;
e22ece54
BL
167 case DCN_VERSION_2_1:
168 res_pool = dcn21_create_resource_pool(init_data, dc);
169 break;
170#endif
7ed4e635 171
4562236b
HW
172 default:
173 break;
174 }
f49cfa27 175
5ac3d3c9 176 if (res_pool != NULL) {
9adc8050 177 if (dc->ctx->dc_bios->fw_info_valid) {
41a5a2a8 178 res_pool->ref_clocks.xtalin_clock_inKhz =
9adc8050 179 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
41a5a2a8 180 /* initialize with firmware data first, no all
181 * ASIC have DCCG SW component. FPGA or
182 * simulation need initialization of
183 * dccg_ref_clock_inKhz, dchub_ref_clock_inKhz
184 * with xtalin_clock_inKhz
185 */
186 res_pool->ref_clocks.dccg_ref_clock_inKhz =
187 res_pool->ref_clocks.xtalin_clock_inKhz;
188 res_pool->ref_clocks.dchub_ref_clock_inKhz =
189 res_pool->ref_clocks.xtalin_clock_inKhz;
190 } else
191 ASSERT_CRITICAL(false);
5ac3d3c9 192 }
4562236b 193
5ac3d3c9 194 return res_pool;
4562236b
HW
195}
196
fb3466a4 197void dc_destroy_resource_pool(struct dc *dc)
4562236b
HW
198{
199 if (dc) {
200 if (dc->res_pool)
201 dc->res_pool->funcs->destroy(&dc->res_pool);
202
d029810c 203 kfree(dc->hwseq);
4562236b
HW
204 }
205}
206
207static void update_num_audio(
208 const struct resource_straps *straps,
209 unsigned int *num_audio,
210 struct audio_support *aud_support)
211{
b8e9eb72
CL
212 aud_support->dp_audio = true;
213 aud_support->hdmi_audio_native = false;
214 aud_support->hdmi_audio_on_dongle = false;
215
4562236b 216 if (straps->hdmi_disable == 0) {
4562236b
HW
217 if (straps->dc_pinstraps_audio & 0x2) {
218 aud_support->hdmi_audio_on_dongle = true;
b8e9eb72 219 aud_support->hdmi_audio_native = true;
4562236b
HW
220 }
221 }
222
223 switch (straps->audio_stream_number) {
224 case 0: /* multi streams supported */
225 break;
226 case 1: /* multi streams not supported */
227 *num_audio = 1;
228 break;
229 default:
230 DC_ERR("DC: unexpected audio fuse!\n");
17a96033 231 }
4562236b
HW
232}
233
234bool resource_construct(
235 unsigned int num_virtual_links,
fb3466a4 236 struct dc *dc,
4562236b
HW
237 struct resource_pool *pool,
238 const struct resource_create_funcs *create_funcs)
239{
240 struct dc_context *ctx = dc->ctx;
241 const struct resource_caps *caps = pool->res_cap;
242 int i;
243 unsigned int num_audio = caps->num_audio;
244 struct resource_straps straps = {0};
245
246 if (create_funcs->read_dce_straps)
247 create_funcs->read_dce_straps(dc->ctx, &straps);
248
249 pool->audio_count = 0;
250 if (create_funcs->create_audio) {
251 /* find the total number of streams available via the
252 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
253 * registers (one for each pin) starting from pin 1
254 * up to the max number of audio pins.
255 * We stop on the first pin where
256 * PORT_CONNECTIVITY == 1 (as instructed by HW team).
257 */
258 update_num_audio(&straps, &num_audio, &pool->audio_support);
5feb9f07 259 for (i = 0; i < caps->num_audio; i++) {
4562236b
HW
260 struct audio *aud = create_funcs->create_audio(ctx, i);
261
262 if (aud == NULL) {
263 DC_ERR("DC: failed to create audio!\n");
264 return false;
265 }
4562236b
HW
266 if (!aud->funcs->endpoint_valid(aud)) {
267 aud->funcs->destroy(&aud);
268 break;
269 }
4562236b
HW
270 pool->audios[i] = aud;
271 pool->audio_count++;
272 }
273 }
274
275 pool->stream_enc_count = 0;
276 if (create_funcs->create_stream_encoder) {
277 for (i = 0; i < caps->num_stream_encoder; i++) {
278 pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx);
279 if (pool->stream_enc[i] == NULL)
280 DC_ERR("DC: failed to create stream_encoder!\n");
281 pool->stream_enc_count++;
282 }
283 }
929c3aaa 284
4176664b
CL
285 dc->caps.dynamic_audio = false;
286 if (pool->audio_count < pool->stream_enc_count) {
287 dc->caps.dynamic_audio = true;
288 }
4562236b
HW
289 for (i = 0; i < num_virtual_links; i++) {
290 pool->stream_enc[pool->stream_enc_count] =
291 virtual_stream_encoder_create(
292 ctx, ctx->dc_bios);
293 if (pool->stream_enc[pool->stream_enc_count] == NULL) {
294 DC_ERR("DC: failed to create stream_encoder!\n");
295 return false;
296 }
297 pool->stream_enc_count++;
298 }
299
300 dc->hwseq = create_funcs->create_hwseq(ctx);
301
302 return true;
303}
ad8960a6
ML
304static int find_matching_clock_source(
305 const struct resource_pool *pool,
306 struct clock_source *clock_source)
307{
4562236b 308
ad8960a6
ML
309 int i;
310
311 for (i = 0; i < pool->clk_src_count; i++) {
312 if (pool->clock_sources[i] == clock_source)
313 return i;
314 }
315 return -1;
316}
4562236b 317
21e67d4d 318void resource_unreference_clock_source(
4562236b 319 struct resource_context *res_ctx,
a2b8659d 320 const struct resource_pool *pool,
4a629536 321 struct clock_source *clock_source)
4562236b 322{
ad8960a6 323 int i = find_matching_clock_source(pool, clock_source);
4562236b 324
ad8960a6 325 if (i > -1)
4562236b
HW
326 res_ctx->clock_source_ref_count[i]--;
327
21e67d4d 328 if (pool->dp_clock_source == clock_source)
4562236b 329 res_ctx->dp_clock_source_ref_count--;
4562236b
HW
330}
331
332void resource_reference_clock_source(
333 struct resource_context *res_ctx,
a2b8659d 334 const struct resource_pool *pool,
4562236b
HW
335 struct clock_source *clock_source)
336{
ad8960a6 337 int i = find_matching_clock_source(pool, clock_source);
4562236b 338
ad8960a6 339 if (i > -1)
4562236b 340 res_ctx->clock_source_ref_count[i]++;
4562236b 341
a2b8659d 342 if (pool->dp_clock_source == clock_source)
4562236b
HW
343 res_ctx->dp_clock_source_ref_count++;
344}
345
ad8960a6
ML
346int resource_get_clock_source_reference(
347 struct resource_context *res_ctx,
348 const struct resource_pool *pool,
349 struct clock_source *clock_source)
350{
351 int i = find_matching_clock_source(pool, clock_source);
352
353 if (i > -1)
354 return res_ctx->clock_source_ref_count[i];
355
356 if (pool->dp_clock_source == clock_source)
357 return res_ctx->dp_clock_source_ref_count;
358
359 return -1;
360}
361
4562236b 362bool resource_are_streams_timing_synchronizable(
0971c40e
HW
363 struct dc_stream_state *stream1,
364 struct dc_stream_state *stream2)
4562236b 365{
4fa086b9 366 if (stream1->timing.h_total != stream2->timing.h_total)
4562236b
HW
367 return false;
368
4fa086b9 369 if (stream1->timing.v_total != stream2->timing.v_total)
4562236b
HW
370 return false;
371
4fa086b9
LSL
372 if (stream1->timing.h_addressable
373 != stream2->timing.h_addressable)
4562236b
HW
374 return false;
375
4fa086b9
LSL
376 if (stream1->timing.v_addressable
377 != stream2->timing.v_addressable)
4562236b
HW
378 return false;
379
380604e2
KC
380 if (stream1->timing.pix_clk_100hz
381 != stream2->timing.pix_clk_100hz)
4562236b
HW
382 return false;
383
3e27e10e
ML
384 if (stream1->clamping.c_depth != stream2->clamping.c_depth)
385 return false;
386
4562236b 387 if (stream1->phy_pix_clk != stream2->phy_pix_clk
7e2fe319
CL
388 && (!dc_is_dp_signal(stream1->signal)
389 || !dc_is_dp_signal(stream2->signal)))
4562236b
HW
390 return false;
391
d77f778e
CL
392 if (stream1->view_format != stream2->view_format)
393 return false;
394
0460f9ab
JL
395 if (stream1->ignore_msa_timing_param || stream2->ignore_msa_timing_param)
396 return false;
397
4562236b
HW
398 return true;
399}
3e27e10e
ML
400static bool is_dp_and_hdmi_sharable(
401 struct dc_stream_state *stream1,
402 struct dc_stream_state *stream2)
403{
404 if (stream1->ctx->dc->caps.disable_dp_clk_share)
405 return false;
406
407 if (stream1->clamping.c_depth != COLOR_DEPTH_888 ||
d77f778e 408 stream2->clamping.c_depth != COLOR_DEPTH_888)
43fbbe89 409 return false;
3e27e10e
ML
410
411 return true;
412
413}
4562236b
HW
414
415static bool is_sharable_clk_src(
416 const struct pipe_ctx *pipe_with_clk_src,
417 const struct pipe_ctx *pipe)
418{
419 if (pipe_with_clk_src->clock_source == NULL)
420 return false;
421
422 if (pipe_with_clk_src->stream->signal == SIGNAL_TYPE_VIRTUAL)
423 return false;
424
3e27e10e
ML
425 if (dc_is_dp_signal(pipe_with_clk_src->stream->signal) ||
426 (dc_is_dp_signal(pipe->stream->signal) &&
427 !is_dp_and_hdmi_sharable(pipe_with_clk_src->stream,
428 pipe->stream)))
4562236b
HW
429 return false;
430
431 if (dc_is_hdmi_signal(pipe_with_clk_src->stream->signal)
fc69009e 432 && dc_is_dual_link_signal(pipe->stream->signal))
4562236b
HW
433 return false;
434
435 if (dc_is_hdmi_signal(pipe->stream->signal)
fc69009e 436 && dc_is_dual_link_signal(pipe_with_clk_src->stream->signal))
4562236b
HW
437 return false;
438
439 if (!resource_are_streams_timing_synchronizable(
440 pipe_with_clk_src->stream, pipe->stream))
441 return false;
442
443 return true;
444}
445
446struct clock_source *resource_find_used_clk_src_for_sharing(
447 struct resource_context *res_ctx,
448 struct pipe_ctx *pipe_ctx)
449{
450 int i;
451
452 for (i = 0; i < MAX_PIPES; i++) {
453 if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx))
454 return res_ctx->pipe_ctx[i].clock_source;
455 }
456
457 return NULL;
458}
459
460static enum pixel_format convert_pixel_format_to_dalsurface(
461 enum surface_pixel_format surface_pixel_format)
462{
463 enum pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
464
465 switch (surface_pixel_format) {
466 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
467 dal_pixel_format = PIXEL_FORMAT_INDEX8;
468 break;
469 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
470 dal_pixel_format = PIXEL_FORMAT_RGB565;
471 break;
472 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
473 dal_pixel_format = PIXEL_FORMAT_RGB565;
474 break;
475 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
476 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
477 break;
8693049a 478 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
4562236b
HW
479 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
480 break;
481 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
482 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
483 break;
484 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
485 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
486 break;
487 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
488 dal_pixel_format = PIXEL_FORMAT_ARGB2101010_XRBIAS;
489 break;
490 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
491 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
492 dal_pixel_format = PIXEL_FORMAT_FP16;
493 break;
494 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
4562236b 495 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
87449a90 496 dal_pixel_format = PIXEL_FORMAT_420BPP8;
4562236b 497 break;
ffbcd19a
VP
498 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
499 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
87449a90 500 dal_pixel_format = PIXEL_FORMAT_420BPP10;
ffbcd19a 501 break;
4562236b
HW
502 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
503 default:
504 dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
505 break;
506 }
507 return dal_pixel_format;
508}
509
9b6067c0
DL
510static inline void get_vp_scan_direction(
511 enum dc_rotation_angle rotation,
512 bool horizontal_mirror,
513 bool *orthogonal_rotation,
514 bool *flip_vert_scan_dir,
515 bool *flip_horz_scan_dir)
4562236b 516{
9b6067c0
DL
517 *orthogonal_rotation = false;
518 *flip_vert_scan_dir = false;
519 *flip_horz_scan_dir = false;
520 if (rotation == ROTATION_ANGLE_180) {
521 *flip_vert_scan_dir = true;
522 *flip_horz_scan_dir = true;
523 } else if (rotation == ROTATION_ANGLE_90) {
524 *orthogonal_rotation = true;
525 *flip_horz_scan_dir = true;
526 } else if (rotation == ROTATION_ANGLE_270) {
527 *orthogonal_rotation = true;
528 *flip_vert_scan_dir = true;
529 }
530
531 if (horizontal_mirror)
532 *flip_horz_scan_dir = !*flip_horz_scan_dir;
4562236b
HW
533}
534
5bf24270
DL
535static void calculate_split_count_and_index(struct pipe_ctx *pipe_ctx, int *split_count, int *split_idx)
536{
537 *split_count = get_num_odm_splits(pipe_ctx);
538 *split_idx = 0;
539 if (*split_count == 0) {
540 /*Check for mpc split*/
541 struct pipe_ctx *split_pipe = pipe_ctx->top_pipe;
542
543 while (split_pipe && split_pipe->plane_state == pipe_ctx->plane_state) {
544 (*split_idx)++;
545 (*split_count)++;
546 split_pipe = split_pipe->top_pipe;
547 }
548 split_pipe = pipe_ctx->bottom_pipe;
549 while (split_pipe && split_pipe->plane_state == pipe_ctx->plane_state) {
550 (*split_count)++;
551 split_pipe = split_pipe->bottom_pipe;
552 }
553 } else {
554 /*Get odm split index*/
555 struct pipe_ctx *split_pipe = pipe_ctx->prev_odm_pipe;
556
557 while (split_pipe) {
558 (*split_idx)++;
559 split_pipe = split_pipe->prev_odm_pipe;
560 }
561 }
562}
563
b2d0a103 564static void calculate_viewport(struct pipe_ctx *pipe_ctx)
4562236b 565{
3be5262e 566 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 567 const struct dc_stream_state *stream = pipe_ctx->stream;
6702a9ac 568 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
3be5262e 569 struct rect surf_src = plane_state->src_rect;
9b6067c0 570 struct rect clip, dest;
87449a90
AK
571 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
572 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
5bf24270
DL
573 int split_count = 0;
574 int split_idx = 0;
9b6067c0 575 bool orthogonal_rotation, flip_y_start, flip_x_start;
83d40659 576
5bf24270
DL
577 calculate_split_count_and_index(pipe_ctx, &split_count, &split_idx);
578
7f5c22d1
VP
579 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE ||
580 stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) {
5bf24270
DL
581 split_count = 0;
582 split_idx = 0;
7b779c99 583 }
86006a7f 584
4562236b
HW
585 /* The actual clip is an intersection between stream
586 * source and surface clip
587 */
9b6067c0 588 dest = plane_state->dst_rect;
3be5262e
HW
589 clip.x = stream->src.x > plane_state->clip_rect.x ?
590 stream->src.x : plane_state->clip_rect.x;
4562236b 591
1fbd2cfc 592 clip.width = stream->src.x + stream->src.width <
3be5262e 593 plane_state->clip_rect.x + plane_state->clip_rect.width ?
1fbd2cfc 594 stream->src.x + stream->src.width - clip.x :
3be5262e 595 plane_state->clip_rect.x + plane_state->clip_rect.width - clip.x ;
4562236b 596
3be5262e
HW
597 clip.y = stream->src.y > plane_state->clip_rect.y ?
598 stream->src.y : plane_state->clip_rect.y;
4562236b 599
1fbd2cfc 600 clip.height = stream->src.y + stream->src.height <
3be5262e 601 plane_state->clip_rect.y + plane_state->clip_rect.height ?
1fbd2cfc 602 stream->src.y + stream->src.height - clip.y :
3be5262e 603 plane_state->clip_rect.y + plane_state->clip_rect.height - clip.y ;
4562236b 604
9b6067c0
DL
605 /*
606 * Need to calculate how scan origin is shifted in vp space
607 * to correctly rotate clip and dst
608 */
609 get_vp_scan_direction(
610 plane_state->rotation,
611 plane_state->horizontal_mirror,
612 &orthogonal_rotation,
613 &flip_y_start,
614 &flip_x_start);
615
616 if (orthogonal_rotation) {
617 swap(clip.x, clip.y);
618 swap(clip.width, clip.height);
619 swap(dest.x, dest.y);
620 swap(dest.width, dest.height);
621 }
622 if (flip_x_start) {
623 clip.x = dest.x + dest.width - clip.x - clip.width;
624 dest.x = 0;
625 }
626 if (flip_y_start) {
627 clip.y = dest.y + dest.height - clip.y - clip.height;
628 dest.y = 0;
629 }
630
86006a7f 631 /* offset = surf_src.ofs + (clip.ofs - surface->dst_rect.ofs) * scl_ratio
4562236b
HW
632 * num_pixels = clip.num_pix * scl_ratio
633 */
9b6067c0
DL
634 data->viewport.x = surf_src.x + (clip.x - dest.x) * surf_src.width / dest.width;
635 data->viewport.width = clip.width * surf_src.width / dest.width;
636
637 data->viewport.y = surf_src.y + (clip.y - dest.y) * surf_src.height / dest.height;
638 data->viewport.height = clip.height * surf_src.height / dest.height;
639
640 /* Handle split */
5bf24270
DL
641 if (split_count) {
642 /* extra pixels in the division remainder need to go to pipes after
643 * the extra pixel index minus one(epimo) defined here as:
644 */
645 int epimo = 0;
646
9b6067c0 647 if (orthogonal_rotation) {
5bf24270
DL
648 if (flip_y_start)
649 split_idx = split_count - split_idx;
650
651 epimo = split_count - data->viewport.height % (split_count + 1);
652
653 data->viewport.y += (data->viewport.height / (split_count + 1)) * split_idx;
654 if (split_idx > epimo)
655 data->viewport.y += split_idx - epimo - 1;
656 data->viewport.height = data->viewport.height / (split_count + 1) + (split_idx > epimo ? 1 : 0);
9b6067c0 657 } else {
5bf24270
DL
658 if (flip_x_start)
659 split_idx = split_count - split_idx;
660
661 epimo = split_count - data->viewport.width % (split_count + 1);
662
663 data->viewport.x += (data->viewport.width / (split_count + 1)) * split_idx;
664 if (split_idx > epimo)
665 data->viewport.x += split_idx - epimo - 1;
666 data->viewport.width = data->viewport.width / (split_count + 1) + (split_idx > epimo ? 1 : 0);
9b6067c0
DL
667 }
668 }
9b5349f7 669
b2d0a103
DL
670 /* Round down, compensate in init */
671 data->viewport_c.x = data->viewport.x / vpc_div;
672 data->viewport_c.y = data->viewport.y / vpc_div;
9b6067c0
DL
673 data->inits.h_c = (data->viewport.x % vpc_div) != 0 ? dc_fixpt_half : dc_fixpt_zero;
674 data->inits.v_c = (data->viewport.y % vpc_div) != 0 ? dc_fixpt_half : dc_fixpt_zero;
675
b2d0a103
DL
676 /* Round up, assume original video size always even dimensions */
677 data->viewport_c.width = (data->viewport.width + vpc_div - 1) / vpc_div;
678 data->viewport_c.height = (data->viewport.height + vpc_div - 1) / vpc_div;
4562236b
HW
679}
680
9b6067c0 681static void calculate_recout(struct pipe_ctx *pipe_ctx)
4562236b 682{
3be5262e 683 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 684 const struct dc_stream_state *stream = pipe_ctx->stream;
5bf24270 685 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
3be5262e 686 struct rect surf_clip = plane_state->clip_rect;
5bf24270
DL
687 bool pri_split_tb = pipe_ctx->bottom_pipe &&
688 pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state &&
689 stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM;
690 bool sec_split_tb = pipe_ctx->top_pipe &&
691 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state &&
692 stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM;
693 int split_count = 0;
694 int split_idx = 0;
695
696 calculate_split_count_and_index(pipe_ctx, &split_count, &split_idx);
697
698 data->recout.x = stream->dst.x;
4fa086b9 699 if (stream->src.x < surf_clip.x)
5bf24270 700 data->recout.x += (surf_clip.x - stream->src.x) * stream->dst.width
4fa086b9 701 / stream->src.width;
4562236b 702
5bf24270
DL
703 data->recout.width = surf_clip.width * stream->dst.width / stream->src.width;
704 if (data->recout.width + data->recout.x > stream->dst.x + stream->dst.width)
705 data->recout.width = stream->dst.x + stream->dst.width - data->recout.x;
4562236b 706
5bf24270 707 data->recout.y = stream->dst.y;
4fa086b9 708 if (stream->src.y < surf_clip.y)
5bf24270 709 data->recout.y += (surf_clip.y - stream->src.y) * stream->dst.height
4fa086b9 710 / stream->src.height;
4562236b 711
5bf24270
DL
712 data->recout.height = surf_clip.height * stream->dst.height / stream->src.height;
713 if (data->recout.height + data->recout.y > stream->dst.y + stream->dst.height)
714 data->recout.height = stream->dst.y + stream->dst.height - data->recout.y;
b2d0a103 715
9b6067c0 716 /* Handle h & v split, handle rotation using viewport */
5bf24270
DL
717 if (sec_split_tb) {
718 data->recout.y += data->recout.height / 2;
0c31a821 719 /* Floor primary pipe, ceil 2ndary pipe */
5bf24270
DL
720 data->recout.height = (data->recout.height + 1) / 2;
721 } else if (pri_split_tb)
722 data->recout.height /= 2;
723 else if (split_count) {
724 /* extra pixels in the division remainder need to go to pipes after
725 * the extra pixel index minus one(epimo) defined here as:
726 */
727 int epimo = split_count - data->recout.width % (split_count + 1);
728
729 /*no recout offset due to odm */
730 if (!pipe_ctx->next_odm_pipe && !pipe_ctx->prev_odm_pipe) {
731 data->recout.x += (data->recout.width / (split_count + 1)) * split_idx;
732 if (split_idx > epimo)
733 data->recout.x += split_idx - epimo - 1;
734 }
735 data->recout.width = data->recout.width / (split_count + 1) + (split_idx > epimo ? 1 : 0);
736 }
4562236b
HW
737}
738
b2d0a103 739static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)
4562236b 740{
3be5262e 741 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 742 const struct dc_stream_state *stream = pipe_ctx->stream;
3be5262e 743 struct rect surf_src = plane_state->src_rect;
4fa086b9
LSL
744 const int in_w = stream->src.width;
745 const int in_h = stream->src.height;
746 const int out_w = stream->dst.width;
747 const int out_h = stream->dst.height;
4562236b 748
9b6067c0 749 /*Swap surf_src height and width since scaling ratios are in recout rotation*/
3be5262e
HW
750 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
751 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
9b6067c0 752 swap(surf_src.height, surf_src.width);
86006a7f 753
eb0e5154 754 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_from_fraction(
86006a7f 755 surf_src.width,
3be5262e 756 plane_state->dst_rect.width);
eb0e5154 757 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction(
86006a7f 758 surf_src.height,
3be5262e 759 plane_state->dst_rect.height);
4562236b 760
4fa086b9 761 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
6702a9ac 762 pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2;
4fa086b9 763 else if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
6702a9ac 764 pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2;
4562236b 765
6702a9ac
HW
766 pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64(
767 pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h);
768 pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64(
769 pipe_ctx->plane_res.scl_data.ratios.horz.value * in_w, out_w);
4562236b 770
6702a9ac
HW
771 pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz;
772 pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert;
4562236b 773
6702a9ac
HW
774 if (pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP8
775 || pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP10) {
776 pipe_ctx->plane_res.scl_data.ratios.horz_c.value /= 2;
777 pipe_ctx->plane_res.scl_data.ratios.vert_c.value /= 2;
4562236b 778 }
0002d3ac
DL
779 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_truncate(
780 pipe_ctx->plane_res.scl_data.ratios.horz, 19);
781 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_truncate(
782 pipe_ctx->plane_res.scl_data.ratios.vert, 19);
783 pipe_ctx->plane_res.scl_data.ratios.horz_c = dc_fixpt_truncate(
784 pipe_ctx->plane_res.scl_data.ratios.horz_c, 19);
785 pipe_ctx->plane_res.scl_data.ratios.vert_c = dc_fixpt_truncate(
786 pipe_ctx->plane_res.scl_data.ratios.vert_c, 19);
4562236b
HW
787}
788
9b6067c0
DL
789static inline void adjust_vp_and_init_for_seamless_clip(
790 bool flip_scan_dir,
791 int recout_skip,
792 int src_size,
793 int taps,
794 struct fixed31_32 ratio,
795 struct fixed31_32 *init,
796 int *vp_offset,
797 int *vp_size)
b2d0a103 798{
9b6067c0 799 if (!flip_scan_dir) {
9a08f51f 800 /* Adjust for viewport end clip-off */
9b6067c0
DL
801 if ((*vp_offset + *vp_size) < src_size) {
802 int vp_clip = src_size - *vp_size - *vp_offset;
803 int int_part = dc_fixpt_floor(dc_fixpt_sub(*init, ratio));
9a08f51f
DL
804
805 int_part = int_part > 0 ? int_part : 0;
9b6067c0 806 *vp_size += int_part < vp_clip ? int_part : vp_clip;
9a08f51f 807 }
b2d0a103 808
9a08f51f 809 /* Adjust for non-0 viewport offset */
9b6067c0 810 if (*vp_offset) {
9a08f51f
DL
811 int int_part;
812
9b6067c0
DL
813 *init = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_skip));
814 int_part = dc_fixpt_floor(*init) - *vp_offset;
815 if (int_part < taps) {
816 int int_adj = *vp_offset >= (taps - int_part) ?
817 (taps - int_part) : *vp_offset;
818 *vp_offset -= int_adj;
819 *vp_size += int_adj;
9a08f51f 820 int_part += int_adj;
9b6067c0
DL
821 } else if (int_part > taps) {
822 *vp_offset += int_part - taps;
823 *vp_size -= int_part - taps;
824 int_part = taps;
9a08f51f 825 }
9b6067c0
DL
826 init->value &= 0xffffffff;
827 *init = dc_fixpt_add_int(*init, int_part);
9a08f51f
DL
828 }
829 } else {
830 /* Adjust for non-0 viewport offset */
9b6067c0
DL
831 if (*vp_offset) {
832 int int_part = dc_fixpt_floor(dc_fixpt_sub(*init, ratio));
b2d0a103 833
9a08f51f 834 int_part = int_part > 0 ? int_part : 0;
9b6067c0
DL
835 *vp_size += int_part < *vp_offset ? int_part : *vp_offset;
836 *vp_offset -= int_part < *vp_offset ? int_part : *vp_offset;
9a08f51f 837 }
b2d0a103 838
9a08f51f 839 /* Adjust for viewport end clip-off */
9b6067c0 840 if ((*vp_offset + *vp_size) < src_size) {
9a08f51f 841 int int_part;
9b6067c0 842 int end_offset = src_size - *vp_offset - *vp_size;
9a08f51f
DL
843
844 /*
845 * this is init if vp had no offset, keep in mind this is from the
846 * right side of vp due to scan direction
847 */
9b6067c0 848 *init = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_skip));
9a08f51f
DL
849 /*
850 * this is the difference between first pixel of viewport available to read
851 * and init position, takning into account scan direction
852 */
9b6067c0
DL
853 int_part = dc_fixpt_floor(*init) - end_offset;
854 if (int_part < taps) {
855 int int_adj = end_offset >= (taps - int_part) ?
856 (taps - int_part) : end_offset;
857 *vp_size += int_adj;
9a08f51f 858 int_part += int_adj;
9b6067c0
DL
859 } else if (int_part > taps) {
860 *vp_size += int_part - taps;
861 int_part = taps;
9a08f51f 862 }
9b6067c0
DL
863 init->value &= 0xffffffff;
864 *init = dc_fixpt_add_int(*init, int_part);
b2d0a103 865 }
b2d0a103 866 }
9b6067c0 867}
9a08f51f 868
9b6067c0
DL
869static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx)
870{
871 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
872 const struct dc_stream_state *stream = pipe_ctx->stream;
5bf24270 873 struct pipe_ctx *odm_pipe = pipe_ctx->prev_odm_pipe;
9b6067c0
DL
874 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
875 struct rect src = pipe_ctx->plane_state->src_rect;
876 int recout_skip_h, recout_skip_v, surf_size_h, surf_size_v;
877 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
878 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
879 bool orthogonal_rotation, flip_vert_scan_dir, flip_horz_scan_dir;
9a08f51f 880
9b6067c0
DL
881 /*
882 * Need to calculate the scan direction for viewport to make adjustments
883 */
884 get_vp_scan_direction(
885 plane_state->rotation,
886 plane_state->horizontal_mirror,
887 &orthogonal_rotation,
888 &flip_vert_scan_dir,
889 &flip_horz_scan_dir);
890
891 /* Calculate src rect rotation adjusted to recout space */
892 surf_size_h = src.x + src.width;
893 surf_size_v = src.y + src.height;
894 if (flip_horz_scan_dir)
895 src.x = 0;
896 if (flip_vert_scan_dir)
897 src.y = 0;
898 if (orthogonal_rotation) {
899 swap(src.x, src.y);
900 swap(src.width, src.height);
901 }
9a08f51f 902
9b6067c0
DL
903 /* Recout matching initial vp offset = recout_offset - (stream dst offset +
904 * ((surf dst offset - stream src offset) * 1/ stream scaling ratio)
905 * - (surf surf_src offset * 1/ full scl ratio))
906 */
907 recout_skip_h = data->recout.x - (stream->dst.x + (plane_state->dst_rect.x - stream->src.x)
908 * stream->dst.width / stream->src.width -
909 src.x * plane_state->dst_rect.width / src.width
910 * stream->dst.width / stream->src.width);
5bf24270
DL
911 /*modified recout_skip_h calculation due to odm having no recout offset caused by split*/
912 while (odm_pipe) {
913 recout_skip_h += odm_pipe->plane_res.scl_data.recout.width + odm_pipe->plane_res.scl_data.recout.x;
914 odm_pipe = odm_pipe->prev_odm_pipe;
915 }
916
9b6067c0
DL
917 recout_skip_v = data->recout.y - (stream->dst.y + (plane_state->dst_rect.y - stream->src.y)
918 * stream->dst.height / stream->src.height -
919 src.y * plane_state->dst_rect.height / src.height
920 * stream->dst.height / stream->src.height);
921 if (orthogonal_rotation)
922 swap(recout_skip_h, recout_skip_v);
923 /*
924 * Init calculated according to formula:
925 * init = (scaling_ratio + number_of_taps + 1) / 2
926 * init_bot = init + scaling_ratio
927 * init_c = init + truncated_vp_c_offset(from calculate viewport)
928 */
929 data->inits.h = dc_fixpt_truncate(dc_fixpt_div_int(
930 dc_fixpt_add_int(data->ratios.horz, data->taps.h_taps + 1), 2), 19);
b2d0a103 931
9b6067c0
DL
932 data->inits.h_c = dc_fixpt_truncate(dc_fixpt_add(data->inits.h_c, dc_fixpt_div_int(
933 dc_fixpt_add_int(data->ratios.horz_c, data->taps.h_taps_c + 1), 2)), 19);
9a08f51f 934
9b6067c0
DL
935 data->inits.v = dc_fixpt_truncate(dc_fixpt_div_int(
936 dc_fixpt_add_int(data->ratios.vert, data->taps.v_taps + 1), 2), 19);
9a08f51f 937
9b6067c0
DL
938 data->inits.v_c = dc_fixpt_truncate(dc_fixpt_add(data->inits.v_c, dc_fixpt_div_int(
939 dc_fixpt_add_int(data->ratios.vert_c, data->taps.v_taps_c + 1), 2)), 19);
9a08f51f 940
9b6067c0
DL
941 /*
942 * Taps, inits and scaling ratios are in recout space need to rotate
943 * to viewport rotation before adjustment
944 */
945 adjust_vp_and_init_for_seamless_clip(
946 flip_horz_scan_dir,
947 recout_skip_h,
948 surf_size_h,
949 orthogonal_rotation ? data->taps.v_taps : data->taps.h_taps,
950 orthogonal_rotation ? data->ratios.vert : data->ratios.horz,
951 orthogonal_rotation ? &data->inits.v : &data->inits.h,
952 &data->viewport.x,
953 &data->viewport.width);
954 adjust_vp_and_init_for_seamless_clip(
955 flip_horz_scan_dir,
956 recout_skip_h,
957 surf_size_h / vpc_div,
958 orthogonal_rotation ? data->taps.v_taps_c : data->taps.h_taps_c,
959 orthogonal_rotation ? data->ratios.vert_c : data->ratios.horz_c,
960 orthogonal_rotation ? &data->inits.v_c : &data->inits.h_c,
961 &data->viewport_c.x,
962 &data->viewport_c.width);
963 adjust_vp_and_init_for_seamless_clip(
964 flip_vert_scan_dir,
965 recout_skip_v,
966 surf_size_v,
967 orthogonal_rotation ? data->taps.h_taps : data->taps.v_taps,
968 orthogonal_rotation ? data->ratios.horz : data->ratios.vert,
969 orthogonal_rotation ? &data->inits.h : &data->inits.v,
970 &data->viewport.y,
971 &data->viewport.height);
972 adjust_vp_and_init_for_seamless_clip(
973 flip_vert_scan_dir,
974 recout_skip_v,
975 surf_size_v / vpc_div,
976 orthogonal_rotation ? data->taps.h_taps_c : data->taps.v_taps_c,
977 orthogonal_rotation ? data->ratios.horz_c : data->ratios.vert_c,
978 orthogonal_rotation ? &data->inits.h_c : &data->inits.v_c,
979 &data->viewport_c.y,
980 &data->viewport_c.height);
b2d0a103
DL
981
982 /* Interlaced inits based on final vert inits */
eb0e5154
DL
983 data->inits.v_bot = dc_fixpt_add(data->inits.v, data->ratios.vert);
984 data->inits.v_c_bot = dc_fixpt_add(data->inits.v_c, data->ratios.vert_c);
1fbd2cfc 985
b2d0a103 986}
3b733278 987
89d07b66
ST
988/*
989 * When handling 270 rotation in mixed SLS mode, we have
990 * stream->timing.h_border_left that is non zero. If we are doing
991 * pipe-splitting, this h_border_left value gets added to recout.x and when it
992 * calls calculate_inits_and_adj_vp() and
993 * adjust_vp_and_init_for_seamless_clip(), it can cause viewport.height for a
994 * pipe to be incorrect.
995 *
996 * To fix this, instead of using stream->timing.h_border_left, we can use
997 * stream->dst.x to represent the border instead. So we will set h_border_left
998 * to 0 and shift the appropriate amount in stream->dst.x. We will then
999 * perform all calculations in resource_build_scaling_params() based on this
1000 * and then restore the h_border_left and stream->dst.x to their original
1001 * values.
1002 *
1003 * shift_border_left_to_dst() will shift the amount of h_border_left to
1004 * stream->dst.x and set h_border_left to 0. restore_border_left_from_dst()
1005 * will restore h_border_left and stream->dst.x back to their original values
1006 * We also need to make sure pipe_ctx->plane_res.scl_data.h_active uses the
1007 * original h_border_left value in its calculation.
1008 */
1009int shift_border_left_to_dst(struct pipe_ctx *pipe_ctx)
1010{
1011 int store_h_border_left = pipe_ctx->stream->timing.h_border_left;
1012
1013 if (store_h_border_left) {
1014 pipe_ctx->stream->timing.h_border_left = 0;
1015 pipe_ctx->stream->dst.x += store_h_border_left;
1016 }
1017 return store_h_border_left;
1018}
1019
1020void restore_border_left_from_dst(struct pipe_ctx *pipe_ctx,
1021 int store_h_border_left)
1022{
1023 pipe_ctx->stream->dst.x -= store_h_border_left;
1024 pipe_ctx->stream->timing.h_border_left = store_h_border_left;
1025}
1026
b2d0a103 1027bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
4562236b 1028{
3be5262e 1029 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
4fa086b9 1030 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
b2d0a103 1031 bool res = false;
89d07b66 1032 int store_h_border_left = shift_border_left_to_dst(pipe_ctx);
5d4b05dd 1033 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
4562236b
HW
1034 /* Important: scaling ratio calculation requires pixel format,
1035 * lb depth calculation requires recout and taps require scaling ratios.
b2d0a103 1036 * Inits require viewport, taps, ratios and recout of split pipe
4562236b 1037 */
6702a9ac 1038 pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface(
3be5262e 1039 pipe_ctx->plane_state->format);
b2d0a103
DL
1040
1041 calculate_scaling_ratios(pipe_ctx);
4562236b 1042
b2d0a103 1043 calculate_viewport(pipe_ctx);
4562236b 1044
89d07b66
ST
1045 if (pipe_ctx->plane_res.scl_data.viewport.height < 16 ||
1046 pipe_ctx->plane_res.scl_data.viewport.width < 16) {
1047 if (store_h_border_left) {
1048 restore_border_left_from_dst(pipe_ctx,
1049 store_h_border_left);
1050 }
4562236b 1051 return false;
89d07b66 1052 }
4562236b 1053
9b6067c0 1054 calculate_recout(pipe_ctx);
4562236b
HW
1055
1056 /**
1057 * Setting line buffer pixel depth to 24bpp yields banding
1058 * on certain displays, such as the Sharp 4k
1059 */
6702a9ac 1060 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
4562236b 1061
199e458a 1062 pipe_ctx->plane_res.scl_data.recout.x += timing->h_border_left;
58bb0e63 1063 pipe_ctx->plane_res.scl_data.recout.y += timing->v_border_top;
199e458a 1064
89d07b66
ST
1065 pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable +
1066 store_h_border_left + timing->h_border_right;
1067 pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable +
1068 timing->v_border_top + timing->v_border_bottom;
5bf24270
DL
1069 if (pipe_ctx->next_odm_pipe || pipe_ctx->prev_odm_pipe)
1070 pipe_ctx->plane_res.scl_data.h_active /= get_num_odm_splits(pipe_ctx) + 1;
1b6c8067 1071
4562236b 1072 /* Taps calculations */
d94585a0
YHL
1073 if (pipe_ctx->plane_res.xfm != NULL)
1074 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
1075 pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
1076
1077 if (pipe_ctx->plane_res.dpp != NULL)
1078 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
1079 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
f7938bc0 1080
f7938bc0 1081
4562236b
HW
1082 if (!res) {
1083 /* Try 24 bpp linebuffer */
6702a9ac 1084 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP;
4562236b 1085
1b6c8067
BL
1086 if (pipe_ctx->plane_res.xfm != NULL)
1087 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
1088 pipe_ctx->plane_res.xfm,
1089 &pipe_ctx->plane_res.scl_data,
1090 &plane_state->scaling_quality);
1091
1092 if (pipe_ctx->plane_res.dpp != NULL)
1093 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
1094 pipe_ctx->plane_res.dpp,
1095 &pipe_ctx->plane_res.scl_data,
1096 &plane_state->scaling_quality);
4562236b
HW
1097 }
1098
b2d0a103 1099 if (res)
1fbd2cfc 1100 /* May need to re-check lb size after this in some obscure scenario */
9b6067c0 1101 calculate_inits_and_adj_vp(pipe_ctx);
b2d0a103 1102
1296423b 1103 DC_LOG_SCALER(
4562236b
HW
1104 "%s: Viewport:\nheight:%d width:%d x:%d "
1105 "y:%d\n dst_rect:\nheight:%d width:%d x:%d "
1106 "y:%d\n",
1107 __func__,
6702a9ac
HW
1108 pipe_ctx->plane_res.scl_data.viewport.height,
1109 pipe_ctx->plane_res.scl_data.viewport.width,
1110 pipe_ctx->plane_res.scl_data.viewport.x,
1111 pipe_ctx->plane_res.scl_data.viewport.y,
3be5262e
HW
1112 plane_state->dst_rect.height,
1113 plane_state->dst_rect.width,
1114 plane_state->dst_rect.x,
1115 plane_state->dst_rect.y);
4562236b 1116
89d07b66
ST
1117 if (store_h_border_left)
1118 restore_border_left_from_dst(pipe_ctx, store_h_border_left);
1119
4562236b
HW
1120 return res;
1121}
1122
1123
1124enum dc_status resource_build_scaling_params_for_context(
fb3466a4 1125 const struct dc *dc,
608ac7bb 1126 struct dc_state *context)
4562236b
HW
1127{
1128 int i;
1129
1130 for (i = 0; i < MAX_PIPES; i++) {
3be5262e 1131 if (context->res_ctx.pipe_ctx[i].plane_state != NULL &&
4562236b 1132 context->res_ctx.pipe_ctx[i].stream != NULL)
b2d0a103 1133 if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i]))
f84a8161 1134 return DC_FAIL_SCALING;
4562236b
HW
1135 }
1136
1137 return DC_OK;
1138}
1139
a2b8659d
TC
1140struct pipe_ctx *find_idle_secondary_pipe(
1141 struct resource_context *res_ctx,
5581192d
JL
1142 const struct resource_pool *pool,
1143 const struct pipe_ctx *primary_pipe)
4562236b
HW
1144{
1145 int i;
1146 struct pipe_ctx *secondary_pipe = NULL;
1147
1148 /*
5581192d
JL
1149 * We add a preferred pipe mapping to avoid the chance that
1150 * MPCCs already in use will need to be reassigned to other trees.
1151 * For example, if we went with the strict, assign backwards logic:
1152 *
1153 * (State 1)
1154 * Display A on, no surface, top pipe = 0
1155 * Display B on, no surface, top pipe = 1
1156 *
1157 * (State 2)
1158 * Display A on, no surface, top pipe = 0
1159 * Display B on, surface enable, top pipe = 1, bottom pipe = 5
1160 *
1161 * (State 3)
1162 * Display A on, surface enable, top pipe = 0, bottom pipe = 5
1163 * Display B on, surface enable, top pipe = 1, bottom pipe = 4
1164 *
1165 * The state 2->3 transition requires remapping MPCC 5 from display B
1166 * to display A.
1167 *
1168 * However, with the preferred pipe logic, state 2 would look like:
1169 *
1170 * (State 2)
1171 * Display A on, no surface, top pipe = 0
1172 * Display B on, surface enable, top pipe = 1, bottom pipe = 4
1173 *
1174 * This would then cause 2->3 to not require remapping any MPCCs.
4562236b 1175 */
5581192d
JL
1176 if (primary_pipe) {
1177 int preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx;
1178 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
1179 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
1180 secondary_pipe->pipe_idx = preferred_pipe_idx;
4562236b
HW
1181 }
1182 }
1183
5581192d
JL
1184 /*
1185 * search backwards for the second pipe to keep pipe
1186 * assignment more consistent
1187 */
1188 if (!secondary_pipe)
1189 for (i = pool->pipe_count - 1; i >= 0; i--) {
1190 if (res_ctx->pipe_ctx[i].stream == NULL) {
1191 secondary_pipe = &res_ctx->pipe_ctx[i];
1192 secondary_pipe->pipe_idx = i;
1193 break;
1194 }
1195 }
4562236b
HW
1196
1197 return secondary_pipe;
1198}
1199
1200struct pipe_ctx *resource_get_head_pipe_for_stream(
1201 struct resource_context *res_ctx,
0971c40e 1202 struct dc_stream_state *stream)
4562236b
HW
1203{
1204 int i;
22498036 1205
a2b8659d 1206 for (i = 0; i < MAX_PIPES; i++) {
b1f6d01c
DL
1207 if (res_ctx->pipe_ctx[i].stream == stream
1208 && !res_ctx->pipe_ctx[i].top_pipe
22498036 1209 && !res_ctx->pipe_ctx[i].prev_odm_pipe)
4562236b 1210 return &res_ctx->pipe_ctx[i];
4562236b
HW
1211 }
1212 return NULL;
1213}
1214
b1f6d01c 1215static struct pipe_ctx *resource_get_tail_pipe(
19f89e23 1216 struct resource_context *res_ctx,
b1f6d01c 1217 struct pipe_ctx *head_pipe)
19f89e23 1218{
b1f6d01c 1219 struct pipe_ctx *tail_pipe;
19f89e23
AG
1220
1221 tail_pipe = head_pipe->bottom_pipe;
1222
1223 while (tail_pipe) {
1224 head_pipe = tail_pipe;
1225 tail_pipe = tail_pipe->bottom_pipe;
1226 }
1227
1228 return head_pipe;
1229}
1230
4562236b 1231/*
ab2541b6
AC
1232 * A free_pipe for a stream is defined here as a pipe
1233 * that has no surface attached yet
4562236b 1234 */
b1f6d01c 1235static struct pipe_ctx *acquire_free_pipe_for_head(
608ac7bb 1236 struct dc_state *context,
a2b8659d 1237 const struct resource_pool *pool,
b1f6d01c 1238 struct pipe_ctx *head_pipe)
4562236b
HW
1239{
1240 int i;
745cc746 1241 struct resource_context *res_ctx = &context->res_ctx;
4562236b 1242
3be5262e 1243 if (!head_pipe->plane_state)
4562236b
HW
1244 return head_pipe;
1245
1246 /* Re-use pipe already acquired for this stream if available*/
a2b8659d 1247 for (i = pool->pipe_count - 1; i >= 0; i--) {
b1f6d01c 1248 if (res_ctx->pipe_ctx[i].stream == head_pipe->stream &&
3be5262e 1249 !res_ctx->pipe_ctx[i].plane_state) {
4562236b
HW
1250 return &res_ctx->pipe_ctx[i];
1251 }
1252 }
1253
1254 /*
1255 * At this point we have no re-useable pipe for this stream and we need
1256 * to acquire an idle one to satisfy the request
1257 */
1258
a2b8659d 1259 if (!pool->funcs->acquire_idle_pipe_for_layer)
4562236b
HW
1260 return NULL;
1261
b1f6d01c 1262 return pool->funcs->acquire_idle_pipe_for_layer(context, pool, head_pipe->stream);
4562236b
HW
1263}
1264
b86a1aa3 1265#if defined(CONFIG_DRM_AMD_DC_DCN)
0f9a536f
DL
1266static int acquire_first_split_pipe(
1267 struct resource_context *res_ctx,
1268 const struct resource_pool *pool,
0971c40e 1269 struct dc_stream_state *stream)
0f9a536f
DL
1270{
1271 int i;
1272
1273 for (i = 0; i < pool->pipe_count; i++) {
79592db3
DL
1274 struct pipe_ctx *split_pipe = &res_ctx->pipe_ctx[i];
1275
b1f6d01c 1276 if (split_pipe->top_pipe &&
79592db3
DL
1277 split_pipe->top_pipe->plane_state == split_pipe->plane_state) {
1278 split_pipe->top_pipe->bottom_pipe = split_pipe->bottom_pipe;
1279 if (split_pipe->bottom_pipe)
1280 split_pipe->bottom_pipe->top_pipe = split_pipe->top_pipe;
1281
1282 if (split_pipe->top_pipe->plane_state)
1283 resource_build_scaling_params(split_pipe->top_pipe);
1284
1285 memset(split_pipe, 0, sizeof(*split_pipe));
1286 split_pipe->stream_res.tg = pool->timing_generators[i];
1287 split_pipe->plane_res.hubp = pool->hubps[i];
1288 split_pipe->plane_res.ipp = pool->ipps[i];
1289 split_pipe->plane_res.dpp = pool->dpps[i];
1290 split_pipe->stream_res.opp = pool->opps[i];
1291 split_pipe->plane_res.mpcc_inst = pool->dpps[i]->inst;
1292 split_pipe->pipe_idx = i;
1293
1294 split_pipe->stream = stream;
0f9a536f
DL
1295 return i;
1296 }
1297 }
1298 return -1;
1299}
1300#endif
1301
19f89e23
AG
1302bool dc_add_plane_to_context(
1303 const struct dc *dc,
0971c40e 1304 struct dc_stream_state *stream,
19f89e23 1305 struct dc_plane_state *plane_state,
608ac7bb 1306 struct dc_state *context)
4562236b
HW
1307{
1308 int i;
19f89e23
AG
1309 struct resource_pool *pool = dc->res_pool;
1310 struct pipe_ctx *head_pipe, *tail_pipe, *free_pipe;
ab2541b6 1311 struct dc_stream_status *stream_status = NULL;
4562236b 1312
19f89e23
AG
1313 for (i = 0; i < context->stream_count; i++)
1314 if (context->streams[i] == stream) {
1315 stream_status = &context->stream_status[i];
1316 break;
1317 }
1318 if (stream_status == NULL) {
1319 dm_error("Existing stream not found; failed to attach surface!\n");
1320 return false;
1321 }
1322
4562236b 1323
19f89e23
AG
1324 if (stream_status->plane_count == MAX_SURFACE_NUM) {
1325 dm_error("Surface: can not attach plane_state %p! Maximum is: %d\n",
1326 plane_state, MAX_SURFACE_NUM);
4562236b
HW
1327 return false;
1328 }
1329
19f89e23
AG
1330 head_pipe = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
1331
1332 if (!head_pipe) {
1333 dm_error("Head pipe not found for stream_state %p !\n", stream);
1334 return false;
1335 }
1336
b1f6d01c
DL
1337 /* retain new surface, but only once per stream */
1338 dc_plane_state_retain(plane_state);
00737c59 1339
b1f6d01c
DL
1340 while (head_pipe) {
1341 tail_pipe = resource_get_tail_pipe(&context->res_ctx, head_pipe);
1342 ASSERT(tail_pipe);
19f89e23 1343
b1f6d01c 1344 free_pipe = acquire_free_pipe_for_head(context, pool, head_pipe);
19f89e23 1345
b86a1aa3 1346 #if defined(CONFIG_DRM_AMD_DC_DCN)
b1f6d01c
DL
1347 if (!free_pipe) {
1348 int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
1349 if (pipe_idx >= 0)
1350 free_pipe = &context->res_ctx.pipe_ctx[pipe_idx];
1351 }
1352 #endif
1353 if (!free_pipe) {
1354 dc_plane_state_release(plane_state);
1355 return false;
1356 }
19f89e23 1357
b1f6d01c
DL
1358 free_pipe->plane_state = plane_state;
1359
1360 if (head_pipe != free_pipe) {
1361 free_pipe->stream_res.tg = tail_pipe->stream_res.tg;
1362 free_pipe->stream_res.abm = tail_pipe->stream_res.abm;
1363 free_pipe->stream_res.opp = tail_pipe->stream_res.opp;
1364 free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc;
1365 free_pipe->stream_res.audio = tail_pipe->stream_res.audio;
1366 free_pipe->clock_source = tail_pipe->clock_source;
1367 free_pipe->top_pipe = tail_pipe;
1368 tail_pipe->bottom_pipe = free_pipe;
1369 }
1370 head_pipe = head_pipe->next_odm_pipe;
1371 }
19f89e23
AG
1372 /* assign new surfaces*/
1373 stream_status->plane_states[stream_status->plane_count] = plane_state;
1374
1375 stream_status->plane_count++;
1376
1377 return true;
1378}
1379
1380bool dc_remove_plane_from_context(
1381 const struct dc *dc,
1382 struct dc_stream_state *stream,
1383 struct dc_plane_state *plane_state,
608ac7bb 1384 struct dc_state *context)
19f89e23
AG
1385{
1386 int i;
1387 struct dc_stream_status *stream_status = NULL;
1388 struct resource_pool *pool = dc->res_pool;
1389
ab2541b6 1390 for (i = 0; i < context->stream_count; i++)
4fa086b9 1391 if (context->streams[i] == stream) {
ab2541b6 1392 stream_status = &context->stream_status[i];
4562236b
HW
1393 break;
1394 }
19f89e23 1395
ab2541b6 1396 if (stream_status == NULL) {
19f89e23 1397 dm_error("Existing stream not found; failed to remove plane.\n");
4562236b
HW
1398 return false;
1399 }
1400
19f89e23
AG
1401 /* release pipe for plane*/
1402 for (i = pool->pipe_count - 1; i >= 0; i--) {
6ffaa6fc 1403 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
4562236b 1404
6ffaa6fc 1405 if (pipe_ctx->plane_state == plane_state) {
19f89e23
AG
1406 if (pipe_ctx->top_pipe)
1407 pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;
4562236b 1408
19f89e23
AG
1409 /* Second condition is to avoid setting NULL to top pipe
1410 * of tail pipe making it look like head pipe in subsequent
1411 * deletes
1412 */
1413 if (pipe_ctx->bottom_pipe && pipe_ctx->top_pipe)
1414 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;
4562236b 1415
19f89e23
AG
1416 /*
1417 * For head pipe detach surfaces from pipe for tail
1418 * pipe just zero it out
1419 */
b1f6d01c 1420 if (!pipe_ctx->top_pipe)
19f89e23 1421 pipe_ctx->plane_state = NULL;
b1f6d01c 1422 else
19f89e23 1423 memset(pipe_ctx, 0, sizeof(*pipe_ctx));
4562236b 1424 }
19f89e23 1425 }
4562236b 1426
4562236b 1427
19f89e23
AG
1428 for (i = 0; i < stream_status->plane_count; i++) {
1429 if (stream_status->plane_states[i] == plane_state) {
1430
1431 dc_plane_state_release(stream_status->plane_states[i]);
1432 break;
4562236b 1433 }
19f89e23 1434 }
4562236b 1435
19f89e23
AG
1436 if (i == stream_status->plane_count) {
1437 dm_error("Existing plane_state not found; failed to detach it!\n");
1438 return false;
4562236b
HW
1439 }
1440
19f89e23 1441 stream_status->plane_count--;
4562236b 1442
abb4986e
AJ
1443 /* Start at the plane we've just released, and move all the planes one index forward to "trim" the array */
1444 for (; i < stream_status->plane_count; i++)
19f89e23
AG
1445 stream_status->plane_states[i] = stream_status->plane_states[i + 1];
1446
1447 stream_status->plane_states[stream_status->plane_count] = NULL;
1448
1449 return true;
1450}
1451
1452bool dc_rem_all_planes_for_stream(
1453 const struct dc *dc,
1454 struct dc_stream_state *stream,
608ac7bb 1455 struct dc_state *context)
19f89e23
AG
1456{
1457 int i, old_plane_count;
1458 struct dc_stream_status *stream_status = NULL;
1459 struct dc_plane_state *del_planes[MAX_SURFACE_NUM] = { 0 };
1460
1461 for (i = 0; i < context->stream_count; i++)
1462 if (context->streams[i] == stream) {
1463 stream_status = &context->stream_status[i];
1464 break;
1465 }
1466
1467 if (stream_status == NULL) {
1468 dm_error("Existing stream %p not found!\n", stream);
1469 return false;
1470 }
1471
1472 old_plane_count = stream_status->plane_count;
1473
1474 for (i = 0; i < old_plane_count; i++)
1475 del_planes[i] = stream_status->plane_states[i];
1476
1477 for (i = 0; i < old_plane_count; i++)
1478 if (!dc_remove_plane_from_context(dc, stream, del_planes[i], context))
1479 return false;
1480
1481 return true;
1482}
1483
1484static bool add_all_planes_for_stream(
1485 const struct dc *dc,
1486 struct dc_stream_state *stream,
1487 const struct dc_validation_set set[],
1488 int set_count,
608ac7bb 1489 struct dc_state *context)
19f89e23
AG
1490{
1491 int i, j;
1492
1493 for (i = 0; i < set_count; i++)
1494 if (set[i].stream == stream)
1495 break;
1496
1497 if (i == set_count) {
1498 dm_error("Stream %p not found in set!\n", stream);
1499 return false;
1500 }
4562236b 1501
19f89e23
AG
1502 for (j = 0; j < set[i].plane_count; j++)
1503 if (!dc_add_plane_to_context(dc, stream, set[i].plane_states[j], context))
1504 return false;
4562236b
HW
1505
1506 return true;
1507}
1508
19f89e23
AG
1509bool dc_add_all_planes_for_stream(
1510 const struct dc *dc,
1511 struct dc_stream_state *stream,
1512 struct dc_plane_state * const *plane_states,
1513 int plane_count,
608ac7bb 1514 struct dc_state *context)
19f89e23
AG
1515{
1516 struct dc_validation_set set;
1517 int i;
1518
1519 set.stream = stream;
1520 set.plane_count = plane_count;
1521
1522 for (i = 0; i < plane_count; i++)
1523 set.plane_states[i] = plane_states[i];
1524
1525 return add_all_planes_for_stream(dc, stream, &set, 1, context);
1526}
1527
1528
6b622181
JP
1529static bool is_hdr_static_meta_changed(struct dc_stream_state *cur_stream,
1530 struct dc_stream_state *new_stream)
1531{
1532 if (cur_stream == NULL)
1533 return true;
1534
1535 if (memcmp(&cur_stream->hdr_static_metadata,
1536 &new_stream->hdr_static_metadata,
1537 sizeof(struct dc_info_packet)) != 0)
1538 return true;
1539
1540 return false;
1541}
4562236b 1542
1336926f
A
1543static bool is_vsc_info_packet_changed(struct dc_stream_state *cur_stream,
1544 struct dc_stream_state *new_stream)
1545{
1546 if (cur_stream == NULL)
1547 return true;
1548
1549 if (memcmp(&cur_stream->vsc_infopacket,
1550 &new_stream->vsc_infopacket,
1551 sizeof(struct dc_info_packet)) != 0)
1552 return true;
1553
1554 return false;
1555}
1556
0971c40e
HW
1557static bool is_timing_changed(struct dc_stream_state *cur_stream,
1558 struct dc_stream_state *new_stream)
4562236b
HW
1559{
1560 if (cur_stream == NULL)
1561 return true;
1562
1563 /* If sink pointer changed, it means this is a hotplug, we should do
1564 * full hw setting.
1565 */
1566 if (cur_stream->sink != new_stream->sink)
1567 return true;
1568
1569 /* If output color space is changed, need to reprogram info frames */
4fa086b9 1570 if (cur_stream->output_color_space != new_stream->output_color_space)
4562236b
HW
1571 return true;
1572
1573 return memcmp(
4fa086b9
LSL
1574 &cur_stream->timing,
1575 &new_stream->timing,
4562236b
HW
1576 sizeof(struct dc_crtc_timing)) != 0;
1577}
1578
1579static bool are_stream_backends_same(
0971c40e 1580 struct dc_stream_state *stream_a, struct dc_stream_state *stream_b)
4562236b
HW
1581{
1582 if (stream_a == stream_b)
1583 return true;
1584
1585 if (stream_a == NULL || stream_b == NULL)
1586 return false;
1587
1588 if (is_timing_changed(stream_a, stream_b))
1589 return false;
1590
6b622181
JP
1591 if (is_hdr_static_meta_changed(stream_a, stream_b))
1592 return false;
1593
1e7e86c4
ST
1594 if (stream_a->dpms_off != stream_b->dpms_off)
1595 return false;
1596
1336926f
A
1597 if (is_vsc_info_packet_changed(stream_a, stream_b))
1598 return false;
1599
4562236b
HW
1600 return true;
1601}
1602
2119aa17
DF
1603/**
1604 * dc_is_stream_unchanged() - Compare two stream states for equivalence.
1605 *
1606 * Checks if there a difference between the two states
1607 * that would require a mode change.
1608 *
1609 * Does not compare cursor position or attributes.
1610 */
d54d29db 1611bool dc_is_stream_unchanged(
0971c40e 1612 struct dc_stream_state *old_stream, struct dc_stream_state *stream)
4562236b 1613{
4562236b 1614
ab2541b6
AC
1615 if (!are_stream_backends_same(old_stream, stream))
1616 return false;
4562236b 1617
0460f9ab
JL
1618 if (old_stream->ignore_msa_timing_param != stream->ignore_msa_timing_param)
1619 return false;
1620
4562236b
HW
1621 return true;
1622}
1623
2119aa17
DF
1624/**
1625 * dc_is_stream_scaling_unchanged() - Compare scaling rectangles of two streams.
1626 */
9a5d9c48
LSL
1627bool dc_is_stream_scaling_unchanged(
1628 struct dc_stream_state *old_stream, struct dc_stream_state *stream)
1629{
1630 if (old_stream == stream)
1631 return true;
1632
1633 if (old_stream == NULL || stream == NULL)
1634 return false;
1635
1636 if (memcmp(&old_stream->src,
1637 &stream->src,
1638 sizeof(struct rect)) != 0)
1639 return false;
1640
1641 if (memcmp(&old_stream->dst,
1642 &stream->dst,
1643 sizeof(struct rect)) != 0)
1644 return false;
1645
1646 return true;
1647}
1648
1dc90497 1649static void update_stream_engine_usage(
4562236b 1650 struct resource_context *res_ctx,
a2b8659d 1651 const struct resource_pool *pool,
1dc90497
AG
1652 struct stream_encoder *stream_enc,
1653 bool acquired)
4562236b
HW
1654{
1655 int i;
1656
a2b8659d
TC
1657 for (i = 0; i < pool->stream_enc_count; i++) {
1658 if (pool->stream_enc[i] == stream_enc)
1dc90497 1659 res_ctx->is_stream_enc_acquired[i] = acquired;
4562236b
HW
1660 }
1661}
1662
1663/* TODO: release audio object */
4176664b 1664void update_audio_usage(
4562236b 1665 struct resource_context *res_ctx,
a2b8659d 1666 const struct resource_pool *pool,
1dc90497
AG
1667 struct audio *audio,
1668 bool acquired)
4562236b
HW
1669{
1670 int i;
a2b8659d
TC
1671 for (i = 0; i < pool->audio_count; i++) {
1672 if (pool->audios[i] == audio)
1dc90497 1673 res_ctx->is_audio_acquired[i] = acquired;
4562236b
HW
1674 }
1675}
1676
1677static int acquire_first_free_pipe(
1678 struct resource_context *res_ctx,
a2b8659d 1679 const struct resource_pool *pool,
0971c40e 1680 struct dc_stream_state *stream)
4562236b
HW
1681{
1682 int i;
1683
a2b8659d 1684 for (i = 0; i < pool->pipe_count; i++) {
4562236b
HW
1685 if (!res_ctx->pipe_ctx[i].stream) {
1686 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
1687
6b670fa9 1688 pipe_ctx->stream_res.tg = pool->timing_generators[i];
86a66c4e 1689 pipe_ctx->plane_res.mi = pool->mis[i];
8feabd03 1690 pipe_ctx->plane_res.hubp = pool->hubps[i];
86a66c4e
HW
1691 pipe_ctx->plane_res.ipp = pool->ipps[i];
1692 pipe_ctx->plane_res.xfm = pool->transforms[i];
d94585a0 1693 pipe_ctx->plane_res.dpp = pool->dpps[i];
a6a6cb34 1694 pipe_ctx->stream_res.opp = pool->opps[i];
bc373a89
RL
1695 if (pool->dpps[i])
1696 pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst;
4562236b
HW
1697 pipe_ctx->pipe_idx = i;
1698
ff5ef992 1699
4562236b
HW
1700 pipe_ctx->stream = stream;
1701 return i;
1702 }
1703 }
1704 return -1;
1705}
1706
a2b8659d
TC
1707static struct audio *find_first_free_audio(
1708 struct resource_context *res_ctx,
cfb071f7 1709 const struct resource_pool *pool,
f24b0522
PH
1710 enum engine_id id,
1711 enum dce_version dc_version)
4562236b 1712{
b5a41620
CL
1713 int i, available_audio_count;
1714
1715 available_audio_count = pool->audio_count;
1716
1717 for (i = 0; i < available_audio_count; i++) {
66bfd4fd 1718 if ((res_ctx->is_audio_acquired[i] == false) && (res_ctx->is_stream_enc_acquired[i] == true)) {
cfb071f7
CL
1719 /*we have enough audio endpoint, find the matching inst*/
1720 if (id != i)
1721 continue;
66bfd4fd 1722 return pool->audios[i];
4562236b 1723 }
66bfd4fd 1724 }
5feb9f07 1725
b5a41620
CL
1726 /* use engine id to find free audio */
1727 if ((id < available_audio_count) && (res_ctx->is_audio_acquired[id] == false)) {
5feb9f07
TM
1728 return pool->audios[id];
1729 }
66bfd4fd 1730 /*not found the matching one, first come first serve*/
b5a41620 1731 for (i = 0; i < available_audio_count; i++) {
66bfd4fd
CL
1732 if (res_ctx->is_audio_acquired[i] == false) {
1733 return pool->audios[i];
4176664b
CL
1734 }
1735 }
4562236b
HW
1736 return 0;
1737}
1738
4562236b 1739bool resource_is_stream_unchanged(
608ac7bb 1740 struct dc_state *old_context, struct dc_stream_state *stream)
4562236b 1741{
ab2541b6 1742 int i;
4562236b 1743
ab2541b6 1744 for (i = 0; i < old_context->stream_count; i++) {
0971c40e 1745 struct dc_stream_state *old_stream = old_context->streams[i];
4562236b 1746
ab2541b6 1747 if (are_stream_backends_same(old_stream, stream))
4562236b 1748 return true;
4562236b
HW
1749 }
1750
1751 return false;
1752}
1753
2119aa17
DF
1754/**
1755 * dc_add_stream_to_ctx() - Add a new dc_stream_state to a dc_state.
1756 */
13ab1b44 1757enum dc_status dc_add_stream_to_ctx(
1dc90497 1758 struct dc *dc,
608ac7bb 1759 struct dc_state *new_ctx,
1dc90497
AG
1760 struct dc_stream_state *stream)
1761{
1dc90497 1762 enum dc_status res;
eb9714a2 1763 DC_LOGGER_INIT(dc->ctx->logger);
1dc90497 1764
ece4147f 1765 if (new_ctx->stream_count >= dc->res_pool->timing_generator_count) {
eb9714a2 1766 DC_LOG_WARNING("Max streams reached, can't add stream %p !\n", stream);
1dc90497
AG
1767 return DC_ERROR_UNEXPECTED;
1768 }
1769
1770 new_ctx->streams[new_ctx->stream_count] = stream;
1771 dc_stream_retain(stream);
1772 new_ctx->stream_count++;
1773
1774 res = dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream);
1775 if (res != DC_OK)
eb9714a2 1776 DC_LOG_WARNING("Adding stream %p to context failed with err %d!\n", stream, res);
1dc90497 1777
13ab1b44 1778 return res;
1dc90497
AG
1779}
1780
2119aa17
DF
1781/**
1782 * dc_remove_stream_from_ctx() - Remove a stream from a dc_state.
1783 */
62c933f9 1784enum dc_status dc_remove_stream_from_ctx(
1dc90497 1785 struct dc *dc,
608ac7bb 1786 struct dc_state *new_ctx,
1dc90497
AG
1787 struct dc_stream_state *stream)
1788{
19f89e23 1789 int i;
1dc90497 1790 struct dc_context *dc_ctx = dc->ctx;
22498036
DL
1791 struct pipe_ctx *del_pipe = resource_get_head_pipe_for_stream(&new_ctx->res_ctx, stream);
1792 struct pipe_ctx *odm_pipe;
1dc90497
AG
1793
1794 if (!del_pipe) {
1795 DC_ERROR("Pipe not found for stream %p !\n", stream);
1796 return DC_ERROR_UNEXPECTED;
1797 }
1798
22498036
DL
1799 odm_pipe = del_pipe->next_odm_pipe;
1800
1801 /* Release primary pipe */
1802 ASSERT(del_pipe->stream_res.stream_enc);
1803 update_stream_engine_usage(
1804 &new_ctx->res_ctx,
1805 dc->res_pool,
1806 del_pipe->stream_res.stream_enc,
1807 false);
1808
1809 if (del_pipe->stream_res.audio)
1810 update_audio_usage(
1811 &new_ctx->res_ctx,
1812 dc->res_pool,
1813 del_pipe->stream_res.audio,
1814 false);
1815
1816 resource_unreference_clock_source(&new_ctx->res_ctx,
1817 dc->res_pool,
1818 del_pipe->clock_source);
1819
1820 if (dc->res_pool->funcs->remove_stream_from_ctx)
1821 dc->res_pool->funcs->remove_stream_from_ctx(dc, new_ctx, stream);
1822
1823 while (odm_pipe) {
1824 struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe;
1825
1826 memset(odm_pipe, 0, sizeof(*odm_pipe));
1827 odm_pipe = next_odm_pipe;
1828 }
1829 memset(del_pipe, 0, sizeof(*del_pipe));
1830
1dc90497
AG
1831 for (i = 0; i < new_ctx->stream_count; i++)
1832 if (new_ctx->streams[i] == stream)
1833 break;
1834
1835 if (new_ctx->streams[i] != stream) {
1836 DC_ERROR("Context doesn't have stream %p !\n", stream);
1837 return DC_ERROR_UNEXPECTED;
1838 }
1839
1840 dc_stream_release(new_ctx->streams[i]);
1841 new_ctx->stream_count--;
1842
1dc90497
AG
1843 /* Trim back arrays */
1844 for (; i < new_ctx->stream_count; i++) {
1845 new_ctx->streams[i] = new_ctx->streams[i + 1];
1846 new_ctx->stream_status[i] = new_ctx->stream_status[i + 1];
1847 }
1848
1849 new_ctx->streams[new_ctx->stream_count] = NULL;
1850 memset(
1851 &new_ctx->stream_status[new_ctx->stream_count],
1852 0,
1853 sizeof(new_ctx->stream_status[0]));
1854
1855 return DC_OK;
1856}
1857
0971c40e
HW
1858static struct dc_stream_state *find_pll_sharable_stream(
1859 struct dc_stream_state *stream_needs_pll,
608ac7bb 1860 struct dc_state *context)
4562236b 1861{
ab2541b6 1862 int i;
4562236b 1863
ab2541b6 1864 for (i = 0; i < context->stream_count; i++) {
0971c40e 1865 struct dc_stream_state *stream_has_pll = context->streams[i];
4562236b 1866
ab2541b6
AC
1867 /* We are looking for non dp, non virtual stream */
1868 if (resource_are_streams_timing_synchronizable(
1869 stream_needs_pll, stream_has_pll)
1870 && !dc_is_dp_signal(stream_has_pll->signal)
ceb3dbb4 1871 && stream_has_pll->link->connector_signal
ab2541b6
AC
1872 != SIGNAL_TYPE_VIRTUAL)
1873 return stream_has_pll;
4562236b 1874
4562236b
HW
1875 }
1876
1877 return NULL;
1878}
1879
1880static int get_norm_pix_clk(const struct dc_crtc_timing *timing)
1881{
380604e2 1882 uint32_t pix_clk = timing->pix_clk_100hz;
4562236b
HW
1883 uint32_t normalized_pix_clk = pix_clk;
1884
1885 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
1886 pix_clk /= 2;
cc4d99b8
CL
1887 if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) {
1888 switch (timing->display_color_depth) {
8897810a 1889 case COLOR_DEPTH_666:
cc4d99b8
CL
1890 case COLOR_DEPTH_888:
1891 normalized_pix_clk = pix_clk;
1892 break;
1893 case COLOR_DEPTH_101010:
1894 normalized_pix_clk = (pix_clk * 30) / 24;
1895 break;
1896 case COLOR_DEPTH_121212:
1897 normalized_pix_clk = (pix_clk * 36) / 24;
4562236b 1898 break;
cc4d99b8
CL
1899 case COLOR_DEPTH_161616:
1900 normalized_pix_clk = (pix_clk * 48) / 24;
4562236b 1901 break;
cc4d99b8
CL
1902 default:
1903 ASSERT(0);
4562236b 1904 break;
cc4d99b8 1905 }
4562236b 1906 }
4562236b
HW
1907 return normalized_pix_clk;
1908}
1909
0971c40e 1910static void calculate_phy_pix_clks(struct dc_stream_state *stream)
4562236b 1911{
9345d987
AG
1912 /* update actual pixel clock on all streams */
1913 if (dc_is_hdmi_signal(stream->signal))
1914 stream->phy_pix_clk = get_norm_pix_clk(
380604e2 1915 &stream->timing) / 10;
9345d987
AG
1916 else
1917 stream->phy_pix_clk =
380604e2 1918 stream->timing.pix_clk_100hz / 10;
39c03e00
CL
1919
1920 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1921 stream->phy_pix_clk *= 2;
4562236b
HW
1922}
1923
d2d7885f
AK
1924static int acquire_resource_from_hw_enabled_state(
1925 struct resource_context *res_ctx,
1926 const struct resource_pool *pool,
1927 struct dc_stream_state *stream)
1928{
1929 struct dc_link *link = stream->link;
08b66279 1930 unsigned int i, inst, tg_inst = 0;
d2d7885f
AK
1931
1932 /* Check for enabled DIG to identify enabled display */
1933 if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
1934 return -1;
1935
5ec43eda 1936 inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
d2d7885f 1937
7f7652ee 1938 if (inst == ENGINE_ID_UNKNOWN)
75441d9d 1939 return -1;
d2d7885f 1940
7f7652ee
ML
1941 for (i = 0; i < pool->stream_enc_count; i++) {
1942 if (pool->stream_enc[i]->id == inst) {
1943 tg_inst = pool->stream_enc[i]->funcs->dig_source_otg(
1944 pool->stream_enc[i]);
1945 break;
1946 }
1947 }
5ec43eda 1948
7f7652ee
ML
1949 // tg_inst not found
1950 if (i == pool->stream_enc_count)
75441d9d 1951 return -1;
5ec43eda
ML
1952
1953 if (tg_inst >= pool->timing_generator_count)
75441d9d 1954 return -1;
5ec43eda
ML
1955
1956 if (!res_ctx->pipe_ctx[tg_inst].stream) {
1957 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[tg_inst];
1958
1959 pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];
1960 pipe_ctx->plane_res.mi = pool->mis[tg_inst];
1961 pipe_ctx->plane_res.hubp = pool->hubps[tg_inst];
1962 pipe_ctx->plane_res.ipp = pool->ipps[tg_inst];
1963 pipe_ctx->plane_res.xfm = pool->transforms[tg_inst];
1964 pipe_ctx->plane_res.dpp = pool->dpps[tg_inst];
1965 pipe_ctx->stream_res.opp = pool->opps[tg_inst];
d2d7885f 1966
ccce745c 1967 if (pool->dpps[tg_inst]) {
5ec43eda 1968 pipe_ctx->plane_res.mpcc_inst = pool->dpps[tg_inst]->inst;
ccce745c
ML
1969
1970 // Read DPP->MPCC->OPP Pipe from HW State
1971 if (pool->mpc->funcs->read_mpcc_state) {
1972 struct mpcc_state s = {0};
1973
1974 pool->mpc->funcs->read_mpcc_state(pool->mpc, pipe_ctx->plane_res.mpcc_inst, &s);
1975
1976 if (s.dpp_id < MAX_MPCC)
1977 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].dpp_id = s.dpp_id;
1978
1979 if (s.bot_mpcc_id < MAX_MPCC)
1980 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].mpcc_bot =
1981 &pool->mpc->mpcc_array[s.bot_mpcc_id];
1982
1983 if (s.opp_id < MAX_OPP)
1984 pipe_ctx->stream_res.opp->mpc_tree_params.opp_id = s.opp_id;
1985 }
1986 }
5ec43eda 1987 pipe_ctx->pipe_idx = tg_inst;
d2d7885f
AK
1988
1989 pipe_ctx->stream = stream;
5ec43eda 1990 return tg_inst;
d2d7885f
AK
1991 }
1992
1993 return -1;
1994}
1995
4562236b 1996enum dc_status resource_map_pool_resources(
fb3466a4 1997 const struct dc *dc,
608ac7bb 1998 struct dc_state *context,
1dc90497 1999 struct dc_stream_state *stream)
4562236b 2000{
a2b8659d 2001 const struct resource_pool *pool = dc->res_pool;
1dc90497
AG
2002 int i;
2003 struct dc_context *dc_ctx = dc->ctx;
2004 struct pipe_ctx *pipe_ctx = NULL;
2005 int pipe_idx = -1;
46570f09 2006 struct dc_bios *dcb = dc->ctx->dc_bios;
4562236b 2007
1dc90497
AG
2008 /* TODO Check if this is needed */
2009 /*if (!resource_is_stream_unchanged(old_context, stream)) {
430ef426 2010 if (stream != NULL && old_context->streams[i] != NULL) {
4b679bc3 2011 stream->bit_depth_params =
430ef426
DL
2012 old_context->streams[i]->bit_depth_params;
2013 stream->clamping = old_context->streams[i]->clamping;
a2b8659d
TC
2014 continue;
2015 }
4b679bc3 2016 }
1dc90497 2017 */
7e2fe319 2018
08e1c28d
YMM
2019 calculate_phy_pix_clks(stream);
2020
46570f09
AK
2021 /* TODO: Check Linux */
2022 if (dc->config.allow_seamless_boot_optimization &&
2023 !dcb->funcs->is_accelerated_mode(dcb)) {
2024 if (dc_validate_seamless_boot_timing(dc, stream->sink, &stream->timing))
2025 stream->apply_seamless_boot_optimization = true;
2026 }
2027
d2d7885f
AK
2028 if (stream->apply_seamless_boot_optimization)
2029 pipe_idx = acquire_resource_from_hw_enabled_state(
2030 &context->res_ctx,
2031 pool,
2032 stream);
2033
2034 if (pipe_idx < 0)
2035 /* acquire new resources */
2036 pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream);
8c737fcc 2037
b86a1aa3 2038#ifdef CONFIG_DRM_AMD_DC_DCN
1dc90497 2039 if (pipe_idx < 0)
13ab1b44 2040 pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
94c6d735 2041#endif
13ab1b44 2042
c5b38aec 2043 if (pipe_idx < 0 || context->res_ctx.pipe_ctx[pipe_idx].stream_res.tg == NULL)
1dc90497
AG
2044 return DC_NO_CONTROLLER_RESOURCE;
2045
2046 pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
2047
2048 pipe_ctx->stream_res.stream_enc =
78cc70b1 2049 dc->res_pool->funcs->find_first_free_match_stream_enc_for_link(
1dc90497
AG
2050 &context->res_ctx, pool, stream);
2051
2052 if (!pipe_ctx->stream_res.stream_enc)
38684e46 2053 return DC_NO_STREAM_ENC_RESOURCE;
1dc90497
AG
2054
2055 update_stream_engine_usage(
2056 &context->res_ctx, pool,
2057 pipe_ctx->stream_res.stream_enc,
2058 true);
2059
2060 /* TODO: Add check if ASIC support and EDID audio */
ceb3dbb4 2061 if (!stream->converter_disable_audio &&
1dc90497 2062 dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&
ce08aad3 2063 stream->audio_info.mode_count && stream->audio_info.flags.all) {
1dc90497 2064 pipe_ctx->stream_res.audio = find_first_free_audio(
f24b0522 2065 &context->res_ctx, pool, pipe_ctx->stream_res.stream_enc->id, dc_ctx->dce_version);
1dc90497
AG
2066
2067 /*
2068 * Audio assigned in order first come first get.
2069 * There are asics which has number of audio
2070 * resources less then number of pipes
2071 */
2072 if (pipe_ctx->stream_res.audio)
2073 update_audio_usage(&context->res_ctx, pool,
2074 pipe_ctx->stream_res.audio, true);
2075 }
268cadbd 2076
9aef1a31
S
2077 /* Add ABM to the resource if on EDP */
2078 if (pipe_ctx->stream && dc_is_embedded_signal(pipe_ctx->stream->signal))
2079 pipe_ctx->stream_res.abm = pool->abm;
2080
1dc90497
AG
2081 for (i = 0; i < context->stream_count; i++)
2082 if (context->streams[i] == stream) {
2083 context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst;
3f0940f8 2084 context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.stream_enc->stream_enc_inst;
5fdb7c4c
NK
2085 context->stream_status[i].audio_inst =
2086 pipe_ctx->stream_res.audio ? pipe_ctx->stream_res.audio->inst : -1;
2087
1dc90497
AG
2088 return DC_OK;
2089 }
4562236b 2090
1dc90497
AG
2091 DC_ERROR("Stream %p not found in new ctx!\n", stream);
2092 return DC_ERROR_UNEXPECTED;
2093}
4562236b 2094
2119aa17
DF
2095/**
2096 * dc_resource_state_copy_construct_current() - Creates a new dc_state from existing state
2097 * Is a shallow copy. Increments refcounts on existing streams and planes.
2098 * @dc: copy out of dc->current_state
2099 * @dst_ctx: copy into this
2100 */
f36cc577 2101void dc_resource_state_copy_construct_current(
1dc90497 2102 const struct dc *dc,
608ac7bb 2103 struct dc_state *dst_ctx)
1dc90497 2104{
f36cc577 2105 dc_resource_state_copy_construct(dc->current_state, dst_ctx);
1dc90497
AG
2106}
2107
ab8db3e1
AG
2108
2109void dc_resource_state_construct(
2110 const struct dc *dc,
2111 struct dc_state *dst_ctx)
2112{
dc88b4a6 2113 dst_ctx->clk_mgr = dc->clk_mgr;
ab8db3e1
AG
2114}
2115
6d822156
NC
2116
2117bool dc_resource_is_dsc_encoding_supported(const struct dc *dc)
2118{
2119 return dc->res_pool->res_cap->num_dsc > 0;
2120}
2121
2122
2119aa17
DF
2123/**
2124 * dc_validate_global_state() - Determine if HW can support a given state
2125 * Checks HW resource availability and bandwidth requirement.
2126 * @dc: dc struct for this driver
2127 * @new_ctx: state to be validated
afcd526b 2128 * @fast_validate: set to true if only yes/no to support matters
2119aa17
DF
2129 *
2130 * Return: DC_OK if the result can be programmed. Otherwise, an error code.
2131 */
e750d56d 2132enum dc_status dc_validate_global_state(
1dc90497 2133 struct dc *dc,
afcd526b
JA
2134 struct dc_state *new_ctx,
2135 bool fast_validate)
4562236b 2136{
1dc90497 2137 enum dc_status result = DC_ERROR_UNEXPECTED;
1dc90497 2138 int i, j;
4562236b 2139
e41ab030
HW
2140 if (!new_ctx)
2141 return DC_ERROR_UNEXPECTED;
2142
d596e5d0 2143 if (dc->res_pool->funcs->validate_global) {
ada8ce15
HW
2144 result = dc->res_pool->funcs->validate_global(dc, new_ctx);
2145 if (result != DC_OK)
2146 return result;
d596e5d0 2147 }
4562236b 2148
e41ab030 2149 for (i = 0; i < new_ctx->stream_count; i++) {
1dc90497
AG
2150 struct dc_stream_state *stream = new_ctx->streams[i];
2151
2152 for (j = 0; j < dc->res_pool->pipe_count; j++) {
2153 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[j];
2154
2155 if (pipe_ctx->stream != stream)
2156 continue;
2157
74eac5f3
SSC
2158 if (dc->res_pool->funcs->get_default_swizzle_mode &&
2159 pipe_ctx->plane_state &&
2160 pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) {
2161 result = dc->res_pool->funcs->get_default_swizzle_mode(pipe_ctx->plane_state);
2162 if (result != DC_OK)
2163 return result;
2164 }
2165
1dc90497
AG
2166 /* Switch to dp clock source only if there is
2167 * no non dp stream that shares the same timing
2168 * with the dp stream.
2169 */
2170 if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
2171 !find_pll_sharable_stream(stream, new_ctx)) {
2172
9d0dcecd 2173 resource_unreference_clock_source(
1dc90497
AG
2174 &new_ctx->res_ctx,
2175 dc->res_pool,
9d0dcecd 2176 pipe_ctx->clock_source);
4a629536 2177
1dc90497
AG
2178 pipe_ctx->clock_source = dc->res_pool->dp_clock_source;
2179 resource_reference_clock_source(
2180 &new_ctx->res_ctx,
2181 dc->res_pool,
2182 pipe_ctx->clock_source);
2183 }
2184 }
2185 }
2186
1dc90497
AG
2187 result = resource_build_scaling_params_for_context(dc, new_ctx);
2188
2189 if (result == DC_OK)
afcd526b 2190 if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx, fast_validate))
1dc90497
AG
2191 result = DC_FAIL_BANDWIDTH_VALIDATE;
2192
2193 return result;
4562236b
HW
2194}
2195
6e4d6bee 2196static void patch_gamut_packet_checksum(
e09b6473 2197 struct dc_info_packet *gamut_packet)
4562236b 2198{
4562236b 2199 /* For gamut we recalc checksum */
6e4d6bee 2200 if (gamut_packet->valid) {
4562236b
HW
2201 uint8_t chk_sum = 0;
2202 uint8_t *ptr;
2203 uint8_t i;
2204
4562236b 2205 /*start of the Gamut data. */
6e4d6bee 2206 ptr = &gamut_packet->sb[3];
4562236b 2207
6e4d6bee 2208 for (i = 0; i <= gamut_packet->sb[1]; i++)
4562236b
HW
2209 chk_sum += ptr[i];
2210
6e4d6bee 2211 gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum);
1646a6fe 2212 }
4562236b
HW
2213}
2214
2215static void set_avi_info_frame(
e09b6473 2216 struct dc_info_packet *info_packet,
4562236b
HW
2217 struct pipe_ctx *pipe_ctx)
2218{
0971c40e 2219 struct dc_stream_state *stream = pipe_ctx->stream;
4562236b 2220 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
4562236b
HW
2221 uint32_t pixel_encoding = 0;
2222 enum scanning_type scan_type = SCANNING_TYPE_NODATA;
2223 enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA;
2224 bool itc = false;
50e27654 2225 uint8_t itc_value = 0;
4562236b 2226 uint8_t cn0_cn1 = 0;
50e27654 2227 unsigned int cn0_cn1_value = 0;
4562236b
HW
2228 uint8_t *check_sum = NULL;
2229 uint8_t byte_index = 0;
754e3673 2230 union hdmi_info_packet hdmi_info;
50e27654 2231 union display_content_support support = {0};
4fa086b9 2232 unsigned int vic = pipe_ctx->stream->timing.vic;
15e17335 2233 enum dc_timing_3d_format format;
4562236b 2234
754e3673
AK
2235 memset(&hdmi_info, 0, sizeof(union hdmi_info_packet));
2236
4fa086b9 2237 color_space = pipe_ctx->stream->output_color_space;
e5f2038e 2238 if (color_space == COLOR_SPACE_UNKNOWN)
4fa086b9 2239 color_space = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ?
e5f2038e 2240 COLOR_SPACE_SRGB:COLOR_SPACE_YCBCR709;
4562236b
HW
2241
2242 /* Initialize header */
e09b6473 2243 hdmi_info.bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI;
4562236b
HW
2244 /* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall
2245 * not be used in HDMI 2.0 (Section 10.1) */
e09b6473
AK
2246 hdmi_info.bits.header.version = 2;
2247 hdmi_info.bits.header.length = HDMI_AVI_INFOFRAME_SIZE;
4562236b
HW
2248
2249 /*
2250 * IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built
2251 * according to HDMI 2.0 spec (Section 10.1)
2252 */
2253
4fa086b9 2254 switch (stream->timing.pixel_encoding) {
4562236b
HW
2255 case PIXEL_ENCODING_YCBCR422:
2256 pixel_encoding = 1;
2257 break;
2258
2259 case PIXEL_ENCODING_YCBCR444:
2260 pixel_encoding = 2;
2261 break;
2262 case PIXEL_ENCODING_YCBCR420:
2263 pixel_encoding = 3;
2264 break;
2265
2266 case PIXEL_ENCODING_RGB:
2267 default:
2268 pixel_encoding = 0;
2269 }
2270
2271 /* Y0_Y1_Y2 : The pixel encoding */
2272 /* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */
e09b6473 2273 hdmi_info.bits.Y0_Y1_Y2 = pixel_encoding;
4562236b
HW
2274
2275 /* A0 = 1 Active Format Information valid */
e09b6473 2276 hdmi_info.bits.A0 = ACTIVE_FORMAT_VALID;
4562236b
HW
2277
2278 /* B0, B1 = 3; Bar info data is valid */
e09b6473 2279 hdmi_info.bits.B0_B1 = BAR_INFO_BOTH_VALID;
4562236b 2280
e09b6473 2281 hdmi_info.bits.SC0_SC1 = PICTURE_SCALING_UNIFORM;
4562236b
HW
2282
2283 /* S0, S1 : Underscan / Overscan */
2284 /* TODO: un-hardcode scan type */
2285 scan_type = SCANNING_TYPE_UNDERSCAN;
e09b6473 2286 hdmi_info.bits.S0_S1 = scan_type;
4562236b
HW
2287
2288 /* C0, C1 : Colorimetry */
8fde5884 2289 if (color_space == COLOR_SPACE_YCBCR709 ||
15e17335 2290 color_space == COLOR_SPACE_YCBCR709_LIMITED)
e09b6473 2291 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU709;
8fde5884
CL
2292 else if (color_space == COLOR_SPACE_YCBCR601 ||
2293 color_space == COLOR_SPACE_YCBCR601_LIMITED)
e09b6473 2294 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU601;
8fde5884 2295 else {
e09b6473 2296 hdmi_info.bits.C0_C1 = COLORIMETRY_NO_DATA;
8fde5884 2297 }
534db198 2298 if (color_space == COLOR_SPACE_2020_RGB_FULLRANGE ||
8fde5884
CL
2299 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE ||
2300 color_space == COLOR_SPACE_2020_YCBCR) {
e09b6473
AK
2301 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR;
2302 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
534db198 2303 } else if (color_space == COLOR_SPACE_ADOBERGB) {
e09b6473
AK
2304 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB;
2305 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
534db198
AZ
2306 }
2307
4562236b 2308 /* TODO: un-hardcode aspect ratio */
4fa086b9 2309 aspect = stream->timing.aspect_ratio;
4562236b
HW
2310
2311 switch (aspect) {
2312 case ASPECT_RATIO_4_3:
2313 case ASPECT_RATIO_16_9:
e09b6473 2314 hdmi_info.bits.M0_M1 = aspect;
4562236b
HW
2315 break;
2316
2317 case ASPECT_RATIO_NO_DATA:
2318 case ASPECT_RATIO_64_27:
2319 case ASPECT_RATIO_256_135:
2320 default:
e09b6473 2321 hdmi_info.bits.M0_M1 = 0;
4562236b
HW
2322 }
2323
2324 /* Active Format Aspect ratio - same as Picture Aspect Ratio. */
e09b6473 2325 hdmi_info.bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE;
4562236b
HW
2326
2327 /* TODO: un-hardcode cn0_cn1 and itc */
50e27654 2328
4562236b 2329 cn0_cn1 = 0;
50e27654
ZF
2330 cn0_cn1_value = 0;
2331
2332 itc = true;
2333 itc_value = 1;
2334
ceb3dbb4 2335 support = stream->content_support;
4562236b
HW
2336
2337 if (itc) {
50e27654
ZF
2338 if (!support.bits.valid_content_type) {
2339 cn0_cn1_value = 0;
2340 } else {
2341 if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GRAPHICS) {
2342 if (support.bits.graphics_content == 1) {
2343 cn0_cn1_value = 0;
2344 }
2345 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_PHOTO) {
2346 if (support.bits.photo_content == 1) {
2347 cn0_cn1_value = 1;
2348 } else {
2349 cn0_cn1_value = 0;
2350 itc_value = 0;
2351 }
2352 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_CINEMA) {
2353 if (support.bits.cinema_content == 1) {
2354 cn0_cn1_value = 2;
2355 } else {
2356 cn0_cn1_value = 0;
2357 itc_value = 0;
2358 }
2359 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GAME) {
2360 if (support.bits.game_content == 1) {
2361 cn0_cn1_value = 3;
2362 } else {
2363 cn0_cn1_value = 0;
2364 itc_value = 0;
2365 }
2366 }
2367 }
e09b6473
AK
2368 hdmi_info.bits.CN0_CN1 = cn0_cn1_value;
2369 hdmi_info.bits.ITC = itc_value;
4562236b
HW
2370 }
2371
2372 /* TODO : We should handle YCC quantization */
2373 /* but we do not have matrix calculation */
ceb3dbb4
JL
2374 if (stream->qs_bit == 1 &&
2375 stream->qy_bit == 1) {
50e27654
ZF
2376 if (color_space == COLOR_SPACE_SRGB ||
2377 color_space == COLOR_SPACE_2020_RGB_FULLRANGE) {
e09b6473 2378 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_FULL_RANGE;
993dca3e 2379 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
50e27654
ZF
2380 } else if (color_space == COLOR_SPACE_SRGB_LIMITED ||
2381 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE) {
e09b6473
AK
2382 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_LIMITED_RANGE;
2383 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
50e27654 2384 } else {
e09b6473
AK
2385 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
2386 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
50e27654 2387 }
4562236b 2388 } else {
e09b6473
AK
2389 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
2390 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
4562236b 2391 }
50e27654 2392
15e17335 2393 ///VIC
4fa086b9 2394 format = stream->timing.timing_3d_format;
15e17335
CL
2395 /*todo, add 3DStereo support*/
2396 if (format != TIMING_3D_FORMAT_NONE) {
2397 // Based on HDMI specs hdmi vic needs to be converted to cea vic when 3D is enabled
4fa086b9 2398 switch (pipe_ctx->stream->timing.hdmi_vic) {
15e17335
CL
2399 case 1:
2400 vic = 95;
2401 break;
2402 case 2:
2403 vic = 94;
2404 break;
2405 case 3:
2406 vic = 93;
2407 break;
2408 case 4:
2409 vic = 98;
2410 break;
2411 default:
2412 break;
2413 }
2414 }
efa02336 2415 /* If VIC >= 128, the Source shall use AVI InfoFrame Version 3*/
e09b6473 2416 hdmi_info.bits.VIC0_VIC7 = vic;
efa02336
CP
2417 if (vic >= 128)
2418 hdmi_info.bits.header.version = 3;
2419 /* If (C1, C0)=(1, 1) and (EC2, EC1, EC0)=(1, 1, 1),
2420 * the Source shall use 20 AVI InfoFrame Version 4
2421 */
2422 if (hdmi_info.bits.C0_C1 == COLORIMETRY_EXTENDED &&
2423 hdmi_info.bits.EC0_EC2 == COLORIMETRYEX_RESERVED) {
2424 hdmi_info.bits.header.version = 4;
2425 hdmi_info.bits.header.length = 14;
2426 }
4562236b
HW
2427
2428 /* pixel repetition
2429 * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel
2430 * repetition start from 1 */
e09b6473 2431 hdmi_info.bits.PR0_PR3 = 0;
4562236b
HW
2432
2433 /* Bar Info
2434 * barTop: Line Number of End of Top Bar.
2435 * barBottom: Line Number of Start of Bottom Bar.
2436 * barLeft: Pixel Number of End of Left Bar.
2437 * barRight: Pixel Number of Start of Right Bar. */
e09b6473
AK
2438 hdmi_info.bits.bar_top = stream->timing.v_border_top;
2439 hdmi_info.bits.bar_bottom = (stream->timing.v_total
4fa086b9 2440 - stream->timing.v_border_bottom + 1);
e09b6473
AK
2441 hdmi_info.bits.bar_left = stream->timing.h_border_left;
2442 hdmi_info.bits.bar_right = (stream->timing.h_total
4fa086b9 2443 - stream->timing.h_border_right + 1);
4562236b 2444
2f482c4f
CP
2445 /* Additional Colorimetry Extension
2446 * Used in conduction with C0-C1 and EC0-EC2
2447 * 0 = DCI-P3 RGB (D65)
2448 * 1 = DCI-P3 RGB (theater)
2449 */
2450 hdmi_info.bits.ACE0_ACE3 = 0;
2451
4562236b 2452 /* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */
e09b6473 2453 check_sum = &hdmi_info.packet_raw_data.sb[0];
e8d726b7 2454
efa02336 2455 *check_sum = HDMI_INFOFRAME_TYPE_AVI + hdmi_info.bits.header.length + hdmi_info.bits.header.version;
4562236b 2456
efa02336 2457 for (byte_index = 1; byte_index <= hdmi_info.bits.header.length; byte_index++)
e09b6473 2458 *check_sum += hdmi_info.packet_raw_data.sb[byte_index];
4562236b
HW
2459
2460 /* one byte complement */
2461 *check_sum = (uint8_t) (0x100 - *check_sum);
2462
2463 /* Store in hw_path_mode */
e09b6473
AK
2464 info_packet->hb0 = hdmi_info.packet_raw_data.hb0;
2465 info_packet->hb1 = hdmi_info.packet_raw_data.hb1;
2466 info_packet->hb2 = hdmi_info.packet_raw_data.hb2;
4562236b 2467
e09b6473
AK
2468 for (byte_index = 0; byte_index < sizeof(hdmi_info.packet_raw_data.sb); byte_index++)
2469 info_packet->sb[byte_index] = hdmi_info.packet_raw_data.sb[byte_index];
4562236b
HW
2470
2471 info_packet->valid = true;
2472}
2473
6e4d6bee 2474static void set_vendor_info_packet(
e09b6473 2475 struct dc_info_packet *info_packet,
0971c40e 2476 struct dc_stream_state *stream)
4562236b 2477{
ecd0136b 2478 /* SPD info packet for FreeSync */
4562236b 2479
ecd0136b
HT
2480 /* Check if Freesync is supported. Return if false. If true,
2481 * set the corresponding bit in the info packet
2482 */
2483 if (!stream->vsp_infopacket.valid)
4562236b
HW
2484 return;
2485
ecd0136b 2486 *info_packet = stream->vsp_infopacket;
4562236b
HW
2487}
2488
6e4d6bee 2489static void set_spd_info_packet(
e09b6473 2490 struct dc_info_packet *info_packet,
0971c40e 2491 struct dc_stream_state *stream)
4562236b
HW
2492{
2493 /* SPD info packet for FreeSync */
2494
4562236b
HW
2495 /* Check if Freesync is supported. Return if false. If true,
2496 * set the corresponding bit in the info packet
2497 */
98e6436d 2498 if (!stream->vrr_infopacket.valid)
4562236b
HW
2499 return;
2500
98e6436d 2501 *info_packet = stream->vrr_infopacket;
4562236b
HW
2502}
2503
1646a6fe 2504static void set_hdr_static_info_packet(
e09b6473 2505 struct dc_info_packet *info_packet,
0971c40e 2506 struct dc_stream_state *stream)
1646a6fe 2507{
0eeef690 2508 /* HDR Static Metadata info packet for HDR10 */
1646a6fe 2509
a10dc97a
KK
2510 if (!stream->hdr_static_metadata.valid ||
2511 stream->use_dynamic_meta)
10bff005
YS
2512 return;
2513
0eeef690 2514 *info_packet = stream->hdr_static_metadata;
1646a6fe
AW
2515}
2516
6e4d6bee 2517static void set_vsc_info_packet(
e09b6473 2518 struct dc_info_packet *info_packet,
0971c40e 2519 struct dc_stream_state *stream)
4562236b 2520{
1336926f 2521 if (!stream->vsc_infopacket.valid)
4562236b
HW
2522 return;
2523
1336926f 2524 *info_packet = stream->vsc_infopacket;
4562236b
HW
2525}
2526
f36cc577 2527void dc_resource_state_destruct(struct dc_state *context)
4562236b
HW
2528{
2529 int i, j;
2530
ab2541b6 2531 for (i = 0; i < context->stream_count; i++) {
3be5262e
HW
2532 for (j = 0; j < context->stream_status[i].plane_count; j++)
2533 dc_plane_state_release(
2534 context->stream_status[i].plane_states[j]);
4562236b 2535
3be5262e 2536 context->stream_status[i].plane_count = 0;
4fa086b9 2537 dc_stream_release(context->streams[i]);
ab2541b6 2538 context->streams[i] = NULL;
4562236b
HW
2539 }
2540}
2541
f36cc577 2542void dc_resource_state_copy_construct(
608ac7bb
JZ
2543 const struct dc_state *src_ctx,
2544 struct dc_state *dst_ctx)
4562236b
HW
2545{
2546 int i, j;
8ee5702a 2547 struct kref refcount = dst_ctx->refcount;
4562236b
HW
2548
2549 *dst_ctx = *src_ctx;
2550
a2b8659d 2551 for (i = 0; i < MAX_PIPES; i++) {
4562236b
HW
2552 struct pipe_ctx *cur_pipe = &dst_ctx->res_ctx.pipe_ctx[i];
2553
2554 if (cur_pipe->top_pipe)
2555 cur_pipe->top_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
2556
2557 if (cur_pipe->bottom_pipe)
2558 cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
b1f6d01c
DL
2559
2560 if (cur_pipe->next_odm_pipe)
2561 cur_pipe->next_odm_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx];
2562
2563 if (cur_pipe->prev_odm_pipe)
2564 cur_pipe->prev_odm_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx];
4562236b
HW
2565 }
2566
ab2541b6 2567 for (i = 0; i < dst_ctx->stream_count; i++) {
4fa086b9 2568 dc_stream_retain(dst_ctx->streams[i]);
3be5262e
HW
2569 for (j = 0; j < dst_ctx->stream_status[i].plane_count; j++)
2570 dc_plane_state_retain(
2571 dst_ctx->stream_status[i].plane_states[j]);
4562236b 2572 }
9a3afbb3
AG
2573
2574 /* context refcount should not be overridden */
8ee5702a 2575 dst_ctx->refcount = refcount;
9a3afbb3 2576
4562236b
HW
2577}
2578
2579struct clock_source *dc_resource_find_first_free_pll(
a2b8659d
TC
2580 struct resource_context *res_ctx,
2581 const struct resource_pool *pool)
4562236b
HW
2582{
2583 int i;
2584
a2b8659d 2585 for (i = 0; i < pool->clk_src_count; ++i) {
4562236b 2586 if (res_ctx->clock_source_ref_count[i] == 0)
a2b8659d 2587 return pool->clock_sources[i];
4562236b
HW
2588 }
2589
2590 return NULL;
2591}
2592
2593void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
2594{
2595 enum signal_type signal = SIGNAL_TYPE_NONE;
96c50c0d 2596 struct encoder_info_frame *info = &pipe_ctx->stream_res.encoder_info_frame;
4562236b
HW
2597
2598 /* default all packets to invalid */
6e4d6bee
TC
2599 info->avi.valid = false;
2600 info->gamut.valid = false;
2601 info->vendor.valid = false;
630e3573 2602 info->spd.valid = false;
6e4d6bee
TC
2603 info->hdrsmd.valid = false;
2604 info->vsc.valid = false;
4562236b
HW
2605
2606 signal = pipe_ctx->stream->signal;
2607
2608 /* HDMi and DP have different info packets*/
2609 if (dc_is_hdmi_signal(signal)) {
6e4d6bee
TC
2610 set_avi_info_frame(&info->avi, pipe_ctx);
2611
2612 set_vendor_info_packet(&info->vendor, pipe_ctx->stream);
2613
2614 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2615
56ef6ed9 2616 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
6e4d6bee 2617
a33fa99d 2618 } else if (dc_is_dp_signal(signal)) {
6e4d6bee
TC
2619 set_vsc_info_packet(&info->vsc, pipe_ctx->stream);
2620
2621 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2622
56ef6ed9 2623 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
a33fa99d 2624 }
4562236b 2625
6e4d6bee 2626 patch_gamut_packet_checksum(&info->gamut);
4562236b
HW
2627}
2628
2629enum dc_status resource_map_clock_resources(
fb3466a4 2630 const struct dc *dc,
608ac7bb 2631 struct dc_state *context,
1dc90497 2632 struct dc_stream_state *stream)
4562236b 2633{
4562236b 2634 /* acquire new resources */
1dc90497
AG
2635 const struct resource_pool *pool = dc->res_pool;
2636 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(
2637 &context->res_ctx, stream);
ab2541b6 2638
1dc90497
AG
2639 if (!pipe_ctx)
2640 return DC_ERROR_UNEXPECTED;
4562236b 2641
1dc90497
AG
2642 if (dc_is_dp_signal(pipe_ctx->stream->signal)
2643 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)
2644 pipe_ctx->clock_source = pool->dp_clock_source;
2645 else {
2646 pipe_ctx->clock_source = NULL;
4562236b 2647
1dc90497 2648 if (!dc->config.disable_disp_pll_sharing)
4ed4e51b 2649 pipe_ctx->clock_source = resource_find_used_clk_src_for_sharing(
1dc90497
AG
2650 &context->res_ctx,
2651 pipe_ctx);
4562236b 2652
1dc90497
AG
2653 if (pipe_ctx->clock_source == NULL)
2654 pipe_ctx->clock_source =
2655 dc_resource_find_first_free_pll(
2656 &context->res_ctx,
2657 pool);
2658 }
4562236b 2659
1dc90497
AG
2660 if (pipe_ctx->clock_source == NULL)
2661 return DC_NO_CLOCK_SOURCE_RESOURCE;
4562236b 2662
1dc90497
AG
2663 resource_reference_clock_source(
2664 &context->res_ctx, pool,
2665 pipe_ctx->clock_source);
4562236b
HW
2666
2667 return DC_OK;
2668}
2669
2670/*
2671 * Note: We need to disable output if clock sources change,
2672 * since bios does optimization and doesn't apply if changing
2673 * PHY when not already disabled.
2674 */
2675bool pipe_need_reprogram(
2676 struct pipe_ctx *pipe_ctx_old,
2677 struct pipe_ctx *pipe_ctx)
2678{
cfe4645e
DL
2679 if (!pipe_ctx_old->stream)
2680 return false;
2681
4562236b
HW
2682 if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink)
2683 return true;
2684
2685 if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal)
2686 return true;
2687
afaacef4 2688 if (pipe_ctx_old->stream_res.audio != pipe_ctx->stream_res.audio)
4562236b
HW
2689 return true;
2690
2691 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source
2692 && pipe_ctx_old->stream != pipe_ctx->stream)
2693 return true;
2694
8e9c4c8c 2695 if (pipe_ctx_old->stream_res.stream_enc != pipe_ctx->stream_res.stream_enc)
4562236b
HW
2696 return true;
2697
2698 if (is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2699 return true;
2700
6b622181
JP
2701 if (is_hdr_static_meta_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2702 return true;
4562236b 2703
1e7e86c4
ST
2704 if (pipe_ctx_old->stream->dpms_off != pipe_ctx->stream->dpms_off)
2705 return true;
2706
1336926f
A
2707 if (is_vsc_info_packet_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2708 return true;
2709
eed928dc
CL
2710 if (false == pipe_ctx_old->stream->link->link_state_valid &&
2711 false == pipe_ctx_old->stream->dpms_off)
2712 return true;
2713
4562236b
HW
2714 return false;
2715}
529cad0f 2716
0971c40e 2717void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream,
529cad0f
DW
2718 struct bit_depth_reduction_params *fmt_bit_depth)
2719{
4fa086b9 2720 enum dc_dither_option option = stream->dither_option;
529cad0f 2721 enum dc_pixel_encoding pixel_encoding =
4fa086b9 2722 stream->timing.pixel_encoding;
529cad0f
DW
2723
2724 memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth));
2725
603767f9
TC
2726 if (option == DITHER_OPTION_DEFAULT) {
2727 switch (stream->timing.display_color_depth) {
2728 case COLOR_DEPTH_666:
2729 option = DITHER_OPTION_SPATIAL6;
2730 break;
2731 case COLOR_DEPTH_888:
2732 option = DITHER_OPTION_SPATIAL8;
2733 break;
2734 case COLOR_DEPTH_101010:
2735 option = DITHER_OPTION_SPATIAL10;
2736 break;
2737 default:
2738 option = DITHER_OPTION_DISABLE;
2739 }
2740 }
2741
529cad0f
DW
2742 if (option == DITHER_OPTION_DISABLE)
2743 return;
2744
2745 if (option == DITHER_OPTION_TRUN6) {
2746 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2747 fmt_bit_depth->flags.TRUNCATE_DEPTH = 0;
2748 } else if (option == DITHER_OPTION_TRUN8 ||
2749 option == DITHER_OPTION_TRUN8_SPATIAL6 ||
2750 option == DITHER_OPTION_TRUN8_FM6) {
2751 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2752 fmt_bit_depth->flags.TRUNCATE_DEPTH = 1;
2753 } else if (option == DITHER_OPTION_TRUN10 ||
2754 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
2755 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
2756 option == DITHER_OPTION_TRUN10_FM8 ||
2757 option == DITHER_OPTION_TRUN10_FM6 ||
2758 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2759 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2760 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2761 }
2762
2763 /* special case - Formatter can only reduce by 4 bits at most.
2764 * When reducing from 12 to 6 bits,
2765 * HW recommends we use trunc with round mode
2766 * (if we did nothing, trunc to 10 bits would be used)
2767 * note that any 12->10 bit reduction is ignored prior to DCE8,
2768 * as the input was 10 bits.
2769 */
2770 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2771 option == DITHER_OPTION_SPATIAL6 ||
2772 option == DITHER_OPTION_FM6) {
2773 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2774 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2775 fmt_bit_depth->flags.TRUNCATE_MODE = 1;
2776 }
2777
2778 /* spatial dither
2779 * note that spatial modes 1-3 are never used
2780 */
2781 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2782 option == DITHER_OPTION_SPATIAL6 ||
2783 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
2784 option == DITHER_OPTION_TRUN8_SPATIAL6) {
2785 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2786 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 0;
2787 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2788 fmt_bit_depth->flags.RGB_RANDOM =
2789 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2790 } else if (option == DITHER_OPTION_SPATIAL8_FRAME_RANDOM ||
2791 option == DITHER_OPTION_SPATIAL8 ||
2792 option == DITHER_OPTION_SPATIAL8_FM6 ||
2793 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
2794 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2795 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2796 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 1;
2797 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2798 fmt_bit_depth->flags.RGB_RANDOM =
2799 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2800 } else if (option == DITHER_OPTION_SPATIAL10_FRAME_RANDOM ||
2801 option == DITHER_OPTION_SPATIAL10 ||
2802 option == DITHER_OPTION_SPATIAL10_FM8 ||
2803 option == DITHER_OPTION_SPATIAL10_FM6) {
2804 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2805 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 2;
2806 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2807 fmt_bit_depth->flags.RGB_RANDOM =
2808 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2809 }
2810
2811 if (option == DITHER_OPTION_SPATIAL6 ||
2812 option == DITHER_OPTION_SPATIAL8 ||
2813 option == DITHER_OPTION_SPATIAL10) {
2814 fmt_bit_depth->flags.FRAME_RANDOM = 0;
2815 } else {
2816 fmt_bit_depth->flags.FRAME_RANDOM = 1;
2817 }
2818
2819 //////////////////////
2820 //// temporal dither
2821 //////////////////////
2822 if (option == DITHER_OPTION_FM6 ||
2823 option == DITHER_OPTION_SPATIAL8_FM6 ||
2824 option == DITHER_OPTION_SPATIAL10_FM6 ||
2825 option == DITHER_OPTION_TRUN10_FM6 ||
2826 option == DITHER_OPTION_TRUN8_FM6 ||
2827 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2828 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2829 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 0;
2830 } else if (option == DITHER_OPTION_FM8 ||
2831 option == DITHER_OPTION_SPATIAL10_FM8 ||
2832 option == DITHER_OPTION_TRUN10_FM8) {
2833 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2834 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 1;
2835 } else if (option == DITHER_OPTION_FM10) {
2836 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2837 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 2;
2838 }
2839
2840 fmt_bit_depth->pixel_encoding = pixel_encoding;
2841}
9345d987 2842
62c933f9 2843enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream)
9345d987 2844{
ceb3dbb4 2845 struct dc_link *link = stream->link;
2b77dcc5 2846 struct timing_generator *tg = dc->res_pool->timing_generators[0];
9345d987
AG
2847 enum dc_status res = DC_OK;
2848
4fa086b9 2849 calculate_phy_pix_clks(stream);
9345d987 2850
4fa086b9 2851 if (!tg->funcs->validate_timing(tg, &stream->timing))
9345d987
AG
2852 res = DC_FAIL_CONTROLLER_VALIDATE;
2853
248cbed6 2854 if (res == DC_OK) {
9345d987 2855 if (!link->link_enc->funcs->validate_output_with_stream(
4fa086b9 2856 link->link_enc, stream))
9345d987 2857 res = DC_FAIL_ENC_VALIDATE;
248cbed6 2858 }
9345d987
AG
2859
2860 /* TODO: validate audio ASIC caps, encoder */
2861
2862 if (res == DC_OK)
4fa086b9 2863 res = dc_link_validate_mode_timing(stream,
9345d987 2864 link,
4fa086b9 2865 &stream->timing);
9345d987 2866
62c933f9 2867 return res;
9345d987 2868}
792671d7 2869
62c933f9 2870enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state)
792671d7 2871{
62c933f9
YS
2872 enum dc_status res = DC_OK;
2873
792671d7 2874 /* TODO For now validates pixel format only */
8e7095b9 2875 if (dc->res_pool->funcs->validate_plane)
62c933f9 2876 return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps);
792671d7 2877
62c933f9 2878 return res;
792671d7 2879}
74eac5f3
SSC
2880
2881unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format)
2882{
2883 switch (format) {
2884 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
2885 return 8;
2886 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
2887 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
2888 return 12;
2889 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
2890 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
2891 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
2892 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
2893 return 16;
2894 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
2895 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
2896 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
2897 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
2898 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
2899 return 32;
2900 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
2901 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
2902 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
2903 return 64;
2904 default:
2905 ASSERT_CRITICAL(false);
2906 return -1;
2907 }
2908}
3ab4cc65
CL
2909static unsigned int get_max_audio_sample_rate(struct audio_mode *modes)
2910{
2911 if (modes) {
2912 if (modes->sample_rates.rate.RATE_192)
2913 return 192000;
2914 if (modes->sample_rates.rate.RATE_176_4)
2915 return 176400;
2916 if (modes->sample_rates.rate.RATE_96)
2917 return 96000;
2918 if (modes->sample_rates.rate.RATE_88_2)
2919 return 88200;
2920 if (modes->sample_rates.rate.RATE_48)
2921 return 48000;
2922 if (modes->sample_rates.rate.RATE_44_1)
2923 return 44100;
2924 if (modes->sample_rates.rate.RATE_32)
2925 return 32000;
2926 }
2927 /*original logic when no audio info*/
2928 return 441000;
2929}
2930
2931void get_audio_check(struct audio_info *aud_modes,
2932 struct audio_check *audio_chk)
2933{
2934 unsigned int i;
2935 unsigned int max_sample_rate = 0;
2936
2937 if (aud_modes) {
2938 audio_chk->audio_packet_type = 0x2;/*audio sample packet AP = .25 for layout0, 1 for layout1*/
2939
2940 audio_chk->max_audiosample_rate = 0;
2941 for (i = 0; i < aud_modes->mode_count; i++) {
2942 max_sample_rate = get_max_audio_sample_rate(&aud_modes->modes[i]);
2943 if (audio_chk->max_audiosample_rate < max_sample_rate)
2944 audio_chk->max_audiosample_rate = max_sample_rate;
2945 /*dts takes the same as type 2: AP = 0.25*/
2946 }
2947 /*check which one take more bandwidth*/
2948 if (audio_chk->max_audiosample_rate > 192000)
2949 audio_chk->audio_packet_type = 0x9;/*AP =1*/
2950 audio_chk->acat = 0;/*not support*/
2951 }
2952}
2953