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drm/amd/display: re-order the luma chroma addres updation
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / display / dc / core / dc_resource.c
CommitLineData
4562236b
HW		 1/*
2* Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25#include "dm_services.h"
26
27#include "resource.h"
28#include "include/irq_service_interface.h"
29#include "link_encoder.h"
30#include "stream_encoder.h"
31#include "opp.h"
32#include "timing_generator.h"
33#include "transform.h"
5ac3d3c9 34#include "core_types.h"
4562236b 35#include "set_mode_types.h"
4562236b
HW		 36#include "virtual/virtual_stream_encoder.h"
37
38#include "dce80/dce80_resource.h"
39#include "dce100/dce100_resource.h"
40#include "dce110/dce110_resource.h"
41#include "dce112/dce112_resource.h"
ff5ef992
AD		 42#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
43#include "dcn10/dcn10_resource.h"
44#endif
2c8ad2d5 45#include "dce120/dce120_resource.h"
4562236b
HW		 46
47enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
48{
49 enum dce_version dc_version = DCE_VERSION_UNKNOWN;
50 switch (asic_id.chip_family) {
51
52 case FAMILY_CI:
53 case FAMILY_KV:
54 dc_version = DCE_VERSION_8_0;
55 break;
56 case FAMILY_CZ:
57 dc_version = DCE_VERSION_11_0;
58 break;
59
60 case FAMILY_VI:
61 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
62 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
63 dc_version = DCE_VERSION_10_0;
64 break;
65 }
66 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
b264d345
JL		 67 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
68 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
4562236b
HW		 69 dc_version = DCE_VERSION_11_2;
70 }
71 break;
2c8ad2d5
AD		 72 case FAMILY_AI:
73 dc_version = DCE_VERSION_12_0;
74 break;
ff5ef992
AD		 75#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
76 case FAMILY_RV:
77 dc_version = DCN_VERSION_1_0;
78 break;
79#endif
4562236b
HW		 80 default:
81 dc_version = DCE_VERSION_UNKNOWN;
82 break;
83 }
84 return dc_version;
85}
86
87struct resource_pool *dc_create_resource_pool(
88 struct core_dc *dc,
89 int num_virtual_links,
90 enum dce_version dc_version,
91 struct hw_asic_id asic_id)
92{
5ac3d3c9 93 struct resource_pool *res_pool = NULL;
4562236b
HW		 94
95 switch (dc_version) {
96 case DCE_VERSION_8_0:
5ac3d3c9 97 res_pool = dce80_create_resource_pool(
4562236b 98 num_virtual_links, dc);
5ac3d3c9 99 break;
4562236b 100 case DCE_VERSION_10_0:
5ac3d3c9 101 res_pool = dce100_create_resource_pool(
4562236b 102 num_virtual_links, dc);
5ac3d3c9 103 break;
4562236b 104 case DCE_VERSION_11_0:
5ac3d3c9 105 res_pool = dce110_create_resource_pool(
4562236b 106 num_virtual_links, dc, asic_id);
5ac3d3c9 107 break;
4562236b 108 case DCE_VERSION_11_2:
5ac3d3c9 109 res_pool = dce112_create_resource_pool(
4562236b 110 num_virtual_links, dc);
5ac3d3c9 111 break;
2c8ad2d5
AD		 112 case DCE_VERSION_12_0:
113 res_pool = dce120_create_resource_pool(
114 num_virtual_links, dc);
115 break;
ff5ef992
AD		 116
117#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
118 case DCN_VERSION_1_0:
119 res_pool = dcn10_create_resource_pool(
120 num_virtual_links, dc);
121 break;
122#endif
4562236b
HW		 123 default:
124 break;
125 }
5ac3d3c9
CL		 126 if (res_pool != NULL) {
127 struct firmware_info fw_info = { { 0 } };
128
129 if (dc->ctx->dc_bios->funcs->get_firmware_info(
130 dc->ctx->dc_bios, &fw_info) == BP_RESULT_OK) {
131 res_pool->ref_clock_inKhz = fw_info.pll_info.crystal_frequency;
132 } else
133 ASSERT_CRITICAL(false);
134 }
4562236b 135
5ac3d3c9 136 return res_pool;
4562236b
HW		 137}
138
139void dc_destroy_resource_pool(struct core_dc *dc)
140{
141 if (dc) {
142 if (dc->res_pool)
143 dc->res_pool->funcs->destroy(&dc->res_pool);
144
145 if (dc->hwseq)
146 dm_free(dc->hwseq);
147 }
148}
149
150static void update_num_audio(
151 const struct resource_straps *straps,
152 unsigned int *num_audio,
153 struct audio_support *aud_support)
154{
155 if (straps->hdmi_disable == 0) {
156 aud_support->hdmi_audio_native = true;
157 aud_support->hdmi_audio_on_dongle = true;
158 aud_support->dp_audio = true;
159 } else {
160 if (straps->dc_pinstraps_audio & 0x2) {
161 aud_support->hdmi_audio_on_dongle = true;
162 aud_support->dp_audio = true;
163 } else {
164 aud_support->dp_audio = true;
165 }
166 }
167
168 switch (straps->audio_stream_number) {
169 case 0: /* multi streams supported */
170 break;
171 case 1: /* multi streams not supported */
172 *num_audio = 1;
173 break;
174 default:
175 DC_ERR("DC: unexpected audio fuse!\n");
17a96033 176 }
4562236b
HW		 177}
178
179bool resource_construct(
180 unsigned int num_virtual_links,
181 struct core_dc *dc,
182 struct resource_pool *pool,
183 const struct resource_create_funcs *create_funcs)
184{
185 struct dc_context *ctx = dc->ctx;
186 const struct resource_caps *caps = pool->res_cap;
187 int i;
188 unsigned int num_audio = caps->num_audio;
189 struct resource_straps straps = {0};
190
191 if (create_funcs->read_dce_straps)
192 create_funcs->read_dce_straps(dc->ctx, &straps);
193
194 pool->audio_count = 0;
195 if (create_funcs->create_audio) {
196 /* find the total number of streams available via the
197 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
198 * registers (one for each pin) starting from pin 1
199 * up to the max number of audio pins.
200 * We stop on the first pin where
201 * PORT_CONNECTIVITY == 1 (as instructed by HW team).
202 */
203 update_num_audio(&straps, &num_audio, &pool->audio_support);
204 for (i = 0; i < pool->pipe_count && i < num_audio; i++) {
205 struct audio *aud = create_funcs->create_audio(ctx, i);
206
207 if (aud == NULL) {
208 DC_ERR("DC: failed to create audio!\n");
209 return false;
210 }
211
212 if (!aud->funcs->endpoint_valid(aud)) {
213 aud->funcs->destroy(&aud);
214 break;
215 }
216
217 pool->audios[i] = aud;
218 pool->audio_count++;
219 }
220 }
221
222 pool->stream_enc_count = 0;
223 if (create_funcs->create_stream_encoder) {
224 for (i = 0; i < caps->num_stream_encoder; i++) {
225 pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx);
226 if (pool->stream_enc[i] == NULL)
227 DC_ERR("DC: failed to create stream_encoder!\n");
228 pool->stream_enc_count++;
229 }
230 }
231
232 for (i = 0; i < num_virtual_links; i++) {
233 pool->stream_enc[pool->stream_enc_count] =
234 virtual_stream_encoder_create(
235 ctx, ctx->dc_bios);
236 if (pool->stream_enc[pool->stream_enc_count] == NULL) {
237 DC_ERR("DC: failed to create stream_encoder!\n");
238 return false;
239 }
240 pool->stream_enc_count++;
241 }
242
243 dc->hwseq = create_funcs->create_hwseq(ctx);
244
245 return true;
246}
247
248
249void resource_unreference_clock_source(
250 struct resource_context *res_ctx,
a2b8659d 251 const struct resource_pool *pool,
8c737fcc 252 struct clock_source **clock_source)
4562236b
HW		 253{
254 int i;
a2b8659d
TC		 255 for (i = 0; i < pool->clk_src_count; i++) {
256 if (pool->clock_sources[i] != *clock_source)
4562236b
HW		 257 continue;
258
259 res_ctx->clock_source_ref_count[i]--;
260
261 if (res_ctx->clock_source_ref_count[i] == 0)
8c737fcc 262 (*clock_source)->funcs->cs_power_down(*clock_source);
4562236b
HW		 263
264 break;
265 }
266
a2b8659d 267 if (pool->dp_clock_source == *clock_source) {
4562236b
HW		 268 res_ctx->dp_clock_source_ref_count--;
269
270 if (res_ctx->dp_clock_source_ref_count == 0)
8c737fcc 271 (*clock_source)->funcs->cs_power_down(*clock_source);
4562236b 272 }
8c737fcc 273 *clock_source = NULL;
4562236b
HW		 274}
275
276void resource_reference_clock_source(
277 struct resource_context *res_ctx,
a2b8659d 278 const struct resource_pool *pool,
4562236b
HW		 279 struct clock_source *clock_source)
280{
281 int i;
a2b8659d
TC		 282 for (i = 0; i < pool->clk_src_count; i++) {
283 if (pool->clock_sources[i] != clock_source)
4562236b
HW		 284 continue;
285
286 res_ctx->clock_source_ref_count[i]++;
287 break;
288 }
289
a2b8659d 290 if (pool->dp_clock_source == clock_source)
4562236b
HW		 291 res_ctx->dp_clock_source_ref_count++;
292}
293
294bool resource_are_streams_timing_synchronizable(
295 const struct core_stream *stream1,
296 const struct core_stream *stream2)
297{
298 if (stream1->public.timing.h_total != stream2->public.timing.h_total)
299 return false;
300
301 if (stream1->public.timing.v_total != stream2->public.timing.v_total)
302 return false;
303
304 if (stream1->public.timing.h_addressable
305 != stream2->public.timing.h_addressable)
306 return false;
307
308 if (stream1->public.timing.v_addressable
309 != stream2->public.timing.v_addressable)
310 return false;
311
312 if (stream1->public.timing.pix_clk_khz
313 != stream2->public.timing.pix_clk_khz)
314 return false;
315
316 if (stream1->phy_pix_clk != stream2->phy_pix_clk
7e2fe319
CL		 317 && (!dc_is_dp_signal(stream1->signal)
318 || !dc_is_dp_signal(stream2->signal)))
4562236b
HW		 319 return false;
320
321 return true;
322}
323
324static bool is_sharable_clk_src(
325 const struct pipe_ctx *pipe_with_clk_src,
326 const struct pipe_ctx *pipe)
327{
328 if (pipe_with_clk_src->clock_source == NULL)
329 return false;
330
331 if (pipe_with_clk_src->stream->signal == SIGNAL_TYPE_VIRTUAL)
332 return false;
333
334 if (dc_is_dp_signal(pipe_with_clk_src->stream->signal))
335 return false;
336
337 if (dc_is_hdmi_signal(pipe_with_clk_src->stream->signal)
338 && dc_is_dvi_signal(pipe->stream->signal))
339 return false;
340
341 if (dc_is_hdmi_signal(pipe->stream->signal)
342 && dc_is_dvi_signal(pipe_with_clk_src->stream->signal))
343 return false;
344
345 if (!resource_are_streams_timing_synchronizable(
346 pipe_with_clk_src->stream, pipe->stream))
347 return false;
348
349 return true;
350}
351
352struct clock_source *resource_find_used_clk_src_for_sharing(
353 struct resource_context *res_ctx,
354 struct pipe_ctx *pipe_ctx)
355{
356 int i;
357
358 for (i = 0; i < MAX_PIPES; i++) {
359 if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx))
360 return res_ctx->pipe_ctx[i].clock_source;
361 }
362
363 return NULL;
364}
365
366static enum pixel_format convert_pixel_format_to_dalsurface(
367 enum surface_pixel_format surface_pixel_format)
368{
369 enum pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
370
371 switch (surface_pixel_format) {
372 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
373 dal_pixel_format = PIXEL_FORMAT_INDEX8;
374 break;
375 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
376 dal_pixel_format = PIXEL_FORMAT_RGB565;
377 break;
378 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
379 dal_pixel_format = PIXEL_FORMAT_RGB565;
380 break;
381 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
382 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
383 break;
8693049a 384 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
4562236b
HW		 385 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
386 break;
387 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
388 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
389 break;
390 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
391 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
392 break;
393 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
394 dal_pixel_format = PIXEL_FORMAT_ARGB2101010_XRBIAS;
395 break;
396 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
397 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
398 dal_pixel_format = PIXEL_FORMAT_FP16;
399 break;
400 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
4562236b
HW		 401 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
402 dal_pixel_format = PIXEL_FORMAT_420BPP12;
403 break;
ffbcd19a
VP		 404 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
405 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
406 dal_pixel_format = PIXEL_FORMAT_420BPP15;
407 break;
4562236b
HW		 408 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
409 default:
410 dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
411 break;
412 }
413 return dal_pixel_format;
414}
415
416static void rect_swap_helper(struct rect *rect)
417{
418 uint32_t temp = 0;
419
420 temp = rect->height;
421 rect->height = rect->width;
422 rect->width = temp;
423
424 temp = rect->x;
425 rect->x = rect->y;
426 rect->y = temp;
427}
428
b2d0a103 429static void calculate_viewport(struct pipe_ctx *pipe_ctx)
4562236b 430{
b2d0a103 431 const struct dc_surface *surface = &pipe_ctx->surface->public;
1fbd2cfc 432 const struct dc_stream *stream = &pipe_ctx->stream->public;
b2d0a103 433 struct scaler_data *data = &pipe_ctx->scl_data;
86006a7f 434 struct rect surf_src = surface->src_rect;
1fbd2cfc 435 struct rect clip = { 0 };
b2d0a103
DL		 436 int vpc_div = (data->format == PIXEL_FORMAT_420BPP12
437 || data->format == PIXEL_FORMAT_420BPP15) ? 2 : 1;
1fbd2cfc
DL		 438 bool pri_split = pipe_ctx->bottom_pipe &&
439 pipe_ctx->bottom_pipe->surface == pipe_ctx->surface;
440 bool sec_split = pipe_ctx->top_pipe &&
441 pipe_ctx->top_pipe->surface == pipe_ctx->surface;
4562236b 442
7b779c99
VP		 443 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_SIDE_BY_SIDE ||
444 stream->timing.timing_3d_format == TIMING_3D_FORMAT_TOP_AND_BOTTOM) {
445 pri_split = false;
446 sec_split = false;
447 }
86006a7f
DL		 448
449 if (pipe_ctx->surface->public.rotation == ROTATION_ANGLE_90 ||
450 pipe_ctx->surface->public.rotation == ROTATION_ANGLE_270)
451 rect_swap_helper(&surf_src);
452
4562236b
HW		 453 /* The actual clip is an intersection between stream
454 * source and surface clip
455 */
1fbd2cfc
DL		 456 clip.x = stream->src.x > surface->clip_rect.x ?
457 stream->src.x : surface->clip_rect.x;
4562236b 458
1fbd2cfc
DL		 459 clip.width = stream->src.x + stream->src.width <
460 surface->clip_rect.x + surface->clip_rect.width ?
461 stream->src.x + stream->src.width - clip.x :
462 surface->clip_rect.x + surface->clip_rect.width - clip.x ;
4562236b 463
1fbd2cfc
DL		 464 clip.y = stream->src.y > surface->clip_rect.y ?
465 stream->src.y : surface->clip_rect.y;
4562236b 466
1fbd2cfc
DL		 467 clip.height = stream->src.y + stream->src.height <
468 surface->clip_rect.y + surface->clip_rect.height ?
469 stream->src.y + stream->src.height - clip.y :
470 surface->clip_rect.y + surface->clip_rect.height - clip.y ;
4562236b 471
86006a7f 472 /* offset = surf_src.ofs + (clip.ofs - surface->dst_rect.ofs) * scl_ratio
4562236b
HW		 473 * num_pixels = clip.num_pix * scl_ratio
474 */
86006a7f
DL		 475 data->viewport.x = surf_src.x + (clip.x - surface->dst_rect.x) *
476 surf_src.width / surface->dst_rect.width;
b2d0a103 477 data->viewport.width = clip.width *
86006a7f 478 surf_src.width / surface->dst_rect.width;
4562236b 479
86006a7f
DL		 480 data->viewport.y = surf_src.y + (clip.y - surface->dst_rect.y) *
481 surf_src.height / surface->dst_rect.height;
b2d0a103 482 data->viewport.height = clip.height *
86006a7f 483 surf_src.height / surface->dst_rect.height;
4562236b 484
b2d0a103
DL		 485 /* Round down, compensate in init */
486 data->viewport_c.x = data->viewport.x / vpc_div;
487 data->viewport_c.y = data->viewport.y / vpc_div;
488 data->inits.h_c = (data->viewport.x % vpc_div) != 0 ?
489 dal_fixed31_32_half : dal_fixed31_32_zero;
490 data->inits.v_c = (data->viewport.y % vpc_div) != 0 ?
491 dal_fixed31_32_half : dal_fixed31_32_zero;
492 /* Round up, assume original video size always even dimensions */
493 data->viewport_c.width = (data->viewport.width + vpc_div - 1) / vpc_div;
494 data->viewport_c.height = (data->viewport.height + vpc_div - 1) / vpc_div;
495
496 /* Handle hsplit */
1fbd2cfc
DL		 497 if (pri_split || sec_split) {
498 /* HMirror XOR Secondary_pipe XOR Rotation_180 */
499 bool right_view = (sec_split != surface->horizontal_mirror) !=
500 (surface->rotation == ROTATION_ANGLE_180);
501
502 if (surface->rotation == ROTATION_ANGLE_90
503 || surface->rotation == ROTATION_ANGLE_270)
504 /* Secondary_pipe XOR Rotation_270 */
505 right_view = (surface->rotation == ROTATION_ANGLE_270) != sec_split;
9e6c74ce
DL		 506
507 if (right_view) {
508 data->viewport.width /= 2;
509 data->viewport_c.width /= 2;
510 data->viewport.x += data->viewport.width;
511 data->viewport_c.x += data->viewport_c.width;
512 /* Ceil offset pipe */
513 data->viewport.width += data->viewport.width % 2;
514 data->viewport_c.width += data->viewport_c.width % 2;
515 } else {
516 data->viewport.width /= 2;
517 data->viewport_c.width /= 2;
518 }
b2d0a103 519 }
1fbd2cfc
DL		 520
521 if (surface->rotation == ROTATION_ANGLE_90 ||
522 surface->rotation == ROTATION_ANGLE_270) {
523 rect_swap_helper(&data->viewport_c);
524 rect_swap_helper(&data->viewport);
525 }
4562236b
HW		 526}
527
b2d0a103 528static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip)
4562236b 529{
b2d0a103 530 const struct dc_surface *surface = &pipe_ctx->surface->public;
4562236b 531 struct core_stream *stream = pipe_ctx->stream;
86006a7f
DL		 532 struct rect surf_src = surface->src_rect;
533 struct rect surf_clip = surface->clip_rect;
c802570e 534 int recout_full_x, recout_full_y;
4562236b 535
86006a7f
DL		 536 if (pipe_ctx->surface->public.rotation == ROTATION_ANGLE_90 ||
537 pipe_ctx->surface->public.rotation == ROTATION_ANGLE_270)
538 rect_swap_helper(&surf_src);
539
4562236b 540 pipe_ctx->scl_data.recout.x = stream->public.dst.x;
86006a7f
DL		 541 if (stream->public.src.x < surf_clip.x)
542 pipe_ctx->scl_data.recout.x += (surf_clip.x
4562236b
HW		 543 - stream->public.src.x) * stream->public.dst.width
544 / stream->public.src.width;
545
86006a7f 546 pipe_ctx->scl_data.recout.width = surf_clip.width *
4562236b
HW		 547 stream->public.dst.width / stream->public.src.width;
548 if (pipe_ctx->scl_data.recout.width + pipe_ctx->scl_data.recout.x >
549 stream->public.dst.x + stream->public.dst.width)
550 pipe_ctx->scl_data.recout.width =
551 stream->public.dst.x + stream->public.dst.width
552 - pipe_ctx->scl_data.recout.x;
553
554 pipe_ctx->scl_data.recout.y = stream->public.dst.y;
86006a7f
DL		 555 if (stream->public.src.y < surf_clip.y)
556 pipe_ctx->scl_data.recout.y += (surf_clip.y
4562236b
HW		 557 - stream->public.src.y) * stream->public.dst.height
558 / stream->public.src.height;
559
86006a7f 560 pipe_ctx->scl_data.recout.height = surf_clip.height *
4562236b
HW		 561 stream->public.dst.height / stream->public.src.height;
562 if (pipe_ctx->scl_data.recout.height + pipe_ctx->scl_data.recout.y >
563 stream->public.dst.y + stream->public.dst.height)
564 pipe_ctx->scl_data.recout.height =
565 stream->public.dst.y + stream->public.dst.height
566 - pipe_ctx->scl_data.recout.y;
b2d0a103 567
7b779c99
VP		 568 /* Handle h & vsplit */
569 if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->surface ==
570 pipe_ctx->surface) {
571 if (stream->public.timing.timing_3d_format ==
572 TIMING_3D_FORMAT_TOP_AND_BOTTOM) {
573 pipe_ctx->scl_data.recout.height /= 2;
574 pipe_ctx->scl_data.recout.y += pipe_ctx->scl_data.recout.height;
575 /* Floor primary pipe, ceil 2ndary pipe */
576 pipe_ctx->scl_data.recout.height += pipe_ctx->scl_data.recout.height % 2;
577 } else {
578 pipe_ctx->scl_data.recout.width /= 2;
579 pipe_ctx->scl_data.recout.x += pipe_ctx->scl_data.recout.width;
580 pipe_ctx->scl_data.recout.width += pipe_ctx->scl_data.recout.width % 2;
581 }
582 } else if (pipe_ctx->bottom_pipe &&
86006a7f 583 pipe_ctx->bottom_pipe->surface == pipe_ctx->surface) {
7b779c99
VP		 584 if (stream->public.timing.timing_3d_format ==
585 TIMING_3D_FORMAT_TOP_AND_BOTTOM)
586 pipe_ctx->scl_data.recout.height /= 2;
587 else
588 pipe_ctx->scl_data.recout.width /= 2;
b2d0a103
DL		 589 }
590
86006a7f
DL		 591 /* Unclipped recout offset = stream dst offset + ((surf dst offset - stream surf_src offset)
592 * * 1/ stream scaling ratio) - (surf surf_src offset * 1/ full scl
c802570e
DL		 593 * ratio)
594 */
595 recout_full_x = stream->public.dst.x + (surface->dst_rect.x - stream->public.src.x)
596 * stream->public.dst.width / stream->public.src.width -
86006a7f 597 surf_src.x * surface->dst_rect.width / surf_src.width
c802570e
DL		 598 * stream->public.dst.width / stream->public.src.width;
599 recout_full_y = stream->public.dst.y + (surface->dst_rect.y - stream->public.src.y)
600 * stream->public.dst.height / stream->public.src.height -
86006a7f 601 surf_src.y * surface->dst_rect.height / surf_src.height
c802570e
DL		 602 * stream->public.dst.height / stream->public.src.height;
603
604 recout_skip->width = pipe_ctx->scl_data.recout.x - recout_full_x;
605 recout_skip->height = pipe_ctx->scl_data.recout.y - recout_full_y;
4562236b
HW		 606}
607
b2d0a103 608static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)
4562236b 609{
b2d0a103 610 const struct dc_surface *surface = &pipe_ctx->surface->public;
4562236b 611 struct core_stream *stream = pipe_ctx->stream;
86006a7f 612 struct rect surf_src = surface->src_rect;
1fbd2cfc
DL		 613 const int in_w = stream->public.src.width;
614 const int in_h = stream->public.src.height;
615 const int out_w = stream->public.dst.width;
616 const int out_h = stream->public.dst.height;
4562236b 617
86006a7f
DL		 618 if (pipe_ctx->surface->public.rotation == ROTATION_ANGLE_90 ||
619 pipe_ctx->surface->public.rotation == ROTATION_ANGLE_270)
620 rect_swap_helper(&surf_src);
621
4562236b 622 pipe_ctx->scl_data.ratios.horz = dal_fixed31_32_from_fraction(
86006a7f 623 surf_src.width,
4562236b
HW		 624 surface->dst_rect.width);
625 pipe_ctx->scl_data.ratios.vert = dal_fixed31_32_from_fraction(
86006a7f 626 surf_src.height,
4562236b
HW		 627 surface->dst_rect.height);
628
629 if (surface->stereo_format == PLANE_STEREO_FORMAT_SIDE_BY_SIDE)
630 pipe_ctx->scl_data.ratios.horz.value *= 2;
631 else if (surface->stereo_format == PLANE_STEREO_FORMAT_TOP_AND_BOTTOM)
632 pipe_ctx->scl_data.ratios.vert.value *= 2;
633
634 pipe_ctx->scl_data.ratios.vert.value = div64_s64(
635 pipe_ctx->scl_data.ratios.vert.value * in_h, out_h);
636 pipe_ctx->scl_data.ratios.horz.value = div64_s64(
637 pipe_ctx->scl_data.ratios.horz.value * in_w, out_w);
638
639 pipe_ctx->scl_data.ratios.horz_c = pipe_ctx->scl_data.ratios.horz;
640 pipe_ctx->scl_data.ratios.vert_c = pipe_ctx->scl_data.ratios.vert;
641
b2d0a103
DL		 642 if (pipe_ctx->scl_data.format == PIXEL_FORMAT_420BPP12
643 || pipe_ctx->scl_data.format == PIXEL_FORMAT_420BPP15) {
4562236b
HW		 644 pipe_ctx->scl_data.ratios.horz_c.value /= 2;
645 pipe_ctx->scl_data.ratios.vert_c.value /= 2;
646 }
647}
648
b2d0a103
DL		 649static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct view *recout_skip)
650{
651 struct scaler_data *data = &pipe_ctx->scl_data;
652 struct rect src = pipe_ctx->surface->public.src_rect;
653 int vpc_div = (data->format == PIXEL_FORMAT_420BPP12
654 || data->format == PIXEL_FORMAT_420BPP15) ? 2 : 1;
655
86006a7f 656
1fbd2cfc
DL		 657 if (pipe_ctx->surface->public.rotation == ROTATION_ANGLE_90 ||
658 pipe_ctx->surface->public.rotation == ROTATION_ANGLE_270) {
86006a7f 659 rect_swap_helper(&src);
1fbd2cfc
DL		 660 rect_swap_helper(&data->viewport_c);
661 rect_swap_helper(&data->viewport);
662 }
663
b2d0a103
DL		 664 /*
665 * Init calculated according to formula:
666 * init = (scaling_ratio + number_of_taps + 1) / 2
667 * init_bot = init + scaling_ratio
668 * init_c = init + truncated_vp_c_offset(from calculate viewport)
669 */
670 data->inits.h = dal_fixed31_32_div_int(
671 dal_fixed31_32_add_int(data->ratios.horz, data->taps.h_taps + 1), 2);
672
673 data->inits.h_c = dal_fixed31_32_add(data->inits.h_c, dal_fixed31_32_div_int(
674 dal_fixed31_32_add_int(data->ratios.horz_c, data->taps.h_taps_c + 1), 2));
675
676 data->inits.v = dal_fixed31_32_div_int(
677 dal_fixed31_32_add_int(data->ratios.vert, data->taps.v_taps + 1), 2);
678
679 data->inits.v_c = dal_fixed31_32_add(data->inits.v_c, dal_fixed31_32_div_int(
680 dal_fixed31_32_add_int(data->ratios.vert_c, data->taps.v_taps_c + 1), 2));
681
682
683 /* Adjust for viewport end clip-off */
684 if ((data->viewport.x + data->viewport.width) < (src.x + src.width)) {
685 int vp_clip = src.x + src.width - data->viewport.width - data->viewport.x;
1fbd2cfc
DL		 686 int int_part = dal_fixed31_32_floor(
687 dal_fixed31_32_sub(data->inits.h, data->ratios.horz));
b2d0a103 688
1fbd2cfc 689 int_part = int_part > 0 ? int_part : 0;
b2d0a103
DL		 690 data->viewport.width += int_part < vp_clip ? int_part : vp_clip;
691 }
692 if ((data->viewport.y + data->viewport.height) < (src.y + src.height)) {
693 int vp_clip = src.y + src.height - data->viewport.height - data->viewport.y;
1fbd2cfc
DL		 694 int int_part = dal_fixed31_32_floor(
695 dal_fixed31_32_sub(data->inits.v, data->ratios.vert));
b2d0a103 696
1fbd2cfc 697 int_part = int_part > 0 ? int_part : 0;
b2d0a103
DL		 698 data->viewport.height += int_part < vp_clip ? int_part : vp_clip;
699 }
700 if ((data->viewport_c.x + data->viewport_c.width) < (src.x + src.width) / vpc_div) {
701 int vp_clip = (src.x + src.width) / vpc_div -
702 data->viewport_c.width - data->viewport_c.x;
1fbd2cfc
DL		 703 int int_part = dal_fixed31_32_floor(
704 dal_fixed31_32_sub(data->inits.h_c, data->ratios.horz_c));
b2d0a103 705
1fbd2cfc 706 int_part = int_part > 0 ? int_part : 0;
b2d0a103
DL		 707 data->viewport_c.width += int_part < vp_clip ? int_part : vp_clip;
708 }
709 if ((data->viewport_c.y + data->viewport_c.height) < (src.y + src.height) / vpc_div) {
710 int vp_clip = (src.y + src.height) / vpc_div -
711 data->viewport_c.height - data->viewport_c.y;
1fbd2cfc
DL		 712 int int_part = dal_fixed31_32_floor(
713 dal_fixed31_32_sub(data->inits.v_c, data->ratios.vert_c));
b2d0a103 714
1fbd2cfc 715 int_part = int_part > 0 ? int_part : 0;
b2d0a103
DL		 716 data->viewport_c.height += int_part < vp_clip ? int_part : vp_clip;
717 }
718
719 /* Adjust for non-0 viewport offset */
720 if (data->viewport.x) {
721 int int_part;
722
723 data->inits.h = dal_fixed31_32_add(data->inits.h, dal_fixed31_32_mul_int(
724 data->ratios.horz, recout_skip->width));
725 int_part = dal_fixed31_32_floor(data->inits.h) - data->viewport.x;
726 if (int_part < data->taps.h_taps) {
727 int int_adj = data->viewport.x >= (data->taps.h_taps - int_part) ?
728 (data->taps.h_taps - int_part) : data->viewport.x;
729 data->viewport.x -= int_adj;
730 data->viewport.width += int_adj;
731 int_part += int_adj;
732 } else if (int_part > data->taps.h_taps) {
733 data->viewport.x += int_part - data->taps.h_taps;
734 data->viewport.width -= int_part - data->taps.h_taps;
735 int_part = data->taps.h_taps;
736 }
737 data->inits.h.value &= 0xffffffff;
738 data->inits.h = dal_fixed31_32_add_int(data->inits.h, int_part);
739 }
740
741 if (data->viewport_c.x) {
742 int int_part;
743
744 data->inits.h_c = dal_fixed31_32_add(data->inits.h_c, dal_fixed31_32_mul_int(
745 data->ratios.horz_c, recout_skip->width));
746 int_part = dal_fixed31_32_floor(data->inits.h_c) - data->viewport_c.x;
747 if (int_part < data->taps.h_taps_c) {
748 int int_adj = data->viewport_c.x >= (data->taps.h_taps_c - int_part) ?
749 (data->taps.h_taps_c - int_part) : data->viewport_c.x;
750 data->viewport_c.x -= int_adj;
751 data->viewport_c.width += int_adj;
752 int_part += int_adj;
753 } else if (int_part > data->taps.h_taps_c) {
754 data->viewport_c.x += int_part - data->taps.h_taps_c;
755 data->viewport_c.width -= int_part - data->taps.h_taps_c;
756 int_part = data->taps.h_taps_c;
757 }
758 data->inits.h_c.value &= 0xffffffff;
759 data->inits.h_c = dal_fixed31_32_add_int(data->inits.h_c, int_part);
760 }
761
762 if (data->viewport.y) {
763 int int_part;
764
765 data->inits.v = dal_fixed31_32_add(data->inits.v, dal_fixed31_32_mul_int(
766 data->ratios.vert, recout_skip->height));
767 int_part = dal_fixed31_32_floor(data->inits.v) - data->viewport.y;
768 if (int_part < data->taps.v_taps) {
769 int int_adj = data->viewport.y >= (data->taps.v_taps - int_part) ?
770 (data->taps.v_taps - int_part) : data->viewport.y;
771 data->viewport.y -= int_adj;
772 data->viewport.height += int_adj;
773 int_part += int_adj;
774 } else if (int_part > data->taps.v_taps) {
775 data->viewport.y += int_part - data->taps.v_taps;
776 data->viewport.height -= int_part - data->taps.v_taps;
777 int_part = data->taps.v_taps;
778 }
779 data->inits.v.value &= 0xffffffff;
780 data->inits.v = dal_fixed31_32_add_int(data->inits.v, int_part);
781 }
782
783 if (data->viewport_c.y) {
784 int int_part;
785
786 data->inits.v_c = dal_fixed31_32_add(data->inits.v_c, dal_fixed31_32_mul_int(
787 data->ratios.vert_c, recout_skip->height));
788 int_part = dal_fixed31_32_floor(data->inits.v_c) - data->viewport_c.y;
789 if (int_part < data->taps.v_taps_c) {
790 int int_adj = data->viewport_c.y >= (data->taps.v_taps_c - int_part) ?
791 (data->taps.v_taps_c - int_part) : data->viewport_c.y;
792 data->viewport_c.y -= int_adj;
793 data->viewport_c.height += int_adj;
794 int_part += int_adj;
795 } else if (int_part > data->taps.v_taps_c) {
796 data->viewport_c.y += int_part - data->taps.v_taps_c;
797 data->viewport_c.height -= int_part - data->taps.v_taps_c;
798 int_part = data->taps.v_taps_c;
799 }
800 data->inits.v_c.value &= 0xffffffff;
801 data->inits.v_c = dal_fixed31_32_add_int(data->inits.v_c, int_part);
802 }
803
804 /* Interlaced inits based on final vert inits */
805 data->inits.v_bot = dal_fixed31_32_add(data->inits.v, data->ratios.vert);
806 data->inits.v_c_bot = dal_fixed31_32_add(data->inits.v_c, data->ratios.vert_c);
1fbd2cfc
DL		 807
808 if (pipe_ctx->surface->public.rotation == ROTATION_ANGLE_90 ||
809 pipe_ctx->surface->public.rotation == ROTATION_ANGLE_270) {
810 rect_swap_helper(&data->viewport_c);
811 rect_swap_helper(&data->viewport);
812 }
b2d0a103
DL		 813}
814
815bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
4562236b 816{
b2d0a103 817 const struct dc_surface *surface = &pipe_ctx->surface->public;
4562236b 818 struct dc_crtc_timing *timing = &pipe_ctx->stream->public.timing;
b2d0a103
DL		 819 struct view recout_skip = { 0 };
820 bool res = false;
821
4562236b
HW		 822 /* Important: scaling ratio calculation requires pixel format,
823 * lb depth calculation requires recout and taps require scaling ratios.
b2d0a103 824 * Inits require viewport, taps, ratios and recout of split pipe
4562236b 825 */
b2d0a103
DL		 826 pipe_ctx->scl_data.format = convert_pixel_format_to_dalsurface(
827 pipe_ctx->surface->public.format);
828
829 calculate_scaling_ratios(pipe_ctx);
4562236b 830
b2d0a103 831 calculate_viewport(pipe_ctx);
4562236b
HW		 832
833 if (pipe_ctx->scl_data.viewport.height < 16 || pipe_ctx->scl_data.viewport.width < 16)
834 return false;
835
b2d0a103 836 calculate_recout(pipe_ctx, &recout_skip);
4562236b
HW		 837
838 /**
839 * Setting line buffer pixel depth to 24bpp yields banding
840 * on certain displays, such as the Sharp 4k
841 */
842 pipe_ctx->scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
843
844 pipe_ctx->scl_data.h_active = timing->h_addressable;
845 pipe_ctx->scl_data.v_active = timing->v_addressable;
846
847 /* Taps calculations */
848 res = pipe_ctx->xfm->funcs->transform_get_optimal_number_of_taps(
849 pipe_ctx->xfm, &pipe_ctx->scl_data, &surface->scaling_quality);
850
851 if (!res) {
852 /* Try 24 bpp linebuffer */
853 pipe_ctx->scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP;
854
855 res = pipe_ctx->xfm->funcs->transform_get_optimal_number_of_taps(
856 pipe_ctx->xfm, &pipe_ctx->scl_data, &surface->scaling_quality);
857 }
858
b2d0a103 859 if (res)
1fbd2cfc 860 /* May need to re-check lb size after this in some obscure scenario */
b2d0a103
DL		 861 calculate_inits_and_adj_vp(pipe_ctx, &recout_skip);
862
4562236b
HW		 863 dm_logger_write(pipe_ctx->stream->ctx->logger, LOG_SCALER,
864 "%s: Viewport:\nheight:%d width:%d x:%d "
865 "y:%d\n dst_rect:\nheight:%d width:%d x:%d "
866 "y:%d\n",
867 __func__,
868 pipe_ctx->scl_data.viewport.height,
869 pipe_ctx->scl_data.viewport.width,
870 pipe_ctx->scl_data.viewport.x,
871 pipe_ctx->scl_data.viewport.y,
872 surface->dst_rect.height,
873 surface->dst_rect.width,
874 surface->dst_rect.x,
875 surface->dst_rect.y);
876
877 return res;
878}
879
880
881enum dc_status resource_build_scaling_params_for_context(
882 const struct core_dc *dc,
883 struct validate_context *context)
884{
885 int i;
886
887 for (i = 0; i < MAX_PIPES; i++) {
888 if (context->res_ctx.pipe_ctx[i].surface != NULL &&
889 context->res_ctx.pipe_ctx[i].stream != NULL)
b2d0a103 890 if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i]))
f84a8161 891 return DC_FAIL_SCALING;
4562236b
HW		 892 }
893
894 return DC_OK;
895}
896
ab2541b6 897static void detach_surfaces_for_stream(
4562236b 898 struct validate_context *context,
a2b8659d 899 const struct resource_pool *pool,
ab2541b6 900 const struct dc_stream *dc_stream)
4562236b
HW		 901{
902 int i;
ab2541b6 903 struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream);
4562236b 904
a2b8659d 905 for (i = 0; i < pool->pipe_count; i++) {
4562236b
HW		 906 struct pipe_ctx *cur_pipe = &context->res_ctx.pipe_ctx[i];
907 if (cur_pipe->stream == stream) {
908 cur_pipe->surface = NULL;
909 cur_pipe->top_pipe = NULL;
910 cur_pipe->bottom_pipe = NULL;
911 }
912 }
913}
914
a2b8659d
TC		 915struct pipe_ctx *find_idle_secondary_pipe(
916 struct resource_context *res_ctx,
917 const struct resource_pool *pool)
4562236b
HW		 918{
919 int i;
920 struct pipe_ctx *secondary_pipe = NULL;
921
922 /*
923 * search backwards for the second pipe to keep pipe
924 * assignment more consistent
925 */
926
a2b8659d 927 for (i = pool->pipe_count - 1; i >= 0; i--) {
4562236b
HW		 928 if (res_ctx->pipe_ctx[i].stream == NULL) {
929 secondary_pipe = &res_ctx->pipe_ctx[i];
930 secondary_pipe->pipe_idx = i;
931 break;
932 }
933 }
934
935
936 return secondary_pipe;
937}
938
939struct pipe_ctx *resource_get_head_pipe_for_stream(
940 struct resource_context *res_ctx,
941 const struct core_stream *stream)
942{
943 int i;
a2b8659d 944 for (i = 0; i < MAX_PIPES; i++) {
4562236b 945 if (res_ctx->pipe_ctx[i].stream == stream &&
e73c1efc 946 res_ctx->pipe_ctx[i].stream_enc) {
4562236b
HW		 947 return &res_ctx->pipe_ctx[i];
948 break;
949 }
950 }
951 return NULL;
952}
953
954/*
ab2541b6
AC		 955 * A free_pipe for a stream is defined here as a pipe
956 * that has no surface attached yet
4562236b 957 */
ab2541b6 958static struct pipe_ctx *acquire_free_pipe_for_stream(
745cc746 959 struct validate_context *context,
a2b8659d 960 const struct resource_pool *pool,
ab2541b6 961 const struct dc_stream *dc_stream)
4562236b
HW		 962{
963 int i;
745cc746 964 struct resource_context *res_ctx = &context->res_ctx;
ab2541b6 965 struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream);
4562236b
HW		 966
967 struct pipe_ctx *head_pipe = NULL;
968
969 /* Find head pipe, which has the back end set up*/
970
971 head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
972
973 if (!head_pipe)
974 ASSERT(0);
975
976 if (!head_pipe->surface)
977 return head_pipe;
978
979 /* Re-use pipe already acquired for this stream if available*/
a2b8659d 980 for (i = pool->pipe_count - 1; i >= 0; i--) {
4562236b
HW		 981 if (res_ctx->pipe_ctx[i].stream == stream &&
982 !res_ctx->pipe_ctx[i].surface) {
983 return &res_ctx->pipe_ctx[i];
984 }
985 }
986
987 /*
988 * At this point we have no re-useable pipe for this stream and we need
989 * to acquire an idle one to satisfy the request
990 */
991
a2b8659d 992 if (!pool->funcs->acquire_idle_pipe_for_layer)
4562236b
HW		 993 return NULL;
994
a2b8659d 995 return pool->funcs->acquire_idle_pipe_for_layer(context, pool, stream);
4562236b
HW		 996
997}
998
ab2541b6 999static void release_free_pipes_for_stream(
4562236b 1000 struct resource_context *res_ctx,
ab2541b6 1001 const struct dc_stream *dc_stream)
4562236b
HW		 1002{
1003 int i;
ab2541b6 1004 struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream);
4562236b 1005
a2b8659d 1006 for (i = MAX_PIPES - 1; i >= 0; i--) {
4562236b
HW		 1007 if (res_ctx->pipe_ctx[i].stream == stream &&
1008 !res_ctx->pipe_ctx[i].surface) {
1009 res_ctx->pipe_ctx[i].stream = NULL;
1010 }
1011 }
1012}
1013
1014bool resource_attach_surfaces_to_context(
1015 const struct dc_surface * const *surfaces,
1016 int surface_count,
ab2541b6 1017 const struct dc_stream *dc_stream,
a2b8659d
TC		 1018 struct validate_context *context,
1019 const struct resource_pool *pool)
4562236b
HW		 1020{
1021 int i;
1022 struct pipe_ctx *tail_pipe;
ab2541b6 1023 struct dc_stream_status *stream_status = NULL;
4562236b
HW		 1024
1025
1026 if (surface_count > MAX_SURFACE_NUM) {
1027 dm_error("Surface: can not attach %d surfaces! Maximum is: %d\n",
1028 surface_count, MAX_SURFACE_NUM);
1029 return false;
1030 }
1031
ab2541b6
AC		 1032 for (i = 0; i < context->stream_count; i++)
1033 if (&context->streams[i]->public == dc_stream) {
1034 stream_status = &context->stream_status[i];
4562236b
HW		 1035 break;
1036 }
ab2541b6
AC		 1037 if (stream_status == NULL) {
1038 dm_error("Existing stream not found; failed to attach surfaces\n");
4562236b
HW		 1039 return false;
1040 }
1041
1042 /* retain new surfaces */
1043 for (i = 0; i < surface_count; i++)
1044 dc_surface_retain(surfaces[i]);
1045
a2b8659d 1046 detach_surfaces_for_stream(context, pool, dc_stream);
4562236b
HW		 1047
1048 /* release existing surfaces*/
ab2541b6
AC		 1049 for (i = 0; i < stream_status->surface_count; i++)
1050 dc_surface_release(stream_status->surfaces[i]);
4562236b 1051
ab2541b6
AC		 1052 for (i = surface_count; i < stream_status->surface_count; i++)
1053 stream_status->surfaces[i] = NULL;
4562236b 1054
ab2541b6 1055 stream_status->surface_count = 0;
4562236b
HW		 1056
1057 if (surface_count == 0)
1058 return true;
1059
1060 tail_pipe = NULL;
1061 for (i = 0; i < surface_count; i++) {
1062 struct core_surface *surface = DC_SURFACE_TO_CORE(surfaces[i]);
a2b8659d
TC		 1063 struct pipe_ctx *free_pipe = acquire_free_pipe_for_stream(
1064 context, pool, dc_stream);
4562236b
HW		 1065
1066 if (!free_pipe) {
ab2541b6 1067 stream_status->surfaces[i] = NULL;
4562236b
HW		 1068 return false;
1069 }
1070
1071 free_pipe->surface = surface;
1072
1073 if (tail_pipe) {
1074 free_pipe->top_pipe = tail_pipe;
1075 tail_pipe->bottom_pipe = free_pipe;
1076 }
1077
1078 tail_pipe = free_pipe;
1079 }
1080
ab2541b6 1081 release_free_pipes_for_stream(&context->res_ctx, dc_stream);
4562236b
HW		 1082
1083 /* assign new surfaces*/
1084 for (i = 0; i < surface_count; i++)
ab2541b6 1085 stream_status->surfaces[i] = surfaces[i];
4562236b 1086
ab2541b6 1087 stream_status->surface_count = surface_count;
4562236b
HW		 1088
1089 return true;
1090}
1091
1092
1093static bool is_timing_changed(const struct core_stream *cur_stream,
1094 const struct core_stream *new_stream)
1095{
1096 if (cur_stream == NULL)
1097 return true;
1098
1099 /* If sink pointer changed, it means this is a hotplug, we should do
1100 * full hw setting.
1101 */
1102 if (cur_stream->sink != new_stream->sink)
1103 return true;
1104
1105 /* If output color space is changed, need to reprogram info frames */
1106 if (cur_stream->public.output_color_space !=
1107 new_stream->public.output_color_space)
1108 return true;
1109
1110 return memcmp(
1111 &cur_stream->public.timing,
1112 &new_stream->public.timing,
1113 sizeof(struct dc_crtc_timing)) != 0;
1114}
1115
1116static bool are_stream_backends_same(
1117 const struct core_stream *stream_a, const struct core_stream *stream_b)
1118{
1119 if (stream_a == stream_b)
1120 return true;
1121
1122 if (stream_a == NULL || stream_b == NULL)
1123 return false;
1124
1125 if (is_timing_changed(stream_a, stream_b))
1126 return false;
1127
1128 return true;
1129}
1130
ab2541b6
AC		 1131bool is_stream_unchanged(
1132 const struct core_stream *old_stream, const struct core_stream *stream)
4562236b 1133{
4562236b 1134
ab2541b6
AC		 1135 if (!are_stream_backends_same(old_stream, stream))
1136 return false;
4562236b
HW		 1137
1138 return true;
1139}
1140
1141bool resource_validate_attach_surfaces(
1142 const struct dc_validation_set set[],
1143 int set_count,
1144 const struct validate_context *old_context,
a2b8659d
TC		 1145 struct validate_context *context,
1146 const struct resource_pool *pool)
4562236b
HW		 1147{
1148 int i, j;
1149
1150 for (i = 0; i < set_count; i++) {
430ef426 1151 for (j = 0; old_context && j < old_context->stream_count; j++)
ab2541b6
AC		 1152 if (is_stream_unchanged(
1153 old_context->streams[j],
1154 context->streams[i])) {
4562236b 1155 if (!resource_attach_surfaces_to_context(
ab2541b6
AC		 1156 old_context->stream_status[j].surfaces,
1157 old_context->stream_status[j].surface_count,
1158 &context->streams[i]->public,
a2b8659d 1159 context, pool))
4562236b 1160 return false;
ab2541b6 1161 context->stream_status[i] = old_context->stream_status[j];
4562236b
HW		 1162 }
1163 if (set[i].surface_count != 0)
1164 if (!resource_attach_surfaces_to_context(
1165 set[i].surfaces,
1166 set[i].surface_count,
ab2541b6 1167 &context->streams[i]->public,
a2b8659d 1168 context, pool))
4562236b
HW		 1169 return false;
1170
1171 }
1172
1173 return true;
1174}
1175
1176/* Maximum TMDS single link pixel clock 165MHz */
1177#define TMDS_MAX_PIXEL_CLOCK_IN_KHZ 165000
1178
1179static void set_stream_engine_in_use(
1180 struct resource_context *res_ctx,
a2b8659d 1181 const struct resource_pool *pool,
4562236b
HW		 1182 struct stream_encoder *stream_enc)
1183{
1184 int i;
1185
a2b8659d
TC		 1186 for (i = 0; i < pool->stream_enc_count; i++) {
1187 if (pool->stream_enc[i] == stream_enc)
4562236b
HW		 1188 res_ctx->is_stream_enc_acquired[i] = true;
1189 }
1190}
1191
1192/* TODO: release audio object */
1193static void set_audio_in_use(
1194 struct resource_context *res_ctx,
a2b8659d 1195 const struct resource_pool *pool,
4562236b
HW		 1196 struct audio *audio)
1197{
1198 int i;
a2b8659d
TC		 1199 for (i = 0; i < pool->audio_count; i++) {
1200 if (pool->audios[i] == audio)
4562236b 1201 res_ctx->is_audio_acquired[i] = true;
4562236b
HW		 1202 }
1203}
1204
1205static int acquire_first_free_pipe(
1206 struct resource_context *res_ctx,
a2b8659d 1207 const struct resource_pool *pool,
4562236b
HW		 1208 struct core_stream *stream)
1209{
1210 int i;
1211
a2b8659d 1212 for (i = 0; i < pool->pipe_count; i++) {
4562236b
HW		 1213 if (!res_ctx->pipe_ctx[i].stream) {
1214 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
1215
a2b8659d
TC		 1216 pipe_ctx->tg = pool->timing_generators[i];
1217 pipe_ctx->mi = pool->mis[i];
1218 pipe_ctx->ipp = pool->ipps[i];
1219 pipe_ctx->xfm = pool->transforms[i];
1220 pipe_ctx->opp = pool->opps[i];
1221 pipe_ctx->dis_clk = pool->display_clock;
4562236b
HW		 1222 pipe_ctx->pipe_idx = i;
1223
ff5ef992
AD		 1224#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1225 pipe_ctx->mpc_idx = -1;
1226#endif
1227
4562236b
HW		 1228 pipe_ctx->stream = stream;
1229 return i;
1230 }
1231 }
1232 return -1;
1233}
1234
1235static struct stream_encoder *find_first_free_match_stream_enc_for_link(
1236 struct resource_context *res_ctx,
a2b8659d 1237 const struct resource_pool *pool,
4562236b
HW		 1238 struct core_stream *stream)
1239{
1240 int i;
1241 int j = -1;
1242 struct core_link *link = stream->sink->link;
1243
a2b8659d 1244 for (i = 0; i < pool->stream_enc_count; i++) {
4562236b 1245 if (!res_ctx->is_stream_enc_acquired[i] &&
a2b8659d 1246 pool->stream_enc[i]) {
4562236b
HW		 1247 /* Store first available for MST second display
1248 * in daisy chain use case */
1249 j = i;
a2b8659d 1250 if (pool->stream_enc[i]->id ==
4562236b 1251 link->link_enc->preferred_engine)
a2b8659d 1252 return pool->stream_enc[i];
4562236b
HW		 1253 }
1254 }
1255
1256 /*
1257 * below can happen in cases when stream encoder is acquired:
1258 * 1) for second MST display in chain, so preferred engine already
1259 * acquired;
1260 * 2) for another link, which preferred engine already acquired by any
1261 * MST configuration.
1262 *
1263 * If signal is of DP type and preferred engine not found, return last available
1264 *
1265 * TODO - This is just a patch up and a generic solution is
1266 * required for non DP connectors.
1267 */
1268
1269 if (j >= 0 && dc_is_dp_signal(stream->signal))
a2b8659d 1270 return pool->stream_enc[j];
4562236b
HW		 1271
1272 return NULL;
1273}
1274
a2b8659d
TC		 1275static struct audio *find_first_free_audio(
1276 struct resource_context *res_ctx,
1277 const struct resource_pool *pool)
4562236b
HW		 1278{
1279 int i;
a2b8659d 1280 for (i = 0; i < pool->audio_count; i++) {
4562236b 1281 if (res_ctx->is_audio_acquired[i] == false) {
a2b8659d 1282 return pool->audios[i];
4562236b
HW		 1283 }
1284 }
1285
1286 return 0;
1287}
1288
1289static void update_stream_signal(struct core_stream *stream)
1290{
8b32076c
ST		 1291 if (stream->public.output_signal == SIGNAL_TYPE_NONE) {
1292 const struct dc_sink *dc_sink = stream->public.sink;
1293
1294 if (dc_sink->sink_signal == SIGNAL_TYPE_NONE)
1295 stream->signal =
1296 stream->sink->link->
1297 public.connector_signal;
4562236b 1298 else
8b32076c
ST		 1299 stream->signal = dc_sink->sink_signal;
1300 } else {
1301 stream->signal = stream->public.output_signal;
1302 }
1303
56dcade3
HW		 1304 if (dc_is_dvi_signal(stream->signal)) {
1305 if (stream->public.timing.pix_clk_khz > TMDS_MAX_PIXEL_CLOCK_IN_KHZ)
1306 stream->signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1307 else
1308 stream->signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1309 }
4562236b
HW		 1310}
1311
1312bool resource_is_stream_unchanged(
ab2541b6 1313 const struct validate_context *old_context, const struct core_stream *stream)
4562236b 1314{
ab2541b6 1315 int i;
4562236b 1316
ab2541b6
AC		 1317 for (i = 0; i < old_context->stream_count; i++) {
1318 const struct core_stream *old_stream = old_context->streams[i];
4562236b 1319
ab2541b6 1320 if (are_stream_backends_same(old_stream, stream))
4562236b 1321 return true;
4562236b
HW		 1322 }
1323
1324 return false;
1325}
1326
1327static void copy_pipe_ctx(
1328 const struct pipe_ctx *from_pipe_ctx, struct pipe_ctx *to_pipe_ctx)
1329{
1330 struct core_surface *surface = to_pipe_ctx->surface;
1331 struct core_stream *stream = to_pipe_ctx->stream;
1332
1333 *to_pipe_ctx = *from_pipe_ctx;
1334 to_pipe_ctx->stream = stream;
1335 if (surface != NULL)
1336 to_pipe_ctx->surface = surface;
1337}
1338
1339static struct core_stream *find_pll_sharable_stream(
1340 const struct core_stream *stream_needs_pll,
1341 struct validate_context *context)
1342{
ab2541b6 1343 int i;
4562236b 1344
ab2541b6
AC		 1345 for (i = 0; i < context->stream_count; i++) {
1346 struct core_stream *stream_has_pll = context->streams[i];
4562236b 1347
ab2541b6
AC		 1348 /* We are looking for non dp, non virtual stream */
1349 if (resource_are_streams_timing_synchronizable(
1350 stream_needs_pll, stream_has_pll)
1351 && !dc_is_dp_signal(stream_has_pll->signal)
1352 && stream_has_pll->sink->link->public.connector_signal
1353 != SIGNAL_TYPE_VIRTUAL)
1354 return stream_has_pll;
4562236b 1355
4562236b
HW		 1356 }
1357
1358 return NULL;
1359}
1360
1361static int get_norm_pix_clk(const struct dc_crtc_timing *timing)
1362{
1363 uint32_t pix_clk = timing->pix_clk_khz;
1364 uint32_t normalized_pix_clk = pix_clk;
1365
1366 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
1367 pix_clk /= 2;
cc4d99b8
CL		 1368 if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) {
1369 switch (timing->display_color_depth) {
1370 case COLOR_DEPTH_888:
1371 normalized_pix_clk = pix_clk;
1372 break;
1373 case COLOR_DEPTH_101010:
1374 normalized_pix_clk = (pix_clk * 30) / 24;
1375 break;
1376 case COLOR_DEPTH_121212:
1377 normalized_pix_clk = (pix_clk * 36) / 24;
4562236b 1378 break;
cc4d99b8
CL		 1379 case COLOR_DEPTH_161616:
1380 normalized_pix_clk = (pix_clk * 48) / 24;
4562236b 1381 break;
cc4d99b8
CL		 1382 default:
1383 ASSERT(0);
4562236b 1384 break;
cc4d99b8 1385 }
4562236b 1386 }
4562236b
HW		 1387 return normalized_pix_clk;
1388}
1389
430ef426 1390static void calculate_phy_pix_clks(struct validate_context *context)
4562236b 1391{
ab2541b6 1392 int i;
4562236b 1393
ab2541b6
AC		 1394 for (i = 0; i < context->stream_count; i++) {
1395 struct core_stream *stream = context->streams[i];
4562236b 1396
ab2541b6 1397 update_stream_signal(stream);
4562236b 1398
ab2541b6
AC		 1399 /* update actual pixel clock on all streams */
1400 if (dc_is_hdmi_signal(stream->signal))
1401 stream->phy_pix_clk = get_norm_pix_clk(
1402 &stream->public.timing);
1403 else
1404 stream->phy_pix_clk =
1405 stream->public.timing.pix_clk_khz;
4562236b
HW		 1406 }
1407}
1408
1409enum dc_status resource_map_pool_resources(
1410 const struct core_dc *dc,
430ef426
DL		 1411 struct validate_context *context,
1412 struct validate_context *old_context)
4562236b 1413{
a2b8659d 1414 const struct resource_pool *pool = dc->res_pool;
ab2541b6 1415 int i, j;
4562236b 1416
430ef426 1417 calculate_phy_pix_clks(context);
4562236b 1418
430ef426 1419 for (i = 0; old_context && i < context->stream_count; i++) {
ab2541b6 1420 struct core_stream *stream = context->streams[i];
4562236b 1421
430ef426
DL		 1422 if (!resource_is_stream_unchanged(old_context, stream)) {
1423 if (stream != NULL && old_context->streams[i] != NULL) {
4b679bc3 1424 stream->bit_depth_params =
430ef426
DL		 1425 old_context->streams[i]->bit_depth_params;
1426 stream->clamping = old_context->streams[i]->clamping;
a2b8659d
TC		 1427 continue;
1428 }
4b679bc3 1429 }
7e2fe319 1430
ab2541b6 1431 /* mark resources used for stream that is already active */
a2b8659d 1432 for (j = 0; j < pool->pipe_count; j++) {
ab2541b6
AC		 1433 struct pipe_ctx *pipe_ctx =
1434 &context->res_ctx.pipe_ctx[j];
1435 const struct pipe_ctx *old_pipe_ctx =
430ef426 1436 &old_context->res_ctx.pipe_ctx[j];
4562236b 1437
ab2541b6
AC		 1438 if (!are_stream_backends_same(old_pipe_ctx->stream, stream))
1439 continue;
8c737fcc 1440
268cadbd
YS		 1441 if (old_pipe_ctx->top_pipe)
1442 continue;
1443
ab2541b6
AC		 1444 pipe_ctx->stream = stream;
1445 copy_pipe_ctx(old_pipe_ctx, pipe_ctx);
4562236b 1446
ab2541b6
AC		 1447 /* Split pipe resource, do not acquire back end */
1448 if (!pipe_ctx->stream_enc)
1449 continue;
4562236b 1450
ab2541b6 1451 set_stream_engine_in_use(
a2b8659d 1452 &context->res_ctx, pool,
ab2541b6
AC		 1453 pipe_ctx->stream_enc);
1454
1455 /* Switch to dp clock source only if there is
1456 * no non dp stream that shares the same timing
1457 * with the dp stream.
1458 */
1459 if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
1460 !find_pll_sharable_stream(stream, context))
a2b8659d 1461 pipe_ctx->clock_source = pool->dp_clock_source;
ab2541b6
AC		 1462
1463 resource_reference_clock_source(
a2b8659d 1464 &context->res_ctx, pool,
ab2541b6
AC		 1465 pipe_ctx->clock_source);
1466
a2b8659d
TC		 1467 set_audio_in_use(&context->res_ctx, pool,
1468 pipe_ctx->audio);
4562236b
HW		 1469 }
1470 }
1471
ab2541b6
AC		 1472 for (i = 0; i < context->stream_count; i++) {
1473 struct core_stream *stream = context->streams[i];
1474 struct pipe_ctx *pipe_ctx = NULL;
1475 int pipe_idx = -1;
4562236b 1476
430ef426 1477 if (old_context && resource_is_stream_unchanged(old_context, stream))
ab2541b6
AC		 1478 continue;
1479 /* acquire new resources */
a2b8659d
TC		 1480 pipe_idx = acquire_first_free_pipe(
1481 &context->res_ctx, pool, stream);
ab2541b6
AC		 1482 if (pipe_idx < 0)
1483 return DC_NO_CONTROLLER_RESOURCE;
1484
ab2541b6
AC		 1485 pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
1486
1487 pipe_ctx->stream_enc =
1488 find_first_free_match_stream_enc_for_link(
a2b8659d 1489 &context->res_ctx, pool, stream);
ab2541b6
AC		 1490
1491 if (!pipe_ctx->stream_enc)
1492 return DC_NO_STREAM_ENG_RESOURCE;
1493
1494 set_stream_engine_in_use(
a2b8659d 1495 &context->res_ctx, pool,
ab2541b6
AC		 1496 pipe_ctx->stream_enc);
1497
1498 /* TODO: Add check if ASIC support and EDID audio */
4a9a5d62 1499 if (!stream->sink->public.converter_disable_audio &&
ab2541b6
AC		 1500 dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&
1501 stream->public.audio_info.mode_count) {
1502 pipe_ctx->audio = find_first_free_audio(
a2b8659d 1503 &context->res_ctx, pool);
ab2541b6
AC		 1504
1505 /*
1506 * Audio assigned in order first come first get.
1507 * There are asics which has number of audio
1508 * resources less then number of pipes
1509 */
1510 if (pipe_ctx->audio)
1511 set_audio_in_use(
a2b8659d 1512 &context->res_ctx, pool,
ab2541b6 1513 pipe_ctx->audio);
4562236b 1514 }
ab2541b6
AC		 1515
1516 context->stream_status[i].primary_otg_inst = pipe_ctx->tg->inst;
4562236b
HW		 1517 }
1518
1519 return DC_OK;
1520}
1521
ab2541b6
AC		 1522/* first stream in the context is used to populate the rest */
1523void validate_guaranteed_copy_streams(
4562236b 1524 struct validate_context *context,
ab2541b6 1525 int max_streams)
4562236b
HW		 1526{
1527 int i;
1528
ab2541b6
AC		 1529 for (i = 1; i < max_streams; i++) {
1530 context->streams[i] = context->streams[0];
4562236b
HW		 1531
1532 copy_pipe_ctx(&context->res_ctx.pipe_ctx[0],
1533 &context->res_ctx.pipe_ctx[i]);
1534 context->res_ctx.pipe_ctx[i].stream =
1535 context->res_ctx.pipe_ctx[0].stream;
1536
ab2541b6
AC		 1537 dc_stream_retain(&context->streams[i]->public);
1538 context->stream_count++;
4562236b
HW		 1539 }
1540}
1541
6e4d6bee
TC		 1542static void patch_gamut_packet_checksum(
1543 struct encoder_info_packet *gamut_packet)
4562236b 1544{
4562236b 1545 /* For gamut we recalc checksum */
6e4d6bee 1546 if (gamut_packet->valid) {
4562236b
HW		 1547 uint8_t chk_sum = 0;
1548 uint8_t *ptr;
1549 uint8_t i;
1550
4562236b 1551 /*start of the Gamut data. */
6e4d6bee 1552 ptr = &gamut_packet->sb[3];
4562236b 1553
6e4d6bee 1554 for (i = 0; i <= gamut_packet->sb[1]; i++)
4562236b
HW		 1555 chk_sum += ptr[i];
1556
6e4d6bee 1557 gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum);
1646a6fe 1558 }
4562236b
HW		 1559}
1560
1561static void set_avi_info_frame(
6e4d6bee 1562 struct encoder_info_packet *info_packet,
4562236b
HW		 1563 struct pipe_ctx *pipe_ctx)
1564{
1565 struct core_stream *stream = pipe_ctx->stream;
1566 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
1567 struct info_frame info_frame = { {0} };
1568 uint32_t pixel_encoding = 0;
1569 enum scanning_type scan_type = SCANNING_TYPE_NODATA;
1570 enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA;
1571 bool itc = false;
1572 uint8_t cn0_cn1 = 0;
1573 uint8_t *check_sum = NULL;
1574 uint8_t byte_index = 0;
e8d726b7 1575 union hdmi_info_packet *hdmi_info = &info_frame.avi_info_packet.info_packet_hdmi;
4562236b 1576
4562236b
HW		 1577 color_space = pipe_ctx->stream->public.output_color_space;
1578
1579 /* Initialize header */
e8d726b7 1580 hdmi_info->bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI;
4562236b
HW		 1581 /* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall
1582 * not be used in HDMI 2.0 (Section 10.1) */
e8d726b7
RA		 1583 hdmi_info->bits.header.version = 2;
1584 hdmi_info->bits.header.length = HDMI_AVI_INFOFRAME_SIZE;
4562236b
HW		 1585
1586 /*
1587 * IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built
1588 * according to HDMI 2.0 spec (Section 10.1)
1589 */
1590
1591 switch (stream->public.timing.pixel_encoding) {
1592 case PIXEL_ENCODING_YCBCR422:
1593 pixel_encoding = 1;
1594 break;
1595
1596 case PIXEL_ENCODING_YCBCR444:
1597 pixel_encoding = 2;
1598 break;
1599 case PIXEL_ENCODING_YCBCR420:
1600 pixel_encoding = 3;
1601 break;
1602
1603 case PIXEL_ENCODING_RGB:
1604 default:
1605 pixel_encoding = 0;
1606 }
1607
1608 /* Y0_Y1_Y2 : The pixel encoding */
1609 /* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */
e8d726b7 1610 hdmi_info->bits.Y0_Y1_Y2 = pixel_encoding;
4562236b
HW		 1611
1612 /* A0 = 1 Active Format Information valid */
e8d726b7 1613 hdmi_info->bits.A0 = ACTIVE_FORMAT_VALID;
4562236b
HW		 1614
1615 /* B0, B1 = 3; Bar info data is valid */
e8d726b7 1616 hdmi_info->bits.B0_B1 = BAR_INFO_BOTH_VALID;
4562236b 1617
e8d726b7 1618 hdmi_info->bits.SC0_SC1 = PICTURE_SCALING_UNIFORM;
4562236b
HW		 1619
1620 /* S0, S1 : Underscan / Overscan */
1621 /* TODO: un-hardcode scan type */
1622 scan_type = SCANNING_TYPE_UNDERSCAN;
e8d726b7 1623 hdmi_info->bits.S0_S1 = scan_type;
4562236b
HW		 1624
1625 /* C0, C1 : Colorimetry */
8fde5884
CL		 1626 if (color_space == COLOR_SPACE_YCBCR709 ||
1627 color_space == COLOR_SPACE_YCBCR709_LIMITED)
e8d726b7 1628 hdmi_info->bits.C0_C1 = COLORIMETRY_ITU709;
8fde5884
CL		 1629 else if (color_space == COLOR_SPACE_YCBCR601 ||
1630 color_space == COLOR_SPACE_YCBCR601_LIMITED)
e8d726b7 1631 hdmi_info->bits.C0_C1 = COLORIMETRY_ITU601;
8fde5884
CL		 1632 else {
1633 if (stream->public.timing.pixel_encoding != PIXEL_ENCODING_RGB)
1634 BREAK_TO_DEBUGGER();
e8d726b7 1635 hdmi_info->bits.C0_C1 = COLORIMETRY_NO_DATA;
8fde5884 1636 }
534db198 1637 if (color_space == COLOR_SPACE_2020_RGB_FULLRANGE ||
8fde5884
CL		 1638 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE ||
1639 color_space == COLOR_SPACE_2020_YCBCR) {
e8d726b7
RA		 1640 hdmi_info->bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR;
1641 hdmi_info->bits.C0_C1 = COLORIMETRY_EXTENDED;
534db198 1642 } else if (color_space == COLOR_SPACE_ADOBERGB) {
e8d726b7
RA		 1643 hdmi_info->bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB;
1644 hdmi_info->bits.C0_C1 = COLORIMETRY_EXTENDED;
534db198
AZ		 1645 }
1646
4562236b
HW		 1647 /* TODO: un-hardcode aspect ratio */
1648 aspect = stream->public.timing.aspect_ratio;
1649
1650 switch (aspect) {
1651 case ASPECT_RATIO_4_3:
1652 case ASPECT_RATIO_16_9:
e8d726b7 1653 hdmi_info->bits.M0_M1 = aspect;
4562236b
HW		 1654 break;
1655
1656 case ASPECT_RATIO_NO_DATA:
1657 case ASPECT_RATIO_64_27:
1658 case ASPECT_RATIO_256_135:
1659 default:
e8d726b7 1660 hdmi_info->bits.M0_M1 = 0;
4562236b
HW		 1661 }
1662
1663 /* Active Format Aspect ratio - same as Picture Aspect Ratio. */
e8d726b7 1664 hdmi_info->bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE;
4562236b
HW		 1665
1666 /* TODO: un-hardcode cn0_cn1 and itc */
1667 cn0_cn1 = 0;
1668 itc = false;
1669
1670 if (itc) {
e8d726b7
RA		 1671 hdmi_info->bits.ITC = 1;
1672 hdmi_info->bits.CN0_CN1 = cn0_cn1;
4562236b
HW		 1673 }
1674
1675 /* TODO : We should handle YCC quantization */
1676 /* but we do not have matrix calculation */
1677 if (color_space == COLOR_SPACE_SRGB) {
e8d726b7
RA		 1678 hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_FULL_RANGE;
1679 hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_FULL_RANGE;
4562236b 1680 } else if (color_space == COLOR_SPACE_SRGB_LIMITED) {
e8d726b7
RA		 1681 hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_LIMITED_RANGE;
1682 hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
4562236b 1683 } else {
e8d726b7
RA		 1684 hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
1685 hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
4562236b
HW		 1686 }
1687
e8d726b7 1688 hdmi_info->bits.VIC0_VIC7 =
4562236b
HW		 1689 stream->public.timing.vic;
1690
1691 /* pixel repetition
1692 * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel
1693 * repetition start from 1 */
e8d726b7 1694 hdmi_info->bits.PR0_PR3 = 0;
4562236b
HW		 1695
1696 /* Bar Info
1697 * barTop: Line Number of End of Top Bar.
1698 * barBottom: Line Number of Start of Bottom Bar.
1699 * barLeft: Pixel Number of End of Left Bar.
1700 * barRight: Pixel Number of Start of Right Bar. */
e8d726b7
RA		 1701 hdmi_info->bits.bar_top = stream->public.timing.v_border_top;
1702 hdmi_info->bits.bar_bottom = (stream->public.timing.v_border_top
4562236b 1703 - stream->public.timing.v_border_bottom + 1);
e8d726b7
RA		 1704 hdmi_info->bits.bar_left = stream->public.timing.h_border_left;
1705 hdmi_info->bits.bar_right = (stream->public.timing.h_total
4562236b
HW		 1706 - stream->public.timing.h_border_right + 1);
1707
1708 /* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */
e8d726b7
RA		 1709 check_sum = &info_frame.avi_info_packet.info_packet_hdmi.packet_raw_data.sb[0];
1710
3e183c5f 1711 *check_sum = HDMI_INFOFRAME_TYPE_AVI + HDMI_AVI_INFOFRAME_SIZE + 2;
4562236b 1712
3e183c5f 1713 for (byte_index = 1; byte_index <= HDMI_AVI_INFOFRAME_SIZE; byte_index++)
e8d726b7 1714 *check_sum += hdmi_info->packet_raw_data.sb[byte_index];
4562236b
HW		 1715
1716 /* one byte complement */
1717 *check_sum = (uint8_t) (0x100 - *check_sum);
1718
1719 /* Store in hw_path_mode */
e8d726b7
RA		 1720 info_packet->hb0 = hdmi_info->packet_raw_data.hb0;
1721 info_packet->hb1 = hdmi_info->packet_raw_data.hb1;
1722 info_packet->hb2 = hdmi_info->packet_raw_data.hb2;
4562236b 1723
e66e4d64
HW		 1724 for (byte_index = 0; byte_index < sizeof(info_frame.avi_info_packet.
1725 info_packet_hdmi.packet_raw_data.sb); byte_index++)
4562236b 1726 info_packet->sb[byte_index] = info_frame.avi_info_packet.
e66e4d64 1727 info_packet_hdmi.packet_raw_data.sb[byte_index];
4562236b
HW		 1728
1729 info_packet->valid = true;
1730}
1731
6e4d6bee
TC		 1732static void set_vendor_info_packet(
1733 struct encoder_info_packet *info_packet,
1734 struct core_stream *stream)
4562236b
HW		 1735{
1736 uint32_t length = 0;
1737 bool hdmi_vic_mode = false;
1738 uint8_t checksum = 0;
1739 uint32_t i = 0;
1740 enum dc_timing_3d_format format;
1741
4562236b
HW		 1742 format = stream->public.timing.timing_3d_format;
1743
1744 /* Can be different depending on packet content */
1745 length = 5;
1746
1747 if (stream->public.timing.hdmi_vic != 0
1748 && stream->public.timing.h_total >= 3840
1749 && stream->public.timing.v_total >= 2160)
1750 hdmi_vic_mode = true;
1751
1752 /* According to HDMI 1.4a CTS, VSIF should be sent
1753 * for both 3D stereo and HDMI VIC modes.
1754 * For all other modes, there is no VSIF sent. */
1755
1756 if (format == TIMING_3D_FORMAT_NONE && !hdmi_vic_mode)
1757 return;
1758
1759 /* 24bit IEEE Registration identifier (0x000c03). LSB first. */
1760 info_packet->sb[1] = 0x03;
1761 info_packet->sb[2] = 0x0C;
1762 info_packet->sb[3] = 0x00;
1763
1764 /*PB4: 5 lower bytes = 0 (reserved). 3 higher bits = HDMI_Video_Format.
1765 * The value for HDMI_Video_Format are:
1766 * 0x0 (0b000) - No additional HDMI video format is presented in this
1767 * packet
1768 * 0x1 (0b001) - Extended resolution format present. 1 byte of HDMI_VIC
1769 * parameter follows
1770 * 0x2 (0b010) - 3D format indication present. 3D_Structure and
1771 * potentially 3D_Ext_Data follows
1772 * 0x3..0x7 (0b011..0b111) - reserved for future use */
1773 if (format != TIMING_3D_FORMAT_NONE)
1774 info_packet->sb[4] = (2 << 5);
1775 else if (hdmi_vic_mode)
1776 info_packet->sb[4] = (1 << 5);
1777
1778 /* PB5: If PB4 claims 3D timing (HDMI_Video_Format = 0x2):
1779 * 4 lower bites = 0 (reserved). 4 higher bits = 3D_Structure.
1780 * The value for 3D_Structure are:
1781 * 0x0 - Frame Packing
1782 * 0x1 - Field Alternative
1783 * 0x2 - Line Alternative
1784 * 0x3 - Side-by-Side (full)
1785 * 0x4 - L + depth
1786 * 0x5 - L + depth + graphics + graphics-depth
1787 * 0x6 - Top-and-Bottom
1788 * 0x7 - Reserved for future use
1789 * 0x8 - Side-by-Side (Half)
1790 * 0x9..0xE - Reserved for future use
1791 * 0xF - Not used */
1792 switch (format) {
1793 case TIMING_3D_FORMAT_HW_FRAME_PACKING:
1794 case TIMING_3D_FORMAT_SW_FRAME_PACKING:
1795 info_packet->sb[5] = (0x0 << 4);
1796 break;
1797
1798 case TIMING_3D_FORMAT_SIDE_BY_SIDE:
1799 case TIMING_3D_FORMAT_SBS_SW_PACKED:
1800 info_packet->sb[5] = (0x8 << 4);
1801 length = 6;
1802 break;
1803
1804 case TIMING_3D_FORMAT_TOP_AND_BOTTOM:
1805 case TIMING_3D_FORMAT_TB_SW_PACKED:
1806 info_packet->sb[5] = (0x6 << 4);
1807 break;
1808
1809 default:
1810 break;
1811 }
1812
1813 /*PB5: If PB4 is set to 0x1 (extended resolution format)
1814 * fill PB5 with the correct HDMI VIC code */
1815 if (hdmi_vic_mode)
1816 info_packet->sb[5] = stream->public.timing.hdmi_vic;
1817
1818 /* Header */
3e183c5f 1819 info_packet->hb0 = HDMI_INFOFRAME_TYPE_VENDOR; /* VSIF packet type. */
4562236b
HW		 1820 info_packet->hb1 = 0x01; /* Version */
1821
1822 /* 4 lower bits = Length, 4 higher bits = 0 (reserved) */
1823 info_packet->hb2 = (uint8_t) (length);
1824
1825 /* Calculate checksum */
1826 checksum = 0;
1827 checksum += info_packet->hb0;
1828 checksum += info_packet->hb1;
1829 checksum += info_packet->hb2;
1830
1831 for (i = 1; i <= length; i++)
1832 checksum += info_packet->sb[i];
1833
1834 info_packet->sb[0] = (uint8_t) (0x100 - checksum);
1835
1836 info_packet->valid = true;
1837}
1838
6e4d6bee
TC		 1839static void set_spd_info_packet(
1840 struct encoder_info_packet *info_packet,
1841 struct core_stream *stream)
4562236b
HW		 1842{
1843 /* SPD info packet for FreeSync */
1844
1845 unsigned char checksum = 0;
1846 unsigned int idx, payload_size = 0;
1847
1848 /* Check if Freesync is supported. Return if false. If true,
1849 * set the corresponding bit in the info packet
1850 */
1851 if (stream->public.freesync_ctx.supported == false)
1852 return;
1853
1854 if (dc_is_hdmi_signal(stream->signal)) {
1855
1856 /* HEADER */
1857
1858 /* HB0 = Packet Type = 0x83 (Source Product
1859 * Descriptor InfoFrame)
1860 */
3e183c5f 1861 info_packet->hb0 = HDMI_INFOFRAME_TYPE_SPD;
4562236b
HW		 1862
1863 /* HB1 = Version = 0x01 */
1864 info_packet->hb1 = 0x01;
1865
1866 /* HB2 = [Bits 7:5 = 0] [Bits 4:0 = Length = 0x08] */
1867 info_packet->hb2 = 0x08;
1868
1869 payload_size = 0x08;
1870
1871 } else if (dc_is_dp_signal(stream->signal)) {
1872
1873 /* HEADER */
1874
1875 /* HB0 = Secondary-data Packet ID = 0 - Only non-zero
1876 * when used to associate audio related info packets
1877 */
1878 info_packet->hb0 = 0x00;
1879
1880 /* HB1 = Packet Type = 0x83 (Source Product
1881 * Descriptor InfoFrame)
1882 */
3e183c5f 1883 info_packet->hb1 = HDMI_INFOFRAME_TYPE_SPD;
4562236b
HW		 1884
1885 /* HB2 = [Bits 7:0 = Least significant eight bits -
1886 * For INFOFRAME, the value must be 1Bh]
1887 */
1888 info_packet->hb2 = 0x1B;
1889
1890 /* HB3 = [Bits 7:2 = INFOFRAME SDP Version Number = 0x1]
1891 * [Bits 1:0 = Most significant two bits = 0x00]
1892 */
1893 info_packet->hb3 = 0x04;
1894
1895 payload_size = 0x1B;
1896 }
1897
1898 /* PB1 = 0x1A (24bit AMD IEEE OUI (0x00001A) - Byte 0) */
1899 info_packet->sb[1] = 0x1A;
1900
1901 /* PB2 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 1) */
1902 info_packet->sb[2] = 0x00;
1903
1904 /* PB3 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 2) */
1905 info_packet->sb[3] = 0x00;
1906
1907 /* PB4 = Reserved */
1908 info_packet->sb[4] = 0x00;
1909
1910 /* PB5 = Reserved */
1911 info_packet->sb[5] = 0x00;
1912
1913 /* PB6 = [Bits 7:3 = Reserved] */
1914 info_packet->sb[6] = 0x00;
1915
1916 if (stream->public.freesync_ctx.supported == true)
1917 /* PB6 = [Bit 0 = FreeSync Supported] */
1918 info_packet->sb[6] |= 0x01;
1919
1920 if (stream->public.freesync_ctx.enabled == true)
1921 /* PB6 = [Bit 1 = FreeSync Enabled] */
1922 info_packet->sb[6] |= 0x02;
1923
1924 if (stream->public.freesync_ctx.active == true)
1925 /* PB6 = [Bit 2 = FreeSync Active] */
1926 info_packet->sb[6] |= 0x04;
1927
1928 /* PB7 = FreeSync Minimum refresh rate (Hz) */
1929 info_packet->sb[7] = (unsigned char) (stream->public.freesync_ctx.
1930 min_refresh_in_micro_hz / 1000000);
1931
1932 /* PB8 = FreeSync Maximum refresh rate (Hz)
1933 *
1934 * Note: We do not use the maximum capable refresh rate
1935 * of the panel, because we should never go above the field
1936 * rate of the mode timing set.
1937 */
1938 info_packet->sb[8] = (unsigned char) (stream->public.freesync_ctx.
1939 nominal_refresh_in_micro_hz / 1000000);
1940
1941 /* PB9 - PB27 = Reserved */
1942 for (idx = 9; idx <= 27; idx++)
1943 info_packet->sb[idx] = 0x00;
1944
1945 /* Calculate checksum */
1946 checksum += info_packet->hb0;
1947 checksum += info_packet->hb1;
1948 checksum += info_packet->hb2;
1949 checksum += info_packet->hb3;
1950
1951 for (idx = 1; idx <= payload_size; idx++)
1952 checksum += info_packet->sb[idx];
1953
1954 /* PB0 = Checksum (one byte complement) */
1955 info_packet->sb[0] = (unsigned char) (0x100 - checksum);
1956
1957 info_packet->valid = true;
1958}
1959
1646a6fe 1960static void set_hdr_static_info_packet(
6e4d6bee 1961 struct encoder_info_packet *info_packet,
1646a6fe 1962 struct core_surface *surface,
6e4d6bee 1963 struct core_stream *stream)
1646a6fe 1964{
e5cf325b 1965 uint16_t i = 0;
1646a6fe 1966 enum signal_type signal = stream->signal;
e5cf325b
HW		 1967 struct dc_hdr_static_metadata hdr_metadata;
1968 uint32_t data;
1646a6fe
AW		 1969
1970 if (!surface)
1971 return;
1972
e5cf325b 1973 hdr_metadata = surface->public.hdr_static_ctx;
1646a6fe 1974
70063a59 1975 if (!hdr_metadata.hdr_supported)
10bff005
YS		 1976 return;
1977
1646a6fe
AW		 1978 if (dc_is_hdmi_signal(signal)) {
1979 info_packet->valid = true;
1980
1981 info_packet->hb0 = 0x87;
1982 info_packet->hb1 = 0x01;
1983 info_packet->hb2 = 0x1A;
1984 i = 1;
1985 } else if (dc_is_dp_signal(signal)) {
1986 info_packet->valid = true;
1987
1988 info_packet->hb0 = 0x00;
1989 info_packet->hb1 = 0x87;
1990 info_packet->hb2 = 0x1D;
1991 info_packet->hb3 = (0x13 << 2);
1992 i = 2;
1993 }
1994
1646a6fe
AW		 1995 data = hdr_metadata.is_hdr;
1996 info_packet->sb[i++] = data ? 0x02 : 0x00;
1997 info_packet->sb[i++] = 0x00;
1998
1999 data = hdr_metadata.chromaticity_green_x / 2;
2000 info_packet->sb[i++] = data & 0xFF;
2001 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2002
2003 data = hdr_metadata.chromaticity_green_y / 2;
2004 info_packet->sb[i++] = data & 0xFF;
2005 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2006
2007 data = hdr_metadata.chromaticity_blue_x / 2;
2008 info_packet->sb[i++] = data & 0xFF;
2009 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2010
2011 data = hdr_metadata.chromaticity_blue_y / 2;
2012 info_packet->sb[i++] = data & 0xFF;
2013 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2014
2015 data = hdr_metadata.chromaticity_red_x / 2;
2016 info_packet->sb[i++] = data & 0xFF;
2017 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2018
2019 data = hdr_metadata.chromaticity_red_y / 2;
2020 info_packet->sb[i++] = data & 0xFF;
2021 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2022
2023 data = hdr_metadata.chromaticity_white_point_x / 2;
2024 info_packet->sb[i++] = data & 0xFF;
2025 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2026
2027 data = hdr_metadata.chromaticity_white_point_y / 2;
2028 info_packet->sb[i++] = data & 0xFF;
2029 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2030
2031 data = hdr_metadata.max_luminance;
2032 info_packet->sb[i++] = data & 0xFF;
2033 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2034
2035 data = hdr_metadata.min_luminance;
2036 info_packet->sb[i++] = data & 0xFF;
2037 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2038
2039 data = hdr_metadata.maximum_content_light_level;
2040 info_packet->sb[i++] = data & 0xFF;
2041 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2042
2043 data = hdr_metadata.maximum_frame_average_light_level;
2044 info_packet->sb[i++] = data & 0xFF;
2045 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2046
2047 if (dc_is_hdmi_signal(signal)) {
2048 uint32_t checksum = 0;
2049
2050 checksum += info_packet->hb0;
2051 checksum += info_packet->hb1;
2052 checksum += info_packet->hb2;
2053
2054 for (i = 1; i <= info_packet->hb2; i++)
2055 checksum += info_packet->sb[i];
2056
2057 info_packet->sb[0] = 0x100 - checksum;
2058 } else if (dc_is_dp_signal(signal)) {
2059 info_packet->sb[0] = 0x01;
2060 info_packet->sb[1] = 0x1A;
2061 }
2062}
2063
6e4d6bee
TC		 2064static void set_vsc_info_packet(
2065 struct encoder_info_packet *info_packet,
2066 struct core_stream *stream)
4562236b
HW		 2067{
2068 unsigned int vscPacketRevision = 0;
2069 unsigned int i;
2070
94267b3d 2071 if (stream->sink->link->psr_enabled) {
4562236b
HW		 2072 vscPacketRevision = 2;
2073 }
2074
2075 /* VSC packet not needed based on the features
2076 * supported by this DP display
2077 */
2078 if (vscPacketRevision == 0)
2079 return;
2080
2081 if (vscPacketRevision == 0x2) {
2082 /* Secondary-data Packet ID = 0*/
2083 info_packet->hb0 = 0x00;
2084 /* 07h - Packet Type Value indicating Video
2085 * Stream Configuration packet
2086 */
2087 info_packet->hb1 = 0x07;
2088 /* 02h = VSC SDP supporting 3D stereo and PSR
2089 * (applies to eDP v1.3 or higher).
2090 */
2091 info_packet->hb2 = 0x02;
2092 /* 08h = VSC packet supporting 3D stereo + PSR
2093 * (HB2 = 02h).
2094 */
2095 info_packet->hb3 = 0x08;
2096
2097 for (i = 0; i < 28; i++)
2098 info_packet->sb[i] = 0;
2099
2100 info_packet->valid = true;
2101 }
2102
2103 /*TODO: stereo 3D support and extend pixel encoding colorimetry*/
2104}
2105
8122a253 2106void dc_resource_validate_ctx_destruct(struct validate_context *context)
4562236b
HW		 2107{
2108 int i, j;
2109
ab2541b6
AC		 2110 for (i = 0; i < context->stream_count; i++) {
2111 for (j = 0; j < context->stream_status[i].surface_count; j++)
4562236b 2112 dc_surface_release(
ab2541b6 2113 context->stream_status[i].surfaces[j]);
4562236b 2114
ab2541b6
AC		 2115 context->stream_status[i].surface_count = 0;
2116 dc_stream_release(&context->streams[i]->public);
2117 context->streams[i] = NULL;
4562236b
HW		 2118 }
2119}
2120
2121/*
ab2541b6 2122 * Copy src_ctx into dst_ctx and retain all surfaces and streams referenced
4562236b
HW		 2123 * by the src_ctx
2124 */
8122a253 2125void dc_resource_validate_ctx_copy_construct(
4562236b
HW		 2126 const struct validate_context *src_ctx,
2127 struct validate_context *dst_ctx)
2128{
2129 int i, j;
2130
2131 *dst_ctx = *src_ctx;
2132
a2b8659d 2133 for (i = 0; i < MAX_PIPES; i++) {
4562236b
HW		 2134 struct pipe_ctx *cur_pipe = &dst_ctx->res_ctx.pipe_ctx[i];
2135
2136 if (cur_pipe->top_pipe)
2137 cur_pipe->top_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
2138
2139 if (cur_pipe->bottom_pipe)
2140 cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
2141
2142 }
2143
ab2541b6
AC		 2144 for (i = 0; i < dst_ctx->stream_count; i++) {
2145 dc_stream_retain(&dst_ctx->streams[i]->public);
2146 for (j = 0; j < dst_ctx->stream_status[i].surface_count; j++)
4562236b 2147 dc_surface_retain(
ab2541b6 2148 dst_ctx->stream_status[i].surfaces[j]);
4562236b
HW		 2149 }
2150}
2151
2152struct clock_source *dc_resource_find_first_free_pll(
a2b8659d
TC		 2153 struct resource_context *res_ctx,
2154 const struct resource_pool *pool)
4562236b
HW		 2155{
2156 int i;
2157
a2b8659d 2158 for (i = 0; i < pool->clk_src_count; ++i) {
4562236b 2159 if (res_ctx->clock_source_ref_count[i] == 0)
a2b8659d 2160 return pool->clock_sources[i];
4562236b
HW		 2161 }
2162
2163 return NULL;
2164}
2165
2166void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
2167{
2168 enum signal_type signal = SIGNAL_TYPE_NONE;
6e4d6bee 2169 struct encoder_info_frame *info = &pipe_ctx->encoder_info_frame;
4562236b
HW		 2170
2171 /* default all packets to invalid */
6e4d6bee
TC		 2172 info->avi.valid = false;
2173 info->gamut.valid = false;
2174 info->vendor.valid = false;
2175 info->hdrsmd.valid = false;
2176 info->vsc.valid = false;
4562236b
HW		 2177
2178 signal = pipe_ctx->stream->signal;
2179
2180 /* HDMi and DP have different info packets*/
2181 if (dc_is_hdmi_signal(signal)) {
6e4d6bee
TC		 2182 set_avi_info_frame(&info->avi, pipe_ctx);
2183
2184 set_vendor_info_packet(&info->vendor, pipe_ctx->stream);
2185
2186 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2187
2188 set_hdr_static_info_packet(&info->hdrsmd,
2189 pipe_ctx->surface, pipe_ctx->stream);
2190
a33fa99d 2191 } else if (dc_is_dp_signal(signal)) {
6e4d6bee
TC		 2192 set_vsc_info_packet(&info->vsc, pipe_ctx->stream);
2193
2194 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2195
2196 set_hdr_static_info_packet(&info->hdrsmd,
2197 pipe_ctx->surface, pipe_ctx->stream);
a33fa99d 2198 }
4562236b 2199
6e4d6bee 2200 patch_gamut_packet_checksum(&info->gamut);
4562236b
HW		 2201}
2202
2203enum dc_status resource_map_clock_resources(
2204 const struct core_dc *dc,
430ef426
DL		 2205 struct validate_context *context,
2206 struct validate_context *old_context)
4562236b 2207{
ab2541b6 2208 int i, j;
a2b8659d 2209 const struct resource_pool *pool = dc->res_pool;
4562236b
HW		 2210
2211 /* acquire new resources */
ab2541b6
AC		 2212 for (i = 0; i < context->stream_count; i++) {
2213 const struct core_stream *stream = context->streams[i];
4562236b 2214
430ef426 2215 if (old_context && resource_is_stream_unchanged(old_context, stream))
ab2541b6
AC		 2216 continue;
2217
2218 for (j = 0; j < MAX_PIPES; j++) {
2219 struct pipe_ctx *pipe_ctx =
2220 &context->res_ctx.pipe_ctx[j];
4562236b 2221
ab2541b6 2222 if (context->res_ctx.pipe_ctx[j].stream != stream)
4562236b
HW		 2223 continue;
2224
ab2541b6
AC		 2225 if (dc_is_dp_signal(pipe_ctx->stream->signal)
2226 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)
a2b8659d 2227 pipe_ctx->clock_source = pool->dp_clock_source;
ab2541b6
AC		 2228 else {
2229 pipe_ctx->clock_source = NULL;
4562236b 2230
ab2541b6
AC		 2231 if (!dc->public.config.disable_disp_pll_sharing)
2232 resource_find_used_clk_src_for_sharing(
2233 &context->res_ctx,
2234 pipe_ctx);
4562236b 2235
ab2541b6 2236 if (pipe_ctx->clock_source == NULL)
4562236b 2237 pipe_ctx->clock_source =
a2b8659d
TC		 2238 dc_resource_find_first_free_pll(
2239 &context->res_ctx,
2240 pool);
ab2541b6 2241 }
4562236b 2242
ab2541b6
AC		 2243 if (pipe_ctx->clock_source == NULL)
2244 return DC_NO_CLOCK_SOURCE_RESOURCE;
4562236b 2245
ab2541b6 2246 resource_reference_clock_source(
a2b8659d 2247 &context->res_ctx, pool,
ab2541b6 2248 pipe_ctx->clock_source);
4562236b 2249
ab2541b6
AC		 2250 /* only one cs per stream regardless of mpo */
2251 break;
4562236b
HW		 2252 }
2253 }
2254
2255 return DC_OK;
2256}
2257
2258/*
2259 * Note: We need to disable output if clock sources change,
2260 * since bios does optimization and doesn't apply if changing
2261 * PHY when not already disabled.
2262 */
2263bool pipe_need_reprogram(
2264 struct pipe_ctx *pipe_ctx_old,
2265 struct pipe_ctx *pipe_ctx)
2266{
2267 if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink)
2268 return true;
2269
2270 if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal)
2271 return true;
2272
2273 if (pipe_ctx_old->audio != pipe_ctx->audio)
2274 return true;
2275
2276 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source
2277 && pipe_ctx_old->stream != pipe_ctx->stream)
2278 return true;
2279
2280 if (pipe_ctx_old->stream_enc != pipe_ctx->stream_enc)
2281 return true;
2282
2283 if (is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2284 return true;
2285
2286
2287 return false;
2288}
529cad0f
DW		 2289
2290void resource_build_bit_depth_reduction_params(const struct core_stream *stream,
2291 struct bit_depth_reduction_params *fmt_bit_depth)
2292{
2293 enum dc_dither_option option = stream->public.dither_option;
2294 enum dc_pixel_encoding pixel_encoding =
2295 stream->public.timing.pixel_encoding;
2296
2297 memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth));
2298
2299 if (option == DITHER_OPTION_DISABLE)
2300 return;
2301
2302 if (option == DITHER_OPTION_TRUN6) {
2303 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2304 fmt_bit_depth->flags.TRUNCATE_DEPTH = 0;
2305 } else if (option == DITHER_OPTION_TRUN8 ||
2306 option == DITHER_OPTION_TRUN8_SPATIAL6 ||
2307 option == DITHER_OPTION_TRUN8_FM6) {
2308 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2309 fmt_bit_depth->flags.TRUNCATE_DEPTH = 1;
2310 } else if (option == DITHER_OPTION_TRUN10 ||
2311 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
2312 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
2313 option == DITHER_OPTION_TRUN10_FM8 ||
2314 option == DITHER_OPTION_TRUN10_FM6 ||
2315 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2316 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2317 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2318 }
2319
2320 /* special case - Formatter can only reduce by 4 bits at most.
2321 * When reducing from 12 to 6 bits,
2322 * HW recommends we use trunc with round mode
2323 * (if we did nothing, trunc to 10 bits would be used)
2324 * note that any 12->10 bit reduction is ignored prior to DCE8,
2325 * as the input was 10 bits.
2326 */
2327 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2328 option == DITHER_OPTION_SPATIAL6 ||
2329 option == DITHER_OPTION_FM6) {
2330 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2331 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2332 fmt_bit_depth->flags.TRUNCATE_MODE = 1;
2333 }
2334
2335 /* spatial dither
2336 * note that spatial modes 1-3 are never used
2337 */
2338 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2339 option == DITHER_OPTION_SPATIAL6 ||
2340 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
2341 option == DITHER_OPTION_TRUN8_SPATIAL6) {
2342 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2343 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 0;
2344 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2345 fmt_bit_depth->flags.RGB_RANDOM =
2346 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2347 } else if (option == DITHER_OPTION_SPATIAL8_FRAME_RANDOM ||
2348 option == DITHER_OPTION_SPATIAL8 ||
2349 option == DITHER_OPTION_SPATIAL8_FM6 ||
2350 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
2351 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2352 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2353 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 1;
2354 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2355 fmt_bit_depth->flags.RGB_RANDOM =
2356 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2357 } else if (option == DITHER_OPTION_SPATIAL10_FRAME_RANDOM ||
2358 option == DITHER_OPTION_SPATIAL10 ||
2359 option == DITHER_OPTION_SPATIAL10_FM8 ||
2360 option == DITHER_OPTION_SPATIAL10_FM6) {
2361 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2362 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 2;
2363 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2364 fmt_bit_depth->flags.RGB_RANDOM =
2365 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2366 }
2367
2368 if (option == DITHER_OPTION_SPATIAL6 ||
2369 option == DITHER_OPTION_SPATIAL8 ||
2370 option == DITHER_OPTION_SPATIAL10) {
2371 fmt_bit_depth->flags.FRAME_RANDOM = 0;
2372 } else {
2373 fmt_bit_depth->flags.FRAME_RANDOM = 1;
2374 }
2375
2376 //////////////////////
2377 //// temporal dither
2378 //////////////////////
2379 if (option == DITHER_OPTION_FM6 ||
2380 option == DITHER_OPTION_SPATIAL8_FM6 ||
2381 option == DITHER_OPTION_SPATIAL10_FM6 ||
2382 option == DITHER_OPTION_TRUN10_FM6 ||
2383 option == DITHER_OPTION_TRUN8_FM6 ||
2384 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2385 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2386 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 0;
2387 } else if (option == DITHER_OPTION_FM8 ||
2388 option == DITHER_OPTION_SPATIAL10_FM8 ||
2389 option == DITHER_OPTION_TRUN10_FM8) {
2390 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2391 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 1;
2392 } else if (option == DITHER_OPTION_FM10) {
2393 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2394 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 2;
2395 }
2396
2397 fmt_bit_depth->pixel_encoding = pixel_encoding;
2398}
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