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drm/amd/display: Synchronous DisplayPort Link Training
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / display / dc / core / dc_resource.c
CommitLineData
4562236b 1/*
9ce6aae1 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4562236b
HW		 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
4fc4dca8
SR		 25
26#include <linux/slab.h>
27
4562236b
HW		 28#include "dm_services.h"
29
30#include "resource.h"
31#include "include/irq_service_interface.h"
32#include "link_encoder.h"
33#include "stream_encoder.h"
34#include "opp.h"
35#include "timing_generator.h"
36#include "transform.h"
33d7598d
JL		 37#include "dccg.h"
38#include "dchubbub.h"
d94585a0 39#include "dpp.h"
5ac3d3c9 40#include "core_types.h"
4562236b 41#include "set_mode_types.h"
4562236b 42#include "virtual/virtual_stream_encoder.h"
3b94a400 43#include "dpcd_defs.h"
4562236b
HW		 44
45#include "dce80/dce80_resource.h"
46#include "dce100/dce100_resource.h"
47#include "dce110/dce110_resource.h"
48#include "dce112/dce112_resource.h"
dc37a9a0 49#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
ff5ef992
AD		 50#include "dcn10/dcn10_resource.h"
51#endif
7ed4e635
HW		 52#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
53#include "dcn20/dcn20_resource.h"
54#endif
2c8ad2d5 55#include "dce120/dce120_resource.h"
5d4b05dd
BL		 56
57#define DC_LOGGER_INIT(logger)
58
4562236b
HW		 59enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
60{
61 enum dce_version dc_version = DCE_VERSION_UNKNOWN;
62 switch (asic_id.chip_family) {
63
64 case FAMILY_CI:
4562236b
HW		 65 dc_version = DCE_VERSION_8_0;
66 break;
ebfdf0d0
AD		 67 case FAMILY_KV:
68 if (ASIC_REV_IS_KALINDI(asic_id.hw_internal_rev) ||
69 ASIC_REV_IS_BHAVANI(asic_id.hw_internal_rev) ||
70 ASIC_REV_IS_GODAVARI(asic_id.hw_internal_rev))
71 dc_version = DCE_VERSION_8_3;
72 else
73 dc_version = DCE_VERSION_8_1;
74 break;
4562236b
HW		 75 case FAMILY_CZ:
76 dc_version = DCE_VERSION_11_0;
77 break;
78
79 case FAMILY_VI:
80 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
81 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
82 dc_version = DCE_VERSION_10_0;
83 break;
84 }
85 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
b264d345
JL		 86 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
87 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
4562236b
HW		 88 dc_version = DCE_VERSION_11_2;
89 }
0c75d5ac
JFZ		 90 if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev))
91 dc_version = DCE_VERSION_11_22;
4562236b 92 break;
2c8ad2d5 93 case FAMILY_AI:
b8b6ce89
LL		 94 if (ASICREV_IS_VEGA20_P(asic_id.hw_internal_rev))
95 dc_version = DCE_VERSION_12_1;
96 else
97 dc_version = DCE_VERSION_12_0;
2c8ad2d5 98 break;
dc37a9a0 99#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
ff5ef992
AD		 100 case FAMILY_RV:
101 dc_version = DCN_VERSION_1_0;
0e3d73f1
BL		 102 if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev))
103 dc_version = DCN_VERSION_1_01;
ff5ef992
AD		 104 break;
105#endif
7ed4e635
HW		 106
107#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
108 case FAMILY_NV:
109 dc_version = DCN_VERSION_2_0;
110 break;
111#endif
4562236b
HW		 112 default:
113 dc_version = DCE_VERSION_UNKNOWN;
114 break;
115 }
116 return dc_version;
117}
118
d9673c92
HW		 119struct resource_pool *dc_create_resource_pool(struct dc *dc,
120 const struct dc_init_data *init_data,
121 enum dce_version dc_version)
4562236b 122{
5ac3d3c9 123 struct resource_pool *res_pool = NULL;
4562236b
HW		 124
125 switch (dc_version) {
126 case DCE_VERSION_8_0:
7992a629 127 res_pool = dce80_create_resource_pool(
d9673c92 128 init_data->num_virtual_links, dc);
7992a629 129 break;
ebfdf0d0 130 case DCE_VERSION_8_1:
7992a629 131 res_pool = dce81_create_resource_pool(
d9673c92 132 init_data->num_virtual_links, dc);
7992a629 133 break;
ebfdf0d0 134 case DCE_VERSION_8_3:
7992a629 135 res_pool = dce83_create_resource_pool(
d9673c92 136 init_data->num_virtual_links, dc);
5ac3d3c9 137 break;
4562236b 138 case DCE_VERSION_10_0:
5ac3d3c9 139 res_pool = dce100_create_resource_pool(
d9673c92 140 init_data->num_virtual_links, dc);
5ac3d3c9 141 break;
4562236b 142 case DCE_VERSION_11_0:
5ac3d3c9 143 res_pool = dce110_create_resource_pool(
d9673c92
HW		 144 init_data->num_virtual_links, dc,
145 init_data->asic_id);
5ac3d3c9 146 break;
4562236b 147 case DCE_VERSION_11_2:
0c75d5ac 148 case DCE_VERSION_11_22:
5ac3d3c9 149 res_pool = dce112_create_resource_pool(
d9673c92 150 init_data->num_virtual_links, dc);
5ac3d3c9 151 break;
2c8ad2d5 152 case DCE_VERSION_12_0:
b8b6ce89 153 case DCE_VERSION_12_1:
2c8ad2d5 154 res_pool = dce120_create_resource_pool(
d9673c92 155 init_data->num_virtual_links, dc);
2c8ad2d5 156 break;
ff5ef992 157
dc37a9a0 158#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
ff5ef992 159 case DCN_VERSION_1_0:
0e3d73f1 160 case DCN_VERSION_1_01:
d9673c92 161 res_pool = dcn10_create_resource_pool(init_data, dc);
ff5ef992
AD		 162 break;
163#endif
3639fa68
ZF		 164
165
7ed4e635
HW		 166#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
167 case DCN_VERSION_2_0:
168 res_pool = dcn20_create_resource_pool(init_data, dc);
169 break;
170#endif
171
4562236b
HW		 172 default:
173 break;
174 }
5ac3d3c9 175 if (res_pool != NULL) {
1515a47b 176 struct dc_firmware_info fw_info = { { 0 } };
5ac3d3c9 177
41a5a2a8 178 if (dc->ctx->dc_bios->funcs->get_firmware_info(dc->ctx->dc_bios,
179 &fw_info) == BP_RESULT_OK) {
180 res_pool->ref_clocks.xtalin_clock_inKhz =
181 fw_info.pll_info.crystal_frequency;
182 /* initialize with firmware data first, no all
183 * ASIC have DCCG SW component. FPGA or
184 * simulation need initialization of
185 * dccg_ref_clock_inKhz, dchub_ref_clock_inKhz
186 * with xtalin_clock_inKhz
187 */
188 res_pool->ref_clocks.dccg_ref_clock_inKhz =
189 res_pool->ref_clocks.xtalin_clock_inKhz;
190 res_pool->ref_clocks.dchub_ref_clock_inKhz =
191 res_pool->ref_clocks.xtalin_clock_inKhz;
192 } else
193 ASSERT_CRITICAL(false);
5ac3d3c9 194 }
4562236b 195
5ac3d3c9 196 return res_pool;
4562236b
HW		 197}
198
fb3466a4 199void dc_destroy_resource_pool(struct dc *dc)
4562236b
HW		 200{
201 if (dc) {
202 if (dc->res_pool)
203 dc->res_pool->funcs->destroy(&dc->res_pool);
204
d029810c 205 kfree(dc->hwseq);
4562236b
HW		 206 }
207}
208
209static void update_num_audio(
210 const struct resource_straps *straps,
211 unsigned int *num_audio,
212 struct audio_support *aud_support)
213{
b8e9eb72
CL		 214 aud_support->dp_audio = true;
215 aud_support->hdmi_audio_native = false;
216 aud_support->hdmi_audio_on_dongle = false;
217
4562236b 218 if (straps->hdmi_disable == 0) {
4562236b
HW		 219 if (straps->dc_pinstraps_audio & 0x2) {
220 aud_support->hdmi_audio_on_dongle = true;
b8e9eb72 221 aud_support->hdmi_audio_native = true;
4562236b
HW		 222 }
223 }
224
225 switch (straps->audio_stream_number) {
226 case 0: /* multi streams supported */
227 break;
228 case 1: /* multi streams not supported */
229 *num_audio = 1;
230 break;
231 default:
232 DC_ERR("DC: unexpected audio fuse!\n");
17a96033 233 }
4562236b
HW		 234}
235
236bool resource_construct(
237 unsigned int num_virtual_links,
fb3466a4 238 struct dc *dc,
4562236b
HW		 239 struct resource_pool *pool,
240 const struct resource_create_funcs *create_funcs)
241{
242 struct dc_context *ctx = dc->ctx;
243 const struct resource_caps *caps = pool->res_cap;
244 int i;
245 unsigned int num_audio = caps->num_audio;
246 struct resource_straps straps = {0};
247
248 if (create_funcs->read_dce_straps)
249 create_funcs->read_dce_straps(dc->ctx, &straps);
250
251 pool->audio_count = 0;
252 if (create_funcs->create_audio) {
253 /* find the total number of streams available via the
254 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
255 * registers (one for each pin) starting from pin 1
256 * up to the max number of audio pins.
257 * We stop on the first pin where
258 * PORT_CONNECTIVITY == 1 (as instructed by HW team).
259 */
260 update_num_audio(&straps, &num_audio, &pool->audio_support);
5feb9f07 261 for (i = 0; i < caps->num_audio; i++) {
4562236b
HW		 262 struct audio *aud = create_funcs->create_audio(ctx, i);
263
264 if (aud == NULL) {
265 DC_ERR("DC: failed to create audio!\n");
266 return false;
267 }
268
269 if (!aud->funcs->endpoint_valid(aud)) {
270 aud->funcs->destroy(&aud);
271 break;
272 }
273
274 pool->audios[i] = aud;
275 pool->audio_count++;
276 }
277 }
278
279 pool->stream_enc_count = 0;
280 if (create_funcs->create_stream_encoder) {
281 for (i = 0; i < caps->num_stream_encoder; i++) {
282 pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx);
283 if (pool->stream_enc[i] == NULL)
284 DC_ERR("DC: failed to create stream_encoder!\n");
285 pool->stream_enc_count++;
286 }
287 }
929c3aaa 288
4176664b
CL		 289 dc->caps.dynamic_audio = false;
290 if (pool->audio_count < pool->stream_enc_count) {
291 dc->caps.dynamic_audio = true;
292 }
4562236b
HW		 293 for (i = 0; i < num_virtual_links; i++) {
294 pool->stream_enc[pool->stream_enc_count] =
295 virtual_stream_encoder_create(
296 ctx, ctx->dc_bios);
297 if (pool->stream_enc[pool->stream_enc_count] == NULL) {
298 DC_ERR("DC: failed to create stream_encoder!\n");
299 return false;
300 }
301 pool->stream_enc_count++;
302 }
303
304 dc->hwseq = create_funcs->create_hwseq(ctx);
305
306 return true;
307}
ad8960a6
ML		 308static int find_matching_clock_source(
309 const struct resource_pool *pool,
310 struct clock_source *clock_source)
311{
4562236b 312
ad8960a6
ML		 313 int i;
314
315 for (i = 0; i < pool->clk_src_count; i++) {
316 if (pool->clock_sources[i] == clock_source)
317 return i;
318 }
319 return -1;
320}
4562236b 321
21e67d4d 322void resource_unreference_clock_source(
4562236b 323 struct resource_context *res_ctx,
a2b8659d 324 const struct resource_pool *pool,
4a629536 325 struct clock_source *clock_source)
4562236b 326{
ad8960a6 327 int i = find_matching_clock_source(pool, clock_source);
4562236b 328
ad8960a6 329 if (i > -1)
4562236b
HW		 330 res_ctx->clock_source_ref_count[i]--;
331
21e67d4d 332 if (pool->dp_clock_source == clock_source)
4562236b 333 res_ctx->dp_clock_source_ref_count--;
4562236b
HW		 334}
335
336void resource_reference_clock_source(
337 struct resource_context *res_ctx,
a2b8659d 338 const struct resource_pool *pool,
4562236b
HW		 339 struct clock_source *clock_source)
340{
ad8960a6 341 int i = find_matching_clock_source(pool, clock_source);
4562236b 342
ad8960a6 343 if (i > -1)
4562236b 344 res_ctx->clock_source_ref_count[i]++;
4562236b 345
a2b8659d 346 if (pool->dp_clock_source == clock_source)
4562236b
HW		 347 res_ctx->dp_clock_source_ref_count++;
348}
349
ad8960a6
ML		 350int resource_get_clock_source_reference(
351 struct resource_context *res_ctx,
352 const struct resource_pool *pool,
353 struct clock_source *clock_source)
354{
355 int i = find_matching_clock_source(pool, clock_source);
356
357 if (i > -1)
358 return res_ctx->clock_source_ref_count[i];
359
360 if (pool->dp_clock_source == clock_source)
361 return res_ctx->dp_clock_source_ref_count;
362
363 return -1;
364}
365
4562236b 366bool resource_are_streams_timing_synchronizable(
0971c40e
HW		 367 struct dc_stream_state *stream1,
368 struct dc_stream_state *stream2)
4562236b 369{
4fa086b9 370 if (stream1->timing.h_total != stream2->timing.h_total)
4562236b
HW		 371 return false;
372
4fa086b9 373 if (stream1->timing.v_total != stream2->timing.v_total)
4562236b
HW		 374 return false;
375
4fa086b9
LSL		 376 if (stream1->timing.h_addressable
377 != stream2->timing.h_addressable)
4562236b
HW		 378 return false;
379
4fa086b9
LSL		 380 if (stream1->timing.v_addressable
381 != stream2->timing.v_addressable)
4562236b
HW		 382 return false;
383
380604e2
KC		 384 if (stream1->timing.pix_clk_100hz
385 != stream2->timing.pix_clk_100hz)
4562236b
HW		 386 return false;
387
3e27e10e
ML		 388 if (stream1->clamping.c_depth != stream2->clamping.c_depth)
389 return false;
390
4562236b 391 if (stream1->phy_pix_clk != stream2->phy_pix_clk
7e2fe319
CL		 392 && (!dc_is_dp_signal(stream1->signal)
393 || !dc_is_dp_signal(stream2->signal)))
4562236b
HW		 394 return false;
395
d77f778e
CL		 396 if (stream1->view_format != stream2->view_format)
397 return false;
398
4562236b
HW		 399 return true;
400}
3e27e10e
ML		 401static bool is_dp_and_hdmi_sharable(
402 struct dc_stream_state *stream1,
403 struct dc_stream_state *stream2)
404{
405 if (stream1->ctx->dc->caps.disable_dp_clk_share)
406 return false;
407
408 if (stream1->clamping.c_depth != COLOR_DEPTH_888 ||
d77f778e 409 stream2->clamping.c_depth != COLOR_DEPTH_888)
43fbbe89 410 return false;
3e27e10e
ML		 411
412 return true;
413
414}
4562236b
HW		 415
416static bool is_sharable_clk_src(
417 const struct pipe_ctx *pipe_with_clk_src,
418 const struct pipe_ctx *pipe)
419{
420 if (pipe_with_clk_src->clock_source == NULL)
421 return false;
422
423 if (pipe_with_clk_src->stream->signal == SIGNAL_TYPE_VIRTUAL)
424 return false;
425
3e27e10e
ML		 426 if (dc_is_dp_signal(pipe_with_clk_src->stream->signal) ||
427 (dc_is_dp_signal(pipe->stream->signal) &&
428 !is_dp_and_hdmi_sharable(pipe_with_clk_src->stream,
429 pipe->stream)))
4562236b
HW		 430 return false;
431
432 if (dc_is_hdmi_signal(pipe_with_clk_src->stream->signal)
fc69009e 433 && dc_is_dual_link_signal(pipe->stream->signal))
4562236b
HW		 434 return false;
435
436 if (dc_is_hdmi_signal(pipe->stream->signal)
fc69009e 437 && dc_is_dual_link_signal(pipe_with_clk_src->stream->signal))
4562236b
HW		 438 return false;
439
440 if (!resource_are_streams_timing_synchronizable(
441 pipe_with_clk_src->stream, pipe->stream))
442 return false;
443
444 return true;
445}
446
447struct clock_source *resource_find_used_clk_src_for_sharing(
448 struct resource_context *res_ctx,
449 struct pipe_ctx *pipe_ctx)
450{
451 int i;
452
453 for (i = 0; i < MAX_PIPES; i++) {
454 if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx))
455 return res_ctx->pipe_ctx[i].clock_source;
456 }
457
458 return NULL;
459}
460
461static enum pixel_format convert_pixel_format_to_dalsurface(
462 enum surface_pixel_format surface_pixel_format)
463{
464 enum pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
465
466 switch (surface_pixel_format) {
467 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
468 dal_pixel_format = PIXEL_FORMAT_INDEX8;
469 break;
470 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
471 dal_pixel_format = PIXEL_FORMAT_RGB565;
472 break;
473 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
474 dal_pixel_format = PIXEL_FORMAT_RGB565;
475 break;
476 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
477 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
478 break;
8693049a 479 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
4562236b
HW		 480 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
481 break;
482 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
483 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
484 break;
485 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
486 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
487 break;
488 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
489 dal_pixel_format = PIXEL_FORMAT_ARGB2101010_XRBIAS;
490 break;
491 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
492 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
493 dal_pixel_format = PIXEL_FORMAT_FP16;
494 break;
495 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
4562236b 496 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
87449a90 497 dal_pixel_format = PIXEL_FORMAT_420BPP8;
4562236b 498 break;
ffbcd19a
VP		 499 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
500 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
87449a90 501 dal_pixel_format = PIXEL_FORMAT_420BPP10;
ffbcd19a 502 break;
4562236b
HW		 503 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
504 default:
505 dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
506 break;
507 }
508 return dal_pixel_format;
509}
510
9b6067c0
DL		 511static inline void get_vp_scan_direction(
512 enum dc_rotation_angle rotation,
513 bool horizontal_mirror,
514 bool *orthogonal_rotation,
515 bool *flip_vert_scan_dir,
516 bool *flip_horz_scan_dir)
4562236b 517{
9b6067c0
DL		 518 *orthogonal_rotation = false;
519 *flip_vert_scan_dir = false;
520 *flip_horz_scan_dir = false;
521 if (rotation == ROTATION_ANGLE_180) {
522 *flip_vert_scan_dir = true;
523 *flip_horz_scan_dir = true;
524 } else if (rotation == ROTATION_ANGLE_90) {
525 *orthogonal_rotation = true;
526 *flip_horz_scan_dir = true;
527 } else if (rotation == ROTATION_ANGLE_270) {
528 *orthogonal_rotation = true;
529 *flip_vert_scan_dir = true;
530 }
531
532 if (horizontal_mirror)
533 *flip_horz_scan_dir = !*flip_horz_scan_dir;
4562236b
HW		 534}
535
b2d0a103 536static void calculate_viewport(struct pipe_ctx *pipe_ctx)
4562236b 537{
3be5262e 538 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 539 const struct dc_stream_state *stream = pipe_ctx->stream;
6702a9ac 540 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
3be5262e 541 struct rect surf_src = plane_state->src_rect;
9b6067c0 542 struct rect clip, dest;
87449a90
AK		 543 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
544 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
1fbd2cfc 545 bool pri_split = pipe_ctx->bottom_pipe &&
3be5262e 546 pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state;
1fbd2cfc 547 bool sec_split = pipe_ctx->top_pipe &&
3be5262e 548 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
9b6067c0 549 bool orthogonal_rotation, flip_y_start, flip_x_start;
83d40659 550
7f5c22d1
VP		 551 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE ||
552 stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) {
7b779c99
VP		 553 pri_split = false;
554 sec_split = false;
555 }
86006a7f 556
4562236b
HW		 557 /* The actual clip is an intersection between stream
558 * source and surface clip
559 */
9b6067c0 560 dest = plane_state->dst_rect;
3be5262e
HW		 561 clip.x = stream->src.x > plane_state->clip_rect.x ?
562 stream->src.x : plane_state->clip_rect.x;
4562236b 563
1fbd2cfc 564 clip.width = stream->src.x + stream->src.width <
3be5262e 565 plane_state->clip_rect.x + plane_state->clip_rect.width ?
1fbd2cfc 566 stream->src.x + stream->src.width - clip.x :
3be5262e 567 plane_state->clip_rect.x + plane_state->clip_rect.width - clip.x ;
4562236b 568
3be5262e
HW		 569 clip.y = stream->src.y > plane_state->clip_rect.y ?
570 stream->src.y : plane_state->clip_rect.y;
4562236b 571
1fbd2cfc 572 clip.height = stream->src.y + stream->src.height <
3be5262e 573 plane_state->clip_rect.y + plane_state->clip_rect.height ?
1fbd2cfc 574 stream->src.y + stream->src.height - clip.y :
3be5262e 575 plane_state->clip_rect.y + plane_state->clip_rect.height - clip.y ;
4562236b 576
9b6067c0
DL		 577 /*
578 * Need to calculate how scan origin is shifted in vp space
579 * to correctly rotate clip and dst
580 */
581 get_vp_scan_direction(
582 plane_state->rotation,
583 plane_state->horizontal_mirror,
584 &orthogonal_rotation,
585 &flip_y_start,
586 &flip_x_start);
587
588 if (orthogonal_rotation) {
589 swap(clip.x, clip.y);
590 swap(clip.width, clip.height);
591 swap(dest.x, dest.y);
592 swap(dest.width, dest.height);
593 }
594 if (flip_x_start) {
595 clip.x = dest.x + dest.width - clip.x - clip.width;
596 dest.x = 0;
597 }
598 if (flip_y_start) {
599 clip.y = dest.y + dest.height - clip.y - clip.height;
600 dest.y = 0;
601 }
602
86006a7f 603 /* offset = surf_src.ofs + (clip.ofs - surface->dst_rect.ofs) * scl_ratio
4562236b
HW		 604 * num_pixels = clip.num_pix * scl_ratio
605 */
9b6067c0
DL		 606 data->viewport.x = surf_src.x + (clip.x - dest.x) * surf_src.width / dest.width;
607 data->viewport.width = clip.width * surf_src.width / dest.width;
608
609 data->viewport.y = surf_src.y + (clip.y - dest.y) * surf_src.height / dest.height;
610 data->viewport.height = clip.height * surf_src.height / dest.height;
611
612 /* Handle split */
613 if (pri_split || sec_split) {
614 if (orthogonal_rotation) {
615 if (flip_y_start != pri_split)
616 data->viewport.height /= 2;
617 else {
618 data->viewport.y += data->viewport.height / 2;
619 /* Ceil offset pipe */
620 data->viewport.height = (data->viewport.height + 1) / 2;
621 }
622 } else {
623 if (flip_x_start != pri_split)
624 data->viewport.width /= 2;
625 else {
626 data->viewport.x += data->viewport.width / 2;
627 /* Ceil offset pipe */
628 data->viewport.width = (data->viewport.width + 1) / 2;
629 }
630 }
631 }
9b5349f7 632
b2d0a103
DL		 633 /* Round down, compensate in init */
634 data->viewport_c.x = data->viewport.x / vpc_div;
635 data->viewport_c.y = data->viewport.y / vpc_div;
9b6067c0
DL		 636 data->inits.h_c = (data->viewport.x % vpc_div) != 0 ? dc_fixpt_half : dc_fixpt_zero;
637 data->inits.v_c = (data->viewport.y % vpc_div) != 0 ? dc_fixpt_half : dc_fixpt_zero;
638
b2d0a103
DL		 639 /* Round up, assume original video size always even dimensions */
640 data->viewport_c.width = (data->viewport.width + vpc_div - 1) / vpc_div;
641 data->viewport_c.height = (data->viewport.height + vpc_div - 1) / vpc_div;
4562236b
HW		 642}
643
9b6067c0 644static void calculate_recout(struct pipe_ctx *pipe_ctx)
4562236b 645{
3be5262e 646 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 647 const struct dc_stream_state *stream = pipe_ctx->stream;
3be5262e 648 struct rect surf_clip = plane_state->clip_rect;
0c31a821
YS		 649 bool pri_split = pipe_ctx->bottom_pipe &&
650 pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state;
651 bool sec_split = pipe_ctx->top_pipe &&
652 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
b0131391 653 bool top_bottom_split = stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM;
4562236b 654
6702a9ac 655 pipe_ctx->plane_res.scl_data.recout.x = stream->dst.x;
4fa086b9 656 if (stream->src.x < surf_clip.x)
6702a9ac 657 pipe_ctx->plane_res.scl_data.recout.x += (surf_clip.x
4fa086b9
LSL		 658 - stream->src.x) * stream->dst.width
659 / stream->src.width;
4562236b 660
6702a9ac 661 pipe_ctx->plane_res.scl_data.recout.width = surf_clip.width *
4fa086b9 662 stream->dst.width / stream->src.width;
6702a9ac 663 if (pipe_ctx->plane_res.scl_data.recout.width + pipe_ctx->plane_res.scl_data.recout.x >
4fa086b9 664 stream->dst.x + stream->dst.width)
6702a9ac 665 pipe_ctx->plane_res.scl_data.recout.width =
4fa086b9 666 stream->dst.x + stream->dst.width
6702a9ac 667 - pipe_ctx->plane_res.scl_data.recout.x;
4562236b 668
6702a9ac 669 pipe_ctx->plane_res.scl_data.recout.y = stream->dst.y;
4fa086b9 670 if (stream->src.y < surf_clip.y)
6702a9ac 671 pipe_ctx->plane_res.scl_data.recout.y += (surf_clip.y
4fa086b9
LSL		 672 - stream->src.y) * stream->dst.height
673 / stream->src.height;
4562236b 674
6702a9ac 675 pipe_ctx->plane_res.scl_data.recout.height = surf_clip.height *
4fa086b9 676 stream->dst.height / stream->src.height;
6702a9ac 677 if (pipe_ctx->plane_res.scl_data.recout.height + pipe_ctx->plane_res.scl_data.recout.y >
4fa086b9 678 stream->dst.y + stream->dst.height)
6702a9ac 679 pipe_ctx->plane_res.scl_data.recout.height =
4fa086b9 680 stream->dst.y + stream->dst.height
6702a9ac 681 - pipe_ctx->plane_res.scl_data.recout.y;
b2d0a103 682
9b6067c0 683 /* Handle h & v split, handle rotation using viewport */
b0131391
DL		 684 if (sec_split && top_bottom_split) {
685 pipe_ctx->plane_res.scl_data.recout.y +=
686 pipe_ctx->plane_res.scl_data.recout.height / 2;
0c31a821 687 /* Floor primary pipe, ceil 2ndary pipe */
b0131391
DL		 688 pipe_ctx->plane_res.scl_data.recout.height =
689 (pipe_ctx->plane_res.scl_data.recout.height + 1) / 2;
690 } else if (pri_split && top_bottom_split)
0c31a821 691 pipe_ctx->plane_res.scl_data.recout.height /= 2;
9b6067c0
DL		 692 else if (sec_split) {
693 pipe_ctx->plane_res.scl_data.recout.x +=
694 pipe_ctx->plane_res.scl_data.recout.width / 2;
695 /* Ceil offset pipe */
696 pipe_ctx->plane_res.scl_data.recout.width =
697 (pipe_ctx->plane_res.scl_data.recout.width + 1) / 2;
698 } else if (pri_split)
699 pipe_ctx->plane_res.scl_data.recout.width /= 2;
4562236b
HW		 700}
701
b2d0a103 702static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)
4562236b 703{
3be5262e 704 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 705 const struct dc_stream_state *stream = pipe_ctx->stream;
3be5262e 706 struct rect surf_src = plane_state->src_rect;
4fa086b9
LSL		 707 const int in_w = stream->src.width;
708 const int in_h = stream->src.height;
709 const int out_w = stream->dst.width;
710 const int out_h = stream->dst.height;
4562236b 711
9b6067c0 712 /*Swap surf_src height and width since scaling ratios are in recout rotation*/
3be5262e
HW		 713 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
714 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
9b6067c0 715 swap(surf_src.height, surf_src.width);
86006a7f 716
eb0e5154 717 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_from_fraction(
86006a7f 718 surf_src.width,
3be5262e 719 plane_state->dst_rect.width);
eb0e5154 720 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction(
86006a7f 721 surf_src.height,
3be5262e 722 plane_state->dst_rect.height);
4562236b 723
4fa086b9 724 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
6702a9ac 725 pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2;
4fa086b9 726 else if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
6702a9ac 727 pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2;
4562236b 728
6702a9ac
HW		 729 pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64(
730 pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h);
731 pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64(
732 pipe_ctx->plane_res.scl_data.ratios.horz.value * in_w, out_w);
4562236b 733
6702a9ac
HW		 734 pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz;
735 pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert;
4562236b 736
6702a9ac
HW		 737 if (pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP8
738 || pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP10) {
739 pipe_ctx->plane_res.scl_data.ratios.horz_c.value /= 2;
740 pipe_ctx->plane_res.scl_data.ratios.vert_c.value /= 2;
4562236b 741 }
0002d3ac
DL		 742 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_truncate(
743 pipe_ctx->plane_res.scl_data.ratios.horz, 19);
744 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_truncate(
745 pipe_ctx->plane_res.scl_data.ratios.vert, 19);
746 pipe_ctx->plane_res.scl_data.ratios.horz_c = dc_fixpt_truncate(
747 pipe_ctx->plane_res.scl_data.ratios.horz_c, 19);
748 pipe_ctx->plane_res.scl_data.ratios.vert_c = dc_fixpt_truncate(
749 pipe_ctx->plane_res.scl_data.ratios.vert_c, 19);
4562236b
HW		 750}
751
9b6067c0
DL		 752static inline void adjust_vp_and_init_for_seamless_clip(
753 bool flip_scan_dir,
754 int recout_skip,
755 int src_size,
756 int taps,
757 struct fixed31_32 ratio,
758 struct fixed31_32 *init,
759 int *vp_offset,
760 int *vp_size)
b2d0a103 761{
9b6067c0 762 if (!flip_scan_dir) {
9a08f51f 763 /* Adjust for viewport end clip-off */
9b6067c0
DL		 764 if ((*vp_offset + *vp_size) < src_size) {
765 int vp_clip = src_size - *vp_size - *vp_offset;
766 int int_part = dc_fixpt_floor(dc_fixpt_sub(*init, ratio));
9a08f51f
DL		 767
768 int_part = int_part > 0 ? int_part : 0;
9b6067c0 769 *vp_size += int_part < vp_clip ? int_part : vp_clip;
9a08f51f 770 }
b2d0a103 771
9a08f51f 772 /* Adjust for non-0 viewport offset */
9b6067c0 773 if (*vp_offset) {
9a08f51f
DL		 774 int int_part;
775
9b6067c0
DL		 776 *init = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_skip));
777 int_part = dc_fixpt_floor(*init) - *vp_offset;
778 if (int_part < taps) {
779 int int_adj = *vp_offset >= (taps - int_part) ?
780 (taps - int_part) : *vp_offset;
781 *vp_offset -= int_adj;
782 *vp_size += int_adj;
9a08f51f 783 int_part += int_adj;
9b6067c0
DL		 784 } else if (int_part > taps) {
785 *vp_offset += int_part - taps;
786 *vp_size -= int_part - taps;
787 int_part = taps;
9a08f51f 788 }
9b6067c0
DL		 789 init->value &= 0xffffffff;
790 *init = dc_fixpt_add_int(*init, int_part);
9a08f51f
DL		 791 }
792 } else {
793 /* Adjust for non-0 viewport offset */
9b6067c0
DL		 794 if (*vp_offset) {
795 int int_part = dc_fixpt_floor(dc_fixpt_sub(*init, ratio));
b2d0a103 796
9a08f51f 797 int_part = int_part > 0 ? int_part : 0;
9b6067c0
DL		 798 *vp_size += int_part < *vp_offset ? int_part : *vp_offset;
799 *vp_offset -= int_part < *vp_offset ? int_part : *vp_offset;
9a08f51f 800 }
b2d0a103 801
9a08f51f 802 /* Adjust for viewport end clip-off */
9b6067c0 803 if ((*vp_offset + *vp_size) < src_size) {
9a08f51f 804 int int_part;
9b6067c0 805 int end_offset = src_size - *vp_offset - *vp_size;
9a08f51f
DL		 806
807 /*
808 * this is init if vp had no offset, keep in mind this is from the
809 * right side of vp due to scan direction
810 */
9b6067c0 811 *init = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_skip));
9a08f51f
DL		 812 /*
813 * this is the difference between first pixel of viewport available to read
814 * and init position, takning into account scan direction
815 */
9b6067c0
DL		 816 int_part = dc_fixpt_floor(*init) - end_offset;
817 if (int_part < taps) {
818 int int_adj = end_offset >= (taps - int_part) ?
819 (taps - int_part) : end_offset;
820 *vp_size += int_adj;
9a08f51f 821 int_part += int_adj;
9b6067c0
DL		 822 } else if (int_part > taps) {
823 *vp_size += int_part - taps;
824 int_part = taps;
9a08f51f 825 }
9b6067c0
DL		 826 init->value &= 0xffffffff;
827 *init = dc_fixpt_add_int(*init, int_part);
b2d0a103 828 }
b2d0a103 829 }
9b6067c0 830}
9a08f51f 831
9b6067c0
DL		 832static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx)
833{
834 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
835 const struct dc_stream_state *stream = pipe_ctx->stream;
836 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
837 struct rect src = pipe_ctx->plane_state->src_rect;
838 int recout_skip_h, recout_skip_v, surf_size_h, surf_size_v;
839 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
840 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
841 bool orthogonal_rotation, flip_vert_scan_dir, flip_horz_scan_dir;
9a08f51f 842
9b6067c0
DL		 843 /*
844 * Need to calculate the scan direction for viewport to make adjustments
845 */
846 get_vp_scan_direction(
847 plane_state->rotation,
848 plane_state->horizontal_mirror,
849 &orthogonal_rotation,
850 &flip_vert_scan_dir,
851 &flip_horz_scan_dir);
852
853 /* Calculate src rect rotation adjusted to recout space */
854 surf_size_h = src.x + src.width;
855 surf_size_v = src.y + src.height;
856 if (flip_horz_scan_dir)
857 src.x = 0;
858 if (flip_vert_scan_dir)
859 src.y = 0;
860 if (orthogonal_rotation) {
861 swap(src.x, src.y);
862 swap(src.width, src.height);
863 }
9a08f51f 864
9b6067c0
DL		 865 /* Recout matching initial vp offset = recout_offset - (stream dst offset +
866 * ((surf dst offset - stream src offset) * 1/ stream scaling ratio)
867 * - (surf surf_src offset * 1/ full scl ratio))
868 */
869 recout_skip_h = data->recout.x - (stream->dst.x + (plane_state->dst_rect.x - stream->src.x)
870 * stream->dst.width / stream->src.width -
871 src.x * plane_state->dst_rect.width / src.width
872 * stream->dst.width / stream->src.width);
873 recout_skip_v = data->recout.y - (stream->dst.y + (plane_state->dst_rect.y - stream->src.y)
874 * stream->dst.height / stream->src.height -
875 src.y * plane_state->dst_rect.height / src.height
876 * stream->dst.height / stream->src.height);
877 if (orthogonal_rotation)
878 swap(recout_skip_h, recout_skip_v);
879 /*
880 * Init calculated according to formula:
881 * init = (scaling_ratio + number_of_taps + 1) / 2
882 * init_bot = init + scaling_ratio
883 * init_c = init + truncated_vp_c_offset(from calculate viewport)
884 */
885 data->inits.h = dc_fixpt_truncate(dc_fixpt_div_int(
886 dc_fixpt_add_int(data->ratios.horz, data->taps.h_taps + 1), 2), 19);
b2d0a103 887
9b6067c0
DL		 888 data->inits.h_c = dc_fixpt_truncate(dc_fixpt_add(data->inits.h_c, dc_fixpt_div_int(
889 dc_fixpt_add_int(data->ratios.horz_c, data->taps.h_taps_c + 1), 2)), 19);
9a08f51f 890
9b6067c0
DL		 891 data->inits.v = dc_fixpt_truncate(dc_fixpt_div_int(
892 dc_fixpt_add_int(data->ratios.vert, data->taps.v_taps + 1), 2), 19);
9a08f51f 893
9b6067c0
DL		 894 data->inits.v_c = dc_fixpt_truncate(dc_fixpt_add(data->inits.v_c, dc_fixpt_div_int(
895 dc_fixpt_add_int(data->ratios.vert_c, data->taps.v_taps_c + 1), 2)), 19);
9a08f51f 896
9b6067c0
DL		 897 /*
898 * Taps, inits and scaling ratios are in recout space need to rotate
899 * to viewport rotation before adjustment
900 */
901 adjust_vp_and_init_for_seamless_clip(
902 flip_horz_scan_dir,
903 recout_skip_h,
904 surf_size_h,
905 orthogonal_rotation ? data->taps.v_taps : data->taps.h_taps,
906 orthogonal_rotation ? data->ratios.vert : data->ratios.horz,
907 orthogonal_rotation ? &data->inits.v : &data->inits.h,
908 &data->viewport.x,
909 &data->viewport.width);
910 adjust_vp_and_init_for_seamless_clip(
911 flip_horz_scan_dir,
912 recout_skip_h,
913 surf_size_h / vpc_div,
914 orthogonal_rotation ? data->taps.v_taps_c : data->taps.h_taps_c,
915 orthogonal_rotation ? data->ratios.vert_c : data->ratios.horz_c,
916 orthogonal_rotation ? &data->inits.v_c : &data->inits.h_c,
917 &data->viewport_c.x,
918 &data->viewport_c.width);
919 adjust_vp_and_init_for_seamless_clip(
920 flip_vert_scan_dir,
921 recout_skip_v,
922 surf_size_v,
923 orthogonal_rotation ? data->taps.h_taps : data->taps.v_taps,
924 orthogonal_rotation ? data->ratios.horz : data->ratios.vert,
925 orthogonal_rotation ? &data->inits.h : &data->inits.v,
926 &data->viewport.y,
927 &data->viewport.height);
928 adjust_vp_and_init_for_seamless_clip(
929 flip_vert_scan_dir,
930 recout_skip_v,
931 surf_size_v / vpc_div,
932 orthogonal_rotation ? data->taps.h_taps_c : data->taps.v_taps_c,
933 orthogonal_rotation ? data->ratios.horz_c : data->ratios.vert_c,
934 orthogonal_rotation ? &data->inits.h_c : &data->inits.v_c,
935 &data->viewport_c.y,
936 &data->viewport_c.height);
b2d0a103
DL		 937
938 /* Interlaced inits based on final vert inits */
eb0e5154
DL		 939 data->inits.v_bot = dc_fixpt_add(data->inits.v, data->ratios.vert);
940 data->inits.v_c_bot = dc_fixpt_add(data->inits.v_c, data->ratios.vert_c);
1fbd2cfc 941
b2d0a103 942}
f7938bc0
RA		 943static bool are_rect_integer_multiples(struct rect src, struct rect dest)
944{
945 if (dest.width >= src.width && dest.width % src.width == 0 &&
946 dest.height >= src.height && dest.height % src.height == 0)
947 return true;
b2d0a103 948
f7938bc0
RA		 949 return false;
950}
b2d0a103 951bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
4562236b 952{
3be5262e 953 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
4fa086b9 954 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
b2d0a103 955 bool res = false;
5d4b05dd 956 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
4562236b
HW		 957 /* Important: scaling ratio calculation requires pixel format,
958 * lb depth calculation requires recout and taps require scaling ratios.
b2d0a103 959 * Inits require viewport, taps, ratios and recout of split pipe
4562236b 960 */
6702a9ac 961 pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface(
3be5262e 962 pipe_ctx->plane_state->format);
b2d0a103
DL		 963
964 calculate_scaling_ratios(pipe_ctx);
4562236b 965
b2d0a103 966 calculate_viewport(pipe_ctx);
4562236b 967
6702a9ac 968 if (pipe_ctx->plane_res.scl_data.viewport.height < 16 || pipe_ctx->plane_res.scl_data.viewport.width < 16)
4562236b
HW		 969 return false;
970
9b6067c0 971 calculate_recout(pipe_ctx);
4562236b
HW		 972
973 /**
974 * Setting line buffer pixel depth to 24bpp yields banding
975 * on certain displays, such as the Sharp 4k
976 */
6702a9ac 977 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
4562236b 978
199e458a 979 pipe_ctx->plane_res.scl_data.recout.x += timing->h_border_left;
58bb0e63 980 pipe_ctx->plane_res.scl_data.recout.y += timing->v_border_top;
199e458a 981
58bb0e63
AJ		 982 pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right;
983 pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable + timing->v_border_top + timing->v_border_bottom;
1b6c8067 984
4562236b 985 /* Taps calculations */
d94585a0
YHL		 986 if (pipe_ctx->plane_res.xfm != NULL)
987 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
988 pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
989
990 if (pipe_ctx->plane_res.dpp != NULL)
991 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
992 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
f7938bc0
RA		 993
994 if (res &&
995 plane_state->scaling_quality.integer_scaling &&
996 are_rect_integer_multiples(pipe_ctx->plane_res.scl_data.viewport,
997 pipe_ctx->plane_res.scl_data.recout)) {
998 pipe_ctx->plane_res.scl_data.taps.v_taps = 1;
999 pipe_ctx->plane_res.scl_data.taps.h_taps = 1;
1000 }
1001
4562236b
HW		 1002 if (!res) {
1003 /* Try 24 bpp linebuffer */
6702a9ac 1004 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP;
4562236b 1005
1b6c8067
BL		 1006 if (pipe_ctx->plane_res.xfm != NULL)
1007 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
1008 pipe_ctx->plane_res.xfm,
1009 &pipe_ctx->plane_res.scl_data,
1010 &plane_state->scaling_quality);
1011
1012 if (pipe_ctx->plane_res.dpp != NULL)
1013 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
1014 pipe_ctx->plane_res.dpp,
1015 &pipe_ctx->plane_res.scl_data,
1016 &plane_state->scaling_quality);
4562236b
HW		 1017 }
1018
b2d0a103 1019 if (res)
1fbd2cfc 1020 /* May need to re-check lb size after this in some obscure scenario */
9b6067c0 1021 calculate_inits_and_adj_vp(pipe_ctx);
b2d0a103 1022
1296423b 1023 DC_LOG_SCALER(
4562236b
HW		 1024 "%s: Viewport:\nheight:%d width:%d x:%d "
1025 "y:%d\n dst_rect:\nheight:%d width:%d x:%d "
1026 "y:%d\n",
1027 __func__,
6702a9ac
HW		 1028 pipe_ctx->plane_res.scl_data.viewport.height,
1029 pipe_ctx->plane_res.scl_data.viewport.width,
1030 pipe_ctx->plane_res.scl_data.viewport.x,
1031 pipe_ctx->plane_res.scl_data.viewport.y,
3be5262e
HW		 1032 plane_state->dst_rect.height,
1033 plane_state->dst_rect.width,
1034 plane_state->dst_rect.x,
1035 plane_state->dst_rect.y);
4562236b
HW		 1036
1037 return res;
1038}
1039
1040
1041enum dc_status resource_build_scaling_params_for_context(
fb3466a4 1042 const struct dc *dc,
608ac7bb 1043 struct dc_state *context)
4562236b
HW		 1044{
1045 int i;
1046
1047 for (i = 0; i < MAX_PIPES; i++) {
3be5262e 1048 if (context->res_ctx.pipe_ctx[i].plane_state != NULL &&
4562236b 1049 context->res_ctx.pipe_ctx[i].stream != NULL)
b2d0a103 1050 if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i]))
f84a8161 1051 return DC_FAIL_SCALING;
4562236b
HW		 1052 }
1053
1054 return DC_OK;
1055}
1056
a2b8659d
TC		 1057struct pipe_ctx *find_idle_secondary_pipe(
1058 struct resource_context *res_ctx,
5581192d
JL		 1059 const struct resource_pool *pool,
1060 const struct pipe_ctx *primary_pipe)
4562236b
HW		 1061{
1062 int i;
1063 struct pipe_ctx *secondary_pipe = NULL;
1064
1065 /*
5581192d
JL		 1066 * We add a preferred pipe mapping to avoid the chance that
1067 * MPCCs already in use will need to be reassigned to other trees.
1068 * For example, if we went with the strict, assign backwards logic:
1069 *
1070 * (State 1)
1071 * Display A on, no surface, top pipe = 0
1072 * Display B on, no surface, top pipe = 1
1073 *
1074 * (State 2)
1075 * Display A on, no surface, top pipe = 0
1076 * Display B on, surface enable, top pipe = 1, bottom pipe = 5
1077 *
1078 * (State 3)
1079 * Display A on, surface enable, top pipe = 0, bottom pipe = 5
1080 * Display B on, surface enable, top pipe = 1, bottom pipe = 4
1081 *
1082 * The state 2->3 transition requires remapping MPCC 5 from display B
1083 * to display A.
1084 *
1085 * However, with the preferred pipe logic, state 2 would look like:
1086 *
1087 * (State 2)
1088 * Display A on, no surface, top pipe = 0
1089 * Display B on, surface enable, top pipe = 1, bottom pipe = 4
1090 *
1091 * This would then cause 2->3 to not require remapping any MPCCs.
4562236b 1092 */
5581192d
JL		 1093 if (primary_pipe) {
1094 int preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx;
1095 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
1096 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
1097 secondary_pipe->pipe_idx = preferred_pipe_idx;
4562236b
HW		 1098 }
1099 }
1100
5581192d
JL		 1101 /*
1102 * search backwards for the second pipe to keep pipe
1103 * assignment more consistent
1104 */
1105 if (!secondary_pipe)
1106 for (i = pool->pipe_count - 1; i >= 0; i--) {
1107 if (res_ctx->pipe_ctx[i].stream == NULL) {
1108 secondary_pipe = &res_ctx->pipe_ctx[i];
1109 secondary_pipe->pipe_idx = i;
1110 break;
1111 }
1112 }
4562236b
HW		 1113
1114 return secondary_pipe;
1115}
1116
1117struct pipe_ctx *resource_get_head_pipe_for_stream(
1118 struct resource_context *res_ctx,
0971c40e 1119 struct dc_stream_state *stream)
4562236b
HW		 1120{
1121 int i;
a2b8659d 1122 for (i = 0; i < MAX_PIPES; i++) {
4562236b 1123 if (res_ctx->pipe_ctx[i].stream == stream &&
1dc90497 1124 !res_ctx->pipe_ctx[i].top_pipe) {
4562236b
HW		 1125 return &res_ctx->pipe_ctx[i];
1126 break;
1127 }
1128 }
1129 return NULL;
1130}
1131
19f89e23
AG		 1132static struct pipe_ctx *resource_get_tail_pipe_for_stream(
1133 struct resource_context *res_ctx,
1134 struct dc_stream_state *stream)
1135{
1136 struct pipe_ctx *head_pipe, *tail_pipe;
1137 head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
1138
1139 if (!head_pipe)
1140 return NULL;
1141
1142 tail_pipe = head_pipe->bottom_pipe;
1143
1144 while (tail_pipe) {
1145 head_pipe = tail_pipe;
1146 tail_pipe = tail_pipe->bottom_pipe;
1147 }
1148
1149 return head_pipe;
1150}
1151
4562236b 1152/*
ab2541b6
AC		 1153 * A free_pipe for a stream is defined here as a pipe
1154 * that has no surface attached yet
4562236b 1155 */
ab2541b6 1156static struct pipe_ctx *acquire_free_pipe_for_stream(
608ac7bb 1157 struct dc_state *context,
a2b8659d 1158 const struct resource_pool *pool,
0971c40e 1159 struct dc_stream_state *stream)
4562236b
HW		 1160{
1161 int i;
745cc746 1162 struct resource_context *res_ctx = &context->res_ctx;
4562236b
HW		 1163
1164 struct pipe_ctx *head_pipe = NULL;
1165
1166 /* Find head pipe, which has the back end set up*/
1167
1168 head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
1169
e41ab030 1170 if (!head_pipe) {
4562236b 1171 ASSERT(0);
e41ab030
HW		 1172 return NULL;
1173 }
4562236b 1174
3be5262e 1175 if (!head_pipe->plane_state)
4562236b
HW		 1176 return head_pipe;
1177
1178 /* Re-use pipe already acquired for this stream if available*/
a2b8659d 1179 for (i = pool->pipe_count - 1; i >= 0; i--) {
4562236b 1180 if (res_ctx->pipe_ctx[i].stream == stream &&
3be5262e 1181 !res_ctx->pipe_ctx[i].plane_state) {
4562236b
HW		 1182 return &res_ctx->pipe_ctx[i];
1183 }
1184 }
1185
1186 /*
1187 * At this point we have no re-useable pipe for this stream and we need
1188 * to acquire an idle one to satisfy the request
1189 */
1190
a2b8659d 1191 if (!pool->funcs->acquire_idle_pipe_for_layer)
4562236b
HW		 1192 return NULL;
1193
a2b8659d 1194 return pool->funcs->acquire_idle_pipe_for_layer(context, pool, stream);
4562236b
HW		 1195
1196}
1197
dc37a9a0 1198#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
0f9a536f
DL		 1199static int acquire_first_split_pipe(
1200 struct resource_context *res_ctx,
1201 const struct resource_pool *pool,
0971c40e 1202 struct dc_stream_state *stream)
0f9a536f
DL		 1203{
1204 int i;
1205
1206 for (i = 0; i < pool->pipe_count; i++) {
79592db3
DL		 1207 struct pipe_ctx *split_pipe = &res_ctx->pipe_ctx[i];
1208
1209 if (split_pipe->top_pipe && !dc_res_is_odm_head_pipe(split_pipe) &&
1210 split_pipe->top_pipe->plane_state == split_pipe->plane_state) {
1211 split_pipe->top_pipe->bottom_pipe = split_pipe->bottom_pipe;
1212 if (split_pipe->bottom_pipe)
1213 split_pipe->bottom_pipe->top_pipe = split_pipe->top_pipe;
1214
1215 if (split_pipe->top_pipe->plane_state)
1216 resource_build_scaling_params(split_pipe->top_pipe);
1217
1218 memset(split_pipe, 0, sizeof(*split_pipe));
1219 split_pipe->stream_res.tg = pool->timing_generators[i];
1220 split_pipe->plane_res.hubp = pool->hubps[i];
1221 split_pipe->plane_res.ipp = pool->ipps[i];
1222 split_pipe->plane_res.dpp = pool->dpps[i];
1223 split_pipe->stream_res.opp = pool->opps[i];
1224 split_pipe->plane_res.mpcc_inst = pool->dpps[i]->inst;
1225 split_pipe->pipe_idx = i;
1226
1227 split_pipe->stream = stream;
0f9a536f
DL		 1228 return i;
1229 }
1230 }
1231 return -1;
1232}
1233#endif
1234
19f89e23
AG		 1235bool dc_add_plane_to_context(
1236 const struct dc *dc,
0971c40e 1237 struct dc_stream_state *stream,
19f89e23 1238 struct dc_plane_state *plane_state,
608ac7bb 1239 struct dc_state *context)
4562236b
HW		 1240{
1241 int i;
19f89e23
AG		 1242 struct resource_pool *pool = dc->res_pool;
1243 struct pipe_ctx *head_pipe, *tail_pipe, *free_pipe;
ab2541b6 1244 struct dc_stream_status *stream_status = NULL;
4562236b 1245
19f89e23
AG		 1246 for (i = 0; i < context->stream_count; i++)
1247 if (context->streams[i] == stream) {
1248 stream_status = &context->stream_status[i];
1249 break;
1250 }
1251 if (stream_status == NULL) {
1252 dm_error("Existing stream not found; failed to attach surface!\n");
1253 return false;
1254 }
1255
4562236b 1256
19f89e23
AG		 1257 if (stream_status->plane_count == MAX_SURFACE_NUM) {
1258 dm_error("Surface: can not attach plane_state %p! Maximum is: %d\n",
1259 plane_state, MAX_SURFACE_NUM);
4562236b
HW		 1260 return false;
1261 }
1262
19f89e23
AG		 1263 head_pipe = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
1264
1265 if (!head_pipe) {
1266 dm_error("Head pipe not found for stream_state %p !\n", stream);
1267 return false;
1268 }
1269
00737c59
EB		 1270 tail_pipe = resource_get_tail_pipe_for_stream(&context->res_ctx, stream);
1271 ASSERT(tail_pipe);
1272
19f89e23
AG		 1273 free_pipe = acquire_free_pipe_for_stream(context, pool, stream);
1274
dc37a9a0 1275#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
19f89e23
AG		 1276 if (!free_pipe) {
1277 int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
1278 if (pipe_idx >= 0)
1279 free_pipe = &context->res_ctx.pipe_ctx[pipe_idx];
1280 }
1281#endif
abb4986e 1282 if (!free_pipe)
19f89e23 1283 return false;
19f89e23 1284
abb4986e
AJ		 1285 /* retain new surfaces */
1286 dc_plane_state_retain(plane_state);
19f89e23
AG		 1287 free_pipe->plane_state = plane_state;
1288
1289 if (head_pipe != free_pipe) {
19f89e23 1290 free_pipe->stream_res.tg = tail_pipe->stream_res.tg;
9aef1a31 1291 free_pipe->stream_res.abm = tail_pipe->stream_res.abm;
19f89e23
AG		 1292 free_pipe->stream_res.opp = tail_pipe->stream_res.opp;
1293 free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc;
1294 free_pipe->stream_res.audio = tail_pipe->stream_res.audio;
1295 free_pipe->clock_source = tail_pipe->clock_source;
1296 free_pipe->top_pipe = tail_pipe;
1297 tail_pipe->bottom_pipe = free_pipe;
4a797d24
DL		 1298 } else if (free_pipe->bottom_pipe && free_pipe->bottom_pipe->plane_state == NULL) {
1299 ASSERT(free_pipe->bottom_pipe->stream_res.opp != free_pipe->stream_res.opp);
1300 free_pipe->bottom_pipe->plane_state = plane_state;
19f89e23
AG		 1301 }
1302
1303 /* assign new surfaces*/
1304 stream_status->plane_states[stream_status->plane_count] = plane_state;
1305
1306 stream_status->plane_count++;
1307
1308 return true;
1309}
1310
6ffaa6fc
DL		 1311struct pipe_ctx *dc_res_get_odm_bottom_pipe(struct pipe_ctx *pipe_ctx)
1312{
1313 struct pipe_ctx *bottom_pipe = pipe_ctx->bottom_pipe;
1314
1315 /* ODM should only be updated once per otg */
1316 if (pipe_ctx->top_pipe)
1317 return NULL;
1318
1319 while (bottom_pipe) {
1320 if (bottom_pipe->stream_res.opp != pipe_ctx->stream_res.opp)
1321 break;
1322 bottom_pipe = bottom_pipe->bottom_pipe;
1323 }
1324
1325 return bottom_pipe;
1326}
1327
c0415c87 1328bool dc_res_is_odm_head_pipe(struct pipe_ctx *pipe_ctx)
6ffaa6fc
DL		 1329{
1330 struct pipe_ctx *top_pipe = pipe_ctx->top_pipe;
6ffaa6fc 1331
fe6382cd
DL		 1332 if (!top_pipe)
1333 return false;
6ffaa6fc
DL		 1334 if (top_pipe && top_pipe->stream_res.opp == pipe_ctx->stream_res.opp)
1335 return false;
1336
fe6382cd 1337 return true;
6ffaa6fc
DL		 1338}
1339
19f89e23
AG		 1340bool dc_remove_plane_from_context(
1341 const struct dc *dc,
1342 struct dc_stream_state *stream,
1343 struct dc_plane_state *plane_state,
608ac7bb 1344 struct dc_state *context)
19f89e23
AG		 1345{
1346 int i;
1347 struct dc_stream_status *stream_status = NULL;
1348 struct resource_pool *pool = dc->res_pool;
1349
ab2541b6 1350 for (i = 0; i < context->stream_count; i++)
4fa086b9 1351 if (context->streams[i] == stream) {
ab2541b6 1352 stream_status = &context->stream_status[i];
4562236b
HW		 1353 break;
1354 }
19f89e23 1355
ab2541b6 1356 if (stream_status == NULL) {
19f89e23 1357 dm_error("Existing stream not found; failed to remove plane.\n");
4562236b
HW		 1358 return false;
1359 }
1360
19f89e23
AG		 1361 /* release pipe for plane*/
1362 for (i = pool->pipe_count - 1; i >= 0; i--) {
6ffaa6fc 1363 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
4562236b 1364
6ffaa6fc 1365 if (pipe_ctx->plane_state == plane_state) {
c0415c87 1366 if (dc_res_is_odm_head_pipe(pipe_ctx)) {
6ffaa6fc
DL		 1367 pipe_ctx->plane_state = NULL;
1368 pipe_ctx->bottom_pipe = NULL;
1369 continue;
1370 }
4562236b 1371
19f89e23
AG		 1372 if (pipe_ctx->top_pipe)
1373 pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;
4562236b 1374
19f89e23
AG		 1375 /* Second condition is to avoid setting NULL to top pipe
1376 * of tail pipe making it look like head pipe in subsequent
1377 * deletes
1378 */
1379 if (pipe_ctx->bottom_pipe && pipe_ctx->top_pipe)
1380 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;
4562236b 1381
19f89e23
AG		 1382 /*
1383 * For head pipe detach surfaces from pipe for tail
1384 * pipe just zero it out
1385 */
6ffaa6fc 1386 if (!pipe_ctx->top_pipe) {
19f89e23 1387 pipe_ctx->plane_state = NULL;
6ffaa6fc
DL		 1388 if (!dc_res_get_odm_bottom_pipe(pipe_ctx))
1389 pipe_ctx->bottom_pipe = NULL;
bc219399 1390 } else {
19f89e23
AG		 1391 memset(pipe_ctx, 0, sizeof(*pipe_ctx));
1392 }
4562236b 1393 }
19f89e23 1394 }
4562236b 1395
4562236b 1396
19f89e23
AG		 1397 for (i = 0; i < stream_status->plane_count; i++) {
1398 if (stream_status->plane_states[i] == plane_state) {
1399
1400 dc_plane_state_release(stream_status->plane_states[i]);
1401 break;
4562236b 1402 }
19f89e23 1403 }
4562236b 1404
19f89e23
AG		 1405 if (i == stream_status->plane_count) {
1406 dm_error("Existing plane_state not found; failed to detach it!\n");
1407 return false;
4562236b
HW		 1408 }
1409
19f89e23 1410 stream_status->plane_count--;
4562236b 1411
abb4986e
AJ		 1412 /* Start at the plane we've just released, and move all the planes one index forward to "trim" the array */
1413 for (; i < stream_status->plane_count; i++)
19f89e23
AG		 1414 stream_status->plane_states[i] = stream_status->plane_states[i + 1];
1415
1416 stream_status->plane_states[stream_status->plane_count] = NULL;
1417
1418 return true;
1419}
1420
1421bool dc_rem_all_planes_for_stream(
1422 const struct dc *dc,
1423 struct dc_stream_state *stream,
608ac7bb 1424 struct dc_state *context)
19f89e23
AG		 1425{
1426 int i, old_plane_count;
1427 struct dc_stream_status *stream_status = NULL;
1428 struct dc_plane_state *del_planes[MAX_SURFACE_NUM] = { 0 };
1429
1430 for (i = 0; i < context->stream_count; i++)
1431 if (context->streams[i] == stream) {
1432 stream_status = &context->stream_status[i];
1433 break;
1434 }
1435
1436 if (stream_status == NULL) {
1437 dm_error("Existing stream %p not found!\n", stream);
1438 return false;
1439 }
1440
1441 old_plane_count = stream_status->plane_count;
1442
1443 for (i = 0; i < old_plane_count; i++)
1444 del_planes[i] = stream_status->plane_states[i];
1445
1446 for (i = 0; i < old_plane_count; i++)
1447 if (!dc_remove_plane_from_context(dc, stream, del_planes[i], context))
1448 return false;
1449
1450 return true;
1451}
1452
1453static bool add_all_planes_for_stream(
1454 const struct dc *dc,
1455 struct dc_stream_state *stream,
1456 const struct dc_validation_set set[],
1457 int set_count,
608ac7bb 1458 struct dc_state *context)
19f89e23
AG		 1459{
1460 int i, j;
1461
1462 for (i = 0; i < set_count; i++)
1463 if (set[i].stream == stream)
1464 break;
1465
1466 if (i == set_count) {
1467 dm_error("Stream %p not found in set!\n", stream);
1468 return false;
1469 }
4562236b 1470
19f89e23
AG		 1471 for (j = 0; j < set[i].plane_count; j++)
1472 if (!dc_add_plane_to_context(dc, stream, set[i].plane_states[j], context))
1473 return false;
4562236b
HW		 1474
1475 return true;
1476}
1477
19f89e23
AG		 1478bool dc_add_all_planes_for_stream(
1479 const struct dc *dc,
1480 struct dc_stream_state *stream,
1481 struct dc_plane_state * const *plane_states,
1482 int plane_count,
608ac7bb 1483 struct dc_state *context)
19f89e23
AG		 1484{
1485 struct dc_validation_set set;
1486 int i;
1487
1488 set.stream = stream;
1489 set.plane_count = plane_count;
1490
1491 for (i = 0; i < plane_count; i++)
1492 set.plane_states[i] = plane_states[i];
1493
1494 return add_all_planes_for_stream(dc, stream, &set, 1, context);
1495}
1496
1497
6b622181
JP		 1498static bool is_hdr_static_meta_changed(struct dc_stream_state *cur_stream,
1499 struct dc_stream_state *new_stream)
1500{
1501 if (cur_stream == NULL)
1502 return true;
1503
1504 if (memcmp(&cur_stream->hdr_static_metadata,
1505 &new_stream->hdr_static_metadata,
1506 sizeof(struct dc_info_packet)) != 0)
1507 return true;
1508
1509 return false;
1510}
4562236b 1511
1336926f
A		 1512static bool is_vsc_info_packet_changed(struct dc_stream_state *cur_stream,
1513 struct dc_stream_state *new_stream)
1514{
1515 if (cur_stream == NULL)
1516 return true;
1517
1518 if (memcmp(&cur_stream->vsc_infopacket,
1519 &new_stream->vsc_infopacket,
1520 sizeof(struct dc_info_packet)) != 0)
1521 return true;
1522
1523 return false;
1524}
1525
0971c40e
HW		 1526static bool is_timing_changed(struct dc_stream_state *cur_stream,
1527 struct dc_stream_state *new_stream)
4562236b
HW		 1528{
1529 if (cur_stream == NULL)
1530 return true;
1531
1532 /* If sink pointer changed, it means this is a hotplug, we should do
1533 * full hw setting.
1534 */
1535 if (cur_stream->sink != new_stream->sink)
1536 return true;
1537
1538 /* If output color space is changed, need to reprogram info frames */
4fa086b9 1539 if (cur_stream->output_color_space != new_stream->output_color_space)
4562236b
HW		 1540 return true;
1541
1542 return memcmp(
4fa086b9
LSL		 1543 &cur_stream->timing,
1544 &new_stream->timing,
4562236b
HW		 1545 sizeof(struct dc_crtc_timing)) != 0;
1546}
1547
1548static bool are_stream_backends_same(
0971c40e 1549 struct dc_stream_state *stream_a, struct dc_stream_state *stream_b)
4562236b
HW		 1550{
1551 if (stream_a == stream_b)
1552 return true;
1553
1554 if (stream_a == NULL || stream_b == NULL)
1555 return false;
1556
1557 if (is_timing_changed(stream_a, stream_b))
1558 return false;
1559
6b622181
JP		 1560 if (is_hdr_static_meta_changed(stream_a, stream_b))
1561 return false;
1562
1e7e86c4
ST		 1563 if (stream_a->dpms_off != stream_b->dpms_off)
1564 return false;
1565
1336926f
A		 1566 if (is_vsc_info_packet_changed(stream_a, stream_b))
1567 return false;
1568
4562236b
HW		 1569 return true;
1570}
1571
2119aa17
DF		 1572/**
1573 * dc_is_stream_unchanged() - Compare two stream states for equivalence.
1574 *
1575 * Checks if there a difference between the two states
1576 * that would require a mode change.
1577 *
1578 * Does not compare cursor position or attributes.
1579 */
d54d29db 1580bool dc_is_stream_unchanged(
0971c40e 1581 struct dc_stream_state *old_stream, struct dc_stream_state *stream)
4562236b 1582{
4562236b 1583
ab2541b6
AC		 1584 if (!are_stream_backends_same(old_stream, stream))
1585 return false;
4562236b
HW		 1586
1587 return true;
1588}
1589
2119aa17
DF		 1590/**
1591 * dc_is_stream_scaling_unchanged() - Compare scaling rectangles of two streams.
1592 */
9a5d9c48
LSL		 1593bool dc_is_stream_scaling_unchanged(
1594 struct dc_stream_state *old_stream, struct dc_stream_state *stream)
1595{
1596 if (old_stream == stream)
1597 return true;
1598
1599 if (old_stream == NULL || stream == NULL)
1600 return false;
1601
1602 if (memcmp(&old_stream->src,
1603 &stream->src,
1604 sizeof(struct rect)) != 0)
1605 return false;
1606
1607 if (memcmp(&old_stream->dst,
1608 &stream->dst,
1609 sizeof(struct rect)) != 0)
1610 return false;
1611
1612 return true;
1613}
1614
1dc90497 1615static void update_stream_engine_usage(
4562236b 1616 struct resource_context *res_ctx,
a2b8659d 1617 const struct resource_pool *pool,
1dc90497
AG		 1618 struct stream_encoder *stream_enc,
1619 bool acquired)
4562236b
HW		 1620{
1621 int i;
1622
a2b8659d
TC		 1623 for (i = 0; i < pool->stream_enc_count; i++) {
1624 if (pool->stream_enc[i] == stream_enc)
1dc90497 1625 res_ctx->is_stream_enc_acquired[i] = acquired;
4562236b
HW		 1626 }
1627}
1628
1629/* TODO: release audio object */
4176664b 1630void update_audio_usage(
4562236b 1631 struct resource_context *res_ctx,
a2b8659d 1632 const struct resource_pool *pool,
1dc90497
AG		 1633 struct audio *audio,
1634 bool acquired)
4562236b
HW		 1635{
1636 int i;
a2b8659d
TC		 1637 for (i = 0; i < pool->audio_count; i++) {
1638 if (pool->audios[i] == audio)
1dc90497 1639 res_ctx->is_audio_acquired[i] = acquired;
4562236b
HW		 1640 }
1641}
1642
1643static int acquire_first_free_pipe(
1644 struct resource_context *res_ctx,
a2b8659d 1645 const struct resource_pool *pool,
0971c40e 1646 struct dc_stream_state *stream)
4562236b
HW		 1647{
1648 int i;
1649
a2b8659d 1650 for (i = 0; i < pool->pipe_count; i++) {
4562236b
HW		 1651 if (!res_ctx->pipe_ctx[i].stream) {
1652 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
1653
6b670fa9 1654 pipe_ctx->stream_res.tg = pool->timing_generators[i];
86a66c4e 1655 pipe_ctx->plane_res.mi = pool->mis[i];
8feabd03 1656 pipe_ctx->plane_res.hubp = pool->hubps[i];
86a66c4e
HW		 1657 pipe_ctx->plane_res.ipp = pool->ipps[i];
1658 pipe_ctx->plane_res.xfm = pool->transforms[i];
d94585a0 1659 pipe_ctx->plane_res.dpp = pool->dpps[i];
a6a6cb34 1660 pipe_ctx->stream_res.opp = pool->opps[i];
bc373a89
RL		 1661 if (pool->dpps[i])
1662 pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst;
4562236b
HW		 1663 pipe_ctx->pipe_idx = i;
1664
ff5ef992 1665
4562236b
HW		 1666 pipe_ctx->stream = stream;
1667 return i;
1668 }
1669 }
1670 return -1;
1671}
1672
a2b8659d
TC		 1673static struct audio *find_first_free_audio(
1674 struct resource_context *res_ctx,
cfb071f7
CL		 1675 const struct resource_pool *pool,
1676 enum engine_id id)
4562236b
HW		 1677{
1678 int i;
66bfd4fd
CL		 1679 for (i = 0; i < pool->audio_count; i++) {
1680 if ((res_ctx->is_audio_acquired[i] == false) && (res_ctx->is_stream_enc_acquired[i] == true)) {
cfb071f7
CL		 1681 /*we have enough audio endpoint, find the matching inst*/
1682 if (id != i)
1683 continue;
1684
66bfd4fd 1685 return pool->audios[i];
4562236b 1686 }
66bfd4fd 1687 }
5feb9f07
TM		 1688
1689 /* use engine id to find free audio */
1690 if ((id < pool->audio_count) && (res_ctx->is_audio_acquired[id] == false)) {
1691 return pool->audios[id];
1692 }
1693
66bfd4fd
CL		 1694 /*not found the matching one, first come first serve*/
1695 for (i = 0; i < pool->audio_count; i++) {
1696 if (res_ctx->is_audio_acquired[i] == false) {
1697 return pool->audios[i];
4176664b
CL		 1698 }
1699 }
4562236b
HW		 1700 return 0;
1701}
1702
4562236b 1703bool resource_is_stream_unchanged(
608ac7bb 1704 struct dc_state *old_context, struct dc_stream_state *stream)
4562236b 1705{
ab2541b6 1706 int i;
4562236b 1707
ab2541b6 1708 for (i = 0; i < old_context->stream_count; i++) {
0971c40e 1709 struct dc_stream_state *old_stream = old_context->streams[i];
4562236b 1710
ab2541b6 1711 if (are_stream_backends_same(old_stream, stream))
4562236b 1712 return true;
4562236b
HW		 1713 }
1714
1715 return false;
1716}
1717
2119aa17
DF		 1718/**
1719 * dc_add_stream_to_ctx() - Add a new dc_stream_state to a dc_state.
1720 */
13ab1b44 1721enum dc_status dc_add_stream_to_ctx(
1dc90497 1722 struct dc *dc,
608ac7bb 1723 struct dc_state *new_ctx,
1dc90497
AG		 1724 struct dc_stream_state *stream)
1725{
1dc90497 1726 enum dc_status res;
eb9714a2 1727 DC_LOGGER_INIT(dc->ctx->logger);
1dc90497 1728
ece4147f 1729 if (new_ctx->stream_count >= dc->res_pool->timing_generator_count) {
eb9714a2 1730 DC_LOG_WARNING("Max streams reached, can't add stream %p !\n", stream);
1dc90497
AG		 1731 return DC_ERROR_UNEXPECTED;
1732 }
1733
1734 new_ctx->streams[new_ctx->stream_count] = stream;
1735 dc_stream_retain(stream);
1736 new_ctx->stream_count++;
1737
1738 res = dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream);
1739 if (res != DC_OK)
eb9714a2 1740 DC_LOG_WARNING("Adding stream %p to context failed with err %d!\n", stream, res);
1dc90497 1741
13ab1b44 1742 return res;
1dc90497
AG		 1743}
1744
2119aa17
DF		 1745/**
1746 * dc_remove_stream_from_ctx() - Remove a stream from a dc_state.
1747 */
62c933f9 1748enum dc_status dc_remove_stream_from_ctx(
1dc90497 1749 struct dc *dc,
608ac7bb 1750 struct dc_state *new_ctx,
1dc90497
AG		 1751 struct dc_stream_state *stream)
1752{
19f89e23 1753 int i;
1dc90497
AG		 1754 struct dc_context *dc_ctx = dc->ctx;
1755 struct pipe_ctx *del_pipe = NULL;
1756
19f89e23 1757 /* Release primary pipe */
1dc90497 1758 for (i = 0; i < MAX_PIPES; i++) {
19f89e23
AG		 1759 if (new_ctx->res_ctx.pipe_ctx[i].stream == stream &&
1760 !new_ctx->res_ctx.pipe_ctx[i].top_pipe) {
6ffaa6fc
DL		 1761 struct pipe_ctx *odm_pipe =
1762 dc_res_get_odm_bottom_pipe(&new_ctx->res_ctx.pipe_ctx[i]);
1763
1dc90497
AG		 1764 del_pipe = &new_ctx->res_ctx.pipe_ctx[i];
1765
19f89e23
AG		 1766 ASSERT(del_pipe->stream_res.stream_enc);
1767 update_stream_engine_usage(
1768 &new_ctx->res_ctx,
1dc90497 1769 dc->res_pool,
19f89e23
AG		 1770 del_pipe->stream_res.stream_enc,
1771 false);
1dc90497
AG		 1772
1773 if (del_pipe->stream_res.audio)
1774 update_audio_usage(
1775 &new_ctx->res_ctx,
1776 dc->res_pool,
1777 del_pipe->stream_res.audio,
1778 false);
1779
9d0dcecd
HW		 1780 resource_unreference_clock_source(&new_ctx->res_ctx,
1781 dc->res_pool,
1782 del_pipe->clock_source);
1783
e56ae556
NC		 1784 if (dc->res_pool->funcs->remove_stream_from_ctx)
1785 dc->res_pool->funcs->remove_stream_from_ctx(dc, new_ctx, stream);
1786
1dc90497 1787 memset(del_pipe, 0, sizeof(*del_pipe));
6ffaa6fc
DL		 1788 if (odm_pipe)
1789 memset(odm_pipe, 0, sizeof(*odm_pipe));
1790
1791 break;
1dc90497
AG		 1792 }
1793 }
1794
1795 if (!del_pipe) {
1796 DC_ERROR("Pipe not found for stream %p !\n", stream);
1797 return DC_ERROR_UNEXPECTED;
1798 }
1799
1800 for (i = 0; i < new_ctx->stream_count; i++)
1801 if (new_ctx->streams[i] == stream)
1802 break;
1803
1804 if (new_ctx->streams[i] != stream) {
1805 DC_ERROR("Context doesn't have stream %p !\n", stream);
1806 return DC_ERROR_UNEXPECTED;
1807 }
1808
1809 dc_stream_release(new_ctx->streams[i]);
1810 new_ctx->stream_count--;
1811
1dc90497
AG		 1812 /* Trim back arrays */
1813 for (; i < new_ctx->stream_count; i++) {
1814 new_ctx->streams[i] = new_ctx->streams[i + 1];
1815 new_ctx->stream_status[i] = new_ctx->stream_status[i + 1];
1816 }
1817
1818 new_ctx->streams[new_ctx->stream_count] = NULL;
1819 memset(
1820 &new_ctx->stream_status[new_ctx->stream_count],
1821 0,
1822 sizeof(new_ctx->stream_status[0]));
1823
1824 return DC_OK;
1825}
1826
0971c40e
HW		 1827static struct dc_stream_state *find_pll_sharable_stream(
1828 struct dc_stream_state *stream_needs_pll,
608ac7bb 1829 struct dc_state *context)
4562236b 1830{
ab2541b6 1831 int i;
4562236b 1832
ab2541b6 1833 for (i = 0; i < context->stream_count; i++) {
0971c40e 1834 struct dc_stream_state *stream_has_pll = context->streams[i];
4562236b 1835
ab2541b6
AC		 1836 /* We are looking for non dp, non virtual stream */
1837 if (resource_are_streams_timing_synchronizable(
1838 stream_needs_pll, stream_has_pll)
1839 && !dc_is_dp_signal(stream_has_pll->signal)
ceb3dbb4 1840 && stream_has_pll->link->connector_signal
ab2541b6
AC		 1841 != SIGNAL_TYPE_VIRTUAL)
1842 return stream_has_pll;
4562236b 1843
4562236b
HW		 1844 }
1845
1846 return NULL;
1847}
1848
1849static int get_norm_pix_clk(const struct dc_crtc_timing *timing)
1850{
380604e2 1851 uint32_t pix_clk = timing->pix_clk_100hz;
4562236b
HW		 1852 uint32_t normalized_pix_clk = pix_clk;
1853
1854 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
1855 pix_clk /= 2;
cc4d99b8
CL		 1856 if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) {
1857 switch (timing->display_color_depth) {
8897810a 1858 case COLOR_DEPTH_666:
cc4d99b8
CL		 1859 case COLOR_DEPTH_888:
1860 normalized_pix_clk = pix_clk;
1861 break;
1862 case COLOR_DEPTH_101010:
1863 normalized_pix_clk = (pix_clk * 30) / 24;
1864 break;
1865 case COLOR_DEPTH_121212:
1866 normalized_pix_clk = (pix_clk * 36) / 24;
4562236b 1867 break;
cc4d99b8
CL		 1868 case COLOR_DEPTH_161616:
1869 normalized_pix_clk = (pix_clk * 48) / 24;
4562236b 1870 break;
cc4d99b8
CL		 1871 default:
1872 ASSERT(0);
4562236b 1873 break;
cc4d99b8 1874 }
4562236b 1875 }
4562236b
HW		 1876 return normalized_pix_clk;
1877}
1878
0971c40e 1879static void calculate_phy_pix_clks(struct dc_stream_state *stream)
4562236b 1880{
9345d987
AG		 1881 /* update actual pixel clock on all streams */
1882 if (dc_is_hdmi_signal(stream->signal))
1883 stream->phy_pix_clk = get_norm_pix_clk(
380604e2 1884 &stream->timing) / 10;
9345d987
AG		 1885 else
1886 stream->phy_pix_clk =
380604e2 1887 stream->timing.pix_clk_100hz / 10;
39c03e00
CL		 1888
1889 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1890 stream->phy_pix_clk *= 2;
4562236b
HW		 1891}
1892
d2d7885f
AK		 1893static int acquire_resource_from_hw_enabled_state(
1894 struct resource_context *res_ctx,
1895 const struct resource_pool *pool,
1896 struct dc_stream_state *stream)
1897{
1898 struct dc_link *link = stream->link;
1899 unsigned int inst;
1900
1901 /* Check for enabled DIG to identify enabled display */
1902 if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
1903 return -1;
1904
1905 /* Check for which front end is used by this encoder.
1906 * Note the inst is 1 indexed, where 0 is undefined.
1907 * Note that DIG_FE can source from different OTG but our
1908 * current implementation always map 1-to-1, so this code makes
1909 * the same assumption and doesn't check OTG source.
1910 */
1911 inst = link->link_enc->funcs->get_dig_frontend(link->link_enc) - 1;
1912
1913 /* Instance should be within the range of the pool */
1914 if (inst >= pool->pipe_count)
1915 return -1;
1916
1917 if (!res_ctx->pipe_ctx[inst].stream) {
1918 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[inst];
1919
1920 pipe_ctx->stream_res.tg = pool->timing_generators[inst];
1921 pipe_ctx->plane_res.mi = pool->mis[inst];
1922 pipe_ctx->plane_res.hubp = pool->hubps[inst];
1923 pipe_ctx->plane_res.ipp = pool->ipps[inst];
1924 pipe_ctx->plane_res.xfm = pool->transforms[inst];
1925 pipe_ctx->plane_res.dpp = pool->dpps[inst];
1926 pipe_ctx->stream_res.opp = pool->opps[inst];
1927 if (pool->dpps[inst])
1928 pipe_ctx->plane_res.mpcc_inst = pool->dpps[inst]->inst;
1929 pipe_ctx->pipe_idx = inst;
1930
1931 pipe_ctx->stream = stream;
1932 return inst;
1933 }
1934
1935 return -1;
1936}
1937
4562236b 1938enum dc_status resource_map_pool_resources(
fb3466a4 1939 const struct dc *dc,
608ac7bb 1940 struct dc_state *context,
1dc90497 1941 struct dc_stream_state *stream)
4562236b 1942{
a2b8659d 1943 const struct resource_pool *pool = dc->res_pool;
1dc90497
AG		 1944 int i;
1945 struct dc_context *dc_ctx = dc->ctx;
1946 struct pipe_ctx *pipe_ctx = NULL;
1947 int pipe_idx = -1;
46570f09 1948 struct dc_bios *dcb = dc->ctx->dc_bios;
4562236b 1949
1dc90497
AG		 1950 /* TODO Check if this is needed */
1951 /*if (!resource_is_stream_unchanged(old_context, stream)) {
430ef426 1952 if (stream != NULL && old_context->streams[i] != NULL) {
4b679bc3 1953 stream->bit_depth_params =
430ef426
DL		 1954 old_context->streams[i]->bit_depth_params;
1955 stream->clamping = old_context->streams[i]->clamping;
a2b8659d
TC		 1956 continue;
1957 }
4b679bc3 1958 }
1dc90497 1959 */
7e2fe319 1960
08e1c28d
YMM		 1961 calculate_phy_pix_clks(stream);
1962
46570f09
AK		 1963 /* TODO: Check Linux */
1964 if (dc->config.allow_seamless_boot_optimization &&
1965 !dcb->funcs->is_accelerated_mode(dcb)) {
1966 if (dc_validate_seamless_boot_timing(dc, stream->sink, &stream->timing))
1967 stream->apply_seamless_boot_optimization = true;
1968 }
1969
d2d7885f
AK		 1970 if (stream->apply_seamless_boot_optimization)
1971 pipe_idx = acquire_resource_from_hw_enabled_state(
1972 &context->res_ctx,
1973 pool,
1974 stream);
1975
1976 if (pipe_idx < 0)
1977 /* acquire new resources */
1978 pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream);
8c737fcc 1979
dc37a9a0 1980#ifdef CONFIG_DRM_AMD_DC_DCN1_0
1dc90497 1981 if (pipe_idx < 0)
13ab1b44 1982 pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
94c6d735 1983#endif
13ab1b44 1984
c5b38aec 1985 if (pipe_idx < 0 || context->res_ctx.pipe_ctx[pipe_idx].stream_res.tg == NULL)
1dc90497
AG		 1986 return DC_NO_CONTROLLER_RESOURCE;
1987
1988 pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
1989
1990 pipe_ctx->stream_res.stream_enc =
78cc70b1 1991 dc->res_pool->funcs->find_first_free_match_stream_enc_for_link(
1dc90497
AG		 1992 &context->res_ctx, pool, stream);
1993
1994 if (!pipe_ctx->stream_res.stream_enc)
38684e46 1995 return DC_NO_STREAM_ENC_RESOURCE;
1dc90497
AG		 1996
1997 update_stream_engine_usage(
1998 &context->res_ctx, pool,
1999 pipe_ctx->stream_res.stream_enc,
2000 true);
2001
2002 /* TODO: Add check if ASIC support and EDID audio */
ceb3dbb4 2003 if (!stream->converter_disable_audio &&
1dc90497 2004 dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&
ce08aad3 2005 stream->audio_info.mode_count && stream->audio_info.flags.all) {
1dc90497 2006 pipe_ctx->stream_res.audio = find_first_free_audio(
cfb071f7 2007 &context->res_ctx, pool, pipe_ctx->stream_res.stream_enc->id);
1dc90497
AG		 2008
2009 /*
2010 * Audio assigned in order first come first get.
2011 * There are asics which has number of audio
2012 * resources less then number of pipes
2013 */
2014 if (pipe_ctx->stream_res.audio)
2015 update_audio_usage(&context->res_ctx, pool,
2016 pipe_ctx->stream_res.audio, true);
2017 }
268cadbd 2018
9aef1a31
S		 2019 /* Add ABM to the resource if on EDP */
2020 if (pipe_ctx->stream && dc_is_embedded_signal(pipe_ctx->stream->signal))
2021 pipe_ctx->stream_res.abm = pool->abm;
2022
1dc90497
AG		 2023 for (i = 0; i < context->stream_count; i++)
2024 if (context->streams[i] == stream) {
2025 context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst;
0f0bdca5 2026 context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.stream_enc->id;
5fdb7c4c
NK		 2027 context->stream_status[i].audio_inst =
2028 pipe_ctx->stream_res.audio ? pipe_ctx->stream_res.audio->inst : -1;
2029
1dc90497
AG		 2030 return DC_OK;
2031 }
4562236b 2032
1dc90497
AG		 2033 DC_ERROR("Stream %p not found in new ctx!\n", stream);
2034 return DC_ERROR_UNEXPECTED;
2035}
4562236b 2036
2119aa17
DF		 2037/**
2038 * dc_resource_state_copy_construct_current() - Creates a new dc_state from existing state
2039 * Is a shallow copy. Increments refcounts on existing streams and planes.
2040 * @dc: copy out of dc->current_state
2041 * @dst_ctx: copy into this
2042 */
f36cc577 2043void dc_resource_state_copy_construct_current(
1dc90497 2044 const struct dc *dc,
608ac7bb 2045 struct dc_state *dst_ctx)
1dc90497 2046{
f36cc577 2047 dc_resource_state_copy_construct(dc->current_state, dst_ctx);
1dc90497
AG		 2048}
2049
ab8db3e1
AG		 2050
2051void dc_resource_state_construct(
2052 const struct dc *dc,
2053 struct dc_state *dst_ctx)
2054{
dc88b4a6 2055 dst_ctx->clk_mgr = dc->clk_mgr;
ab8db3e1
AG		 2056}
2057
2119aa17
DF		 2058/**
2059 * dc_validate_global_state() - Determine if HW can support a given state
2060 * Checks HW resource availability and bandwidth requirement.
2061 * @dc: dc struct for this driver
2062 * @new_ctx: state to be validated
afcd526b 2063 * @fast_validate: set to true if only yes/no to support matters
2119aa17
DF		 2064 *
2065 * Return: DC_OK if the result can be programmed. Otherwise, an error code.
2066 */
e750d56d 2067enum dc_status dc_validate_global_state(
1dc90497 2068 struct dc *dc,
afcd526b
JA		 2069 struct dc_state *new_ctx,
2070 bool fast_validate)
4562236b 2071{
1dc90497 2072 enum dc_status result = DC_ERROR_UNEXPECTED;
1dc90497 2073 int i, j;
4562236b 2074
e41ab030
HW		 2075 if (!new_ctx)
2076 return DC_ERROR_UNEXPECTED;
2077
d596e5d0 2078 if (dc->res_pool->funcs->validate_global) {
ada8ce15
HW		 2079 result = dc->res_pool->funcs->validate_global(dc, new_ctx);
2080 if (result != DC_OK)
2081 return result;
d596e5d0 2082 }
4562236b 2083
e41ab030 2084 for (i = 0; i < new_ctx->stream_count; i++) {
1dc90497
AG		 2085 struct dc_stream_state *stream = new_ctx->streams[i];
2086
2087 for (j = 0; j < dc->res_pool->pipe_count; j++) {
2088 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[j];
2089
2090 if (pipe_ctx->stream != stream)
2091 continue;
2092
74eac5f3
SSC		 2093 if (dc->res_pool->funcs->get_default_swizzle_mode &&
2094 pipe_ctx->plane_state &&
2095 pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) {
2096 result = dc->res_pool->funcs->get_default_swizzle_mode(pipe_ctx->plane_state);
2097 if (result != DC_OK)
2098 return result;
2099 }
2100
1dc90497
AG		 2101 /* Switch to dp clock source only if there is
2102 * no non dp stream that shares the same timing
2103 * with the dp stream.
2104 */
2105 if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
2106 !find_pll_sharable_stream(stream, new_ctx)) {
2107
9d0dcecd 2108 resource_unreference_clock_source(
1dc90497
AG		 2109 &new_ctx->res_ctx,
2110 dc->res_pool,
9d0dcecd 2111 pipe_ctx->clock_source);
4a629536 2112
1dc90497
AG		 2113 pipe_ctx->clock_source = dc->res_pool->dp_clock_source;
2114 resource_reference_clock_source(
2115 &new_ctx->res_ctx,
2116 dc->res_pool,
2117 pipe_ctx->clock_source);
2118 }
2119 }
2120 }
2121
1dc90497
AG		 2122 result = resource_build_scaling_params_for_context(dc, new_ctx);
2123
2124 if (result == DC_OK)
afcd526b 2125 if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx, fast_validate))
1dc90497
AG		 2126 result = DC_FAIL_BANDWIDTH_VALIDATE;
2127
2128 return result;
4562236b
HW		 2129}
2130
6e4d6bee 2131static void patch_gamut_packet_checksum(
e09b6473 2132 struct dc_info_packet *gamut_packet)
4562236b 2133{
4562236b 2134 /* For gamut we recalc checksum */
6e4d6bee 2135 if (gamut_packet->valid) {
4562236b
HW		 2136 uint8_t chk_sum = 0;
2137 uint8_t *ptr;
2138 uint8_t i;
2139
4562236b 2140 /*start of the Gamut data. */
6e4d6bee 2141 ptr = &gamut_packet->sb[3];
4562236b 2142
6e4d6bee 2143 for (i = 0; i <= gamut_packet->sb[1]; i++)
4562236b
HW		 2144 chk_sum += ptr[i];
2145
6e4d6bee 2146 gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum);
1646a6fe 2147 }
4562236b
HW		 2148}
2149
2150static void set_avi_info_frame(
e09b6473 2151 struct dc_info_packet *info_packet,
4562236b
HW		 2152 struct pipe_ctx *pipe_ctx)
2153{
0971c40e 2154 struct dc_stream_state *stream = pipe_ctx->stream;
4562236b 2155 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
4562236b
HW		 2156 uint32_t pixel_encoding = 0;
2157 enum scanning_type scan_type = SCANNING_TYPE_NODATA;
2158 enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA;
2159 bool itc = false;
50e27654 2160 uint8_t itc_value = 0;
4562236b 2161 uint8_t cn0_cn1 = 0;
50e27654 2162 unsigned int cn0_cn1_value = 0;
4562236b
HW		 2163 uint8_t *check_sum = NULL;
2164 uint8_t byte_index = 0;
754e3673 2165 union hdmi_info_packet hdmi_info;
50e27654 2166 union display_content_support support = {0};
4fa086b9 2167 unsigned int vic = pipe_ctx->stream->timing.vic;
15e17335 2168 enum dc_timing_3d_format format;
4562236b 2169
754e3673
AK		 2170 memset(&hdmi_info, 0, sizeof(union hdmi_info_packet));
2171
4fa086b9 2172 color_space = pipe_ctx->stream->output_color_space;
e5f2038e 2173 if (color_space == COLOR_SPACE_UNKNOWN)
4fa086b9 2174 color_space = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ?
e5f2038e 2175 COLOR_SPACE_SRGB:COLOR_SPACE_YCBCR709;
4562236b
HW		 2176
2177 /* Initialize header */
e09b6473 2178 hdmi_info.bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI;
4562236b
HW		 2179 /* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall
2180 * not be used in HDMI 2.0 (Section 10.1) */
e09b6473
AK		 2181 hdmi_info.bits.header.version = 2;
2182 hdmi_info.bits.header.length = HDMI_AVI_INFOFRAME_SIZE;
4562236b
HW		 2183
2184 /*
2185 * IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built
2186 * according to HDMI 2.0 spec (Section 10.1)
2187 */
2188
4fa086b9 2189 switch (stream->timing.pixel_encoding) {
4562236b
HW		 2190 case PIXEL_ENCODING_YCBCR422:
2191 pixel_encoding = 1;
2192 break;
2193
2194 case PIXEL_ENCODING_YCBCR444:
2195 pixel_encoding = 2;
2196 break;
2197 case PIXEL_ENCODING_YCBCR420:
2198 pixel_encoding = 3;
2199 break;
2200
2201 case PIXEL_ENCODING_RGB:
2202 default:
2203 pixel_encoding = 0;
2204 }
2205
2206 /* Y0_Y1_Y2 : The pixel encoding */
2207 /* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */
e09b6473 2208 hdmi_info.bits.Y0_Y1_Y2 = pixel_encoding;
4562236b
HW		 2209
2210 /* A0 = 1 Active Format Information valid */
e09b6473 2211 hdmi_info.bits.A0 = ACTIVE_FORMAT_VALID;
4562236b
HW		 2212
2213 /* B0, B1 = 3; Bar info data is valid */
e09b6473 2214 hdmi_info.bits.B0_B1 = BAR_INFO_BOTH_VALID;
4562236b 2215
e09b6473 2216 hdmi_info.bits.SC0_SC1 = PICTURE_SCALING_UNIFORM;
4562236b
HW		 2217
2218 /* S0, S1 : Underscan / Overscan */
2219 /* TODO: un-hardcode scan type */
2220 scan_type = SCANNING_TYPE_UNDERSCAN;
e09b6473 2221 hdmi_info.bits.S0_S1 = scan_type;
4562236b
HW		 2222
2223 /* C0, C1 : Colorimetry */
8fde5884 2224 if (color_space == COLOR_SPACE_YCBCR709 ||
15e17335 2225 color_space == COLOR_SPACE_YCBCR709_LIMITED)
e09b6473 2226 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU709;
8fde5884
CL		 2227 else if (color_space == COLOR_SPACE_YCBCR601 ||
2228 color_space == COLOR_SPACE_YCBCR601_LIMITED)
e09b6473 2229 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU601;
8fde5884 2230 else {
e09b6473 2231 hdmi_info.bits.C0_C1 = COLORIMETRY_NO_DATA;
8fde5884 2232 }
534db198 2233 if (color_space == COLOR_SPACE_2020_RGB_FULLRANGE ||
8fde5884
CL		 2234 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE ||
2235 color_space == COLOR_SPACE_2020_YCBCR) {
e09b6473
AK		 2236 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR;
2237 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
534db198 2238 } else if (color_space == COLOR_SPACE_ADOBERGB) {
e09b6473
AK		 2239 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB;
2240 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
534db198
AZ		 2241 }
2242
4562236b 2243 /* TODO: un-hardcode aspect ratio */
4fa086b9 2244 aspect = stream->timing.aspect_ratio;
4562236b
HW		 2245
2246 switch (aspect) {
2247 case ASPECT_RATIO_4_3:
2248 case ASPECT_RATIO_16_9:
e09b6473 2249 hdmi_info.bits.M0_M1 = aspect;
4562236b
HW		 2250 break;
2251
2252 case ASPECT_RATIO_NO_DATA:
2253 case ASPECT_RATIO_64_27:
2254 case ASPECT_RATIO_256_135:
2255 default:
e09b6473 2256 hdmi_info.bits.M0_M1 = 0;
4562236b
HW		 2257 }
2258
2259 /* Active Format Aspect ratio - same as Picture Aspect Ratio. */
e09b6473 2260 hdmi_info.bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE;
4562236b
HW		 2261
2262 /* TODO: un-hardcode cn0_cn1 and itc */
50e27654 2263
4562236b 2264 cn0_cn1 = 0;
50e27654
ZF		 2265 cn0_cn1_value = 0;
2266
2267 itc = true;
2268 itc_value = 1;
2269
ceb3dbb4 2270 support = stream->content_support;
4562236b
HW		 2271
2272 if (itc) {
50e27654
ZF		 2273 if (!support.bits.valid_content_type) {
2274 cn0_cn1_value = 0;
2275 } else {
2276 if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GRAPHICS) {
2277 if (support.bits.graphics_content == 1) {
2278 cn0_cn1_value = 0;
2279 }
2280 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_PHOTO) {
2281 if (support.bits.photo_content == 1) {
2282 cn0_cn1_value = 1;
2283 } else {
2284 cn0_cn1_value = 0;
2285 itc_value = 0;
2286 }
2287 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_CINEMA) {
2288 if (support.bits.cinema_content == 1) {
2289 cn0_cn1_value = 2;
2290 } else {
2291 cn0_cn1_value = 0;
2292 itc_value = 0;
2293 }
2294 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GAME) {
2295 if (support.bits.game_content == 1) {
2296 cn0_cn1_value = 3;
2297 } else {
2298 cn0_cn1_value = 0;
2299 itc_value = 0;
2300 }
2301 }
2302 }
e09b6473
AK		 2303 hdmi_info.bits.CN0_CN1 = cn0_cn1_value;
2304 hdmi_info.bits.ITC = itc_value;
4562236b
HW		 2305 }
2306
2307 /* TODO : We should handle YCC quantization */
2308 /* but we do not have matrix calculation */
ceb3dbb4
JL		 2309 if (stream->qs_bit == 1 &&
2310 stream->qy_bit == 1) {
50e27654
ZF		 2311 if (color_space == COLOR_SPACE_SRGB ||
2312 color_space == COLOR_SPACE_2020_RGB_FULLRANGE) {
e09b6473
AK		 2313 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_FULL_RANGE;
2314 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_FULL_RANGE;
50e27654
ZF		 2315 } else if (color_space == COLOR_SPACE_SRGB_LIMITED ||
2316 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE) {
e09b6473
AK		 2317 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_LIMITED_RANGE;
2318 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
50e27654 2319 } else {
e09b6473
AK		 2320 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
2321 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
50e27654 2322 }
4562236b 2323 } else {
e09b6473
AK		 2324 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
2325 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
4562236b 2326 }
50e27654 2327
15e17335 2328 ///VIC
4fa086b9 2329 format = stream->timing.timing_3d_format;
15e17335
CL		 2330 /*todo, add 3DStereo support*/
2331 if (format != TIMING_3D_FORMAT_NONE) {
2332 // Based on HDMI specs hdmi vic needs to be converted to cea vic when 3D is enabled
4fa086b9 2333 switch (pipe_ctx->stream->timing.hdmi_vic) {
15e17335
CL		 2334 case 1:
2335 vic = 95;
2336 break;
2337 case 2:
2338 vic = 94;
2339 break;
2340 case 3:
2341 vic = 93;
2342 break;
2343 case 4:
2344 vic = 98;
2345 break;
2346 default:
2347 break;
2348 }
2349 }
efa02336 2350 /* If VIC >= 128, the Source shall use AVI InfoFrame Version 3*/
e09b6473 2351 hdmi_info.bits.VIC0_VIC7 = vic;
efa02336
CP		 2352 if (vic >= 128)
2353 hdmi_info.bits.header.version = 3;
2354 /* If (C1, C0)=(1, 1) and (EC2, EC1, EC0)=(1, 1, 1),
2355 * the Source shall use 20 AVI InfoFrame Version 4
2356 */
2357 if (hdmi_info.bits.C0_C1 == COLORIMETRY_EXTENDED &&
2358 hdmi_info.bits.EC0_EC2 == COLORIMETRYEX_RESERVED) {
2359 hdmi_info.bits.header.version = 4;
2360 hdmi_info.bits.header.length = 14;
2361 }
4562236b
HW		 2362
2363 /* pixel repetition
2364 * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel
2365 * repetition start from 1 */
e09b6473 2366 hdmi_info.bits.PR0_PR3 = 0;
4562236b
HW		 2367
2368 /* Bar Info
2369 * barTop: Line Number of End of Top Bar.
2370 * barBottom: Line Number of Start of Bottom Bar.
2371 * barLeft: Pixel Number of End of Left Bar.
2372 * barRight: Pixel Number of Start of Right Bar. */
e09b6473
AK		 2373 hdmi_info.bits.bar_top = stream->timing.v_border_top;
2374 hdmi_info.bits.bar_bottom = (stream->timing.v_total
4fa086b9 2375 - stream->timing.v_border_bottom + 1);
e09b6473
AK		 2376 hdmi_info.bits.bar_left = stream->timing.h_border_left;
2377 hdmi_info.bits.bar_right = (stream->timing.h_total
4fa086b9 2378 - stream->timing.h_border_right + 1);
4562236b 2379
2f482c4f
CP		 2380 /* Additional Colorimetry Extension
2381 * Used in conduction with C0-C1 and EC0-EC2
2382 * 0 = DCI-P3 RGB (D65)
2383 * 1 = DCI-P3 RGB (theater)
2384 */
2385 hdmi_info.bits.ACE0_ACE3 = 0;
2386
4562236b 2387 /* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */
e09b6473 2388 check_sum = &hdmi_info.packet_raw_data.sb[0];
e8d726b7 2389
efa02336 2390 *check_sum = HDMI_INFOFRAME_TYPE_AVI + hdmi_info.bits.header.length + hdmi_info.bits.header.version;
4562236b 2391
efa02336 2392 for (byte_index = 1; byte_index <= hdmi_info.bits.header.length; byte_index++)
e09b6473 2393 *check_sum += hdmi_info.packet_raw_data.sb[byte_index];
4562236b
HW		 2394
2395 /* one byte complement */
2396 *check_sum = (uint8_t) (0x100 - *check_sum);
2397
2398 /* Store in hw_path_mode */
e09b6473
AK		 2399 info_packet->hb0 = hdmi_info.packet_raw_data.hb0;
2400 info_packet->hb1 = hdmi_info.packet_raw_data.hb1;
2401 info_packet->hb2 = hdmi_info.packet_raw_data.hb2;
4562236b 2402
e09b6473
AK		 2403 for (byte_index = 0; byte_index < sizeof(hdmi_info.packet_raw_data.sb); byte_index++)
2404 info_packet->sb[byte_index] = hdmi_info.packet_raw_data.sb[byte_index];
4562236b
HW		 2405
2406 info_packet->valid = true;
2407}
2408
6e4d6bee 2409static void set_vendor_info_packet(
e09b6473 2410 struct dc_info_packet *info_packet,
0971c40e 2411 struct dc_stream_state *stream)
4562236b 2412{
ecd0136b 2413 /* SPD info packet for FreeSync */
4562236b 2414
ecd0136b
HT		 2415 /* Check if Freesync is supported. Return if false. If true,
2416 * set the corresponding bit in the info packet
2417 */
2418 if (!stream->vsp_infopacket.valid)
4562236b
HW		 2419 return;
2420
ecd0136b 2421 *info_packet = stream->vsp_infopacket;
4562236b
HW		 2422}
2423
6e4d6bee 2424static void set_spd_info_packet(
e09b6473 2425 struct dc_info_packet *info_packet,
0971c40e 2426 struct dc_stream_state *stream)
4562236b
HW		 2427{
2428 /* SPD info packet for FreeSync */
2429
4562236b
HW		 2430 /* Check if Freesync is supported. Return if false. If true,
2431 * set the corresponding bit in the info packet
2432 */
98e6436d 2433 if (!stream->vrr_infopacket.valid)
4562236b
HW		 2434 return;
2435
98e6436d 2436 *info_packet = stream->vrr_infopacket;
4562236b
HW		 2437}
2438
1646a6fe 2439static void set_hdr_static_info_packet(
e09b6473 2440 struct dc_info_packet *info_packet,
0971c40e 2441 struct dc_stream_state *stream)
1646a6fe 2442{
0eeef690 2443 /* HDR Static Metadata info packet for HDR10 */
1646a6fe 2444
a10dc97a
KK		 2445 if (!stream->hdr_static_metadata.valid ||
2446 stream->use_dynamic_meta)
10bff005
YS		 2447 return;
2448
0eeef690 2449 *info_packet = stream->hdr_static_metadata;
1646a6fe
AW		 2450}
2451
6e4d6bee 2452static void set_vsc_info_packet(
e09b6473 2453 struct dc_info_packet *info_packet,
0971c40e 2454 struct dc_stream_state *stream)
4562236b 2455{
1336926f 2456 if (!stream->vsc_infopacket.valid)
4562236b
HW		 2457 return;
2458
1336926f 2459 *info_packet = stream->vsc_infopacket;
4562236b
HW		 2460}
2461
f36cc577 2462void dc_resource_state_destruct(struct dc_state *context)
4562236b
HW		 2463{
2464 int i, j;
2465
ab2541b6 2466 for (i = 0; i < context->stream_count; i++) {
3be5262e
HW		 2467 for (j = 0; j < context->stream_status[i].plane_count; j++)
2468 dc_plane_state_release(
2469 context->stream_status[i].plane_states[j]);
4562236b 2470
3be5262e 2471 context->stream_status[i].plane_count = 0;
4fa086b9 2472 dc_stream_release(context->streams[i]);
ab2541b6 2473 context->streams[i] = NULL;
4562236b
HW		 2474 }
2475}
2476
f36cc577 2477void dc_resource_state_copy_construct(
608ac7bb
JZ		 2478 const struct dc_state *src_ctx,
2479 struct dc_state *dst_ctx)
4562236b
HW		 2480{
2481 int i, j;
8ee5702a 2482 struct kref refcount = dst_ctx->refcount;
4562236b
HW		 2483
2484 *dst_ctx = *src_ctx;
2485
a2b8659d 2486 for (i = 0; i < MAX_PIPES; i++) {
4562236b
HW		 2487 struct pipe_ctx *cur_pipe = &dst_ctx->res_ctx.pipe_ctx[i];
2488
2489 if (cur_pipe->top_pipe)
2490 cur_pipe->top_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
2491
2492 if (cur_pipe->bottom_pipe)
2493 cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
4562236b
HW		 2494 }
2495
ab2541b6 2496 for (i = 0; i < dst_ctx->stream_count; i++) {
4fa086b9 2497 dc_stream_retain(dst_ctx->streams[i]);
3be5262e
HW		 2498 for (j = 0; j < dst_ctx->stream_status[i].plane_count; j++)
2499 dc_plane_state_retain(
2500 dst_ctx->stream_status[i].plane_states[j]);
4562236b 2501 }
9a3afbb3
AG		 2502
2503 /* context refcount should not be overridden */
8ee5702a 2504 dst_ctx->refcount = refcount;
9a3afbb3 2505
4562236b
HW		 2506}
2507
2508struct clock_source *dc_resource_find_first_free_pll(
a2b8659d
TC		 2509 struct resource_context *res_ctx,
2510 const struct resource_pool *pool)
4562236b
HW		 2511{
2512 int i;
2513
a2b8659d 2514 for (i = 0; i < pool->clk_src_count; ++i) {
4562236b 2515 if (res_ctx->clock_source_ref_count[i] == 0)
a2b8659d 2516 return pool->clock_sources[i];
4562236b
HW		 2517 }
2518
2519 return NULL;
2520}
2521
2522void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
2523{
2524 enum signal_type signal = SIGNAL_TYPE_NONE;
96c50c0d 2525 struct encoder_info_frame *info = &pipe_ctx->stream_res.encoder_info_frame;
4562236b
HW		 2526
2527 /* default all packets to invalid */
6e4d6bee
TC		 2528 info->avi.valid = false;
2529 info->gamut.valid = false;
2530 info->vendor.valid = false;
630e3573 2531 info->spd.valid = false;
6e4d6bee
TC		 2532 info->hdrsmd.valid = false;
2533 info->vsc.valid = false;
4562236b
HW		 2534
2535 signal = pipe_ctx->stream->signal;
2536
2537 /* HDMi and DP have different info packets*/
2538 if (dc_is_hdmi_signal(signal)) {
6e4d6bee
TC		 2539 set_avi_info_frame(&info->avi, pipe_ctx);
2540
2541 set_vendor_info_packet(&info->vendor, pipe_ctx->stream);
2542
2543 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2544
56ef6ed9 2545 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
6e4d6bee 2546
a33fa99d 2547 } else if (dc_is_dp_signal(signal)) {
6e4d6bee
TC		 2548 set_vsc_info_packet(&info->vsc, pipe_ctx->stream);
2549
2550 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2551
56ef6ed9 2552 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
a33fa99d 2553 }
4562236b 2554
6e4d6bee 2555 patch_gamut_packet_checksum(&info->gamut);
4562236b
HW		 2556}
2557
2558enum dc_status resource_map_clock_resources(
fb3466a4 2559 const struct dc *dc,
608ac7bb 2560 struct dc_state *context,
1dc90497 2561 struct dc_stream_state *stream)
4562236b 2562{
4562236b 2563 /* acquire new resources */
1dc90497
AG		 2564 const struct resource_pool *pool = dc->res_pool;
2565 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(
2566 &context->res_ctx, stream);
ab2541b6 2567
1dc90497
AG		 2568 if (!pipe_ctx)
2569 return DC_ERROR_UNEXPECTED;
4562236b 2570
1dc90497
AG		 2571 if (dc_is_dp_signal(pipe_ctx->stream->signal)
2572 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)
2573 pipe_ctx->clock_source = pool->dp_clock_source;
2574 else {
2575 pipe_ctx->clock_source = NULL;
4562236b 2576
1dc90497 2577 if (!dc->config.disable_disp_pll_sharing)
4ed4e51b 2578 pipe_ctx->clock_source = resource_find_used_clk_src_for_sharing(
1dc90497
AG		 2579 &context->res_ctx,
2580 pipe_ctx);
4562236b 2581
1dc90497
AG		 2582 if (pipe_ctx->clock_source == NULL)
2583 pipe_ctx->clock_source =
2584 dc_resource_find_first_free_pll(
2585 &context->res_ctx,
2586 pool);
2587 }
4562236b 2588
1dc90497
AG		 2589 if (pipe_ctx->clock_source == NULL)
2590 return DC_NO_CLOCK_SOURCE_RESOURCE;
4562236b 2591
1dc90497
AG		 2592 resource_reference_clock_source(
2593 &context->res_ctx, pool,
2594 pipe_ctx->clock_source);
4562236b
HW		 2595
2596 return DC_OK;
2597}
2598
2599/*
2600 * Note: We need to disable output if clock sources change,
2601 * since bios does optimization and doesn't apply if changing
2602 * PHY when not already disabled.
2603 */
2604bool pipe_need_reprogram(
2605 struct pipe_ctx *pipe_ctx_old,
2606 struct pipe_ctx *pipe_ctx)
2607{
cfe4645e
DL		 2608 if (!pipe_ctx_old->stream)
2609 return false;
2610
4562236b
HW		 2611 if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink)
2612 return true;
2613
2614 if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal)
2615 return true;
2616
afaacef4 2617 if (pipe_ctx_old->stream_res.audio != pipe_ctx->stream_res.audio)
4562236b
HW		 2618 return true;
2619
2620 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source
2621 && pipe_ctx_old->stream != pipe_ctx->stream)
2622 return true;
2623
8e9c4c8c 2624 if (pipe_ctx_old->stream_res.stream_enc != pipe_ctx->stream_res.stream_enc)
4562236b
HW		 2625 return true;
2626
2627 if (is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2628 return true;
2629
6b622181
JP		 2630 if (is_hdr_static_meta_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2631 return true;
4562236b 2632
1e7e86c4
ST		 2633 if (pipe_ctx_old->stream->dpms_off != pipe_ctx->stream->dpms_off)
2634 return true;
2635
1336926f
A		 2636 if (is_vsc_info_packet_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2637 return true;
2638
eed928dc
CL		 2639 if (false == pipe_ctx_old->stream->link->link_state_valid &&
2640 false == pipe_ctx_old->stream->dpms_off)
2641 return true;
2642
4562236b
HW		 2643 return false;
2644}
529cad0f 2645
0971c40e 2646void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream,
529cad0f
DW		 2647 struct bit_depth_reduction_params *fmt_bit_depth)
2648{
4fa086b9 2649 enum dc_dither_option option = stream->dither_option;
529cad0f 2650 enum dc_pixel_encoding pixel_encoding =
4fa086b9 2651 stream->timing.pixel_encoding;
529cad0f
DW		 2652
2653 memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth));
2654
603767f9
TC		 2655 if (option == DITHER_OPTION_DEFAULT) {
2656 switch (stream->timing.display_color_depth) {
2657 case COLOR_DEPTH_666:
2658 option = DITHER_OPTION_SPATIAL6;
2659 break;
2660 case COLOR_DEPTH_888:
2661 option = DITHER_OPTION_SPATIAL8;
2662 break;
2663 case COLOR_DEPTH_101010:
2664 option = DITHER_OPTION_SPATIAL10;
2665 break;
2666 default:
2667 option = DITHER_OPTION_DISABLE;
2668 }
2669 }
2670
529cad0f
DW		 2671 if (option == DITHER_OPTION_DISABLE)
2672 return;
2673
2674 if (option == DITHER_OPTION_TRUN6) {
2675 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2676 fmt_bit_depth->flags.TRUNCATE_DEPTH = 0;
2677 } else if (option == DITHER_OPTION_TRUN8 ||
2678 option == DITHER_OPTION_TRUN8_SPATIAL6 ||
2679 option == DITHER_OPTION_TRUN8_FM6) {
2680 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2681 fmt_bit_depth->flags.TRUNCATE_DEPTH = 1;
2682 } else if (option == DITHER_OPTION_TRUN10 ||
2683 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
2684 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
2685 option == DITHER_OPTION_TRUN10_FM8 ||
2686 option == DITHER_OPTION_TRUN10_FM6 ||
2687 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2688 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2689 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2690 }
2691
2692 /* special case - Formatter can only reduce by 4 bits at most.
2693 * When reducing from 12 to 6 bits,
2694 * HW recommends we use trunc with round mode
2695 * (if we did nothing, trunc to 10 bits would be used)
2696 * note that any 12->10 bit reduction is ignored prior to DCE8,
2697 * as the input was 10 bits.
2698 */
2699 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2700 option == DITHER_OPTION_SPATIAL6 ||
2701 option == DITHER_OPTION_FM6) {
2702 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2703 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2704 fmt_bit_depth->flags.TRUNCATE_MODE = 1;
2705 }
2706
2707 /* spatial dither
2708 * note that spatial modes 1-3 are never used
2709 */
2710 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2711 option == DITHER_OPTION_SPATIAL6 ||
2712 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
2713 option == DITHER_OPTION_TRUN8_SPATIAL6) {
2714 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2715 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 0;
2716 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2717 fmt_bit_depth->flags.RGB_RANDOM =
2718 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2719 } else if (option == DITHER_OPTION_SPATIAL8_FRAME_RANDOM ||
2720 option == DITHER_OPTION_SPATIAL8 ||
2721 option == DITHER_OPTION_SPATIAL8_FM6 ||
2722 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
2723 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2724 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2725 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 1;
2726 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2727 fmt_bit_depth->flags.RGB_RANDOM =
2728 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2729 } else if (option == DITHER_OPTION_SPATIAL10_FRAME_RANDOM ||
2730 option == DITHER_OPTION_SPATIAL10 ||
2731 option == DITHER_OPTION_SPATIAL10_FM8 ||
2732 option == DITHER_OPTION_SPATIAL10_FM6) {
2733 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2734 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 2;
2735 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2736 fmt_bit_depth->flags.RGB_RANDOM =
2737 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2738 }
2739
2740 if (option == DITHER_OPTION_SPATIAL6 ||
2741 option == DITHER_OPTION_SPATIAL8 ||
2742 option == DITHER_OPTION_SPATIAL10) {
2743 fmt_bit_depth->flags.FRAME_RANDOM = 0;
2744 } else {
2745 fmt_bit_depth->flags.FRAME_RANDOM = 1;
2746 }
2747
2748 //////////////////////
2749 //// temporal dither
2750 //////////////////////
2751 if (option == DITHER_OPTION_FM6 ||
2752 option == DITHER_OPTION_SPATIAL8_FM6 ||
2753 option == DITHER_OPTION_SPATIAL10_FM6 ||
2754 option == DITHER_OPTION_TRUN10_FM6 ||
2755 option == DITHER_OPTION_TRUN8_FM6 ||
2756 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2757 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2758 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 0;
2759 } else if (option == DITHER_OPTION_FM8 ||
2760 option == DITHER_OPTION_SPATIAL10_FM8 ||
2761 option == DITHER_OPTION_TRUN10_FM8) {
2762 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2763 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 1;
2764 } else if (option == DITHER_OPTION_FM10) {
2765 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2766 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 2;
2767 }
2768
2769 fmt_bit_depth->pixel_encoding = pixel_encoding;
2770}
9345d987 2771
62c933f9 2772enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream)
9345d987 2773{
fb3466a4 2774 struct dc *core_dc = dc;
ceb3dbb4 2775 struct dc_link *link = stream->link;
9345d987
AG		 2776 struct timing_generator *tg = core_dc->res_pool->timing_generators[0];
2777 enum dc_status res = DC_OK;
2778
4fa086b9 2779 calculate_phy_pix_clks(stream);
9345d987 2780
4fa086b9 2781 if (!tg->funcs->validate_timing(tg, &stream->timing))
9345d987
AG		 2782 res = DC_FAIL_CONTROLLER_VALIDATE;
2783
248cbed6 2784 if (res == DC_OK) {
9345d987 2785 if (!link->link_enc->funcs->validate_output_with_stream(
4fa086b9 2786 link->link_enc, stream))
9345d987 2787 res = DC_FAIL_ENC_VALIDATE;
248cbed6 2788 }
9345d987
AG		 2789
2790 /* TODO: validate audio ASIC caps, encoder */
2791
2792 if (res == DC_OK)
4fa086b9 2793 res = dc_link_validate_mode_timing(stream,
9345d987 2794 link,
4fa086b9 2795 &stream->timing);
9345d987 2796
62c933f9 2797 return res;
9345d987 2798}
792671d7 2799
62c933f9 2800enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state)
792671d7 2801{
62c933f9
YS		 2802 enum dc_status res = DC_OK;
2803
792671d7 2804 /* TODO For now validates pixel format only */
8e7095b9 2805 if (dc->res_pool->funcs->validate_plane)
62c933f9 2806 return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps);
792671d7 2807
62c933f9 2808 return res;
792671d7 2809}
74eac5f3
SSC		 2810
2811unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format)
2812{
2813 switch (format) {
2814 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
2815 return 8;
2816 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
2817 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
2818 return 12;
2819 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
2820 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
2821 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
2822 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
2823 return 16;
2824 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
2825 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
2826 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
2827 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
2828 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
2829 return 32;
2830 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
2831 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
2832 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
2833 return 64;
2834 default:
2835 ASSERT_CRITICAL(false);
2836 return -1;
2837 }
2838}
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