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drm/amd/display: Set addressable region as active + border
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / display / dc / core / dc_resource.c
CommitLineData
4562236b
HW		 1/*
2* Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25#include "dm_services.h"
26
27#include "resource.h"
28#include "include/irq_service_interface.h"
29#include "link_encoder.h"
30#include "stream_encoder.h"
31#include "opp.h"
32#include "timing_generator.h"
33#include "transform.h"
d94585a0 34#include "dpp.h"
5ac3d3c9 35#include "core_types.h"
4562236b 36#include "set_mode_types.h"
4562236b
HW		 37#include "virtual/virtual_stream_encoder.h"
38
39#include "dce80/dce80_resource.h"
40#include "dce100/dce100_resource.h"
41#include "dce110/dce110_resource.h"
42#include "dce112/dce112_resource.h"
ff5ef992
AD		 43#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
44#include "dcn10/dcn10_resource.h"
45#endif
2c8ad2d5 46#include "dce120/dce120_resource.h"
4562236b
HW		 47
48enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
49{
50 enum dce_version dc_version = DCE_VERSION_UNKNOWN;
51 switch (asic_id.chip_family) {
52
53 case FAMILY_CI:
4562236b
HW		 54 dc_version = DCE_VERSION_8_0;
55 break;
ebfdf0d0
AD		 56 case FAMILY_KV:
57 if (ASIC_REV_IS_KALINDI(asic_id.hw_internal_rev) ||
58 ASIC_REV_IS_BHAVANI(asic_id.hw_internal_rev) ||
59 ASIC_REV_IS_GODAVARI(asic_id.hw_internal_rev))
60 dc_version = DCE_VERSION_8_3;
61 else
62 dc_version = DCE_VERSION_8_1;
63 break;
4562236b
HW		 64 case FAMILY_CZ:
65 dc_version = DCE_VERSION_11_0;
66 break;
67
68 case FAMILY_VI:
69 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
70 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
71 dc_version = DCE_VERSION_10_0;
72 break;
73 }
74 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
b264d345
JL		 75 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
76 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
4562236b
HW		 77 dc_version = DCE_VERSION_11_2;
78 }
79 break;
2c8ad2d5
AD		 80 case FAMILY_AI:
81 dc_version = DCE_VERSION_12_0;
82 break;
ff5ef992
AD		 83#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
84 case FAMILY_RV:
85 dc_version = DCN_VERSION_1_0;
86 break;
87#endif
4562236b
HW		 88 default:
89 dc_version = DCE_VERSION_UNKNOWN;
90 break;
91 }
92 return dc_version;
93}
94
95struct resource_pool *dc_create_resource_pool(
fb3466a4 96 struct dc *dc,
4562236b
HW		 97 int num_virtual_links,
98 enum dce_version dc_version,
99 struct hw_asic_id asic_id)
100{
5ac3d3c9 101 struct resource_pool *res_pool = NULL;
4562236b
HW		 102
103 switch (dc_version) {
104 case DCE_VERSION_8_0:
7992a629
AD		 105 res_pool = dce80_create_resource_pool(
106 num_virtual_links, dc);
107 break;
ebfdf0d0 108 case DCE_VERSION_8_1:
7992a629
AD		 109 res_pool = dce81_create_resource_pool(
110 num_virtual_links, dc);
111 break;
ebfdf0d0 112 case DCE_VERSION_8_3:
7992a629 113 res_pool = dce83_create_resource_pool(
4562236b 114 num_virtual_links, dc);
5ac3d3c9 115 break;
4562236b 116 case DCE_VERSION_10_0:
5ac3d3c9 117 res_pool = dce100_create_resource_pool(
4562236b 118 num_virtual_links, dc);
5ac3d3c9 119 break;
4562236b 120 case DCE_VERSION_11_0:
5ac3d3c9 121 res_pool = dce110_create_resource_pool(
4562236b 122 num_virtual_links, dc, asic_id);
5ac3d3c9 123 break;
4562236b 124 case DCE_VERSION_11_2:
5ac3d3c9 125 res_pool = dce112_create_resource_pool(
4562236b 126 num_virtual_links, dc);
5ac3d3c9 127 break;
2c8ad2d5
AD		 128 case DCE_VERSION_12_0:
129 res_pool = dce120_create_resource_pool(
130 num_virtual_links, dc);
131 break;
ff5ef992
AD		 132
133#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
134 case DCN_VERSION_1_0:
135 res_pool = dcn10_create_resource_pool(
503a7c6f 136 num_virtual_links, dc);
ff5ef992
AD		 137 break;
138#endif
3639fa68
ZF		 139
140
4562236b
HW		 141 default:
142 break;
143 }
5ac3d3c9 144 if (res_pool != NULL) {
1515a47b 145 struct dc_firmware_info fw_info = { { 0 } };
5ac3d3c9
CL		 146
147 if (dc->ctx->dc_bios->funcs->get_firmware_info(
148 dc->ctx->dc_bios, &fw_info) == BP_RESULT_OK) {
149 res_pool->ref_clock_inKhz = fw_info.pll_info.crystal_frequency;
150 } else
151 ASSERT_CRITICAL(false);
152 }
4562236b 153
5ac3d3c9 154 return res_pool;
4562236b
HW		 155}
156
fb3466a4 157void dc_destroy_resource_pool(struct dc *dc)
4562236b
HW		 158{
159 if (dc) {
160 if (dc->res_pool)
161 dc->res_pool->funcs->destroy(&dc->res_pool);
162
d029810c 163 kfree(dc->hwseq);
4562236b
HW		 164 }
165}
166
167static void update_num_audio(
168 const struct resource_straps *straps,
169 unsigned int *num_audio,
170 struct audio_support *aud_support)
171{
b8e9eb72
CL		 172 aud_support->dp_audio = true;
173 aud_support->hdmi_audio_native = false;
174 aud_support->hdmi_audio_on_dongle = false;
175
4562236b 176 if (straps->hdmi_disable == 0) {
4562236b
HW		 177 if (straps->dc_pinstraps_audio & 0x2) {
178 aud_support->hdmi_audio_on_dongle = true;
b8e9eb72 179 aud_support->hdmi_audio_native = true;
4562236b
HW		 180 }
181 }
182
183 switch (straps->audio_stream_number) {
184 case 0: /* multi streams supported */
185 break;
186 case 1: /* multi streams not supported */
187 *num_audio = 1;
188 break;
189 default:
190 DC_ERR("DC: unexpected audio fuse!\n");
17a96033 191 }
4562236b
HW		 192}
193
194bool resource_construct(
195 unsigned int num_virtual_links,
fb3466a4 196 struct dc *dc,
4562236b
HW		 197 struct resource_pool *pool,
198 const struct resource_create_funcs *create_funcs)
199{
200 struct dc_context *ctx = dc->ctx;
201 const struct resource_caps *caps = pool->res_cap;
202 int i;
203 unsigned int num_audio = caps->num_audio;
204 struct resource_straps straps = {0};
205
206 if (create_funcs->read_dce_straps)
207 create_funcs->read_dce_straps(dc->ctx, &straps);
208
209 pool->audio_count = 0;
210 if (create_funcs->create_audio) {
211 /* find the total number of streams available via the
212 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
213 * registers (one for each pin) starting from pin 1
214 * up to the max number of audio pins.
215 * We stop on the first pin where
216 * PORT_CONNECTIVITY == 1 (as instructed by HW team).
217 */
218 update_num_audio(&straps, &num_audio, &pool->audio_support);
219 for (i = 0; i < pool->pipe_count && i < num_audio; i++) {
220 struct audio *aud = create_funcs->create_audio(ctx, i);
221
222 if (aud == NULL) {
223 DC_ERR("DC: failed to create audio!\n");
224 return false;
225 }
226
227 if (!aud->funcs->endpoint_valid(aud)) {
228 aud->funcs->destroy(&aud);
229 break;
230 }
231
232 pool->audios[i] = aud;
233 pool->audio_count++;
234 }
235 }
236
237 pool->stream_enc_count = 0;
238 if (create_funcs->create_stream_encoder) {
239 for (i = 0; i < caps->num_stream_encoder; i++) {
240 pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx);
241 if (pool->stream_enc[i] == NULL)
242 DC_ERR("DC: failed to create stream_encoder!\n");
243 pool->stream_enc_count++;
244 }
245 }
4176664b
CL		 246 dc->caps.dynamic_audio = false;
247 if (pool->audio_count < pool->stream_enc_count) {
248 dc->caps.dynamic_audio = true;
249 }
4562236b
HW		 250 for (i = 0; i < num_virtual_links; i++) {
251 pool->stream_enc[pool->stream_enc_count] =
252 virtual_stream_encoder_create(
253 ctx, ctx->dc_bios);
254 if (pool->stream_enc[pool->stream_enc_count] == NULL) {
255 DC_ERR("DC: failed to create stream_encoder!\n");
256 return false;
257 }
258 pool->stream_enc_count++;
259 }
260
261 dc->hwseq = create_funcs->create_hwseq(ctx);
262
263 return true;
264}
265
266
21e67d4d 267void resource_unreference_clock_source(
4562236b 268 struct resource_context *res_ctx,
a2b8659d 269 const struct resource_pool *pool,
4a629536 270 struct clock_source *clock_source)
4562236b
HW		 271{
272 int i;
4a629536 273
a2b8659d 274 for (i = 0; i < pool->clk_src_count; i++) {
4a629536 275 if (pool->clock_sources[i] != clock_source)
4562236b
HW		 276 continue;
277
278 res_ctx->clock_source_ref_count[i]--;
279
4562236b
HW		 280 break;
281 }
282
21e67d4d 283 if (pool->dp_clock_source == clock_source)
4562236b 284 res_ctx->dp_clock_source_ref_count--;
4562236b
HW		 285}
286
287void resource_reference_clock_source(
288 struct resource_context *res_ctx,
a2b8659d 289 const struct resource_pool *pool,
4562236b
HW		 290 struct clock_source *clock_source)
291{
292 int i;
a2b8659d
TC		 293 for (i = 0; i < pool->clk_src_count; i++) {
294 if (pool->clock_sources[i] != clock_source)
4562236b
HW		 295 continue;
296
297 res_ctx->clock_source_ref_count[i]++;
298 break;
299 }
300
a2b8659d 301 if (pool->dp_clock_source == clock_source)
4562236b
HW		 302 res_ctx->dp_clock_source_ref_count++;
303}
304
305bool resource_are_streams_timing_synchronizable(
0971c40e
HW		 306 struct dc_stream_state *stream1,
307 struct dc_stream_state *stream2)
4562236b 308{
4fa086b9 309 if (stream1->timing.h_total != stream2->timing.h_total)
4562236b
HW		 310 return false;
311
4fa086b9 312 if (stream1->timing.v_total != stream2->timing.v_total)
4562236b
HW		 313 return false;
314
4fa086b9
LSL		 315 if (stream1->timing.h_addressable
316 != stream2->timing.h_addressable)
4562236b
HW		 317 return false;
318
4fa086b9
LSL		 319 if (stream1->timing.v_addressable
320 != stream2->timing.v_addressable)
4562236b
HW		 321 return false;
322
4fa086b9
LSL		 323 if (stream1->timing.pix_clk_khz
324 != stream2->timing.pix_clk_khz)
4562236b
HW		 325 return false;
326
327 if (stream1->phy_pix_clk != stream2->phy_pix_clk
7e2fe319
CL		 328 && (!dc_is_dp_signal(stream1->signal)
329 || !dc_is_dp_signal(stream2->signal)))
4562236b
HW		 330 return false;
331
332 return true;
333}
334
335static bool is_sharable_clk_src(
336 const struct pipe_ctx *pipe_with_clk_src,
337 const struct pipe_ctx *pipe)
338{
339 if (pipe_with_clk_src->clock_source == NULL)
340 return false;
341
342 if (pipe_with_clk_src->stream->signal == SIGNAL_TYPE_VIRTUAL)
343 return false;
344
345 if (dc_is_dp_signal(pipe_with_clk_src->stream->signal))
346 return false;
347
348 if (dc_is_hdmi_signal(pipe_with_clk_src->stream->signal)
349 && dc_is_dvi_signal(pipe->stream->signal))
350 return false;
351
352 if (dc_is_hdmi_signal(pipe->stream->signal)
353 && dc_is_dvi_signal(pipe_with_clk_src->stream->signal))
354 return false;
355
356 if (!resource_are_streams_timing_synchronizable(
357 pipe_with_clk_src->stream, pipe->stream))
358 return false;
359
360 return true;
361}
362
363struct clock_source *resource_find_used_clk_src_for_sharing(
364 struct resource_context *res_ctx,
365 struct pipe_ctx *pipe_ctx)
366{
367 int i;
368
369 for (i = 0; i < MAX_PIPES; i++) {
370 if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx))
371 return res_ctx->pipe_ctx[i].clock_source;
372 }
373
374 return NULL;
375}
376
377static enum pixel_format convert_pixel_format_to_dalsurface(
378 enum surface_pixel_format surface_pixel_format)
379{
380 enum pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
381
382 switch (surface_pixel_format) {
383 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
384 dal_pixel_format = PIXEL_FORMAT_INDEX8;
385 break;
386 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
387 dal_pixel_format = PIXEL_FORMAT_RGB565;
388 break;
389 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
390 dal_pixel_format = PIXEL_FORMAT_RGB565;
391 break;
392 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
393 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
394 break;
8693049a 395 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
4562236b
HW		 396 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
397 break;
398 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
399 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
400 break;
401 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
402 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
403 break;
404 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
405 dal_pixel_format = PIXEL_FORMAT_ARGB2101010_XRBIAS;
406 break;
407 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
408 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
409 dal_pixel_format = PIXEL_FORMAT_FP16;
410 break;
411 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
4562236b 412 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
87449a90 413 dal_pixel_format = PIXEL_FORMAT_420BPP8;
4562236b 414 break;
ffbcd19a
VP		 415 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
416 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
87449a90 417 dal_pixel_format = PIXEL_FORMAT_420BPP10;
ffbcd19a 418 break;
4562236b
HW		 419 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
420 default:
421 dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
422 break;
423 }
424 return dal_pixel_format;
425}
426
427static void rect_swap_helper(struct rect *rect)
428{
429 uint32_t temp = 0;
430
431 temp = rect->height;
432 rect->height = rect->width;
433 rect->width = temp;
434
435 temp = rect->x;
436 rect->x = rect->y;
437 rect->y = temp;
438}
439
b2d0a103 440static void calculate_viewport(struct pipe_ctx *pipe_ctx)
4562236b 441{
3be5262e 442 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 443 const struct dc_stream_state *stream = pipe_ctx->stream;
6702a9ac 444 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
3be5262e 445 struct rect surf_src = plane_state->src_rect;
1fbd2cfc 446 struct rect clip = { 0 };
87449a90
AK		 447 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
448 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
1fbd2cfc 449 bool pri_split = pipe_ctx->bottom_pipe &&
3be5262e 450 pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state;
1fbd2cfc 451 bool sec_split = pipe_ctx->top_pipe &&
3be5262e 452 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
4562236b 453
7f5c22d1
VP		 454 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE ||
455 stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) {
7b779c99
VP		 456 pri_split = false;
457 sec_split = false;
458 }
86006a7f 459
3be5262e
HW		 460 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
461 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
86006a7f
DL		 462 rect_swap_helper(&surf_src);
463
4562236b
HW		 464 /* The actual clip is an intersection between stream
465 * source and surface clip
466 */
3be5262e
HW		 467 clip.x = stream->src.x > plane_state->clip_rect.x ?
468 stream->src.x : plane_state->clip_rect.x;
4562236b 469
1fbd2cfc 470 clip.width = stream->src.x + stream->src.width <
3be5262e 471 plane_state->clip_rect.x + plane_state->clip_rect.width ?
1fbd2cfc 472 stream->src.x + stream->src.width - clip.x :
3be5262e 473 plane_state->clip_rect.x + plane_state->clip_rect.width - clip.x ;
4562236b 474
3be5262e
HW		 475 clip.y = stream->src.y > plane_state->clip_rect.y ?
476 stream->src.y : plane_state->clip_rect.y;
4562236b 477
1fbd2cfc 478 clip.height = stream->src.y + stream->src.height <
3be5262e 479 plane_state->clip_rect.y + plane_state->clip_rect.height ?
1fbd2cfc 480 stream->src.y + stream->src.height - clip.y :
3be5262e 481 plane_state->clip_rect.y + plane_state->clip_rect.height - clip.y ;
4562236b 482
86006a7f 483 /* offset = surf_src.ofs + (clip.ofs - surface->dst_rect.ofs) * scl_ratio
4562236b
HW		 484 * num_pixels = clip.num_pix * scl_ratio
485 */
3be5262e
HW		 486 data->viewport.x = surf_src.x + (clip.x - plane_state->dst_rect.x) *
487 surf_src.width / plane_state->dst_rect.width;
b2d0a103 488 data->viewport.width = clip.width *
3be5262e 489 surf_src.width / plane_state->dst_rect.width;
4562236b 490
3be5262e
HW		 491 data->viewport.y = surf_src.y + (clip.y - plane_state->dst_rect.y) *
492 surf_src.height / plane_state->dst_rect.height;
b2d0a103 493 data->viewport.height = clip.height *
3be5262e 494 surf_src.height / plane_state->dst_rect.height;
4562236b 495
b2d0a103
DL		 496 /* Round down, compensate in init */
497 data->viewport_c.x = data->viewport.x / vpc_div;
498 data->viewport_c.y = data->viewport.y / vpc_div;
499 data->inits.h_c = (data->viewport.x % vpc_div) != 0 ?
500 dal_fixed31_32_half : dal_fixed31_32_zero;
501 data->inits.v_c = (data->viewport.y % vpc_div) != 0 ?
502 dal_fixed31_32_half : dal_fixed31_32_zero;
503 /* Round up, assume original video size always even dimensions */
504 data->viewport_c.width = (data->viewport.width + vpc_div - 1) / vpc_div;
505 data->viewport_c.height = (data->viewport.height + vpc_div - 1) / vpc_div;
506
507 /* Handle hsplit */
1fbd2cfc
DL		 508 if (pri_split || sec_split) {
509 /* HMirror XOR Secondary_pipe XOR Rotation_180 */
3be5262e
HW		 510 bool right_view = (sec_split != plane_state->horizontal_mirror) !=
511 (plane_state->rotation == ROTATION_ANGLE_180);
1fbd2cfc 512
3be5262e
HW		 513 if (plane_state->rotation == ROTATION_ANGLE_90
514 || plane_state->rotation == ROTATION_ANGLE_270)
1fbd2cfc 515 /* Secondary_pipe XOR Rotation_270 */
3be5262e 516 right_view = (plane_state->rotation == ROTATION_ANGLE_270) != sec_split;
9e6c74ce
DL		 517
518 if (right_view) {
519 data->viewport.width /= 2;
520 data->viewport_c.width /= 2;
521 data->viewport.x += data->viewport.width;
522 data->viewport_c.x += data->viewport_c.width;
523 /* Ceil offset pipe */
524 data->viewport.width += data->viewport.width % 2;
525 data->viewport_c.width += data->viewport_c.width % 2;
526 } else {
527 data->viewport.width /= 2;
528 data->viewport_c.width /= 2;
529 }
b2d0a103 530 }
1fbd2cfc 531
3be5262e
HW		 532 if (plane_state->rotation == ROTATION_ANGLE_90 ||
533 plane_state->rotation == ROTATION_ANGLE_270) {
1fbd2cfc
DL		 534 rect_swap_helper(&data->viewport_c);
535 rect_swap_helper(&data->viewport);
536 }
4562236b
HW		 537}
538
b2d0a103 539static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip)
4562236b 540{
3be5262e 541 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 542 const struct dc_stream_state *stream = pipe_ctx->stream;
3be5262e
HW		 543 struct rect surf_src = plane_state->src_rect;
544 struct rect surf_clip = plane_state->clip_rect;
c802570e 545 int recout_full_x, recout_full_y;
4562236b 546
3be5262e
HW		 547 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
548 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
86006a7f
DL		 549 rect_swap_helper(&surf_src);
550
6702a9ac 551 pipe_ctx->plane_res.scl_data.recout.x = stream->dst.x;
4fa086b9 552 if (stream->src.x < surf_clip.x)
6702a9ac 553 pipe_ctx->plane_res.scl_data.recout.x += (surf_clip.x
4fa086b9
LSL		 554 - stream->src.x) * stream->dst.width
555 / stream->src.width;
4562236b 556
6702a9ac 557 pipe_ctx->plane_res.scl_data.recout.width = surf_clip.width *
4fa086b9 558 stream->dst.width / stream->src.width;
6702a9ac 559 if (pipe_ctx->plane_res.scl_data.recout.width + pipe_ctx->plane_res.scl_data.recout.x >
4fa086b9 560 stream->dst.x + stream->dst.width)
6702a9ac 561 pipe_ctx->plane_res.scl_data.recout.width =
4fa086b9 562 stream->dst.x + stream->dst.width
6702a9ac 563 - pipe_ctx->plane_res.scl_data.recout.x;
4562236b 564
6702a9ac 565 pipe_ctx->plane_res.scl_data.recout.y = stream->dst.y;
4fa086b9 566 if (stream->src.y < surf_clip.y)
6702a9ac 567 pipe_ctx->plane_res.scl_data.recout.y += (surf_clip.y
4fa086b9
LSL		 568 - stream->src.y) * stream->dst.height
569 / stream->src.height;
4562236b 570
6702a9ac 571 pipe_ctx->plane_res.scl_data.recout.height = surf_clip.height *
4fa086b9 572 stream->dst.height / stream->src.height;
6702a9ac 573 if (pipe_ctx->plane_res.scl_data.recout.height + pipe_ctx->plane_res.scl_data.recout.y >
4fa086b9 574 stream->dst.y + stream->dst.height)
6702a9ac 575 pipe_ctx->plane_res.scl_data.recout.height =
4fa086b9 576 stream->dst.y + stream->dst.height
6702a9ac 577 - pipe_ctx->plane_res.scl_data.recout.y;
b2d0a103 578
7b779c99 579 /* Handle h & vsplit */
3be5262e
HW		 580 if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->plane_state ==
581 pipe_ctx->plane_state) {
4fa086b9 582 if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) {
6702a9ac
HW		 583 pipe_ctx->plane_res.scl_data.recout.height /= 2;
584 pipe_ctx->plane_res.scl_data.recout.y += pipe_ctx->plane_res.scl_data.recout.height;
7b779c99 585 /* Floor primary pipe, ceil 2ndary pipe */
6702a9ac 586 pipe_ctx->plane_res.scl_data.recout.height += pipe_ctx->plane_res.scl_data.recout.height % 2;
7b779c99 587 } else {
6702a9ac
HW		 588 pipe_ctx->plane_res.scl_data.recout.width /= 2;
589 pipe_ctx->plane_res.scl_data.recout.x += pipe_ctx->plane_res.scl_data.recout.width;
590 pipe_ctx->plane_res.scl_data.recout.width += pipe_ctx->plane_res.scl_data.recout.width % 2;
7b779c99
VP		 591 }
592 } else if (pipe_ctx->bottom_pipe &&
3be5262e 593 pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state) {
4fa086b9 594 if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
6702a9ac 595 pipe_ctx->plane_res.scl_data.recout.height /= 2;
7b779c99 596 else
6702a9ac 597 pipe_ctx->plane_res.scl_data.recout.width /= 2;
b2d0a103
DL		 598 }
599
86006a7f
DL		 600 /* Unclipped recout offset = stream dst offset + ((surf dst offset - stream surf_src offset)
601 * * 1/ stream scaling ratio) - (surf surf_src offset * 1/ full scl
c802570e
DL		 602 * ratio)
603 */
3be5262e 604 recout_full_x = stream->dst.x + (plane_state->dst_rect.x - stream->src.x)
4fa086b9 605 * stream->dst.width / stream->src.width -
3be5262e 606 surf_src.x * plane_state->dst_rect.width / surf_src.width
4fa086b9 607 * stream->dst.width / stream->src.width;
3be5262e 608 recout_full_y = stream->dst.y + (plane_state->dst_rect.y - stream->src.y)
4fa086b9 609 * stream->dst.height / stream->src.height -
3be5262e 610 surf_src.y * plane_state->dst_rect.height / surf_src.height
4fa086b9 611 * stream->dst.height / stream->src.height;
c802570e 612
6702a9ac
HW		 613 recout_skip->width = pipe_ctx->plane_res.scl_data.recout.x - recout_full_x;
614 recout_skip->height = pipe_ctx->plane_res.scl_data.recout.y - recout_full_y;
4562236b
HW		 615}
616
b2d0a103 617static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)
4562236b 618{
3be5262e 619 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 620 const struct dc_stream_state *stream = pipe_ctx->stream;
3be5262e 621 struct rect surf_src = plane_state->src_rect;
4fa086b9
LSL		 622 const int in_w = stream->src.width;
623 const int in_h = stream->src.height;
624 const int out_w = stream->dst.width;
625 const int out_h = stream->dst.height;
4562236b 626
3be5262e
HW		 627 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
628 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
86006a7f
DL		 629 rect_swap_helper(&surf_src);
630
6702a9ac 631 pipe_ctx->plane_res.scl_data.ratios.horz = dal_fixed31_32_from_fraction(
86006a7f 632 surf_src.width,
3be5262e 633 plane_state->dst_rect.width);
6702a9ac 634 pipe_ctx->plane_res.scl_data.ratios.vert = dal_fixed31_32_from_fraction(
86006a7f 635 surf_src.height,
3be5262e 636 plane_state->dst_rect.height);
4562236b 637
4fa086b9 638 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
6702a9ac 639 pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2;
4fa086b9 640 else if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
6702a9ac 641 pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2;
4562236b 642
6702a9ac
HW		 643 pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64(
644 pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h);
645 pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64(
646 pipe_ctx->plane_res.scl_data.ratios.horz.value * in_w, out_w);
4562236b 647
6702a9ac
HW		 648 pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz;
649 pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert;
4562236b 650
6702a9ac
HW		 651 if (pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP8
652 || pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP10) {
653 pipe_ctx->plane_res.scl_data.ratios.horz_c.value /= 2;
654 pipe_ctx->plane_res.scl_data.ratios.vert_c.value /= 2;
4562236b
HW		 655 }
656}
657
b2d0a103
DL		 658static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct view *recout_skip)
659{
6702a9ac 660 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
3be5262e 661 struct rect src = pipe_ctx->plane_state->src_rect;
87449a90
AK		 662 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
663 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
b2d0a103 664
86006a7f 665
3be5262e
HW		 666 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
667 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) {
86006a7f 668 rect_swap_helper(&src);
1fbd2cfc
DL		 669 rect_swap_helper(&data->viewport_c);
670 rect_swap_helper(&data->viewport);
671 }
672
b2d0a103
DL		 673 /*
674 * Init calculated according to formula:
675 * init = (scaling_ratio + number_of_taps + 1) / 2
676 * init_bot = init + scaling_ratio
677 * init_c = init + truncated_vp_c_offset(from calculate viewport)
678 */
679 data->inits.h = dal_fixed31_32_div_int(
680 dal_fixed31_32_add_int(data->ratios.horz, data->taps.h_taps + 1), 2);
681
682 data->inits.h_c = dal_fixed31_32_add(data->inits.h_c, dal_fixed31_32_div_int(
683 dal_fixed31_32_add_int(data->ratios.horz_c, data->taps.h_taps_c + 1), 2));
684
685 data->inits.v = dal_fixed31_32_div_int(
686 dal_fixed31_32_add_int(data->ratios.vert, data->taps.v_taps + 1), 2);
687
688 data->inits.v_c = dal_fixed31_32_add(data->inits.v_c, dal_fixed31_32_div_int(
689 dal_fixed31_32_add_int(data->ratios.vert_c, data->taps.v_taps_c + 1), 2));
690
691
692 /* Adjust for viewport end clip-off */
693 if ((data->viewport.x + data->viewport.width) < (src.x + src.width)) {
694 int vp_clip = src.x + src.width - data->viewport.width - data->viewport.x;
1fbd2cfc
DL		 695 int int_part = dal_fixed31_32_floor(
696 dal_fixed31_32_sub(data->inits.h, data->ratios.horz));
b2d0a103 697
1fbd2cfc 698 int_part = int_part > 0 ? int_part : 0;
b2d0a103
DL		 699 data->viewport.width += int_part < vp_clip ? int_part : vp_clip;
700 }
701 if ((data->viewport.y + data->viewport.height) < (src.y + src.height)) {
702 int vp_clip = src.y + src.height - data->viewport.height - data->viewport.y;
1fbd2cfc
DL		 703 int int_part = dal_fixed31_32_floor(
704 dal_fixed31_32_sub(data->inits.v, data->ratios.vert));
b2d0a103 705
1fbd2cfc 706 int_part = int_part > 0 ? int_part : 0;
b2d0a103
DL		 707 data->viewport.height += int_part < vp_clip ? int_part : vp_clip;
708 }
709 if ((data->viewport_c.x + data->viewport_c.width) < (src.x + src.width) / vpc_div) {
710 int vp_clip = (src.x + src.width) / vpc_div -
711 data->viewport_c.width - data->viewport_c.x;
1fbd2cfc
DL		 712 int int_part = dal_fixed31_32_floor(
713 dal_fixed31_32_sub(data->inits.h_c, data->ratios.horz_c));
b2d0a103 714
1fbd2cfc 715 int_part = int_part > 0 ? int_part : 0;
b2d0a103
DL		 716 data->viewport_c.width += int_part < vp_clip ? int_part : vp_clip;
717 }
718 if ((data->viewport_c.y + data->viewport_c.height) < (src.y + src.height) / vpc_div) {
719 int vp_clip = (src.y + src.height) / vpc_div -
720 data->viewport_c.height - data->viewport_c.y;
1fbd2cfc
DL		 721 int int_part = dal_fixed31_32_floor(
722 dal_fixed31_32_sub(data->inits.v_c, data->ratios.vert_c));
b2d0a103 723
1fbd2cfc 724 int_part = int_part > 0 ? int_part : 0;
b2d0a103
DL		 725 data->viewport_c.height += int_part < vp_clip ? int_part : vp_clip;
726 }
727
728 /* Adjust for non-0 viewport offset */
729 if (data->viewport.x) {
730 int int_part;
731
732 data->inits.h = dal_fixed31_32_add(data->inits.h, dal_fixed31_32_mul_int(
733 data->ratios.horz, recout_skip->width));
734 int_part = dal_fixed31_32_floor(data->inits.h) - data->viewport.x;
735 if (int_part < data->taps.h_taps) {
736 int int_adj = data->viewport.x >= (data->taps.h_taps - int_part) ?
737 (data->taps.h_taps - int_part) : data->viewport.x;
738 data->viewport.x -= int_adj;
739 data->viewport.width += int_adj;
740 int_part += int_adj;
741 } else if (int_part > data->taps.h_taps) {
742 data->viewport.x += int_part - data->taps.h_taps;
743 data->viewport.width -= int_part - data->taps.h_taps;
744 int_part = data->taps.h_taps;
745 }
746 data->inits.h.value &= 0xffffffff;
747 data->inits.h = dal_fixed31_32_add_int(data->inits.h, int_part);
748 }
749
750 if (data->viewport_c.x) {
751 int int_part;
752
753 data->inits.h_c = dal_fixed31_32_add(data->inits.h_c, dal_fixed31_32_mul_int(
754 data->ratios.horz_c, recout_skip->width));
755 int_part = dal_fixed31_32_floor(data->inits.h_c) - data->viewport_c.x;
756 if (int_part < data->taps.h_taps_c) {
757 int int_adj = data->viewport_c.x >= (data->taps.h_taps_c - int_part) ?
758 (data->taps.h_taps_c - int_part) : data->viewport_c.x;
759 data->viewport_c.x -= int_adj;
760 data->viewport_c.width += int_adj;
761 int_part += int_adj;
762 } else if (int_part > data->taps.h_taps_c) {
763 data->viewport_c.x += int_part - data->taps.h_taps_c;
764 data->viewport_c.width -= int_part - data->taps.h_taps_c;
765 int_part = data->taps.h_taps_c;
766 }
767 data->inits.h_c.value &= 0xffffffff;
768 data->inits.h_c = dal_fixed31_32_add_int(data->inits.h_c, int_part);
769 }
770
771 if (data->viewport.y) {
772 int int_part;
773
774 data->inits.v = dal_fixed31_32_add(data->inits.v, dal_fixed31_32_mul_int(
775 data->ratios.vert, recout_skip->height));
776 int_part = dal_fixed31_32_floor(data->inits.v) - data->viewport.y;
777 if (int_part < data->taps.v_taps) {
778 int int_adj = data->viewport.y >= (data->taps.v_taps - int_part) ?
779 (data->taps.v_taps - int_part) : data->viewport.y;
780 data->viewport.y -= int_adj;
781 data->viewport.height += int_adj;
782 int_part += int_adj;
783 } else if (int_part > data->taps.v_taps) {
784 data->viewport.y += int_part - data->taps.v_taps;
785 data->viewport.height -= int_part - data->taps.v_taps;
786 int_part = data->taps.v_taps;
787 }
788 data->inits.v.value &= 0xffffffff;
789 data->inits.v = dal_fixed31_32_add_int(data->inits.v, int_part);
790 }
791
792 if (data->viewport_c.y) {
793 int int_part;
794
795 data->inits.v_c = dal_fixed31_32_add(data->inits.v_c, dal_fixed31_32_mul_int(
796 data->ratios.vert_c, recout_skip->height));
797 int_part = dal_fixed31_32_floor(data->inits.v_c) - data->viewport_c.y;
798 if (int_part < data->taps.v_taps_c) {
799 int int_adj = data->viewport_c.y >= (data->taps.v_taps_c - int_part) ?
800 (data->taps.v_taps_c - int_part) : data->viewport_c.y;
801 data->viewport_c.y -= int_adj;
802 data->viewport_c.height += int_adj;
803 int_part += int_adj;
804 } else if (int_part > data->taps.v_taps_c) {
805 data->viewport_c.y += int_part - data->taps.v_taps_c;
806 data->viewport_c.height -= int_part - data->taps.v_taps_c;
807 int_part = data->taps.v_taps_c;
808 }
809 data->inits.v_c.value &= 0xffffffff;
810 data->inits.v_c = dal_fixed31_32_add_int(data->inits.v_c, int_part);
811 }
812
813 /* Interlaced inits based on final vert inits */
814 data->inits.v_bot = dal_fixed31_32_add(data->inits.v, data->ratios.vert);
815 data->inits.v_c_bot = dal_fixed31_32_add(data->inits.v_c, data->ratios.vert_c);
1fbd2cfc 816
3be5262e
HW		 817 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
818 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) {
1fbd2cfc
DL		 819 rect_swap_helper(&data->viewport_c);
820 rect_swap_helper(&data->viewport);
821 }
b2d0a103
DL		 822}
823
824bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
4562236b 825{
3be5262e 826 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
4fa086b9 827 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
b2d0a103
DL		 828 struct view recout_skip = { 0 };
829 bool res = false;
830
4562236b
HW		 831 /* Important: scaling ratio calculation requires pixel format,
832 * lb depth calculation requires recout and taps require scaling ratios.
b2d0a103 833 * Inits require viewport, taps, ratios and recout of split pipe
4562236b 834 */
6702a9ac 835 pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface(
3be5262e 836 pipe_ctx->plane_state->format);
b2d0a103
DL		 837
838 calculate_scaling_ratios(pipe_ctx);
4562236b 839
b2d0a103 840 calculate_viewport(pipe_ctx);
4562236b 841
6702a9ac 842 if (pipe_ctx->plane_res.scl_data.viewport.height < 16 || pipe_ctx->plane_res.scl_data.viewport.width < 16)
4562236b
HW		 843 return false;
844
b2d0a103 845 calculate_recout(pipe_ctx, &recout_skip);
4562236b
HW		 846
847 /**
848 * Setting line buffer pixel depth to 24bpp yields banding
849 * on certain displays, such as the Sharp 4k
850 */
6702a9ac 851 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
4562236b 852
199e458a
DL		 853 /**
854 * KMD sends us h and v_addressable without the borders, which causes us sometimes to draw
855 * the blank region on-screen. Correct for this by adding the borders back to their
856 * respective addressable values, and by shifting recout.
857 */
858 timing->h_addressable += timing->h_border_left + timing->h_border_right;
859 timing->v_addressable += timing->v_border_top + timing->v_border_bottom;
860 pipe_ctx->plane_res.scl_data.recout.y += timing->v_border_top;
861 pipe_ctx->plane_res.scl_data.recout.x += timing->h_border_left;
862 timing->v_border_top = 0;
863 timing->v_border_bottom = 0;
864 timing->h_border_left = 0;
865 timing->h_border_right = 0;
866
6702a9ac
HW		 867 pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable;
868 pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable;
4562236b
HW		 869
870 /* Taps calculations */
d94585a0
YHL		 871 if (pipe_ctx->plane_res.xfm != NULL)
872 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
873 pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
874
875 if (pipe_ctx->plane_res.dpp != NULL)
876 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
877 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
4562236b
HW		 878
879 if (!res) {
880 /* Try 24 bpp linebuffer */
6702a9ac 881 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP;
4562236b 882
86a66c4e
HW		 883 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
884 pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
d94585a0
YHL		 885
886 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
887 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
4562236b
HW		 888 }
889
b2d0a103 890 if (res)
1fbd2cfc 891 /* May need to re-check lb size after this in some obscure scenario */
b2d0a103
DL		 892 calculate_inits_and_adj_vp(pipe_ctx, &recout_skip);
893
4562236b
HW		 894 dm_logger_write(pipe_ctx->stream->ctx->logger, LOG_SCALER,
895 "%s: Viewport:\nheight:%d width:%d x:%d "
896 "y:%d\n dst_rect:\nheight:%d width:%d x:%d "
897 "y:%d\n",
898 __func__,
6702a9ac
HW		 899 pipe_ctx->plane_res.scl_data.viewport.height,
900 pipe_ctx->plane_res.scl_data.viewport.width,
901 pipe_ctx->plane_res.scl_data.viewport.x,
902 pipe_ctx->plane_res.scl_data.viewport.y,
3be5262e
HW		 903 plane_state->dst_rect.height,
904 plane_state->dst_rect.width,
905 plane_state->dst_rect.x,
906 plane_state->dst_rect.y);
4562236b
HW		 907
908 return res;
909}
910
911
912enum dc_status resource_build_scaling_params_for_context(
fb3466a4 913 const struct dc *dc,
608ac7bb 914 struct dc_state *context)
4562236b
HW		 915{
916 int i;
917
918 for (i = 0; i < MAX_PIPES; i++) {
3be5262e 919 if (context->res_ctx.pipe_ctx[i].plane_state != NULL &&
4562236b 920 context->res_ctx.pipe_ctx[i].stream != NULL)
b2d0a103 921 if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i]))
f84a8161 922 return DC_FAIL_SCALING;
4562236b
HW		 923 }
924
925 return DC_OK;
926}
927
a2b8659d
TC		 928struct pipe_ctx *find_idle_secondary_pipe(
929 struct resource_context *res_ctx,
930 const struct resource_pool *pool)
4562236b
HW		 931{
932 int i;
933 struct pipe_ctx *secondary_pipe = NULL;
934
935 /*
936 * search backwards for the second pipe to keep pipe
937 * assignment more consistent
938 */
939
a2b8659d 940 for (i = pool->pipe_count - 1; i >= 0; i--) {
4562236b
HW		 941 if (res_ctx->pipe_ctx[i].stream == NULL) {
942 secondary_pipe = &res_ctx->pipe_ctx[i];
943 secondary_pipe->pipe_idx = i;
944 break;
945 }
946 }
947
948
949 return secondary_pipe;
950}
951
952struct pipe_ctx *resource_get_head_pipe_for_stream(
953 struct resource_context *res_ctx,
0971c40e 954 struct dc_stream_state *stream)
4562236b
HW		 955{
956 int i;
a2b8659d 957 for (i = 0; i < MAX_PIPES; i++) {
4562236b 958 if (res_ctx->pipe_ctx[i].stream == stream &&
1dc90497 959 !res_ctx->pipe_ctx[i].top_pipe) {
4562236b
HW		 960 return &res_ctx->pipe_ctx[i];
961 break;
962 }
963 }
964 return NULL;
965}
966
19f89e23
AG		 967static struct pipe_ctx *resource_get_tail_pipe_for_stream(
968 struct resource_context *res_ctx,
969 struct dc_stream_state *stream)
970{
971 struct pipe_ctx *head_pipe, *tail_pipe;
972 head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
973
974 if (!head_pipe)
975 return NULL;
976
977 tail_pipe = head_pipe->bottom_pipe;
978
979 while (tail_pipe) {
980 head_pipe = tail_pipe;
981 tail_pipe = tail_pipe->bottom_pipe;
982 }
983
984 return head_pipe;
985}
986
4562236b 987/*
ab2541b6
AC		 988 * A free_pipe for a stream is defined here as a pipe
989 * that has no surface attached yet
4562236b 990 */
ab2541b6 991static struct pipe_ctx *acquire_free_pipe_for_stream(
608ac7bb 992 struct dc_state *context,
a2b8659d 993 const struct resource_pool *pool,
0971c40e 994 struct dc_stream_state *stream)
4562236b
HW		 995{
996 int i;
745cc746 997 struct resource_context *res_ctx = &context->res_ctx;
4562236b
HW		 998
999 struct pipe_ctx *head_pipe = NULL;
1000
1001 /* Find head pipe, which has the back end set up*/
1002
1003 head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
1004
1005 if (!head_pipe)
1006 ASSERT(0);
1007
3be5262e 1008 if (!head_pipe->plane_state)
4562236b
HW		 1009 return head_pipe;
1010
1011 /* Re-use pipe already acquired for this stream if available*/
a2b8659d 1012 for (i = pool->pipe_count - 1; i >= 0; i--) {
4562236b 1013 if (res_ctx->pipe_ctx[i].stream == stream &&
3be5262e 1014 !res_ctx->pipe_ctx[i].plane_state) {
4562236b
HW		 1015 return &res_ctx->pipe_ctx[i];
1016 }
1017 }
1018
1019 /*
1020 * At this point we have no re-useable pipe for this stream and we need
1021 * to acquire an idle one to satisfy the request
1022 */
1023
a2b8659d 1024 if (!pool->funcs->acquire_idle_pipe_for_layer)
4562236b
HW		 1025 return NULL;
1026
a2b8659d 1027 return pool->funcs->acquire_idle_pipe_for_layer(context, pool, stream);
4562236b
HW		 1028
1029}
1030
0f9a536f
DL		 1031#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1032static int acquire_first_split_pipe(
1033 struct resource_context *res_ctx,
1034 const struct resource_pool *pool,
0971c40e 1035 struct dc_stream_state *stream)
0f9a536f
DL		 1036{
1037 int i;
1038
1039 for (i = 0; i < pool->pipe_count; i++) {
1040 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
1041
1042 if (pipe_ctx->top_pipe &&
3be5262e 1043 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state) {
0f9a536f
DL		 1044 pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;
1045 if (pipe_ctx->bottom_pipe)
1046 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;
1047
1048 memset(pipe_ctx, 0, sizeof(*pipe_ctx));
6b670fa9 1049 pipe_ctx->stream_res.tg = pool->timing_generators[i];
8feabd03 1050 pipe_ctx->plane_res.hubp = pool->hubps[i];
86a66c4e 1051 pipe_ctx->plane_res.ipp = pool->ipps[i];
d94585a0 1052 pipe_ctx->plane_res.dpp = pool->dpps[i];
a6a6cb34 1053 pipe_ctx->stream_res.opp = pool->opps[i];
0f9a536f 1054 pipe_ctx->pipe_idx = i;
0f9a536f
DL		 1055
1056 pipe_ctx->stream = stream;
1057 return i;
1058 }
1059 }
1060 return -1;
1061}
1062#endif
1063
19f89e23
AG		 1064bool dc_add_plane_to_context(
1065 const struct dc *dc,
0971c40e 1066 struct dc_stream_state *stream,
19f89e23 1067 struct dc_plane_state *plane_state,
608ac7bb 1068 struct dc_state *context)
4562236b
HW		 1069{
1070 int i;
19f89e23
AG		 1071 struct resource_pool *pool = dc->res_pool;
1072 struct pipe_ctx *head_pipe, *tail_pipe, *free_pipe;
ab2541b6 1073 struct dc_stream_status *stream_status = NULL;
4562236b 1074
19f89e23
AG		 1075 for (i = 0; i < context->stream_count; i++)
1076 if (context->streams[i] == stream) {
1077 stream_status = &context->stream_status[i];
1078 break;
1079 }
1080 if (stream_status == NULL) {
1081 dm_error("Existing stream not found; failed to attach surface!\n");
1082 return false;
1083 }
1084
4562236b 1085
19f89e23
AG		 1086 if (stream_status->plane_count == MAX_SURFACE_NUM) {
1087 dm_error("Surface: can not attach plane_state %p! Maximum is: %d\n",
1088 plane_state, MAX_SURFACE_NUM);
4562236b
HW		 1089 return false;
1090 }
1091
19f89e23
AG		 1092 head_pipe = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
1093
1094 if (!head_pipe) {
1095 dm_error("Head pipe not found for stream_state %p !\n", stream);
1096 return false;
1097 }
1098
19f89e23
AG		 1099 free_pipe = acquire_free_pipe_for_stream(context, pool, stream);
1100
1101#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1102 if (!free_pipe) {
1103 int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
1104 if (pipe_idx >= 0)
1105 free_pipe = &context->res_ctx.pipe_ctx[pipe_idx];
1106 }
1107#endif
abb4986e 1108 if (!free_pipe)
19f89e23 1109 return false;
19f89e23 1110
abb4986e
AJ		 1111 /* retain new surfaces */
1112 dc_plane_state_retain(plane_state);
19f89e23
AG		 1113 free_pipe->plane_state = plane_state;
1114
1115 if (head_pipe != free_pipe) {
1116
1117 tail_pipe = resource_get_tail_pipe_for_stream(&context->res_ctx, stream);
1118 ASSERT(tail_pipe);
1119
1120 free_pipe->stream_res.tg = tail_pipe->stream_res.tg;
1121 free_pipe->stream_res.opp = tail_pipe->stream_res.opp;
1122 free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc;
1123 free_pipe->stream_res.audio = tail_pipe->stream_res.audio;
1124 free_pipe->clock_source = tail_pipe->clock_source;
1125 free_pipe->top_pipe = tail_pipe;
1126 tail_pipe->bottom_pipe = free_pipe;
1127 }
1128
1129 /* assign new surfaces*/
1130 stream_status->plane_states[stream_status->plane_count] = plane_state;
1131
1132 stream_status->plane_count++;
1133
1134 return true;
1135}
1136
1137bool dc_remove_plane_from_context(
1138 const struct dc *dc,
1139 struct dc_stream_state *stream,
1140 struct dc_plane_state *plane_state,
608ac7bb 1141 struct dc_state *context)
19f89e23
AG		 1142{
1143 int i;
1144 struct dc_stream_status *stream_status = NULL;
1145 struct resource_pool *pool = dc->res_pool;
1146
ab2541b6 1147 for (i = 0; i < context->stream_count; i++)
4fa086b9 1148 if (context->streams[i] == stream) {
ab2541b6 1149 stream_status = &context->stream_status[i];
4562236b
HW		 1150 break;
1151 }
19f89e23 1152
ab2541b6 1153 if (stream_status == NULL) {
19f89e23 1154 dm_error("Existing stream not found; failed to remove plane.\n");
4562236b
HW		 1155 return false;
1156 }
1157
19f89e23
AG		 1158 /* release pipe for plane*/
1159 for (i = pool->pipe_count - 1; i >= 0; i--) {
1160 struct pipe_ctx *pipe_ctx;
4562236b 1161
19f89e23
AG		 1162 if (context->res_ctx.pipe_ctx[i].plane_state == plane_state) {
1163 pipe_ctx = &context->res_ctx.pipe_ctx[i];
4562236b 1164
19f89e23
AG		 1165 if (pipe_ctx->top_pipe)
1166 pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;
4562236b 1167
19f89e23
AG		 1168 /* Second condition is to avoid setting NULL to top pipe
1169 * of tail pipe making it look like head pipe in subsequent
1170 * deletes
1171 */
1172 if (pipe_ctx->bottom_pipe && pipe_ctx->top_pipe)
1173 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;
4562236b 1174
19f89e23
AG		 1175 /*
1176 * For head pipe detach surfaces from pipe for tail
1177 * pipe just zero it out
1178 */
1179 if (!pipe_ctx->top_pipe) {
1180 pipe_ctx->plane_state = NULL;
1181 pipe_ctx->bottom_pipe = NULL;
1182 } else {
1183 memset(pipe_ctx, 0, sizeof(*pipe_ctx));
1184 }
4562236b 1185 }
19f89e23 1186 }
4562236b 1187
4562236b 1188
19f89e23
AG		 1189 for (i = 0; i < stream_status->plane_count; i++) {
1190 if (stream_status->plane_states[i] == plane_state) {
1191
1192 dc_plane_state_release(stream_status->plane_states[i]);
1193 break;
4562236b 1194 }
19f89e23 1195 }
4562236b 1196
19f89e23
AG		 1197 if (i == stream_status->plane_count) {
1198 dm_error("Existing plane_state not found; failed to detach it!\n");
1199 return false;
4562236b
HW		 1200 }
1201
19f89e23 1202 stream_status->plane_count--;
4562236b 1203
abb4986e
AJ		 1204 /* Start at the plane we've just released, and move all the planes one index forward to "trim" the array */
1205 for (; i < stream_status->plane_count; i++)
19f89e23
AG		 1206 stream_status->plane_states[i] = stream_status->plane_states[i + 1];
1207
1208 stream_status->plane_states[stream_status->plane_count] = NULL;
1209
1210 return true;
1211}
1212
1213bool dc_rem_all_planes_for_stream(
1214 const struct dc *dc,
1215 struct dc_stream_state *stream,
608ac7bb 1216 struct dc_state *context)
19f89e23
AG		 1217{
1218 int i, old_plane_count;
1219 struct dc_stream_status *stream_status = NULL;
1220 struct dc_plane_state *del_planes[MAX_SURFACE_NUM] = { 0 };
1221
1222 for (i = 0; i < context->stream_count; i++)
1223 if (context->streams[i] == stream) {
1224 stream_status = &context->stream_status[i];
1225 break;
1226 }
1227
1228 if (stream_status == NULL) {
1229 dm_error("Existing stream %p not found!\n", stream);
1230 return false;
1231 }
1232
1233 old_plane_count = stream_status->plane_count;
1234
1235 for (i = 0; i < old_plane_count; i++)
1236 del_planes[i] = stream_status->plane_states[i];
1237
1238 for (i = 0; i < old_plane_count; i++)
1239 if (!dc_remove_plane_from_context(dc, stream, del_planes[i], context))
1240 return false;
1241
1242 return true;
1243}
1244
1245static bool add_all_planes_for_stream(
1246 const struct dc *dc,
1247 struct dc_stream_state *stream,
1248 const struct dc_validation_set set[],
1249 int set_count,
608ac7bb 1250 struct dc_state *context)
19f89e23
AG		 1251{
1252 int i, j;
1253
1254 for (i = 0; i < set_count; i++)
1255 if (set[i].stream == stream)
1256 break;
1257
1258 if (i == set_count) {
1259 dm_error("Stream %p not found in set!\n", stream);
1260 return false;
1261 }
4562236b 1262
19f89e23
AG		 1263 for (j = 0; j < set[i].plane_count; j++)
1264 if (!dc_add_plane_to_context(dc, stream, set[i].plane_states[j], context))
1265 return false;
4562236b
HW		 1266
1267 return true;
1268}
1269
19f89e23
AG		 1270bool dc_add_all_planes_for_stream(
1271 const struct dc *dc,
1272 struct dc_stream_state *stream,
1273 struct dc_plane_state * const *plane_states,
1274 int plane_count,
608ac7bb 1275 struct dc_state *context)
19f89e23
AG		 1276{
1277 struct dc_validation_set set;
1278 int i;
1279
1280 set.stream = stream;
1281 set.plane_count = plane_count;
1282
1283 for (i = 0; i < plane_count; i++)
1284 set.plane_states[i] = plane_states[i];
1285
1286 return add_all_planes_for_stream(dc, stream, &set, 1, context);
1287}
1288
1289
4562236b 1290
0971c40e
HW		 1291static bool is_timing_changed(struct dc_stream_state *cur_stream,
1292 struct dc_stream_state *new_stream)
4562236b
HW		 1293{
1294 if (cur_stream == NULL)
1295 return true;
1296
1297 /* If sink pointer changed, it means this is a hotplug, we should do
1298 * full hw setting.
1299 */
1300 if (cur_stream->sink != new_stream->sink)
1301 return true;
1302
1303 /* If output color space is changed, need to reprogram info frames */
4fa086b9 1304 if (cur_stream->output_color_space != new_stream->output_color_space)
4562236b
HW		 1305 return true;
1306
1307 return memcmp(
4fa086b9
LSL		 1308 &cur_stream->timing,
1309 &new_stream->timing,
4562236b
HW		 1310 sizeof(struct dc_crtc_timing)) != 0;
1311}
1312
1313static bool are_stream_backends_same(
0971c40e 1314 struct dc_stream_state *stream_a, struct dc_stream_state *stream_b)
4562236b
HW		 1315{
1316 if (stream_a == stream_b)
1317 return true;
1318
1319 if (stream_a == NULL || stream_b == NULL)
1320 return false;
1321
1322 if (is_timing_changed(stream_a, stream_b))
1323 return false;
1324
1325 return true;
1326}
1327
d54d29db 1328bool dc_is_stream_unchanged(
0971c40e 1329 struct dc_stream_state *old_stream, struct dc_stream_state *stream)
4562236b 1330{
4562236b 1331
ab2541b6
AC		 1332 if (!are_stream_backends_same(old_stream, stream))
1333 return false;
4562236b
HW		 1334
1335 return true;
1336}
1337
4562236b
HW		 1338/* Maximum TMDS single link pixel clock 165MHz */
1339#define TMDS_MAX_PIXEL_CLOCK_IN_KHZ 165000
1340
1dc90497 1341static void update_stream_engine_usage(
4562236b 1342 struct resource_context *res_ctx,
a2b8659d 1343 const struct resource_pool *pool,
1dc90497
AG		 1344 struct stream_encoder *stream_enc,
1345 bool acquired)
4562236b
HW		 1346{
1347 int i;
1348
a2b8659d
TC		 1349 for (i = 0; i < pool->stream_enc_count; i++) {
1350 if (pool->stream_enc[i] == stream_enc)
1dc90497 1351 res_ctx->is_stream_enc_acquired[i] = acquired;
4562236b
HW		 1352 }
1353}
1354
1355/* TODO: release audio object */
4176664b 1356void update_audio_usage(
4562236b 1357 struct resource_context *res_ctx,
a2b8659d 1358 const struct resource_pool *pool,
1dc90497
AG		 1359 struct audio *audio,
1360 bool acquired)
4562236b
HW		 1361{
1362 int i;
a2b8659d
TC		 1363 for (i = 0; i < pool->audio_count; i++) {
1364 if (pool->audios[i] == audio)
1dc90497 1365 res_ctx->is_audio_acquired[i] = acquired;
4562236b
HW		 1366 }
1367}
1368
1369static int acquire_first_free_pipe(
1370 struct resource_context *res_ctx,
a2b8659d 1371 const struct resource_pool *pool,
0971c40e 1372 struct dc_stream_state *stream)
4562236b
HW		 1373{
1374 int i;
1375
a2b8659d 1376 for (i = 0; i < pool->pipe_count; i++) {
4562236b
HW		 1377 if (!res_ctx->pipe_ctx[i].stream) {
1378 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
1379
6b670fa9 1380 pipe_ctx->stream_res.tg = pool->timing_generators[i];
86a66c4e 1381 pipe_ctx->plane_res.mi = pool->mis[i];
8feabd03 1382 pipe_ctx->plane_res.hubp = pool->hubps[i];
86a66c4e
HW		 1383 pipe_ctx->plane_res.ipp = pool->ipps[i];
1384 pipe_ctx->plane_res.xfm = pool->transforms[i];
d94585a0 1385 pipe_ctx->plane_res.dpp = pool->dpps[i];
a6a6cb34 1386 pipe_ctx->stream_res.opp = pool->opps[i];
4562236b
HW		 1387 pipe_ctx->pipe_idx = i;
1388
ff5ef992 1389
4562236b
HW		 1390 pipe_ctx->stream = stream;
1391 return i;
1392 }
1393 }
1394 return -1;
1395}
1396
1397static struct stream_encoder *find_first_free_match_stream_enc_for_link(
1398 struct resource_context *res_ctx,
a2b8659d 1399 const struct resource_pool *pool,
0971c40e 1400 struct dc_stream_state *stream)
4562236b
HW		 1401{
1402 int i;
1403 int j = -1;
d0778ebf 1404 struct dc_link *link = stream->sink->link;
4562236b 1405
a2b8659d 1406 for (i = 0; i < pool->stream_enc_count; i++) {
4562236b 1407 if (!res_ctx->is_stream_enc_acquired[i] &&
a2b8659d 1408 pool->stream_enc[i]) {
4562236b
HW		 1409 /* Store first available for MST second display
1410 * in daisy chain use case */
1411 j = i;
a2b8659d 1412 if (pool->stream_enc[i]->id ==
4562236b 1413 link->link_enc->preferred_engine)
a2b8659d 1414 return pool->stream_enc[i];
4562236b
HW		 1415 }
1416 }
1417
1418 /*
1419 * below can happen in cases when stream encoder is acquired:
1420 * 1) for second MST display in chain, so preferred engine already
1421 * acquired;
1422 * 2) for another link, which preferred engine already acquired by any
1423 * MST configuration.
1424 *
1425 * If signal is of DP type and preferred engine not found, return last available
1426 *
1427 * TODO - This is just a patch up and a generic solution is
1428 * required for non DP connectors.
1429 */
1430
1431 if (j >= 0 && dc_is_dp_signal(stream->signal))
a2b8659d 1432 return pool->stream_enc[j];
4562236b
HW		 1433
1434 return NULL;
1435}
1436
a2b8659d
TC		 1437static struct audio *find_first_free_audio(
1438 struct resource_context *res_ctx,
1439 const struct resource_pool *pool)
4562236b
HW		 1440{
1441 int i;
66bfd4fd
CL		 1442 for (i = 0; i < pool->audio_count; i++) {
1443 if ((res_ctx->is_audio_acquired[i] == false) && (res_ctx->is_stream_enc_acquired[i] == true)) {
1444 return pool->audios[i];
4562236b 1445 }
66bfd4fd
CL		 1446 }
1447 /*not found the matching one, first come first serve*/
1448 for (i = 0; i < pool->audio_count; i++) {
1449 if (res_ctx->is_audio_acquired[i] == false) {
1450 return pool->audios[i];
4176664b
CL		 1451 }
1452 }
4562236b
HW		 1453 return 0;
1454}
1455
4562236b 1456bool resource_is_stream_unchanged(
608ac7bb 1457 struct dc_state *old_context, struct dc_stream_state *stream)
4562236b 1458{
ab2541b6 1459 int i;
4562236b 1460
ab2541b6 1461 for (i = 0; i < old_context->stream_count; i++) {
0971c40e 1462 struct dc_stream_state *old_stream = old_context->streams[i];
4562236b 1463
ab2541b6 1464 if (are_stream_backends_same(old_stream, stream))
4562236b 1465 return true;
4562236b
HW		 1466 }
1467
1468 return false;
1469}
1470
13ab1b44 1471enum dc_status dc_add_stream_to_ctx(
1dc90497 1472 struct dc *dc,
608ac7bb 1473 struct dc_state *new_ctx,
1dc90497
AG		 1474 struct dc_stream_state *stream)
1475{
1476 struct dc_context *dc_ctx = dc->ctx;
1477 enum dc_status res;
1478
1479 if (new_ctx->stream_count >= dc->res_pool->pipe_count) {
1480 DC_ERROR("Max streams reached, can add stream %p !\n", stream);
1481 return DC_ERROR_UNEXPECTED;
1482 }
1483
1484 new_ctx->streams[new_ctx->stream_count] = stream;
1485 dc_stream_retain(stream);
1486 new_ctx->stream_count++;
1487
1488 res = dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream);
1489 if (res != DC_OK)
1490 DC_ERROR("Adding stream %p to context failed with err %d!\n", stream, res);
1491
13ab1b44 1492 return res;
1dc90497
AG		 1493}
1494
1495bool dc_remove_stream_from_ctx(
1496 struct dc *dc,
608ac7bb 1497 struct dc_state *new_ctx,
1dc90497
AG		 1498 struct dc_stream_state *stream)
1499{
19f89e23 1500 int i;
1dc90497
AG		 1501 struct dc_context *dc_ctx = dc->ctx;
1502 struct pipe_ctx *del_pipe = NULL;
1503
19f89e23 1504 /* Release primary pipe */
1dc90497 1505 for (i = 0; i < MAX_PIPES; i++) {
19f89e23
AG		 1506 if (new_ctx->res_ctx.pipe_ctx[i].stream == stream &&
1507 !new_ctx->res_ctx.pipe_ctx[i].top_pipe) {
1dc90497
AG		 1508 del_pipe = &new_ctx->res_ctx.pipe_ctx[i];
1509
19f89e23
AG		 1510 ASSERT(del_pipe->stream_res.stream_enc);
1511 update_stream_engine_usage(
1512 &new_ctx->res_ctx,
1dc90497 1513 dc->res_pool,
19f89e23
AG		 1514 del_pipe->stream_res.stream_enc,
1515 false);
1dc90497
AG		 1516
1517 if (del_pipe->stream_res.audio)
1518 update_audio_usage(
1519 &new_ctx->res_ctx,
1520 dc->res_pool,
1521 del_pipe->stream_res.audio,
1522 false);
1523
9d0dcecd
HW		 1524 resource_unreference_clock_source(&new_ctx->res_ctx,
1525 dc->res_pool,
1526 del_pipe->clock_source);
1527
1dc90497 1528 memset(del_pipe, 0, sizeof(*del_pipe));
19f89e23
AG		 1529
1530 break;
1dc90497
AG		 1531 }
1532 }
1533
1534 if (!del_pipe) {
1535 DC_ERROR("Pipe not found for stream %p !\n", stream);
1536 return DC_ERROR_UNEXPECTED;
1537 }
1538
1539 for (i = 0; i < new_ctx->stream_count; i++)
1540 if (new_ctx->streams[i] == stream)
1541 break;
1542
1543 if (new_ctx->streams[i] != stream) {
1544 DC_ERROR("Context doesn't have stream %p !\n", stream);
1545 return DC_ERROR_UNEXPECTED;
1546 }
1547
1548 dc_stream_release(new_ctx->streams[i]);
1549 new_ctx->stream_count--;
1550
1dc90497
AG		 1551 /* Trim back arrays */
1552 for (; i < new_ctx->stream_count; i++) {
1553 new_ctx->streams[i] = new_ctx->streams[i + 1];
1554 new_ctx->stream_status[i] = new_ctx->stream_status[i + 1];
1555 }
1556
1557 new_ctx->streams[new_ctx->stream_count] = NULL;
1558 memset(
1559 &new_ctx->stream_status[new_ctx->stream_count],
1560 0,
1561 sizeof(new_ctx->stream_status[0]));
1562
1563 return DC_OK;
1564}
1565
4562236b
HW		 1566static void copy_pipe_ctx(
1567 const struct pipe_ctx *from_pipe_ctx, struct pipe_ctx *to_pipe_ctx)
1568{
3be5262e 1569 struct dc_plane_state *plane_state = to_pipe_ctx->plane_state;
0971c40e 1570 struct dc_stream_state *stream = to_pipe_ctx->stream;
4562236b
HW		 1571
1572 *to_pipe_ctx = *from_pipe_ctx;
1573 to_pipe_ctx->stream = stream;
3be5262e
HW		 1574 if (plane_state != NULL)
1575 to_pipe_ctx->plane_state = plane_state;
4562236b
HW		 1576}
1577
0971c40e
HW		 1578static struct dc_stream_state *find_pll_sharable_stream(
1579 struct dc_stream_state *stream_needs_pll,
608ac7bb 1580 struct dc_state *context)
4562236b 1581{
ab2541b6 1582 int i;
4562236b 1583
ab2541b6 1584 for (i = 0; i < context->stream_count; i++) {
0971c40e 1585 struct dc_stream_state *stream_has_pll = context->streams[i];
4562236b 1586
ab2541b6
AC		 1587 /* We are looking for non dp, non virtual stream */
1588 if (resource_are_streams_timing_synchronizable(
1589 stream_needs_pll, stream_has_pll)
1590 && !dc_is_dp_signal(stream_has_pll->signal)
d0778ebf 1591 && stream_has_pll->sink->link->connector_signal
ab2541b6
AC		 1592 != SIGNAL_TYPE_VIRTUAL)
1593 return stream_has_pll;
4562236b 1594
4562236b
HW		 1595 }
1596
1597 return NULL;
1598}
1599
1600static int get_norm_pix_clk(const struct dc_crtc_timing *timing)
1601{
1602 uint32_t pix_clk = timing->pix_clk_khz;
1603 uint32_t normalized_pix_clk = pix_clk;
1604
1605 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
1606 pix_clk /= 2;
cc4d99b8
CL		 1607 if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) {
1608 switch (timing->display_color_depth) {
1609 case COLOR_DEPTH_888:
1610 normalized_pix_clk = pix_clk;
1611 break;
1612 case COLOR_DEPTH_101010:
1613 normalized_pix_clk = (pix_clk * 30) / 24;
1614 break;
1615 case COLOR_DEPTH_121212:
1616 normalized_pix_clk = (pix_clk * 36) / 24;
4562236b 1617 break;
cc4d99b8
CL		 1618 case COLOR_DEPTH_161616:
1619 normalized_pix_clk = (pix_clk * 48) / 24;
4562236b 1620 break;
cc4d99b8
CL		 1621 default:
1622 ASSERT(0);
4562236b 1623 break;
cc4d99b8 1624 }
4562236b 1625 }
4562236b
HW		 1626 return normalized_pix_clk;
1627}
1628
0971c40e 1629static void calculate_phy_pix_clks(struct dc_stream_state *stream)
4562236b 1630{
9345d987
AG		 1631 /* update actual pixel clock on all streams */
1632 if (dc_is_hdmi_signal(stream->signal))
1633 stream->phy_pix_clk = get_norm_pix_clk(
4fa086b9 1634 &stream->timing);
9345d987
AG		 1635 else
1636 stream->phy_pix_clk =
4fa086b9 1637 stream->timing.pix_clk_khz;
4562236b
HW		 1638}
1639
1640enum dc_status resource_map_pool_resources(
fb3466a4 1641 const struct dc *dc,
608ac7bb 1642 struct dc_state *context,
1dc90497 1643 struct dc_stream_state *stream)
4562236b 1644{
a2b8659d 1645 const struct resource_pool *pool = dc->res_pool;
1dc90497
AG		 1646 int i;
1647 struct dc_context *dc_ctx = dc->ctx;
1648 struct pipe_ctx *pipe_ctx = NULL;
1649 int pipe_idx = -1;
4562236b 1650
1dc90497
AG		 1651 /* TODO Check if this is needed */
1652 /*if (!resource_is_stream_unchanged(old_context, stream)) {
430ef426 1653 if (stream != NULL && old_context->streams[i] != NULL) {
4b679bc3 1654 stream->bit_depth_params =
430ef426
DL		 1655 old_context->streams[i]->bit_depth_params;
1656 stream->clamping = old_context->streams[i]->clamping;
a2b8659d
TC		 1657 continue;
1658 }
4b679bc3 1659 }
1dc90497 1660 */
7e2fe319 1661
1dc90497
AG		 1662 /* acquire new resources */
1663 pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream);
8c737fcc 1664
1dc90497 1665 if (pipe_idx < 0)
13ab1b44
YS		 1666 pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
1667
1dc90497
AG		 1668 if (pipe_idx < 0)
1669 return DC_NO_CONTROLLER_RESOURCE;
1670
1671 pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
1672
1673 pipe_ctx->stream_res.stream_enc =
1674 find_first_free_match_stream_enc_for_link(
1675 &context->res_ctx, pool, stream);
1676
1677 if (!pipe_ctx->stream_res.stream_enc)
1678 return DC_NO_STREAM_ENG_RESOURCE;
1679
1680 update_stream_engine_usage(
1681 &context->res_ctx, pool,
1682 pipe_ctx->stream_res.stream_enc,
1683 true);
1684
1685 /* TODO: Add check if ASIC support and EDID audio */
1686 if (!stream->sink->converter_disable_audio &&
1687 dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&
1688 stream->audio_info.mode_count) {
1689 pipe_ctx->stream_res.audio = find_first_free_audio(
1690 &context->res_ctx, pool);
1691
1692 /*
1693 * Audio assigned in order first come first get.
1694 * There are asics which has number of audio
1695 * resources less then number of pipes
1696 */
1697 if (pipe_ctx->stream_res.audio)
1698 update_audio_usage(&context->res_ctx, pool,
1699 pipe_ctx->stream_res.audio, true);
1700 }
268cadbd 1701
1dc90497
AG		 1702 for (i = 0; i < context->stream_count; i++)
1703 if (context->streams[i] == stream) {
1704 context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst;
0f0bdca5 1705 context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.stream_enc->id;
1dc90497
AG		 1706 return DC_OK;
1707 }
4562236b 1708
1dc90497
AG		 1709 DC_ERROR("Stream %p not found in new ctx!\n", stream);
1710 return DC_ERROR_UNEXPECTED;
1711}
4562236b 1712
1dc90497
AG		 1713/* first stream in the context is used to populate the rest */
1714void validate_guaranteed_copy_streams(
608ac7bb 1715 struct dc_state *context,
1dc90497
AG		 1716 int max_streams)
1717{
1718 int i;
ab2541b6 1719
1dc90497
AG		 1720 for (i = 1; i < max_streams; i++) {
1721 context->streams[i] = context->streams[0];
ab2541b6 1722
1dc90497
AG		 1723 copy_pipe_ctx(&context->res_ctx.pipe_ctx[0],
1724 &context->res_ctx.pipe_ctx[i]);
1725 context->res_ctx.pipe_ctx[i].stream =
1726 context->res_ctx.pipe_ctx[0].stream;
ab2541b6 1727
1dc90497
AG		 1728 dc_stream_retain(context->streams[i]);
1729 context->stream_count++;
4562236b 1730 }
1dc90497 1731}
4562236b 1732
f36cc577 1733void dc_resource_state_copy_construct_current(
1dc90497 1734 const struct dc *dc,
608ac7bb 1735 struct dc_state *dst_ctx)
1dc90497 1736{
f36cc577 1737 dc_resource_state_copy_construct(dc->current_state, dst_ctx);
1dc90497
AG		 1738}
1739
ab8db3e1
AG		 1740
1741void dc_resource_state_construct(
1742 const struct dc *dc,
1743 struct dc_state *dst_ctx)
1744{
1745 dst_ctx->dis_clk = dc->res_pool->display_clock;
1746}
1747
e750d56d 1748enum dc_status dc_validate_global_state(
1dc90497 1749 struct dc *dc,
608ac7bb 1750 struct dc_state *new_ctx)
4562236b 1751{
1dc90497 1752 enum dc_status result = DC_ERROR_UNEXPECTED;
1dc90497 1753 int i, j;
4562236b 1754
d596e5d0
YS		 1755 if (dc->res_pool->funcs->validate_global) {
1756 result = dc->res_pool->funcs->validate_global(dc, new_ctx);
1757 if (result != DC_OK)
1758 return result;
1759 }
4562236b 1760
1dc90497
AG		 1761 for (i = 0; new_ctx && i < new_ctx->stream_count; i++) {
1762 struct dc_stream_state *stream = new_ctx->streams[i];
1763
1764 for (j = 0; j < dc->res_pool->pipe_count; j++) {
1765 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[j];
1766
1767 if (pipe_ctx->stream != stream)
1768 continue;
1769
1770 /* Switch to dp clock source only if there is
1771 * no non dp stream that shares the same timing
1772 * with the dp stream.
1773 */
1774 if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
1775 !find_pll_sharable_stream(stream, new_ctx)) {
1776
9d0dcecd 1777 resource_unreference_clock_source(
1dc90497
AG		 1778 &new_ctx->res_ctx,
1779 dc->res_pool,
9d0dcecd 1780 pipe_ctx->clock_source);
4a629536 1781
1dc90497
AG		 1782 pipe_ctx->clock_source = dc->res_pool->dp_clock_source;
1783 resource_reference_clock_source(
1784 &new_ctx->res_ctx,
1785 dc->res_pool,
1786 pipe_ctx->clock_source);
1787 }
1788 }
1789 }
1790
1dc90497
AG		 1791 result = resource_build_scaling_params_for_context(dc, new_ctx);
1792
1793 if (result == DC_OK)
1794 if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx))
1795 result = DC_FAIL_BANDWIDTH_VALIDATE;
1796
1797 return result;
4562236b
HW		 1798}
1799
6e4d6bee
TC		 1800static void patch_gamut_packet_checksum(
1801 struct encoder_info_packet *gamut_packet)
4562236b 1802{
4562236b 1803 /* For gamut we recalc checksum */
6e4d6bee 1804 if (gamut_packet->valid) {
4562236b
HW		 1805 uint8_t chk_sum = 0;
1806 uint8_t *ptr;
1807 uint8_t i;
1808
4562236b 1809 /*start of the Gamut data. */
6e4d6bee 1810 ptr = &gamut_packet->sb[3];
4562236b 1811
6e4d6bee 1812 for (i = 0; i <= gamut_packet->sb[1]; i++)
4562236b
HW		 1813 chk_sum += ptr[i];
1814
6e4d6bee 1815 gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum);
1646a6fe 1816 }
4562236b
HW		 1817}
1818
1819static void set_avi_info_frame(
6e4d6bee 1820 struct encoder_info_packet *info_packet,
4562236b
HW		 1821 struct pipe_ctx *pipe_ctx)
1822{
0971c40e 1823 struct dc_stream_state *stream = pipe_ctx->stream;
4562236b
HW		 1824 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
1825 struct info_frame info_frame = { {0} };
1826 uint32_t pixel_encoding = 0;
1827 enum scanning_type scan_type = SCANNING_TYPE_NODATA;
1828 enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA;
1829 bool itc = false;
50e27654 1830 uint8_t itc_value = 0;
4562236b 1831 uint8_t cn0_cn1 = 0;
50e27654 1832 unsigned int cn0_cn1_value = 0;
4562236b
HW		 1833 uint8_t *check_sum = NULL;
1834 uint8_t byte_index = 0;
e8d726b7 1835 union hdmi_info_packet *hdmi_info = &info_frame.avi_info_packet.info_packet_hdmi;
50e27654 1836 union display_content_support support = {0};
4fa086b9 1837 unsigned int vic = pipe_ctx->stream->timing.vic;
15e17335 1838 enum dc_timing_3d_format format;
4562236b 1839
4fa086b9 1840 color_space = pipe_ctx->stream->output_color_space;
e5f2038e 1841 if (color_space == COLOR_SPACE_UNKNOWN)
4fa086b9 1842 color_space = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ?
e5f2038e 1843 COLOR_SPACE_SRGB:COLOR_SPACE_YCBCR709;
4562236b
HW		 1844
1845 /* Initialize header */
e8d726b7 1846 hdmi_info->bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI;
4562236b
HW		 1847 /* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall
1848 * not be used in HDMI 2.0 (Section 10.1) */
e8d726b7
RA		 1849 hdmi_info->bits.header.version = 2;
1850 hdmi_info->bits.header.length = HDMI_AVI_INFOFRAME_SIZE;
4562236b
HW		 1851
1852 /*
1853 * IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built
1854 * according to HDMI 2.0 spec (Section 10.1)
1855 */
1856
4fa086b9 1857 switch (stream->timing.pixel_encoding) {
4562236b
HW		 1858 case PIXEL_ENCODING_YCBCR422:
1859 pixel_encoding = 1;
1860 break;
1861
1862 case PIXEL_ENCODING_YCBCR444:
1863 pixel_encoding = 2;
1864 break;
1865 case PIXEL_ENCODING_YCBCR420:
1866 pixel_encoding = 3;
1867 break;
1868
1869 case PIXEL_ENCODING_RGB:
1870 default:
1871 pixel_encoding = 0;
1872 }
1873
1874 /* Y0_Y1_Y2 : The pixel encoding */
1875 /* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */
e8d726b7 1876 hdmi_info->bits.Y0_Y1_Y2 = pixel_encoding;
4562236b
HW		 1877
1878 /* A0 = 1 Active Format Information valid */
e8d726b7 1879 hdmi_info->bits.A0 = ACTIVE_FORMAT_VALID;
4562236b
HW		 1880
1881 /* B0, B1 = 3; Bar info data is valid */
e8d726b7 1882 hdmi_info->bits.B0_B1 = BAR_INFO_BOTH_VALID;
4562236b 1883
e8d726b7 1884 hdmi_info->bits.SC0_SC1 = PICTURE_SCALING_UNIFORM;
4562236b
HW		 1885
1886 /* S0, S1 : Underscan / Overscan */
1887 /* TODO: un-hardcode scan type */
1888 scan_type = SCANNING_TYPE_UNDERSCAN;
e8d726b7 1889 hdmi_info->bits.S0_S1 = scan_type;
4562236b
HW		 1890
1891 /* C0, C1 : Colorimetry */
8fde5884 1892 if (color_space == COLOR_SPACE_YCBCR709 ||
15e17335 1893 color_space == COLOR_SPACE_YCBCR709_LIMITED)
e8d726b7 1894 hdmi_info->bits.C0_C1 = COLORIMETRY_ITU709;
8fde5884
CL		 1895 else if (color_space == COLOR_SPACE_YCBCR601 ||
1896 color_space == COLOR_SPACE_YCBCR601_LIMITED)
e8d726b7 1897 hdmi_info->bits.C0_C1 = COLORIMETRY_ITU601;
8fde5884 1898 else {
e8d726b7 1899 hdmi_info->bits.C0_C1 = COLORIMETRY_NO_DATA;
8fde5884 1900 }
534db198 1901 if (color_space == COLOR_SPACE_2020_RGB_FULLRANGE ||
8fde5884
CL		 1902 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE ||
1903 color_space == COLOR_SPACE_2020_YCBCR) {
e8d726b7
RA		 1904 hdmi_info->bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR;
1905 hdmi_info->bits.C0_C1 = COLORIMETRY_EXTENDED;
534db198 1906 } else if (color_space == COLOR_SPACE_ADOBERGB) {
e8d726b7
RA		 1907 hdmi_info->bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB;
1908 hdmi_info->bits.C0_C1 = COLORIMETRY_EXTENDED;
534db198
AZ		 1909 }
1910
4562236b 1911 /* TODO: un-hardcode aspect ratio */
4fa086b9 1912 aspect = stream->timing.aspect_ratio;
4562236b
HW		 1913
1914 switch (aspect) {
1915 case ASPECT_RATIO_4_3:
1916 case ASPECT_RATIO_16_9:
e8d726b7 1917 hdmi_info->bits.M0_M1 = aspect;
4562236b
HW		 1918 break;
1919
1920 case ASPECT_RATIO_NO_DATA:
1921 case ASPECT_RATIO_64_27:
1922 case ASPECT_RATIO_256_135:
1923 default:
e8d726b7 1924 hdmi_info->bits.M0_M1 = 0;
4562236b
HW		 1925 }
1926
1927 /* Active Format Aspect ratio - same as Picture Aspect Ratio. */
e8d726b7 1928 hdmi_info->bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE;
4562236b
HW		 1929
1930 /* TODO: un-hardcode cn0_cn1 and itc */
50e27654 1931
4562236b 1932 cn0_cn1 = 0;
50e27654
ZF		 1933 cn0_cn1_value = 0;
1934
1935 itc = true;
1936 itc_value = 1;
1937
4fa086b9 1938 support = stream->sink->edid_caps.content_support;
4562236b
HW		 1939
1940 if (itc) {
50e27654
ZF		 1941 if (!support.bits.valid_content_type) {
1942 cn0_cn1_value = 0;
1943 } else {
1944 if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GRAPHICS) {
1945 if (support.bits.graphics_content == 1) {
1946 cn0_cn1_value = 0;
1947 }
1948 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_PHOTO) {
1949 if (support.bits.photo_content == 1) {
1950 cn0_cn1_value = 1;
1951 } else {
1952 cn0_cn1_value = 0;
1953 itc_value = 0;
1954 }
1955 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_CINEMA) {
1956 if (support.bits.cinema_content == 1) {
1957 cn0_cn1_value = 2;
1958 } else {
1959 cn0_cn1_value = 0;
1960 itc_value = 0;
1961 }
1962 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GAME) {
1963 if (support.bits.game_content == 1) {
1964 cn0_cn1_value = 3;
1965 } else {
1966 cn0_cn1_value = 0;
1967 itc_value = 0;
1968 }
1969 }
1970 }
1971 hdmi_info->bits.CN0_CN1 = cn0_cn1_value;
1972 hdmi_info->bits.ITC = itc_value;
4562236b
HW		 1973 }
1974
1975 /* TODO : We should handle YCC quantization */
1976 /* but we do not have matrix calculation */
4fa086b9
LSL		 1977 if (stream->sink->edid_caps.qs_bit == 1 &&
1978 stream->sink->edid_caps.qy_bit == 1) {
50e27654
ZF		 1979 if (color_space == COLOR_SPACE_SRGB ||
1980 color_space == COLOR_SPACE_2020_RGB_FULLRANGE) {
1981 hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_FULL_RANGE;
1982 hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_FULL_RANGE;
1983 } else if (color_space == COLOR_SPACE_SRGB_LIMITED ||
1984 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE) {
1985 hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_LIMITED_RANGE;
1986 hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
1987 } else {
1988 hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
1989 hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
1990 }
4562236b 1991 } else {
e8d726b7 1992 hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
50e27654 1993 hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
4562236b 1994 }
50e27654 1995
15e17335 1996 ///VIC
4fa086b9 1997 format = stream->timing.timing_3d_format;
15e17335
CL		 1998 /*todo, add 3DStereo support*/
1999 if (format != TIMING_3D_FORMAT_NONE) {
2000 // Based on HDMI specs hdmi vic needs to be converted to cea vic when 3D is enabled
4fa086b9 2001 switch (pipe_ctx->stream->timing.hdmi_vic) {
15e17335
CL		 2002 case 1:
2003 vic = 95;
2004 break;
2005 case 2:
2006 vic = 94;
2007 break;
2008 case 3:
2009 vic = 93;
2010 break;
2011 case 4:
2012 vic = 98;
2013 break;
2014 default:
2015 break;
2016 }
2017 }
2018 hdmi_info->bits.VIC0_VIC7 = vic;
4562236b
HW		 2019
2020 /* pixel repetition
2021 * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel
2022 * repetition start from 1 */
e8d726b7 2023 hdmi_info->bits.PR0_PR3 = 0;
4562236b
HW		 2024
2025 /* Bar Info
2026 * barTop: Line Number of End of Top Bar.
2027 * barBottom: Line Number of Start of Bottom Bar.
2028 * barLeft: Pixel Number of End of Left Bar.
2029 * barRight: Pixel Number of Start of Right Bar. */
4fa086b9
LSL		 2030 hdmi_info->bits.bar_top = stream->timing.v_border_top;
2031 hdmi_info->bits.bar_bottom = (stream->timing.v_total
2032 - stream->timing.v_border_bottom + 1);
2033 hdmi_info->bits.bar_left = stream->timing.h_border_left;
2034 hdmi_info->bits.bar_right = (stream->timing.h_total
2035 - stream->timing.h_border_right + 1);
4562236b
HW		 2036
2037 /* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */
e8d726b7
RA		 2038 check_sum = &info_frame.avi_info_packet.info_packet_hdmi.packet_raw_data.sb[0];
2039
3e183c5f 2040 *check_sum = HDMI_INFOFRAME_TYPE_AVI + HDMI_AVI_INFOFRAME_SIZE + 2;
4562236b 2041
3e183c5f 2042 for (byte_index = 1; byte_index <= HDMI_AVI_INFOFRAME_SIZE; byte_index++)
e8d726b7 2043 *check_sum += hdmi_info->packet_raw_data.sb[byte_index];
4562236b
HW		 2044
2045 /* one byte complement */
2046 *check_sum = (uint8_t) (0x100 - *check_sum);
2047
2048 /* Store in hw_path_mode */
e8d726b7
RA		 2049 info_packet->hb0 = hdmi_info->packet_raw_data.hb0;
2050 info_packet->hb1 = hdmi_info->packet_raw_data.hb1;
2051 info_packet->hb2 = hdmi_info->packet_raw_data.hb2;
4562236b 2052
e66e4d64
HW		 2053 for (byte_index = 0; byte_index < sizeof(info_frame.avi_info_packet.
2054 info_packet_hdmi.packet_raw_data.sb); byte_index++)
4562236b 2055 info_packet->sb[byte_index] = info_frame.avi_info_packet.
e66e4d64 2056 info_packet_hdmi.packet_raw_data.sb[byte_index];
4562236b
HW		 2057
2058 info_packet->valid = true;
2059}
2060
6e4d6bee
TC		 2061static void set_vendor_info_packet(
2062 struct encoder_info_packet *info_packet,
0971c40e 2063 struct dc_stream_state *stream)
4562236b
HW		 2064{
2065 uint32_t length = 0;
2066 bool hdmi_vic_mode = false;
2067 uint8_t checksum = 0;
2068 uint32_t i = 0;
2069 enum dc_timing_3d_format format;
15e17335
CL		 2070 // Can be different depending on packet content /*todo*/
2071 // unsigned int length = pPathMode->dolbyVision ? 24 : 5;
2072
2073 info_packet->valid = false;
4562236b 2074
4fa086b9
LSL		 2075 format = stream->timing.timing_3d_format;
2076 if (stream->view_format == VIEW_3D_FORMAT_NONE)
7f5c22d1 2077 format = TIMING_3D_FORMAT_NONE;
4562236b
HW		 2078
2079 /* Can be different depending on packet content */
2080 length = 5;
2081
4fa086b9
LSL		 2082 if (stream->timing.hdmi_vic != 0
2083 && stream->timing.h_total >= 3840
2084 && stream->timing.v_total >= 2160)
4562236b
HW		 2085 hdmi_vic_mode = true;
2086
2087 /* According to HDMI 1.4a CTS, VSIF should be sent
2088 * for both 3D stereo and HDMI VIC modes.
2089 * For all other modes, there is no VSIF sent. */
2090
2091 if (format == TIMING_3D_FORMAT_NONE && !hdmi_vic_mode)
2092 return;
2093
2094 /* 24bit IEEE Registration identifier (0x000c03). LSB first. */
2095 info_packet->sb[1] = 0x03;
2096 info_packet->sb[2] = 0x0C;
2097 info_packet->sb[3] = 0x00;
2098
2099 /*PB4: 5 lower bytes = 0 (reserved). 3 higher bits = HDMI_Video_Format.
2100 * The value for HDMI_Video_Format are:
2101 * 0x0 (0b000) - No additional HDMI video format is presented in this
2102 * packet
2103 * 0x1 (0b001) - Extended resolution format present. 1 byte of HDMI_VIC
2104 * parameter follows
2105 * 0x2 (0b010) - 3D format indication present. 3D_Structure and
2106 * potentially 3D_Ext_Data follows
2107 * 0x3..0x7 (0b011..0b111) - reserved for future use */
2108 if (format != TIMING_3D_FORMAT_NONE)
2109 info_packet->sb[4] = (2 << 5);
2110 else if (hdmi_vic_mode)
2111 info_packet->sb[4] = (1 << 5);
2112
2113 /* PB5: If PB4 claims 3D timing (HDMI_Video_Format = 0x2):
2114 * 4 lower bites = 0 (reserved). 4 higher bits = 3D_Structure.
2115 * The value for 3D_Structure are:
2116 * 0x0 - Frame Packing
2117 * 0x1 - Field Alternative
2118 * 0x2 - Line Alternative
2119 * 0x3 - Side-by-Side (full)
2120 * 0x4 - L + depth
2121 * 0x5 - L + depth + graphics + graphics-depth
2122 * 0x6 - Top-and-Bottom
2123 * 0x7 - Reserved for future use
2124 * 0x8 - Side-by-Side (Half)
2125 * 0x9..0xE - Reserved for future use
2126 * 0xF - Not used */
2127 switch (format) {
2128 case TIMING_3D_FORMAT_HW_FRAME_PACKING:
2129 case TIMING_3D_FORMAT_SW_FRAME_PACKING:
2130 info_packet->sb[5] = (0x0 << 4);
2131 break;
2132
2133 case TIMING_3D_FORMAT_SIDE_BY_SIDE:
2134 case TIMING_3D_FORMAT_SBS_SW_PACKED:
2135 info_packet->sb[5] = (0x8 << 4);
2136 length = 6;
2137 break;
2138
2139 case TIMING_3D_FORMAT_TOP_AND_BOTTOM:
2140 case TIMING_3D_FORMAT_TB_SW_PACKED:
2141 info_packet->sb[5] = (0x6 << 4);
2142 break;
2143
2144 default:
2145 break;
2146 }
2147
2148 /*PB5: If PB4 is set to 0x1 (extended resolution format)
2149 * fill PB5 with the correct HDMI VIC code */
2150 if (hdmi_vic_mode)
4fa086b9 2151 info_packet->sb[5] = stream->timing.hdmi_vic;
4562236b
HW		 2152
2153 /* Header */
3e183c5f 2154 info_packet->hb0 = HDMI_INFOFRAME_TYPE_VENDOR; /* VSIF packet type. */
4562236b
HW		 2155 info_packet->hb1 = 0x01; /* Version */
2156
2157 /* 4 lower bits = Length, 4 higher bits = 0 (reserved) */
2158 info_packet->hb2 = (uint8_t) (length);
2159
2160 /* Calculate checksum */
2161 checksum = 0;
2162 checksum += info_packet->hb0;
2163 checksum += info_packet->hb1;
2164 checksum += info_packet->hb2;
2165
2166 for (i = 1; i <= length; i++)
2167 checksum += info_packet->sb[i];
2168
2169 info_packet->sb[0] = (uint8_t) (0x100 - checksum);
2170
2171 info_packet->valid = true;
2172}
2173
6e4d6bee
TC		 2174static void set_spd_info_packet(
2175 struct encoder_info_packet *info_packet,
0971c40e 2176 struct dc_stream_state *stream)
4562236b
HW		 2177{
2178 /* SPD info packet for FreeSync */
2179
2180 unsigned char checksum = 0;
2181 unsigned int idx, payload_size = 0;
2182
2183 /* Check if Freesync is supported. Return if false. If true,
2184 * set the corresponding bit in the info packet
2185 */
4fa086b9 2186 if (stream->freesync_ctx.supported == false)
4562236b
HW		 2187 return;
2188
2189 if (dc_is_hdmi_signal(stream->signal)) {
2190
2191 /* HEADER */
2192
2193 /* HB0 = Packet Type = 0x83 (Source Product
2194 * Descriptor InfoFrame)
2195 */
3e183c5f 2196 info_packet->hb0 = HDMI_INFOFRAME_TYPE_SPD;
4562236b
HW		 2197
2198 /* HB1 = Version = 0x01 */
2199 info_packet->hb1 = 0x01;
2200
2201 /* HB2 = [Bits 7:5 = 0] [Bits 4:0 = Length = 0x08] */
2202 info_packet->hb2 = 0x08;
2203
2204 payload_size = 0x08;
2205
2206 } else if (dc_is_dp_signal(stream->signal)) {
2207
2208 /* HEADER */
2209
2210 /* HB0 = Secondary-data Packet ID = 0 - Only non-zero
2211 * when used to associate audio related info packets
2212 */
2213 info_packet->hb0 = 0x00;
2214
2215 /* HB1 = Packet Type = 0x83 (Source Product
2216 * Descriptor InfoFrame)
2217 */
3e183c5f 2218 info_packet->hb1 = HDMI_INFOFRAME_TYPE_SPD;
4562236b
HW		 2219
2220 /* HB2 = [Bits 7:0 = Least significant eight bits -
2221 * For INFOFRAME, the value must be 1Bh]
2222 */
2223 info_packet->hb2 = 0x1B;
2224
2225 /* HB3 = [Bits 7:2 = INFOFRAME SDP Version Number = 0x1]
2226 * [Bits 1:0 = Most significant two bits = 0x00]
2227 */
2228 info_packet->hb3 = 0x04;
2229
2230 payload_size = 0x1B;
2231 }
2232
2233 /* PB1 = 0x1A (24bit AMD IEEE OUI (0x00001A) - Byte 0) */
2234 info_packet->sb[1] = 0x1A;
2235
2236 /* PB2 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 1) */
2237 info_packet->sb[2] = 0x00;
2238
2239 /* PB3 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 2) */
2240 info_packet->sb[3] = 0x00;
2241
2242 /* PB4 = Reserved */
2243 info_packet->sb[4] = 0x00;
2244
2245 /* PB5 = Reserved */
2246 info_packet->sb[5] = 0x00;
2247
2248 /* PB6 = [Bits 7:3 = Reserved] */
2249 info_packet->sb[6] = 0x00;
2250
4fa086b9 2251 if (stream->freesync_ctx.supported == true)
4562236b
HW		 2252 /* PB6 = [Bit 0 = FreeSync Supported] */
2253 info_packet->sb[6] |= 0x01;
2254
4fa086b9 2255 if (stream->freesync_ctx.enabled == true)
4562236b
HW		 2256 /* PB6 = [Bit 1 = FreeSync Enabled] */
2257 info_packet->sb[6] |= 0x02;
2258
4fa086b9 2259 if (stream->freesync_ctx.active == true)
4562236b
HW		 2260 /* PB6 = [Bit 2 = FreeSync Active] */
2261 info_packet->sb[6] |= 0x04;
2262
2263 /* PB7 = FreeSync Minimum refresh rate (Hz) */
4fa086b9 2264 info_packet->sb[7] = (unsigned char) (stream->freesync_ctx.
4562236b
HW		 2265 min_refresh_in_micro_hz / 1000000);
2266
2267 /* PB8 = FreeSync Maximum refresh rate (Hz)
2268 *
2269 * Note: We do not use the maximum capable refresh rate
2270 * of the panel, because we should never go above the field
2271 * rate of the mode timing set.
2272 */
4fa086b9 2273 info_packet->sb[8] = (unsigned char) (stream->freesync_ctx.
4562236b
HW		 2274 nominal_refresh_in_micro_hz / 1000000);
2275
2276 /* PB9 - PB27 = Reserved */
2277 for (idx = 9; idx <= 27; idx++)
2278 info_packet->sb[idx] = 0x00;
2279
2280 /* Calculate checksum */
2281 checksum += info_packet->hb0;
2282 checksum += info_packet->hb1;
2283 checksum += info_packet->hb2;
2284 checksum += info_packet->hb3;
2285
2286 for (idx = 1; idx <= payload_size; idx++)
2287 checksum += info_packet->sb[idx];
2288
2289 /* PB0 = Checksum (one byte complement) */
2290 info_packet->sb[0] = (unsigned char) (0x100 - checksum);
2291
2292 info_packet->valid = true;
2293}
2294
1646a6fe 2295static void set_hdr_static_info_packet(
6e4d6bee 2296 struct encoder_info_packet *info_packet,
3be5262e 2297 struct dc_plane_state *plane_state,
0971c40e 2298 struct dc_stream_state *stream)
1646a6fe 2299{
e5cf325b 2300 uint16_t i = 0;
1646a6fe 2301 enum signal_type signal = stream->signal;
e5cf325b
HW		 2302 struct dc_hdr_static_metadata hdr_metadata;
2303 uint32_t data;
1646a6fe 2304
3be5262e 2305 if (!plane_state)
1646a6fe
AW		 2306 return;
2307
3be5262e 2308 hdr_metadata = plane_state->hdr_static_ctx;
1646a6fe 2309
70063a59 2310 if (!hdr_metadata.hdr_supported)
10bff005
YS		 2311 return;
2312
1646a6fe
AW		 2313 if (dc_is_hdmi_signal(signal)) {
2314 info_packet->valid = true;
2315
2316 info_packet->hb0 = 0x87;
2317 info_packet->hb1 = 0x01;
2318 info_packet->hb2 = 0x1A;
2319 i = 1;
2320 } else if (dc_is_dp_signal(signal)) {
2321 info_packet->valid = true;
2322
2323 info_packet->hb0 = 0x00;
2324 info_packet->hb1 = 0x87;
2325 info_packet->hb2 = 0x1D;
2326 info_packet->hb3 = (0x13 << 2);
2327 i = 2;
2328 }
2329
1646a6fe
AW		 2330 data = hdr_metadata.is_hdr;
2331 info_packet->sb[i++] = data ? 0x02 : 0x00;
2332 info_packet->sb[i++] = 0x00;
2333
2334 data = hdr_metadata.chromaticity_green_x / 2;
2335 info_packet->sb[i++] = data & 0xFF;
2336 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2337
2338 data = hdr_metadata.chromaticity_green_y / 2;
2339 info_packet->sb[i++] = data & 0xFF;
2340 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2341
2342 data = hdr_metadata.chromaticity_blue_x / 2;
2343 info_packet->sb[i++] = data & 0xFF;
2344 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2345
2346 data = hdr_metadata.chromaticity_blue_y / 2;
2347 info_packet->sb[i++] = data & 0xFF;
2348 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2349
2350 data = hdr_metadata.chromaticity_red_x / 2;
2351 info_packet->sb[i++] = data & 0xFF;
2352 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2353
2354 data = hdr_metadata.chromaticity_red_y / 2;
2355 info_packet->sb[i++] = data & 0xFF;
2356 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2357
2358 data = hdr_metadata.chromaticity_white_point_x / 2;
2359 info_packet->sb[i++] = data & 0xFF;
2360 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2361
2362 data = hdr_metadata.chromaticity_white_point_y / 2;
2363 info_packet->sb[i++] = data & 0xFF;
2364 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2365
2366 data = hdr_metadata.max_luminance;
2367 info_packet->sb[i++] = data & 0xFF;
2368 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2369
2370 data = hdr_metadata.min_luminance;
2371 info_packet->sb[i++] = data & 0xFF;
2372 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2373
2374 data = hdr_metadata.maximum_content_light_level;
2375 info_packet->sb[i++] = data & 0xFF;
2376 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2377
2378 data = hdr_metadata.maximum_frame_average_light_level;
2379 info_packet->sb[i++] = data & 0xFF;
2380 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2381
2382 if (dc_is_hdmi_signal(signal)) {
2383 uint32_t checksum = 0;
2384
2385 checksum += info_packet->hb0;
2386 checksum += info_packet->hb1;
2387 checksum += info_packet->hb2;
2388
2389 for (i = 1; i <= info_packet->hb2; i++)
2390 checksum += info_packet->sb[i];
2391
2392 info_packet->sb[0] = 0x100 - checksum;
2393 } else if (dc_is_dp_signal(signal)) {
2394 info_packet->sb[0] = 0x01;
2395 info_packet->sb[1] = 0x1A;
2396 }
2397}
2398
6e4d6bee
TC		 2399static void set_vsc_info_packet(
2400 struct encoder_info_packet *info_packet,
0971c40e 2401 struct dc_stream_state *stream)
4562236b
HW		 2402{
2403 unsigned int vscPacketRevision = 0;
2404 unsigned int i;
2405
94267b3d 2406 if (stream->sink->link->psr_enabled) {
4562236b
HW		 2407 vscPacketRevision = 2;
2408 }
2409
2410 /* VSC packet not needed based on the features
2411 * supported by this DP display
2412 */
2413 if (vscPacketRevision == 0)
2414 return;
2415
2416 if (vscPacketRevision == 0x2) {
2417 /* Secondary-data Packet ID = 0*/
2418 info_packet->hb0 = 0x00;
2419 /* 07h - Packet Type Value indicating Video
2420 * Stream Configuration packet
2421 */
2422 info_packet->hb1 = 0x07;
2423 /* 02h = VSC SDP supporting 3D stereo and PSR
2424 * (applies to eDP v1.3 or higher).
2425 */
2426 info_packet->hb2 = 0x02;
2427 /* 08h = VSC packet supporting 3D stereo + PSR
2428 * (HB2 = 02h).
2429 */
2430 info_packet->hb3 = 0x08;
2431
2432 for (i = 0; i < 28; i++)
2433 info_packet->sb[i] = 0;
2434
2435 info_packet->valid = true;
2436 }
2437
2438 /*TODO: stereo 3D support and extend pixel encoding colorimetry*/
2439}
2440
f36cc577 2441void dc_resource_state_destruct(struct dc_state *context)
4562236b
HW		 2442{
2443 int i, j;
2444
ab2541b6 2445 for (i = 0; i < context->stream_count; i++) {
3be5262e
HW		 2446 for (j = 0; j < context->stream_status[i].plane_count; j++)
2447 dc_plane_state_release(
2448 context->stream_status[i].plane_states[j]);
4562236b 2449
3be5262e 2450 context->stream_status[i].plane_count = 0;
4fa086b9 2451 dc_stream_release(context->streams[i]);
ab2541b6 2452 context->streams[i] = NULL;
4562236b
HW		 2453 }
2454}
2455
2456/*
ab2541b6 2457 * Copy src_ctx into dst_ctx and retain all surfaces and streams referenced
4562236b
HW		 2458 * by the src_ctx
2459 */
f36cc577 2460void dc_resource_state_copy_construct(
608ac7bb
JZ		 2461 const struct dc_state *src_ctx,
2462 struct dc_state *dst_ctx)
4562236b
HW		 2463{
2464 int i, j;
8ee5702a 2465 struct kref refcount = dst_ctx->refcount;
4562236b
HW		 2466
2467 *dst_ctx = *src_ctx;
2468
a2b8659d 2469 for (i = 0; i < MAX_PIPES; i++) {
4562236b
HW		 2470 struct pipe_ctx *cur_pipe = &dst_ctx->res_ctx.pipe_ctx[i];
2471
2472 if (cur_pipe->top_pipe)
2473 cur_pipe->top_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
2474
2475 if (cur_pipe->bottom_pipe)
2476 cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
2477
2478 }
2479
ab2541b6 2480 for (i = 0; i < dst_ctx->stream_count; i++) {
4fa086b9 2481 dc_stream_retain(dst_ctx->streams[i]);
3be5262e
HW		 2482 for (j = 0; j < dst_ctx->stream_status[i].plane_count; j++)
2483 dc_plane_state_retain(
2484 dst_ctx->stream_status[i].plane_states[j]);
4562236b 2485 }
9a3afbb3
AG		 2486
2487 /* context refcount should not be overridden */
8ee5702a 2488 dst_ctx->refcount = refcount;
9a3afbb3 2489
4562236b
HW		 2490}
2491
2492struct clock_source *dc_resource_find_first_free_pll(
a2b8659d
TC		 2493 struct resource_context *res_ctx,
2494 const struct resource_pool *pool)
4562236b
HW		 2495{
2496 int i;
2497
a2b8659d 2498 for (i = 0; i < pool->clk_src_count; ++i) {
4562236b 2499 if (res_ctx->clock_source_ref_count[i] == 0)
a2b8659d 2500 return pool->clock_sources[i];
4562236b
HW		 2501 }
2502
2503 return NULL;
2504}
2505
2506void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
2507{
2508 enum signal_type signal = SIGNAL_TYPE_NONE;
96c50c0d 2509 struct encoder_info_frame *info = &pipe_ctx->stream_res.encoder_info_frame;
4562236b
HW		 2510
2511 /* default all packets to invalid */
6e4d6bee
TC		 2512 info->avi.valid = false;
2513 info->gamut.valid = false;
2514 info->vendor.valid = false;
630e3573 2515 info->spd.valid = false;
6e4d6bee
TC		 2516 info->hdrsmd.valid = false;
2517 info->vsc.valid = false;
4562236b
HW		 2518
2519 signal = pipe_ctx->stream->signal;
2520
2521 /* HDMi and DP have different info packets*/
2522 if (dc_is_hdmi_signal(signal)) {
6e4d6bee
TC		 2523 set_avi_info_frame(&info->avi, pipe_ctx);
2524
2525 set_vendor_info_packet(&info->vendor, pipe_ctx->stream);
2526
2527 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2528
2529 set_hdr_static_info_packet(&info->hdrsmd,
3be5262e 2530 pipe_ctx->plane_state, pipe_ctx->stream);
6e4d6bee 2531
a33fa99d 2532 } else if (dc_is_dp_signal(signal)) {
6e4d6bee
TC		 2533 set_vsc_info_packet(&info->vsc, pipe_ctx->stream);
2534
2535 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2536
2537 set_hdr_static_info_packet(&info->hdrsmd,
3be5262e 2538 pipe_ctx->plane_state, pipe_ctx->stream);
a33fa99d 2539 }
4562236b 2540
6e4d6bee 2541 patch_gamut_packet_checksum(&info->gamut);
4562236b
HW		 2542}
2543
2544enum dc_status resource_map_clock_resources(
fb3466a4 2545 const struct dc *dc,
608ac7bb 2546 struct dc_state *context,
1dc90497 2547 struct dc_stream_state *stream)
4562236b 2548{
4562236b 2549 /* acquire new resources */
1dc90497
AG		 2550 const struct resource_pool *pool = dc->res_pool;
2551 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(
2552 &context->res_ctx, stream);
ab2541b6 2553
1dc90497
AG		 2554 if (!pipe_ctx)
2555 return DC_ERROR_UNEXPECTED;
4562236b 2556
1dc90497
AG		 2557 if (dc_is_dp_signal(pipe_ctx->stream->signal)
2558 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)
2559 pipe_ctx->clock_source = pool->dp_clock_source;
2560 else {
2561 pipe_ctx->clock_source = NULL;
4562236b 2562
1dc90497 2563 if (!dc->config.disable_disp_pll_sharing)
4ed4e51b 2564 pipe_ctx->clock_source = resource_find_used_clk_src_for_sharing(
1dc90497
AG		 2565 &context->res_ctx,
2566 pipe_ctx);
4562236b 2567
1dc90497
AG		 2568 if (pipe_ctx->clock_source == NULL)
2569 pipe_ctx->clock_source =
2570 dc_resource_find_first_free_pll(
2571 &context->res_ctx,
2572 pool);
2573 }
4562236b 2574
1dc90497
AG		 2575 if (pipe_ctx->clock_source == NULL)
2576 return DC_NO_CLOCK_SOURCE_RESOURCE;
4562236b 2577
1dc90497
AG		 2578 resource_reference_clock_source(
2579 &context->res_ctx, pool,
2580 pipe_ctx->clock_source);
4562236b
HW		 2581
2582 return DC_OK;
2583}
2584
2585/*
2586 * Note: We need to disable output if clock sources change,
2587 * since bios does optimization and doesn't apply if changing
2588 * PHY when not already disabled.
2589 */
2590bool pipe_need_reprogram(
2591 struct pipe_ctx *pipe_ctx_old,
2592 struct pipe_ctx *pipe_ctx)
2593{
cfe4645e
DL		 2594 if (!pipe_ctx_old->stream)
2595 return false;
2596
4562236b
HW		 2597 if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink)
2598 return true;
2599
2600 if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal)
2601 return true;
2602
afaacef4 2603 if (pipe_ctx_old->stream_res.audio != pipe_ctx->stream_res.audio)
4562236b
HW		 2604 return true;
2605
2606 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source
2607 && pipe_ctx_old->stream != pipe_ctx->stream)
2608 return true;
2609
8e9c4c8c 2610 if (pipe_ctx_old->stream_res.stream_enc != pipe_ctx->stream_res.stream_enc)
4562236b
HW		 2611 return true;
2612
2613 if (is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2614 return true;
2615
2616
2617 return false;
2618}
529cad0f 2619
0971c40e 2620void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream,
529cad0f
DW		 2621 struct bit_depth_reduction_params *fmt_bit_depth)
2622{
4fa086b9 2623 enum dc_dither_option option = stream->dither_option;
529cad0f 2624 enum dc_pixel_encoding pixel_encoding =
4fa086b9 2625 stream->timing.pixel_encoding;
529cad0f
DW		 2626
2627 memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth));
2628
603767f9
TC		 2629 if (option == DITHER_OPTION_DEFAULT) {
2630 switch (stream->timing.display_color_depth) {
2631 case COLOR_DEPTH_666:
2632 option = DITHER_OPTION_SPATIAL6;
2633 break;
2634 case COLOR_DEPTH_888:
2635 option = DITHER_OPTION_SPATIAL8;
2636 break;
2637 case COLOR_DEPTH_101010:
2638 option = DITHER_OPTION_SPATIAL10;
2639 break;
2640 default:
2641 option = DITHER_OPTION_DISABLE;
2642 }
2643 }
2644
529cad0f
DW		 2645 if (option == DITHER_OPTION_DISABLE)
2646 return;
2647
2648 if (option == DITHER_OPTION_TRUN6) {
2649 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2650 fmt_bit_depth->flags.TRUNCATE_DEPTH = 0;
2651 } else if (option == DITHER_OPTION_TRUN8 ||
2652 option == DITHER_OPTION_TRUN8_SPATIAL6 ||
2653 option == DITHER_OPTION_TRUN8_FM6) {
2654 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2655 fmt_bit_depth->flags.TRUNCATE_DEPTH = 1;
2656 } else if (option == DITHER_OPTION_TRUN10 ||
2657 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
2658 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
2659 option == DITHER_OPTION_TRUN10_FM8 ||
2660 option == DITHER_OPTION_TRUN10_FM6 ||
2661 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2662 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2663 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2664 }
2665
2666 /* special case - Formatter can only reduce by 4 bits at most.
2667 * When reducing from 12 to 6 bits,
2668 * HW recommends we use trunc with round mode
2669 * (if we did nothing, trunc to 10 bits would be used)
2670 * note that any 12->10 bit reduction is ignored prior to DCE8,
2671 * as the input was 10 bits.
2672 */
2673 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2674 option == DITHER_OPTION_SPATIAL6 ||
2675 option == DITHER_OPTION_FM6) {
2676 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2677 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2678 fmt_bit_depth->flags.TRUNCATE_MODE = 1;
2679 }
2680
2681 /* spatial dither
2682 * note that spatial modes 1-3 are never used
2683 */
2684 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2685 option == DITHER_OPTION_SPATIAL6 ||
2686 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
2687 option == DITHER_OPTION_TRUN8_SPATIAL6) {
2688 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2689 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 0;
2690 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2691 fmt_bit_depth->flags.RGB_RANDOM =
2692 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2693 } else if (option == DITHER_OPTION_SPATIAL8_FRAME_RANDOM ||
2694 option == DITHER_OPTION_SPATIAL8 ||
2695 option == DITHER_OPTION_SPATIAL8_FM6 ||
2696 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
2697 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2698 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2699 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 1;
2700 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2701 fmt_bit_depth->flags.RGB_RANDOM =
2702 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2703 } else if (option == DITHER_OPTION_SPATIAL10_FRAME_RANDOM ||
2704 option == DITHER_OPTION_SPATIAL10 ||
2705 option == DITHER_OPTION_SPATIAL10_FM8 ||
2706 option == DITHER_OPTION_SPATIAL10_FM6) {
2707 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2708 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 2;
2709 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2710 fmt_bit_depth->flags.RGB_RANDOM =
2711 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2712 }
2713
2714 if (option == DITHER_OPTION_SPATIAL6 ||
2715 option == DITHER_OPTION_SPATIAL8 ||
2716 option == DITHER_OPTION_SPATIAL10) {
2717 fmt_bit_depth->flags.FRAME_RANDOM = 0;
2718 } else {
2719 fmt_bit_depth->flags.FRAME_RANDOM = 1;
2720 }
2721
2722 //////////////////////
2723 //// temporal dither
2724 //////////////////////
2725 if (option == DITHER_OPTION_FM6 ||
2726 option == DITHER_OPTION_SPATIAL8_FM6 ||
2727 option == DITHER_OPTION_SPATIAL10_FM6 ||
2728 option == DITHER_OPTION_TRUN10_FM6 ||
2729 option == DITHER_OPTION_TRUN8_FM6 ||
2730 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2731 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2732 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 0;
2733 } else if (option == DITHER_OPTION_FM8 ||
2734 option == DITHER_OPTION_SPATIAL10_FM8 ||
2735 option == DITHER_OPTION_TRUN10_FM8) {
2736 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2737 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 1;
2738 } else if (option == DITHER_OPTION_FM10) {
2739 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2740 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 2;
2741 }
2742
2743 fmt_bit_depth->pixel_encoding = pixel_encoding;
2744}
9345d987 2745
fb3466a4 2746bool dc_validate_stream(struct dc *dc, struct dc_stream_state *stream)
9345d987 2747{
fb3466a4 2748 struct dc *core_dc = dc;
4fa086b9 2749 struct dc_link *link = stream->sink->link;
9345d987
AG		 2750 struct timing_generator *tg = core_dc->res_pool->timing_generators[0];
2751 enum dc_status res = DC_OK;
2752
4fa086b9 2753 calculate_phy_pix_clks(stream);
9345d987 2754
4fa086b9 2755 if (!tg->funcs->validate_timing(tg, &stream->timing))
9345d987
AG		 2756 res = DC_FAIL_CONTROLLER_VALIDATE;
2757
2758 if (res == DC_OK)
2759 if (!link->link_enc->funcs->validate_output_with_stream(
4fa086b9 2760 link->link_enc, stream))
9345d987
AG		 2761 res = DC_FAIL_ENC_VALIDATE;
2762
2763 /* TODO: validate audio ASIC caps, encoder */
2764
2765 if (res == DC_OK)
4fa086b9 2766 res = dc_link_validate_mode_timing(stream,
9345d987 2767 link,
4fa086b9 2768 &stream->timing);
9345d987 2769
9345d987
AG		 2770 return res == DC_OK;
2771}
792671d7 2772
fb3466a4 2773bool dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state)
792671d7 2774{
792671d7 2775 /* TODO For now validates pixel format only */
8e7095b9
DL		 2776 if (dc->res_pool->funcs->validate_plane)
2777 return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps) == DC_OK;
792671d7
AG		 2778
2779 return true;
2780}
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