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[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / display / dc / core / dc_resource.c
CommitLineData
4562236b
HW		 1/*
2* Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25#include "dm_services.h"
26
27#include "resource.h"
28#include "include/irq_service_interface.h"
29#include "link_encoder.h"
30#include "stream_encoder.h"
31#include "opp.h"
32#include "timing_generator.h"
33#include "transform.h"
5ac3d3c9 34#include "core_types.h"
4562236b 35#include "set_mode_types.h"
4562236b
HW		 36#include "virtual/virtual_stream_encoder.h"
37
38#include "dce80/dce80_resource.h"
39#include "dce100/dce100_resource.h"
40#include "dce110/dce110_resource.h"
41#include "dce112/dce112_resource.h"
ff5ef992
AD		 42#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
43#include "dcn10/dcn10_resource.h"
44#endif
2c8ad2d5 45#include "dce120/dce120_resource.h"
4562236b
HW		 46
47enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
48{
49 enum dce_version dc_version = DCE_VERSION_UNKNOWN;
50 switch (asic_id.chip_family) {
51
52 case FAMILY_CI:
53 case FAMILY_KV:
54 dc_version = DCE_VERSION_8_0;
55 break;
56 case FAMILY_CZ:
57 dc_version = DCE_VERSION_11_0;
58 break;
59
60 case FAMILY_VI:
61 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
62 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
63 dc_version = DCE_VERSION_10_0;
64 break;
65 }
66 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
b264d345
JL		 67 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
68 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
4562236b
HW		 69 dc_version = DCE_VERSION_11_2;
70 }
71 break;
2c8ad2d5
AD		 72 case FAMILY_AI:
73 dc_version = DCE_VERSION_12_0;
74 break;
ff5ef992
AD		 75#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
76 case FAMILY_RV:
77 dc_version = DCN_VERSION_1_0;
78 break;
79#endif
4562236b
HW		 80 default:
81 dc_version = DCE_VERSION_UNKNOWN;
82 break;
83 }
84 return dc_version;
85}
86
87struct resource_pool *dc_create_resource_pool(
88 struct core_dc *dc,
89 int num_virtual_links,
90 enum dce_version dc_version,
91 struct hw_asic_id asic_id)
92{
5ac3d3c9 93 struct resource_pool *res_pool = NULL;
4562236b
HW		 94
95 switch (dc_version) {
96 case DCE_VERSION_8_0:
5ac3d3c9 97 res_pool = dce80_create_resource_pool(
4562236b 98 num_virtual_links, dc);
5ac3d3c9 99 break;
4562236b 100 case DCE_VERSION_10_0:
5ac3d3c9 101 res_pool = dce100_create_resource_pool(
4562236b 102 num_virtual_links, dc);
5ac3d3c9 103 break;
4562236b 104 case DCE_VERSION_11_0:
5ac3d3c9 105 res_pool = dce110_create_resource_pool(
4562236b 106 num_virtual_links, dc, asic_id);
5ac3d3c9 107 break;
4562236b 108 case DCE_VERSION_11_2:
5ac3d3c9 109 res_pool = dce112_create_resource_pool(
4562236b 110 num_virtual_links, dc);
5ac3d3c9 111 break;
2c8ad2d5
AD		 112 case DCE_VERSION_12_0:
113 res_pool = dce120_create_resource_pool(
114 num_virtual_links, dc);
115 break;
ff5ef992
AD		 116
117#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
118 case DCN_VERSION_1_0:
119 res_pool = dcn10_create_resource_pool(
120 num_virtual_links, dc);
121 break;
122#endif
3639fa68
ZF		 123
124
4562236b
HW		 125 default:
126 break;
127 }
5ac3d3c9
CL		 128 if (res_pool != NULL) {
129 struct firmware_info fw_info = { { 0 } };
130
131 if (dc->ctx->dc_bios->funcs->get_firmware_info(
132 dc->ctx->dc_bios, &fw_info) == BP_RESULT_OK) {
133 res_pool->ref_clock_inKhz = fw_info.pll_info.crystal_frequency;
134 } else
135 ASSERT_CRITICAL(false);
136 }
4562236b 137
5ac3d3c9 138 return res_pool;
4562236b
HW		 139}
140
141void dc_destroy_resource_pool(struct core_dc *dc)
142{
143 if (dc) {
144 if (dc->res_pool)
145 dc->res_pool->funcs->destroy(&dc->res_pool);
146
147 if (dc->hwseq)
148 dm_free(dc->hwseq);
149 }
150}
151
152static void update_num_audio(
153 const struct resource_straps *straps,
154 unsigned int *num_audio,
155 struct audio_support *aud_support)
156{
157 if (straps->hdmi_disable == 0) {
158 aud_support->hdmi_audio_native = true;
159 aud_support->hdmi_audio_on_dongle = true;
160 aud_support->dp_audio = true;
161 } else {
162 if (straps->dc_pinstraps_audio & 0x2) {
163 aud_support->hdmi_audio_on_dongle = true;
164 aud_support->dp_audio = true;
165 } else {
166 aud_support->dp_audio = true;
167 }
168 }
169
170 switch (straps->audio_stream_number) {
171 case 0: /* multi streams supported */
172 break;
173 case 1: /* multi streams not supported */
174 *num_audio = 1;
175 break;
176 default:
177 DC_ERR("DC: unexpected audio fuse!\n");
17a96033 178 }
4562236b
HW		 179}
180
181bool resource_construct(
182 unsigned int num_virtual_links,
183 struct core_dc *dc,
184 struct resource_pool *pool,
185 const struct resource_create_funcs *create_funcs)
186{
187 struct dc_context *ctx = dc->ctx;
188 const struct resource_caps *caps = pool->res_cap;
189 int i;
190 unsigned int num_audio = caps->num_audio;
191 struct resource_straps straps = {0};
192
193 if (create_funcs->read_dce_straps)
194 create_funcs->read_dce_straps(dc->ctx, &straps);
195
196 pool->audio_count = 0;
197 if (create_funcs->create_audio) {
198 /* find the total number of streams available via the
199 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
200 * registers (one for each pin) starting from pin 1
201 * up to the max number of audio pins.
202 * We stop on the first pin where
203 * PORT_CONNECTIVITY == 1 (as instructed by HW team).
204 */
205 update_num_audio(&straps, &num_audio, &pool->audio_support);
206 for (i = 0; i < pool->pipe_count && i < num_audio; i++) {
207 struct audio *aud = create_funcs->create_audio(ctx, i);
208
209 if (aud == NULL) {
210 DC_ERR("DC: failed to create audio!\n");
211 return false;
212 }
213
214 if (!aud->funcs->endpoint_valid(aud)) {
215 aud->funcs->destroy(&aud);
216 break;
217 }
218
219 pool->audios[i] = aud;
220 pool->audio_count++;
221 }
222 }
223
224 pool->stream_enc_count = 0;
225 if (create_funcs->create_stream_encoder) {
226 for (i = 0; i < caps->num_stream_encoder; i++) {
227 pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx);
228 if (pool->stream_enc[i] == NULL)
229 DC_ERR("DC: failed to create stream_encoder!\n");
230 pool->stream_enc_count++;
231 }
232 }
233
234 for (i = 0; i < num_virtual_links; i++) {
235 pool->stream_enc[pool->stream_enc_count] =
236 virtual_stream_encoder_create(
237 ctx, ctx->dc_bios);
238 if (pool->stream_enc[pool->stream_enc_count] == NULL) {
239 DC_ERR("DC: failed to create stream_encoder!\n");
240 return false;
241 }
242 pool->stream_enc_count++;
243 }
244
245 dc->hwseq = create_funcs->create_hwseq(ctx);
246
247 return true;
248}
249
250
251void resource_unreference_clock_source(
252 struct resource_context *res_ctx,
a2b8659d 253 const struct resource_pool *pool,
8c737fcc 254 struct clock_source **clock_source)
4562236b
HW		 255{
256 int i;
a2b8659d
TC		 257 for (i = 0; i < pool->clk_src_count; i++) {
258 if (pool->clock_sources[i] != *clock_source)
4562236b
HW		 259 continue;
260
261 res_ctx->clock_source_ref_count[i]--;
262
263 if (res_ctx->clock_source_ref_count[i] == 0)
8c737fcc 264 (*clock_source)->funcs->cs_power_down(*clock_source);
4562236b
HW		 265
266 break;
267 }
268
a2b8659d 269 if (pool->dp_clock_source == *clock_source) {
4562236b
HW		 270 res_ctx->dp_clock_source_ref_count--;
271
272 if (res_ctx->dp_clock_source_ref_count == 0)
8c737fcc 273 (*clock_source)->funcs->cs_power_down(*clock_source);
4562236b 274 }
8c737fcc 275 *clock_source = NULL;
4562236b
HW		 276}
277
278void resource_reference_clock_source(
279 struct resource_context *res_ctx,
a2b8659d 280 const struct resource_pool *pool,
4562236b
HW		 281 struct clock_source *clock_source)
282{
283 int i;
a2b8659d
TC		 284 for (i = 0; i < pool->clk_src_count; i++) {
285 if (pool->clock_sources[i] != clock_source)
4562236b
HW		 286 continue;
287
288 res_ctx->clock_source_ref_count[i]++;
289 break;
290 }
291
a2b8659d 292 if (pool->dp_clock_source == clock_source)
4562236b
HW		 293 res_ctx->dp_clock_source_ref_count++;
294}
295
296bool resource_are_streams_timing_synchronizable(
297 const struct core_stream *stream1,
298 const struct core_stream *stream2)
299{
300 if (stream1->public.timing.h_total != stream2->public.timing.h_total)
301 return false;
302
303 if (stream1->public.timing.v_total != stream2->public.timing.v_total)
304 return false;
305
306 if (stream1->public.timing.h_addressable
307 != stream2->public.timing.h_addressable)
308 return false;
309
310 if (stream1->public.timing.v_addressable
311 != stream2->public.timing.v_addressable)
312 return false;
313
314 if (stream1->public.timing.pix_clk_khz
315 != stream2->public.timing.pix_clk_khz)
316 return false;
317
318 if (stream1->phy_pix_clk != stream2->phy_pix_clk
7e2fe319
CL		 319 && (!dc_is_dp_signal(stream1->signal)
320 || !dc_is_dp_signal(stream2->signal)))
4562236b
HW		 321 return false;
322
323 return true;
324}
325
326static bool is_sharable_clk_src(
327 const struct pipe_ctx *pipe_with_clk_src,
328 const struct pipe_ctx *pipe)
329{
330 if (pipe_with_clk_src->clock_source == NULL)
331 return false;
332
333 if (pipe_with_clk_src->stream->signal == SIGNAL_TYPE_VIRTUAL)
334 return false;
335
336 if (dc_is_dp_signal(pipe_with_clk_src->stream->signal))
337 return false;
338
339 if (dc_is_hdmi_signal(pipe_with_clk_src->stream->signal)
340 && dc_is_dvi_signal(pipe->stream->signal))
341 return false;
342
343 if (dc_is_hdmi_signal(pipe->stream->signal)
344 && dc_is_dvi_signal(pipe_with_clk_src->stream->signal))
345 return false;
346
347 if (!resource_are_streams_timing_synchronizable(
348 pipe_with_clk_src->stream, pipe->stream))
349 return false;
350
351 return true;
352}
353
354struct clock_source *resource_find_used_clk_src_for_sharing(
355 struct resource_context *res_ctx,
356 struct pipe_ctx *pipe_ctx)
357{
358 int i;
359
360 for (i = 0; i < MAX_PIPES; i++) {
361 if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx))
362 return res_ctx->pipe_ctx[i].clock_source;
363 }
364
365 return NULL;
366}
367
368static enum pixel_format convert_pixel_format_to_dalsurface(
369 enum surface_pixel_format surface_pixel_format)
370{
371 enum pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
372
373 switch (surface_pixel_format) {
374 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
375 dal_pixel_format = PIXEL_FORMAT_INDEX8;
376 break;
377 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
378 dal_pixel_format = PIXEL_FORMAT_RGB565;
379 break;
380 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
381 dal_pixel_format = PIXEL_FORMAT_RGB565;
382 break;
383 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
384 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
385 break;
8693049a 386 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
4562236b
HW		 387 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
388 break;
389 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
390 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
391 break;
392 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
393 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
394 break;
395 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
396 dal_pixel_format = PIXEL_FORMAT_ARGB2101010_XRBIAS;
397 break;
398 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
399 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
400 dal_pixel_format = PIXEL_FORMAT_FP16;
401 break;
402 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
4562236b 403 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
87449a90 404 dal_pixel_format = PIXEL_FORMAT_420BPP8;
4562236b 405 break;
ffbcd19a
VP		 406 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
407 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
87449a90 408 dal_pixel_format = PIXEL_FORMAT_420BPP10;
ffbcd19a 409 break;
4562236b
HW		 410 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
411 default:
412 dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
413 break;
414 }
415 return dal_pixel_format;
416}
417
418static void rect_swap_helper(struct rect *rect)
419{
420 uint32_t temp = 0;
421
422 temp = rect->height;
423 rect->height = rect->width;
424 rect->width = temp;
425
426 temp = rect->x;
427 rect->x = rect->y;
428 rect->y = temp;
429}
430
b2d0a103 431static void calculate_viewport(struct pipe_ctx *pipe_ctx)
4562236b 432{
e12cfcb1 433 const struct dc_surface *surface = pipe_ctx->surface;
1fbd2cfc 434 const struct dc_stream *stream = &pipe_ctx->stream->public;
b2d0a103 435 struct scaler_data *data = &pipe_ctx->scl_data;
86006a7f 436 struct rect surf_src = surface->src_rect;
1fbd2cfc 437 struct rect clip = { 0 };
87449a90
AK		 438 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
439 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
1fbd2cfc
DL		 440 bool pri_split = pipe_ctx->bottom_pipe &&
441 pipe_ctx->bottom_pipe->surface == pipe_ctx->surface;
442 bool sec_split = pipe_ctx->top_pipe &&
443 pipe_ctx->top_pipe->surface == pipe_ctx->surface;
4562236b 444
7f5c22d1
VP		 445 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE ||
446 stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) {
7b779c99
VP		 447 pri_split = false;
448 sec_split = false;
449 }
86006a7f 450
e12cfcb1
HW		 451 if (pipe_ctx->surface->rotation == ROTATION_ANGLE_90 ||
452 pipe_ctx->surface->rotation == ROTATION_ANGLE_270)
86006a7f
DL		 453 rect_swap_helper(&surf_src);
454
4562236b
HW		 455 /* The actual clip is an intersection between stream
456 * source and surface clip
457 */
1fbd2cfc
DL		 458 clip.x = stream->src.x > surface->clip_rect.x ?
459 stream->src.x : surface->clip_rect.x;
4562236b 460
1fbd2cfc
DL		 461 clip.width = stream->src.x + stream->src.width <
462 surface->clip_rect.x + surface->clip_rect.width ?
463 stream->src.x + stream->src.width - clip.x :
464 surface->clip_rect.x + surface->clip_rect.width - clip.x ;
4562236b 465
1fbd2cfc
DL		 466 clip.y = stream->src.y > surface->clip_rect.y ?
467 stream->src.y : surface->clip_rect.y;
4562236b 468
1fbd2cfc
DL		 469 clip.height = stream->src.y + stream->src.height <
470 surface->clip_rect.y + surface->clip_rect.height ?
471 stream->src.y + stream->src.height - clip.y :
472 surface->clip_rect.y + surface->clip_rect.height - clip.y ;
4562236b 473
86006a7f 474 /* offset = surf_src.ofs + (clip.ofs - surface->dst_rect.ofs) * scl_ratio
4562236b
HW		 475 * num_pixels = clip.num_pix * scl_ratio
476 */
86006a7f
DL		 477 data->viewport.x = surf_src.x + (clip.x - surface->dst_rect.x) *
478 surf_src.width / surface->dst_rect.width;
b2d0a103 479 data->viewport.width = clip.width *
86006a7f 480 surf_src.width / surface->dst_rect.width;
4562236b 481
86006a7f
DL		 482 data->viewport.y = surf_src.y + (clip.y - surface->dst_rect.y) *
483 surf_src.height / surface->dst_rect.height;
b2d0a103 484 data->viewport.height = clip.height *
86006a7f 485 surf_src.height / surface->dst_rect.height;
4562236b 486
b2d0a103
DL		 487 /* Round down, compensate in init */
488 data->viewport_c.x = data->viewport.x / vpc_div;
489 data->viewport_c.y = data->viewport.y / vpc_div;
490 data->inits.h_c = (data->viewport.x % vpc_div) != 0 ?
491 dal_fixed31_32_half : dal_fixed31_32_zero;
492 data->inits.v_c = (data->viewport.y % vpc_div) != 0 ?
493 dal_fixed31_32_half : dal_fixed31_32_zero;
494 /* Round up, assume original video size always even dimensions */
495 data->viewport_c.width = (data->viewport.width + vpc_div - 1) / vpc_div;
496 data->viewport_c.height = (data->viewport.height + vpc_div - 1) / vpc_div;
497
498 /* Handle hsplit */
1fbd2cfc
DL		 499 if (pri_split || sec_split) {
500 /* HMirror XOR Secondary_pipe XOR Rotation_180 */
501 bool right_view = (sec_split != surface->horizontal_mirror) !=
502 (surface->rotation == ROTATION_ANGLE_180);
503
504 if (surface->rotation == ROTATION_ANGLE_90
505 || surface->rotation == ROTATION_ANGLE_270)
506 /* Secondary_pipe XOR Rotation_270 */
507 right_view = (surface->rotation == ROTATION_ANGLE_270) != sec_split;
9e6c74ce
DL		 508
509 if (right_view) {
510 data->viewport.width /= 2;
511 data->viewport_c.width /= 2;
512 data->viewport.x += data->viewport.width;
513 data->viewport_c.x += data->viewport_c.width;
514 /* Ceil offset pipe */
515 data->viewport.width += data->viewport.width % 2;
516 data->viewport_c.width += data->viewport_c.width % 2;
517 } else {
518 data->viewport.width /= 2;
519 data->viewport_c.width /= 2;
520 }
b2d0a103 521 }
1fbd2cfc
DL		 522
523 if (surface->rotation == ROTATION_ANGLE_90 ||
524 surface->rotation == ROTATION_ANGLE_270) {
525 rect_swap_helper(&data->viewport_c);
526 rect_swap_helper(&data->viewport);
527 }
4562236b
HW		 528}
529
b2d0a103 530static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip)
4562236b 531{
e12cfcb1 532 const struct dc_surface *surface = pipe_ctx->surface;
4562236b 533 struct core_stream *stream = pipe_ctx->stream;
86006a7f
DL		 534 struct rect surf_src = surface->src_rect;
535 struct rect surf_clip = surface->clip_rect;
c802570e 536 int recout_full_x, recout_full_y;
4562236b 537
e12cfcb1
HW		 538 if (pipe_ctx->surface->rotation == ROTATION_ANGLE_90 ||
539 pipe_ctx->surface->rotation == ROTATION_ANGLE_270)
86006a7f
DL		 540 rect_swap_helper(&surf_src);
541
4562236b 542 pipe_ctx->scl_data.recout.x = stream->public.dst.x;
86006a7f
DL		 543 if (stream->public.src.x < surf_clip.x)
544 pipe_ctx->scl_data.recout.x += (surf_clip.x
4562236b
HW		 545 - stream->public.src.x) * stream->public.dst.width
546 / stream->public.src.width;
547
86006a7f 548 pipe_ctx->scl_data.recout.width = surf_clip.width *
4562236b
HW		 549 stream->public.dst.width / stream->public.src.width;
550 if (pipe_ctx->scl_data.recout.width + pipe_ctx->scl_data.recout.x >
551 stream->public.dst.x + stream->public.dst.width)
552 pipe_ctx->scl_data.recout.width =
553 stream->public.dst.x + stream->public.dst.width
554 - pipe_ctx->scl_data.recout.x;
555
556 pipe_ctx->scl_data.recout.y = stream->public.dst.y;
86006a7f
DL		 557 if (stream->public.src.y < surf_clip.y)
558 pipe_ctx->scl_data.recout.y += (surf_clip.y
4562236b
HW		 559 - stream->public.src.y) * stream->public.dst.height
560 / stream->public.src.height;
561
86006a7f 562 pipe_ctx->scl_data.recout.height = surf_clip.height *
4562236b
HW		 563 stream->public.dst.height / stream->public.src.height;
564 if (pipe_ctx->scl_data.recout.height + pipe_ctx->scl_data.recout.y >
565 stream->public.dst.y + stream->public.dst.height)
566 pipe_ctx->scl_data.recout.height =
567 stream->public.dst.y + stream->public.dst.height
568 - pipe_ctx->scl_data.recout.y;
b2d0a103 569
7b779c99
VP		 570 /* Handle h & vsplit */
571 if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->surface ==
572 pipe_ctx->surface) {
7f5c22d1 573 if (stream->public.view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) {
7b779c99
VP		 574 pipe_ctx->scl_data.recout.height /= 2;
575 pipe_ctx->scl_data.recout.y += pipe_ctx->scl_data.recout.height;
576 /* Floor primary pipe, ceil 2ndary pipe */
577 pipe_ctx->scl_data.recout.height += pipe_ctx->scl_data.recout.height % 2;
578 } else {
579 pipe_ctx->scl_data.recout.width /= 2;
580 pipe_ctx->scl_data.recout.x += pipe_ctx->scl_data.recout.width;
581 pipe_ctx->scl_data.recout.width += pipe_ctx->scl_data.recout.width % 2;
582 }
583 } else if (pipe_ctx->bottom_pipe &&
86006a7f 584 pipe_ctx->bottom_pipe->surface == pipe_ctx->surface) {
7f5c22d1 585 if (stream->public.view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
7b779c99
VP		 586 pipe_ctx->scl_data.recout.height /= 2;
587 else
588 pipe_ctx->scl_data.recout.width /= 2;
b2d0a103
DL		 589 }
590
86006a7f
DL		 591 /* Unclipped recout offset = stream dst offset + ((surf dst offset - stream surf_src offset)
592 * * 1/ stream scaling ratio) - (surf surf_src offset * 1/ full scl
c802570e
DL		 593 * ratio)
594 */
595 recout_full_x = stream->public.dst.x + (surface->dst_rect.x - stream->public.src.x)
596 * stream->public.dst.width / stream->public.src.width -
86006a7f 597 surf_src.x * surface->dst_rect.width / surf_src.width
c802570e
DL		 598 * stream->public.dst.width / stream->public.src.width;
599 recout_full_y = stream->public.dst.y + (surface->dst_rect.y - stream->public.src.y)
600 * stream->public.dst.height / stream->public.src.height -
86006a7f 601 surf_src.y * surface->dst_rect.height / surf_src.height
c802570e
DL		 602 * stream->public.dst.height / stream->public.src.height;
603
604 recout_skip->width = pipe_ctx->scl_data.recout.x - recout_full_x;
605 recout_skip->height = pipe_ctx->scl_data.recout.y - recout_full_y;
4562236b
HW		 606}
607
b2d0a103 608static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)
4562236b 609{
e12cfcb1 610 const struct dc_surface *surface = pipe_ctx->surface;
4562236b 611 struct core_stream *stream = pipe_ctx->stream;
86006a7f 612 struct rect surf_src = surface->src_rect;
1fbd2cfc
DL		 613 const int in_w = stream->public.src.width;
614 const int in_h = stream->public.src.height;
615 const int out_w = stream->public.dst.width;
616 const int out_h = stream->public.dst.height;
4562236b 617
e12cfcb1
HW		 618 if (pipe_ctx->surface->rotation == ROTATION_ANGLE_90 ||
619 pipe_ctx->surface->rotation == ROTATION_ANGLE_270)
86006a7f
DL		 620 rect_swap_helper(&surf_src);
621
4562236b 622 pipe_ctx->scl_data.ratios.horz = dal_fixed31_32_from_fraction(
86006a7f 623 surf_src.width,
4562236b
HW		 624 surface->dst_rect.width);
625 pipe_ctx->scl_data.ratios.vert = dal_fixed31_32_from_fraction(
86006a7f 626 surf_src.height,
4562236b
HW		 627 surface->dst_rect.height);
628
7f5c22d1 629 if (stream->public.view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
4562236b 630 pipe_ctx->scl_data.ratios.horz.value *= 2;
cdc5e048 631 else if (stream->public.view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
4562236b
HW		 632 pipe_ctx->scl_data.ratios.vert.value *= 2;
633
634 pipe_ctx->scl_data.ratios.vert.value = div64_s64(
635 pipe_ctx->scl_data.ratios.vert.value * in_h, out_h);
636 pipe_ctx->scl_data.ratios.horz.value = div64_s64(
637 pipe_ctx->scl_data.ratios.horz.value * in_w, out_w);
638
639 pipe_ctx->scl_data.ratios.horz_c = pipe_ctx->scl_data.ratios.horz;
640 pipe_ctx->scl_data.ratios.vert_c = pipe_ctx->scl_data.ratios.vert;
641
87449a90
AK		 642 if (pipe_ctx->scl_data.format == PIXEL_FORMAT_420BPP8
643 || pipe_ctx->scl_data.format == PIXEL_FORMAT_420BPP10) {
4562236b
HW		 644 pipe_ctx->scl_data.ratios.horz_c.value /= 2;
645 pipe_ctx->scl_data.ratios.vert_c.value /= 2;
646 }
647}
648
b2d0a103
DL		 649static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct view *recout_skip)
650{
651 struct scaler_data *data = &pipe_ctx->scl_data;
e12cfcb1 652 struct rect src = pipe_ctx->surface->src_rect;
87449a90
AK		 653 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
654 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
b2d0a103 655
86006a7f 656
e12cfcb1
HW		 657 if (pipe_ctx->surface->rotation == ROTATION_ANGLE_90 ||
658 pipe_ctx->surface->rotation == ROTATION_ANGLE_270) {
86006a7f 659 rect_swap_helper(&src);
1fbd2cfc
DL		 660 rect_swap_helper(&data->viewport_c);
661 rect_swap_helper(&data->viewport);
662 }
663
b2d0a103
DL		 664 /*
665 * Init calculated according to formula:
666 * init = (scaling_ratio + number_of_taps + 1) / 2
667 * init_bot = init + scaling_ratio
668 * init_c = init + truncated_vp_c_offset(from calculate viewport)
669 */
670 data->inits.h = dal_fixed31_32_div_int(
671 dal_fixed31_32_add_int(data->ratios.horz, data->taps.h_taps + 1), 2);
672
673 data->inits.h_c = dal_fixed31_32_add(data->inits.h_c, dal_fixed31_32_div_int(
674 dal_fixed31_32_add_int(data->ratios.horz_c, data->taps.h_taps_c + 1), 2));
675
676 data->inits.v = dal_fixed31_32_div_int(
677 dal_fixed31_32_add_int(data->ratios.vert, data->taps.v_taps + 1), 2);
678
679 data->inits.v_c = dal_fixed31_32_add(data->inits.v_c, dal_fixed31_32_div_int(
680 dal_fixed31_32_add_int(data->ratios.vert_c, data->taps.v_taps_c + 1), 2));
681
682
683 /* Adjust for viewport end clip-off */
684 if ((data->viewport.x + data->viewport.width) < (src.x + src.width)) {
685 int vp_clip = src.x + src.width - data->viewport.width - data->viewport.x;
1fbd2cfc
DL		 686 int int_part = dal_fixed31_32_floor(
687 dal_fixed31_32_sub(data->inits.h, data->ratios.horz));
b2d0a103 688
1fbd2cfc 689 int_part = int_part > 0 ? int_part : 0;
b2d0a103
DL		 690 data->viewport.width += int_part < vp_clip ? int_part : vp_clip;
691 }
692 if ((data->viewport.y + data->viewport.height) < (src.y + src.height)) {
693 int vp_clip = src.y + src.height - data->viewport.height - data->viewport.y;
1fbd2cfc
DL		 694 int int_part = dal_fixed31_32_floor(
695 dal_fixed31_32_sub(data->inits.v, data->ratios.vert));
b2d0a103 696
1fbd2cfc 697 int_part = int_part > 0 ? int_part : 0;
b2d0a103
DL		 698 data->viewport.height += int_part < vp_clip ? int_part : vp_clip;
699 }
700 if ((data->viewport_c.x + data->viewport_c.width) < (src.x + src.width) / vpc_div) {
701 int vp_clip = (src.x + src.width) / vpc_div -
702 data->viewport_c.width - data->viewport_c.x;
1fbd2cfc
DL		 703 int int_part = dal_fixed31_32_floor(
704 dal_fixed31_32_sub(data->inits.h_c, data->ratios.horz_c));
b2d0a103 705
1fbd2cfc 706 int_part = int_part > 0 ? int_part : 0;
b2d0a103
DL		 707 data->viewport_c.width += int_part < vp_clip ? int_part : vp_clip;
708 }
709 if ((data->viewport_c.y + data->viewport_c.height) < (src.y + src.height) / vpc_div) {
710 int vp_clip = (src.y + src.height) / vpc_div -
711 data->viewport_c.height - data->viewport_c.y;
1fbd2cfc
DL		 712 int int_part = dal_fixed31_32_floor(
713 dal_fixed31_32_sub(data->inits.v_c, data->ratios.vert_c));
b2d0a103 714
1fbd2cfc 715 int_part = int_part > 0 ? int_part : 0;
b2d0a103
DL		 716 data->viewport_c.height += int_part < vp_clip ? int_part : vp_clip;
717 }
718
719 /* Adjust for non-0 viewport offset */
720 if (data->viewport.x) {
721 int int_part;
722
723 data->inits.h = dal_fixed31_32_add(data->inits.h, dal_fixed31_32_mul_int(
724 data->ratios.horz, recout_skip->width));
725 int_part = dal_fixed31_32_floor(data->inits.h) - data->viewport.x;
726 if (int_part < data->taps.h_taps) {
727 int int_adj = data->viewport.x >= (data->taps.h_taps - int_part) ?
728 (data->taps.h_taps - int_part) : data->viewport.x;
729 data->viewport.x -= int_adj;
730 data->viewport.width += int_adj;
731 int_part += int_adj;
732 } else if (int_part > data->taps.h_taps) {
733 data->viewport.x += int_part - data->taps.h_taps;
734 data->viewport.width -= int_part - data->taps.h_taps;
735 int_part = data->taps.h_taps;
736 }
737 data->inits.h.value &= 0xffffffff;
738 data->inits.h = dal_fixed31_32_add_int(data->inits.h, int_part);
739 }
740
741 if (data->viewport_c.x) {
742 int int_part;
743
744 data->inits.h_c = dal_fixed31_32_add(data->inits.h_c, dal_fixed31_32_mul_int(
745 data->ratios.horz_c, recout_skip->width));
746 int_part = dal_fixed31_32_floor(data->inits.h_c) - data->viewport_c.x;
747 if (int_part < data->taps.h_taps_c) {
748 int int_adj = data->viewport_c.x >= (data->taps.h_taps_c - int_part) ?
749 (data->taps.h_taps_c - int_part) : data->viewport_c.x;
750 data->viewport_c.x -= int_adj;
751 data->viewport_c.width += int_adj;
752 int_part += int_adj;
753 } else if (int_part > data->taps.h_taps_c) {
754 data->viewport_c.x += int_part - data->taps.h_taps_c;
755 data->viewport_c.width -= int_part - data->taps.h_taps_c;
756 int_part = data->taps.h_taps_c;
757 }
758 data->inits.h_c.value &= 0xffffffff;
759 data->inits.h_c = dal_fixed31_32_add_int(data->inits.h_c, int_part);
760 }
761
762 if (data->viewport.y) {
763 int int_part;
764
765 data->inits.v = dal_fixed31_32_add(data->inits.v, dal_fixed31_32_mul_int(
766 data->ratios.vert, recout_skip->height));
767 int_part = dal_fixed31_32_floor(data->inits.v) - data->viewport.y;
768 if (int_part < data->taps.v_taps) {
769 int int_adj = data->viewport.y >= (data->taps.v_taps - int_part) ?
770 (data->taps.v_taps - int_part) : data->viewport.y;
771 data->viewport.y -= int_adj;
772 data->viewport.height += int_adj;
773 int_part += int_adj;
774 } else if (int_part > data->taps.v_taps) {
775 data->viewport.y += int_part - data->taps.v_taps;
776 data->viewport.height -= int_part - data->taps.v_taps;
777 int_part = data->taps.v_taps;
778 }
779 data->inits.v.value &= 0xffffffff;
780 data->inits.v = dal_fixed31_32_add_int(data->inits.v, int_part);
781 }
782
783 if (data->viewport_c.y) {
784 int int_part;
785
786 data->inits.v_c = dal_fixed31_32_add(data->inits.v_c, dal_fixed31_32_mul_int(
787 data->ratios.vert_c, recout_skip->height));
788 int_part = dal_fixed31_32_floor(data->inits.v_c) - data->viewport_c.y;
789 if (int_part < data->taps.v_taps_c) {
790 int int_adj = data->viewport_c.y >= (data->taps.v_taps_c - int_part) ?
791 (data->taps.v_taps_c - int_part) : data->viewport_c.y;
792 data->viewport_c.y -= int_adj;
793 data->viewport_c.height += int_adj;
794 int_part += int_adj;
795 } else if (int_part > data->taps.v_taps_c) {
796 data->viewport_c.y += int_part - data->taps.v_taps_c;
797 data->viewport_c.height -= int_part - data->taps.v_taps_c;
798 int_part = data->taps.v_taps_c;
799 }
800 data->inits.v_c.value &= 0xffffffff;
801 data->inits.v_c = dal_fixed31_32_add_int(data->inits.v_c, int_part);
802 }
803
804 /* Interlaced inits based on final vert inits */
805 data->inits.v_bot = dal_fixed31_32_add(data->inits.v, data->ratios.vert);
806 data->inits.v_c_bot = dal_fixed31_32_add(data->inits.v_c, data->ratios.vert_c);
1fbd2cfc 807
e12cfcb1
HW		 808 if (pipe_ctx->surface->rotation == ROTATION_ANGLE_90 ||
809 pipe_ctx->surface->rotation == ROTATION_ANGLE_270) {
1fbd2cfc
DL		 810 rect_swap_helper(&data->viewport_c);
811 rect_swap_helper(&data->viewport);
812 }
b2d0a103
DL		 813}
814
815bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
4562236b 816{
e12cfcb1 817 const struct dc_surface *surface = pipe_ctx->surface;
4562236b 818 struct dc_crtc_timing *timing = &pipe_ctx->stream->public.timing;
b2d0a103
DL		 819 struct view recout_skip = { 0 };
820 bool res = false;
821
4562236b
HW		 822 /* Important: scaling ratio calculation requires pixel format,
823 * lb depth calculation requires recout and taps require scaling ratios.
b2d0a103 824 * Inits require viewport, taps, ratios and recout of split pipe
4562236b 825 */
b2d0a103 826 pipe_ctx->scl_data.format = convert_pixel_format_to_dalsurface(
e12cfcb1 827 pipe_ctx->surface->format);
b2d0a103
DL		 828
829 calculate_scaling_ratios(pipe_ctx);
4562236b 830
b2d0a103 831 calculate_viewport(pipe_ctx);
4562236b
HW		 832
833 if (pipe_ctx->scl_data.viewport.height < 16 || pipe_ctx->scl_data.viewport.width < 16)
834 return false;
835
b2d0a103 836 calculate_recout(pipe_ctx, &recout_skip);
4562236b
HW		 837
838 /**
839 * Setting line buffer pixel depth to 24bpp yields banding
840 * on certain displays, such as the Sharp 4k
841 */
842 pipe_ctx->scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
843
844 pipe_ctx->scl_data.h_active = timing->h_addressable;
845 pipe_ctx->scl_data.v_active = timing->v_addressable;
846
847 /* Taps calculations */
848 res = pipe_ctx->xfm->funcs->transform_get_optimal_number_of_taps(
849 pipe_ctx->xfm, &pipe_ctx->scl_data, &surface->scaling_quality);
850
851 if (!res) {
852 /* Try 24 bpp linebuffer */
853 pipe_ctx->scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP;
854
855 res = pipe_ctx->xfm->funcs->transform_get_optimal_number_of_taps(
856 pipe_ctx->xfm, &pipe_ctx->scl_data, &surface->scaling_quality);
857 }
858
b2d0a103 859 if (res)
1fbd2cfc 860 /* May need to re-check lb size after this in some obscure scenario */
b2d0a103
DL		 861 calculate_inits_and_adj_vp(pipe_ctx, &recout_skip);
862
4562236b
HW		 863 dm_logger_write(pipe_ctx->stream->ctx->logger, LOG_SCALER,
864 "%s: Viewport:\nheight:%d width:%d x:%d "
865 "y:%d\n dst_rect:\nheight:%d width:%d x:%d "
866 "y:%d\n",
867 __func__,
868 pipe_ctx->scl_data.viewport.height,
869 pipe_ctx->scl_data.viewport.width,
870 pipe_ctx->scl_data.viewport.x,
871 pipe_ctx->scl_data.viewport.y,
872 surface->dst_rect.height,
873 surface->dst_rect.width,
874 surface->dst_rect.x,
875 surface->dst_rect.y);
876
877 return res;
878}
879
880
881enum dc_status resource_build_scaling_params_for_context(
882 const struct core_dc *dc,
883 struct validate_context *context)
884{
885 int i;
886
887 for (i = 0; i < MAX_PIPES; i++) {
888 if (context->res_ctx.pipe_ctx[i].surface != NULL &&
889 context->res_ctx.pipe_ctx[i].stream != NULL)
b2d0a103 890 if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i]))
f84a8161 891 return DC_FAIL_SCALING;
4562236b
HW		 892 }
893
894 return DC_OK;
895}
896
a2b8659d
TC		 897struct pipe_ctx *find_idle_secondary_pipe(
898 struct resource_context *res_ctx,
899 const struct resource_pool *pool)
4562236b
HW		 900{
901 int i;
902 struct pipe_ctx *secondary_pipe = NULL;
903
904 /*
905 * search backwards for the second pipe to keep pipe
906 * assignment more consistent
907 */
908
a2b8659d 909 for (i = pool->pipe_count - 1; i >= 0; i--) {
4562236b
HW		 910 if (res_ctx->pipe_ctx[i].stream == NULL) {
911 secondary_pipe = &res_ctx->pipe_ctx[i];
912 secondary_pipe->pipe_idx = i;
913 break;
914 }
915 }
916
917
918 return secondary_pipe;
919}
920
921struct pipe_ctx *resource_get_head_pipe_for_stream(
922 struct resource_context *res_ctx,
923 const struct core_stream *stream)
924{
925 int i;
a2b8659d 926 for (i = 0; i < MAX_PIPES; i++) {
4562236b 927 if (res_ctx->pipe_ctx[i].stream == stream &&
e73c1efc 928 res_ctx->pipe_ctx[i].stream_enc) {
4562236b
HW		 929 return &res_ctx->pipe_ctx[i];
930 break;
931 }
932 }
933 return NULL;
934}
935
936/*
ab2541b6
AC		 937 * A free_pipe for a stream is defined here as a pipe
938 * that has no surface attached yet
4562236b 939 */
ab2541b6 940static struct pipe_ctx *acquire_free_pipe_for_stream(
745cc746 941 struct validate_context *context,
a2b8659d 942 const struct resource_pool *pool,
ab2541b6 943 const struct dc_stream *dc_stream)
4562236b
HW		 944{
945 int i;
745cc746 946 struct resource_context *res_ctx = &context->res_ctx;
ab2541b6 947 struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream);
4562236b
HW		 948
949 struct pipe_ctx *head_pipe = NULL;
950
951 /* Find head pipe, which has the back end set up*/
952
953 head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
954
955 if (!head_pipe)
956 ASSERT(0);
957
958 if (!head_pipe->surface)
959 return head_pipe;
960
961 /* Re-use pipe already acquired for this stream if available*/
a2b8659d 962 for (i = pool->pipe_count - 1; i >= 0; i--) {
4562236b
HW		 963 if (res_ctx->pipe_ctx[i].stream == stream &&
964 !res_ctx->pipe_ctx[i].surface) {
965 return &res_ctx->pipe_ctx[i];
966 }
967 }
968
969 /*
970 * At this point we have no re-useable pipe for this stream and we need
971 * to acquire an idle one to satisfy the request
972 */
973
a2b8659d 974 if (!pool->funcs->acquire_idle_pipe_for_layer)
4562236b
HW		 975 return NULL;
976
a2b8659d 977 return pool->funcs->acquire_idle_pipe_for_layer(context, pool, stream);
4562236b
HW		 978
979}
980
ab2541b6 981static void release_free_pipes_for_stream(
4562236b 982 struct resource_context *res_ctx,
ab2541b6 983 const struct dc_stream *dc_stream)
4562236b
HW		 984{
985 int i;
ab2541b6 986 struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream);
4562236b 987
a2b8659d 988 for (i = MAX_PIPES - 1; i >= 0; i--) {
05a19c39 989 /* never release the topmost pipe*/
4562236b 990 if (res_ctx->pipe_ctx[i].stream == stream &&
05a19c39 991 res_ctx->pipe_ctx[i].top_pipe &&
4562236b 992 !res_ctx->pipe_ctx[i].surface) {
05a19c39 993 memset(&res_ctx->pipe_ctx[i], 0, sizeof(struct pipe_ctx));
4562236b
HW		 994 }
995 }
996}
997
0f9a536f
DL		 998#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
999static int acquire_first_split_pipe(
1000 struct resource_context *res_ctx,
1001 const struct resource_pool *pool,
1002 struct core_stream *stream)
1003{
1004 int i;
1005
1006 for (i = 0; i < pool->pipe_count; i++) {
1007 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
1008
1009 if (pipe_ctx->top_pipe &&
1010 pipe_ctx->top_pipe->surface == pipe_ctx->surface) {
0f9a536f
DL		 1011 pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;
1012 if (pipe_ctx->bottom_pipe)
1013 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;
1014
1015 memset(pipe_ctx, 0, sizeof(*pipe_ctx));
1016 pipe_ctx->tg = pool->timing_generators[i];
1017 pipe_ctx->mi = pool->mis[i];
1018 pipe_ctx->ipp = pool->ipps[i];
1019 pipe_ctx->xfm = pool->transforms[i];
1020 pipe_ctx->opp = pool->opps[i];
1021 pipe_ctx->dis_clk = pool->display_clock;
f0558542 1022 pipe_ctx->mpcc = pool->mpcc[i];
0f9a536f 1023 pipe_ctx->pipe_idx = i;
0f9a536f
DL		 1024
1025 pipe_ctx->stream = stream;
1026 return i;
1027 }
1028 }
1029 return -1;
1030}
1031#endif
1032
4562236b 1033bool resource_attach_surfaces_to_context(
e12cfcb1 1034 struct dc_surface * const *surfaces,
4562236b 1035 int surface_count,
ab2541b6 1036 const struct dc_stream *dc_stream,
a2b8659d
TC		 1037 struct validate_context *context,
1038 const struct resource_pool *pool)
4562236b
HW		 1039{
1040 int i;
1041 struct pipe_ctx *tail_pipe;
ab2541b6 1042 struct dc_stream_status *stream_status = NULL;
05a19c39 1043 struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream);
4562236b
HW		 1044
1045
1046 if (surface_count > MAX_SURFACE_NUM) {
1047 dm_error("Surface: can not attach %d surfaces! Maximum is: %d\n",
1048 surface_count, MAX_SURFACE_NUM);
1049 return false;
1050 }
1051
ab2541b6
AC		 1052 for (i = 0; i < context->stream_count; i++)
1053 if (&context->streams[i]->public == dc_stream) {
1054 stream_status = &context->stream_status[i];
4562236b
HW		 1055 break;
1056 }
ab2541b6
AC		 1057 if (stream_status == NULL) {
1058 dm_error("Existing stream not found; failed to attach surfaces\n");
4562236b
HW		 1059 return false;
1060 }
1061
1062 /* retain new surfaces */
1063 for (i = 0; i < surface_count; i++)
1064 dc_surface_retain(surfaces[i]);
1065
05a19c39
DL		 1066 /* detach surfaces from pipes */
1067 for (i = 0; i < pool->pipe_count; i++)
1068 if (context->res_ctx.pipe_ctx[i].stream == stream) {
1069 context->res_ctx.pipe_ctx[i].surface = NULL;
1070 context->res_ctx.pipe_ctx[i].bottom_pipe = NULL;
1071 }
4562236b
HW		 1072
1073 /* release existing surfaces*/
ab2541b6
AC		 1074 for (i = 0; i < stream_status->surface_count; i++)
1075 dc_surface_release(stream_status->surfaces[i]);
4562236b 1076
ab2541b6
AC		 1077 for (i = surface_count; i < stream_status->surface_count; i++)
1078 stream_status->surfaces[i] = NULL;
4562236b 1079
4562236b
HW		 1080 tail_pipe = NULL;
1081 for (i = 0; i < surface_count; i++) {
e12cfcb1 1082 struct dc_surface *surface = surfaces[i];
a2b8659d
TC		 1083 struct pipe_ctx *free_pipe = acquire_free_pipe_for_stream(
1084 context, pool, dc_stream);
4562236b 1085
0f9a536f
DL		 1086#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1087 if (!free_pipe) {
1088 int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
1089 if (pipe_idx >= 0)
1090 free_pipe = &context->res_ctx.pipe_ctx[pipe_idx];
1091 }
1092#endif
4562236b 1093 if (!free_pipe) {
ab2541b6 1094 stream_status->surfaces[i] = NULL;
4562236b
HW		 1095 return false;
1096 }
1097
1098 free_pipe->surface = surface;
1099
1100 if (tail_pipe) {
cfe4645e
DL		 1101 free_pipe->tg = tail_pipe->tg;
1102 free_pipe->stream_enc = tail_pipe->stream_enc;
1103 free_pipe->audio = tail_pipe->audio;
1104 free_pipe->clock_source = tail_pipe->clock_source;
4562236b
HW		 1105 free_pipe->top_pipe = tail_pipe;
1106 tail_pipe->bottom_pipe = free_pipe;
1107 }
1108
1109 tail_pipe = free_pipe;
1110 }
1111
ab2541b6 1112 release_free_pipes_for_stream(&context->res_ctx, dc_stream);
4562236b
HW		 1113
1114 /* assign new surfaces*/
1115 for (i = 0; i < surface_count; i++)
ab2541b6 1116 stream_status->surfaces[i] = surfaces[i];
4562236b 1117
ab2541b6 1118 stream_status->surface_count = surface_count;
4562236b
HW		 1119
1120 return true;
1121}
1122
1123
1124static bool is_timing_changed(const struct core_stream *cur_stream,
1125 const struct core_stream *new_stream)
1126{
1127 if (cur_stream == NULL)
1128 return true;
1129
1130 /* If sink pointer changed, it means this is a hotplug, we should do
1131 * full hw setting.
1132 */
1133 if (cur_stream->sink != new_stream->sink)
1134 return true;
1135
1136 /* If output color space is changed, need to reprogram info frames */
1137 if (cur_stream->public.output_color_space !=
1138 new_stream->public.output_color_space)
1139 return true;
1140
1141 return memcmp(
1142 &cur_stream->public.timing,
1143 &new_stream->public.timing,
1144 sizeof(struct dc_crtc_timing)) != 0;
1145}
1146
1147static bool are_stream_backends_same(
1148 const struct core_stream *stream_a, const struct core_stream *stream_b)
1149{
1150 if (stream_a == stream_b)
1151 return true;
1152
1153 if (stream_a == NULL || stream_b == NULL)
1154 return false;
1155
1156 if (is_timing_changed(stream_a, stream_b))
1157 return false;
1158
1159 return true;
1160}
1161
ab2541b6
AC		 1162bool is_stream_unchanged(
1163 const struct core_stream *old_stream, const struct core_stream *stream)
4562236b 1164{
4562236b 1165
ab2541b6
AC		 1166 if (!are_stream_backends_same(old_stream, stream))
1167 return false;
4562236b
HW		 1168
1169 return true;
1170}
1171
1172bool resource_validate_attach_surfaces(
1173 const struct dc_validation_set set[],
1174 int set_count,
1175 const struct validate_context *old_context,
a2b8659d
TC		 1176 struct validate_context *context,
1177 const struct resource_pool *pool)
4562236b
HW		 1178{
1179 int i, j;
1180
1181 for (i = 0; i < set_count; i++) {
430ef426 1182 for (j = 0; old_context && j < old_context->stream_count; j++)
ab2541b6
AC		 1183 if (is_stream_unchanged(
1184 old_context->streams[j],
1185 context->streams[i])) {
4562236b 1186 if (!resource_attach_surfaces_to_context(
ab2541b6
AC		 1187 old_context->stream_status[j].surfaces,
1188 old_context->stream_status[j].surface_count,
1189 &context->streams[i]->public,
a2b8659d 1190 context, pool))
4562236b 1191 return false;
ab2541b6 1192 context->stream_status[i] = old_context->stream_status[j];
4562236b
HW		 1193 }
1194 if (set[i].surface_count != 0)
1195 if (!resource_attach_surfaces_to_context(
1196 set[i].surfaces,
1197 set[i].surface_count,
ab2541b6 1198 &context->streams[i]->public,
a2b8659d 1199 context, pool))
4562236b
HW		 1200 return false;
1201
1202 }
1203
1204 return true;
1205}
1206
1207/* Maximum TMDS single link pixel clock 165MHz */
1208#define TMDS_MAX_PIXEL_CLOCK_IN_KHZ 165000
909e8c9e 1209#define TMDS_MAX_PIXEL_CLOCK_IN_KHZ_UPMOST 297000
4562236b
HW		 1210
1211static void set_stream_engine_in_use(
1212 struct resource_context *res_ctx,
a2b8659d 1213 const struct resource_pool *pool,
4562236b
HW		 1214 struct stream_encoder *stream_enc)
1215{
1216 int i;
1217
a2b8659d
TC		 1218 for (i = 0; i < pool->stream_enc_count; i++) {
1219 if (pool->stream_enc[i] == stream_enc)
4562236b
HW		 1220 res_ctx->is_stream_enc_acquired[i] = true;
1221 }
1222}
1223
1224/* TODO: release audio object */
1225static void set_audio_in_use(
1226 struct resource_context *res_ctx,
a2b8659d 1227 const struct resource_pool *pool,
4562236b
HW		 1228 struct audio *audio)
1229{
1230 int i;
a2b8659d
TC		 1231 for (i = 0; i < pool->audio_count; i++) {
1232 if (pool->audios[i] == audio)
4562236b 1233 res_ctx->is_audio_acquired[i] = true;
4562236b
HW		 1234 }
1235}
1236
1237static int acquire_first_free_pipe(
1238 struct resource_context *res_ctx,
a2b8659d 1239 const struct resource_pool *pool,
4562236b
HW		 1240 struct core_stream *stream)
1241{
1242 int i;
1243
a2b8659d 1244 for (i = 0; i < pool->pipe_count; i++) {
4562236b
HW		 1245 if (!res_ctx->pipe_ctx[i].stream) {
1246 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
1247
f0558542
DL		 1248#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1249 pipe_ctx->mpcc = pool->mpcc[i];
1250#endif
a2b8659d
TC		 1251 pipe_ctx->tg = pool->timing_generators[i];
1252 pipe_ctx->mi = pool->mis[i];
1253 pipe_ctx->ipp = pool->ipps[i];
1254 pipe_ctx->xfm = pool->transforms[i];
1255 pipe_ctx->opp = pool->opps[i];
1256 pipe_ctx->dis_clk = pool->display_clock;
4562236b
HW		 1257 pipe_ctx->pipe_idx = i;
1258
ff5ef992 1259
4562236b
HW		 1260 pipe_ctx->stream = stream;
1261 return i;
1262 }
1263 }
1264 return -1;
1265}
1266
1267static struct stream_encoder *find_first_free_match_stream_enc_for_link(
1268 struct resource_context *res_ctx,
a2b8659d 1269 const struct resource_pool *pool,
4562236b
HW		 1270 struct core_stream *stream)
1271{
1272 int i;
1273 int j = -1;
d0778ebf 1274 struct dc_link *link = stream->sink->link;
4562236b 1275
a2b8659d 1276 for (i = 0; i < pool->stream_enc_count; i++) {
4562236b 1277 if (!res_ctx->is_stream_enc_acquired[i] &&
a2b8659d 1278 pool->stream_enc[i]) {
4562236b
HW		 1279 /* Store first available for MST second display
1280 * in daisy chain use case */
1281 j = i;
a2b8659d 1282 if (pool->stream_enc[i]->id ==
4562236b 1283 link->link_enc->preferred_engine)
a2b8659d 1284 return pool->stream_enc[i];
4562236b
HW		 1285 }
1286 }
1287
1288 /*
1289 * below can happen in cases when stream encoder is acquired:
1290 * 1) for second MST display in chain, so preferred engine already
1291 * acquired;
1292 * 2) for another link, which preferred engine already acquired by any
1293 * MST configuration.
1294 *
1295 * If signal is of DP type and preferred engine not found, return last available
1296 *
1297 * TODO - This is just a patch up and a generic solution is
1298 * required for non DP connectors.
1299 */
1300
1301 if (j >= 0 && dc_is_dp_signal(stream->signal))
a2b8659d 1302 return pool->stream_enc[j];
4562236b
HW		 1303
1304 return NULL;
1305}
1306
a2b8659d
TC		 1307static struct audio *find_first_free_audio(
1308 struct resource_context *res_ctx,
1309 const struct resource_pool *pool)
4562236b
HW		 1310{
1311 int i;
a2b8659d 1312 for (i = 0; i < pool->audio_count; i++) {
4562236b 1313 if (res_ctx->is_audio_acquired[i] == false) {
a2b8659d 1314 return pool->audios[i];
4562236b
HW		 1315 }
1316 }
1317
1318 return 0;
1319}
1320
1321static void update_stream_signal(struct core_stream *stream)
1322{
8b32076c 1323 if (stream->public.output_signal == SIGNAL_TYPE_NONE) {
b3d6c3f0 1324 struct dc_sink *dc_sink = stream->public.sink;
8b32076c
ST		 1325
1326 if (dc_sink->sink_signal == SIGNAL_TYPE_NONE)
d0778ebf 1327 stream->signal = stream->sink->link->connector_signal;
4562236b 1328 else
8b32076c
ST		 1329 stream->signal = dc_sink->sink_signal;
1330 } else {
1331 stream->signal = stream->public.output_signal;
1332 }
1333
56dcade3 1334 if (dc_is_dvi_signal(stream->signal)) {
909e8c9e
CL		 1335 if (stream->public.timing.pix_clk_khz > TMDS_MAX_PIXEL_CLOCK_IN_KHZ_UPMOST &&
1336 stream->public.sink->sink_signal != SIGNAL_TYPE_DVI_SINGLE_LINK)
56dcade3
HW		 1337 stream->signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1338 else
1339 stream->signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1340 }
4562236b
HW		 1341}
1342
1343bool resource_is_stream_unchanged(
ab2541b6 1344 const struct validate_context *old_context, const struct core_stream *stream)
4562236b 1345{
ab2541b6 1346 int i;
4562236b 1347
ab2541b6
AC		 1348 for (i = 0; i < old_context->stream_count; i++) {
1349 const struct core_stream *old_stream = old_context->streams[i];
4562236b 1350
ab2541b6 1351 if (are_stream_backends_same(old_stream, stream))
4562236b 1352 return true;
4562236b
HW		 1353 }
1354
1355 return false;
1356}
1357
1358static void copy_pipe_ctx(
1359 const struct pipe_ctx *from_pipe_ctx, struct pipe_ctx *to_pipe_ctx)
1360{
e12cfcb1 1361 struct dc_surface *surface = to_pipe_ctx->surface;
4562236b
HW		 1362 struct core_stream *stream = to_pipe_ctx->stream;
1363
1364 *to_pipe_ctx = *from_pipe_ctx;
1365 to_pipe_ctx->stream = stream;
1366 if (surface != NULL)
1367 to_pipe_ctx->surface = surface;
1368}
1369
1370static struct core_stream *find_pll_sharable_stream(
1371 const struct core_stream *stream_needs_pll,
1372 struct validate_context *context)
1373{
ab2541b6 1374 int i;
4562236b 1375
ab2541b6
AC		 1376 for (i = 0; i < context->stream_count; i++) {
1377 struct core_stream *stream_has_pll = context->streams[i];
4562236b 1378
ab2541b6
AC		 1379 /* We are looking for non dp, non virtual stream */
1380 if (resource_are_streams_timing_synchronizable(
1381 stream_needs_pll, stream_has_pll)
1382 && !dc_is_dp_signal(stream_has_pll->signal)
d0778ebf 1383 && stream_has_pll->sink->link->connector_signal
ab2541b6
AC		 1384 != SIGNAL_TYPE_VIRTUAL)
1385 return stream_has_pll;
4562236b 1386
4562236b
HW		 1387 }
1388
1389 return NULL;
1390}
1391
1392static int get_norm_pix_clk(const struct dc_crtc_timing *timing)
1393{
1394 uint32_t pix_clk = timing->pix_clk_khz;
1395 uint32_t normalized_pix_clk = pix_clk;
1396
1397 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
1398 pix_clk /= 2;
cc4d99b8
CL		 1399 if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) {
1400 switch (timing->display_color_depth) {
1401 case COLOR_DEPTH_888:
1402 normalized_pix_clk = pix_clk;
1403 break;
1404 case COLOR_DEPTH_101010:
1405 normalized_pix_clk = (pix_clk * 30) / 24;
1406 break;
1407 case COLOR_DEPTH_121212:
1408 normalized_pix_clk = (pix_clk * 36) / 24;
4562236b 1409 break;
cc4d99b8
CL		 1410 case COLOR_DEPTH_161616:
1411 normalized_pix_clk = (pix_clk * 48) / 24;
4562236b 1412 break;
cc4d99b8
CL		 1413 default:
1414 ASSERT(0);
4562236b 1415 break;
cc4d99b8 1416 }
4562236b 1417 }
4562236b
HW		 1418 return normalized_pix_clk;
1419}
1420
9345d987 1421static void calculate_phy_pix_clks(struct core_stream *stream)
4562236b 1422{
9345d987
AG		 1423 update_stream_signal(stream);
1424
1425 /* update actual pixel clock on all streams */
1426 if (dc_is_hdmi_signal(stream->signal))
1427 stream->phy_pix_clk = get_norm_pix_clk(
1428 &stream->public.timing);
1429 else
1430 stream->phy_pix_clk =
1431 stream->public.timing.pix_clk_khz;
4562236b
HW		 1432}
1433
1434enum dc_status resource_map_pool_resources(
1435 const struct core_dc *dc,
430ef426
DL		 1436 struct validate_context *context,
1437 struct validate_context *old_context)
4562236b 1438{
a2b8659d 1439 const struct resource_pool *pool = dc->res_pool;
ab2541b6 1440 int i, j;
4562236b 1441
430ef426 1442 for (i = 0; old_context && i < context->stream_count; i++) {
ab2541b6 1443 struct core_stream *stream = context->streams[i];
4562236b 1444
430ef426
DL		 1445 if (!resource_is_stream_unchanged(old_context, stream)) {
1446 if (stream != NULL && old_context->streams[i] != NULL) {
4b679bc3 1447 stream->bit_depth_params =
430ef426
DL		 1448 old_context->streams[i]->bit_depth_params;
1449 stream->clamping = old_context->streams[i]->clamping;
a2b8659d
TC		 1450 continue;
1451 }
4b679bc3 1452 }
7e2fe319 1453
ab2541b6 1454 /* mark resources used for stream that is already active */
a2b8659d 1455 for (j = 0; j < pool->pipe_count; j++) {
ab2541b6
AC		 1456 struct pipe_ctx *pipe_ctx =
1457 &context->res_ctx.pipe_ctx[j];
1458 const struct pipe_ctx *old_pipe_ctx =
430ef426 1459 &old_context->res_ctx.pipe_ctx[j];
4562236b 1460
ab2541b6
AC		 1461 if (!are_stream_backends_same(old_pipe_ctx->stream, stream))
1462 continue;
8c737fcc 1463
268cadbd
YS		 1464 if (old_pipe_ctx->top_pipe)
1465 continue;
1466
ab2541b6
AC		 1467 pipe_ctx->stream = stream;
1468 copy_pipe_ctx(old_pipe_ctx, pipe_ctx);
4562236b 1469
ab2541b6
AC		 1470 /* Split pipe resource, do not acquire back end */
1471 if (!pipe_ctx->stream_enc)
1472 continue;
4562236b 1473
ab2541b6 1474 set_stream_engine_in_use(
a2b8659d 1475 &context->res_ctx, pool,
ab2541b6
AC		 1476 pipe_ctx->stream_enc);
1477
1478 /* Switch to dp clock source only if there is
1479 * no non dp stream that shares the same timing
1480 * with the dp stream.
1481 */
1482 if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
1483 !find_pll_sharable_stream(stream, context))
a2b8659d 1484 pipe_ctx->clock_source = pool->dp_clock_source;
ab2541b6
AC		 1485
1486 resource_reference_clock_source(
a2b8659d 1487 &context->res_ctx, pool,
ab2541b6
AC		 1488 pipe_ctx->clock_source);
1489
a2b8659d
TC		 1490 set_audio_in_use(&context->res_ctx, pool,
1491 pipe_ctx->audio);
4562236b
HW		 1492 }
1493 }
1494
ab2541b6
AC		 1495 for (i = 0; i < context->stream_count; i++) {
1496 struct core_stream *stream = context->streams[i];
1497 struct pipe_ctx *pipe_ctx = NULL;
1498 int pipe_idx = -1;
4562236b 1499
430ef426 1500 if (old_context && resource_is_stream_unchanged(old_context, stream))
ab2541b6
AC		 1501 continue;
1502 /* acquire new resources */
5d11e9fc
DL		 1503 pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream);
1504#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1505 if (pipe_idx < 0)
1506 acquire_first_split_pipe(&context->res_ctx, pool, stream);
1507#endif
ab2541b6
AC		 1508 if (pipe_idx < 0)
1509 return DC_NO_CONTROLLER_RESOURCE;
1510
ab2541b6
AC		 1511 pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
1512
1513 pipe_ctx->stream_enc =
1514 find_first_free_match_stream_enc_for_link(
a2b8659d 1515 &context->res_ctx, pool, stream);
ab2541b6
AC		 1516
1517 if (!pipe_ctx->stream_enc)
1518 return DC_NO_STREAM_ENG_RESOURCE;
1519
1520 set_stream_engine_in_use(
a2b8659d 1521 &context->res_ctx, pool,
ab2541b6
AC		 1522 pipe_ctx->stream_enc);
1523
1524 /* TODO: Add check if ASIC support and EDID audio */
b73a22d3 1525 if (!stream->sink->converter_disable_audio &&
ab2541b6
AC		 1526 dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&
1527 stream->public.audio_info.mode_count) {
1528 pipe_ctx->audio = find_first_free_audio(
a2b8659d 1529 &context->res_ctx, pool);
ab2541b6
AC		 1530
1531 /*
1532 * Audio assigned in order first come first get.
1533 * There are asics which has number of audio
1534 * resources less then number of pipes
1535 */
1536 if (pipe_ctx->audio)
1537 set_audio_in_use(
a2b8659d 1538 &context->res_ctx, pool,
ab2541b6 1539 pipe_ctx->audio);
4562236b 1540 }
ab2541b6
AC		 1541
1542 context->stream_status[i].primary_otg_inst = pipe_ctx->tg->inst;
4562236b
HW		 1543 }
1544
1545 return DC_OK;
1546}
1547
ab2541b6
AC		 1548/* first stream in the context is used to populate the rest */
1549void validate_guaranteed_copy_streams(
4562236b 1550 struct validate_context *context,
ab2541b6 1551 int max_streams)
4562236b
HW		 1552{
1553 int i;
1554
ab2541b6
AC		 1555 for (i = 1; i < max_streams; i++) {
1556 context->streams[i] = context->streams[0];
4562236b
HW		 1557
1558 copy_pipe_ctx(&context->res_ctx.pipe_ctx[0],
1559 &context->res_ctx.pipe_ctx[i]);
1560 context->res_ctx.pipe_ctx[i].stream =
1561 context->res_ctx.pipe_ctx[0].stream;
1562
ab2541b6
AC		 1563 dc_stream_retain(&context->streams[i]->public);
1564 context->stream_count++;
4562236b
HW		 1565 }
1566}
1567
6e4d6bee
TC		 1568static void patch_gamut_packet_checksum(
1569 struct encoder_info_packet *gamut_packet)
4562236b 1570{
4562236b 1571 /* For gamut we recalc checksum */
6e4d6bee 1572 if (gamut_packet->valid) {
4562236b
HW		 1573 uint8_t chk_sum = 0;
1574 uint8_t *ptr;
1575 uint8_t i;
1576
4562236b 1577 /*start of the Gamut data. */
6e4d6bee 1578 ptr = &gamut_packet->sb[3];
4562236b 1579
6e4d6bee 1580 for (i = 0; i <= gamut_packet->sb[1]; i++)
4562236b
HW		 1581 chk_sum += ptr[i];
1582
6e4d6bee 1583 gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum);
1646a6fe 1584 }
4562236b
HW		 1585}
1586
1587static void set_avi_info_frame(
6e4d6bee 1588 struct encoder_info_packet *info_packet,
4562236b
HW		 1589 struct pipe_ctx *pipe_ctx)
1590{
1591 struct core_stream *stream = pipe_ctx->stream;
1592 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
1593 struct info_frame info_frame = { {0} };
1594 uint32_t pixel_encoding = 0;
1595 enum scanning_type scan_type = SCANNING_TYPE_NODATA;
1596 enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA;
1597 bool itc = false;
50e27654 1598 uint8_t itc_value = 0;
4562236b 1599 uint8_t cn0_cn1 = 0;
50e27654 1600 unsigned int cn0_cn1_value = 0;
4562236b
HW		 1601 uint8_t *check_sum = NULL;
1602 uint8_t byte_index = 0;
e8d726b7 1603 union hdmi_info_packet *hdmi_info = &info_frame.avi_info_packet.info_packet_hdmi;
50e27654 1604 union display_content_support support = {0};
15e17335
CL		 1605 unsigned int vic = pipe_ctx->stream->public.timing.vic;
1606 enum dc_timing_3d_format format;
4562236b 1607
4562236b 1608 color_space = pipe_ctx->stream->public.output_color_space;
e5f2038e
CL		 1609 if (color_space == COLOR_SPACE_UNKNOWN)
1610 color_space = (stream->public.timing.pixel_encoding == PIXEL_ENCODING_RGB)?
1611 COLOR_SPACE_SRGB:COLOR_SPACE_YCBCR709;
4562236b
HW		 1612
1613 /* Initialize header */
e8d726b7 1614 hdmi_info->bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI;
4562236b
HW		 1615 /* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall
1616 * not be used in HDMI 2.0 (Section 10.1) */
e8d726b7
RA		 1617 hdmi_info->bits.header.version = 2;
1618 hdmi_info->bits.header.length = HDMI_AVI_INFOFRAME_SIZE;
4562236b
HW		 1619
1620 /*
1621 * IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built
1622 * according to HDMI 2.0 spec (Section 10.1)
1623 */
1624
1625 switch (stream->public.timing.pixel_encoding) {
1626 case PIXEL_ENCODING_YCBCR422:
1627 pixel_encoding = 1;
1628 break;
1629
1630 case PIXEL_ENCODING_YCBCR444:
1631 pixel_encoding = 2;
1632 break;
1633 case PIXEL_ENCODING_YCBCR420:
1634 pixel_encoding = 3;
1635 break;
1636
1637 case PIXEL_ENCODING_RGB:
1638 default:
1639 pixel_encoding = 0;
1640 }
1641
1642 /* Y0_Y1_Y2 : The pixel encoding */
1643 /* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */
e8d726b7 1644 hdmi_info->bits.Y0_Y1_Y2 = pixel_encoding;
4562236b
HW		 1645
1646 /* A0 = 1 Active Format Information valid */
e8d726b7 1647 hdmi_info->bits.A0 = ACTIVE_FORMAT_VALID;
4562236b
HW		 1648
1649 /* B0, B1 = 3; Bar info data is valid */
e8d726b7 1650 hdmi_info->bits.B0_B1 = BAR_INFO_BOTH_VALID;
4562236b 1651
e8d726b7 1652 hdmi_info->bits.SC0_SC1 = PICTURE_SCALING_UNIFORM;
4562236b
HW		 1653
1654 /* S0, S1 : Underscan / Overscan */
1655 /* TODO: un-hardcode scan type */
1656 scan_type = SCANNING_TYPE_UNDERSCAN;
e8d726b7 1657 hdmi_info->bits.S0_S1 = scan_type;
4562236b
HW		 1658
1659 /* C0, C1 : Colorimetry */
8fde5884 1660 if (color_space == COLOR_SPACE_YCBCR709 ||
15e17335 1661 color_space == COLOR_SPACE_YCBCR709_LIMITED)
e8d726b7 1662 hdmi_info->bits.C0_C1 = COLORIMETRY_ITU709;
8fde5884
CL		 1663 else if (color_space == COLOR_SPACE_YCBCR601 ||
1664 color_space == COLOR_SPACE_YCBCR601_LIMITED)
e8d726b7 1665 hdmi_info->bits.C0_C1 = COLORIMETRY_ITU601;
8fde5884
CL		 1666 else {
1667 if (stream->public.timing.pixel_encoding != PIXEL_ENCODING_RGB)
1668 BREAK_TO_DEBUGGER();
e8d726b7 1669 hdmi_info->bits.C0_C1 = COLORIMETRY_NO_DATA;
8fde5884 1670 }
534db198 1671 if (color_space == COLOR_SPACE_2020_RGB_FULLRANGE ||
8fde5884
CL		 1672 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE ||
1673 color_space == COLOR_SPACE_2020_YCBCR) {
e8d726b7
RA		 1674 hdmi_info->bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR;
1675 hdmi_info->bits.C0_C1 = COLORIMETRY_EXTENDED;
534db198 1676 } else if (color_space == COLOR_SPACE_ADOBERGB) {
e8d726b7
RA		 1677 hdmi_info->bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB;
1678 hdmi_info->bits.C0_C1 = COLORIMETRY_EXTENDED;
534db198
AZ		 1679 }
1680
4562236b
HW		 1681 /* TODO: un-hardcode aspect ratio */
1682 aspect = stream->public.timing.aspect_ratio;
1683
1684 switch (aspect) {
1685 case ASPECT_RATIO_4_3:
1686 case ASPECT_RATIO_16_9:
e8d726b7 1687 hdmi_info->bits.M0_M1 = aspect;
4562236b
HW		 1688 break;
1689
1690 case ASPECT_RATIO_NO_DATA:
1691 case ASPECT_RATIO_64_27:
1692 case ASPECT_RATIO_256_135:
1693 default:
e8d726b7 1694 hdmi_info->bits.M0_M1 = 0;
4562236b
HW		 1695 }
1696
1697 /* Active Format Aspect ratio - same as Picture Aspect Ratio. */
e8d726b7 1698 hdmi_info->bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE;
4562236b
HW		 1699
1700 /* TODO: un-hardcode cn0_cn1 and itc */
50e27654 1701
4562236b 1702 cn0_cn1 = 0;
50e27654
ZF		 1703 cn0_cn1_value = 0;
1704
1705 itc = true;
1706 itc_value = 1;
1707
1708 support = stream->public.sink->edid_caps.content_support;
4562236b
HW		 1709
1710 if (itc) {
50e27654
ZF		 1711 if (!support.bits.valid_content_type) {
1712 cn0_cn1_value = 0;
1713 } else {
1714 if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GRAPHICS) {
1715 if (support.bits.graphics_content == 1) {
1716 cn0_cn1_value = 0;
1717 }
1718 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_PHOTO) {
1719 if (support.bits.photo_content == 1) {
1720 cn0_cn1_value = 1;
1721 } else {
1722 cn0_cn1_value = 0;
1723 itc_value = 0;
1724 }
1725 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_CINEMA) {
1726 if (support.bits.cinema_content == 1) {
1727 cn0_cn1_value = 2;
1728 } else {
1729 cn0_cn1_value = 0;
1730 itc_value = 0;
1731 }
1732 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GAME) {
1733 if (support.bits.game_content == 1) {
1734 cn0_cn1_value = 3;
1735 } else {
1736 cn0_cn1_value = 0;
1737 itc_value = 0;
1738 }
1739 }
1740 }
1741 hdmi_info->bits.CN0_CN1 = cn0_cn1_value;
1742 hdmi_info->bits.ITC = itc_value;
4562236b
HW		 1743 }
1744
1745 /* TODO : We should handle YCC quantization */
1746 /* but we do not have matrix calculation */
50e27654
ZF		 1747 if (stream->public.sink->edid_caps.qs_bit == 1 &&
1748 stream->public.sink->edid_caps.qy_bit == 1) {
1749 if (color_space == COLOR_SPACE_SRGB ||
1750 color_space == COLOR_SPACE_2020_RGB_FULLRANGE) {
1751 hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_FULL_RANGE;
1752 hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_FULL_RANGE;
1753 } else if (color_space == COLOR_SPACE_SRGB_LIMITED ||
1754 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE) {
1755 hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_LIMITED_RANGE;
1756 hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
1757 } else {
1758 hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
1759 hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
1760 }
4562236b 1761 } else {
e8d726b7 1762 hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
50e27654 1763 hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
4562236b 1764 }
50e27654 1765
15e17335
CL		 1766 ///VIC
1767 format = stream->public.timing.timing_3d_format;
1768 /*todo, add 3DStereo support*/
1769 if (format != TIMING_3D_FORMAT_NONE) {
1770 // Based on HDMI specs hdmi vic needs to be converted to cea vic when 3D is enabled
1771 switch (pipe_ctx->stream->public.timing.hdmi_vic) {
1772 case 1:
1773 vic = 95;
1774 break;
1775 case 2:
1776 vic = 94;
1777 break;
1778 case 3:
1779 vic = 93;
1780 break;
1781 case 4:
1782 vic = 98;
1783 break;
1784 default:
1785 break;
1786 }
1787 }
1788 hdmi_info->bits.VIC0_VIC7 = vic;
4562236b
HW		 1789
1790 /* pixel repetition
1791 * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel
1792 * repetition start from 1 */
e8d726b7 1793 hdmi_info->bits.PR0_PR3 = 0;
4562236b
HW		 1794
1795 /* Bar Info
1796 * barTop: Line Number of End of Top Bar.
1797 * barBottom: Line Number of Start of Bottom Bar.
1798 * barLeft: Pixel Number of End of Left Bar.
1799 * barRight: Pixel Number of Start of Right Bar. */
e8d726b7 1800 hdmi_info->bits.bar_top = stream->public.timing.v_border_top;
15e17335 1801 hdmi_info->bits.bar_bottom = (stream->public.timing.v_total
4562236b 1802 - stream->public.timing.v_border_bottom + 1);
e8d726b7
RA		 1803 hdmi_info->bits.bar_left = stream->public.timing.h_border_left;
1804 hdmi_info->bits.bar_right = (stream->public.timing.h_total
4562236b
HW		 1805 - stream->public.timing.h_border_right + 1);
1806
1807 /* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */
e8d726b7
RA		 1808 check_sum = &info_frame.avi_info_packet.info_packet_hdmi.packet_raw_data.sb[0];
1809
3e183c5f 1810 *check_sum = HDMI_INFOFRAME_TYPE_AVI + HDMI_AVI_INFOFRAME_SIZE + 2;
4562236b 1811
3e183c5f 1812 for (byte_index = 1; byte_index <= HDMI_AVI_INFOFRAME_SIZE; byte_index++)
e8d726b7 1813 *check_sum += hdmi_info->packet_raw_data.sb[byte_index];
4562236b
HW		 1814
1815 /* one byte complement */
1816 *check_sum = (uint8_t) (0x100 - *check_sum);
1817
1818 /* Store in hw_path_mode */
e8d726b7
RA		 1819 info_packet->hb0 = hdmi_info->packet_raw_data.hb0;
1820 info_packet->hb1 = hdmi_info->packet_raw_data.hb1;
1821 info_packet->hb2 = hdmi_info->packet_raw_data.hb2;
4562236b 1822
e66e4d64
HW		 1823 for (byte_index = 0; byte_index < sizeof(info_frame.avi_info_packet.
1824 info_packet_hdmi.packet_raw_data.sb); byte_index++)
4562236b 1825 info_packet->sb[byte_index] = info_frame.avi_info_packet.
e66e4d64 1826 info_packet_hdmi.packet_raw_data.sb[byte_index];
4562236b
HW		 1827
1828 info_packet->valid = true;
1829}
1830
6e4d6bee
TC		 1831static void set_vendor_info_packet(
1832 struct encoder_info_packet *info_packet,
1833 struct core_stream *stream)
4562236b
HW		 1834{
1835 uint32_t length = 0;
1836 bool hdmi_vic_mode = false;
1837 uint8_t checksum = 0;
1838 uint32_t i = 0;
1839 enum dc_timing_3d_format format;
15e17335
CL		 1840 // Can be different depending on packet content /*todo*/
1841 // unsigned int length = pPathMode->dolbyVision ? 24 : 5;
1842
1843 info_packet->valid = false;
4562236b 1844
4562236b 1845 format = stream->public.timing.timing_3d_format;
7f5c22d1
VP		 1846 if (stream->public.view_format == VIEW_3D_FORMAT_NONE)
1847 format = TIMING_3D_FORMAT_NONE;
4562236b
HW		 1848
1849 /* Can be different depending on packet content */
1850 length = 5;
1851
1852 if (stream->public.timing.hdmi_vic != 0
1853 && stream->public.timing.h_total >= 3840
1854 && stream->public.timing.v_total >= 2160)
1855 hdmi_vic_mode = true;
1856
1857 /* According to HDMI 1.4a CTS, VSIF should be sent
1858 * for both 3D stereo and HDMI VIC modes.
1859 * For all other modes, there is no VSIF sent. */
1860
1861 if (format == TIMING_3D_FORMAT_NONE && !hdmi_vic_mode)
1862 return;
1863
1864 /* 24bit IEEE Registration identifier (0x000c03). LSB first. */
1865 info_packet->sb[1] = 0x03;
1866 info_packet->sb[2] = 0x0C;
1867 info_packet->sb[3] = 0x00;
1868
1869 /*PB4: 5 lower bytes = 0 (reserved). 3 higher bits = HDMI_Video_Format.
1870 * The value for HDMI_Video_Format are:
1871 * 0x0 (0b000) - No additional HDMI video format is presented in this
1872 * packet
1873 * 0x1 (0b001) - Extended resolution format present. 1 byte of HDMI_VIC
1874 * parameter follows
1875 * 0x2 (0b010) - 3D format indication present. 3D_Structure and
1876 * potentially 3D_Ext_Data follows
1877 * 0x3..0x7 (0b011..0b111) - reserved for future use */
1878 if (format != TIMING_3D_FORMAT_NONE)
1879 info_packet->sb[4] = (2 << 5);
1880 else if (hdmi_vic_mode)
1881 info_packet->sb[4] = (1 << 5);
1882
1883 /* PB5: If PB4 claims 3D timing (HDMI_Video_Format = 0x2):
1884 * 4 lower bites = 0 (reserved). 4 higher bits = 3D_Structure.
1885 * The value for 3D_Structure are:
1886 * 0x0 - Frame Packing
1887 * 0x1 - Field Alternative
1888 * 0x2 - Line Alternative
1889 * 0x3 - Side-by-Side (full)
1890 * 0x4 - L + depth
1891 * 0x5 - L + depth + graphics + graphics-depth
1892 * 0x6 - Top-and-Bottom
1893 * 0x7 - Reserved for future use
1894 * 0x8 - Side-by-Side (Half)
1895 * 0x9..0xE - Reserved for future use
1896 * 0xF - Not used */
1897 switch (format) {
1898 case TIMING_3D_FORMAT_HW_FRAME_PACKING:
1899 case TIMING_3D_FORMAT_SW_FRAME_PACKING:
1900 info_packet->sb[5] = (0x0 << 4);
1901 break;
1902
1903 case TIMING_3D_FORMAT_SIDE_BY_SIDE:
1904 case TIMING_3D_FORMAT_SBS_SW_PACKED:
1905 info_packet->sb[5] = (0x8 << 4);
1906 length = 6;
1907 break;
1908
1909 case TIMING_3D_FORMAT_TOP_AND_BOTTOM:
1910 case TIMING_3D_FORMAT_TB_SW_PACKED:
1911 info_packet->sb[5] = (0x6 << 4);
1912 break;
1913
1914 default:
1915 break;
1916 }
1917
1918 /*PB5: If PB4 is set to 0x1 (extended resolution format)
1919 * fill PB5 with the correct HDMI VIC code */
1920 if (hdmi_vic_mode)
1921 info_packet->sb[5] = stream->public.timing.hdmi_vic;
1922
1923 /* Header */
3e183c5f 1924 info_packet->hb0 = HDMI_INFOFRAME_TYPE_VENDOR; /* VSIF packet type. */
4562236b
HW		 1925 info_packet->hb1 = 0x01; /* Version */
1926
1927 /* 4 lower bits = Length, 4 higher bits = 0 (reserved) */
1928 info_packet->hb2 = (uint8_t) (length);
1929
1930 /* Calculate checksum */
1931 checksum = 0;
1932 checksum += info_packet->hb0;
1933 checksum += info_packet->hb1;
1934 checksum += info_packet->hb2;
1935
1936 for (i = 1; i <= length; i++)
1937 checksum += info_packet->sb[i];
1938
1939 info_packet->sb[0] = (uint8_t) (0x100 - checksum);
1940
1941 info_packet->valid = true;
1942}
1943
6e4d6bee
TC		 1944static void set_spd_info_packet(
1945 struct encoder_info_packet *info_packet,
1946 struct core_stream *stream)
4562236b
HW		 1947{
1948 /* SPD info packet for FreeSync */
1949
1950 unsigned char checksum = 0;
1951 unsigned int idx, payload_size = 0;
1952
1953 /* Check if Freesync is supported. Return if false. If true,
1954 * set the corresponding bit in the info packet
1955 */
1956 if (stream->public.freesync_ctx.supported == false)
1957 return;
1958
1959 if (dc_is_hdmi_signal(stream->signal)) {
1960
1961 /* HEADER */
1962
1963 /* HB0 = Packet Type = 0x83 (Source Product
1964 * Descriptor InfoFrame)
1965 */
3e183c5f 1966 info_packet->hb0 = HDMI_INFOFRAME_TYPE_SPD;
4562236b
HW		 1967
1968 /* HB1 = Version = 0x01 */
1969 info_packet->hb1 = 0x01;
1970
1971 /* HB2 = [Bits 7:5 = 0] [Bits 4:0 = Length = 0x08] */
1972 info_packet->hb2 = 0x08;
1973
1974 payload_size = 0x08;
1975
1976 } else if (dc_is_dp_signal(stream->signal)) {
1977
1978 /* HEADER */
1979
1980 /* HB0 = Secondary-data Packet ID = 0 - Only non-zero
1981 * when used to associate audio related info packets
1982 */
1983 info_packet->hb0 = 0x00;
1984
1985 /* HB1 = Packet Type = 0x83 (Source Product
1986 * Descriptor InfoFrame)
1987 */
3e183c5f 1988 info_packet->hb1 = HDMI_INFOFRAME_TYPE_SPD;
4562236b
HW		 1989
1990 /* HB2 = [Bits 7:0 = Least significant eight bits -
1991 * For INFOFRAME, the value must be 1Bh]
1992 */
1993 info_packet->hb2 = 0x1B;
1994
1995 /* HB3 = [Bits 7:2 = INFOFRAME SDP Version Number = 0x1]
1996 * [Bits 1:0 = Most significant two bits = 0x00]
1997 */
1998 info_packet->hb3 = 0x04;
1999
2000 payload_size = 0x1B;
2001 }
2002
2003 /* PB1 = 0x1A (24bit AMD IEEE OUI (0x00001A) - Byte 0) */
2004 info_packet->sb[1] = 0x1A;
2005
2006 /* PB2 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 1) */
2007 info_packet->sb[2] = 0x00;
2008
2009 /* PB3 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 2) */
2010 info_packet->sb[3] = 0x00;
2011
2012 /* PB4 = Reserved */
2013 info_packet->sb[4] = 0x00;
2014
2015 /* PB5 = Reserved */
2016 info_packet->sb[5] = 0x00;
2017
2018 /* PB6 = [Bits 7:3 = Reserved] */
2019 info_packet->sb[6] = 0x00;
2020
2021 if (stream->public.freesync_ctx.supported == true)
2022 /* PB6 = [Bit 0 = FreeSync Supported] */
2023 info_packet->sb[6] |= 0x01;
2024
2025 if (stream->public.freesync_ctx.enabled == true)
2026 /* PB6 = [Bit 1 = FreeSync Enabled] */
2027 info_packet->sb[6] |= 0x02;
2028
2029 if (stream->public.freesync_ctx.active == true)
2030 /* PB6 = [Bit 2 = FreeSync Active] */
2031 info_packet->sb[6] |= 0x04;
2032
2033 /* PB7 = FreeSync Minimum refresh rate (Hz) */
2034 info_packet->sb[7] = (unsigned char) (stream->public.freesync_ctx.
2035 min_refresh_in_micro_hz / 1000000);
2036
2037 /* PB8 = FreeSync Maximum refresh rate (Hz)
2038 *
2039 * Note: We do not use the maximum capable refresh rate
2040 * of the panel, because we should never go above the field
2041 * rate of the mode timing set.
2042 */
2043 info_packet->sb[8] = (unsigned char) (stream->public.freesync_ctx.
2044 nominal_refresh_in_micro_hz / 1000000);
2045
2046 /* PB9 - PB27 = Reserved */
2047 for (idx = 9; idx <= 27; idx++)
2048 info_packet->sb[idx] = 0x00;
2049
2050 /* Calculate checksum */
2051 checksum += info_packet->hb0;
2052 checksum += info_packet->hb1;
2053 checksum += info_packet->hb2;
2054 checksum += info_packet->hb3;
2055
2056 for (idx = 1; idx <= payload_size; idx++)
2057 checksum += info_packet->sb[idx];
2058
2059 /* PB0 = Checksum (one byte complement) */
2060 info_packet->sb[0] = (unsigned char) (0x100 - checksum);
2061
2062 info_packet->valid = true;
2063}
2064
1646a6fe 2065static void set_hdr_static_info_packet(
6e4d6bee 2066 struct encoder_info_packet *info_packet,
e12cfcb1 2067 struct dc_surface *surface,
6e4d6bee 2068 struct core_stream *stream)
1646a6fe 2069{
e5cf325b 2070 uint16_t i = 0;
1646a6fe 2071 enum signal_type signal = stream->signal;
e5cf325b
HW		 2072 struct dc_hdr_static_metadata hdr_metadata;
2073 uint32_t data;
1646a6fe
AW		 2074
2075 if (!surface)
2076 return;
2077
e12cfcb1 2078 hdr_metadata = surface->hdr_static_ctx;
1646a6fe 2079
70063a59 2080 if (!hdr_metadata.hdr_supported)
10bff005
YS		 2081 return;
2082
1646a6fe
AW		 2083 if (dc_is_hdmi_signal(signal)) {
2084 info_packet->valid = true;
2085
2086 info_packet->hb0 = 0x87;
2087 info_packet->hb1 = 0x01;
2088 info_packet->hb2 = 0x1A;
2089 i = 1;
2090 } else if (dc_is_dp_signal(signal)) {
2091 info_packet->valid = true;
2092
2093 info_packet->hb0 = 0x00;
2094 info_packet->hb1 = 0x87;
2095 info_packet->hb2 = 0x1D;
2096 info_packet->hb3 = (0x13 << 2);
2097 i = 2;
2098 }
2099
1646a6fe
AW		 2100 data = hdr_metadata.is_hdr;
2101 info_packet->sb[i++] = data ? 0x02 : 0x00;
2102 info_packet->sb[i++] = 0x00;
2103
2104 data = hdr_metadata.chromaticity_green_x / 2;
2105 info_packet->sb[i++] = data & 0xFF;
2106 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2107
2108 data = hdr_metadata.chromaticity_green_y / 2;
2109 info_packet->sb[i++] = data & 0xFF;
2110 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2111
2112 data = hdr_metadata.chromaticity_blue_x / 2;
2113 info_packet->sb[i++] = data & 0xFF;
2114 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2115
2116 data = hdr_metadata.chromaticity_blue_y / 2;
2117 info_packet->sb[i++] = data & 0xFF;
2118 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2119
2120 data = hdr_metadata.chromaticity_red_x / 2;
2121 info_packet->sb[i++] = data & 0xFF;
2122 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2123
2124 data = hdr_metadata.chromaticity_red_y / 2;
2125 info_packet->sb[i++] = data & 0xFF;
2126 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2127
2128 data = hdr_metadata.chromaticity_white_point_x / 2;
2129 info_packet->sb[i++] = data & 0xFF;
2130 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2131
2132 data = hdr_metadata.chromaticity_white_point_y / 2;
2133 info_packet->sb[i++] = data & 0xFF;
2134 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2135
2136 data = hdr_metadata.max_luminance;
2137 info_packet->sb[i++] = data & 0xFF;
2138 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2139
2140 data = hdr_metadata.min_luminance;
2141 info_packet->sb[i++] = data & 0xFF;
2142 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2143
2144 data = hdr_metadata.maximum_content_light_level;
2145 info_packet->sb[i++] = data & 0xFF;
2146 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2147
2148 data = hdr_metadata.maximum_frame_average_light_level;
2149 info_packet->sb[i++] = data & 0xFF;
2150 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2151
2152 if (dc_is_hdmi_signal(signal)) {
2153 uint32_t checksum = 0;
2154
2155 checksum += info_packet->hb0;
2156 checksum += info_packet->hb1;
2157 checksum += info_packet->hb2;
2158
2159 for (i = 1; i <= info_packet->hb2; i++)
2160 checksum += info_packet->sb[i];
2161
2162 info_packet->sb[0] = 0x100 - checksum;
2163 } else if (dc_is_dp_signal(signal)) {
2164 info_packet->sb[0] = 0x01;
2165 info_packet->sb[1] = 0x1A;
2166 }
2167}
2168
6e4d6bee
TC		 2169static void set_vsc_info_packet(
2170 struct encoder_info_packet *info_packet,
2171 struct core_stream *stream)
4562236b
HW		 2172{
2173 unsigned int vscPacketRevision = 0;
2174 unsigned int i;
2175
94267b3d 2176 if (stream->sink->link->psr_enabled) {
4562236b
HW		 2177 vscPacketRevision = 2;
2178 }
2179
2180 /* VSC packet not needed based on the features
2181 * supported by this DP display
2182 */
2183 if (vscPacketRevision == 0)
2184 return;
2185
2186 if (vscPacketRevision == 0x2) {
2187 /* Secondary-data Packet ID = 0*/
2188 info_packet->hb0 = 0x00;
2189 /* 07h - Packet Type Value indicating Video
2190 * Stream Configuration packet
2191 */
2192 info_packet->hb1 = 0x07;
2193 /* 02h = VSC SDP supporting 3D stereo and PSR
2194 * (applies to eDP v1.3 or higher).
2195 */
2196 info_packet->hb2 = 0x02;
2197 /* 08h = VSC packet supporting 3D stereo + PSR
2198 * (HB2 = 02h).
2199 */
2200 info_packet->hb3 = 0x08;
2201
2202 for (i = 0; i < 28; i++)
2203 info_packet->sb[i] = 0;
2204
2205 info_packet->valid = true;
2206 }
2207
2208 /*TODO: stereo 3D support and extend pixel encoding colorimetry*/
2209}
2210
8122a253 2211void dc_resource_validate_ctx_destruct(struct validate_context *context)
4562236b
HW		 2212{
2213 int i, j;
2214
ab2541b6
AC		 2215 for (i = 0; i < context->stream_count; i++) {
2216 for (j = 0; j < context->stream_status[i].surface_count; j++)
4562236b 2217 dc_surface_release(
ab2541b6 2218 context->stream_status[i].surfaces[j]);
4562236b 2219
ab2541b6
AC		 2220 context->stream_status[i].surface_count = 0;
2221 dc_stream_release(&context->streams[i]->public);
2222 context->streams[i] = NULL;
4562236b
HW		 2223 }
2224}
2225
2226/*
ab2541b6 2227 * Copy src_ctx into dst_ctx and retain all surfaces and streams referenced
4562236b
HW		 2228 * by the src_ctx
2229 */
8122a253 2230void dc_resource_validate_ctx_copy_construct(
4562236b
HW		 2231 const struct validate_context *src_ctx,
2232 struct validate_context *dst_ctx)
2233{
2234 int i, j;
9a3afbb3 2235 int ref_count = dst_ctx->ref_count;
4562236b
HW		 2236
2237 *dst_ctx = *src_ctx;
2238
a2b8659d 2239 for (i = 0; i < MAX_PIPES; i++) {
4562236b
HW		 2240 struct pipe_ctx *cur_pipe = &dst_ctx->res_ctx.pipe_ctx[i];
2241
2242 if (cur_pipe->top_pipe)
2243 cur_pipe->top_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
2244
2245 if (cur_pipe->bottom_pipe)
2246 cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
2247
2248 }
2249
ab2541b6
AC		 2250 for (i = 0; i < dst_ctx->stream_count; i++) {
2251 dc_stream_retain(&dst_ctx->streams[i]->public);
2252 for (j = 0; j < dst_ctx->stream_status[i].surface_count; j++)
4562236b 2253 dc_surface_retain(
ab2541b6 2254 dst_ctx->stream_status[i].surfaces[j]);
4562236b 2255 }
9a3afbb3
AG		 2256
2257 /* context refcount should not be overridden */
2258 dst_ctx->ref_count = ref_count;
2259
4562236b
HW		 2260}
2261
2262struct clock_source *dc_resource_find_first_free_pll(
a2b8659d
TC		 2263 struct resource_context *res_ctx,
2264 const struct resource_pool *pool)
4562236b
HW		 2265{
2266 int i;
2267
a2b8659d 2268 for (i = 0; i < pool->clk_src_count; ++i) {
4562236b 2269 if (res_ctx->clock_source_ref_count[i] == 0)
a2b8659d 2270 return pool->clock_sources[i];
4562236b
HW		 2271 }
2272
2273 return NULL;
2274}
2275
2276void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
2277{
2278 enum signal_type signal = SIGNAL_TYPE_NONE;
6e4d6bee 2279 struct encoder_info_frame *info = &pipe_ctx->encoder_info_frame;
4562236b
HW		 2280
2281 /* default all packets to invalid */
6e4d6bee
TC		 2282 info->avi.valid = false;
2283 info->gamut.valid = false;
2284 info->vendor.valid = false;
630e3573 2285 info->spd.valid = false;
6e4d6bee
TC		 2286 info->hdrsmd.valid = false;
2287 info->vsc.valid = false;
4562236b
HW		 2288
2289 signal = pipe_ctx->stream->signal;
2290
2291 /* HDMi and DP have different info packets*/
2292 if (dc_is_hdmi_signal(signal)) {
6e4d6bee
TC		 2293 set_avi_info_frame(&info->avi, pipe_ctx);
2294
2295 set_vendor_info_packet(&info->vendor, pipe_ctx->stream);
2296
2297 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2298
2299 set_hdr_static_info_packet(&info->hdrsmd,
2300 pipe_ctx->surface, pipe_ctx->stream);
2301
a33fa99d 2302 } else if (dc_is_dp_signal(signal)) {
6e4d6bee
TC		 2303 set_vsc_info_packet(&info->vsc, pipe_ctx->stream);
2304
2305 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2306
2307 set_hdr_static_info_packet(&info->hdrsmd,
2308 pipe_ctx->surface, pipe_ctx->stream);
a33fa99d 2309 }
4562236b 2310
6e4d6bee 2311 patch_gamut_packet_checksum(&info->gamut);
4562236b
HW		 2312}
2313
2314enum dc_status resource_map_clock_resources(
2315 const struct core_dc *dc,
430ef426
DL		 2316 struct validate_context *context,
2317 struct validate_context *old_context)
4562236b 2318{
ab2541b6 2319 int i, j;
a2b8659d 2320 const struct resource_pool *pool = dc->res_pool;
4562236b
HW		 2321
2322 /* acquire new resources */
ab2541b6
AC		 2323 for (i = 0; i < context->stream_count; i++) {
2324 const struct core_stream *stream = context->streams[i];
4562236b 2325
430ef426 2326 if (old_context && resource_is_stream_unchanged(old_context, stream))
ab2541b6
AC		 2327 continue;
2328
2329 for (j = 0; j < MAX_PIPES; j++) {
2330 struct pipe_ctx *pipe_ctx =
2331 &context->res_ctx.pipe_ctx[j];
4562236b 2332
ab2541b6 2333 if (context->res_ctx.pipe_ctx[j].stream != stream)
4562236b
HW		 2334 continue;
2335
ab2541b6
AC		 2336 if (dc_is_dp_signal(pipe_ctx->stream->signal)
2337 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)
a2b8659d 2338 pipe_ctx->clock_source = pool->dp_clock_source;
ab2541b6
AC		 2339 else {
2340 pipe_ctx->clock_source = NULL;
4562236b 2341
ab2541b6
AC		 2342 if (!dc->public.config.disable_disp_pll_sharing)
2343 resource_find_used_clk_src_for_sharing(
2344 &context->res_ctx,
2345 pipe_ctx);
4562236b 2346
ab2541b6 2347 if (pipe_ctx->clock_source == NULL)
4562236b 2348 pipe_ctx->clock_source =
a2b8659d
TC		 2349 dc_resource_find_first_free_pll(
2350 &context->res_ctx,
2351 pool);
ab2541b6 2352 }
4562236b 2353
ab2541b6
AC		 2354 if (pipe_ctx->clock_source == NULL)
2355 return DC_NO_CLOCK_SOURCE_RESOURCE;
4562236b 2356
ab2541b6 2357 resource_reference_clock_source(
a2b8659d 2358 &context->res_ctx, pool,
ab2541b6 2359 pipe_ctx->clock_source);
4562236b 2360
ab2541b6
AC		 2361 /* only one cs per stream regardless of mpo */
2362 break;
4562236b
HW		 2363 }
2364 }
2365
2366 return DC_OK;
2367}
2368
2369/*
2370 * Note: We need to disable output if clock sources change,
2371 * since bios does optimization and doesn't apply if changing
2372 * PHY when not already disabled.
2373 */
2374bool pipe_need_reprogram(
2375 struct pipe_ctx *pipe_ctx_old,
2376 struct pipe_ctx *pipe_ctx)
2377{
cfe4645e
DL		 2378 if (!pipe_ctx_old->stream)
2379 return false;
2380
4562236b
HW		 2381 if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink)
2382 return true;
2383
2384 if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal)
2385 return true;
2386
2387 if (pipe_ctx_old->audio != pipe_ctx->audio)
2388 return true;
2389
2390 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source
2391 && pipe_ctx_old->stream != pipe_ctx->stream)
2392 return true;
2393
2394 if (pipe_ctx_old->stream_enc != pipe_ctx->stream_enc)
2395 return true;
2396
2397 if (is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2398 return true;
2399
2400
2401 return false;
2402}
529cad0f
DW		 2403
2404void resource_build_bit_depth_reduction_params(const struct core_stream *stream,
2405 struct bit_depth_reduction_params *fmt_bit_depth)
2406{
2407 enum dc_dither_option option = stream->public.dither_option;
2408 enum dc_pixel_encoding pixel_encoding =
2409 stream->public.timing.pixel_encoding;
2410
2411 memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth));
2412
2413 if (option == DITHER_OPTION_DISABLE)
2414 return;
2415
2416 if (option == DITHER_OPTION_TRUN6) {
2417 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2418 fmt_bit_depth->flags.TRUNCATE_DEPTH = 0;
2419 } else if (option == DITHER_OPTION_TRUN8 ||
2420 option == DITHER_OPTION_TRUN8_SPATIAL6 ||
2421 option == DITHER_OPTION_TRUN8_FM6) {
2422 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2423 fmt_bit_depth->flags.TRUNCATE_DEPTH = 1;
2424 } else if (option == DITHER_OPTION_TRUN10 ||
2425 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
2426 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
2427 option == DITHER_OPTION_TRUN10_FM8 ||
2428 option == DITHER_OPTION_TRUN10_FM6 ||
2429 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2430 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2431 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2432 }
2433
2434 /* special case - Formatter can only reduce by 4 bits at most.
2435 * When reducing from 12 to 6 bits,
2436 * HW recommends we use trunc with round mode
2437 * (if we did nothing, trunc to 10 bits would be used)
2438 * note that any 12->10 bit reduction is ignored prior to DCE8,
2439 * as the input was 10 bits.
2440 */
2441 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2442 option == DITHER_OPTION_SPATIAL6 ||
2443 option == DITHER_OPTION_FM6) {
2444 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2445 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2446 fmt_bit_depth->flags.TRUNCATE_MODE = 1;
2447 }
2448
2449 /* spatial dither
2450 * note that spatial modes 1-3 are never used
2451 */
2452 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2453 option == DITHER_OPTION_SPATIAL6 ||
2454 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
2455 option == DITHER_OPTION_TRUN8_SPATIAL6) {
2456 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2457 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 0;
2458 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2459 fmt_bit_depth->flags.RGB_RANDOM =
2460 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2461 } else if (option == DITHER_OPTION_SPATIAL8_FRAME_RANDOM ||
2462 option == DITHER_OPTION_SPATIAL8 ||
2463 option == DITHER_OPTION_SPATIAL8_FM6 ||
2464 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
2465 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2466 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2467 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 1;
2468 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2469 fmt_bit_depth->flags.RGB_RANDOM =
2470 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2471 } else if (option == DITHER_OPTION_SPATIAL10_FRAME_RANDOM ||
2472 option == DITHER_OPTION_SPATIAL10 ||
2473 option == DITHER_OPTION_SPATIAL10_FM8 ||
2474 option == DITHER_OPTION_SPATIAL10_FM6) {
2475 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2476 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 2;
2477 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2478 fmt_bit_depth->flags.RGB_RANDOM =
2479 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2480 }
2481
2482 if (option == DITHER_OPTION_SPATIAL6 ||
2483 option == DITHER_OPTION_SPATIAL8 ||
2484 option == DITHER_OPTION_SPATIAL10) {
2485 fmt_bit_depth->flags.FRAME_RANDOM = 0;
2486 } else {
2487 fmt_bit_depth->flags.FRAME_RANDOM = 1;
2488 }
2489
2490 //////////////////////
2491 //// temporal dither
2492 //////////////////////
2493 if (option == DITHER_OPTION_FM6 ||
2494 option == DITHER_OPTION_SPATIAL8_FM6 ||
2495 option == DITHER_OPTION_SPATIAL10_FM6 ||
2496 option == DITHER_OPTION_TRUN10_FM6 ||
2497 option == DITHER_OPTION_TRUN8_FM6 ||
2498 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2499 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2500 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 0;
2501 } else if (option == DITHER_OPTION_FM8 ||
2502 option == DITHER_OPTION_SPATIAL10_FM8 ||
2503 option == DITHER_OPTION_TRUN10_FM8) {
2504 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2505 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 1;
2506 } else if (option == DITHER_OPTION_FM10) {
2507 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2508 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 2;
2509 }
2510
2511 fmt_bit_depth->pixel_encoding = pixel_encoding;
2512}
9345d987
AG		 2513
2514bool dc_validate_stream(const struct dc *dc, const struct dc_stream *stream)
2515{
2516 struct core_dc *core_dc = DC_TO_CORE(dc);
2517 struct dc_context *dc_ctx = core_dc->ctx;
2518 struct core_stream *core_stream = DC_STREAM_TO_CORE(stream);
2519 struct dc_link *link = core_stream->sink->link;
2520 struct timing_generator *tg = core_dc->res_pool->timing_generators[0];
2521 enum dc_status res = DC_OK;
2522
2523 calculate_phy_pix_clks(core_stream);
2524
2525 if (!tg->funcs->validate_timing(tg, &core_stream->public.timing))
2526 res = DC_FAIL_CONTROLLER_VALIDATE;
2527
2528 if (res == DC_OK)
2529 if (!link->link_enc->funcs->validate_output_with_stream(
2530 link->link_enc, core_stream))
2531 res = DC_FAIL_ENC_VALIDATE;
2532
2533 /* TODO: validate audio ASIC caps, encoder */
2534
2535 if (res == DC_OK)
2536 res = dc_link_validate_mode_timing(core_stream,
2537 link,
2538 &core_stream->public.timing);
2539
2540 if (res != DC_OK)
2541 DC_ERROR("Failed validation for stream %p, err:%d, !\n",
2542 stream, res);
2543
2544 return res == DC_OK;
2545}
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