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drm/amd/display: CTS 4.2.2.7
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / display / dc / core / dc_resource.c
CommitLineData
4562236b 1/*
9ce6aae1 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4562236b
HW		 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25#include "dm_services.h"
26
27#include "resource.h"
28#include "include/irq_service_interface.h"
29#include "link_encoder.h"
30#include "stream_encoder.h"
31#include "opp.h"
32#include "timing_generator.h"
33#include "transform.h"
d94585a0 34#include "dpp.h"
5ac3d3c9 35#include "core_types.h"
4562236b 36#include "set_mode_types.h"
4562236b 37#include "virtual/virtual_stream_encoder.h"
3b94a400 38#include "dpcd_defs.h"
4562236b
HW		 39
40#include "dce80/dce80_resource.h"
41#include "dce100/dce100_resource.h"
42#include "dce110/dce110_resource.h"
43#include "dce112/dce112_resource.h"
dc37a9a0 44#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
ff5ef992
AD		 45#include "dcn10/dcn10_resource.h"
46#endif
2c8ad2d5 47#include "dce120/dce120_resource.h"
5d4b05dd
BL		 48
49#define DC_LOGGER_INIT(logger)
50
4562236b
HW		 51enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
52{
53 enum dce_version dc_version = DCE_VERSION_UNKNOWN;
54 switch (asic_id.chip_family) {
55
56 case FAMILY_CI:
4562236b
HW		 57 dc_version = DCE_VERSION_8_0;
58 break;
ebfdf0d0
AD		 59 case FAMILY_KV:
60 if (ASIC_REV_IS_KALINDI(asic_id.hw_internal_rev) ||
61 ASIC_REV_IS_BHAVANI(asic_id.hw_internal_rev) ||
62 ASIC_REV_IS_GODAVARI(asic_id.hw_internal_rev))
63 dc_version = DCE_VERSION_8_3;
64 else
65 dc_version = DCE_VERSION_8_1;
66 break;
4562236b
HW		 67 case FAMILY_CZ:
68 dc_version = DCE_VERSION_11_0;
69 break;
70
71 case FAMILY_VI:
72 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
73 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
74 dc_version = DCE_VERSION_10_0;
75 break;
76 }
77 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
b264d345
JL		 78 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
79 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
4562236b
HW		 80 dc_version = DCE_VERSION_11_2;
81 }
0c75d5ac
JFZ		 82 if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev))
83 dc_version = DCE_VERSION_11_22;
4562236b 84 break;
2c8ad2d5
AD		 85 case FAMILY_AI:
86 dc_version = DCE_VERSION_12_0;
87 break;
dc37a9a0 88#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
ff5ef992
AD		 89 case FAMILY_RV:
90 dc_version = DCN_VERSION_1_0;
0e3d73f1
BL		 91#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
92 if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev))
93 dc_version = DCN_VERSION_1_01;
94#endif
ff5ef992
AD		 95 break;
96#endif
4562236b
HW		 97 default:
98 dc_version = DCE_VERSION_UNKNOWN;
99 break;
100 }
101 return dc_version;
102}
103
104struct resource_pool *dc_create_resource_pool(
fb3466a4 105 struct dc *dc,
4562236b
HW		 106 int num_virtual_links,
107 enum dce_version dc_version,
108 struct hw_asic_id asic_id)
109{
5ac3d3c9 110 struct resource_pool *res_pool = NULL;
4562236b
HW		 111
112 switch (dc_version) {
113 case DCE_VERSION_8_0:
7992a629
AD		 114 res_pool = dce80_create_resource_pool(
115 num_virtual_links, dc);
116 break;
ebfdf0d0 117 case DCE_VERSION_8_1:
7992a629
AD		 118 res_pool = dce81_create_resource_pool(
119 num_virtual_links, dc);
120 break;
ebfdf0d0 121 case DCE_VERSION_8_3:
7992a629 122 res_pool = dce83_create_resource_pool(
4562236b 123 num_virtual_links, dc);
5ac3d3c9 124 break;
4562236b 125 case DCE_VERSION_10_0:
5ac3d3c9 126 res_pool = dce100_create_resource_pool(
4562236b 127 num_virtual_links, dc);
5ac3d3c9 128 break;
4562236b 129 case DCE_VERSION_11_0:
5ac3d3c9 130 res_pool = dce110_create_resource_pool(
4562236b 131 num_virtual_links, dc, asic_id);
5ac3d3c9 132 break;
4562236b 133 case DCE_VERSION_11_2:
0c75d5ac 134 case DCE_VERSION_11_22:
5ac3d3c9 135 res_pool = dce112_create_resource_pool(
4562236b 136 num_virtual_links, dc);
5ac3d3c9 137 break;
2c8ad2d5
AD		 138 case DCE_VERSION_12_0:
139 res_pool = dce120_create_resource_pool(
140 num_virtual_links, dc);
141 break;
ff5ef992 142
dc37a9a0 143#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
ff5ef992 144 case DCN_VERSION_1_0:
0e3d73f1
BL		 145#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
146 case DCN_VERSION_1_01:
147#endif
ff5ef992 148 res_pool = dcn10_create_resource_pool(
503a7c6f 149 num_virtual_links, dc);
ff5ef992
AD		 150 break;
151#endif
3639fa68
ZF		 152
153
4562236b
HW		 154 default:
155 break;
156 }
5ac3d3c9 157 if (res_pool != NULL) {
1515a47b 158 struct dc_firmware_info fw_info = { { 0 } };
5ac3d3c9
CL		 159
160 if (dc->ctx->dc_bios->funcs->get_firmware_info(
161 dc->ctx->dc_bios, &fw_info) == BP_RESULT_OK) {
162 res_pool->ref_clock_inKhz = fw_info.pll_info.crystal_frequency;
163 } else
164 ASSERT_CRITICAL(false);
165 }
4562236b 166
5ac3d3c9 167 return res_pool;
4562236b
HW		 168}
169
fb3466a4 170void dc_destroy_resource_pool(struct dc *dc)
4562236b
HW		 171{
172 if (dc) {
173 if (dc->res_pool)
174 dc->res_pool->funcs->destroy(&dc->res_pool);
175
d029810c 176 kfree(dc->hwseq);
4562236b
HW		 177 }
178}
179
180static void update_num_audio(
181 const struct resource_straps *straps,
182 unsigned int *num_audio,
183 struct audio_support *aud_support)
184{
b8e9eb72
CL		 185 aud_support->dp_audio = true;
186 aud_support->hdmi_audio_native = false;
187 aud_support->hdmi_audio_on_dongle = false;
188
4562236b 189 if (straps->hdmi_disable == 0) {
4562236b
HW		 190 if (straps->dc_pinstraps_audio & 0x2) {
191 aud_support->hdmi_audio_on_dongle = true;
b8e9eb72 192 aud_support->hdmi_audio_native = true;
4562236b
HW		 193 }
194 }
195
196 switch (straps->audio_stream_number) {
197 case 0: /* multi streams supported */
198 break;
199 case 1: /* multi streams not supported */
200 *num_audio = 1;
201 break;
202 default:
203 DC_ERR("DC: unexpected audio fuse!\n");
17a96033 204 }
4562236b
HW		 205}
206
207bool resource_construct(
208 unsigned int num_virtual_links,
fb3466a4 209 struct dc *dc,
4562236b
HW		 210 struct resource_pool *pool,
211 const struct resource_create_funcs *create_funcs)
212{
213 struct dc_context *ctx = dc->ctx;
214 const struct resource_caps *caps = pool->res_cap;
215 int i;
216 unsigned int num_audio = caps->num_audio;
217 struct resource_straps straps = {0};
218
219 if (create_funcs->read_dce_straps)
220 create_funcs->read_dce_straps(dc->ctx, &straps);
221
222 pool->audio_count = 0;
223 if (create_funcs->create_audio) {
224 /* find the total number of streams available via the
225 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
226 * registers (one for each pin) starting from pin 1
227 * up to the max number of audio pins.
228 * We stop on the first pin where
229 * PORT_CONNECTIVITY == 1 (as instructed by HW team).
230 */
231 update_num_audio(&straps, &num_audio, &pool->audio_support);
232 for (i = 0; i < pool->pipe_count && i < num_audio; i++) {
233 struct audio *aud = create_funcs->create_audio(ctx, i);
234
235 if (aud == NULL) {
236 DC_ERR("DC: failed to create audio!\n");
237 return false;
238 }
239
240 if (!aud->funcs->endpoint_valid(aud)) {
241 aud->funcs->destroy(&aud);
242 break;
243 }
244
245 pool->audios[i] = aud;
246 pool->audio_count++;
247 }
248 }
249
250 pool->stream_enc_count = 0;
251 if (create_funcs->create_stream_encoder) {
252 for (i = 0; i < caps->num_stream_encoder; i++) {
253 pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx);
254 if (pool->stream_enc[i] == NULL)
255 DC_ERR("DC: failed to create stream_encoder!\n");
256 pool->stream_enc_count++;
257 }
258 }
4176664b
CL		 259 dc->caps.dynamic_audio = false;
260 if (pool->audio_count < pool->stream_enc_count) {
261 dc->caps.dynamic_audio = true;
262 }
4562236b
HW		 263 for (i = 0; i < num_virtual_links; i++) {
264 pool->stream_enc[pool->stream_enc_count] =
265 virtual_stream_encoder_create(
266 ctx, ctx->dc_bios);
267 if (pool->stream_enc[pool->stream_enc_count] == NULL) {
268 DC_ERR("DC: failed to create stream_encoder!\n");
269 return false;
270 }
271 pool->stream_enc_count++;
272 }
273
274 dc->hwseq = create_funcs->create_hwseq(ctx);
275
276 return true;
277}
ad8960a6
ML		 278static int find_matching_clock_source(
279 const struct resource_pool *pool,
280 struct clock_source *clock_source)
281{
4562236b 282
ad8960a6
ML		 283 int i;
284
285 for (i = 0; i < pool->clk_src_count; i++) {
286 if (pool->clock_sources[i] == clock_source)
287 return i;
288 }
289 return -1;
290}
4562236b 291
21e67d4d 292void resource_unreference_clock_source(
4562236b 293 struct resource_context *res_ctx,
a2b8659d 294 const struct resource_pool *pool,
4a629536 295 struct clock_source *clock_source)
4562236b 296{
ad8960a6 297 int i = find_matching_clock_source(pool, clock_source);
4562236b 298
ad8960a6 299 if (i > -1)
4562236b
HW		 300 res_ctx->clock_source_ref_count[i]--;
301
21e67d4d 302 if (pool->dp_clock_source == clock_source)
4562236b 303 res_ctx->dp_clock_source_ref_count--;
4562236b
HW		 304}
305
306void resource_reference_clock_source(
307 struct resource_context *res_ctx,
a2b8659d 308 const struct resource_pool *pool,
4562236b
HW		 309 struct clock_source *clock_source)
310{
ad8960a6 311 int i = find_matching_clock_source(pool, clock_source);
4562236b 312
ad8960a6 313 if (i > -1)
4562236b 314 res_ctx->clock_source_ref_count[i]++;
4562236b 315
a2b8659d 316 if (pool->dp_clock_source == clock_source)
4562236b
HW		 317 res_ctx->dp_clock_source_ref_count++;
318}
319
ad8960a6
ML		 320int resource_get_clock_source_reference(
321 struct resource_context *res_ctx,
322 const struct resource_pool *pool,
323 struct clock_source *clock_source)
324{
325 int i = find_matching_clock_source(pool, clock_source);
326
327 if (i > -1)
328 return res_ctx->clock_source_ref_count[i];
329
330 if (pool->dp_clock_source == clock_source)
331 return res_ctx->dp_clock_source_ref_count;
332
333 return -1;
334}
335
4562236b 336bool resource_are_streams_timing_synchronizable(
0971c40e
HW		 337 struct dc_stream_state *stream1,
338 struct dc_stream_state *stream2)
4562236b 339{
4fa086b9 340 if (stream1->timing.h_total != stream2->timing.h_total)
4562236b
HW		 341 return false;
342
4fa086b9 343 if (stream1->timing.v_total != stream2->timing.v_total)
4562236b
HW		 344 return false;
345
4fa086b9
LSL		 346 if (stream1->timing.h_addressable
347 != stream2->timing.h_addressable)
4562236b
HW		 348 return false;
349
4fa086b9
LSL		 350 if (stream1->timing.v_addressable
351 != stream2->timing.v_addressable)
4562236b
HW		 352 return false;
353
4fa086b9
LSL		 354 if (stream1->timing.pix_clk_khz
355 != stream2->timing.pix_clk_khz)
4562236b
HW		 356 return false;
357
3e27e10e
ML		 358 if (stream1->clamping.c_depth != stream2->clamping.c_depth)
359 return false;
360
4562236b 361 if (stream1->phy_pix_clk != stream2->phy_pix_clk
7e2fe319
CL		 362 && (!dc_is_dp_signal(stream1->signal)
363 || !dc_is_dp_signal(stream2->signal)))
4562236b
HW		 364 return false;
365
d77f778e
CL		 366 if (stream1->view_format != stream2->view_format)
367 return false;
368
4562236b
HW		 369 return true;
370}
3e27e10e
ML		 371static bool is_dp_and_hdmi_sharable(
372 struct dc_stream_state *stream1,
373 struct dc_stream_state *stream2)
374{
375 if (stream1->ctx->dc->caps.disable_dp_clk_share)
376 return false;
377
378 if (stream1->clamping.c_depth != COLOR_DEPTH_888 ||
d77f778e 379 stream2->clamping.c_depth != COLOR_DEPTH_888)
43fbbe89 380 return false;
3e27e10e
ML		 381
382 return true;
383
384}
4562236b
HW		 385
386static bool is_sharable_clk_src(
387 const struct pipe_ctx *pipe_with_clk_src,
388 const struct pipe_ctx *pipe)
389{
390 if (pipe_with_clk_src->clock_source == NULL)
391 return false;
392
393 if (pipe_with_clk_src->stream->signal == SIGNAL_TYPE_VIRTUAL)
394 return false;
395
3e27e10e
ML		 396 if (dc_is_dp_signal(pipe_with_clk_src->stream->signal) ||
397 (dc_is_dp_signal(pipe->stream->signal) &&
398 !is_dp_and_hdmi_sharable(pipe_with_clk_src->stream,
399 pipe->stream)))
4562236b
HW		 400 return false;
401
402 if (dc_is_hdmi_signal(pipe_with_clk_src->stream->signal)
fc69009e 403 && dc_is_dual_link_signal(pipe->stream->signal))
4562236b
HW		 404 return false;
405
406 if (dc_is_hdmi_signal(pipe->stream->signal)
fc69009e 407 && dc_is_dual_link_signal(pipe_with_clk_src->stream->signal))
4562236b
HW		 408 return false;
409
410 if (!resource_are_streams_timing_synchronizable(
411 pipe_with_clk_src->stream, pipe->stream))
412 return false;
413
414 return true;
415}
416
417struct clock_source *resource_find_used_clk_src_for_sharing(
418 struct resource_context *res_ctx,
419 struct pipe_ctx *pipe_ctx)
420{
421 int i;
422
423 for (i = 0; i < MAX_PIPES; i++) {
424 if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx))
425 return res_ctx->pipe_ctx[i].clock_source;
426 }
427
428 return NULL;
429}
430
431static enum pixel_format convert_pixel_format_to_dalsurface(
432 enum surface_pixel_format surface_pixel_format)
433{
434 enum pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
435
436 switch (surface_pixel_format) {
437 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
438 dal_pixel_format = PIXEL_FORMAT_INDEX8;
439 break;
440 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
441 dal_pixel_format = PIXEL_FORMAT_RGB565;
442 break;
443 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
444 dal_pixel_format = PIXEL_FORMAT_RGB565;
445 break;
446 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
447 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
448 break;
8693049a 449 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
4562236b
HW		 450 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
451 break;
452 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
453 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
454 break;
455 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
456 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
457 break;
458 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
459 dal_pixel_format = PIXEL_FORMAT_ARGB2101010_XRBIAS;
460 break;
461 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
462 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
463 dal_pixel_format = PIXEL_FORMAT_FP16;
464 break;
465 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
4562236b 466 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
87449a90 467 dal_pixel_format = PIXEL_FORMAT_420BPP8;
4562236b 468 break;
ffbcd19a
VP		 469 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
470 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
87449a90 471 dal_pixel_format = PIXEL_FORMAT_420BPP10;
ffbcd19a 472 break;
4562236b
HW		 473 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
474 default:
475 dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
476 break;
477 }
478 return dal_pixel_format;
479}
480
9b6067c0
DL		 481static inline void get_vp_scan_direction(
482 enum dc_rotation_angle rotation,
483 bool horizontal_mirror,
484 bool *orthogonal_rotation,
485 bool *flip_vert_scan_dir,
486 bool *flip_horz_scan_dir)
4562236b 487{
9b6067c0
DL		 488 *orthogonal_rotation = false;
489 *flip_vert_scan_dir = false;
490 *flip_horz_scan_dir = false;
491 if (rotation == ROTATION_ANGLE_180) {
492 *flip_vert_scan_dir = true;
493 *flip_horz_scan_dir = true;
494 } else if (rotation == ROTATION_ANGLE_90) {
495 *orthogonal_rotation = true;
496 *flip_horz_scan_dir = true;
497 } else if (rotation == ROTATION_ANGLE_270) {
498 *orthogonal_rotation = true;
499 *flip_vert_scan_dir = true;
500 }
501
502 if (horizontal_mirror)
503 *flip_horz_scan_dir = !*flip_horz_scan_dir;
4562236b
HW		 504}
505
b2d0a103 506static void calculate_viewport(struct pipe_ctx *pipe_ctx)
4562236b 507{
3be5262e 508 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 509 const struct dc_stream_state *stream = pipe_ctx->stream;
6702a9ac 510 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
3be5262e 511 struct rect surf_src = plane_state->src_rect;
9b6067c0 512 struct rect clip, dest;
87449a90
AK		 513 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
514 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
1fbd2cfc 515 bool pri_split = pipe_ctx->bottom_pipe &&
3be5262e 516 pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state;
1fbd2cfc 517 bool sec_split = pipe_ctx->top_pipe &&
3be5262e 518 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
9b6067c0 519 bool orthogonal_rotation, flip_y_start, flip_x_start;
83d40659 520
7f5c22d1
VP		 521 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE ||
522 stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) {
7b779c99
VP		 523 pri_split = false;
524 sec_split = false;
525 }
86006a7f 526
4562236b
HW		 527 /* The actual clip is an intersection between stream
528 * source and surface clip
529 */
9b6067c0 530 dest = plane_state->dst_rect;
3be5262e
HW		 531 clip.x = stream->src.x > plane_state->clip_rect.x ?
532 stream->src.x : plane_state->clip_rect.x;
4562236b 533
1fbd2cfc 534 clip.width = stream->src.x + stream->src.width <
3be5262e 535 plane_state->clip_rect.x + plane_state->clip_rect.width ?
1fbd2cfc 536 stream->src.x + stream->src.width - clip.x :
3be5262e 537 plane_state->clip_rect.x + plane_state->clip_rect.width - clip.x ;
4562236b 538
3be5262e
HW		 539 clip.y = stream->src.y > plane_state->clip_rect.y ?
540 stream->src.y : plane_state->clip_rect.y;
4562236b 541
1fbd2cfc 542 clip.height = stream->src.y + stream->src.height <
3be5262e 543 plane_state->clip_rect.y + plane_state->clip_rect.height ?
1fbd2cfc 544 stream->src.y + stream->src.height - clip.y :
3be5262e 545 plane_state->clip_rect.y + plane_state->clip_rect.height - clip.y ;
4562236b 546
9b6067c0
DL		 547 /*
548 * Need to calculate how scan origin is shifted in vp space
549 * to correctly rotate clip and dst
550 */
551 get_vp_scan_direction(
552 plane_state->rotation,
553 plane_state->horizontal_mirror,
554 &orthogonal_rotation,
555 &flip_y_start,
556 &flip_x_start);
557
558 if (orthogonal_rotation) {
559 swap(clip.x, clip.y);
560 swap(clip.width, clip.height);
561 swap(dest.x, dest.y);
562 swap(dest.width, dest.height);
563 }
564 if (flip_x_start) {
565 clip.x = dest.x + dest.width - clip.x - clip.width;
566 dest.x = 0;
567 }
568 if (flip_y_start) {
569 clip.y = dest.y + dest.height - clip.y - clip.height;
570 dest.y = 0;
571 }
572
86006a7f 573 /* offset = surf_src.ofs + (clip.ofs - surface->dst_rect.ofs) * scl_ratio
4562236b
HW		 574 * num_pixels = clip.num_pix * scl_ratio
575 */
9b6067c0
DL		 576 data->viewport.x = surf_src.x + (clip.x - dest.x) * surf_src.width / dest.width;
577 data->viewport.width = clip.width * surf_src.width / dest.width;
578
579 data->viewport.y = surf_src.y + (clip.y - dest.y) * surf_src.height / dest.height;
580 data->viewport.height = clip.height * surf_src.height / dest.height;
581
582 /* Handle split */
583 if (pri_split || sec_split) {
584 if (orthogonal_rotation) {
585 if (flip_y_start != pri_split)
586 data->viewport.height /= 2;
587 else {
588 data->viewport.y += data->viewport.height / 2;
589 /* Ceil offset pipe */
590 data->viewport.height = (data->viewport.height + 1) / 2;
591 }
592 } else {
593 if (flip_x_start != pri_split)
594 data->viewport.width /= 2;
595 else {
596 data->viewport.x += data->viewport.width / 2;
597 /* Ceil offset pipe */
598 data->viewport.width = (data->viewport.width + 1) / 2;
599 }
600 }
601 }
9b5349f7 602
b2d0a103
DL		 603 /* Round down, compensate in init */
604 data->viewport_c.x = data->viewport.x / vpc_div;
605 data->viewport_c.y = data->viewport.y / vpc_div;
9b6067c0
DL		 606 data->inits.h_c = (data->viewport.x % vpc_div) != 0 ? dc_fixpt_half : dc_fixpt_zero;
607 data->inits.v_c = (data->viewport.y % vpc_div) != 0 ? dc_fixpt_half : dc_fixpt_zero;
608
b2d0a103
DL		 609 /* Round up, assume original video size always even dimensions */
610 data->viewport_c.width = (data->viewport.width + vpc_div - 1) / vpc_div;
611 data->viewport_c.height = (data->viewport.height + vpc_div - 1) / vpc_div;
4562236b
HW		 612}
613
9b6067c0 614static void calculate_recout(struct pipe_ctx *pipe_ctx)
4562236b 615{
3be5262e 616 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 617 const struct dc_stream_state *stream = pipe_ctx->stream;
3be5262e 618 struct rect surf_clip = plane_state->clip_rect;
0c31a821
YS		 619 bool pri_split = pipe_ctx->bottom_pipe &&
620 pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state;
621 bool sec_split = pipe_ctx->top_pipe &&
622 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
b0131391 623 bool top_bottom_split = stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM;
4562236b 624
6702a9ac 625 pipe_ctx->plane_res.scl_data.recout.x = stream->dst.x;
4fa086b9 626 if (stream->src.x < surf_clip.x)
6702a9ac 627 pipe_ctx->plane_res.scl_data.recout.x += (surf_clip.x
4fa086b9
LSL		 628 - stream->src.x) * stream->dst.width
629 / stream->src.width;
4562236b 630
6702a9ac 631 pipe_ctx->plane_res.scl_data.recout.width = surf_clip.width *
4fa086b9 632 stream->dst.width / stream->src.width;
6702a9ac 633 if (pipe_ctx->plane_res.scl_data.recout.width + pipe_ctx->plane_res.scl_data.recout.x >
4fa086b9 634 stream->dst.x + stream->dst.width)
6702a9ac 635 pipe_ctx->plane_res.scl_data.recout.width =
4fa086b9 636 stream->dst.x + stream->dst.width
6702a9ac 637 - pipe_ctx->plane_res.scl_data.recout.x;
4562236b 638
6702a9ac 639 pipe_ctx->plane_res.scl_data.recout.y = stream->dst.y;
4fa086b9 640 if (stream->src.y < surf_clip.y)
6702a9ac 641 pipe_ctx->plane_res.scl_data.recout.y += (surf_clip.y
4fa086b9
LSL		 642 - stream->src.y) * stream->dst.height
643 / stream->src.height;
4562236b 644
6702a9ac 645 pipe_ctx->plane_res.scl_data.recout.height = surf_clip.height *
4fa086b9 646 stream->dst.height / stream->src.height;
6702a9ac 647 if (pipe_ctx->plane_res.scl_data.recout.height + pipe_ctx->plane_res.scl_data.recout.y >
4fa086b9 648 stream->dst.y + stream->dst.height)
6702a9ac 649 pipe_ctx->plane_res.scl_data.recout.height =
4fa086b9 650 stream->dst.y + stream->dst.height
6702a9ac 651 - pipe_ctx->plane_res.scl_data.recout.y;
b2d0a103 652
9b6067c0 653 /* Handle h & v split, handle rotation using viewport */
b0131391
DL		 654 if (sec_split && top_bottom_split) {
655 pipe_ctx->plane_res.scl_data.recout.y +=
656 pipe_ctx->plane_res.scl_data.recout.height / 2;
0c31a821 657 /* Floor primary pipe, ceil 2ndary pipe */
b0131391
DL		 658 pipe_ctx->plane_res.scl_data.recout.height =
659 (pipe_ctx->plane_res.scl_data.recout.height + 1) / 2;
660 } else if (pri_split && top_bottom_split)
0c31a821 661 pipe_ctx->plane_res.scl_data.recout.height /= 2;
9b6067c0
DL		 662 else if (sec_split) {
663 pipe_ctx->plane_res.scl_data.recout.x +=
664 pipe_ctx->plane_res.scl_data.recout.width / 2;
665 /* Ceil offset pipe */
666 pipe_ctx->plane_res.scl_data.recout.width =
667 (pipe_ctx->plane_res.scl_data.recout.width + 1) / 2;
668 } else if (pri_split)
669 pipe_ctx->plane_res.scl_data.recout.width /= 2;
4562236b
HW		 670}
671
b2d0a103 672static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)
4562236b 673{
3be5262e 674 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 675 const struct dc_stream_state *stream = pipe_ctx->stream;
3be5262e 676 struct rect surf_src = plane_state->src_rect;
4fa086b9
LSL		 677 const int in_w = stream->src.width;
678 const int in_h = stream->src.height;
679 const int out_w = stream->dst.width;
680 const int out_h = stream->dst.height;
4562236b 681
9b6067c0 682 /*Swap surf_src height and width since scaling ratios are in recout rotation*/
3be5262e
HW		 683 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
684 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
9b6067c0 685 swap(surf_src.height, surf_src.width);
86006a7f 686
eb0e5154 687 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_from_fraction(
86006a7f 688 surf_src.width,
3be5262e 689 plane_state->dst_rect.width);
eb0e5154 690 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction(
86006a7f 691 surf_src.height,
3be5262e 692 plane_state->dst_rect.height);
4562236b 693
4fa086b9 694 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
6702a9ac 695 pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2;
4fa086b9 696 else if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
6702a9ac 697 pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2;
4562236b 698
6702a9ac
HW		 699 pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64(
700 pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h);
701 pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64(
702 pipe_ctx->plane_res.scl_data.ratios.horz.value * in_w, out_w);
4562236b 703
6702a9ac
HW		 704 pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz;
705 pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert;
4562236b 706
6702a9ac
HW		 707 if (pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP8
708 || pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP10) {
709 pipe_ctx->plane_res.scl_data.ratios.horz_c.value /= 2;
710 pipe_ctx->plane_res.scl_data.ratios.vert_c.value /= 2;
4562236b 711 }
0002d3ac
DL		 712 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_truncate(
713 pipe_ctx->plane_res.scl_data.ratios.horz, 19);
714 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_truncate(
715 pipe_ctx->plane_res.scl_data.ratios.vert, 19);
716 pipe_ctx->plane_res.scl_data.ratios.horz_c = dc_fixpt_truncate(
717 pipe_ctx->plane_res.scl_data.ratios.horz_c, 19);
718 pipe_ctx->plane_res.scl_data.ratios.vert_c = dc_fixpt_truncate(
719 pipe_ctx->plane_res.scl_data.ratios.vert_c, 19);
4562236b
HW		 720}
721
9b6067c0
DL		 722static inline void adjust_vp_and_init_for_seamless_clip(
723 bool flip_scan_dir,
724 int recout_skip,
725 int src_size,
726 int taps,
727 struct fixed31_32 ratio,
728 struct fixed31_32 *init,
729 int *vp_offset,
730 int *vp_size)
b2d0a103 731{
9b6067c0 732 if (!flip_scan_dir) {
9a08f51f 733 /* Adjust for viewport end clip-off */
9b6067c0
DL		 734 if ((*vp_offset + *vp_size) < src_size) {
735 int vp_clip = src_size - *vp_size - *vp_offset;
736 int int_part = dc_fixpt_floor(dc_fixpt_sub(*init, ratio));
9a08f51f
DL		 737
738 int_part = int_part > 0 ? int_part : 0;
9b6067c0 739 *vp_size += int_part < vp_clip ? int_part : vp_clip;
9a08f51f 740 }
b2d0a103 741
9a08f51f 742 /* Adjust for non-0 viewport offset */
9b6067c0 743 if (*vp_offset) {
9a08f51f
DL		 744 int int_part;
745
9b6067c0
DL		 746 *init = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_skip));
747 int_part = dc_fixpt_floor(*init) - *vp_offset;
748 if (int_part < taps) {
749 int int_adj = *vp_offset >= (taps - int_part) ?
750 (taps - int_part) : *vp_offset;
751 *vp_offset -= int_adj;
752 *vp_size += int_adj;
9a08f51f 753 int_part += int_adj;
9b6067c0
DL		 754 } else if (int_part > taps) {
755 *vp_offset += int_part - taps;
756 *vp_size -= int_part - taps;
757 int_part = taps;
9a08f51f 758 }
9b6067c0
DL		 759 init->value &= 0xffffffff;
760 *init = dc_fixpt_add_int(*init, int_part);
9a08f51f
DL		 761 }
762 } else {
763 /* Adjust for non-0 viewport offset */
9b6067c0
DL		 764 if (*vp_offset) {
765 int int_part = dc_fixpt_floor(dc_fixpt_sub(*init, ratio));
b2d0a103 766
9a08f51f 767 int_part = int_part > 0 ? int_part : 0;
9b6067c0
DL		 768 *vp_size += int_part < *vp_offset ? int_part : *vp_offset;
769 *vp_offset -= int_part < *vp_offset ? int_part : *vp_offset;
9a08f51f 770 }
b2d0a103 771
9a08f51f 772 /* Adjust for viewport end clip-off */
9b6067c0 773 if ((*vp_offset + *vp_size) < src_size) {
9a08f51f 774 int int_part;
9b6067c0 775 int end_offset = src_size - *vp_offset - *vp_size;
9a08f51f
DL		 776
777 /*
778 * this is init if vp had no offset, keep in mind this is from the
779 * right side of vp due to scan direction
780 */
9b6067c0 781 *init = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_skip));
9a08f51f
DL		 782 /*
783 * this is the difference between first pixel of viewport available to read
784 * and init position, takning into account scan direction
785 */
9b6067c0
DL		 786 int_part = dc_fixpt_floor(*init) - end_offset;
787 if (int_part < taps) {
788 int int_adj = end_offset >= (taps - int_part) ?
789 (taps - int_part) : end_offset;
790 *vp_size += int_adj;
9a08f51f 791 int_part += int_adj;
9b6067c0
DL		 792 } else if (int_part > taps) {
793 *vp_size += int_part - taps;
794 int_part = taps;
9a08f51f 795 }
9b6067c0
DL		 796 init->value &= 0xffffffff;
797 *init = dc_fixpt_add_int(*init, int_part);
b2d0a103 798 }
b2d0a103 799 }
9b6067c0 800}
9a08f51f 801
9b6067c0
DL		 802static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx)
803{
804 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
805 const struct dc_stream_state *stream = pipe_ctx->stream;
806 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
807 struct rect src = pipe_ctx->plane_state->src_rect;
808 int recout_skip_h, recout_skip_v, surf_size_h, surf_size_v;
809 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
810 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
811 bool orthogonal_rotation, flip_vert_scan_dir, flip_horz_scan_dir;
9a08f51f 812
9b6067c0
DL		 813 /*
814 * Need to calculate the scan direction for viewport to make adjustments
815 */
816 get_vp_scan_direction(
817 plane_state->rotation,
818 plane_state->horizontal_mirror,
819 &orthogonal_rotation,
820 &flip_vert_scan_dir,
821 &flip_horz_scan_dir);
822
823 /* Calculate src rect rotation adjusted to recout space */
824 surf_size_h = src.x + src.width;
825 surf_size_v = src.y + src.height;
826 if (flip_horz_scan_dir)
827 src.x = 0;
828 if (flip_vert_scan_dir)
829 src.y = 0;
830 if (orthogonal_rotation) {
831 swap(src.x, src.y);
832 swap(src.width, src.height);
833 }
9a08f51f 834
9b6067c0
DL		 835 /* Recout matching initial vp offset = recout_offset - (stream dst offset +
836 * ((surf dst offset - stream src offset) * 1/ stream scaling ratio)
837 * - (surf surf_src offset * 1/ full scl ratio))
838 */
839 recout_skip_h = data->recout.x - (stream->dst.x + (plane_state->dst_rect.x - stream->src.x)
840 * stream->dst.width / stream->src.width -
841 src.x * plane_state->dst_rect.width / src.width
842 * stream->dst.width / stream->src.width);
843 recout_skip_v = data->recout.y - (stream->dst.y + (plane_state->dst_rect.y - stream->src.y)
844 * stream->dst.height / stream->src.height -
845 src.y * plane_state->dst_rect.height / src.height
846 * stream->dst.height / stream->src.height);
847 if (orthogonal_rotation)
848 swap(recout_skip_h, recout_skip_v);
849 /*
850 * Init calculated according to formula:
851 * init = (scaling_ratio + number_of_taps + 1) / 2
852 * init_bot = init + scaling_ratio
853 * init_c = init + truncated_vp_c_offset(from calculate viewport)
854 */
855 data->inits.h = dc_fixpt_truncate(dc_fixpt_div_int(
856 dc_fixpt_add_int(data->ratios.horz, data->taps.h_taps + 1), 2), 19);
b2d0a103 857
9b6067c0
DL		 858 data->inits.h_c = dc_fixpt_truncate(dc_fixpt_add(data->inits.h_c, dc_fixpt_div_int(
859 dc_fixpt_add_int(data->ratios.horz_c, data->taps.h_taps_c + 1), 2)), 19);
9a08f51f 860
9b6067c0
DL		 861 data->inits.v = dc_fixpt_truncate(dc_fixpt_div_int(
862 dc_fixpt_add_int(data->ratios.vert, data->taps.v_taps + 1), 2), 19);
9a08f51f 863
9b6067c0
DL		 864 data->inits.v_c = dc_fixpt_truncate(dc_fixpt_add(data->inits.v_c, dc_fixpt_div_int(
865 dc_fixpt_add_int(data->ratios.vert_c, data->taps.v_taps_c + 1), 2)), 19);
9a08f51f 866
9b6067c0
DL		 867 /*
868 * Taps, inits and scaling ratios are in recout space need to rotate
869 * to viewport rotation before adjustment
870 */
871 adjust_vp_and_init_for_seamless_clip(
872 flip_horz_scan_dir,
873 recout_skip_h,
874 surf_size_h,
875 orthogonal_rotation ? data->taps.v_taps : data->taps.h_taps,
876 orthogonal_rotation ? data->ratios.vert : data->ratios.horz,
877 orthogonal_rotation ? &data->inits.v : &data->inits.h,
878 &data->viewport.x,
879 &data->viewport.width);
880 adjust_vp_and_init_for_seamless_clip(
881 flip_horz_scan_dir,
882 recout_skip_h,
883 surf_size_h / vpc_div,
884 orthogonal_rotation ? data->taps.v_taps_c : data->taps.h_taps_c,
885 orthogonal_rotation ? data->ratios.vert_c : data->ratios.horz_c,
886 orthogonal_rotation ? &data->inits.v_c : &data->inits.h_c,
887 &data->viewport_c.x,
888 &data->viewport_c.width);
889 adjust_vp_and_init_for_seamless_clip(
890 flip_vert_scan_dir,
891 recout_skip_v,
892 surf_size_v,
893 orthogonal_rotation ? data->taps.h_taps : data->taps.v_taps,
894 orthogonal_rotation ? data->ratios.horz : data->ratios.vert,
895 orthogonal_rotation ? &data->inits.h : &data->inits.v,
896 &data->viewport.y,
897 &data->viewport.height);
898 adjust_vp_and_init_for_seamless_clip(
899 flip_vert_scan_dir,
900 recout_skip_v,
901 surf_size_v / vpc_div,
902 orthogonal_rotation ? data->taps.h_taps_c : data->taps.v_taps_c,
903 orthogonal_rotation ? data->ratios.horz_c : data->ratios.vert_c,
904 orthogonal_rotation ? &data->inits.h_c : &data->inits.v_c,
905 &data->viewport_c.y,
906 &data->viewport_c.height);
b2d0a103
DL		 907
908 /* Interlaced inits based on final vert inits */
eb0e5154
DL		 909 data->inits.v_bot = dc_fixpt_add(data->inits.v, data->ratios.vert);
910 data->inits.v_c_bot = dc_fixpt_add(data->inits.v_c, data->ratios.vert_c);
1fbd2cfc 911
b2d0a103
DL		 912}
913
914bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
4562236b 915{
3be5262e 916 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
4fa086b9 917 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
b2d0a103 918 bool res = false;
5d4b05dd 919 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
4562236b
HW		 920 /* Important: scaling ratio calculation requires pixel format,
921 * lb depth calculation requires recout and taps require scaling ratios.
b2d0a103 922 * Inits require viewport, taps, ratios and recout of split pipe
4562236b 923 */
6702a9ac 924 pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface(
3be5262e 925 pipe_ctx->plane_state->format);
b2d0a103
DL		 926
927 calculate_scaling_ratios(pipe_ctx);
4562236b 928
b2d0a103 929 calculate_viewport(pipe_ctx);
4562236b 930
6702a9ac 931 if (pipe_ctx->plane_res.scl_data.viewport.height < 16 || pipe_ctx->plane_res.scl_data.viewport.width < 16)
4562236b
HW		 932 return false;
933
9b6067c0 934 calculate_recout(pipe_ctx);
4562236b
HW		 935
936 /**
937 * Setting line buffer pixel depth to 24bpp yields banding
938 * on certain displays, such as the Sharp 4k
939 */
6702a9ac 940 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
4562236b 941
199e458a 942 pipe_ctx->plane_res.scl_data.recout.x += timing->h_border_left;
58bb0e63 943 pipe_ctx->plane_res.scl_data.recout.y += timing->v_border_top;
199e458a 944
58bb0e63
AJ		 945 pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right;
946 pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable + timing->v_border_top + timing->v_border_bottom;
1b6c8067 947
4562236b 948 /* Taps calculations */
d94585a0
YHL		 949 if (pipe_ctx->plane_res.xfm != NULL)
950 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
951 pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
952
953 if (pipe_ctx->plane_res.dpp != NULL)
954 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
955 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
4562236b
HW		 956 if (!res) {
957 /* Try 24 bpp linebuffer */
6702a9ac 958 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP;
4562236b 959
1b6c8067
BL		 960 if (pipe_ctx->plane_res.xfm != NULL)
961 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
962 pipe_ctx->plane_res.xfm,
963 &pipe_ctx->plane_res.scl_data,
964 &plane_state->scaling_quality);
965
966 if (pipe_ctx->plane_res.dpp != NULL)
967 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
968 pipe_ctx->plane_res.dpp,
969 &pipe_ctx->plane_res.scl_data,
970 &plane_state->scaling_quality);
4562236b
HW		 971 }
972
b2d0a103 973 if (res)
1fbd2cfc 974 /* May need to re-check lb size after this in some obscure scenario */
9b6067c0 975 calculate_inits_and_adj_vp(pipe_ctx);
b2d0a103 976
1296423b 977 DC_LOG_SCALER(
4562236b
HW		 978 "%s: Viewport:\nheight:%d width:%d x:%d "
979 "y:%d\n dst_rect:\nheight:%d width:%d x:%d "
980 "y:%d\n",
981 __func__,
6702a9ac
HW		 982 pipe_ctx->plane_res.scl_data.viewport.height,
983 pipe_ctx->plane_res.scl_data.viewport.width,
984 pipe_ctx->plane_res.scl_data.viewport.x,
985 pipe_ctx->plane_res.scl_data.viewport.y,
3be5262e
HW		 986 plane_state->dst_rect.height,
987 plane_state->dst_rect.width,
988 plane_state->dst_rect.x,
989 plane_state->dst_rect.y);
4562236b
HW		 990
991 return res;
992}
993
994
995enum dc_status resource_build_scaling_params_for_context(
fb3466a4 996 const struct dc *dc,
608ac7bb 997 struct dc_state *context)
4562236b
HW		 998{
999 int i;
1000
1001 for (i = 0; i < MAX_PIPES; i++) {
3be5262e 1002 if (context->res_ctx.pipe_ctx[i].plane_state != NULL &&
4562236b 1003 context->res_ctx.pipe_ctx[i].stream != NULL)
b2d0a103 1004 if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i]))
f84a8161 1005 return DC_FAIL_SCALING;
4562236b
HW		 1006 }
1007
1008 return DC_OK;
1009}
1010
a2b8659d
TC		 1011struct pipe_ctx *find_idle_secondary_pipe(
1012 struct resource_context *res_ctx,
1013 const struct resource_pool *pool)
4562236b
HW		 1014{
1015 int i;
1016 struct pipe_ctx *secondary_pipe = NULL;
1017
1018 /*
1019 * search backwards for the second pipe to keep pipe
1020 * assignment more consistent
1021 */
1022
a2b8659d 1023 for (i = pool->pipe_count - 1; i >= 0; i--) {
4562236b
HW		 1024 if (res_ctx->pipe_ctx[i].stream == NULL) {
1025 secondary_pipe = &res_ctx->pipe_ctx[i];
1026 secondary_pipe->pipe_idx = i;
1027 break;
1028 }
1029 }
1030
1031
1032 return secondary_pipe;
1033}
1034
1035struct pipe_ctx *resource_get_head_pipe_for_stream(
1036 struct resource_context *res_ctx,
0971c40e 1037 struct dc_stream_state *stream)
4562236b
HW		 1038{
1039 int i;
a2b8659d 1040 for (i = 0; i < MAX_PIPES; i++) {
4562236b 1041 if (res_ctx->pipe_ctx[i].stream == stream &&
1dc90497 1042 !res_ctx->pipe_ctx[i].top_pipe) {
4562236b
HW		 1043 return &res_ctx->pipe_ctx[i];
1044 break;
1045 }
1046 }
1047 return NULL;
1048}
1049
19f89e23
AG		 1050static struct pipe_ctx *resource_get_tail_pipe_for_stream(
1051 struct resource_context *res_ctx,
1052 struct dc_stream_state *stream)
1053{
1054 struct pipe_ctx *head_pipe, *tail_pipe;
1055 head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
1056
1057 if (!head_pipe)
1058 return NULL;
1059
1060 tail_pipe = head_pipe->bottom_pipe;
1061
1062 while (tail_pipe) {
1063 head_pipe = tail_pipe;
1064 tail_pipe = tail_pipe->bottom_pipe;
1065 }
1066
1067 return head_pipe;
1068}
1069
4562236b 1070/*
ab2541b6
AC		 1071 * A free_pipe for a stream is defined here as a pipe
1072 * that has no surface attached yet
4562236b 1073 */
ab2541b6 1074static struct pipe_ctx *acquire_free_pipe_for_stream(
608ac7bb 1075 struct dc_state *context,
a2b8659d 1076 const struct resource_pool *pool,
0971c40e 1077 struct dc_stream_state *stream)
4562236b
HW		 1078{
1079 int i;
745cc746 1080 struct resource_context *res_ctx = &context->res_ctx;
4562236b
HW		 1081
1082 struct pipe_ctx *head_pipe = NULL;
1083
1084 /* Find head pipe, which has the back end set up*/
1085
1086 head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
1087
e41ab030 1088 if (!head_pipe) {
4562236b 1089 ASSERT(0);
e41ab030
HW		 1090 return NULL;
1091 }
4562236b 1092
3be5262e 1093 if (!head_pipe->plane_state)
4562236b
HW		 1094 return head_pipe;
1095
1096 /* Re-use pipe already acquired for this stream if available*/
a2b8659d 1097 for (i = pool->pipe_count - 1; i >= 0; i--) {
4562236b 1098 if (res_ctx->pipe_ctx[i].stream == stream &&
3be5262e 1099 !res_ctx->pipe_ctx[i].plane_state) {
4562236b
HW		 1100 return &res_ctx->pipe_ctx[i];
1101 }
1102 }
1103
1104 /*
1105 * At this point we have no re-useable pipe for this stream and we need
1106 * to acquire an idle one to satisfy the request
1107 */
1108
a2b8659d 1109 if (!pool->funcs->acquire_idle_pipe_for_layer)
4562236b
HW		 1110 return NULL;
1111
a2b8659d 1112 return pool->funcs->acquire_idle_pipe_for_layer(context, pool, stream);
4562236b
HW		 1113
1114}
1115
dc37a9a0 1116#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
0f9a536f
DL		 1117static int acquire_first_split_pipe(
1118 struct resource_context *res_ctx,
1119 const struct resource_pool *pool,
0971c40e 1120 struct dc_stream_state *stream)
0f9a536f
DL		 1121{
1122 int i;
1123
1124 for (i = 0; i < pool->pipe_count; i++) {
1125 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
1126
1127 if (pipe_ctx->top_pipe &&
3be5262e 1128 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state) {
0f9a536f
DL		 1129 pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;
1130 if (pipe_ctx->bottom_pipe)
1131 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;
1132
1133 memset(pipe_ctx, 0, sizeof(*pipe_ctx));
6b670fa9 1134 pipe_ctx->stream_res.tg = pool->timing_generators[i];
8feabd03 1135 pipe_ctx->plane_res.hubp = pool->hubps[i];
86a66c4e 1136 pipe_ctx->plane_res.ipp = pool->ipps[i];
d94585a0 1137 pipe_ctx->plane_res.dpp = pool->dpps[i];
a6a6cb34 1138 pipe_ctx->stream_res.opp = pool->opps[i];
e07f541f 1139 pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst;
0f9a536f 1140 pipe_ctx->pipe_idx = i;
0f9a536f
DL		 1141
1142 pipe_ctx->stream = stream;
1143 return i;
1144 }
1145 }
1146 return -1;
1147}
1148#endif
1149
19f89e23
AG		 1150bool dc_add_plane_to_context(
1151 const struct dc *dc,
0971c40e 1152 struct dc_stream_state *stream,
19f89e23 1153 struct dc_plane_state *plane_state,
608ac7bb 1154 struct dc_state *context)
4562236b
HW		 1155{
1156 int i;
19f89e23
AG		 1157 struct resource_pool *pool = dc->res_pool;
1158 struct pipe_ctx *head_pipe, *tail_pipe, *free_pipe;
ab2541b6 1159 struct dc_stream_status *stream_status = NULL;
4562236b 1160
19f89e23
AG		 1161 for (i = 0; i < context->stream_count; i++)
1162 if (context->streams[i] == stream) {
1163 stream_status = &context->stream_status[i];
1164 break;
1165 }
1166 if (stream_status == NULL) {
1167 dm_error("Existing stream not found; failed to attach surface!\n");
1168 return false;
1169 }
1170
4562236b 1171
19f89e23
AG		 1172 if (stream_status->plane_count == MAX_SURFACE_NUM) {
1173 dm_error("Surface: can not attach plane_state %p! Maximum is: %d\n",
1174 plane_state, MAX_SURFACE_NUM);
4562236b
HW		 1175 return false;
1176 }
1177
19f89e23
AG		 1178 head_pipe = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
1179
1180 if (!head_pipe) {
1181 dm_error("Head pipe not found for stream_state %p !\n", stream);
1182 return false;
1183 }
1184
00737c59
EB		 1185 tail_pipe = resource_get_tail_pipe_for_stream(&context->res_ctx, stream);
1186 ASSERT(tail_pipe);
1187
19f89e23
AG		 1188 free_pipe = acquire_free_pipe_for_stream(context, pool, stream);
1189
dc37a9a0 1190#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
19f89e23
AG		 1191 if (!free_pipe) {
1192 int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
1193 if (pipe_idx >= 0)
1194 free_pipe = &context->res_ctx.pipe_ctx[pipe_idx];
1195 }
1196#endif
abb4986e 1197 if (!free_pipe)
19f89e23 1198 return false;
19f89e23 1199
abb4986e
AJ		 1200 /* retain new surfaces */
1201 dc_plane_state_retain(plane_state);
19f89e23
AG		 1202 free_pipe->plane_state = plane_state;
1203
1204 if (head_pipe != free_pipe) {
19f89e23 1205 free_pipe->stream_res.tg = tail_pipe->stream_res.tg;
9aef1a31 1206 free_pipe->stream_res.abm = tail_pipe->stream_res.abm;
19f89e23
AG		 1207 free_pipe->stream_res.opp = tail_pipe->stream_res.opp;
1208 free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc;
1209 free_pipe->stream_res.audio = tail_pipe->stream_res.audio;
1210 free_pipe->clock_source = tail_pipe->clock_source;
1211 free_pipe->top_pipe = tail_pipe;
1212 tail_pipe->bottom_pipe = free_pipe;
1213 }
1214
1215 /* assign new surfaces*/
1216 stream_status->plane_states[stream_status->plane_count] = plane_state;
1217
1218 stream_status->plane_count++;
1219
1220 return true;
1221}
1222
1223bool dc_remove_plane_from_context(
1224 const struct dc *dc,
1225 struct dc_stream_state *stream,
1226 struct dc_plane_state *plane_state,
608ac7bb 1227 struct dc_state *context)
19f89e23
AG		 1228{
1229 int i;
1230 struct dc_stream_status *stream_status = NULL;
1231 struct resource_pool *pool = dc->res_pool;
1232
ab2541b6 1233 for (i = 0; i < context->stream_count; i++)
4fa086b9 1234 if (context->streams[i] == stream) {
ab2541b6 1235 stream_status = &context->stream_status[i];
4562236b
HW		 1236 break;
1237 }
19f89e23 1238
ab2541b6 1239 if (stream_status == NULL) {
19f89e23 1240 dm_error("Existing stream not found; failed to remove plane.\n");
4562236b
HW		 1241 return false;
1242 }
1243
19f89e23
AG		 1244 /* release pipe for plane*/
1245 for (i = pool->pipe_count - 1; i >= 0; i--) {
1246 struct pipe_ctx *pipe_ctx;
4562236b 1247
19f89e23
AG		 1248 if (context->res_ctx.pipe_ctx[i].plane_state == plane_state) {
1249 pipe_ctx = &context->res_ctx.pipe_ctx[i];
4562236b 1250
19f89e23
AG		 1251 if (pipe_ctx->top_pipe)
1252 pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;
4562236b 1253
19f89e23
AG		 1254 /* Second condition is to avoid setting NULL to top pipe
1255 * of tail pipe making it look like head pipe in subsequent
1256 * deletes
1257 */
1258 if (pipe_ctx->bottom_pipe && pipe_ctx->top_pipe)
1259 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;
4562236b 1260
19f89e23
AG		 1261 /*
1262 * For head pipe detach surfaces from pipe for tail
1263 * pipe just zero it out
1264 */
1265 if (!pipe_ctx->top_pipe) {
1266 pipe_ctx->plane_state = NULL;
1267 pipe_ctx->bottom_pipe = NULL;
1268 } else {
1269 memset(pipe_ctx, 0, sizeof(*pipe_ctx));
1270 }
4562236b 1271 }
19f89e23 1272 }
4562236b 1273
4562236b 1274
19f89e23
AG		 1275 for (i = 0; i < stream_status->plane_count; i++) {
1276 if (stream_status->plane_states[i] == plane_state) {
1277
1278 dc_plane_state_release(stream_status->plane_states[i]);
1279 break;
4562236b 1280 }
19f89e23 1281 }
4562236b 1282
19f89e23
AG		 1283 if (i == stream_status->plane_count) {
1284 dm_error("Existing plane_state not found; failed to detach it!\n");
1285 return false;
4562236b
HW		 1286 }
1287
19f89e23 1288 stream_status->plane_count--;
4562236b 1289
abb4986e
AJ		 1290 /* Start at the plane we've just released, and move all the planes one index forward to "trim" the array */
1291 for (; i < stream_status->plane_count; i++)
19f89e23
AG		 1292 stream_status->plane_states[i] = stream_status->plane_states[i + 1];
1293
1294 stream_status->plane_states[stream_status->plane_count] = NULL;
1295
1296 return true;
1297}
1298
1299bool dc_rem_all_planes_for_stream(
1300 const struct dc *dc,
1301 struct dc_stream_state *stream,
608ac7bb 1302 struct dc_state *context)
19f89e23
AG		 1303{
1304 int i, old_plane_count;
1305 struct dc_stream_status *stream_status = NULL;
1306 struct dc_plane_state *del_planes[MAX_SURFACE_NUM] = { 0 };
1307
1308 for (i = 0; i < context->stream_count; i++)
1309 if (context->streams[i] == stream) {
1310 stream_status = &context->stream_status[i];
1311 break;
1312 }
1313
1314 if (stream_status == NULL) {
1315 dm_error("Existing stream %p not found!\n", stream);
1316 return false;
1317 }
1318
1319 old_plane_count = stream_status->plane_count;
1320
1321 for (i = 0; i < old_plane_count; i++)
1322 del_planes[i] = stream_status->plane_states[i];
1323
1324 for (i = 0; i < old_plane_count; i++)
1325 if (!dc_remove_plane_from_context(dc, stream, del_planes[i], context))
1326 return false;
1327
1328 return true;
1329}
1330
1331static bool add_all_planes_for_stream(
1332 const struct dc *dc,
1333 struct dc_stream_state *stream,
1334 const struct dc_validation_set set[],
1335 int set_count,
608ac7bb 1336 struct dc_state *context)
19f89e23
AG		 1337{
1338 int i, j;
1339
1340 for (i = 0; i < set_count; i++)
1341 if (set[i].stream == stream)
1342 break;
1343
1344 if (i == set_count) {
1345 dm_error("Stream %p not found in set!\n", stream);
1346 return false;
1347 }
4562236b 1348
19f89e23
AG		 1349 for (j = 0; j < set[i].plane_count; j++)
1350 if (!dc_add_plane_to_context(dc, stream, set[i].plane_states[j], context))
1351 return false;
4562236b
HW		 1352
1353 return true;
1354}
1355
19f89e23
AG		 1356bool dc_add_all_planes_for_stream(
1357 const struct dc *dc,
1358 struct dc_stream_state *stream,
1359 struct dc_plane_state * const *plane_states,
1360 int plane_count,
608ac7bb 1361 struct dc_state *context)
19f89e23
AG		 1362{
1363 struct dc_validation_set set;
1364 int i;
1365
1366 set.stream = stream;
1367 set.plane_count = plane_count;
1368
1369 for (i = 0; i < plane_count; i++)
1370 set.plane_states[i] = plane_states[i];
1371
1372 return add_all_planes_for_stream(dc, stream, &set, 1, context);
1373}
1374
1375
6b622181
JP		 1376static bool is_hdr_static_meta_changed(struct dc_stream_state *cur_stream,
1377 struct dc_stream_state *new_stream)
1378{
1379 if (cur_stream == NULL)
1380 return true;
1381
1382 if (memcmp(&cur_stream->hdr_static_metadata,
1383 &new_stream->hdr_static_metadata,
1384 sizeof(struct dc_info_packet)) != 0)
1385 return true;
1386
1387 return false;
1388}
4562236b 1389
1336926f
A		 1390static bool is_vsc_info_packet_changed(struct dc_stream_state *cur_stream,
1391 struct dc_stream_state *new_stream)
1392{
1393 if (cur_stream == NULL)
1394 return true;
1395
1396 if (memcmp(&cur_stream->vsc_infopacket,
1397 &new_stream->vsc_infopacket,
1398 sizeof(struct dc_info_packet)) != 0)
1399 return true;
1400
1401 return false;
1402}
1403
0971c40e
HW		 1404static bool is_timing_changed(struct dc_stream_state *cur_stream,
1405 struct dc_stream_state *new_stream)
4562236b
HW		 1406{
1407 if (cur_stream == NULL)
1408 return true;
1409
1410 /* If sink pointer changed, it means this is a hotplug, we should do
1411 * full hw setting.
1412 */
1413 if (cur_stream->sink != new_stream->sink)
1414 return true;
1415
1416 /* If output color space is changed, need to reprogram info frames */
4fa086b9 1417 if (cur_stream->output_color_space != new_stream->output_color_space)
4562236b
HW		 1418 return true;
1419
1420 return memcmp(
4fa086b9
LSL		 1421 &cur_stream->timing,
1422 &new_stream->timing,
4562236b
HW		 1423 sizeof(struct dc_crtc_timing)) != 0;
1424}
1425
1426static bool are_stream_backends_same(
0971c40e 1427 struct dc_stream_state *stream_a, struct dc_stream_state *stream_b)
4562236b
HW		 1428{
1429 if (stream_a == stream_b)
1430 return true;
1431
1432 if (stream_a == NULL || stream_b == NULL)
1433 return false;
1434
1435 if (is_timing_changed(stream_a, stream_b))
1436 return false;
1437
6b622181
JP		 1438 if (is_hdr_static_meta_changed(stream_a, stream_b))
1439 return false;
1440
1e7e86c4
ST		 1441 if (stream_a->dpms_off != stream_b->dpms_off)
1442 return false;
1443
1336926f
A		 1444 if (is_vsc_info_packet_changed(stream_a, stream_b))
1445 return false;
1446
4562236b
HW		 1447 return true;
1448}
1449
2119aa17
DF		 1450/**
1451 * dc_is_stream_unchanged() - Compare two stream states for equivalence.
1452 *
1453 * Checks if there a difference between the two states
1454 * that would require a mode change.
1455 *
1456 * Does not compare cursor position or attributes.
1457 */
d54d29db 1458bool dc_is_stream_unchanged(
0971c40e 1459 struct dc_stream_state *old_stream, struct dc_stream_state *stream)
4562236b 1460{
4562236b 1461
ab2541b6
AC		 1462 if (!are_stream_backends_same(old_stream, stream))
1463 return false;
4562236b
HW		 1464
1465 return true;
1466}
1467
2119aa17
DF		 1468/**
1469 * dc_is_stream_scaling_unchanged() - Compare scaling rectangles of two streams.
1470 */
9a5d9c48
LSL		 1471bool dc_is_stream_scaling_unchanged(
1472 struct dc_stream_state *old_stream, struct dc_stream_state *stream)
1473{
1474 if (old_stream == stream)
1475 return true;
1476
1477 if (old_stream == NULL || stream == NULL)
1478 return false;
1479
1480 if (memcmp(&old_stream->src,
1481 &stream->src,
1482 sizeof(struct rect)) != 0)
1483 return false;
1484
1485 if (memcmp(&old_stream->dst,
1486 &stream->dst,
1487 sizeof(struct rect)) != 0)
1488 return false;
1489
1490 return true;
1491}
1492
1dc90497 1493static void update_stream_engine_usage(
4562236b 1494 struct resource_context *res_ctx,
a2b8659d 1495 const struct resource_pool *pool,
1dc90497
AG		 1496 struct stream_encoder *stream_enc,
1497 bool acquired)
4562236b
HW		 1498{
1499 int i;
1500
a2b8659d
TC		 1501 for (i = 0; i < pool->stream_enc_count; i++) {
1502 if (pool->stream_enc[i] == stream_enc)
1dc90497 1503 res_ctx->is_stream_enc_acquired[i] = acquired;
4562236b
HW		 1504 }
1505}
1506
1507/* TODO: release audio object */
4176664b 1508void update_audio_usage(
4562236b 1509 struct resource_context *res_ctx,
a2b8659d 1510 const struct resource_pool *pool,
1dc90497
AG		 1511 struct audio *audio,
1512 bool acquired)
4562236b
HW		 1513{
1514 int i;
a2b8659d
TC		 1515 for (i = 0; i < pool->audio_count; i++) {
1516 if (pool->audios[i] == audio)
1dc90497 1517 res_ctx->is_audio_acquired[i] = acquired;
4562236b
HW		 1518 }
1519}
1520
1521static int acquire_first_free_pipe(
1522 struct resource_context *res_ctx,
a2b8659d 1523 const struct resource_pool *pool,
0971c40e 1524 struct dc_stream_state *stream)
4562236b
HW		 1525{
1526 int i;
1527
a2b8659d 1528 for (i = 0; i < pool->pipe_count; i++) {
4562236b
HW		 1529 if (!res_ctx->pipe_ctx[i].stream) {
1530 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
1531
6b670fa9 1532 pipe_ctx->stream_res.tg = pool->timing_generators[i];
86a66c4e 1533 pipe_ctx->plane_res.mi = pool->mis[i];
8feabd03 1534 pipe_ctx->plane_res.hubp = pool->hubps[i];
86a66c4e
HW		 1535 pipe_ctx->plane_res.ipp = pool->ipps[i];
1536 pipe_ctx->plane_res.xfm = pool->transforms[i];
d94585a0 1537 pipe_ctx->plane_res.dpp = pool->dpps[i];
a6a6cb34 1538 pipe_ctx->stream_res.opp = pool->opps[i];
bc373a89
RL		 1539 if (pool->dpps[i])
1540 pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst;
4562236b
HW		 1541 pipe_ctx->pipe_idx = i;
1542
ff5ef992 1543
4562236b
HW		 1544 pipe_ctx->stream = stream;
1545 return i;
1546 }
1547 }
1548 return -1;
1549}
1550
1551static struct stream_encoder *find_first_free_match_stream_enc_for_link(
1552 struct resource_context *res_ctx,
a2b8659d 1553 const struct resource_pool *pool,
0971c40e 1554 struct dc_stream_state *stream)
4562236b
HW		 1555{
1556 int i;
1557 int j = -1;
d0778ebf 1558 struct dc_link *link = stream->sink->link;
4562236b 1559
a2b8659d 1560 for (i = 0; i < pool->stream_enc_count; i++) {
4562236b 1561 if (!res_ctx->is_stream_enc_acquired[i] &&
a2b8659d 1562 pool->stream_enc[i]) {
4562236b
HW		 1563 /* Store first available for MST second display
1564 * in daisy chain use case */
1565 j = i;
a2b8659d 1566 if (pool->stream_enc[i]->id ==
4562236b 1567 link->link_enc->preferred_engine)
a2b8659d 1568 return pool->stream_enc[i];
4562236b
HW		 1569 }
1570 }
1571
1572 /*
1573 * below can happen in cases when stream encoder is acquired:
1574 * 1) for second MST display in chain, so preferred engine already
1575 * acquired;
1576 * 2) for another link, which preferred engine already acquired by any
1577 * MST configuration.
1578 *
1579 * If signal is of DP type and preferred engine not found, return last available
1580 *
1581 * TODO - This is just a patch up and a generic solution is
1582 * required for non DP connectors.
1583 */
1584
cae50a43 1585 if (j >= 0 && link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT)
a2b8659d 1586 return pool->stream_enc[j];
4562236b
HW		 1587
1588 return NULL;
1589}
1590
a2b8659d
TC		 1591static struct audio *find_first_free_audio(
1592 struct resource_context *res_ctx,
cfb071f7
CL		 1593 const struct resource_pool *pool,
1594 enum engine_id id)
4562236b
HW		 1595{
1596 int i;
66bfd4fd
CL		 1597 for (i = 0; i < pool->audio_count; i++) {
1598 if ((res_ctx->is_audio_acquired[i] == false) && (res_ctx->is_stream_enc_acquired[i] == true)) {
cfb071f7
CL		 1599 /*we have enough audio endpoint, find the matching inst*/
1600 if (id != i)
1601 continue;
1602
66bfd4fd 1603 return pool->audios[i];
4562236b 1604 }
66bfd4fd
CL		 1605 }
1606 /*not found the matching one, first come first serve*/
1607 for (i = 0; i < pool->audio_count; i++) {
1608 if (res_ctx->is_audio_acquired[i] == false) {
1609 return pool->audios[i];
4176664b
CL		 1610 }
1611 }
4562236b
HW		 1612 return 0;
1613}
1614
4562236b 1615bool resource_is_stream_unchanged(
608ac7bb 1616 struct dc_state *old_context, struct dc_stream_state *stream)
4562236b 1617{
ab2541b6 1618 int i;
4562236b 1619
ab2541b6 1620 for (i = 0; i < old_context->stream_count; i++) {
0971c40e 1621 struct dc_stream_state *old_stream = old_context->streams[i];
4562236b 1622
ab2541b6 1623 if (are_stream_backends_same(old_stream, stream))
4562236b 1624 return true;
4562236b
HW		 1625 }
1626
1627 return false;
1628}
1629
2119aa17
DF		 1630/**
1631 * dc_add_stream_to_ctx() - Add a new dc_stream_state to a dc_state.
1632 */
13ab1b44 1633enum dc_status dc_add_stream_to_ctx(
1dc90497 1634 struct dc *dc,
608ac7bb 1635 struct dc_state *new_ctx,
1dc90497
AG		 1636 struct dc_stream_state *stream)
1637{
1dc90497 1638 enum dc_status res;
eb9714a2 1639 DC_LOGGER_INIT(dc->ctx->logger);
1dc90497 1640
ece4147f 1641 if (new_ctx->stream_count >= dc->res_pool->timing_generator_count) {
eb9714a2 1642 DC_LOG_WARNING("Max streams reached, can't add stream %p !\n", stream);
1dc90497
AG		 1643 return DC_ERROR_UNEXPECTED;
1644 }
1645
1646 new_ctx->streams[new_ctx->stream_count] = stream;
1647 dc_stream_retain(stream);
1648 new_ctx->stream_count++;
1649
1650 res = dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream);
1651 if (res != DC_OK)
eb9714a2 1652 DC_LOG_WARNING("Adding stream %p to context failed with err %d!\n", stream, res);
1dc90497 1653
13ab1b44 1654 return res;
1dc90497
AG		 1655}
1656
2119aa17
DF		 1657/**
1658 * dc_remove_stream_from_ctx() - Remove a stream from a dc_state.
1659 */
62c933f9 1660enum dc_status dc_remove_stream_from_ctx(
1dc90497 1661 struct dc *dc,
608ac7bb 1662 struct dc_state *new_ctx,
1dc90497
AG		 1663 struct dc_stream_state *stream)
1664{
19f89e23 1665 int i;
1dc90497
AG		 1666 struct dc_context *dc_ctx = dc->ctx;
1667 struct pipe_ctx *del_pipe = NULL;
1668
19f89e23 1669 /* Release primary pipe */
1dc90497 1670 for (i = 0; i < MAX_PIPES; i++) {
19f89e23
AG		 1671 if (new_ctx->res_ctx.pipe_ctx[i].stream == stream &&
1672 !new_ctx->res_ctx.pipe_ctx[i].top_pipe) {
1dc90497
AG		 1673 del_pipe = &new_ctx->res_ctx.pipe_ctx[i];
1674
19f89e23
AG		 1675 ASSERT(del_pipe->stream_res.stream_enc);
1676 update_stream_engine_usage(
1677 &new_ctx->res_ctx,
1dc90497 1678 dc->res_pool,
19f89e23
AG		 1679 del_pipe->stream_res.stream_enc,
1680 false);
1dc90497
AG		 1681
1682 if (del_pipe->stream_res.audio)
1683 update_audio_usage(
1684 &new_ctx->res_ctx,
1685 dc->res_pool,
1686 del_pipe->stream_res.audio,
1687 false);
1688
9d0dcecd
HW		 1689 resource_unreference_clock_source(&new_ctx->res_ctx,
1690 dc->res_pool,
1691 del_pipe->clock_source);
1692
e56ae556
NC		 1693 if (dc->res_pool->funcs->remove_stream_from_ctx)
1694 dc->res_pool->funcs->remove_stream_from_ctx(dc, new_ctx, stream);
1695
1dc90497 1696 memset(del_pipe, 0, sizeof(*del_pipe));
19f89e23
AG		 1697
1698 break;
1dc90497
AG		 1699 }
1700 }
1701
1702 if (!del_pipe) {
1703 DC_ERROR("Pipe not found for stream %p !\n", stream);
1704 return DC_ERROR_UNEXPECTED;
1705 }
1706
1707 for (i = 0; i < new_ctx->stream_count; i++)
1708 if (new_ctx->streams[i] == stream)
1709 break;
1710
1711 if (new_ctx->streams[i] != stream) {
1712 DC_ERROR("Context doesn't have stream %p !\n", stream);
1713 return DC_ERROR_UNEXPECTED;
1714 }
1715
1716 dc_stream_release(new_ctx->streams[i]);
1717 new_ctx->stream_count--;
1718
1dc90497
AG		 1719 /* Trim back arrays */
1720 for (; i < new_ctx->stream_count; i++) {
1721 new_ctx->streams[i] = new_ctx->streams[i + 1];
1722 new_ctx->stream_status[i] = new_ctx->stream_status[i + 1];
1723 }
1724
1725 new_ctx->streams[new_ctx->stream_count] = NULL;
1726 memset(
1727 &new_ctx->stream_status[new_ctx->stream_count],
1728 0,
1729 sizeof(new_ctx->stream_status[0]));
1730
1731 return DC_OK;
1732}
1733
0971c40e
HW		 1734static struct dc_stream_state *find_pll_sharable_stream(
1735 struct dc_stream_state *stream_needs_pll,
608ac7bb 1736 struct dc_state *context)
4562236b 1737{
ab2541b6 1738 int i;
4562236b 1739
ab2541b6 1740 for (i = 0; i < context->stream_count; i++) {
0971c40e 1741 struct dc_stream_state *stream_has_pll = context->streams[i];
4562236b 1742
ab2541b6
AC		 1743 /* We are looking for non dp, non virtual stream */
1744 if (resource_are_streams_timing_synchronizable(
1745 stream_needs_pll, stream_has_pll)
1746 && !dc_is_dp_signal(stream_has_pll->signal)
d0778ebf 1747 && stream_has_pll->sink->link->connector_signal
ab2541b6
AC		 1748 != SIGNAL_TYPE_VIRTUAL)
1749 return stream_has_pll;
4562236b 1750
4562236b
HW		 1751 }
1752
1753 return NULL;
1754}
1755
1756static int get_norm_pix_clk(const struct dc_crtc_timing *timing)
1757{
1758 uint32_t pix_clk = timing->pix_clk_khz;
1759 uint32_t normalized_pix_clk = pix_clk;
1760
1761 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
1762 pix_clk /= 2;
cc4d99b8
CL		 1763 if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) {
1764 switch (timing->display_color_depth) {
1765 case COLOR_DEPTH_888:
1766 normalized_pix_clk = pix_clk;
1767 break;
1768 case COLOR_DEPTH_101010:
1769 normalized_pix_clk = (pix_clk * 30) / 24;
1770 break;
1771 case COLOR_DEPTH_121212:
1772 normalized_pix_clk = (pix_clk * 36) / 24;
4562236b 1773 break;
cc4d99b8
CL		 1774 case COLOR_DEPTH_161616:
1775 normalized_pix_clk = (pix_clk * 48) / 24;
4562236b 1776 break;
cc4d99b8
CL		 1777 default:
1778 ASSERT(0);
4562236b 1779 break;
cc4d99b8 1780 }
4562236b 1781 }
4562236b
HW		 1782 return normalized_pix_clk;
1783}
1784
0971c40e 1785static void calculate_phy_pix_clks(struct dc_stream_state *stream)
4562236b 1786{
9345d987
AG		 1787 /* update actual pixel clock on all streams */
1788 if (dc_is_hdmi_signal(stream->signal))
1789 stream->phy_pix_clk = get_norm_pix_clk(
4fa086b9 1790 &stream->timing);
9345d987
AG		 1791 else
1792 stream->phy_pix_clk =
4fa086b9 1793 stream->timing.pix_clk_khz;
39c03e00
CL		 1794
1795 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1796 stream->phy_pix_clk *= 2;
4562236b
HW		 1797}
1798
1799enum dc_status resource_map_pool_resources(
fb3466a4 1800 const struct dc *dc,
608ac7bb 1801 struct dc_state *context,
1dc90497 1802 struct dc_stream_state *stream)
4562236b 1803{
a2b8659d 1804 const struct resource_pool *pool = dc->res_pool;
1dc90497
AG		 1805 int i;
1806 struct dc_context *dc_ctx = dc->ctx;
1807 struct pipe_ctx *pipe_ctx = NULL;
1808 int pipe_idx = -1;
4562236b 1809
1dc90497
AG		 1810 /* TODO Check if this is needed */
1811 /*if (!resource_is_stream_unchanged(old_context, stream)) {
430ef426 1812 if (stream != NULL && old_context->streams[i] != NULL) {
4b679bc3 1813 stream->bit_depth_params =
430ef426
DL		 1814 old_context->streams[i]->bit_depth_params;
1815 stream->clamping = old_context->streams[i]->clamping;
a2b8659d
TC		 1816 continue;
1817 }
4b679bc3 1818 }
1dc90497 1819 */
7e2fe319 1820
08e1c28d
YMM		 1821 calculate_phy_pix_clks(stream);
1822
1dc90497
AG		 1823 /* acquire new resources */
1824 pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream);
8c737fcc 1825
dc37a9a0 1826#ifdef CONFIG_DRM_AMD_DC_DCN1_0
1dc90497 1827 if (pipe_idx < 0)
13ab1b44 1828 pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
94c6d735 1829#endif
13ab1b44 1830
c5b38aec 1831 if (pipe_idx < 0 || context->res_ctx.pipe_ctx[pipe_idx].stream_res.tg == NULL)
1dc90497
AG		 1832 return DC_NO_CONTROLLER_RESOURCE;
1833
1834 pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
1835
1836 pipe_ctx->stream_res.stream_enc =
1837 find_first_free_match_stream_enc_for_link(
1838 &context->res_ctx, pool, stream);
1839
1840 if (!pipe_ctx->stream_res.stream_enc)
1841 return DC_NO_STREAM_ENG_RESOURCE;
1842
1843 update_stream_engine_usage(
1844 &context->res_ctx, pool,
1845 pipe_ctx->stream_res.stream_enc,
1846 true);
1847
1848 /* TODO: Add check if ASIC support and EDID audio */
1849 if (!stream->sink->converter_disable_audio &&
1850 dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&
1851 stream->audio_info.mode_count) {
1852 pipe_ctx->stream_res.audio = find_first_free_audio(
cfb071f7 1853 &context->res_ctx, pool, pipe_ctx->stream_res.stream_enc->id);
1dc90497
AG		 1854
1855 /*
1856 * Audio assigned in order first come first get.
1857 * There are asics which has number of audio
1858 * resources less then number of pipes
1859 */
1860 if (pipe_ctx->stream_res.audio)
1861 update_audio_usage(&context->res_ctx, pool,
1862 pipe_ctx->stream_res.audio, true);
1863 }
268cadbd 1864
9aef1a31
S		 1865 /* Add ABM to the resource if on EDP */
1866 if (pipe_ctx->stream && dc_is_embedded_signal(pipe_ctx->stream->signal))
1867 pipe_ctx->stream_res.abm = pool->abm;
1868
1dc90497
AG		 1869 for (i = 0; i < context->stream_count; i++)
1870 if (context->streams[i] == stream) {
1871 context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst;
0f0bdca5 1872 context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.stream_enc->id;
1dc90497
AG		 1873 return DC_OK;
1874 }
4562236b 1875
1dc90497
AG		 1876 DC_ERROR("Stream %p not found in new ctx!\n", stream);
1877 return DC_ERROR_UNEXPECTED;
1878}
4562236b 1879
2119aa17
DF		 1880/**
1881 * dc_resource_state_copy_construct_current() - Creates a new dc_state from existing state
1882 * Is a shallow copy. Increments refcounts on existing streams and planes.
1883 * @dc: copy out of dc->current_state
1884 * @dst_ctx: copy into this
1885 */
f36cc577 1886void dc_resource_state_copy_construct_current(
1dc90497 1887 const struct dc *dc,
608ac7bb 1888 struct dc_state *dst_ctx)
1dc90497 1889{
f36cc577 1890 dc_resource_state_copy_construct(dc->current_state, dst_ctx);
1dc90497
AG		 1891}
1892
ab8db3e1
AG		 1893
1894void dc_resource_state_construct(
1895 const struct dc *dc,
1896 struct dc_state *dst_ctx)
1897{
84e7fc05 1898 dst_ctx->dccg = dc->res_pool->clk_mgr;
ab8db3e1
AG		 1899}
1900
2119aa17
DF		 1901/**
1902 * dc_validate_global_state() - Determine if HW can support a given state
1903 * Checks HW resource availability and bandwidth requirement.
1904 * @dc: dc struct for this driver
1905 * @new_ctx: state to be validated
1906 *
1907 * Return: DC_OK if the result can be programmed. Otherwise, an error code.
1908 */
e750d56d 1909enum dc_status dc_validate_global_state(
1dc90497 1910 struct dc *dc,
608ac7bb 1911 struct dc_state *new_ctx)
4562236b 1912{
1dc90497 1913 enum dc_status result = DC_ERROR_UNEXPECTED;
1dc90497 1914 int i, j;
4562236b 1915
e41ab030
HW		 1916 if (!new_ctx)
1917 return DC_ERROR_UNEXPECTED;
1918
d596e5d0 1919 if (dc->res_pool->funcs->validate_global) {
ada8ce15
HW		 1920 result = dc->res_pool->funcs->validate_global(dc, new_ctx);
1921 if (result != DC_OK)
1922 return result;
d596e5d0 1923 }
4562236b 1924
e41ab030 1925 for (i = 0; i < new_ctx->stream_count; i++) {
1dc90497
AG		 1926 struct dc_stream_state *stream = new_ctx->streams[i];
1927
1928 for (j = 0; j < dc->res_pool->pipe_count; j++) {
1929 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[j];
1930
1931 if (pipe_ctx->stream != stream)
1932 continue;
1933
74eac5f3
SSC		 1934 if (dc->res_pool->funcs->get_default_swizzle_mode &&
1935 pipe_ctx->plane_state &&
1936 pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) {
1937 result = dc->res_pool->funcs->get_default_swizzle_mode(pipe_ctx->plane_state);
1938 if (result != DC_OK)
1939 return result;
1940 }
1941
1dc90497
AG		 1942 /* Switch to dp clock source only if there is
1943 * no non dp stream that shares the same timing
1944 * with the dp stream.
1945 */
1946 if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
1947 !find_pll_sharable_stream(stream, new_ctx)) {
1948
9d0dcecd 1949 resource_unreference_clock_source(
1dc90497
AG		 1950 &new_ctx->res_ctx,
1951 dc->res_pool,
9d0dcecd 1952 pipe_ctx->clock_source);
4a629536 1953
1dc90497
AG		 1954 pipe_ctx->clock_source = dc->res_pool->dp_clock_source;
1955 resource_reference_clock_source(
1956 &new_ctx->res_ctx,
1957 dc->res_pool,
1958 pipe_ctx->clock_source);
1959 }
1960 }
1961 }
1962
1dc90497
AG		 1963 result = resource_build_scaling_params_for_context(dc, new_ctx);
1964
1965 if (result == DC_OK)
1966 if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx))
1967 result = DC_FAIL_BANDWIDTH_VALIDATE;
1968
1969 return result;
4562236b
HW		 1970}
1971
6e4d6bee 1972static void patch_gamut_packet_checksum(
e09b6473 1973 struct dc_info_packet *gamut_packet)
4562236b 1974{
4562236b 1975 /* For gamut we recalc checksum */
6e4d6bee 1976 if (gamut_packet->valid) {
4562236b
HW		 1977 uint8_t chk_sum = 0;
1978 uint8_t *ptr;
1979 uint8_t i;
1980
4562236b 1981 /*start of the Gamut data. */
6e4d6bee 1982 ptr = &gamut_packet->sb[3];
4562236b 1983
6e4d6bee 1984 for (i = 0; i <= gamut_packet->sb[1]; i++)
4562236b
HW		 1985 chk_sum += ptr[i];
1986
6e4d6bee 1987 gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum);
1646a6fe 1988 }
4562236b
HW		 1989}
1990
1991static void set_avi_info_frame(
e09b6473 1992 struct dc_info_packet *info_packet,
4562236b
HW		 1993 struct pipe_ctx *pipe_ctx)
1994{
0971c40e 1995 struct dc_stream_state *stream = pipe_ctx->stream;
4562236b 1996 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
4562236b
HW		 1997 uint32_t pixel_encoding = 0;
1998 enum scanning_type scan_type = SCANNING_TYPE_NODATA;
1999 enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA;
2000 bool itc = false;
50e27654 2001 uint8_t itc_value = 0;
4562236b 2002 uint8_t cn0_cn1 = 0;
50e27654 2003 unsigned int cn0_cn1_value = 0;
4562236b
HW		 2004 uint8_t *check_sum = NULL;
2005 uint8_t byte_index = 0;
754e3673 2006 union hdmi_info_packet hdmi_info;
50e27654 2007 union display_content_support support = {0};
4fa086b9 2008 unsigned int vic = pipe_ctx->stream->timing.vic;
15e17335 2009 enum dc_timing_3d_format format;
4562236b 2010
754e3673
AK		 2011 memset(&hdmi_info, 0, sizeof(union hdmi_info_packet));
2012
4fa086b9 2013 color_space = pipe_ctx->stream->output_color_space;
e5f2038e 2014 if (color_space == COLOR_SPACE_UNKNOWN)
4fa086b9 2015 color_space = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ?
e5f2038e 2016 COLOR_SPACE_SRGB:COLOR_SPACE_YCBCR709;
4562236b
HW		 2017
2018 /* Initialize header */
e09b6473 2019 hdmi_info.bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI;
4562236b
HW		 2020 /* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall
2021 * not be used in HDMI 2.0 (Section 10.1) */
e09b6473
AK		 2022 hdmi_info.bits.header.version = 2;
2023 hdmi_info.bits.header.length = HDMI_AVI_INFOFRAME_SIZE;
4562236b
HW		 2024
2025 /*
2026 * IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built
2027 * according to HDMI 2.0 spec (Section 10.1)
2028 */
2029
4fa086b9 2030 switch (stream->timing.pixel_encoding) {
4562236b
HW		 2031 case PIXEL_ENCODING_YCBCR422:
2032 pixel_encoding = 1;
2033 break;
2034
2035 case PIXEL_ENCODING_YCBCR444:
2036 pixel_encoding = 2;
2037 break;
2038 case PIXEL_ENCODING_YCBCR420:
2039 pixel_encoding = 3;
2040 break;
2041
2042 case PIXEL_ENCODING_RGB:
2043 default:
2044 pixel_encoding = 0;
2045 }
2046
2047 /* Y0_Y1_Y2 : The pixel encoding */
2048 /* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */
e09b6473 2049 hdmi_info.bits.Y0_Y1_Y2 = pixel_encoding;
4562236b
HW		 2050
2051 /* A0 = 1 Active Format Information valid */
e09b6473 2052 hdmi_info.bits.A0 = ACTIVE_FORMAT_VALID;
4562236b
HW		 2053
2054 /* B0, B1 = 3; Bar info data is valid */
e09b6473 2055 hdmi_info.bits.B0_B1 = BAR_INFO_BOTH_VALID;
4562236b 2056
e09b6473 2057 hdmi_info.bits.SC0_SC1 = PICTURE_SCALING_UNIFORM;
4562236b
HW		 2058
2059 /* S0, S1 : Underscan / Overscan */
2060 /* TODO: un-hardcode scan type */
2061 scan_type = SCANNING_TYPE_UNDERSCAN;
e09b6473 2062 hdmi_info.bits.S0_S1 = scan_type;
4562236b
HW		 2063
2064 /* C0, C1 : Colorimetry */
8fde5884 2065 if (color_space == COLOR_SPACE_YCBCR709 ||
15e17335 2066 color_space == COLOR_SPACE_YCBCR709_LIMITED)
e09b6473 2067 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU709;
8fde5884
CL		 2068 else if (color_space == COLOR_SPACE_YCBCR601 ||
2069 color_space == COLOR_SPACE_YCBCR601_LIMITED)
e09b6473 2070 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU601;
8fde5884 2071 else {
e09b6473 2072 hdmi_info.bits.C0_C1 = COLORIMETRY_NO_DATA;
8fde5884 2073 }
534db198 2074 if (color_space == COLOR_SPACE_2020_RGB_FULLRANGE ||
8fde5884
CL		 2075 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE ||
2076 color_space == COLOR_SPACE_2020_YCBCR) {
e09b6473
AK		 2077 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR;
2078 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
534db198 2079 } else if (color_space == COLOR_SPACE_ADOBERGB) {
e09b6473
AK		 2080 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB;
2081 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
534db198
AZ		 2082 }
2083
4562236b 2084 /* TODO: un-hardcode aspect ratio */
4fa086b9 2085 aspect = stream->timing.aspect_ratio;
4562236b
HW		 2086
2087 switch (aspect) {
2088 case ASPECT_RATIO_4_3:
2089 case ASPECT_RATIO_16_9:
e09b6473 2090 hdmi_info.bits.M0_M1 = aspect;
4562236b
HW		 2091 break;
2092
2093 case ASPECT_RATIO_NO_DATA:
2094 case ASPECT_RATIO_64_27:
2095 case ASPECT_RATIO_256_135:
2096 default:
e09b6473 2097 hdmi_info.bits.M0_M1 = 0;
4562236b
HW		 2098 }
2099
2100 /* Active Format Aspect ratio - same as Picture Aspect Ratio. */
e09b6473 2101 hdmi_info.bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE;
4562236b
HW		 2102
2103 /* TODO: un-hardcode cn0_cn1 and itc */
50e27654 2104
4562236b 2105 cn0_cn1 = 0;
50e27654
ZF		 2106 cn0_cn1_value = 0;
2107
2108 itc = true;
2109 itc_value = 1;
2110
4fa086b9 2111 support = stream->sink->edid_caps.content_support;
4562236b
HW		 2112
2113 if (itc) {
50e27654
ZF		 2114 if (!support.bits.valid_content_type) {
2115 cn0_cn1_value = 0;
2116 } else {
2117 if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GRAPHICS) {
2118 if (support.bits.graphics_content == 1) {
2119 cn0_cn1_value = 0;
2120 }
2121 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_PHOTO) {
2122 if (support.bits.photo_content == 1) {
2123 cn0_cn1_value = 1;
2124 } else {
2125 cn0_cn1_value = 0;
2126 itc_value = 0;
2127 }
2128 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_CINEMA) {
2129 if (support.bits.cinema_content == 1) {
2130 cn0_cn1_value = 2;
2131 } else {
2132 cn0_cn1_value = 0;
2133 itc_value = 0;
2134 }
2135 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GAME) {
2136 if (support.bits.game_content == 1) {
2137 cn0_cn1_value = 3;
2138 } else {
2139 cn0_cn1_value = 0;
2140 itc_value = 0;
2141 }
2142 }
2143 }
e09b6473
AK		 2144 hdmi_info.bits.CN0_CN1 = cn0_cn1_value;
2145 hdmi_info.bits.ITC = itc_value;
4562236b
HW		 2146 }
2147
2148 /* TODO : We should handle YCC quantization */
2149 /* but we do not have matrix calculation */
4fa086b9
LSL		 2150 if (stream->sink->edid_caps.qs_bit == 1 &&
2151 stream->sink->edid_caps.qy_bit == 1) {
50e27654
ZF		 2152 if (color_space == COLOR_SPACE_SRGB ||
2153 color_space == COLOR_SPACE_2020_RGB_FULLRANGE) {
e09b6473
AK		 2154 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_FULL_RANGE;
2155 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_FULL_RANGE;
50e27654
ZF		 2156 } else if (color_space == COLOR_SPACE_SRGB_LIMITED ||
2157 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE) {
e09b6473
AK		 2158 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_LIMITED_RANGE;
2159 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
50e27654 2160 } else {
e09b6473
AK		 2161 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
2162 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
50e27654 2163 }
4562236b 2164 } else {
e09b6473
AK		 2165 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
2166 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
4562236b 2167 }
50e27654 2168
15e17335 2169 ///VIC
4fa086b9 2170 format = stream->timing.timing_3d_format;
15e17335
CL		 2171 /*todo, add 3DStereo support*/
2172 if (format != TIMING_3D_FORMAT_NONE) {
2173 // Based on HDMI specs hdmi vic needs to be converted to cea vic when 3D is enabled
4fa086b9 2174 switch (pipe_ctx->stream->timing.hdmi_vic) {
15e17335
CL		 2175 case 1:
2176 vic = 95;
2177 break;
2178 case 2:
2179 vic = 94;
2180 break;
2181 case 3:
2182 vic = 93;
2183 break;
2184 case 4:
2185 vic = 98;
2186 break;
2187 default:
2188 break;
2189 }
2190 }
e09b6473 2191 hdmi_info.bits.VIC0_VIC7 = vic;
4562236b
HW		 2192
2193 /* pixel repetition
2194 * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel
2195 * repetition start from 1 */
e09b6473 2196 hdmi_info.bits.PR0_PR3 = 0;
4562236b
HW		 2197
2198 /* Bar Info
2199 * barTop: Line Number of End of Top Bar.
2200 * barBottom: Line Number of Start of Bottom Bar.
2201 * barLeft: Pixel Number of End of Left Bar.
2202 * barRight: Pixel Number of Start of Right Bar. */
e09b6473
AK		 2203 hdmi_info.bits.bar_top = stream->timing.v_border_top;
2204 hdmi_info.bits.bar_bottom = (stream->timing.v_total
4fa086b9 2205 - stream->timing.v_border_bottom + 1);
e09b6473
AK		 2206 hdmi_info.bits.bar_left = stream->timing.h_border_left;
2207 hdmi_info.bits.bar_right = (stream->timing.h_total
4fa086b9 2208 - stream->timing.h_border_right + 1);
4562236b
HW		 2209
2210 /* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */
e09b6473 2211 check_sum = &hdmi_info.packet_raw_data.sb[0];
e8d726b7 2212
3e183c5f 2213 *check_sum = HDMI_INFOFRAME_TYPE_AVI + HDMI_AVI_INFOFRAME_SIZE + 2;
4562236b 2214
3e183c5f 2215 for (byte_index = 1; byte_index <= HDMI_AVI_INFOFRAME_SIZE; byte_index++)
e09b6473 2216 *check_sum += hdmi_info.packet_raw_data.sb[byte_index];
4562236b
HW		 2217
2218 /* one byte complement */
2219 *check_sum = (uint8_t) (0x100 - *check_sum);
2220
2221 /* Store in hw_path_mode */
e09b6473
AK		 2222 info_packet->hb0 = hdmi_info.packet_raw_data.hb0;
2223 info_packet->hb1 = hdmi_info.packet_raw_data.hb1;
2224 info_packet->hb2 = hdmi_info.packet_raw_data.hb2;
4562236b 2225
e09b6473
AK		 2226 for (byte_index = 0; byte_index < sizeof(hdmi_info.packet_raw_data.sb); byte_index++)
2227 info_packet->sb[byte_index] = hdmi_info.packet_raw_data.sb[byte_index];
4562236b
HW		 2228
2229 info_packet->valid = true;
2230}
2231
6e4d6bee 2232static void set_vendor_info_packet(
e09b6473 2233 struct dc_info_packet *info_packet,
0971c40e 2234 struct dc_stream_state *stream)
4562236b
HW		 2235{
2236 uint32_t length = 0;
2237 bool hdmi_vic_mode = false;
2238 uint8_t checksum = 0;
2239 uint32_t i = 0;
2240 enum dc_timing_3d_format format;
15e17335
CL		 2241 // Can be different depending on packet content /*todo*/
2242 // unsigned int length = pPathMode->dolbyVision ? 24 : 5;
2243
2244 info_packet->valid = false;
4562236b 2245
4fa086b9
LSL		 2246 format = stream->timing.timing_3d_format;
2247 if (stream->view_format == VIEW_3D_FORMAT_NONE)
7f5c22d1 2248 format = TIMING_3D_FORMAT_NONE;
4562236b
HW		 2249
2250 /* Can be different depending on packet content */
2251 length = 5;
2252
4fa086b9
LSL		 2253 if (stream->timing.hdmi_vic != 0
2254 && stream->timing.h_total >= 3840
2255 && stream->timing.v_total >= 2160)
4562236b
HW		 2256 hdmi_vic_mode = true;
2257
2258 /* According to HDMI 1.4a CTS, VSIF should be sent
2259 * for both 3D stereo and HDMI VIC modes.
2260 * For all other modes, there is no VSIF sent. */
2261
2262 if (format == TIMING_3D_FORMAT_NONE && !hdmi_vic_mode)
2263 return;
2264
2265 /* 24bit IEEE Registration identifier (0x000c03). LSB first. */
2266 info_packet->sb[1] = 0x03;
2267 info_packet->sb[2] = 0x0C;
2268 info_packet->sb[3] = 0x00;
2269
2270 /*PB4: 5 lower bytes = 0 (reserved). 3 higher bits = HDMI_Video_Format.
2271 * The value for HDMI_Video_Format are:
2272 * 0x0 (0b000) - No additional HDMI video format is presented in this
2273 * packet
2274 * 0x1 (0b001) - Extended resolution format present. 1 byte of HDMI_VIC
2275 * parameter follows
2276 * 0x2 (0b010) - 3D format indication present. 3D_Structure and
2277 * potentially 3D_Ext_Data follows
2278 * 0x3..0x7 (0b011..0b111) - reserved for future use */
2279 if (format != TIMING_3D_FORMAT_NONE)
2280 info_packet->sb[4] = (2 << 5);
2281 else if (hdmi_vic_mode)
2282 info_packet->sb[4] = (1 << 5);
2283
2284 /* PB5: If PB4 claims 3D timing (HDMI_Video_Format = 0x2):
2285 * 4 lower bites = 0 (reserved). 4 higher bits = 3D_Structure.
2286 * The value for 3D_Structure are:
2287 * 0x0 - Frame Packing
2288 * 0x1 - Field Alternative
2289 * 0x2 - Line Alternative
2290 * 0x3 - Side-by-Side (full)
2291 * 0x4 - L + depth
2292 * 0x5 - L + depth + graphics + graphics-depth
2293 * 0x6 - Top-and-Bottom
2294 * 0x7 - Reserved for future use
2295 * 0x8 - Side-by-Side (Half)
2296 * 0x9..0xE - Reserved for future use
2297 * 0xF - Not used */
2298 switch (format) {
2299 case TIMING_3D_FORMAT_HW_FRAME_PACKING:
2300 case TIMING_3D_FORMAT_SW_FRAME_PACKING:
2301 info_packet->sb[5] = (0x0 << 4);
2302 break;
2303
2304 case TIMING_3D_FORMAT_SIDE_BY_SIDE:
2305 case TIMING_3D_FORMAT_SBS_SW_PACKED:
2306 info_packet->sb[5] = (0x8 << 4);
2307 length = 6;
2308 break;
2309
2310 case TIMING_3D_FORMAT_TOP_AND_BOTTOM:
2311 case TIMING_3D_FORMAT_TB_SW_PACKED:
2312 info_packet->sb[5] = (0x6 << 4);
2313 break;
2314
2315 default:
2316 break;
2317 }
2318
2319 /*PB5: If PB4 is set to 0x1 (extended resolution format)
2320 * fill PB5 with the correct HDMI VIC code */
2321 if (hdmi_vic_mode)
4fa086b9 2322 info_packet->sb[5] = stream->timing.hdmi_vic;
4562236b
HW		 2323
2324 /* Header */
3e183c5f 2325 info_packet->hb0 = HDMI_INFOFRAME_TYPE_VENDOR; /* VSIF packet type. */
4562236b
HW		 2326 info_packet->hb1 = 0x01; /* Version */
2327
2328 /* 4 lower bits = Length, 4 higher bits = 0 (reserved) */
2329 info_packet->hb2 = (uint8_t) (length);
2330
2331 /* Calculate checksum */
2332 checksum = 0;
2333 checksum += info_packet->hb0;
2334 checksum += info_packet->hb1;
2335 checksum += info_packet->hb2;
2336
2337 for (i = 1; i <= length; i++)
2338 checksum += info_packet->sb[i];
2339
2340 info_packet->sb[0] = (uint8_t) (0x100 - checksum);
2341
2342 info_packet->valid = true;
2343}
2344
6e4d6bee 2345static void set_spd_info_packet(
e09b6473 2346 struct dc_info_packet *info_packet,
0971c40e 2347 struct dc_stream_state *stream)
4562236b
HW		 2348{
2349 /* SPD info packet for FreeSync */
2350
4562236b
HW		 2351 /* Check if Freesync is supported. Return if false. If true,
2352 * set the corresponding bit in the info packet
2353 */
98e6436d 2354 if (!stream->vrr_infopacket.valid)
4562236b
HW		 2355 return;
2356
98e6436d 2357 *info_packet = stream->vrr_infopacket;
4562236b
HW		 2358}
2359
1646a6fe 2360static void set_hdr_static_info_packet(
e09b6473 2361 struct dc_info_packet *info_packet,
0971c40e 2362 struct dc_stream_state *stream)
1646a6fe 2363{
0eeef690 2364 /* HDR Static Metadata info packet for HDR10 */
1646a6fe 2365
a10dc97a
KK		 2366 if (!stream->hdr_static_metadata.valid ||
2367 stream->use_dynamic_meta)
10bff005
YS		 2368 return;
2369
0eeef690 2370 *info_packet = stream->hdr_static_metadata;
1646a6fe
AW		 2371}
2372
6e4d6bee 2373static void set_vsc_info_packet(
e09b6473 2374 struct dc_info_packet *info_packet,
0971c40e 2375 struct dc_stream_state *stream)
4562236b 2376{
1336926f 2377 if (!stream->vsc_infopacket.valid)
4562236b
HW		 2378 return;
2379
1336926f 2380 *info_packet = stream->vsc_infopacket;
4562236b
HW		 2381}
2382
f36cc577 2383void dc_resource_state_destruct(struct dc_state *context)
4562236b
HW		 2384{
2385 int i, j;
2386
ab2541b6 2387 for (i = 0; i < context->stream_count; i++) {
3be5262e
HW		 2388 for (j = 0; j < context->stream_status[i].plane_count; j++)
2389 dc_plane_state_release(
2390 context->stream_status[i].plane_states[j]);
4562236b 2391
3be5262e 2392 context->stream_status[i].plane_count = 0;
4fa086b9 2393 dc_stream_release(context->streams[i]);
ab2541b6 2394 context->streams[i] = NULL;
4562236b
HW		 2395 }
2396}
2397
f36cc577 2398void dc_resource_state_copy_construct(
608ac7bb
JZ		 2399 const struct dc_state *src_ctx,
2400 struct dc_state *dst_ctx)
4562236b
HW		 2401{
2402 int i, j;
8ee5702a 2403 struct kref refcount = dst_ctx->refcount;
4562236b
HW		 2404
2405 *dst_ctx = *src_ctx;
2406
a2b8659d 2407 for (i = 0; i < MAX_PIPES; i++) {
4562236b
HW		 2408 struct pipe_ctx *cur_pipe = &dst_ctx->res_ctx.pipe_ctx[i];
2409
2410 if (cur_pipe->top_pipe)
2411 cur_pipe->top_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
2412
2413 if (cur_pipe->bottom_pipe)
2414 cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
2415
2416 }
2417
ab2541b6 2418 for (i = 0; i < dst_ctx->stream_count; i++) {
4fa086b9 2419 dc_stream_retain(dst_ctx->streams[i]);
3be5262e
HW		 2420 for (j = 0; j < dst_ctx->stream_status[i].plane_count; j++)
2421 dc_plane_state_retain(
2422 dst_ctx->stream_status[i].plane_states[j]);
4562236b 2423 }
9a3afbb3
AG		 2424
2425 /* context refcount should not be overridden */
8ee5702a 2426 dst_ctx->refcount = refcount;
9a3afbb3 2427
4562236b
HW		 2428}
2429
2430struct clock_source *dc_resource_find_first_free_pll(
a2b8659d
TC		 2431 struct resource_context *res_ctx,
2432 const struct resource_pool *pool)
4562236b
HW		 2433{
2434 int i;
2435
a2b8659d 2436 for (i = 0; i < pool->clk_src_count; ++i) {
4562236b 2437 if (res_ctx->clock_source_ref_count[i] == 0)
a2b8659d 2438 return pool->clock_sources[i];
4562236b
HW		 2439 }
2440
2441 return NULL;
2442}
2443
2444void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
2445{
2446 enum signal_type signal = SIGNAL_TYPE_NONE;
96c50c0d 2447 struct encoder_info_frame *info = &pipe_ctx->stream_res.encoder_info_frame;
4562236b
HW		 2448
2449 /* default all packets to invalid */
6e4d6bee
TC		 2450 info->avi.valid = false;
2451 info->gamut.valid = false;
2452 info->vendor.valid = false;
630e3573 2453 info->spd.valid = false;
6e4d6bee
TC		 2454 info->hdrsmd.valid = false;
2455 info->vsc.valid = false;
4562236b
HW		 2456
2457 signal = pipe_ctx->stream->signal;
2458
2459 /* HDMi and DP have different info packets*/
2460 if (dc_is_hdmi_signal(signal)) {
6e4d6bee
TC		 2461 set_avi_info_frame(&info->avi, pipe_ctx);
2462
2463 set_vendor_info_packet(&info->vendor, pipe_ctx->stream);
2464
2465 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2466
56ef6ed9 2467 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
6e4d6bee 2468
a33fa99d 2469 } else if (dc_is_dp_signal(signal)) {
6e4d6bee
TC		 2470 set_vsc_info_packet(&info->vsc, pipe_ctx->stream);
2471
2472 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2473
56ef6ed9 2474 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
a33fa99d 2475 }
4562236b 2476
6e4d6bee 2477 patch_gamut_packet_checksum(&info->gamut);
4562236b
HW		 2478}
2479
2480enum dc_status resource_map_clock_resources(
fb3466a4 2481 const struct dc *dc,
608ac7bb 2482 struct dc_state *context,
1dc90497 2483 struct dc_stream_state *stream)
4562236b 2484{
4562236b 2485 /* acquire new resources */
1dc90497
AG		 2486 const struct resource_pool *pool = dc->res_pool;
2487 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(
2488 &context->res_ctx, stream);
ab2541b6 2489
1dc90497
AG		 2490 if (!pipe_ctx)
2491 return DC_ERROR_UNEXPECTED;
4562236b 2492
1dc90497
AG		 2493 if (dc_is_dp_signal(pipe_ctx->stream->signal)
2494 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)
2495 pipe_ctx->clock_source = pool->dp_clock_source;
2496 else {
2497 pipe_ctx->clock_source = NULL;
4562236b 2498
1dc90497 2499 if (!dc->config.disable_disp_pll_sharing)
4ed4e51b 2500 pipe_ctx->clock_source = resource_find_used_clk_src_for_sharing(
1dc90497
AG		 2501 &context->res_ctx,
2502 pipe_ctx);
4562236b 2503
1dc90497
AG		 2504 if (pipe_ctx->clock_source == NULL)
2505 pipe_ctx->clock_source =
2506 dc_resource_find_first_free_pll(
2507 &context->res_ctx,
2508 pool);
2509 }
4562236b 2510
1dc90497
AG		 2511 if (pipe_ctx->clock_source == NULL)
2512 return DC_NO_CLOCK_SOURCE_RESOURCE;
4562236b 2513
1dc90497
AG		 2514 resource_reference_clock_source(
2515 &context->res_ctx, pool,
2516 pipe_ctx->clock_source);
4562236b
HW		 2517
2518 return DC_OK;
2519}
2520
2521/*
2522 * Note: We need to disable output if clock sources change,
2523 * since bios does optimization and doesn't apply if changing
2524 * PHY when not already disabled.
2525 */
2526bool pipe_need_reprogram(
2527 struct pipe_ctx *pipe_ctx_old,
2528 struct pipe_ctx *pipe_ctx)
2529{
cfe4645e
DL		 2530 if (!pipe_ctx_old->stream)
2531 return false;
2532
4562236b
HW		 2533 if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink)
2534 return true;
2535
2536 if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal)
2537 return true;
2538
afaacef4 2539 if (pipe_ctx_old->stream_res.audio != pipe_ctx->stream_res.audio)
4562236b
HW		 2540 return true;
2541
2542 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source
2543 && pipe_ctx_old->stream != pipe_ctx->stream)
2544 return true;
2545
8e9c4c8c 2546 if (pipe_ctx_old->stream_res.stream_enc != pipe_ctx->stream_res.stream_enc)
4562236b
HW		 2547 return true;
2548
2549 if (is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2550 return true;
2551
6b622181
JP		 2552 if (is_hdr_static_meta_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2553 return true;
4562236b 2554
1e7e86c4
ST		 2555 if (pipe_ctx_old->stream->dpms_off != pipe_ctx->stream->dpms_off)
2556 return true;
2557
1336926f
A		 2558 if (is_vsc_info_packet_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2559 return true;
2560
4562236b
HW		 2561 return false;
2562}
529cad0f 2563
0971c40e 2564void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream,
529cad0f
DW		 2565 struct bit_depth_reduction_params *fmt_bit_depth)
2566{
4fa086b9 2567 enum dc_dither_option option = stream->dither_option;
529cad0f 2568 enum dc_pixel_encoding pixel_encoding =
4fa086b9 2569 stream->timing.pixel_encoding;
529cad0f
DW		 2570
2571 memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth));
2572
603767f9
TC		 2573 if (option == DITHER_OPTION_DEFAULT) {
2574 switch (stream->timing.display_color_depth) {
2575 case COLOR_DEPTH_666:
2576 option = DITHER_OPTION_SPATIAL6;
2577 break;
2578 case COLOR_DEPTH_888:
2579 option = DITHER_OPTION_SPATIAL8;
2580 break;
2581 case COLOR_DEPTH_101010:
2582 option = DITHER_OPTION_SPATIAL10;
2583 break;
2584 default:
2585 option = DITHER_OPTION_DISABLE;
2586 }
2587 }
2588
529cad0f
DW		 2589 if (option == DITHER_OPTION_DISABLE)
2590 return;
2591
2592 if (option == DITHER_OPTION_TRUN6) {
2593 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2594 fmt_bit_depth->flags.TRUNCATE_DEPTH = 0;
2595 } else if (option == DITHER_OPTION_TRUN8 ||
2596 option == DITHER_OPTION_TRUN8_SPATIAL6 ||
2597 option == DITHER_OPTION_TRUN8_FM6) {
2598 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2599 fmt_bit_depth->flags.TRUNCATE_DEPTH = 1;
2600 } else if (option == DITHER_OPTION_TRUN10 ||
2601 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
2602 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
2603 option == DITHER_OPTION_TRUN10_FM8 ||
2604 option == DITHER_OPTION_TRUN10_FM6 ||
2605 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2606 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2607 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2608 }
2609
2610 /* special case - Formatter can only reduce by 4 bits at most.
2611 * When reducing from 12 to 6 bits,
2612 * HW recommends we use trunc with round mode
2613 * (if we did nothing, trunc to 10 bits would be used)
2614 * note that any 12->10 bit reduction is ignored prior to DCE8,
2615 * as the input was 10 bits.
2616 */
2617 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2618 option == DITHER_OPTION_SPATIAL6 ||
2619 option == DITHER_OPTION_FM6) {
2620 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2621 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2622 fmt_bit_depth->flags.TRUNCATE_MODE = 1;
2623 }
2624
2625 /* spatial dither
2626 * note that spatial modes 1-3 are never used
2627 */
2628 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2629 option == DITHER_OPTION_SPATIAL6 ||
2630 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
2631 option == DITHER_OPTION_TRUN8_SPATIAL6) {
2632 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2633 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 0;
2634 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2635 fmt_bit_depth->flags.RGB_RANDOM =
2636 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2637 } else if (option == DITHER_OPTION_SPATIAL8_FRAME_RANDOM ||
2638 option == DITHER_OPTION_SPATIAL8 ||
2639 option == DITHER_OPTION_SPATIAL8_FM6 ||
2640 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
2641 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2642 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2643 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 1;
2644 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2645 fmt_bit_depth->flags.RGB_RANDOM =
2646 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2647 } else if (option == DITHER_OPTION_SPATIAL10_FRAME_RANDOM ||
2648 option == DITHER_OPTION_SPATIAL10 ||
2649 option == DITHER_OPTION_SPATIAL10_FM8 ||
2650 option == DITHER_OPTION_SPATIAL10_FM6) {
2651 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2652 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 2;
2653 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2654 fmt_bit_depth->flags.RGB_RANDOM =
2655 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2656 }
2657
2658 if (option == DITHER_OPTION_SPATIAL6 ||
2659 option == DITHER_OPTION_SPATIAL8 ||
2660 option == DITHER_OPTION_SPATIAL10) {
2661 fmt_bit_depth->flags.FRAME_RANDOM = 0;
2662 } else {
2663 fmt_bit_depth->flags.FRAME_RANDOM = 1;
2664 }
2665
2666 //////////////////////
2667 //// temporal dither
2668 //////////////////////
2669 if (option == DITHER_OPTION_FM6 ||
2670 option == DITHER_OPTION_SPATIAL8_FM6 ||
2671 option == DITHER_OPTION_SPATIAL10_FM6 ||
2672 option == DITHER_OPTION_TRUN10_FM6 ||
2673 option == DITHER_OPTION_TRUN8_FM6 ||
2674 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2675 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2676 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 0;
2677 } else if (option == DITHER_OPTION_FM8 ||
2678 option == DITHER_OPTION_SPATIAL10_FM8 ||
2679 option == DITHER_OPTION_TRUN10_FM8) {
2680 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2681 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 1;
2682 } else if (option == DITHER_OPTION_FM10) {
2683 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2684 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 2;
2685 }
2686
2687 fmt_bit_depth->pixel_encoding = pixel_encoding;
2688}
9345d987 2689
62c933f9 2690enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream)
9345d987 2691{
fb3466a4 2692 struct dc *core_dc = dc;
4fa086b9 2693 struct dc_link *link = stream->sink->link;
9345d987
AG		 2694 struct timing_generator *tg = core_dc->res_pool->timing_generators[0];
2695 enum dc_status res = DC_OK;
2696
4fa086b9 2697 calculate_phy_pix_clks(stream);
9345d987 2698
4fa086b9 2699 if (!tg->funcs->validate_timing(tg, &stream->timing))
9345d987
AG		 2700 res = DC_FAIL_CONTROLLER_VALIDATE;
2701
2702 if (res == DC_OK)
2703 if (!link->link_enc->funcs->validate_output_with_stream(
4fa086b9 2704 link->link_enc, stream))
9345d987
AG		 2705 res = DC_FAIL_ENC_VALIDATE;
2706
2707 /* TODO: validate audio ASIC caps, encoder */
2708
2709 if (res == DC_OK)
4fa086b9 2710 res = dc_link_validate_mode_timing(stream,
9345d987 2711 link,
4fa086b9 2712 &stream->timing);
9345d987 2713
62c933f9 2714 return res;
9345d987 2715}
792671d7 2716
62c933f9 2717enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state)
792671d7 2718{
62c933f9
YS		 2719 enum dc_status res = DC_OK;
2720
792671d7 2721 /* TODO For now validates pixel format only */
8e7095b9 2722 if (dc->res_pool->funcs->validate_plane)
62c933f9 2723 return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps);
792671d7 2724
62c933f9 2725 return res;
792671d7 2726}
74eac5f3
SSC		 2727
2728unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format)
2729{
2730 switch (format) {
2731 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
2732 return 8;
2733 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
2734 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
2735 return 12;
2736 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
2737 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
2738 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
2739 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
2740 return 16;
2741 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
2742 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
2743 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
2744 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
2745 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
2746 return 32;
2747 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
2748 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
2749 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
2750 return 64;
2751 default:
2752 ASSERT_CRITICAL(false);
2753 return -1;
2754 }
2755}
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