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drm/amd/display: fix seq issue: turn on clock before programming afmt.
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / display / dc / core / dc_resource.c
CommitLineData
4562236b
HW		 1/*
2* Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25#include "dm_services.h"
26
27#include "resource.h"
28#include "include/irq_service_interface.h"
29#include "link_encoder.h"
30#include "stream_encoder.h"
31#include "opp.h"
32#include "timing_generator.h"
33#include "transform.h"
d94585a0 34#include "dpp.h"
5ac3d3c9 35#include "core_types.h"
4562236b 36#include "set_mode_types.h"
4562236b
HW		 37#include "virtual/virtual_stream_encoder.h"
38
39#include "dce80/dce80_resource.h"
40#include "dce100/dce100_resource.h"
41#include "dce110/dce110_resource.h"
42#include "dce112/dce112_resource.h"
ff5ef992
AD		 43#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
44#include "dcn10/dcn10_resource.h"
45#endif
2c8ad2d5 46#include "dce120/dce120_resource.h"
4562236b
HW		 47
48enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
49{
50 enum dce_version dc_version = DCE_VERSION_UNKNOWN;
51 switch (asic_id.chip_family) {
52
53 case FAMILY_CI:
4562236b
HW		 54 dc_version = DCE_VERSION_8_0;
55 break;
ebfdf0d0
AD		 56 case FAMILY_KV:
57 if (ASIC_REV_IS_KALINDI(asic_id.hw_internal_rev) ||
58 ASIC_REV_IS_BHAVANI(asic_id.hw_internal_rev) ||
59 ASIC_REV_IS_GODAVARI(asic_id.hw_internal_rev))
60 dc_version = DCE_VERSION_8_3;
61 else
62 dc_version = DCE_VERSION_8_1;
63 break;
4562236b
HW		 64 case FAMILY_CZ:
65 dc_version = DCE_VERSION_11_0;
66 break;
67
68 case FAMILY_VI:
69 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
70 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
71 dc_version = DCE_VERSION_10_0;
72 break;
73 }
74 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
b264d345
JL		 75 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
76 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
4562236b
HW		 77 dc_version = DCE_VERSION_11_2;
78 }
79 break;
2c8ad2d5
AD		 80 case FAMILY_AI:
81 dc_version = DCE_VERSION_12_0;
82 break;
ff5ef992
AD		 83#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
84 case FAMILY_RV:
85 dc_version = DCN_VERSION_1_0;
86 break;
87#endif
4562236b
HW		 88 default:
89 dc_version = DCE_VERSION_UNKNOWN;
90 break;
91 }
92 return dc_version;
93}
94
95struct resource_pool *dc_create_resource_pool(
fb3466a4 96 struct dc *dc,
4562236b
HW		 97 int num_virtual_links,
98 enum dce_version dc_version,
99 struct hw_asic_id asic_id)
100{
5ac3d3c9 101 struct resource_pool *res_pool = NULL;
4562236b
HW		 102
103 switch (dc_version) {
104 case DCE_VERSION_8_0:
7992a629
AD		 105 res_pool = dce80_create_resource_pool(
106 num_virtual_links, dc);
107 break;
ebfdf0d0 108 case DCE_VERSION_8_1:
7992a629
AD		 109 res_pool = dce81_create_resource_pool(
110 num_virtual_links, dc);
111 break;
ebfdf0d0 112 case DCE_VERSION_8_3:
7992a629 113 res_pool = dce83_create_resource_pool(
4562236b 114 num_virtual_links, dc);
5ac3d3c9 115 break;
4562236b 116 case DCE_VERSION_10_0:
5ac3d3c9 117 res_pool = dce100_create_resource_pool(
4562236b 118 num_virtual_links, dc);
5ac3d3c9 119 break;
4562236b 120 case DCE_VERSION_11_0:
5ac3d3c9 121 res_pool = dce110_create_resource_pool(
4562236b 122 num_virtual_links, dc, asic_id);
5ac3d3c9 123 break;
4562236b 124 case DCE_VERSION_11_2:
5ac3d3c9 125 res_pool = dce112_create_resource_pool(
4562236b 126 num_virtual_links, dc);
5ac3d3c9 127 break;
2c8ad2d5
AD		 128 case DCE_VERSION_12_0:
129 res_pool = dce120_create_resource_pool(
130 num_virtual_links, dc);
131 break;
ff5ef992
AD		 132
133#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
134 case DCN_VERSION_1_0:
135 res_pool = dcn10_create_resource_pool(
503a7c6f 136 num_virtual_links, dc);
ff5ef992
AD		 137 break;
138#endif
3639fa68
ZF		 139
140
4562236b
HW		 141 default:
142 break;
143 }
5ac3d3c9 144 if (res_pool != NULL) {
1515a47b 145 struct dc_firmware_info fw_info = { { 0 } };
5ac3d3c9
CL		 146
147 if (dc->ctx->dc_bios->funcs->get_firmware_info(
148 dc->ctx->dc_bios, &fw_info) == BP_RESULT_OK) {
149 res_pool->ref_clock_inKhz = fw_info.pll_info.crystal_frequency;
150 } else
151 ASSERT_CRITICAL(false);
152 }
4562236b 153
5ac3d3c9 154 return res_pool;
4562236b
HW		 155}
156
fb3466a4 157void dc_destroy_resource_pool(struct dc *dc)
4562236b
HW		 158{
159 if (dc) {
160 if (dc->res_pool)
161 dc->res_pool->funcs->destroy(&dc->res_pool);
162
d029810c 163 kfree(dc->hwseq);
4562236b
HW		 164 }
165}
166
167static void update_num_audio(
168 const struct resource_straps *straps,
169 unsigned int *num_audio,
170 struct audio_support *aud_support)
171{
b8e9eb72
CL		 172 aud_support->dp_audio = true;
173 aud_support->hdmi_audio_native = false;
174 aud_support->hdmi_audio_on_dongle = false;
175
4562236b 176 if (straps->hdmi_disable == 0) {
4562236b
HW		 177 if (straps->dc_pinstraps_audio & 0x2) {
178 aud_support->hdmi_audio_on_dongle = true;
b8e9eb72 179 aud_support->hdmi_audio_native = true;
4562236b
HW		 180 }
181 }
182
183 switch (straps->audio_stream_number) {
184 case 0: /* multi streams supported */
185 break;
186 case 1: /* multi streams not supported */
187 *num_audio = 1;
188 break;
189 default:
190 DC_ERR("DC: unexpected audio fuse!\n");
17a96033 191 }
4562236b
HW		 192}
193
194bool resource_construct(
195 unsigned int num_virtual_links,
fb3466a4 196 struct dc *dc,
4562236b
HW		 197 struct resource_pool *pool,
198 const struct resource_create_funcs *create_funcs)
199{
200 struct dc_context *ctx = dc->ctx;
201 const struct resource_caps *caps = pool->res_cap;
202 int i;
203 unsigned int num_audio = caps->num_audio;
204 struct resource_straps straps = {0};
205
206 if (create_funcs->read_dce_straps)
207 create_funcs->read_dce_straps(dc->ctx, &straps);
208
209 pool->audio_count = 0;
210 if (create_funcs->create_audio) {
211 /* find the total number of streams available via the
212 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
213 * registers (one for each pin) starting from pin 1
214 * up to the max number of audio pins.
215 * We stop on the first pin where
216 * PORT_CONNECTIVITY == 1 (as instructed by HW team).
217 */
218 update_num_audio(&straps, &num_audio, &pool->audio_support);
219 for (i = 0; i < pool->pipe_count && i < num_audio; i++) {
220 struct audio *aud = create_funcs->create_audio(ctx, i);
221
222 if (aud == NULL) {
223 DC_ERR("DC: failed to create audio!\n");
224 return false;
225 }
226
227 if (!aud->funcs->endpoint_valid(aud)) {
228 aud->funcs->destroy(&aud);
229 break;
230 }
231
232 pool->audios[i] = aud;
233 pool->audio_count++;
234 }
235 }
236
237 pool->stream_enc_count = 0;
238 if (create_funcs->create_stream_encoder) {
239 for (i = 0; i < caps->num_stream_encoder; i++) {
240 pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx);
241 if (pool->stream_enc[i] == NULL)
242 DC_ERR("DC: failed to create stream_encoder!\n");
243 pool->stream_enc_count++;
244 }
245 }
4176664b
CL		 246 dc->caps.dynamic_audio = false;
247 if (pool->audio_count < pool->stream_enc_count) {
248 dc->caps.dynamic_audio = true;
249 }
4562236b
HW		 250 for (i = 0; i < num_virtual_links; i++) {
251 pool->stream_enc[pool->stream_enc_count] =
252 virtual_stream_encoder_create(
253 ctx, ctx->dc_bios);
254 if (pool->stream_enc[pool->stream_enc_count] == NULL) {
255 DC_ERR("DC: failed to create stream_encoder!\n");
256 return false;
257 }
258 pool->stream_enc_count++;
259 }
260
261 dc->hwseq = create_funcs->create_hwseq(ctx);
262
263 return true;
264}
265
266
21e67d4d 267void resource_unreference_clock_source(
4562236b 268 struct resource_context *res_ctx,
a2b8659d 269 const struct resource_pool *pool,
4a629536 270 struct clock_source *clock_source)
4562236b
HW		 271{
272 int i;
4a629536 273
a2b8659d 274 for (i = 0; i < pool->clk_src_count; i++) {
4a629536 275 if (pool->clock_sources[i] != clock_source)
4562236b
HW		 276 continue;
277
278 res_ctx->clock_source_ref_count[i]--;
279
4562236b
HW		 280 break;
281 }
282
21e67d4d 283 if (pool->dp_clock_source == clock_source)
4562236b 284 res_ctx->dp_clock_source_ref_count--;
4562236b
HW		 285}
286
287void resource_reference_clock_source(
288 struct resource_context *res_ctx,
a2b8659d 289 const struct resource_pool *pool,
4562236b
HW		 290 struct clock_source *clock_source)
291{
292 int i;
a2b8659d
TC		 293 for (i = 0; i < pool->clk_src_count; i++) {
294 if (pool->clock_sources[i] != clock_source)
4562236b
HW		 295 continue;
296
297 res_ctx->clock_source_ref_count[i]++;
298 break;
299 }
300
a2b8659d 301 if (pool->dp_clock_source == clock_source)
4562236b
HW		 302 res_ctx->dp_clock_source_ref_count++;
303}
304
305bool resource_are_streams_timing_synchronizable(
0971c40e
HW		 306 struct dc_stream_state *stream1,
307 struct dc_stream_state *stream2)
4562236b 308{
4fa086b9 309 if (stream1->timing.h_total != stream2->timing.h_total)
4562236b
HW		 310 return false;
311
4fa086b9 312 if (stream1->timing.v_total != stream2->timing.v_total)
4562236b
HW		 313 return false;
314
4fa086b9
LSL		 315 if (stream1->timing.h_addressable
316 != stream2->timing.h_addressable)
4562236b
HW		 317 return false;
318
4fa086b9
LSL		 319 if (stream1->timing.v_addressable
320 != stream2->timing.v_addressable)
4562236b
HW		 321 return false;
322
4fa086b9
LSL		 323 if (stream1->timing.pix_clk_khz
324 != stream2->timing.pix_clk_khz)
4562236b
HW		 325 return false;
326
327 if (stream1->phy_pix_clk != stream2->phy_pix_clk
7e2fe319
CL		 328 && (!dc_is_dp_signal(stream1->signal)
329 || !dc_is_dp_signal(stream2->signal)))
4562236b
HW		 330 return false;
331
332 return true;
333}
334
335static bool is_sharable_clk_src(
336 const struct pipe_ctx *pipe_with_clk_src,
337 const struct pipe_ctx *pipe)
338{
339 if (pipe_with_clk_src->clock_source == NULL)
340 return false;
341
342 if (pipe_with_clk_src->stream->signal == SIGNAL_TYPE_VIRTUAL)
343 return false;
344
345 if (dc_is_dp_signal(pipe_with_clk_src->stream->signal))
346 return false;
347
348 if (dc_is_hdmi_signal(pipe_with_clk_src->stream->signal)
349 && dc_is_dvi_signal(pipe->stream->signal))
350 return false;
351
352 if (dc_is_hdmi_signal(pipe->stream->signal)
353 && dc_is_dvi_signal(pipe_with_clk_src->stream->signal))
354 return false;
355
356 if (!resource_are_streams_timing_synchronizable(
357 pipe_with_clk_src->stream, pipe->stream))
358 return false;
359
360 return true;
361}
362
363struct clock_source *resource_find_used_clk_src_for_sharing(
364 struct resource_context *res_ctx,
365 struct pipe_ctx *pipe_ctx)
366{
367 int i;
368
369 for (i = 0; i < MAX_PIPES; i++) {
370 if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx))
371 return res_ctx->pipe_ctx[i].clock_source;
372 }
373
374 return NULL;
375}
376
377static enum pixel_format convert_pixel_format_to_dalsurface(
378 enum surface_pixel_format surface_pixel_format)
379{
380 enum pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
381
382 switch (surface_pixel_format) {
383 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
384 dal_pixel_format = PIXEL_FORMAT_INDEX8;
385 break;
386 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
387 dal_pixel_format = PIXEL_FORMAT_RGB565;
388 break;
389 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
390 dal_pixel_format = PIXEL_FORMAT_RGB565;
391 break;
392 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
393 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
394 break;
8693049a 395 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
4562236b
HW		 396 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
397 break;
398 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
399 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
400 break;
401 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
402 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
403 break;
404 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
405 dal_pixel_format = PIXEL_FORMAT_ARGB2101010_XRBIAS;
406 break;
407 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
408 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
409 dal_pixel_format = PIXEL_FORMAT_FP16;
410 break;
411 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
4562236b 412 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
87449a90 413 dal_pixel_format = PIXEL_FORMAT_420BPP8;
4562236b 414 break;
ffbcd19a
VP		 415 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
416 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
87449a90 417 dal_pixel_format = PIXEL_FORMAT_420BPP10;
ffbcd19a 418 break;
4562236b
HW		 419 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
420 default:
421 dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
422 break;
423 }
424 return dal_pixel_format;
425}
426
427static void rect_swap_helper(struct rect *rect)
428{
429 uint32_t temp = 0;
430
431 temp = rect->height;
432 rect->height = rect->width;
433 rect->width = temp;
434
435 temp = rect->x;
436 rect->x = rect->y;
437 rect->y = temp;
438}
439
b2d0a103 440static void calculate_viewport(struct pipe_ctx *pipe_ctx)
4562236b 441{
3be5262e 442 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 443 const struct dc_stream_state *stream = pipe_ctx->stream;
6702a9ac 444 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
3be5262e 445 struct rect surf_src = plane_state->src_rect;
1fbd2cfc 446 struct rect clip = { 0 };
87449a90
AK		 447 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
448 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
1fbd2cfc 449 bool pri_split = pipe_ctx->bottom_pipe &&
3be5262e 450 pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state;
1fbd2cfc 451 bool sec_split = pipe_ctx->top_pipe &&
3be5262e 452 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
4562236b 453
7f5c22d1
VP		 454 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE ||
455 stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) {
7b779c99
VP		 456 pri_split = false;
457 sec_split = false;
458 }
86006a7f 459
3be5262e
HW		 460 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
461 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
86006a7f
DL		 462 rect_swap_helper(&surf_src);
463
4562236b
HW		 464 /* The actual clip is an intersection between stream
465 * source and surface clip
466 */
3be5262e
HW		 467 clip.x = stream->src.x > plane_state->clip_rect.x ?
468 stream->src.x : plane_state->clip_rect.x;
4562236b 469
1fbd2cfc 470 clip.width = stream->src.x + stream->src.width <
3be5262e 471 plane_state->clip_rect.x + plane_state->clip_rect.width ?
1fbd2cfc 472 stream->src.x + stream->src.width - clip.x :
3be5262e 473 plane_state->clip_rect.x + plane_state->clip_rect.width - clip.x ;
4562236b 474
3be5262e
HW		 475 clip.y = stream->src.y > plane_state->clip_rect.y ?
476 stream->src.y : plane_state->clip_rect.y;
4562236b 477
1fbd2cfc 478 clip.height = stream->src.y + stream->src.height <
3be5262e 479 plane_state->clip_rect.y + plane_state->clip_rect.height ?
1fbd2cfc 480 stream->src.y + stream->src.height - clip.y :
3be5262e 481 plane_state->clip_rect.y + plane_state->clip_rect.height - clip.y ;
4562236b 482
86006a7f 483 /* offset = surf_src.ofs + (clip.ofs - surface->dst_rect.ofs) * scl_ratio
4562236b
HW		 484 * num_pixels = clip.num_pix * scl_ratio
485 */
3be5262e
HW		 486 data->viewport.x = surf_src.x + (clip.x - plane_state->dst_rect.x) *
487 surf_src.width / plane_state->dst_rect.width;
b2d0a103 488 data->viewport.width = clip.width *
3be5262e 489 surf_src.width / plane_state->dst_rect.width;
4562236b 490
3be5262e
HW		 491 data->viewport.y = surf_src.y + (clip.y - plane_state->dst_rect.y) *
492 surf_src.height / plane_state->dst_rect.height;
b2d0a103 493 data->viewport.height = clip.height *
3be5262e 494 surf_src.height / plane_state->dst_rect.height;
4562236b 495
b2d0a103
DL		 496 /* Round down, compensate in init */
497 data->viewport_c.x = data->viewport.x / vpc_div;
498 data->viewport_c.y = data->viewport.y / vpc_div;
499 data->inits.h_c = (data->viewport.x % vpc_div) != 0 ?
500 dal_fixed31_32_half : dal_fixed31_32_zero;
501 data->inits.v_c = (data->viewport.y % vpc_div) != 0 ?
502 dal_fixed31_32_half : dal_fixed31_32_zero;
503 /* Round up, assume original video size always even dimensions */
504 data->viewport_c.width = (data->viewport.width + vpc_div - 1) / vpc_div;
505 data->viewport_c.height = (data->viewport.height + vpc_div - 1) / vpc_div;
506
507 /* Handle hsplit */
1fbd2cfc
DL		 508 if (pri_split || sec_split) {
509 /* HMirror XOR Secondary_pipe XOR Rotation_180 */
3be5262e
HW		 510 bool right_view = (sec_split != plane_state->horizontal_mirror) !=
511 (plane_state->rotation == ROTATION_ANGLE_180);
1fbd2cfc 512
3be5262e
HW		 513 if (plane_state->rotation == ROTATION_ANGLE_90
514 || plane_state->rotation == ROTATION_ANGLE_270)
1fbd2cfc 515 /* Secondary_pipe XOR Rotation_270 */
3be5262e 516 right_view = (plane_state->rotation == ROTATION_ANGLE_270) != sec_split;
9e6c74ce
DL		 517
518 if (right_view) {
16fb754a
DL		 519 data->viewport.x += data->viewport.width / 2;
520 data->viewport_c.x += data->viewport_c.width / 2;
9e6c74ce 521 /* Ceil offset pipe */
16fb754a
DL		 522 data->viewport.width = (data->viewport.width + 1) / 2;
523 data->viewport_c.width = (data->viewport_c.width + 1) / 2;
9e6c74ce
DL		 524 } else {
525 data->viewport.width /= 2;
526 data->viewport_c.width /= 2;
527 }
b2d0a103 528 }
1fbd2cfc 529
3be5262e
HW		 530 if (plane_state->rotation == ROTATION_ANGLE_90 ||
531 plane_state->rotation == ROTATION_ANGLE_270) {
1fbd2cfc
DL		 532 rect_swap_helper(&data->viewport_c);
533 rect_swap_helper(&data->viewport);
534 }
4562236b
HW		 535}
536
b2d0a103 537static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip)
4562236b 538{
3be5262e 539 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 540 const struct dc_stream_state *stream = pipe_ctx->stream;
3be5262e
HW		 541 struct rect surf_src = plane_state->src_rect;
542 struct rect surf_clip = plane_state->clip_rect;
c802570e 543 int recout_full_x, recout_full_y;
4562236b 544
3be5262e
HW		 545 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
546 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
86006a7f
DL		 547 rect_swap_helper(&surf_src);
548
6702a9ac 549 pipe_ctx->plane_res.scl_data.recout.x = stream->dst.x;
4fa086b9 550 if (stream->src.x < surf_clip.x)
6702a9ac 551 pipe_ctx->plane_res.scl_data.recout.x += (surf_clip.x
4fa086b9
LSL		 552 - stream->src.x) * stream->dst.width
553 / stream->src.width;
4562236b 554
6702a9ac 555 pipe_ctx->plane_res.scl_data.recout.width = surf_clip.width *
4fa086b9 556 stream->dst.width / stream->src.width;
6702a9ac 557 if (pipe_ctx->plane_res.scl_data.recout.width + pipe_ctx->plane_res.scl_data.recout.x >
4fa086b9 558 stream->dst.x + stream->dst.width)
6702a9ac 559 pipe_ctx->plane_res.scl_data.recout.width =
4fa086b9 560 stream->dst.x + stream->dst.width
6702a9ac 561 - pipe_ctx->plane_res.scl_data.recout.x;
4562236b 562
6702a9ac 563 pipe_ctx->plane_res.scl_data.recout.y = stream->dst.y;
4fa086b9 564 if (stream->src.y < surf_clip.y)
6702a9ac 565 pipe_ctx->plane_res.scl_data.recout.y += (surf_clip.y
4fa086b9
LSL		 566 - stream->src.y) * stream->dst.height
567 / stream->src.height;
4562236b 568
6702a9ac 569 pipe_ctx->plane_res.scl_data.recout.height = surf_clip.height *
4fa086b9 570 stream->dst.height / stream->src.height;
6702a9ac 571 if (pipe_ctx->plane_res.scl_data.recout.height + pipe_ctx->plane_res.scl_data.recout.y >
4fa086b9 572 stream->dst.y + stream->dst.height)
6702a9ac 573 pipe_ctx->plane_res.scl_data.recout.height =
4fa086b9 574 stream->dst.y + stream->dst.height
6702a9ac 575 - pipe_ctx->plane_res.scl_data.recout.y;
b2d0a103 576
7b779c99 577 /* Handle h & vsplit */
3be5262e
HW		 578 if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->plane_state ==
579 pipe_ctx->plane_state) {
4fa086b9 580 if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) {
116b2632 581 pipe_ctx->plane_res.scl_data.recout.y += pipe_ctx->plane_res.scl_data.recout.height / 2;
7b779c99 582 /* Floor primary pipe, ceil 2ndary pipe */
4ddd76d1 583 pipe_ctx->plane_res.scl_data.recout.height = (pipe_ctx->plane_res.scl_data.recout.height + 1) / 2;
7b779c99 584 } else {
116b2632 585 pipe_ctx->plane_res.scl_data.recout.x += pipe_ctx->plane_res.scl_data.recout.width / 2;
4ddd76d1 586 pipe_ctx->plane_res.scl_data.recout.width = (pipe_ctx->plane_res.scl_data.recout.width + 1) / 2;
7b779c99
VP		 587 }
588 } else if (pipe_ctx->bottom_pipe &&
3be5262e 589 pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state) {
4fa086b9 590 if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
6702a9ac 591 pipe_ctx->plane_res.scl_data.recout.height /= 2;
7b779c99 592 else
6702a9ac 593 pipe_ctx->plane_res.scl_data.recout.width /= 2;
b2d0a103
DL		 594 }
595
86006a7f
DL		 596 /* Unclipped recout offset = stream dst offset + ((surf dst offset - stream surf_src offset)
597 * * 1/ stream scaling ratio) - (surf surf_src offset * 1/ full scl
c802570e
DL		 598 * ratio)
599 */
3be5262e 600 recout_full_x = stream->dst.x + (plane_state->dst_rect.x - stream->src.x)
4fa086b9 601 * stream->dst.width / stream->src.width -
3be5262e 602 surf_src.x * plane_state->dst_rect.width / surf_src.width
4fa086b9 603 * stream->dst.width / stream->src.width;
3be5262e 604 recout_full_y = stream->dst.y + (plane_state->dst_rect.y - stream->src.y)
4fa086b9 605 * stream->dst.height / stream->src.height -
3be5262e 606 surf_src.y * plane_state->dst_rect.height / surf_src.height
4fa086b9 607 * stream->dst.height / stream->src.height;
c802570e 608
6702a9ac
HW		 609 recout_skip->width = pipe_ctx->plane_res.scl_data.recout.x - recout_full_x;
610 recout_skip->height = pipe_ctx->plane_res.scl_data.recout.y - recout_full_y;
4562236b
HW		 611}
612
b2d0a103 613static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)
4562236b 614{
3be5262e 615 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 616 const struct dc_stream_state *stream = pipe_ctx->stream;
3be5262e 617 struct rect surf_src = plane_state->src_rect;
4fa086b9
LSL		 618 const int in_w = stream->src.width;
619 const int in_h = stream->src.height;
620 const int out_w = stream->dst.width;
621 const int out_h = stream->dst.height;
4562236b 622
3be5262e
HW		 623 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
624 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
86006a7f
DL		 625 rect_swap_helper(&surf_src);
626
6702a9ac 627 pipe_ctx->plane_res.scl_data.ratios.horz = dal_fixed31_32_from_fraction(
86006a7f 628 surf_src.width,
3be5262e 629 plane_state->dst_rect.width);
6702a9ac 630 pipe_ctx->plane_res.scl_data.ratios.vert = dal_fixed31_32_from_fraction(
86006a7f 631 surf_src.height,
3be5262e 632 plane_state->dst_rect.height);
4562236b 633
4fa086b9 634 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
6702a9ac 635 pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2;
4fa086b9 636 else if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
6702a9ac 637 pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2;
4562236b 638
6702a9ac
HW		 639 pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64(
640 pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h);
641 pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64(
642 pipe_ctx->plane_res.scl_data.ratios.horz.value * in_w, out_w);
4562236b 643
6702a9ac
HW		 644 pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz;
645 pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert;
4562236b 646
6702a9ac
HW		 647 if (pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP8
648 || pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP10) {
649 pipe_ctx->plane_res.scl_data.ratios.horz_c.value /= 2;
650 pipe_ctx->plane_res.scl_data.ratios.vert_c.value /= 2;
4562236b
HW		 651 }
652}
653
b2d0a103
DL		 654static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct view *recout_skip)
655{
6702a9ac 656 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
3be5262e 657 struct rect src = pipe_ctx->plane_state->src_rect;
87449a90
AK		 658 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
659 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
b2d0a103 660
86006a7f 661
3be5262e
HW		 662 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
663 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) {
86006a7f 664 rect_swap_helper(&src);
1fbd2cfc
DL		 665 rect_swap_helper(&data->viewport_c);
666 rect_swap_helper(&data->viewport);
667 }
668
b2d0a103
DL		 669 /*
670 * Init calculated according to formula:
671 * init = (scaling_ratio + number_of_taps + 1) / 2
672 * init_bot = init + scaling_ratio
673 * init_c = init + truncated_vp_c_offset(from calculate viewport)
674 */
675 data->inits.h = dal_fixed31_32_div_int(
676 dal_fixed31_32_add_int(data->ratios.horz, data->taps.h_taps + 1), 2);
677
678 data->inits.h_c = dal_fixed31_32_add(data->inits.h_c, dal_fixed31_32_div_int(
679 dal_fixed31_32_add_int(data->ratios.horz_c, data->taps.h_taps_c + 1), 2));
680
681 data->inits.v = dal_fixed31_32_div_int(
682 dal_fixed31_32_add_int(data->ratios.vert, data->taps.v_taps + 1), 2);
683
684 data->inits.v_c = dal_fixed31_32_add(data->inits.v_c, dal_fixed31_32_div_int(
685 dal_fixed31_32_add_int(data->ratios.vert_c, data->taps.v_taps_c + 1), 2));
686
687
688 /* Adjust for viewport end clip-off */
689 if ((data->viewport.x + data->viewport.width) < (src.x + src.width)) {
690 int vp_clip = src.x + src.width - data->viewport.width - data->viewport.x;
1fbd2cfc
DL		 691 int int_part = dal_fixed31_32_floor(
692 dal_fixed31_32_sub(data->inits.h, data->ratios.horz));
b2d0a103 693
1fbd2cfc 694 int_part = int_part > 0 ? int_part : 0;
b2d0a103
DL		 695 data->viewport.width += int_part < vp_clip ? int_part : vp_clip;
696 }
697 if ((data->viewport.y + data->viewport.height) < (src.y + src.height)) {
698 int vp_clip = src.y + src.height - data->viewport.height - data->viewport.y;
1fbd2cfc
DL		 699 int int_part = dal_fixed31_32_floor(
700 dal_fixed31_32_sub(data->inits.v, data->ratios.vert));
b2d0a103 701
1fbd2cfc 702 int_part = int_part > 0 ? int_part : 0;
b2d0a103
DL		 703 data->viewport.height += int_part < vp_clip ? int_part : vp_clip;
704 }
705 if ((data->viewport_c.x + data->viewport_c.width) < (src.x + src.width) / vpc_div) {
706 int vp_clip = (src.x + src.width) / vpc_div -
707 data->viewport_c.width - data->viewport_c.x;
1fbd2cfc
DL		 708 int int_part = dal_fixed31_32_floor(
709 dal_fixed31_32_sub(data->inits.h_c, data->ratios.horz_c));
b2d0a103 710
1fbd2cfc 711 int_part = int_part > 0 ? int_part : 0;
b2d0a103
DL		 712 data->viewport_c.width += int_part < vp_clip ? int_part : vp_clip;
713 }
714 if ((data->viewport_c.y + data->viewport_c.height) < (src.y + src.height) / vpc_div) {
715 int vp_clip = (src.y + src.height) / vpc_div -
716 data->viewport_c.height - data->viewport_c.y;
1fbd2cfc
DL		 717 int int_part = dal_fixed31_32_floor(
718 dal_fixed31_32_sub(data->inits.v_c, data->ratios.vert_c));
b2d0a103 719
1fbd2cfc 720 int_part = int_part > 0 ? int_part : 0;
b2d0a103
DL		 721 data->viewport_c.height += int_part < vp_clip ? int_part : vp_clip;
722 }
723
724 /* Adjust for non-0 viewport offset */
725 if (data->viewport.x) {
726 int int_part;
727
728 data->inits.h = dal_fixed31_32_add(data->inits.h, dal_fixed31_32_mul_int(
729 data->ratios.horz, recout_skip->width));
730 int_part = dal_fixed31_32_floor(data->inits.h) - data->viewport.x;
731 if (int_part < data->taps.h_taps) {
732 int int_adj = data->viewport.x >= (data->taps.h_taps - int_part) ?
733 (data->taps.h_taps - int_part) : data->viewport.x;
734 data->viewport.x -= int_adj;
735 data->viewport.width += int_adj;
736 int_part += int_adj;
737 } else if (int_part > data->taps.h_taps) {
738 data->viewport.x += int_part - data->taps.h_taps;
739 data->viewport.width -= int_part - data->taps.h_taps;
740 int_part = data->taps.h_taps;
741 }
742 data->inits.h.value &= 0xffffffff;
743 data->inits.h = dal_fixed31_32_add_int(data->inits.h, int_part);
744 }
745
746 if (data->viewport_c.x) {
747 int int_part;
748
749 data->inits.h_c = dal_fixed31_32_add(data->inits.h_c, dal_fixed31_32_mul_int(
750 data->ratios.horz_c, recout_skip->width));
751 int_part = dal_fixed31_32_floor(data->inits.h_c) - data->viewport_c.x;
752 if (int_part < data->taps.h_taps_c) {
753 int int_adj = data->viewport_c.x >= (data->taps.h_taps_c - int_part) ?
754 (data->taps.h_taps_c - int_part) : data->viewport_c.x;
755 data->viewport_c.x -= int_adj;
756 data->viewport_c.width += int_adj;
757 int_part += int_adj;
758 } else if (int_part > data->taps.h_taps_c) {
759 data->viewport_c.x += int_part - data->taps.h_taps_c;
760 data->viewport_c.width -= int_part - data->taps.h_taps_c;
761 int_part = data->taps.h_taps_c;
762 }
763 data->inits.h_c.value &= 0xffffffff;
764 data->inits.h_c = dal_fixed31_32_add_int(data->inits.h_c, int_part);
765 }
766
767 if (data->viewport.y) {
768 int int_part;
769
770 data->inits.v = dal_fixed31_32_add(data->inits.v, dal_fixed31_32_mul_int(
771 data->ratios.vert, recout_skip->height));
772 int_part = dal_fixed31_32_floor(data->inits.v) - data->viewport.y;
773 if (int_part < data->taps.v_taps) {
774 int int_adj = data->viewport.y >= (data->taps.v_taps - int_part) ?
775 (data->taps.v_taps - int_part) : data->viewport.y;
776 data->viewport.y -= int_adj;
777 data->viewport.height += int_adj;
778 int_part += int_adj;
779 } else if (int_part > data->taps.v_taps) {
780 data->viewport.y += int_part - data->taps.v_taps;
781 data->viewport.height -= int_part - data->taps.v_taps;
782 int_part = data->taps.v_taps;
783 }
784 data->inits.v.value &= 0xffffffff;
785 data->inits.v = dal_fixed31_32_add_int(data->inits.v, int_part);
786 }
787
788 if (data->viewport_c.y) {
789 int int_part;
790
791 data->inits.v_c = dal_fixed31_32_add(data->inits.v_c, dal_fixed31_32_mul_int(
792 data->ratios.vert_c, recout_skip->height));
793 int_part = dal_fixed31_32_floor(data->inits.v_c) - data->viewport_c.y;
794 if (int_part < data->taps.v_taps_c) {
795 int int_adj = data->viewport_c.y >= (data->taps.v_taps_c - int_part) ?
796 (data->taps.v_taps_c - int_part) : data->viewport_c.y;
797 data->viewport_c.y -= int_adj;
798 data->viewport_c.height += int_adj;
799 int_part += int_adj;
800 } else if (int_part > data->taps.v_taps_c) {
801 data->viewport_c.y += int_part - data->taps.v_taps_c;
802 data->viewport_c.height -= int_part - data->taps.v_taps_c;
803 int_part = data->taps.v_taps_c;
804 }
805 data->inits.v_c.value &= 0xffffffff;
806 data->inits.v_c = dal_fixed31_32_add_int(data->inits.v_c, int_part);
807 }
808
809 /* Interlaced inits based on final vert inits */
810 data->inits.v_bot = dal_fixed31_32_add(data->inits.v, data->ratios.vert);
811 data->inits.v_c_bot = dal_fixed31_32_add(data->inits.v_c, data->ratios.vert_c);
1fbd2cfc 812
3be5262e
HW		 813 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
814 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) {
1fbd2cfc
DL		 815 rect_swap_helper(&data->viewport_c);
816 rect_swap_helper(&data->viewport);
817 }
b2d0a103
DL		 818}
819
820bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
4562236b 821{
3be5262e 822 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
4fa086b9 823 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
b2d0a103
DL		 824 struct view recout_skip = { 0 };
825 bool res = false;
826
4562236b
HW		 827 /* Important: scaling ratio calculation requires pixel format,
828 * lb depth calculation requires recout and taps require scaling ratios.
b2d0a103 829 * Inits require viewport, taps, ratios and recout of split pipe
4562236b 830 */
6702a9ac 831 pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface(
3be5262e 832 pipe_ctx->plane_state->format);
b2d0a103
DL		 833
834 calculate_scaling_ratios(pipe_ctx);
4562236b 835
b2d0a103 836 calculate_viewport(pipe_ctx);
4562236b 837
6702a9ac 838 if (pipe_ctx->plane_res.scl_data.viewport.height < 16 || pipe_ctx->plane_res.scl_data.viewport.width < 16)
4562236b
HW		 839 return false;
840
b2d0a103 841 calculate_recout(pipe_ctx, &recout_skip);
4562236b
HW		 842
843 /**
844 * Setting line buffer pixel depth to 24bpp yields banding
845 * on certain displays, such as the Sharp 4k
846 */
6702a9ac 847 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
4562236b 848
199e458a 849 pipe_ctx->plane_res.scl_data.recout.x += timing->h_border_left;
58bb0e63 850 pipe_ctx->plane_res.scl_data.recout.y += timing->v_border_top;
199e458a 851
58bb0e63
AJ		 852 pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right;
853 pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable + timing->v_border_top + timing->v_border_bottom;
4562236b 854
1b6c8067 855
4562236b 856 /* Taps calculations */
d94585a0
YHL		 857 if (pipe_ctx->plane_res.xfm != NULL)
858 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
859 pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
860
861 if (pipe_ctx->plane_res.dpp != NULL)
862 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
863 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
4562236b
HW		 864 if (!res) {
865 /* Try 24 bpp linebuffer */
6702a9ac 866 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP;
4562236b 867
1b6c8067
BL		 868 if (pipe_ctx->plane_res.xfm != NULL)
869 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
870 pipe_ctx->plane_res.xfm,
871 &pipe_ctx->plane_res.scl_data,
872 &plane_state->scaling_quality);
873
874 if (pipe_ctx->plane_res.dpp != NULL)
875 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
876 pipe_ctx->plane_res.dpp,
877 &pipe_ctx->plane_res.scl_data,
878 &plane_state->scaling_quality);
4562236b
HW		 879 }
880
b2d0a103 881 if (res)
1fbd2cfc 882 /* May need to re-check lb size after this in some obscure scenario */
b2d0a103
DL		 883 calculate_inits_and_adj_vp(pipe_ctx, &recout_skip);
884
4562236b
HW		 885 dm_logger_write(pipe_ctx->stream->ctx->logger, LOG_SCALER,
886 "%s: Viewport:\nheight:%d width:%d x:%d "
887 "y:%d\n dst_rect:\nheight:%d width:%d x:%d "
888 "y:%d\n",
889 __func__,
6702a9ac
HW		 890 pipe_ctx->plane_res.scl_data.viewport.height,
891 pipe_ctx->plane_res.scl_data.viewport.width,
892 pipe_ctx->plane_res.scl_data.viewport.x,
893 pipe_ctx->plane_res.scl_data.viewport.y,
3be5262e
HW		 894 plane_state->dst_rect.height,
895 plane_state->dst_rect.width,
896 plane_state->dst_rect.x,
897 plane_state->dst_rect.y);
4562236b
HW		 898
899 return res;
900}
901
902
903enum dc_status resource_build_scaling_params_for_context(
fb3466a4 904 const struct dc *dc,
608ac7bb 905 struct dc_state *context)
4562236b
HW		 906{
907 int i;
908
909 for (i = 0; i < MAX_PIPES; i++) {
3be5262e 910 if (context->res_ctx.pipe_ctx[i].plane_state != NULL &&
4562236b 911 context->res_ctx.pipe_ctx[i].stream != NULL)
b2d0a103 912 if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i]))
f84a8161 913 return DC_FAIL_SCALING;
4562236b
HW		 914 }
915
916 return DC_OK;
917}
918
a2b8659d
TC		 919struct pipe_ctx *find_idle_secondary_pipe(
920 struct resource_context *res_ctx,
921 const struct resource_pool *pool)
4562236b
HW		 922{
923 int i;
924 struct pipe_ctx *secondary_pipe = NULL;
925
926 /*
927 * search backwards for the second pipe to keep pipe
928 * assignment more consistent
929 */
930
a2b8659d 931 for (i = pool->pipe_count - 1; i >= 0; i--) {
4562236b
HW		 932 if (res_ctx->pipe_ctx[i].stream == NULL) {
933 secondary_pipe = &res_ctx->pipe_ctx[i];
934 secondary_pipe->pipe_idx = i;
935 break;
936 }
937 }
938
939
940 return secondary_pipe;
941}
942
943struct pipe_ctx *resource_get_head_pipe_for_stream(
944 struct resource_context *res_ctx,
0971c40e 945 struct dc_stream_state *stream)
4562236b
HW		 946{
947 int i;
a2b8659d 948 for (i = 0; i < MAX_PIPES; i++) {
4562236b 949 if (res_ctx->pipe_ctx[i].stream == stream &&
1dc90497 950 !res_ctx->pipe_ctx[i].top_pipe) {
4562236b
HW		 951 return &res_ctx->pipe_ctx[i];
952 break;
953 }
954 }
955 return NULL;
956}
957
19f89e23
AG		 958static struct pipe_ctx *resource_get_tail_pipe_for_stream(
959 struct resource_context *res_ctx,
960 struct dc_stream_state *stream)
961{
962 struct pipe_ctx *head_pipe, *tail_pipe;
963 head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
964
965 if (!head_pipe)
966 return NULL;
967
968 tail_pipe = head_pipe->bottom_pipe;
969
970 while (tail_pipe) {
971 head_pipe = tail_pipe;
972 tail_pipe = tail_pipe->bottom_pipe;
973 }
974
975 return head_pipe;
976}
977
4562236b 978/*
ab2541b6
AC		 979 * A free_pipe for a stream is defined here as a pipe
980 * that has no surface attached yet
4562236b 981 */
ab2541b6 982static struct pipe_ctx *acquire_free_pipe_for_stream(
608ac7bb 983 struct dc_state *context,
a2b8659d 984 const struct resource_pool *pool,
0971c40e 985 struct dc_stream_state *stream)
4562236b
HW		 986{
987 int i;
745cc746 988 struct resource_context *res_ctx = &context->res_ctx;
4562236b
HW		 989
990 struct pipe_ctx *head_pipe = NULL;
991
992 /* Find head pipe, which has the back end set up*/
993
994 head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
995
996 if (!head_pipe)
997 ASSERT(0);
998
3be5262e 999 if (!head_pipe->plane_state)
4562236b
HW		 1000 return head_pipe;
1001
1002 /* Re-use pipe already acquired for this stream if available*/
a2b8659d 1003 for (i = pool->pipe_count - 1; i >= 0; i--) {
4562236b 1004 if (res_ctx->pipe_ctx[i].stream == stream &&
3be5262e 1005 !res_ctx->pipe_ctx[i].plane_state) {
4562236b
HW		 1006 return &res_ctx->pipe_ctx[i];
1007 }
1008 }
1009
1010 /*
1011 * At this point we have no re-useable pipe for this stream and we need
1012 * to acquire an idle one to satisfy the request
1013 */
1014
a2b8659d 1015 if (!pool->funcs->acquire_idle_pipe_for_layer)
4562236b
HW		 1016 return NULL;
1017
a2b8659d 1018 return pool->funcs->acquire_idle_pipe_for_layer(context, pool, stream);
4562236b
HW		 1019
1020}
1021
0f9a536f
DL		 1022#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1023static int acquire_first_split_pipe(
1024 struct resource_context *res_ctx,
1025 const struct resource_pool *pool,
0971c40e 1026 struct dc_stream_state *stream)
0f9a536f
DL		 1027{
1028 int i;
1029
1030 for (i = 0; i < pool->pipe_count; i++) {
1031 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
1032
1033 if (pipe_ctx->top_pipe &&
3be5262e 1034 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state) {
0f9a536f
DL		 1035 pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;
1036 if (pipe_ctx->bottom_pipe)
1037 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;
1038
1039 memset(pipe_ctx, 0, sizeof(*pipe_ctx));
6b670fa9 1040 pipe_ctx->stream_res.tg = pool->timing_generators[i];
8feabd03 1041 pipe_ctx->plane_res.hubp = pool->hubps[i];
86a66c4e 1042 pipe_ctx->plane_res.ipp = pool->ipps[i];
d94585a0 1043 pipe_ctx->plane_res.dpp = pool->dpps[i];
a6a6cb34 1044 pipe_ctx->stream_res.opp = pool->opps[i];
0f9a536f 1045 pipe_ctx->pipe_idx = i;
0f9a536f
DL		 1046
1047 pipe_ctx->stream = stream;
1048 return i;
1049 }
1050 }
1051 return -1;
1052}
1053#endif
1054
19f89e23
AG		 1055bool dc_add_plane_to_context(
1056 const struct dc *dc,
0971c40e 1057 struct dc_stream_state *stream,
19f89e23 1058 struct dc_plane_state *plane_state,
608ac7bb 1059 struct dc_state *context)
4562236b
HW		 1060{
1061 int i;
19f89e23
AG		 1062 struct resource_pool *pool = dc->res_pool;
1063 struct pipe_ctx *head_pipe, *tail_pipe, *free_pipe;
ab2541b6 1064 struct dc_stream_status *stream_status = NULL;
4562236b 1065
19f89e23
AG		 1066 for (i = 0; i < context->stream_count; i++)
1067 if (context->streams[i] == stream) {
1068 stream_status = &context->stream_status[i];
1069 break;
1070 }
1071 if (stream_status == NULL) {
1072 dm_error("Existing stream not found; failed to attach surface!\n");
1073 return false;
1074 }
1075
4562236b 1076
19f89e23
AG		 1077 if (stream_status->plane_count == MAX_SURFACE_NUM) {
1078 dm_error("Surface: can not attach plane_state %p! Maximum is: %d\n",
1079 plane_state, MAX_SURFACE_NUM);
4562236b
HW		 1080 return false;
1081 }
1082
19f89e23
AG		 1083 head_pipe = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
1084
1085 if (!head_pipe) {
1086 dm_error("Head pipe not found for stream_state %p !\n", stream);
1087 return false;
1088 }
1089
19f89e23
AG		 1090 free_pipe = acquire_free_pipe_for_stream(context, pool, stream);
1091
1092#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1093 if (!free_pipe) {
1094 int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
1095 if (pipe_idx >= 0)
1096 free_pipe = &context->res_ctx.pipe_ctx[pipe_idx];
1097 }
1098#endif
abb4986e 1099 if (!free_pipe)
19f89e23 1100 return false;
19f89e23 1101
abb4986e
AJ		 1102 /* retain new surfaces */
1103 dc_plane_state_retain(plane_state);
19f89e23
AG		 1104 free_pipe->plane_state = plane_state;
1105
1106 if (head_pipe != free_pipe) {
1107
1108 tail_pipe = resource_get_tail_pipe_for_stream(&context->res_ctx, stream);
1109 ASSERT(tail_pipe);
1110
1111 free_pipe->stream_res.tg = tail_pipe->stream_res.tg;
1112 free_pipe->stream_res.opp = tail_pipe->stream_res.opp;
1113 free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc;
1114 free_pipe->stream_res.audio = tail_pipe->stream_res.audio;
1115 free_pipe->clock_source = tail_pipe->clock_source;
1116 free_pipe->top_pipe = tail_pipe;
1117 tail_pipe->bottom_pipe = free_pipe;
1118 }
1119
1120 /* assign new surfaces*/
1121 stream_status->plane_states[stream_status->plane_count] = plane_state;
1122
1123 stream_status->plane_count++;
1124
1125 return true;
1126}
1127
1128bool dc_remove_plane_from_context(
1129 const struct dc *dc,
1130 struct dc_stream_state *stream,
1131 struct dc_plane_state *plane_state,
608ac7bb 1132 struct dc_state *context)
19f89e23
AG		 1133{
1134 int i;
1135 struct dc_stream_status *stream_status = NULL;
1136 struct resource_pool *pool = dc->res_pool;
1137
ab2541b6 1138 for (i = 0; i < context->stream_count; i++)
4fa086b9 1139 if (context->streams[i] == stream) {
ab2541b6 1140 stream_status = &context->stream_status[i];
4562236b
HW		 1141 break;
1142 }
19f89e23 1143
ab2541b6 1144 if (stream_status == NULL) {
19f89e23 1145 dm_error("Existing stream not found; failed to remove plane.\n");
4562236b
HW		 1146 return false;
1147 }
1148
19f89e23
AG		 1149 /* release pipe for plane*/
1150 for (i = pool->pipe_count - 1; i >= 0; i--) {
1151 struct pipe_ctx *pipe_ctx;
4562236b 1152
19f89e23
AG		 1153 if (context->res_ctx.pipe_ctx[i].plane_state == plane_state) {
1154 pipe_ctx = &context->res_ctx.pipe_ctx[i];
4562236b 1155
19f89e23
AG		 1156 if (pipe_ctx->top_pipe)
1157 pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;
4562236b 1158
19f89e23
AG		 1159 /* Second condition is to avoid setting NULL to top pipe
1160 * of tail pipe making it look like head pipe in subsequent
1161 * deletes
1162 */
1163 if (pipe_ctx->bottom_pipe && pipe_ctx->top_pipe)
1164 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;
4562236b 1165
19f89e23
AG		 1166 /*
1167 * For head pipe detach surfaces from pipe for tail
1168 * pipe just zero it out
1169 */
1170 if (!pipe_ctx->top_pipe) {
1171 pipe_ctx->plane_state = NULL;
1172 pipe_ctx->bottom_pipe = NULL;
1173 } else {
1174 memset(pipe_ctx, 0, sizeof(*pipe_ctx));
1175 }
4562236b 1176 }
19f89e23 1177 }
4562236b 1178
4562236b 1179
19f89e23
AG		 1180 for (i = 0; i < stream_status->plane_count; i++) {
1181 if (stream_status->plane_states[i] == plane_state) {
1182
1183 dc_plane_state_release(stream_status->plane_states[i]);
1184 break;
4562236b 1185 }
19f89e23 1186 }
4562236b 1187
19f89e23
AG		 1188 if (i == stream_status->plane_count) {
1189 dm_error("Existing plane_state not found; failed to detach it!\n");
1190 return false;
4562236b
HW		 1191 }
1192
19f89e23 1193 stream_status->plane_count--;
4562236b 1194
abb4986e
AJ		 1195 /* Start at the plane we've just released, and move all the planes one index forward to "trim" the array */
1196 for (; i < stream_status->plane_count; i++)
19f89e23
AG		 1197 stream_status->plane_states[i] = stream_status->plane_states[i + 1];
1198
1199 stream_status->plane_states[stream_status->plane_count] = NULL;
1200
1201 return true;
1202}
1203
1204bool dc_rem_all_planes_for_stream(
1205 const struct dc *dc,
1206 struct dc_stream_state *stream,
608ac7bb 1207 struct dc_state *context)
19f89e23
AG		 1208{
1209 int i, old_plane_count;
1210 struct dc_stream_status *stream_status = NULL;
1211 struct dc_plane_state *del_planes[MAX_SURFACE_NUM] = { 0 };
1212
1213 for (i = 0; i < context->stream_count; i++)
1214 if (context->streams[i] == stream) {
1215 stream_status = &context->stream_status[i];
1216 break;
1217 }
1218
1219 if (stream_status == NULL) {
1220 dm_error("Existing stream %p not found!\n", stream);
1221 return false;
1222 }
1223
1224 old_plane_count = stream_status->plane_count;
1225
1226 for (i = 0; i < old_plane_count; i++)
1227 del_planes[i] = stream_status->plane_states[i];
1228
1229 for (i = 0; i < old_plane_count; i++)
1230 if (!dc_remove_plane_from_context(dc, stream, del_planes[i], context))
1231 return false;
1232
1233 return true;
1234}
1235
1236static bool add_all_planes_for_stream(
1237 const struct dc *dc,
1238 struct dc_stream_state *stream,
1239 const struct dc_validation_set set[],
1240 int set_count,
608ac7bb 1241 struct dc_state *context)
19f89e23
AG		 1242{
1243 int i, j;
1244
1245 for (i = 0; i < set_count; i++)
1246 if (set[i].stream == stream)
1247 break;
1248
1249 if (i == set_count) {
1250 dm_error("Stream %p not found in set!\n", stream);
1251 return false;
1252 }
4562236b 1253
19f89e23
AG		 1254 for (j = 0; j < set[i].plane_count; j++)
1255 if (!dc_add_plane_to_context(dc, stream, set[i].plane_states[j], context))
1256 return false;
4562236b
HW		 1257
1258 return true;
1259}
1260
19f89e23
AG		 1261bool dc_add_all_planes_for_stream(
1262 const struct dc *dc,
1263 struct dc_stream_state *stream,
1264 struct dc_plane_state * const *plane_states,
1265 int plane_count,
608ac7bb 1266 struct dc_state *context)
19f89e23
AG		 1267{
1268 struct dc_validation_set set;
1269 int i;
1270
1271 set.stream = stream;
1272 set.plane_count = plane_count;
1273
1274 for (i = 0; i < plane_count; i++)
1275 set.plane_states[i] = plane_states[i];
1276
1277 return add_all_planes_for_stream(dc, stream, &set, 1, context);
1278}
1279
1280
4562236b 1281
0971c40e
HW		 1282static bool is_timing_changed(struct dc_stream_state *cur_stream,
1283 struct dc_stream_state *new_stream)
4562236b
HW		 1284{
1285 if (cur_stream == NULL)
1286 return true;
1287
1288 /* If sink pointer changed, it means this is a hotplug, we should do
1289 * full hw setting.
1290 */
1291 if (cur_stream->sink != new_stream->sink)
1292 return true;
1293
1294 /* If output color space is changed, need to reprogram info frames */
4fa086b9 1295 if (cur_stream->output_color_space != new_stream->output_color_space)
4562236b
HW		 1296 return true;
1297
1298 return memcmp(
4fa086b9
LSL		 1299 &cur_stream->timing,
1300 &new_stream->timing,
4562236b
HW		 1301 sizeof(struct dc_crtc_timing)) != 0;
1302}
1303
1304static bool are_stream_backends_same(
0971c40e 1305 struct dc_stream_state *stream_a, struct dc_stream_state *stream_b)
4562236b
HW		 1306{
1307 if (stream_a == stream_b)
1308 return true;
1309
1310 if (stream_a == NULL || stream_b == NULL)
1311 return false;
1312
1313 if (is_timing_changed(stream_a, stream_b))
1314 return false;
1315
1316 return true;
1317}
1318
d54d29db 1319bool dc_is_stream_unchanged(
0971c40e 1320 struct dc_stream_state *old_stream, struct dc_stream_state *stream)
4562236b 1321{
4562236b 1322
ab2541b6
AC		 1323 if (!are_stream_backends_same(old_stream, stream))
1324 return false;
4562236b
HW		 1325
1326 return true;
1327}
1328
9a5d9c48
LSL		 1329bool dc_is_stream_scaling_unchanged(
1330 struct dc_stream_state *old_stream, struct dc_stream_state *stream)
1331{
1332 if (old_stream == stream)
1333 return true;
1334
1335 if (old_stream == NULL || stream == NULL)
1336 return false;
1337
1338 if (memcmp(&old_stream->src,
1339 &stream->src,
1340 sizeof(struct rect)) != 0)
1341 return false;
1342
1343 if (memcmp(&old_stream->dst,
1344 &stream->dst,
1345 sizeof(struct rect)) != 0)
1346 return false;
1347
1348 return true;
1349}
1350
4562236b
HW		 1351/* Maximum TMDS single link pixel clock 165MHz */
1352#define TMDS_MAX_PIXEL_CLOCK_IN_KHZ 165000
1353
1dc90497 1354static void update_stream_engine_usage(
4562236b 1355 struct resource_context *res_ctx,
a2b8659d 1356 const struct resource_pool *pool,
1dc90497
AG		 1357 struct stream_encoder *stream_enc,
1358 bool acquired)
4562236b
HW		 1359{
1360 int i;
1361
a2b8659d
TC		 1362 for (i = 0; i < pool->stream_enc_count; i++) {
1363 if (pool->stream_enc[i] == stream_enc)
1dc90497 1364 res_ctx->is_stream_enc_acquired[i] = acquired;
4562236b
HW		 1365 }
1366}
1367
1368/* TODO: release audio object */
4176664b 1369void update_audio_usage(
4562236b 1370 struct resource_context *res_ctx,
a2b8659d 1371 const struct resource_pool *pool,
1dc90497
AG		 1372 struct audio *audio,
1373 bool acquired)
4562236b
HW		 1374{
1375 int i;
a2b8659d
TC		 1376 for (i = 0; i < pool->audio_count; i++) {
1377 if (pool->audios[i] == audio)
1dc90497 1378 res_ctx->is_audio_acquired[i] = acquired;
4562236b
HW		 1379 }
1380}
1381
1382static int acquire_first_free_pipe(
1383 struct resource_context *res_ctx,
a2b8659d 1384 const struct resource_pool *pool,
0971c40e 1385 struct dc_stream_state *stream)
4562236b
HW		 1386{
1387 int i;
1388
a2b8659d 1389 for (i = 0; i < pool->pipe_count; i++) {
4562236b
HW		 1390 if (!res_ctx->pipe_ctx[i].stream) {
1391 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
1392
6b670fa9 1393 pipe_ctx->stream_res.tg = pool->timing_generators[i];
86a66c4e 1394 pipe_ctx->plane_res.mi = pool->mis[i];
8feabd03 1395 pipe_ctx->plane_res.hubp = pool->hubps[i];
86a66c4e
HW		 1396 pipe_ctx->plane_res.ipp = pool->ipps[i];
1397 pipe_ctx->plane_res.xfm = pool->transforms[i];
d94585a0 1398 pipe_ctx->plane_res.dpp = pool->dpps[i];
a6a6cb34 1399 pipe_ctx->stream_res.opp = pool->opps[i];
4562236b
HW		 1400 pipe_ctx->pipe_idx = i;
1401
ff5ef992 1402
4562236b
HW		 1403 pipe_ctx->stream = stream;
1404 return i;
1405 }
1406 }
1407 return -1;
1408}
1409
1410static struct stream_encoder *find_first_free_match_stream_enc_for_link(
1411 struct resource_context *res_ctx,
a2b8659d 1412 const struct resource_pool *pool,
0971c40e 1413 struct dc_stream_state *stream)
4562236b
HW		 1414{
1415 int i;
1416 int j = -1;
d0778ebf 1417 struct dc_link *link = stream->sink->link;
4562236b 1418
a2b8659d 1419 for (i = 0; i < pool->stream_enc_count; i++) {
4562236b 1420 if (!res_ctx->is_stream_enc_acquired[i] &&
a2b8659d 1421 pool->stream_enc[i]) {
4562236b
HW		 1422 /* Store first available for MST second display
1423 * in daisy chain use case */
1424 j = i;
a2b8659d 1425 if (pool->stream_enc[i]->id ==
4562236b 1426 link->link_enc->preferred_engine)
a2b8659d 1427 return pool->stream_enc[i];
4562236b
HW		 1428 }
1429 }
1430
1431 /*
1432 * below can happen in cases when stream encoder is acquired:
1433 * 1) for second MST display in chain, so preferred engine already
1434 * acquired;
1435 * 2) for another link, which preferred engine already acquired by any
1436 * MST configuration.
1437 *
1438 * If signal is of DP type and preferred engine not found, return last available
1439 *
1440 * TODO - This is just a patch up and a generic solution is
1441 * required for non DP connectors.
1442 */
1443
1444 if (j >= 0 && dc_is_dp_signal(stream->signal))
a2b8659d 1445 return pool->stream_enc[j];
4562236b
HW		 1446
1447 return NULL;
1448}
1449
a2b8659d
TC		 1450static struct audio *find_first_free_audio(
1451 struct resource_context *res_ctx,
1452 const struct resource_pool *pool)
4562236b
HW		 1453{
1454 int i;
66bfd4fd
CL		 1455 for (i = 0; i < pool->audio_count; i++) {
1456 if ((res_ctx->is_audio_acquired[i] == false) && (res_ctx->is_stream_enc_acquired[i] == true)) {
1457 return pool->audios[i];
4562236b 1458 }
66bfd4fd
CL		 1459 }
1460 /*not found the matching one, first come first serve*/
1461 for (i = 0; i < pool->audio_count; i++) {
1462 if (res_ctx->is_audio_acquired[i] == false) {
1463 return pool->audios[i];
4176664b
CL		 1464 }
1465 }
4562236b
HW		 1466 return 0;
1467}
1468
4562236b 1469bool resource_is_stream_unchanged(
608ac7bb 1470 struct dc_state *old_context, struct dc_stream_state *stream)
4562236b 1471{
ab2541b6 1472 int i;
4562236b 1473
ab2541b6 1474 for (i = 0; i < old_context->stream_count; i++) {
0971c40e 1475 struct dc_stream_state *old_stream = old_context->streams[i];
4562236b 1476
ab2541b6 1477 if (are_stream_backends_same(old_stream, stream))
4562236b 1478 return true;
4562236b
HW		 1479 }
1480
1481 return false;
1482}
1483
13ab1b44 1484enum dc_status dc_add_stream_to_ctx(
1dc90497 1485 struct dc *dc,
608ac7bb 1486 struct dc_state *new_ctx,
1dc90497
AG		 1487 struct dc_stream_state *stream)
1488{
1489 struct dc_context *dc_ctx = dc->ctx;
1490 enum dc_status res;
1491
1492 if (new_ctx->stream_count >= dc->res_pool->pipe_count) {
1493 DC_ERROR("Max streams reached, can add stream %p !\n", stream);
1494 return DC_ERROR_UNEXPECTED;
1495 }
1496
1497 new_ctx->streams[new_ctx->stream_count] = stream;
1498 dc_stream_retain(stream);
1499 new_ctx->stream_count++;
1500
1501 res = dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream);
1502 if (res != DC_OK)
1503 DC_ERROR("Adding stream %p to context failed with err %d!\n", stream, res);
1504
13ab1b44 1505 return res;
1dc90497
AG		 1506}
1507
62c933f9 1508enum dc_status dc_remove_stream_from_ctx(
1dc90497 1509 struct dc *dc,
608ac7bb 1510 struct dc_state *new_ctx,
1dc90497
AG		 1511 struct dc_stream_state *stream)
1512{
19f89e23 1513 int i;
1dc90497
AG		 1514 struct dc_context *dc_ctx = dc->ctx;
1515 struct pipe_ctx *del_pipe = NULL;
1516
19f89e23 1517 /* Release primary pipe */
1dc90497 1518 for (i = 0; i < MAX_PIPES; i++) {
19f89e23
AG		 1519 if (new_ctx->res_ctx.pipe_ctx[i].stream == stream &&
1520 !new_ctx->res_ctx.pipe_ctx[i].top_pipe) {
1dc90497
AG		 1521 del_pipe = &new_ctx->res_ctx.pipe_ctx[i];
1522
19f89e23
AG		 1523 ASSERT(del_pipe->stream_res.stream_enc);
1524 update_stream_engine_usage(
1525 &new_ctx->res_ctx,
1dc90497 1526 dc->res_pool,
19f89e23
AG		 1527 del_pipe->stream_res.stream_enc,
1528 false);
1dc90497
AG		 1529
1530 if (del_pipe->stream_res.audio)
1531 update_audio_usage(
1532 &new_ctx->res_ctx,
1533 dc->res_pool,
1534 del_pipe->stream_res.audio,
1535 false);
1536
9d0dcecd
HW		 1537 resource_unreference_clock_source(&new_ctx->res_ctx,
1538 dc->res_pool,
1539 del_pipe->clock_source);
1540
1dc90497 1541 memset(del_pipe, 0, sizeof(*del_pipe));
19f89e23
AG		 1542
1543 break;
1dc90497
AG		 1544 }
1545 }
1546
1547 if (!del_pipe) {
1548 DC_ERROR("Pipe not found for stream %p !\n", stream);
1549 return DC_ERROR_UNEXPECTED;
1550 }
1551
1552 for (i = 0; i < new_ctx->stream_count; i++)
1553 if (new_ctx->streams[i] == stream)
1554 break;
1555
1556 if (new_ctx->streams[i] != stream) {
1557 DC_ERROR("Context doesn't have stream %p !\n", stream);
1558 return DC_ERROR_UNEXPECTED;
1559 }
1560
1561 dc_stream_release(new_ctx->streams[i]);
1562 new_ctx->stream_count--;
1563
1dc90497
AG		 1564 /* Trim back arrays */
1565 for (; i < new_ctx->stream_count; i++) {
1566 new_ctx->streams[i] = new_ctx->streams[i + 1];
1567 new_ctx->stream_status[i] = new_ctx->stream_status[i + 1];
1568 }
1569
1570 new_ctx->streams[new_ctx->stream_count] = NULL;
1571 memset(
1572 &new_ctx->stream_status[new_ctx->stream_count],
1573 0,
1574 sizeof(new_ctx->stream_status[0]));
1575
1576 return DC_OK;
1577}
1578
4562236b
HW		 1579static void copy_pipe_ctx(
1580 const struct pipe_ctx *from_pipe_ctx, struct pipe_ctx *to_pipe_ctx)
1581{
3be5262e 1582 struct dc_plane_state *plane_state = to_pipe_ctx->plane_state;
0971c40e 1583 struct dc_stream_state *stream = to_pipe_ctx->stream;
4562236b
HW		 1584
1585 *to_pipe_ctx = *from_pipe_ctx;
1586 to_pipe_ctx->stream = stream;
3be5262e
HW		 1587 if (plane_state != NULL)
1588 to_pipe_ctx->plane_state = plane_state;
4562236b
HW		 1589}
1590
0971c40e
HW		 1591static struct dc_stream_state *find_pll_sharable_stream(
1592 struct dc_stream_state *stream_needs_pll,
608ac7bb 1593 struct dc_state *context)
4562236b 1594{
ab2541b6 1595 int i;
4562236b 1596
ab2541b6 1597 for (i = 0; i < context->stream_count; i++) {
0971c40e 1598 struct dc_stream_state *stream_has_pll = context->streams[i];
4562236b 1599
ab2541b6
AC		 1600 /* We are looking for non dp, non virtual stream */
1601 if (resource_are_streams_timing_synchronizable(
1602 stream_needs_pll, stream_has_pll)
1603 && !dc_is_dp_signal(stream_has_pll->signal)
d0778ebf 1604 && stream_has_pll->sink->link->connector_signal
ab2541b6
AC		 1605 != SIGNAL_TYPE_VIRTUAL)
1606 return stream_has_pll;
4562236b 1607
4562236b
HW		 1608 }
1609
1610 return NULL;
1611}
1612
1613static int get_norm_pix_clk(const struct dc_crtc_timing *timing)
1614{
1615 uint32_t pix_clk = timing->pix_clk_khz;
1616 uint32_t normalized_pix_clk = pix_clk;
1617
1618 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
1619 pix_clk /= 2;
cc4d99b8
CL		 1620 if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) {
1621 switch (timing->display_color_depth) {
1622 case COLOR_DEPTH_888:
1623 normalized_pix_clk = pix_clk;
1624 break;
1625 case COLOR_DEPTH_101010:
1626 normalized_pix_clk = (pix_clk * 30) / 24;
1627 break;
1628 case COLOR_DEPTH_121212:
1629 normalized_pix_clk = (pix_clk * 36) / 24;
4562236b 1630 break;
cc4d99b8
CL		 1631 case COLOR_DEPTH_161616:
1632 normalized_pix_clk = (pix_clk * 48) / 24;
4562236b 1633 break;
cc4d99b8
CL		 1634 default:
1635 ASSERT(0);
4562236b 1636 break;
cc4d99b8 1637 }
4562236b 1638 }
4562236b
HW		 1639 return normalized_pix_clk;
1640}
1641
0971c40e 1642static void calculate_phy_pix_clks(struct dc_stream_state *stream)
4562236b 1643{
9345d987
AG		 1644 /* update actual pixel clock on all streams */
1645 if (dc_is_hdmi_signal(stream->signal))
1646 stream->phy_pix_clk = get_norm_pix_clk(
4fa086b9 1647 &stream->timing);
9345d987
AG		 1648 else
1649 stream->phy_pix_clk =
4fa086b9 1650 stream->timing.pix_clk_khz;
4562236b
HW		 1651}
1652
1653enum dc_status resource_map_pool_resources(
fb3466a4 1654 const struct dc *dc,
608ac7bb 1655 struct dc_state *context,
1dc90497 1656 struct dc_stream_state *stream)
4562236b 1657{
a2b8659d 1658 const struct resource_pool *pool = dc->res_pool;
1dc90497
AG		 1659 int i;
1660 struct dc_context *dc_ctx = dc->ctx;
1661 struct pipe_ctx *pipe_ctx = NULL;
1662 int pipe_idx = -1;
4562236b 1663
1dc90497
AG		 1664 /* TODO Check if this is needed */
1665 /*if (!resource_is_stream_unchanged(old_context, stream)) {
430ef426 1666 if (stream != NULL && old_context->streams[i] != NULL) {
4b679bc3 1667 stream->bit_depth_params =
430ef426
DL		 1668 old_context->streams[i]->bit_depth_params;
1669 stream->clamping = old_context->streams[i]->clamping;
a2b8659d
TC		 1670 continue;
1671 }
4b679bc3 1672 }
1dc90497 1673 */
7e2fe319 1674
1dc90497
AG		 1675 /* acquire new resources */
1676 pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream);
8c737fcc 1677
94c6d735 1678#ifdef CONFIG_DRM_AMD_DC_DCN1_0
1dc90497 1679 if (pipe_idx < 0)
13ab1b44 1680 pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
94c6d735 1681#endif
13ab1b44 1682
1dc90497
AG		 1683 if (pipe_idx < 0)
1684 return DC_NO_CONTROLLER_RESOURCE;
1685
1686 pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
1687
1688 pipe_ctx->stream_res.stream_enc =
1689 find_first_free_match_stream_enc_for_link(
1690 &context->res_ctx, pool, stream);
1691
1692 if (!pipe_ctx->stream_res.stream_enc)
1693 return DC_NO_STREAM_ENG_RESOURCE;
1694
1695 update_stream_engine_usage(
1696 &context->res_ctx, pool,
1697 pipe_ctx->stream_res.stream_enc,
1698 true);
1699
1700 /* TODO: Add check if ASIC support and EDID audio */
1701 if (!stream->sink->converter_disable_audio &&
1702 dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&
1703 stream->audio_info.mode_count) {
1704 pipe_ctx->stream_res.audio = find_first_free_audio(
1705 &context->res_ctx, pool);
1706
1707 /*
1708 * Audio assigned in order first come first get.
1709 * There are asics which has number of audio
1710 * resources less then number of pipes
1711 */
1712 if (pipe_ctx->stream_res.audio)
1713 update_audio_usage(&context->res_ctx, pool,
1714 pipe_ctx->stream_res.audio, true);
1715 }
268cadbd 1716
1dc90497
AG		 1717 for (i = 0; i < context->stream_count; i++)
1718 if (context->streams[i] == stream) {
1719 context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst;
0f0bdca5 1720 context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.stream_enc->id;
1dc90497
AG		 1721 return DC_OK;
1722 }
4562236b 1723
1dc90497
AG		 1724 DC_ERROR("Stream %p not found in new ctx!\n", stream);
1725 return DC_ERROR_UNEXPECTED;
1726}
4562236b 1727
1dc90497
AG		 1728/* first stream in the context is used to populate the rest */
1729void validate_guaranteed_copy_streams(
608ac7bb 1730 struct dc_state *context,
1dc90497
AG		 1731 int max_streams)
1732{
1733 int i;
ab2541b6 1734
1dc90497
AG		 1735 for (i = 1; i < max_streams; i++) {
1736 context->streams[i] = context->streams[0];
ab2541b6 1737
1dc90497
AG		 1738 copy_pipe_ctx(&context->res_ctx.pipe_ctx[0],
1739 &context->res_ctx.pipe_ctx[i]);
1740 context->res_ctx.pipe_ctx[i].stream =
1741 context->res_ctx.pipe_ctx[0].stream;
ab2541b6 1742
1dc90497
AG		 1743 dc_stream_retain(context->streams[i]);
1744 context->stream_count++;
4562236b 1745 }
1dc90497 1746}
4562236b 1747
f36cc577 1748void dc_resource_state_copy_construct_current(
1dc90497 1749 const struct dc *dc,
608ac7bb 1750 struct dc_state *dst_ctx)
1dc90497 1751{
f36cc577 1752 dc_resource_state_copy_construct(dc->current_state, dst_ctx);
1dc90497
AG		 1753}
1754
ab8db3e1
AG		 1755
1756void dc_resource_state_construct(
1757 const struct dc *dc,
1758 struct dc_state *dst_ctx)
1759{
1760 dst_ctx->dis_clk = dc->res_pool->display_clock;
1761}
1762
e750d56d 1763enum dc_status dc_validate_global_state(
1dc90497 1764 struct dc *dc,
608ac7bb 1765 struct dc_state *new_ctx)
4562236b 1766{
1dc90497 1767 enum dc_status result = DC_ERROR_UNEXPECTED;
1dc90497 1768 int i, j;
4562236b 1769
d596e5d0
YS		 1770 if (dc->res_pool->funcs->validate_global) {
1771 result = dc->res_pool->funcs->validate_global(dc, new_ctx);
1772 if (result != DC_OK)
1773 return result;
1774 }
4562236b 1775
1dc90497
AG		 1776 for (i = 0; new_ctx && i < new_ctx->stream_count; i++) {
1777 struct dc_stream_state *stream = new_ctx->streams[i];
1778
1779 for (j = 0; j < dc->res_pool->pipe_count; j++) {
1780 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[j];
1781
1782 if (pipe_ctx->stream != stream)
1783 continue;
1784
1785 /* Switch to dp clock source only if there is
1786 * no non dp stream that shares the same timing
1787 * with the dp stream.
1788 */
1789 if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
1790 !find_pll_sharable_stream(stream, new_ctx)) {
1791
9d0dcecd 1792 resource_unreference_clock_source(
1dc90497
AG		 1793 &new_ctx->res_ctx,
1794 dc->res_pool,
9d0dcecd 1795 pipe_ctx->clock_source);
4a629536 1796
1dc90497
AG		 1797 pipe_ctx->clock_source = dc->res_pool->dp_clock_source;
1798 resource_reference_clock_source(
1799 &new_ctx->res_ctx,
1800 dc->res_pool,
1801 pipe_ctx->clock_source);
1802 }
1803 }
1804 }
1805
1dc90497
AG		 1806 result = resource_build_scaling_params_for_context(dc, new_ctx);
1807
1808 if (result == DC_OK)
1809 if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx))
1810 result = DC_FAIL_BANDWIDTH_VALIDATE;
1811
1812 return result;
4562236b
HW		 1813}
1814
6e4d6bee
TC		 1815static void patch_gamut_packet_checksum(
1816 struct encoder_info_packet *gamut_packet)
4562236b 1817{
4562236b 1818 /* For gamut we recalc checksum */
6e4d6bee 1819 if (gamut_packet->valid) {
4562236b
HW		 1820 uint8_t chk_sum = 0;
1821 uint8_t *ptr;
1822 uint8_t i;
1823
4562236b 1824 /*start of the Gamut data. */
6e4d6bee 1825 ptr = &gamut_packet->sb[3];
4562236b 1826
6e4d6bee 1827 for (i = 0; i <= gamut_packet->sb[1]; i++)
4562236b
HW		 1828 chk_sum += ptr[i];
1829
6e4d6bee 1830 gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum);
1646a6fe 1831 }
4562236b
HW		 1832}
1833
1834static void set_avi_info_frame(
6e4d6bee 1835 struct encoder_info_packet *info_packet,
4562236b
HW		 1836 struct pipe_ctx *pipe_ctx)
1837{
0971c40e 1838 struct dc_stream_state *stream = pipe_ctx->stream;
4562236b
HW		 1839 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
1840 struct info_frame info_frame = { {0} };
1841 uint32_t pixel_encoding = 0;
1842 enum scanning_type scan_type = SCANNING_TYPE_NODATA;
1843 enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA;
1844 bool itc = false;
50e27654 1845 uint8_t itc_value = 0;
4562236b 1846 uint8_t cn0_cn1 = 0;
50e27654 1847 unsigned int cn0_cn1_value = 0;
4562236b
HW		 1848 uint8_t *check_sum = NULL;
1849 uint8_t byte_index = 0;
e8d726b7 1850 union hdmi_info_packet *hdmi_info = &info_frame.avi_info_packet.info_packet_hdmi;
50e27654 1851 union display_content_support support = {0};
4fa086b9 1852 unsigned int vic = pipe_ctx->stream->timing.vic;
15e17335 1853 enum dc_timing_3d_format format;
4562236b 1854
4fa086b9 1855 color_space = pipe_ctx->stream->output_color_space;
e5f2038e 1856 if (color_space == COLOR_SPACE_UNKNOWN)
4fa086b9 1857 color_space = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ?
e5f2038e 1858 COLOR_SPACE_SRGB:COLOR_SPACE_YCBCR709;
4562236b
HW		 1859
1860 /* Initialize header */
e8d726b7 1861 hdmi_info->bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI;
4562236b
HW		 1862 /* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall
1863 * not be used in HDMI 2.0 (Section 10.1) */
e8d726b7
RA		 1864 hdmi_info->bits.header.version = 2;
1865 hdmi_info->bits.header.length = HDMI_AVI_INFOFRAME_SIZE;
4562236b
HW		 1866
1867 /*
1868 * IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built
1869 * according to HDMI 2.0 spec (Section 10.1)
1870 */
1871
4fa086b9 1872 switch (stream->timing.pixel_encoding) {
4562236b
HW		 1873 case PIXEL_ENCODING_YCBCR422:
1874 pixel_encoding = 1;
1875 break;
1876
1877 case PIXEL_ENCODING_YCBCR444:
1878 pixel_encoding = 2;
1879 break;
1880 case PIXEL_ENCODING_YCBCR420:
1881 pixel_encoding = 3;
1882 break;
1883
1884 case PIXEL_ENCODING_RGB:
1885 default:
1886 pixel_encoding = 0;
1887 }
1888
1889 /* Y0_Y1_Y2 : The pixel encoding */
1890 /* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */
e8d726b7 1891 hdmi_info->bits.Y0_Y1_Y2 = pixel_encoding;
4562236b
HW		 1892
1893 /* A0 = 1 Active Format Information valid */
e8d726b7 1894 hdmi_info->bits.A0 = ACTIVE_FORMAT_VALID;
4562236b
HW		 1895
1896 /* B0, B1 = 3; Bar info data is valid */
e8d726b7 1897 hdmi_info->bits.B0_B1 = BAR_INFO_BOTH_VALID;
4562236b 1898
e8d726b7 1899 hdmi_info->bits.SC0_SC1 = PICTURE_SCALING_UNIFORM;
4562236b
HW		 1900
1901 /* S0, S1 : Underscan / Overscan */
1902 /* TODO: un-hardcode scan type */
1903 scan_type = SCANNING_TYPE_UNDERSCAN;
e8d726b7 1904 hdmi_info->bits.S0_S1 = scan_type;
4562236b
HW		 1905
1906 /* C0, C1 : Colorimetry */
8fde5884 1907 if (color_space == COLOR_SPACE_YCBCR709 ||
15e17335 1908 color_space == COLOR_SPACE_YCBCR709_LIMITED)
e8d726b7 1909 hdmi_info->bits.C0_C1 = COLORIMETRY_ITU709;
8fde5884
CL		 1910 else if (color_space == COLOR_SPACE_YCBCR601 ||
1911 color_space == COLOR_SPACE_YCBCR601_LIMITED)
e8d726b7 1912 hdmi_info->bits.C0_C1 = COLORIMETRY_ITU601;
8fde5884 1913 else {
e8d726b7 1914 hdmi_info->bits.C0_C1 = COLORIMETRY_NO_DATA;
8fde5884 1915 }
534db198 1916 if (color_space == COLOR_SPACE_2020_RGB_FULLRANGE ||
8fde5884
CL		 1917 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE ||
1918 color_space == COLOR_SPACE_2020_YCBCR) {
e8d726b7
RA		 1919 hdmi_info->bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR;
1920 hdmi_info->bits.C0_C1 = COLORIMETRY_EXTENDED;
534db198 1921 } else if (color_space == COLOR_SPACE_ADOBERGB) {
e8d726b7
RA		 1922 hdmi_info->bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB;
1923 hdmi_info->bits.C0_C1 = COLORIMETRY_EXTENDED;
534db198
AZ		 1924 }
1925
4562236b 1926 /* TODO: un-hardcode aspect ratio */
4fa086b9 1927 aspect = stream->timing.aspect_ratio;
4562236b
HW		 1928
1929 switch (aspect) {
1930 case ASPECT_RATIO_4_3:
1931 case ASPECT_RATIO_16_9:
e8d726b7 1932 hdmi_info->bits.M0_M1 = aspect;
4562236b
HW		 1933 break;
1934
1935 case ASPECT_RATIO_NO_DATA:
1936 case ASPECT_RATIO_64_27:
1937 case ASPECT_RATIO_256_135:
1938 default:
e8d726b7 1939 hdmi_info->bits.M0_M1 = 0;
4562236b
HW		 1940 }
1941
1942 /* Active Format Aspect ratio - same as Picture Aspect Ratio. */
e8d726b7 1943 hdmi_info->bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE;
4562236b
HW		 1944
1945 /* TODO: un-hardcode cn0_cn1 and itc */
50e27654 1946
4562236b 1947 cn0_cn1 = 0;
50e27654
ZF		 1948 cn0_cn1_value = 0;
1949
1950 itc = true;
1951 itc_value = 1;
1952
4fa086b9 1953 support = stream->sink->edid_caps.content_support;
4562236b
HW		 1954
1955 if (itc) {
50e27654
ZF		 1956 if (!support.bits.valid_content_type) {
1957 cn0_cn1_value = 0;
1958 } else {
1959 if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GRAPHICS) {
1960 if (support.bits.graphics_content == 1) {
1961 cn0_cn1_value = 0;
1962 }
1963 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_PHOTO) {
1964 if (support.bits.photo_content == 1) {
1965 cn0_cn1_value = 1;
1966 } else {
1967 cn0_cn1_value = 0;
1968 itc_value = 0;
1969 }
1970 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_CINEMA) {
1971 if (support.bits.cinema_content == 1) {
1972 cn0_cn1_value = 2;
1973 } else {
1974 cn0_cn1_value = 0;
1975 itc_value = 0;
1976 }
1977 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GAME) {
1978 if (support.bits.game_content == 1) {
1979 cn0_cn1_value = 3;
1980 } else {
1981 cn0_cn1_value = 0;
1982 itc_value = 0;
1983 }
1984 }
1985 }
1986 hdmi_info->bits.CN0_CN1 = cn0_cn1_value;
1987 hdmi_info->bits.ITC = itc_value;
4562236b
HW		 1988 }
1989
1990 /* TODO : We should handle YCC quantization */
1991 /* but we do not have matrix calculation */
4fa086b9
LSL		 1992 if (stream->sink->edid_caps.qs_bit == 1 &&
1993 stream->sink->edid_caps.qy_bit == 1) {
50e27654
ZF		 1994 if (color_space == COLOR_SPACE_SRGB ||
1995 color_space == COLOR_SPACE_2020_RGB_FULLRANGE) {
1996 hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_FULL_RANGE;
1997 hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_FULL_RANGE;
1998 } else if (color_space == COLOR_SPACE_SRGB_LIMITED ||
1999 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE) {
2000 hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_LIMITED_RANGE;
2001 hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
2002 } else {
2003 hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
2004 hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
2005 }
4562236b 2006 } else {
e8d726b7 2007 hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
50e27654 2008 hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
4562236b 2009 }
50e27654 2010
15e17335 2011 ///VIC
4fa086b9 2012 format = stream->timing.timing_3d_format;
15e17335
CL		 2013 /*todo, add 3DStereo support*/
2014 if (format != TIMING_3D_FORMAT_NONE) {
2015 // Based on HDMI specs hdmi vic needs to be converted to cea vic when 3D is enabled
4fa086b9 2016 switch (pipe_ctx->stream->timing.hdmi_vic) {
15e17335
CL		 2017 case 1:
2018 vic = 95;
2019 break;
2020 case 2:
2021 vic = 94;
2022 break;
2023 case 3:
2024 vic = 93;
2025 break;
2026 case 4:
2027 vic = 98;
2028 break;
2029 default:
2030 break;
2031 }
2032 }
2033 hdmi_info->bits.VIC0_VIC7 = vic;
4562236b
HW		 2034
2035 /* pixel repetition
2036 * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel
2037 * repetition start from 1 */
e8d726b7 2038 hdmi_info->bits.PR0_PR3 = 0;
4562236b
HW		 2039
2040 /* Bar Info
2041 * barTop: Line Number of End of Top Bar.
2042 * barBottom: Line Number of Start of Bottom Bar.
2043 * barLeft: Pixel Number of End of Left Bar.
2044 * barRight: Pixel Number of Start of Right Bar. */
4fa086b9
LSL		 2045 hdmi_info->bits.bar_top = stream->timing.v_border_top;
2046 hdmi_info->bits.bar_bottom = (stream->timing.v_total
2047 - stream->timing.v_border_bottom + 1);
2048 hdmi_info->bits.bar_left = stream->timing.h_border_left;
2049 hdmi_info->bits.bar_right = (stream->timing.h_total
2050 - stream->timing.h_border_right + 1);
4562236b
HW		 2051
2052 /* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */
e8d726b7
RA		 2053 check_sum = &info_frame.avi_info_packet.info_packet_hdmi.packet_raw_data.sb[0];
2054
3e183c5f 2055 *check_sum = HDMI_INFOFRAME_TYPE_AVI + HDMI_AVI_INFOFRAME_SIZE + 2;
4562236b 2056
3e183c5f 2057 for (byte_index = 1; byte_index <= HDMI_AVI_INFOFRAME_SIZE; byte_index++)
e8d726b7 2058 *check_sum += hdmi_info->packet_raw_data.sb[byte_index];
4562236b
HW		 2059
2060 /* one byte complement */
2061 *check_sum = (uint8_t) (0x100 - *check_sum);
2062
2063 /* Store in hw_path_mode */
e8d726b7
RA		 2064 info_packet->hb0 = hdmi_info->packet_raw_data.hb0;
2065 info_packet->hb1 = hdmi_info->packet_raw_data.hb1;
2066 info_packet->hb2 = hdmi_info->packet_raw_data.hb2;
4562236b 2067
e66e4d64
HW		 2068 for (byte_index = 0; byte_index < sizeof(info_frame.avi_info_packet.
2069 info_packet_hdmi.packet_raw_data.sb); byte_index++)
4562236b 2070 info_packet->sb[byte_index] = info_frame.avi_info_packet.
e66e4d64 2071 info_packet_hdmi.packet_raw_data.sb[byte_index];
4562236b
HW		 2072
2073 info_packet->valid = true;
2074}
2075
6e4d6bee
TC		 2076static void set_vendor_info_packet(
2077 struct encoder_info_packet *info_packet,
0971c40e 2078 struct dc_stream_state *stream)
4562236b
HW		 2079{
2080 uint32_t length = 0;
2081 bool hdmi_vic_mode = false;
2082 uint8_t checksum = 0;
2083 uint32_t i = 0;
2084 enum dc_timing_3d_format format;
15e17335
CL		 2085 // Can be different depending on packet content /*todo*/
2086 // unsigned int length = pPathMode->dolbyVision ? 24 : 5;
2087
2088 info_packet->valid = false;
4562236b 2089
4fa086b9
LSL		 2090 format = stream->timing.timing_3d_format;
2091 if (stream->view_format == VIEW_3D_FORMAT_NONE)
7f5c22d1 2092 format = TIMING_3D_FORMAT_NONE;
4562236b
HW		 2093
2094 /* Can be different depending on packet content */
2095 length = 5;
2096
4fa086b9
LSL		 2097 if (stream->timing.hdmi_vic != 0
2098 && stream->timing.h_total >= 3840
2099 && stream->timing.v_total >= 2160)
4562236b
HW		 2100 hdmi_vic_mode = true;
2101
2102 /* According to HDMI 1.4a CTS, VSIF should be sent
2103 * for both 3D stereo and HDMI VIC modes.
2104 * For all other modes, there is no VSIF sent. */
2105
2106 if (format == TIMING_3D_FORMAT_NONE && !hdmi_vic_mode)
2107 return;
2108
2109 /* 24bit IEEE Registration identifier (0x000c03). LSB first. */
2110 info_packet->sb[1] = 0x03;
2111 info_packet->sb[2] = 0x0C;
2112 info_packet->sb[3] = 0x00;
2113
2114 /*PB4: 5 lower bytes = 0 (reserved). 3 higher bits = HDMI_Video_Format.
2115 * The value for HDMI_Video_Format are:
2116 * 0x0 (0b000) - No additional HDMI video format is presented in this
2117 * packet
2118 * 0x1 (0b001) - Extended resolution format present. 1 byte of HDMI_VIC
2119 * parameter follows
2120 * 0x2 (0b010) - 3D format indication present. 3D_Structure and
2121 * potentially 3D_Ext_Data follows
2122 * 0x3..0x7 (0b011..0b111) - reserved for future use */
2123 if (format != TIMING_3D_FORMAT_NONE)
2124 info_packet->sb[4] = (2 << 5);
2125 else if (hdmi_vic_mode)
2126 info_packet->sb[4] = (1 << 5);
2127
2128 /* PB5: If PB4 claims 3D timing (HDMI_Video_Format = 0x2):
2129 * 4 lower bites = 0 (reserved). 4 higher bits = 3D_Structure.
2130 * The value for 3D_Structure are:
2131 * 0x0 - Frame Packing
2132 * 0x1 - Field Alternative
2133 * 0x2 - Line Alternative
2134 * 0x3 - Side-by-Side (full)
2135 * 0x4 - L + depth
2136 * 0x5 - L + depth + graphics + graphics-depth
2137 * 0x6 - Top-and-Bottom
2138 * 0x7 - Reserved for future use
2139 * 0x8 - Side-by-Side (Half)
2140 * 0x9..0xE - Reserved for future use
2141 * 0xF - Not used */
2142 switch (format) {
2143 case TIMING_3D_FORMAT_HW_FRAME_PACKING:
2144 case TIMING_3D_FORMAT_SW_FRAME_PACKING:
2145 info_packet->sb[5] = (0x0 << 4);
2146 break;
2147
2148 case TIMING_3D_FORMAT_SIDE_BY_SIDE:
2149 case TIMING_3D_FORMAT_SBS_SW_PACKED:
2150 info_packet->sb[5] = (0x8 << 4);
2151 length = 6;
2152 break;
2153
2154 case TIMING_3D_FORMAT_TOP_AND_BOTTOM:
2155 case TIMING_3D_FORMAT_TB_SW_PACKED:
2156 info_packet->sb[5] = (0x6 << 4);
2157 break;
2158
2159 default:
2160 break;
2161 }
2162
2163 /*PB5: If PB4 is set to 0x1 (extended resolution format)
2164 * fill PB5 with the correct HDMI VIC code */
2165 if (hdmi_vic_mode)
4fa086b9 2166 info_packet->sb[5] = stream->timing.hdmi_vic;
4562236b
HW		 2167
2168 /* Header */
3e183c5f 2169 info_packet->hb0 = HDMI_INFOFRAME_TYPE_VENDOR; /* VSIF packet type. */
4562236b
HW		 2170 info_packet->hb1 = 0x01; /* Version */
2171
2172 /* 4 lower bits = Length, 4 higher bits = 0 (reserved) */
2173 info_packet->hb2 = (uint8_t) (length);
2174
2175 /* Calculate checksum */
2176 checksum = 0;
2177 checksum += info_packet->hb0;
2178 checksum += info_packet->hb1;
2179 checksum += info_packet->hb2;
2180
2181 for (i = 1; i <= length; i++)
2182 checksum += info_packet->sb[i];
2183
2184 info_packet->sb[0] = (uint8_t) (0x100 - checksum);
2185
2186 info_packet->valid = true;
2187}
2188
6e4d6bee
TC		 2189static void set_spd_info_packet(
2190 struct encoder_info_packet *info_packet,
0971c40e 2191 struct dc_stream_state *stream)
4562236b
HW		 2192{
2193 /* SPD info packet for FreeSync */
2194
2195 unsigned char checksum = 0;
2196 unsigned int idx, payload_size = 0;
2197
2198 /* Check if Freesync is supported. Return if false. If true,
2199 * set the corresponding bit in the info packet
2200 */
4fa086b9 2201 if (stream->freesync_ctx.supported == false)
4562236b
HW		 2202 return;
2203
2204 if (dc_is_hdmi_signal(stream->signal)) {
2205
2206 /* HEADER */
2207
2208 /* HB0 = Packet Type = 0x83 (Source Product
2209 * Descriptor InfoFrame)
2210 */
3e183c5f 2211 info_packet->hb0 = HDMI_INFOFRAME_TYPE_SPD;
4562236b
HW		 2212
2213 /* HB1 = Version = 0x01 */
2214 info_packet->hb1 = 0x01;
2215
2216 /* HB2 = [Bits 7:5 = 0] [Bits 4:0 = Length = 0x08] */
2217 info_packet->hb2 = 0x08;
2218
2219 payload_size = 0x08;
2220
2221 } else if (dc_is_dp_signal(stream->signal)) {
2222
2223 /* HEADER */
2224
2225 /* HB0 = Secondary-data Packet ID = 0 - Only non-zero
2226 * when used to associate audio related info packets
2227 */
2228 info_packet->hb0 = 0x00;
2229
2230 /* HB1 = Packet Type = 0x83 (Source Product
2231 * Descriptor InfoFrame)
2232 */
3e183c5f 2233 info_packet->hb1 = HDMI_INFOFRAME_TYPE_SPD;
4562236b
HW		 2234
2235 /* HB2 = [Bits 7:0 = Least significant eight bits -
2236 * For INFOFRAME, the value must be 1Bh]
2237 */
2238 info_packet->hb2 = 0x1B;
2239
2240 /* HB3 = [Bits 7:2 = INFOFRAME SDP Version Number = 0x1]
2241 * [Bits 1:0 = Most significant two bits = 0x00]
2242 */
2243 info_packet->hb3 = 0x04;
2244
2245 payload_size = 0x1B;
2246 }
2247
2248 /* PB1 = 0x1A (24bit AMD IEEE OUI (0x00001A) - Byte 0) */
2249 info_packet->sb[1] = 0x1A;
2250
2251 /* PB2 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 1) */
2252 info_packet->sb[2] = 0x00;
2253
2254 /* PB3 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 2) */
2255 info_packet->sb[3] = 0x00;
2256
2257 /* PB4 = Reserved */
2258 info_packet->sb[4] = 0x00;
2259
2260 /* PB5 = Reserved */
2261 info_packet->sb[5] = 0x00;
2262
2263 /* PB6 = [Bits 7:3 = Reserved] */
2264 info_packet->sb[6] = 0x00;
2265
4fa086b9 2266 if (stream->freesync_ctx.supported == true)
4562236b
HW		 2267 /* PB6 = [Bit 0 = FreeSync Supported] */
2268 info_packet->sb[6] |= 0x01;
2269
4fa086b9 2270 if (stream->freesync_ctx.enabled == true)
4562236b
HW		 2271 /* PB6 = [Bit 1 = FreeSync Enabled] */
2272 info_packet->sb[6] |= 0x02;
2273
4fa086b9 2274 if (stream->freesync_ctx.active == true)
4562236b
HW		 2275 /* PB6 = [Bit 2 = FreeSync Active] */
2276 info_packet->sb[6] |= 0x04;
2277
2278 /* PB7 = FreeSync Minimum refresh rate (Hz) */
4fa086b9 2279 info_packet->sb[7] = (unsigned char) (stream->freesync_ctx.
4562236b
HW		 2280 min_refresh_in_micro_hz / 1000000);
2281
2282 /* PB8 = FreeSync Maximum refresh rate (Hz)
2283 *
2284 * Note: We do not use the maximum capable refresh rate
2285 * of the panel, because we should never go above the field
2286 * rate of the mode timing set.
2287 */
4fa086b9 2288 info_packet->sb[8] = (unsigned char) (stream->freesync_ctx.
4562236b
HW		 2289 nominal_refresh_in_micro_hz / 1000000);
2290
2291 /* PB9 - PB27 = Reserved */
2292 for (idx = 9; idx <= 27; idx++)
2293 info_packet->sb[idx] = 0x00;
2294
2295 /* Calculate checksum */
2296 checksum += info_packet->hb0;
2297 checksum += info_packet->hb1;
2298 checksum += info_packet->hb2;
2299 checksum += info_packet->hb3;
2300
2301 for (idx = 1; idx <= payload_size; idx++)
2302 checksum += info_packet->sb[idx];
2303
2304 /* PB0 = Checksum (one byte complement) */
2305 info_packet->sb[0] = (unsigned char) (0x100 - checksum);
2306
2307 info_packet->valid = true;
2308}
2309
1646a6fe 2310static void set_hdr_static_info_packet(
6e4d6bee 2311 struct encoder_info_packet *info_packet,
3be5262e 2312 struct dc_plane_state *plane_state,
0971c40e 2313 struct dc_stream_state *stream)
1646a6fe 2314{
e5cf325b 2315 uint16_t i = 0;
1646a6fe 2316 enum signal_type signal = stream->signal;
e5cf325b
HW		 2317 struct dc_hdr_static_metadata hdr_metadata;
2318 uint32_t data;
1646a6fe 2319
3be5262e 2320 if (!plane_state)
1646a6fe
AW		 2321 return;
2322
3be5262e 2323 hdr_metadata = plane_state->hdr_static_ctx;
1646a6fe 2324
70063a59 2325 if (!hdr_metadata.hdr_supported)
10bff005
YS		 2326 return;
2327
1646a6fe
AW		 2328 if (dc_is_hdmi_signal(signal)) {
2329 info_packet->valid = true;
2330
2331 info_packet->hb0 = 0x87;
2332 info_packet->hb1 = 0x01;
2333 info_packet->hb2 = 0x1A;
2334 i = 1;
2335 } else if (dc_is_dp_signal(signal)) {
2336 info_packet->valid = true;
2337
2338 info_packet->hb0 = 0x00;
2339 info_packet->hb1 = 0x87;
2340 info_packet->hb2 = 0x1D;
2341 info_packet->hb3 = (0x13 << 2);
2342 i = 2;
2343 }
2344
1646a6fe
AW		 2345 data = hdr_metadata.is_hdr;
2346 info_packet->sb[i++] = data ? 0x02 : 0x00;
2347 info_packet->sb[i++] = 0x00;
2348
2349 data = hdr_metadata.chromaticity_green_x / 2;
2350 info_packet->sb[i++] = data & 0xFF;
2351 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2352
2353 data = hdr_metadata.chromaticity_green_y / 2;
2354 info_packet->sb[i++] = data & 0xFF;
2355 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2356
2357 data = hdr_metadata.chromaticity_blue_x / 2;
2358 info_packet->sb[i++] = data & 0xFF;
2359 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2360
2361 data = hdr_metadata.chromaticity_blue_y / 2;
2362 info_packet->sb[i++] = data & 0xFF;
2363 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2364
2365 data = hdr_metadata.chromaticity_red_x / 2;
2366 info_packet->sb[i++] = data & 0xFF;
2367 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2368
2369 data = hdr_metadata.chromaticity_red_y / 2;
2370 info_packet->sb[i++] = data & 0xFF;
2371 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2372
2373 data = hdr_metadata.chromaticity_white_point_x / 2;
2374 info_packet->sb[i++] = data & 0xFF;
2375 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2376
2377 data = hdr_metadata.chromaticity_white_point_y / 2;
2378 info_packet->sb[i++] = data & 0xFF;
2379 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2380
2381 data = hdr_metadata.max_luminance;
2382 info_packet->sb[i++] = data & 0xFF;
2383 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2384
2385 data = hdr_metadata.min_luminance;
2386 info_packet->sb[i++] = data & 0xFF;
2387 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2388
2389 data = hdr_metadata.maximum_content_light_level;
2390 info_packet->sb[i++] = data & 0xFF;
2391 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2392
2393 data = hdr_metadata.maximum_frame_average_light_level;
2394 info_packet->sb[i++] = data & 0xFF;
2395 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2396
2397 if (dc_is_hdmi_signal(signal)) {
2398 uint32_t checksum = 0;
2399
2400 checksum += info_packet->hb0;
2401 checksum += info_packet->hb1;
2402 checksum += info_packet->hb2;
2403
2404 for (i = 1; i <= info_packet->hb2; i++)
2405 checksum += info_packet->sb[i];
2406
2407 info_packet->sb[0] = 0x100 - checksum;
2408 } else if (dc_is_dp_signal(signal)) {
2409 info_packet->sb[0] = 0x01;
2410 info_packet->sb[1] = 0x1A;
2411 }
2412}
2413
6e4d6bee
TC		 2414static void set_vsc_info_packet(
2415 struct encoder_info_packet *info_packet,
0971c40e 2416 struct dc_stream_state *stream)
4562236b
HW		 2417{
2418 unsigned int vscPacketRevision = 0;
2419 unsigned int i;
2420
94267b3d 2421 if (stream->sink->link->psr_enabled) {
4562236b
HW		 2422 vscPacketRevision = 2;
2423 }
2424
2425 /* VSC packet not needed based on the features
2426 * supported by this DP display
2427 */
2428 if (vscPacketRevision == 0)
2429 return;
2430
2431 if (vscPacketRevision == 0x2) {
2432 /* Secondary-data Packet ID = 0*/
2433 info_packet->hb0 = 0x00;
2434 /* 07h - Packet Type Value indicating Video
2435 * Stream Configuration packet
2436 */
2437 info_packet->hb1 = 0x07;
2438 /* 02h = VSC SDP supporting 3D stereo and PSR
2439 * (applies to eDP v1.3 or higher).
2440 */
2441 info_packet->hb2 = 0x02;
2442 /* 08h = VSC packet supporting 3D stereo + PSR
2443 * (HB2 = 02h).
2444 */
2445 info_packet->hb3 = 0x08;
2446
2447 for (i = 0; i < 28; i++)
2448 info_packet->sb[i] = 0;
2449
2450 info_packet->valid = true;
2451 }
2452
2453 /*TODO: stereo 3D support and extend pixel encoding colorimetry*/
2454}
2455
f36cc577 2456void dc_resource_state_destruct(struct dc_state *context)
4562236b
HW		 2457{
2458 int i, j;
2459
ab2541b6 2460 for (i = 0; i < context->stream_count; i++) {
3be5262e
HW		 2461 for (j = 0; j < context->stream_status[i].plane_count; j++)
2462 dc_plane_state_release(
2463 context->stream_status[i].plane_states[j]);
4562236b 2464
3be5262e 2465 context->stream_status[i].plane_count = 0;
4fa086b9 2466 dc_stream_release(context->streams[i]);
ab2541b6 2467 context->streams[i] = NULL;
4562236b
HW		 2468 }
2469}
2470
2471/*
ab2541b6 2472 * Copy src_ctx into dst_ctx and retain all surfaces and streams referenced
4562236b
HW		 2473 * by the src_ctx
2474 */
f36cc577 2475void dc_resource_state_copy_construct(
608ac7bb
JZ		 2476 const struct dc_state *src_ctx,
2477 struct dc_state *dst_ctx)
4562236b
HW		 2478{
2479 int i, j;
8ee5702a 2480 struct kref refcount = dst_ctx->refcount;
4562236b
HW		 2481
2482 *dst_ctx = *src_ctx;
2483
a2b8659d 2484 for (i = 0; i < MAX_PIPES; i++) {
4562236b
HW		 2485 struct pipe_ctx *cur_pipe = &dst_ctx->res_ctx.pipe_ctx[i];
2486
2487 if (cur_pipe->top_pipe)
2488 cur_pipe->top_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
2489
2490 if (cur_pipe->bottom_pipe)
2491 cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
2492
2493 }
2494
ab2541b6 2495 for (i = 0; i < dst_ctx->stream_count; i++) {
4fa086b9 2496 dc_stream_retain(dst_ctx->streams[i]);
3be5262e
HW		 2497 for (j = 0; j < dst_ctx->stream_status[i].plane_count; j++)
2498 dc_plane_state_retain(
2499 dst_ctx->stream_status[i].plane_states[j]);
4562236b 2500 }
9a3afbb3
AG		 2501
2502 /* context refcount should not be overridden */
8ee5702a 2503 dst_ctx->refcount = refcount;
9a3afbb3 2504
4562236b
HW		 2505}
2506
2507struct clock_source *dc_resource_find_first_free_pll(
a2b8659d
TC		 2508 struct resource_context *res_ctx,
2509 const struct resource_pool *pool)
4562236b
HW		 2510{
2511 int i;
2512
a2b8659d 2513 for (i = 0; i < pool->clk_src_count; ++i) {
4562236b 2514 if (res_ctx->clock_source_ref_count[i] == 0)
a2b8659d 2515 return pool->clock_sources[i];
4562236b
HW		 2516 }
2517
2518 return NULL;
2519}
2520
2521void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
2522{
2523 enum signal_type signal = SIGNAL_TYPE_NONE;
96c50c0d 2524 struct encoder_info_frame *info = &pipe_ctx->stream_res.encoder_info_frame;
4562236b
HW		 2525
2526 /* default all packets to invalid */
6e4d6bee
TC		 2527 info->avi.valid = false;
2528 info->gamut.valid = false;
2529 info->vendor.valid = false;
630e3573 2530 info->spd.valid = false;
6e4d6bee
TC		 2531 info->hdrsmd.valid = false;
2532 info->vsc.valid = false;
4562236b
HW		 2533
2534 signal = pipe_ctx->stream->signal;
2535
2536 /* HDMi and DP have different info packets*/
2537 if (dc_is_hdmi_signal(signal)) {
6e4d6bee
TC		 2538 set_avi_info_frame(&info->avi, pipe_ctx);
2539
2540 set_vendor_info_packet(&info->vendor, pipe_ctx->stream);
2541
2542 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2543
2544 set_hdr_static_info_packet(&info->hdrsmd,
3be5262e 2545 pipe_ctx->plane_state, pipe_ctx->stream);
6e4d6bee 2546
a33fa99d 2547 } else if (dc_is_dp_signal(signal)) {
6e4d6bee
TC		 2548 set_vsc_info_packet(&info->vsc, pipe_ctx->stream);
2549
2550 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2551
2552 set_hdr_static_info_packet(&info->hdrsmd,
3be5262e 2553 pipe_ctx->plane_state, pipe_ctx->stream);
a33fa99d 2554 }
4562236b 2555
6e4d6bee 2556 patch_gamut_packet_checksum(&info->gamut);
4562236b
HW		 2557}
2558
2559enum dc_status resource_map_clock_resources(
fb3466a4 2560 const struct dc *dc,
608ac7bb 2561 struct dc_state *context,
1dc90497 2562 struct dc_stream_state *stream)
4562236b 2563{
4562236b 2564 /* acquire new resources */
1dc90497
AG		 2565 const struct resource_pool *pool = dc->res_pool;
2566 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(
2567 &context->res_ctx, stream);
ab2541b6 2568
1dc90497
AG		 2569 if (!pipe_ctx)
2570 return DC_ERROR_UNEXPECTED;
4562236b 2571
1dc90497
AG		 2572 if (dc_is_dp_signal(pipe_ctx->stream->signal)
2573 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)
2574 pipe_ctx->clock_source = pool->dp_clock_source;
2575 else {
2576 pipe_ctx->clock_source = NULL;
4562236b 2577
1dc90497 2578 if (!dc->config.disable_disp_pll_sharing)
4ed4e51b 2579 pipe_ctx->clock_source = resource_find_used_clk_src_for_sharing(
1dc90497
AG		 2580 &context->res_ctx,
2581 pipe_ctx);
4562236b 2582
1dc90497
AG		 2583 if (pipe_ctx->clock_source == NULL)
2584 pipe_ctx->clock_source =
2585 dc_resource_find_first_free_pll(
2586 &context->res_ctx,
2587 pool);
2588 }
4562236b 2589
1dc90497
AG		 2590 if (pipe_ctx->clock_source == NULL)
2591 return DC_NO_CLOCK_SOURCE_RESOURCE;
4562236b 2592
1dc90497
AG		 2593 resource_reference_clock_source(
2594 &context->res_ctx, pool,
2595 pipe_ctx->clock_source);
4562236b
HW		 2596
2597 return DC_OK;
2598}
2599
2600/*
2601 * Note: We need to disable output if clock sources change,
2602 * since bios does optimization and doesn't apply if changing
2603 * PHY when not already disabled.
2604 */
2605bool pipe_need_reprogram(
2606 struct pipe_ctx *pipe_ctx_old,
2607 struct pipe_ctx *pipe_ctx)
2608{
cfe4645e
DL		 2609 if (!pipe_ctx_old->stream)
2610 return false;
2611
4562236b
HW		 2612 if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink)
2613 return true;
2614
2615 if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal)
2616 return true;
2617
afaacef4 2618 if (pipe_ctx_old->stream_res.audio != pipe_ctx->stream_res.audio)
4562236b
HW		 2619 return true;
2620
2621 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source
2622 && pipe_ctx_old->stream != pipe_ctx->stream)
2623 return true;
2624
8e9c4c8c 2625 if (pipe_ctx_old->stream_res.stream_enc != pipe_ctx->stream_res.stream_enc)
4562236b
HW		 2626 return true;
2627
2628 if (is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2629 return true;
2630
2631
2632 return false;
2633}
529cad0f 2634
0971c40e 2635void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream,
529cad0f
DW		 2636 struct bit_depth_reduction_params *fmt_bit_depth)
2637{
4fa086b9 2638 enum dc_dither_option option = stream->dither_option;
529cad0f 2639 enum dc_pixel_encoding pixel_encoding =
4fa086b9 2640 stream->timing.pixel_encoding;
529cad0f
DW		 2641
2642 memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth));
2643
603767f9
TC		 2644 if (option == DITHER_OPTION_DEFAULT) {
2645 switch (stream->timing.display_color_depth) {
2646 case COLOR_DEPTH_666:
2647 option = DITHER_OPTION_SPATIAL6;
2648 break;
2649 case COLOR_DEPTH_888:
2650 option = DITHER_OPTION_SPATIAL8;
2651 break;
2652 case COLOR_DEPTH_101010:
2653 option = DITHER_OPTION_SPATIAL10;
2654 break;
2655 default:
2656 option = DITHER_OPTION_DISABLE;
2657 }
2658 }
2659
529cad0f
DW		 2660 if (option == DITHER_OPTION_DISABLE)
2661 return;
2662
2663 if (option == DITHER_OPTION_TRUN6) {
2664 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2665 fmt_bit_depth->flags.TRUNCATE_DEPTH = 0;
2666 } else if (option == DITHER_OPTION_TRUN8 ||
2667 option == DITHER_OPTION_TRUN8_SPATIAL6 ||
2668 option == DITHER_OPTION_TRUN8_FM6) {
2669 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2670 fmt_bit_depth->flags.TRUNCATE_DEPTH = 1;
2671 } else if (option == DITHER_OPTION_TRUN10 ||
2672 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
2673 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
2674 option == DITHER_OPTION_TRUN10_FM8 ||
2675 option == DITHER_OPTION_TRUN10_FM6 ||
2676 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2677 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2678 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2679 }
2680
2681 /* special case - Formatter can only reduce by 4 bits at most.
2682 * When reducing from 12 to 6 bits,
2683 * HW recommends we use trunc with round mode
2684 * (if we did nothing, trunc to 10 bits would be used)
2685 * note that any 12->10 bit reduction is ignored prior to DCE8,
2686 * as the input was 10 bits.
2687 */
2688 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2689 option == DITHER_OPTION_SPATIAL6 ||
2690 option == DITHER_OPTION_FM6) {
2691 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2692 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2693 fmt_bit_depth->flags.TRUNCATE_MODE = 1;
2694 }
2695
2696 /* spatial dither
2697 * note that spatial modes 1-3 are never used
2698 */
2699 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2700 option == DITHER_OPTION_SPATIAL6 ||
2701 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
2702 option == DITHER_OPTION_TRUN8_SPATIAL6) {
2703 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2704 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 0;
2705 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2706 fmt_bit_depth->flags.RGB_RANDOM =
2707 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2708 } else if (option == DITHER_OPTION_SPATIAL8_FRAME_RANDOM ||
2709 option == DITHER_OPTION_SPATIAL8 ||
2710 option == DITHER_OPTION_SPATIAL8_FM6 ||
2711 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
2712 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2713 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2714 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 1;
2715 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2716 fmt_bit_depth->flags.RGB_RANDOM =
2717 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2718 } else if (option == DITHER_OPTION_SPATIAL10_FRAME_RANDOM ||
2719 option == DITHER_OPTION_SPATIAL10 ||
2720 option == DITHER_OPTION_SPATIAL10_FM8 ||
2721 option == DITHER_OPTION_SPATIAL10_FM6) {
2722 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2723 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 2;
2724 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2725 fmt_bit_depth->flags.RGB_RANDOM =
2726 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2727 }
2728
2729 if (option == DITHER_OPTION_SPATIAL6 ||
2730 option == DITHER_OPTION_SPATIAL8 ||
2731 option == DITHER_OPTION_SPATIAL10) {
2732 fmt_bit_depth->flags.FRAME_RANDOM = 0;
2733 } else {
2734 fmt_bit_depth->flags.FRAME_RANDOM = 1;
2735 }
2736
2737 //////////////////////
2738 //// temporal dither
2739 //////////////////////
2740 if (option == DITHER_OPTION_FM6 ||
2741 option == DITHER_OPTION_SPATIAL8_FM6 ||
2742 option == DITHER_OPTION_SPATIAL10_FM6 ||
2743 option == DITHER_OPTION_TRUN10_FM6 ||
2744 option == DITHER_OPTION_TRUN8_FM6 ||
2745 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2746 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2747 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 0;
2748 } else if (option == DITHER_OPTION_FM8 ||
2749 option == DITHER_OPTION_SPATIAL10_FM8 ||
2750 option == DITHER_OPTION_TRUN10_FM8) {
2751 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2752 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 1;
2753 } else if (option == DITHER_OPTION_FM10) {
2754 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2755 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 2;
2756 }
2757
2758 fmt_bit_depth->pixel_encoding = pixel_encoding;
2759}
9345d987 2760
62c933f9 2761enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream)
9345d987 2762{
fb3466a4 2763 struct dc *core_dc = dc;
4fa086b9 2764 struct dc_link *link = stream->sink->link;
9345d987
AG		 2765 struct timing_generator *tg = core_dc->res_pool->timing_generators[0];
2766 enum dc_status res = DC_OK;
2767
4fa086b9 2768 calculate_phy_pix_clks(stream);
9345d987 2769
4fa086b9 2770 if (!tg->funcs->validate_timing(tg, &stream->timing))
9345d987
AG		 2771 res = DC_FAIL_CONTROLLER_VALIDATE;
2772
2773 if (res == DC_OK)
2774 if (!link->link_enc->funcs->validate_output_with_stream(
4fa086b9 2775 link->link_enc, stream))
9345d987
AG		 2776 res = DC_FAIL_ENC_VALIDATE;
2777
2778 /* TODO: validate audio ASIC caps, encoder */
2779
2780 if (res == DC_OK)
4fa086b9 2781 res = dc_link_validate_mode_timing(stream,
9345d987 2782 link,
4fa086b9 2783 &stream->timing);
9345d987 2784
62c933f9 2785 return res;
9345d987 2786}
792671d7 2787
62c933f9 2788enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state)
792671d7 2789{
62c933f9
YS		 2790 enum dc_status res = DC_OK;
2791
792671d7 2792 /* TODO For now validates pixel format only */
8e7095b9 2793 if (dc->res_pool->funcs->validate_plane)
62c933f9 2794 return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps);
792671d7 2795
62c933f9 2796 return res;
792671d7 2797}
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