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[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / display / dc / core / dc_resource.c
CommitLineData
4562236b 1/*
9ce6aae1 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4562236b
HW
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
4fc4dca8
SR
25
26#include <linux/slab.h>
27
4562236b
HW
28#include "dm_services.h"
29
30#include "resource.h"
31#include "include/irq_service_interface.h"
32#include "link_encoder.h"
33#include "stream_encoder.h"
34#include "opp.h"
35#include "timing_generator.h"
36#include "transform.h"
33d7598d
JL
37#include "dccg.h"
38#include "dchubbub.h"
d94585a0 39#include "dpp.h"
5ac3d3c9 40#include "core_types.h"
4562236b 41#include "set_mode_types.h"
4562236b 42#include "virtual/virtual_stream_encoder.h"
3b94a400 43#include "dpcd_defs.h"
4562236b
HW
44
45#include "dce80/dce80_resource.h"
46#include "dce100/dce100_resource.h"
47#include "dce110/dce110_resource.h"
48#include "dce112/dce112_resource.h"
b86a1aa3 49#if defined(CONFIG_DRM_AMD_DC_DCN)
ff5ef992
AD
50#include "dcn10/dcn10_resource.h"
51#endif
7ed4e635 52#include "dcn20/dcn20_resource.h"
e22ece54 53#include "dcn21/dcn21_resource.h"
2c8ad2d5 54#include "dce120/dce120_resource.h"
5d4b05dd
BL
55
56#define DC_LOGGER_INIT(logger)
57
4562236b
HW
58enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
59{
60 enum dce_version dc_version = DCE_VERSION_UNKNOWN;
61 switch (asic_id.chip_family) {
62
63 case FAMILY_CI:
4562236b
HW
64 dc_version = DCE_VERSION_8_0;
65 break;
ebfdf0d0
AD
66 case FAMILY_KV:
67 if (ASIC_REV_IS_KALINDI(asic_id.hw_internal_rev) ||
68 ASIC_REV_IS_BHAVANI(asic_id.hw_internal_rev) ||
69 ASIC_REV_IS_GODAVARI(asic_id.hw_internal_rev))
70 dc_version = DCE_VERSION_8_3;
71 else
72 dc_version = DCE_VERSION_8_1;
73 break;
4562236b
HW
74 case FAMILY_CZ:
75 dc_version = DCE_VERSION_11_0;
76 break;
77
78 case FAMILY_VI:
79 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
80 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
81 dc_version = DCE_VERSION_10_0;
82 break;
83 }
84 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
b264d345
JL
85 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
86 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
4562236b
HW
87 dc_version = DCE_VERSION_11_2;
88 }
0c75d5ac
JFZ
89 if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev))
90 dc_version = DCE_VERSION_11_22;
4562236b 91 break;
2c8ad2d5 92 case FAMILY_AI:
b8b6ce89
LL
93 if (ASICREV_IS_VEGA20_P(asic_id.hw_internal_rev))
94 dc_version = DCE_VERSION_12_1;
95 else
96 dc_version = DCE_VERSION_12_0;
2c8ad2d5 97 break;
b86a1aa3 98#if defined(CONFIG_DRM_AMD_DC_DCN)
ff5ef992
AD
99 case FAMILY_RV:
100 dc_version = DCN_VERSION_1_0;
0e3d73f1
BL
101 if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev))
102 dc_version = DCN_VERSION_1_01;
e22ece54
BL
103 if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev))
104 dc_version = DCN_VERSION_2_1;
ff5ef992
AD
105 break;
106#endif
7ed4e635 107
7ed4e635
HW
108 case FAMILY_NV:
109 dc_version = DCN_VERSION_2_0;
110 break;
4562236b
HW
111 default:
112 dc_version = DCE_VERSION_UNKNOWN;
113 break;
114 }
115 return dc_version;
116}
117
d9673c92
HW
118struct resource_pool *dc_create_resource_pool(struct dc *dc,
119 const struct dc_init_data *init_data,
120 enum dce_version dc_version)
4562236b 121{
5ac3d3c9 122 struct resource_pool *res_pool = NULL;
4562236b
HW
123
124 switch (dc_version) {
125 case DCE_VERSION_8_0:
7992a629 126 res_pool = dce80_create_resource_pool(
d9673c92 127 init_data->num_virtual_links, dc);
7992a629 128 break;
ebfdf0d0 129 case DCE_VERSION_8_1:
7992a629 130 res_pool = dce81_create_resource_pool(
d9673c92 131 init_data->num_virtual_links, dc);
7992a629 132 break;
ebfdf0d0 133 case DCE_VERSION_8_3:
7992a629 134 res_pool = dce83_create_resource_pool(
d9673c92 135 init_data->num_virtual_links, dc);
5ac3d3c9 136 break;
4562236b 137 case DCE_VERSION_10_0:
5ac3d3c9 138 res_pool = dce100_create_resource_pool(
d9673c92 139 init_data->num_virtual_links, dc);
5ac3d3c9 140 break;
4562236b 141 case DCE_VERSION_11_0:
5ac3d3c9 142 res_pool = dce110_create_resource_pool(
d9673c92
HW
143 init_data->num_virtual_links, dc,
144 init_data->asic_id);
5ac3d3c9 145 break;
4562236b 146 case DCE_VERSION_11_2:
0c75d5ac 147 case DCE_VERSION_11_22:
5ac3d3c9 148 res_pool = dce112_create_resource_pool(
d9673c92 149 init_data->num_virtual_links, dc);
5ac3d3c9 150 break;
2c8ad2d5 151 case DCE_VERSION_12_0:
b8b6ce89 152 case DCE_VERSION_12_1:
2c8ad2d5 153 res_pool = dce120_create_resource_pool(
d9673c92 154 init_data->num_virtual_links, dc);
2c8ad2d5 155 break;
ff5ef992 156
b86a1aa3 157#if defined(CONFIG_DRM_AMD_DC_DCN)
ff5ef992 158 case DCN_VERSION_1_0:
0e3d73f1 159 case DCN_VERSION_1_01:
d9673c92 160 res_pool = dcn10_create_resource_pool(init_data, dc);
ff5ef992 161 break;
3639fa68
ZF
162
163
7ed4e635
HW
164 case DCN_VERSION_2_0:
165 res_pool = dcn20_create_resource_pool(init_data, dc);
166 break;
e22ece54
BL
167 case DCN_VERSION_2_1:
168 res_pool = dcn21_create_resource_pool(init_data, dc);
169 break;
170#endif
7ed4e635 171
4562236b
HW
172 default:
173 break;
174 }
f49cfa27 175
5ac3d3c9 176 if (res_pool != NULL) {
9adc8050 177 if (dc->ctx->dc_bios->fw_info_valid) {
41a5a2a8 178 res_pool->ref_clocks.xtalin_clock_inKhz =
9adc8050 179 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
41a5a2a8 180 /* initialize with firmware data first, no all
181 * ASIC have DCCG SW component. FPGA or
182 * simulation need initialization of
183 * dccg_ref_clock_inKhz, dchub_ref_clock_inKhz
184 * with xtalin_clock_inKhz
185 */
186 res_pool->ref_clocks.dccg_ref_clock_inKhz =
187 res_pool->ref_clocks.xtalin_clock_inKhz;
188 res_pool->ref_clocks.dchub_ref_clock_inKhz =
189 res_pool->ref_clocks.xtalin_clock_inKhz;
190 } else
191 ASSERT_CRITICAL(false);
5ac3d3c9 192 }
4562236b 193
5ac3d3c9 194 return res_pool;
4562236b
HW
195}
196
fb3466a4 197void dc_destroy_resource_pool(struct dc *dc)
4562236b
HW
198{
199 if (dc) {
200 if (dc->res_pool)
201 dc->res_pool->funcs->destroy(&dc->res_pool);
202
d029810c 203 kfree(dc->hwseq);
4562236b
HW
204 }
205}
206
207static void update_num_audio(
208 const struct resource_straps *straps,
209 unsigned int *num_audio,
210 struct audio_support *aud_support)
211{
b8e9eb72
CL
212 aud_support->dp_audio = true;
213 aud_support->hdmi_audio_native = false;
214 aud_support->hdmi_audio_on_dongle = false;
215
4562236b 216 if (straps->hdmi_disable == 0) {
4562236b
HW
217 if (straps->dc_pinstraps_audio & 0x2) {
218 aud_support->hdmi_audio_on_dongle = true;
b8e9eb72 219 aud_support->hdmi_audio_native = true;
4562236b
HW
220 }
221 }
222
223 switch (straps->audio_stream_number) {
224 case 0: /* multi streams supported */
225 break;
226 case 1: /* multi streams not supported */
227 *num_audio = 1;
228 break;
229 default:
230 DC_ERR("DC: unexpected audio fuse!\n");
17a96033 231 }
4562236b
HW
232}
233
234bool resource_construct(
235 unsigned int num_virtual_links,
fb3466a4 236 struct dc *dc,
4562236b
HW
237 struct resource_pool *pool,
238 const struct resource_create_funcs *create_funcs)
239{
240 struct dc_context *ctx = dc->ctx;
241 const struct resource_caps *caps = pool->res_cap;
242 int i;
243 unsigned int num_audio = caps->num_audio;
244 struct resource_straps straps = {0};
245
246 if (create_funcs->read_dce_straps)
247 create_funcs->read_dce_straps(dc->ctx, &straps);
248
249 pool->audio_count = 0;
250 if (create_funcs->create_audio) {
251 /* find the total number of streams available via the
252 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
253 * registers (one for each pin) starting from pin 1
254 * up to the max number of audio pins.
255 * We stop on the first pin where
256 * PORT_CONNECTIVITY == 1 (as instructed by HW team).
257 */
258 update_num_audio(&straps, &num_audio, &pool->audio_support);
5feb9f07 259 for (i = 0; i < caps->num_audio; i++) {
4562236b
HW
260 struct audio *aud = create_funcs->create_audio(ctx, i);
261
262 if (aud == NULL) {
263 DC_ERR("DC: failed to create audio!\n");
264 return false;
265 }
4562236b
HW
266 if (!aud->funcs->endpoint_valid(aud)) {
267 aud->funcs->destroy(&aud);
268 break;
269 }
4562236b
HW
270 pool->audios[i] = aud;
271 pool->audio_count++;
272 }
273 }
274
275 pool->stream_enc_count = 0;
276 if (create_funcs->create_stream_encoder) {
277 for (i = 0; i < caps->num_stream_encoder; i++) {
278 pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx);
279 if (pool->stream_enc[i] == NULL)
280 DC_ERR("DC: failed to create stream_encoder!\n");
281 pool->stream_enc_count++;
282 }
283 }
929c3aaa 284
4176664b
CL
285 dc->caps.dynamic_audio = false;
286 if (pool->audio_count < pool->stream_enc_count) {
287 dc->caps.dynamic_audio = true;
288 }
4562236b
HW
289 for (i = 0; i < num_virtual_links; i++) {
290 pool->stream_enc[pool->stream_enc_count] =
291 virtual_stream_encoder_create(
292 ctx, ctx->dc_bios);
293 if (pool->stream_enc[pool->stream_enc_count] == NULL) {
294 DC_ERR("DC: failed to create stream_encoder!\n");
295 return false;
296 }
297 pool->stream_enc_count++;
298 }
299
300 dc->hwseq = create_funcs->create_hwseq(ctx);
301
302 return true;
303}
ad8960a6
ML
304static int find_matching_clock_source(
305 const struct resource_pool *pool,
306 struct clock_source *clock_source)
307{
4562236b 308
ad8960a6
ML
309 int i;
310
311 for (i = 0; i < pool->clk_src_count; i++) {
312 if (pool->clock_sources[i] == clock_source)
313 return i;
314 }
315 return -1;
316}
4562236b 317
21e67d4d 318void resource_unreference_clock_source(
4562236b 319 struct resource_context *res_ctx,
a2b8659d 320 const struct resource_pool *pool,
4a629536 321 struct clock_source *clock_source)
4562236b 322{
ad8960a6 323 int i = find_matching_clock_source(pool, clock_source);
4562236b 324
ad8960a6 325 if (i > -1)
4562236b
HW
326 res_ctx->clock_source_ref_count[i]--;
327
21e67d4d 328 if (pool->dp_clock_source == clock_source)
4562236b 329 res_ctx->dp_clock_source_ref_count--;
4562236b
HW
330}
331
332void resource_reference_clock_source(
333 struct resource_context *res_ctx,
a2b8659d 334 const struct resource_pool *pool,
4562236b
HW
335 struct clock_source *clock_source)
336{
ad8960a6 337 int i = find_matching_clock_source(pool, clock_source);
4562236b 338
ad8960a6 339 if (i > -1)
4562236b 340 res_ctx->clock_source_ref_count[i]++;
4562236b 341
a2b8659d 342 if (pool->dp_clock_source == clock_source)
4562236b
HW
343 res_ctx->dp_clock_source_ref_count++;
344}
345
ad8960a6
ML
346int resource_get_clock_source_reference(
347 struct resource_context *res_ctx,
348 const struct resource_pool *pool,
349 struct clock_source *clock_source)
350{
351 int i = find_matching_clock_source(pool, clock_source);
352
353 if (i > -1)
354 return res_ctx->clock_source_ref_count[i];
355
356 if (pool->dp_clock_source == clock_source)
357 return res_ctx->dp_clock_source_ref_count;
358
359 return -1;
360}
361
4562236b 362bool resource_are_streams_timing_synchronizable(
0971c40e
HW
363 struct dc_stream_state *stream1,
364 struct dc_stream_state *stream2)
4562236b 365{
4fa086b9 366 if (stream1->timing.h_total != stream2->timing.h_total)
4562236b
HW
367 return false;
368
4fa086b9 369 if (stream1->timing.v_total != stream2->timing.v_total)
4562236b
HW
370 return false;
371
4fa086b9
LSL
372 if (stream1->timing.h_addressable
373 != stream2->timing.h_addressable)
4562236b
HW
374 return false;
375
4fa086b9
LSL
376 if (stream1->timing.v_addressable
377 != stream2->timing.v_addressable)
4562236b
HW
378 return false;
379
380604e2
KC
380 if (stream1->timing.pix_clk_100hz
381 != stream2->timing.pix_clk_100hz)
4562236b
HW
382 return false;
383
3e27e10e
ML
384 if (stream1->clamping.c_depth != stream2->clamping.c_depth)
385 return false;
386
4562236b 387 if (stream1->phy_pix_clk != stream2->phy_pix_clk
7e2fe319
CL
388 && (!dc_is_dp_signal(stream1->signal)
389 || !dc_is_dp_signal(stream2->signal)))
4562236b
HW
390 return false;
391
d77f778e
CL
392 if (stream1->view_format != stream2->view_format)
393 return false;
394
0460f9ab
JL
395 if (stream1->ignore_msa_timing_param || stream2->ignore_msa_timing_param)
396 return false;
397
4562236b
HW
398 return true;
399}
3e27e10e
ML
400static bool is_dp_and_hdmi_sharable(
401 struct dc_stream_state *stream1,
402 struct dc_stream_state *stream2)
403{
404 if (stream1->ctx->dc->caps.disable_dp_clk_share)
405 return false;
406
407 if (stream1->clamping.c_depth != COLOR_DEPTH_888 ||
d77f778e 408 stream2->clamping.c_depth != COLOR_DEPTH_888)
43fbbe89 409 return false;
3e27e10e
ML
410
411 return true;
412
413}
4562236b
HW
414
415static bool is_sharable_clk_src(
416 const struct pipe_ctx *pipe_with_clk_src,
417 const struct pipe_ctx *pipe)
418{
419 if (pipe_with_clk_src->clock_source == NULL)
420 return false;
421
422 if (pipe_with_clk_src->stream->signal == SIGNAL_TYPE_VIRTUAL)
423 return false;
424
3e27e10e
ML
425 if (dc_is_dp_signal(pipe_with_clk_src->stream->signal) ||
426 (dc_is_dp_signal(pipe->stream->signal) &&
427 !is_dp_and_hdmi_sharable(pipe_with_clk_src->stream,
428 pipe->stream)))
4562236b
HW
429 return false;
430
431 if (dc_is_hdmi_signal(pipe_with_clk_src->stream->signal)
fc69009e 432 && dc_is_dual_link_signal(pipe->stream->signal))
4562236b
HW
433 return false;
434
435 if (dc_is_hdmi_signal(pipe->stream->signal)
fc69009e 436 && dc_is_dual_link_signal(pipe_with_clk_src->stream->signal))
4562236b
HW
437 return false;
438
439 if (!resource_are_streams_timing_synchronizable(
440 pipe_with_clk_src->stream, pipe->stream))
441 return false;
442
443 return true;
444}
445
446struct clock_source *resource_find_used_clk_src_for_sharing(
447 struct resource_context *res_ctx,
448 struct pipe_ctx *pipe_ctx)
449{
450 int i;
451
452 for (i = 0; i < MAX_PIPES; i++) {
453 if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx))
454 return res_ctx->pipe_ctx[i].clock_source;
455 }
456
457 return NULL;
458}
459
460static enum pixel_format convert_pixel_format_to_dalsurface(
461 enum surface_pixel_format surface_pixel_format)
462{
463 enum pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
464
465 switch (surface_pixel_format) {
466 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
467 dal_pixel_format = PIXEL_FORMAT_INDEX8;
468 break;
469 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
470 dal_pixel_format = PIXEL_FORMAT_RGB565;
471 break;
472 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
473 dal_pixel_format = PIXEL_FORMAT_RGB565;
474 break;
475 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
476 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
477 break;
8693049a 478 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
4562236b
HW
479 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
480 break;
481 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
482 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
483 break;
484 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
485 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
486 break;
487 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
488 dal_pixel_format = PIXEL_FORMAT_ARGB2101010_XRBIAS;
489 break;
490 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
491 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
492 dal_pixel_format = PIXEL_FORMAT_FP16;
493 break;
494 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
4562236b 495 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
87449a90 496 dal_pixel_format = PIXEL_FORMAT_420BPP8;
4562236b 497 break;
ffbcd19a
VP
498 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
499 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
87449a90 500 dal_pixel_format = PIXEL_FORMAT_420BPP10;
ffbcd19a 501 break;
4562236b
HW
502 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
503 default:
504 dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
505 break;
506 }
507 return dal_pixel_format;
508}
509
9b6067c0
DL
510static inline void get_vp_scan_direction(
511 enum dc_rotation_angle rotation,
512 bool horizontal_mirror,
513 bool *orthogonal_rotation,
514 bool *flip_vert_scan_dir,
515 bool *flip_horz_scan_dir)
4562236b 516{
9b6067c0
DL
517 *orthogonal_rotation = false;
518 *flip_vert_scan_dir = false;
519 *flip_horz_scan_dir = false;
520 if (rotation == ROTATION_ANGLE_180) {
521 *flip_vert_scan_dir = true;
522 *flip_horz_scan_dir = true;
523 } else if (rotation == ROTATION_ANGLE_90) {
524 *orthogonal_rotation = true;
525 *flip_horz_scan_dir = true;
526 } else if (rotation == ROTATION_ANGLE_270) {
527 *orthogonal_rotation = true;
528 *flip_vert_scan_dir = true;
529 }
530
531 if (horizontal_mirror)
532 *flip_horz_scan_dir = !*flip_horz_scan_dir;
4562236b
HW
533}
534
b2d0a103 535static void calculate_viewport(struct pipe_ctx *pipe_ctx)
4562236b 536{
3be5262e 537 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 538 const struct dc_stream_state *stream = pipe_ctx->stream;
6702a9ac 539 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
3be5262e 540 struct rect surf_src = plane_state->src_rect;
9b6067c0 541 struct rect clip, dest;
87449a90
AK
542 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
543 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
1fbd2cfc 544 bool pri_split = pipe_ctx->bottom_pipe &&
3be5262e 545 pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state;
1fbd2cfc 546 bool sec_split = pipe_ctx->top_pipe &&
3be5262e 547 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
9b6067c0 548 bool orthogonal_rotation, flip_y_start, flip_x_start;
83d40659 549
7f5c22d1
VP
550 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE ||
551 stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) {
7b779c99
VP
552 pri_split = false;
553 sec_split = false;
554 }
86006a7f 555
4562236b
HW
556 /* The actual clip is an intersection between stream
557 * source and surface clip
558 */
9b6067c0 559 dest = plane_state->dst_rect;
3be5262e
HW
560 clip.x = stream->src.x > plane_state->clip_rect.x ?
561 stream->src.x : plane_state->clip_rect.x;
4562236b 562
1fbd2cfc 563 clip.width = stream->src.x + stream->src.width <
3be5262e 564 plane_state->clip_rect.x + plane_state->clip_rect.width ?
1fbd2cfc 565 stream->src.x + stream->src.width - clip.x :
3be5262e 566 plane_state->clip_rect.x + plane_state->clip_rect.width - clip.x ;
4562236b 567
3be5262e
HW
568 clip.y = stream->src.y > plane_state->clip_rect.y ?
569 stream->src.y : plane_state->clip_rect.y;
4562236b 570
1fbd2cfc 571 clip.height = stream->src.y + stream->src.height <
3be5262e 572 plane_state->clip_rect.y + plane_state->clip_rect.height ?
1fbd2cfc 573 stream->src.y + stream->src.height - clip.y :
3be5262e 574 plane_state->clip_rect.y + plane_state->clip_rect.height - clip.y ;
4562236b 575
9b6067c0
DL
576 /*
577 * Need to calculate how scan origin is shifted in vp space
578 * to correctly rotate clip and dst
579 */
580 get_vp_scan_direction(
581 plane_state->rotation,
582 plane_state->horizontal_mirror,
583 &orthogonal_rotation,
584 &flip_y_start,
585 &flip_x_start);
586
587 if (orthogonal_rotation) {
588 swap(clip.x, clip.y);
589 swap(clip.width, clip.height);
590 swap(dest.x, dest.y);
591 swap(dest.width, dest.height);
592 }
593 if (flip_x_start) {
594 clip.x = dest.x + dest.width - clip.x - clip.width;
595 dest.x = 0;
596 }
597 if (flip_y_start) {
598 clip.y = dest.y + dest.height - clip.y - clip.height;
599 dest.y = 0;
600 }
601
86006a7f 602 /* offset = surf_src.ofs + (clip.ofs - surface->dst_rect.ofs) * scl_ratio
4562236b
HW
603 * num_pixels = clip.num_pix * scl_ratio
604 */
9b6067c0
DL
605 data->viewport.x = surf_src.x + (clip.x - dest.x) * surf_src.width / dest.width;
606 data->viewport.width = clip.width * surf_src.width / dest.width;
607
608 data->viewport.y = surf_src.y + (clip.y - dest.y) * surf_src.height / dest.height;
609 data->viewport.height = clip.height * surf_src.height / dest.height;
610
611 /* Handle split */
612 if (pri_split || sec_split) {
613 if (orthogonal_rotation) {
614 if (flip_y_start != pri_split)
615 data->viewport.height /= 2;
616 else {
617 data->viewport.y += data->viewport.height / 2;
618 /* Ceil offset pipe */
619 data->viewport.height = (data->viewport.height + 1) / 2;
620 }
621 } else {
622 if (flip_x_start != pri_split)
623 data->viewport.width /= 2;
624 else {
625 data->viewport.x += data->viewport.width / 2;
626 /* Ceil offset pipe */
627 data->viewport.width = (data->viewport.width + 1) / 2;
628 }
629 }
630 }
9b5349f7 631
b2d0a103
DL
632 /* Round down, compensate in init */
633 data->viewport_c.x = data->viewport.x / vpc_div;
634 data->viewport_c.y = data->viewport.y / vpc_div;
9b6067c0
DL
635 data->inits.h_c = (data->viewport.x % vpc_div) != 0 ? dc_fixpt_half : dc_fixpt_zero;
636 data->inits.v_c = (data->viewport.y % vpc_div) != 0 ? dc_fixpt_half : dc_fixpt_zero;
637
b2d0a103
DL
638 /* Round up, assume original video size always even dimensions */
639 data->viewport_c.width = (data->viewport.width + vpc_div - 1) / vpc_div;
640 data->viewport_c.height = (data->viewport.height + vpc_div - 1) / vpc_div;
4562236b
HW
641}
642
9b6067c0 643static void calculate_recout(struct pipe_ctx *pipe_ctx)
4562236b 644{
3be5262e 645 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 646 const struct dc_stream_state *stream = pipe_ctx->stream;
3be5262e 647 struct rect surf_clip = plane_state->clip_rect;
0c31a821
YS
648 bool pri_split = pipe_ctx->bottom_pipe &&
649 pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state;
650 bool sec_split = pipe_ctx->top_pipe &&
651 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
b0131391 652 bool top_bottom_split = stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM;
4562236b 653
6702a9ac 654 pipe_ctx->plane_res.scl_data.recout.x = stream->dst.x;
4fa086b9 655 if (stream->src.x < surf_clip.x)
6702a9ac 656 pipe_ctx->plane_res.scl_data.recout.x += (surf_clip.x
4fa086b9
LSL
657 - stream->src.x) * stream->dst.width
658 / stream->src.width;
4562236b 659
6702a9ac 660 pipe_ctx->plane_res.scl_data.recout.width = surf_clip.width *
4fa086b9 661 stream->dst.width / stream->src.width;
6702a9ac 662 if (pipe_ctx->plane_res.scl_data.recout.width + pipe_ctx->plane_res.scl_data.recout.x >
4fa086b9 663 stream->dst.x + stream->dst.width)
6702a9ac 664 pipe_ctx->plane_res.scl_data.recout.width =
4fa086b9 665 stream->dst.x + stream->dst.width
6702a9ac 666 - pipe_ctx->plane_res.scl_data.recout.x;
4562236b 667
6702a9ac 668 pipe_ctx->plane_res.scl_data.recout.y = stream->dst.y;
4fa086b9 669 if (stream->src.y < surf_clip.y)
6702a9ac 670 pipe_ctx->plane_res.scl_data.recout.y += (surf_clip.y
4fa086b9
LSL
671 - stream->src.y) * stream->dst.height
672 / stream->src.height;
4562236b 673
6702a9ac 674 pipe_ctx->plane_res.scl_data.recout.height = surf_clip.height *
4fa086b9 675 stream->dst.height / stream->src.height;
6702a9ac 676 if (pipe_ctx->plane_res.scl_data.recout.height + pipe_ctx->plane_res.scl_data.recout.y >
4fa086b9 677 stream->dst.y + stream->dst.height)
6702a9ac 678 pipe_ctx->plane_res.scl_data.recout.height =
4fa086b9 679 stream->dst.y + stream->dst.height
6702a9ac 680 - pipe_ctx->plane_res.scl_data.recout.y;
b2d0a103 681
9b6067c0 682 /* Handle h & v split, handle rotation using viewport */
b0131391
DL
683 if (sec_split && top_bottom_split) {
684 pipe_ctx->plane_res.scl_data.recout.y +=
685 pipe_ctx->plane_res.scl_data.recout.height / 2;
0c31a821 686 /* Floor primary pipe, ceil 2ndary pipe */
b0131391
DL
687 pipe_ctx->plane_res.scl_data.recout.height =
688 (pipe_ctx->plane_res.scl_data.recout.height + 1) / 2;
689 } else if (pri_split && top_bottom_split)
0c31a821 690 pipe_ctx->plane_res.scl_data.recout.height /= 2;
9b6067c0
DL
691 else if (sec_split) {
692 pipe_ctx->plane_res.scl_data.recout.x +=
693 pipe_ctx->plane_res.scl_data.recout.width / 2;
694 /* Ceil offset pipe */
695 pipe_ctx->plane_res.scl_data.recout.width =
696 (pipe_ctx->plane_res.scl_data.recout.width + 1) / 2;
697 } else if (pri_split)
698 pipe_ctx->plane_res.scl_data.recout.width /= 2;
4562236b
HW
699}
700
b2d0a103 701static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)
4562236b 702{
3be5262e 703 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 704 const struct dc_stream_state *stream = pipe_ctx->stream;
3be5262e 705 struct rect surf_src = plane_state->src_rect;
4fa086b9
LSL
706 const int in_w = stream->src.width;
707 const int in_h = stream->src.height;
708 const int out_w = stream->dst.width;
709 const int out_h = stream->dst.height;
4562236b 710
9b6067c0 711 /*Swap surf_src height and width since scaling ratios are in recout rotation*/
3be5262e
HW
712 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
713 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
9b6067c0 714 swap(surf_src.height, surf_src.width);
86006a7f 715
eb0e5154 716 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_from_fraction(
86006a7f 717 surf_src.width,
3be5262e 718 plane_state->dst_rect.width);
eb0e5154 719 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction(
86006a7f 720 surf_src.height,
3be5262e 721 plane_state->dst_rect.height);
4562236b 722
4fa086b9 723 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
6702a9ac 724 pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2;
4fa086b9 725 else if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
6702a9ac 726 pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2;
4562236b 727
6702a9ac
HW
728 pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64(
729 pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h);
730 pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64(
731 pipe_ctx->plane_res.scl_data.ratios.horz.value * in_w, out_w);
4562236b 732
6702a9ac
HW
733 pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz;
734 pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert;
4562236b 735
6702a9ac
HW
736 if (pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP8
737 || pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP10) {
738 pipe_ctx->plane_res.scl_data.ratios.horz_c.value /= 2;
739 pipe_ctx->plane_res.scl_data.ratios.vert_c.value /= 2;
4562236b 740 }
0002d3ac
DL
741 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_truncate(
742 pipe_ctx->plane_res.scl_data.ratios.horz, 19);
743 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_truncate(
744 pipe_ctx->plane_res.scl_data.ratios.vert, 19);
745 pipe_ctx->plane_res.scl_data.ratios.horz_c = dc_fixpt_truncate(
746 pipe_ctx->plane_res.scl_data.ratios.horz_c, 19);
747 pipe_ctx->plane_res.scl_data.ratios.vert_c = dc_fixpt_truncate(
748 pipe_ctx->plane_res.scl_data.ratios.vert_c, 19);
4562236b
HW
749}
750
9b6067c0
DL
751static inline void adjust_vp_and_init_for_seamless_clip(
752 bool flip_scan_dir,
753 int recout_skip,
754 int src_size,
755 int taps,
756 struct fixed31_32 ratio,
757 struct fixed31_32 *init,
758 int *vp_offset,
759 int *vp_size)
b2d0a103 760{
9b6067c0 761 if (!flip_scan_dir) {
9a08f51f 762 /* Adjust for viewport end clip-off */
9b6067c0
DL
763 if ((*vp_offset + *vp_size) < src_size) {
764 int vp_clip = src_size - *vp_size - *vp_offset;
765 int int_part = dc_fixpt_floor(dc_fixpt_sub(*init, ratio));
9a08f51f
DL
766
767 int_part = int_part > 0 ? int_part : 0;
9b6067c0 768 *vp_size += int_part < vp_clip ? int_part : vp_clip;
9a08f51f 769 }
b2d0a103 770
9a08f51f 771 /* Adjust for non-0 viewport offset */
9b6067c0 772 if (*vp_offset) {
9a08f51f
DL
773 int int_part;
774
9b6067c0
DL
775 *init = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_skip));
776 int_part = dc_fixpt_floor(*init) - *vp_offset;
777 if (int_part < taps) {
778 int int_adj = *vp_offset >= (taps - int_part) ?
779 (taps - int_part) : *vp_offset;
780 *vp_offset -= int_adj;
781 *vp_size += int_adj;
9a08f51f 782 int_part += int_adj;
9b6067c0
DL
783 } else if (int_part > taps) {
784 *vp_offset += int_part - taps;
785 *vp_size -= int_part - taps;
786 int_part = taps;
9a08f51f 787 }
9b6067c0
DL
788 init->value &= 0xffffffff;
789 *init = dc_fixpt_add_int(*init, int_part);
9a08f51f
DL
790 }
791 } else {
792 /* Adjust for non-0 viewport offset */
9b6067c0
DL
793 if (*vp_offset) {
794 int int_part = dc_fixpt_floor(dc_fixpt_sub(*init, ratio));
b2d0a103 795
9a08f51f 796 int_part = int_part > 0 ? int_part : 0;
9b6067c0
DL
797 *vp_size += int_part < *vp_offset ? int_part : *vp_offset;
798 *vp_offset -= int_part < *vp_offset ? int_part : *vp_offset;
9a08f51f 799 }
b2d0a103 800
9a08f51f 801 /* Adjust for viewport end clip-off */
9b6067c0 802 if ((*vp_offset + *vp_size) < src_size) {
9a08f51f 803 int int_part;
9b6067c0 804 int end_offset = src_size - *vp_offset - *vp_size;
9a08f51f
DL
805
806 /*
807 * this is init if vp had no offset, keep in mind this is from the
808 * right side of vp due to scan direction
809 */
9b6067c0 810 *init = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_skip));
9a08f51f
DL
811 /*
812 * this is the difference between first pixel of viewport available to read
813 * and init position, takning into account scan direction
814 */
9b6067c0
DL
815 int_part = dc_fixpt_floor(*init) - end_offset;
816 if (int_part < taps) {
817 int int_adj = end_offset >= (taps - int_part) ?
818 (taps - int_part) : end_offset;
819 *vp_size += int_adj;
9a08f51f 820 int_part += int_adj;
9b6067c0
DL
821 } else if (int_part > taps) {
822 *vp_size += int_part - taps;
823 int_part = taps;
9a08f51f 824 }
9b6067c0
DL
825 init->value &= 0xffffffff;
826 *init = dc_fixpt_add_int(*init, int_part);
b2d0a103 827 }
b2d0a103 828 }
9b6067c0 829}
9a08f51f 830
9b6067c0
DL
831static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx)
832{
833 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
834 const struct dc_stream_state *stream = pipe_ctx->stream;
835 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
836 struct rect src = pipe_ctx->plane_state->src_rect;
837 int recout_skip_h, recout_skip_v, surf_size_h, surf_size_v;
838 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
839 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
840 bool orthogonal_rotation, flip_vert_scan_dir, flip_horz_scan_dir;
9a08f51f 841
9b6067c0
DL
842 /*
843 * Need to calculate the scan direction for viewport to make adjustments
844 */
845 get_vp_scan_direction(
846 plane_state->rotation,
847 plane_state->horizontal_mirror,
848 &orthogonal_rotation,
849 &flip_vert_scan_dir,
850 &flip_horz_scan_dir);
851
852 /* Calculate src rect rotation adjusted to recout space */
853 surf_size_h = src.x + src.width;
854 surf_size_v = src.y + src.height;
855 if (flip_horz_scan_dir)
856 src.x = 0;
857 if (flip_vert_scan_dir)
858 src.y = 0;
859 if (orthogonal_rotation) {
860 swap(src.x, src.y);
861 swap(src.width, src.height);
862 }
9a08f51f 863
9b6067c0
DL
864 /* Recout matching initial vp offset = recout_offset - (stream dst offset +
865 * ((surf dst offset - stream src offset) * 1/ stream scaling ratio)
866 * - (surf surf_src offset * 1/ full scl ratio))
867 */
868 recout_skip_h = data->recout.x - (stream->dst.x + (plane_state->dst_rect.x - stream->src.x)
869 * stream->dst.width / stream->src.width -
870 src.x * plane_state->dst_rect.width / src.width
871 * stream->dst.width / stream->src.width);
872 recout_skip_v = data->recout.y - (stream->dst.y + (plane_state->dst_rect.y - stream->src.y)
873 * stream->dst.height / stream->src.height -
874 src.y * plane_state->dst_rect.height / src.height
875 * stream->dst.height / stream->src.height);
876 if (orthogonal_rotation)
877 swap(recout_skip_h, recout_skip_v);
878 /*
879 * Init calculated according to formula:
880 * init = (scaling_ratio + number_of_taps + 1) / 2
881 * init_bot = init + scaling_ratio
882 * init_c = init + truncated_vp_c_offset(from calculate viewport)
883 */
884 data->inits.h = dc_fixpt_truncate(dc_fixpt_div_int(
885 dc_fixpt_add_int(data->ratios.horz, data->taps.h_taps + 1), 2), 19);
b2d0a103 886
9b6067c0
DL
887 data->inits.h_c = dc_fixpt_truncate(dc_fixpt_add(data->inits.h_c, dc_fixpt_div_int(
888 dc_fixpt_add_int(data->ratios.horz_c, data->taps.h_taps_c + 1), 2)), 19);
9a08f51f 889
9b6067c0
DL
890 data->inits.v = dc_fixpt_truncate(dc_fixpt_div_int(
891 dc_fixpt_add_int(data->ratios.vert, data->taps.v_taps + 1), 2), 19);
9a08f51f 892
9b6067c0
DL
893 data->inits.v_c = dc_fixpt_truncate(dc_fixpt_add(data->inits.v_c, dc_fixpt_div_int(
894 dc_fixpt_add_int(data->ratios.vert_c, data->taps.v_taps_c + 1), 2)), 19);
9a08f51f 895
9b6067c0
DL
896 /*
897 * Taps, inits and scaling ratios are in recout space need to rotate
898 * to viewport rotation before adjustment
899 */
900 adjust_vp_and_init_for_seamless_clip(
901 flip_horz_scan_dir,
902 recout_skip_h,
903 surf_size_h,
904 orthogonal_rotation ? data->taps.v_taps : data->taps.h_taps,
905 orthogonal_rotation ? data->ratios.vert : data->ratios.horz,
906 orthogonal_rotation ? &data->inits.v : &data->inits.h,
907 &data->viewport.x,
908 &data->viewport.width);
909 adjust_vp_and_init_for_seamless_clip(
910 flip_horz_scan_dir,
911 recout_skip_h,
912 surf_size_h / vpc_div,
913 orthogonal_rotation ? data->taps.v_taps_c : data->taps.h_taps_c,
914 orthogonal_rotation ? data->ratios.vert_c : data->ratios.horz_c,
915 orthogonal_rotation ? &data->inits.v_c : &data->inits.h_c,
916 &data->viewport_c.x,
917 &data->viewport_c.width);
918 adjust_vp_and_init_for_seamless_clip(
919 flip_vert_scan_dir,
920 recout_skip_v,
921 surf_size_v,
922 orthogonal_rotation ? data->taps.h_taps : data->taps.v_taps,
923 orthogonal_rotation ? data->ratios.horz : data->ratios.vert,
924 orthogonal_rotation ? &data->inits.h : &data->inits.v,
925 &data->viewport.y,
926 &data->viewport.height);
927 adjust_vp_and_init_for_seamless_clip(
928 flip_vert_scan_dir,
929 recout_skip_v,
930 surf_size_v / vpc_div,
931 orthogonal_rotation ? data->taps.h_taps_c : data->taps.v_taps_c,
932 orthogonal_rotation ? data->ratios.horz_c : data->ratios.vert_c,
933 orthogonal_rotation ? &data->inits.h_c : &data->inits.v_c,
934 &data->viewport_c.y,
935 &data->viewport_c.height);
b2d0a103
DL
936
937 /* Interlaced inits based on final vert inits */
eb0e5154
DL
938 data->inits.v_bot = dc_fixpt_add(data->inits.v, data->ratios.vert);
939 data->inits.v_c_bot = dc_fixpt_add(data->inits.v_c, data->ratios.vert_c);
1fbd2cfc 940
b2d0a103 941}
3b733278 942
4ef0b9d0 943static void calculate_integer_scaling(struct pipe_ctx *pipe_ctx)
3b733278 944{
00ada9d1 945 unsigned int integer_multiple = 1;
3b733278 946
00ada9d1 947 if (pipe_ctx->plane_state->scaling_quality.integer_scaling) {
3b733278 948 // calculate maximum # of replication of src onto addressable
00ada9d1 949 integer_multiple = min(
3b733278
RA
950 pipe_ctx->stream->timing.h_addressable / pipe_ctx->stream->src.width,
951 pipe_ctx->stream->timing.v_addressable / pipe_ctx->stream->src.height);
952
953 //scale dst
954 pipe_ctx->stream->dst.width = integer_multiple * pipe_ctx->stream->src.width;
955 pipe_ctx->stream->dst.height = integer_multiple * pipe_ctx->stream->src.height;
956
957 //center dst onto addressable
958 pipe_ctx->stream->dst.x = (pipe_ctx->stream->timing.h_addressable - pipe_ctx->stream->dst.width)/2;
959 pipe_ctx->stream->dst.y = (pipe_ctx->stream->timing.v_addressable - pipe_ctx->stream->dst.height)/2;
3b733278 960
00ada9d1 961 //We are guaranteed that we are scaling in integer ratio
3b733278
RA
962 pipe_ctx->plane_state->scaling_quality.v_taps = 1;
963 pipe_ctx->plane_state->scaling_quality.h_taps = 1;
964 pipe_ctx->plane_state->scaling_quality.v_taps_c = 1;
965 pipe_ctx->plane_state->scaling_quality.h_taps_c = 1;
966 }
967}
968
b2d0a103 969bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
4562236b 970{
3be5262e 971 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
4fa086b9 972 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
b2d0a103 973 bool res = false;
5d4b05dd 974 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
4562236b
HW
975 /* Important: scaling ratio calculation requires pixel format,
976 * lb depth calculation requires recout and taps require scaling ratios.
b2d0a103 977 * Inits require viewport, taps, ratios and recout of split pipe
4562236b 978 */
6702a9ac 979 pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface(
3be5262e 980 pipe_ctx->plane_state->format);
b2d0a103 981
3b733278
RA
982 calculate_integer_scaling(pipe_ctx);
983
b2d0a103 984 calculate_scaling_ratios(pipe_ctx);
4562236b 985
b2d0a103 986 calculate_viewport(pipe_ctx);
4562236b 987
6702a9ac 988 if (pipe_ctx->plane_res.scl_data.viewport.height < 16 || pipe_ctx->plane_res.scl_data.viewport.width < 16)
4562236b
HW
989 return false;
990
9b6067c0 991 calculate_recout(pipe_ctx);
4562236b
HW
992
993 /**
994 * Setting line buffer pixel depth to 24bpp yields banding
995 * on certain displays, such as the Sharp 4k
996 */
6702a9ac 997 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
4562236b 998
199e458a 999 pipe_ctx->plane_res.scl_data.recout.x += timing->h_border_left;
58bb0e63 1000 pipe_ctx->plane_res.scl_data.recout.y += timing->v_border_top;
199e458a 1001
58bb0e63
AJ
1002 pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right;
1003 pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable + timing->v_border_top + timing->v_border_bottom;
1b6c8067 1004
4562236b 1005 /* Taps calculations */
d94585a0
YHL
1006 if (pipe_ctx->plane_res.xfm != NULL)
1007 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
1008 pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
1009
1010 if (pipe_ctx->plane_res.dpp != NULL)
1011 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
1012 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
f7938bc0 1013
f7938bc0 1014
4562236b
HW
1015 if (!res) {
1016 /* Try 24 bpp linebuffer */
6702a9ac 1017 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP;
4562236b 1018
1b6c8067
BL
1019 if (pipe_ctx->plane_res.xfm != NULL)
1020 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
1021 pipe_ctx->plane_res.xfm,
1022 &pipe_ctx->plane_res.scl_data,
1023 &plane_state->scaling_quality);
1024
1025 if (pipe_ctx->plane_res.dpp != NULL)
1026 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
1027 pipe_ctx->plane_res.dpp,
1028 &pipe_ctx->plane_res.scl_data,
1029 &plane_state->scaling_quality);
4562236b
HW
1030 }
1031
b2d0a103 1032 if (res)
1fbd2cfc 1033 /* May need to re-check lb size after this in some obscure scenario */
9b6067c0 1034 calculate_inits_and_adj_vp(pipe_ctx);
b2d0a103 1035
1296423b 1036 DC_LOG_SCALER(
4562236b
HW
1037 "%s: Viewport:\nheight:%d width:%d x:%d "
1038 "y:%d\n dst_rect:\nheight:%d width:%d x:%d "
1039 "y:%d\n",
1040 __func__,
6702a9ac
HW
1041 pipe_ctx->plane_res.scl_data.viewport.height,
1042 pipe_ctx->plane_res.scl_data.viewport.width,
1043 pipe_ctx->plane_res.scl_data.viewport.x,
1044 pipe_ctx->plane_res.scl_data.viewport.y,
3be5262e
HW
1045 plane_state->dst_rect.height,
1046 plane_state->dst_rect.width,
1047 plane_state->dst_rect.x,
1048 plane_state->dst_rect.y);
4562236b
HW
1049
1050 return res;
1051}
1052
1053
1054enum dc_status resource_build_scaling_params_for_context(
fb3466a4 1055 const struct dc *dc,
608ac7bb 1056 struct dc_state *context)
4562236b
HW
1057{
1058 int i;
1059
1060 for (i = 0; i < MAX_PIPES; i++) {
3be5262e 1061 if (context->res_ctx.pipe_ctx[i].plane_state != NULL &&
4562236b 1062 context->res_ctx.pipe_ctx[i].stream != NULL)
b2d0a103 1063 if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i]))
f84a8161 1064 return DC_FAIL_SCALING;
4562236b
HW
1065 }
1066
1067 return DC_OK;
1068}
1069
a2b8659d
TC
1070struct pipe_ctx *find_idle_secondary_pipe(
1071 struct resource_context *res_ctx,
5581192d
JL
1072 const struct resource_pool *pool,
1073 const struct pipe_ctx *primary_pipe)
4562236b
HW
1074{
1075 int i;
1076 struct pipe_ctx *secondary_pipe = NULL;
1077
1078 /*
5581192d
JL
1079 * We add a preferred pipe mapping to avoid the chance that
1080 * MPCCs already in use will need to be reassigned to other trees.
1081 * For example, if we went with the strict, assign backwards logic:
1082 *
1083 * (State 1)
1084 * Display A on, no surface, top pipe = 0
1085 * Display B on, no surface, top pipe = 1
1086 *
1087 * (State 2)
1088 * Display A on, no surface, top pipe = 0
1089 * Display B on, surface enable, top pipe = 1, bottom pipe = 5
1090 *
1091 * (State 3)
1092 * Display A on, surface enable, top pipe = 0, bottom pipe = 5
1093 * Display B on, surface enable, top pipe = 1, bottom pipe = 4
1094 *
1095 * The state 2->3 transition requires remapping MPCC 5 from display B
1096 * to display A.
1097 *
1098 * However, with the preferred pipe logic, state 2 would look like:
1099 *
1100 * (State 2)
1101 * Display A on, no surface, top pipe = 0
1102 * Display B on, surface enable, top pipe = 1, bottom pipe = 4
1103 *
1104 * This would then cause 2->3 to not require remapping any MPCCs.
4562236b 1105 */
5581192d
JL
1106 if (primary_pipe) {
1107 int preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx;
1108 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
1109 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
1110 secondary_pipe->pipe_idx = preferred_pipe_idx;
4562236b
HW
1111 }
1112 }
1113
5581192d
JL
1114 /*
1115 * search backwards for the second pipe to keep pipe
1116 * assignment more consistent
1117 */
1118 if (!secondary_pipe)
1119 for (i = pool->pipe_count - 1; i >= 0; i--) {
1120 if (res_ctx->pipe_ctx[i].stream == NULL) {
1121 secondary_pipe = &res_ctx->pipe_ctx[i];
1122 secondary_pipe->pipe_idx = i;
1123 break;
1124 }
1125 }
4562236b
HW
1126
1127 return secondary_pipe;
1128}
1129
1130struct pipe_ctx *resource_get_head_pipe_for_stream(
1131 struct resource_context *res_ctx,
0971c40e 1132 struct dc_stream_state *stream)
4562236b
HW
1133{
1134 int i;
22498036 1135
a2b8659d 1136 for (i = 0; i < MAX_PIPES; i++) {
b1f6d01c
DL
1137 if (res_ctx->pipe_ctx[i].stream == stream
1138 && !res_ctx->pipe_ctx[i].top_pipe
22498036 1139 && !res_ctx->pipe_ctx[i].prev_odm_pipe)
4562236b 1140 return &res_ctx->pipe_ctx[i];
4562236b
HW
1141 }
1142 return NULL;
1143}
1144
b1f6d01c 1145static struct pipe_ctx *resource_get_tail_pipe(
19f89e23 1146 struct resource_context *res_ctx,
b1f6d01c 1147 struct pipe_ctx *head_pipe)
19f89e23 1148{
b1f6d01c 1149 struct pipe_ctx *tail_pipe;
19f89e23
AG
1150
1151 tail_pipe = head_pipe->bottom_pipe;
1152
1153 while (tail_pipe) {
1154 head_pipe = tail_pipe;
1155 tail_pipe = tail_pipe->bottom_pipe;
1156 }
1157
1158 return head_pipe;
1159}
1160
4562236b 1161/*
ab2541b6
AC
1162 * A free_pipe for a stream is defined here as a pipe
1163 * that has no surface attached yet
4562236b 1164 */
b1f6d01c 1165static struct pipe_ctx *acquire_free_pipe_for_head(
608ac7bb 1166 struct dc_state *context,
a2b8659d 1167 const struct resource_pool *pool,
b1f6d01c 1168 struct pipe_ctx *head_pipe)
4562236b
HW
1169{
1170 int i;
745cc746 1171 struct resource_context *res_ctx = &context->res_ctx;
4562236b 1172
3be5262e 1173 if (!head_pipe->plane_state)
4562236b
HW
1174 return head_pipe;
1175
1176 /* Re-use pipe already acquired for this stream if available*/
a2b8659d 1177 for (i = pool->pipe_count - 1; i >= 0; i--) {
b1f6d01c 1178 if (res_ctx->pipe_ctx[i].stream == head_pipe->stream &&
3be5262e 1179 !res_ctx->pipe_ctx[i].plane_state) {
4562236b
HW
1180 return &res_ctx->pipe_ctx[i];
1181 }
1182 }
1183
1184 /*
1185 * At this point we have no re-useable pipe for this stream and we need
1186 * to acquire an idle one to satisfy the request
1187 */
1188
a2b8659d 1189 if (!pool->funcs->acquire_idle_pipe_for_layer)
4562236b
HW
1190 return NULL;
1191
b1f6d01c 1192 return pool->funcs->acquire_idle_pipe_for_layer(context, pool, head_pipe->stream);
4562236b
HW
1193}
1194
b86a1aa3 1195#if defined(CONFIG_DRM_AMD_DC_DCN)
0f9a536f
DL
1196static int acquire_first_split_pipe(
1197 struct resource_context *res_ctx,
1198 const struct resource_pool *pool,
0971c40e 1199 struct dc_stream_state *stream)
0f9a536f
DL
1200{
1201 int i;
1202
1203 for (i = 0; i < pool->pipe_count; i++) {
79592db3
DL
1204 struct pipe_ctx *split_pipe = &res_ctx->pipe_ctx[i];
1205
b1f6d01c 1206 if (split_pipe->top_pipe &&
79592db3
DL
1207 split_pipe->top_pipe->plane_state == split_pipe->plane_state) {
1208 split_pipe->top_pipe->bottom_pipe = split_pipe->bottom_pipe;
1209 if (split_pipe->bottom_pipe)
1210 split_pipe->bottom_pipe->top_pipe = split_pipe->top_pipe;
1211
1212 if (split_pipe->top_pipe->plane_state)
1213 resource_build_scaling_params(split_pipe->top_pipe);
1214
1215 memset(split_pipe, 0, sizeof(*split_pipe));
1216 split_pipe->stream_res.tg = pool->timing_generators[i];
1217 split_pipe->plane_res.hubp = pool->hubps[i];
1218 split_pipe->plane_res.ipp = pool->ipps[i];
1219 split_pipe->plane_res.dpp = pool->dpps[i];
1220 split_pipe->stream_res.opp = pool->opps[i];
1221 split_pipe->plane_res.mpcc_inst = pool->dpps[i]->inst;
1222 split_pipe->pipe_idx = i;
1223
1224 split_pipe->stream = stream;
0f9a536f
DL
1225 return i;
1226 }
1227 }
1228 return -1;
1229}
1230#endif
1231
19f89e23
AG
1232bool dc_add_plane_to_context(
1233 const struct dc *dc,
0971c40e 1234 struct dc_stream_state *stream,
19f89e23 1235 struct dc_plane_state *plane_state,
608ac7bb 1236 struct dc_state *context)
4562236b
HW
1237{
1238 int i;
19f89e23
AG
1239 struct resource_pool *pool = dc->res_pool;
1240 struct pipe_ctx *head_pipe, *tail_pipe, *free_pipe;
ab2541b6 1241 struct dc_stream_status *stream_status = NULL;
4562236b 1242
19f89e23
AG
1243 for (i = 0; i < context->stream_count; i++)
1244 if (context->streams[i] == stream) {
1245 stream_status = &context->stream_status[i];
1246 break;
1247 }
1248 if (stream_status == NULL) {
1249 dm_error("Existing stream not found; failed to attach surface!\n");
1250 return false;
1251 }
1252
4562236b 1253
19f89e23
AG
1254 if (stream_status->plane_count == MAX_SURFACE_NUM) {
1255 dm_error("Surface: can not attach plane_state %p! Maximum is: %d\n",
1256 plane_state, MAX_SURFACE_NUM);
4562236b
HW
1257 return false;
1258 }
1259
19f89e23
AG
1260 head_pipe = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
1261
1262 if (!head_pipe) {
1263 dm_error("Head pipe not found for stream_state %p !\n", stream);
1264 return false;
1265 }
1266
b1f6d01c
DL
1267 /* retain new surface, but only once per stream */
1268 dc_plane_state_retain(plane_state);
00737c59 1269
b1f6d01c
DL
1270 while (head_pipe) {
1271 tail_pipe = resource_get_tail_pipe(&context->res_ctx, head_pipe);
1272 ASSERT(tail_pipe);
19f89e23 1273
b1f6d01c 1274 free_pipe = acquire_free_pipe_for_head(context, pool, head_pipe);
19f89e23 1275
b86a1aa3 1276 #if defined(CONFIG_DRM_AMD_DC_DCN)
b1f6d01c
DL
1277 if (!free_pipe) {
1278 int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
1279 if (pipe_idx >= 0)
1280 free_pipe = &context->res_ctx.pipe_ctx[pipe_idx];
1281 }
1282 #endif
1283 if (!free_pipe) {
1284 dc_plane_state_release(plane_state);
1285 return false;
1286 }
19f89e23 1287
b1f6d01c
DL
1288 free_pipe->plane_state = plane_state;
1289
1290 if (head_pipe != free_pipe) {
1291 free_pipe->stream_res.tg = tail_pipe->stream_res.tg;
1292 free_pipe->stream_res.abm = tail_pipe->stream_res.abm;
1293 free_pipe->stream_res.opp = tail_pipe->stream_res.opp;
1294 free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc;
1295 free_pipe->stream_res.audio = tail_pipe->stream_res.audio;
1296 free_pipe->clock_source = tail_pipe->clock_source;
1297 free_pipe->top_pipe = tail_pipe;
1298 tail_pipe->bottom_pipe = free_pipe;
1299 }
1300 head_pipe = head_pipe->next_odm_pipe;
1301 }
19f89e23
AG
1302 /* assign new surfaces*/
1303 stream_status->plane_states[stream_status->plane_count] = plane_state;
1304
1305 stream_status->plane_count++;
1306
1307 return true;
1308}
1309
1310bool dc_remove_plane_from_context(
1311 const struct dc *dc,
1312 struct dc_stream_state *stream,
1313 struct dc_plane_state *plane_state,
608ac7bb 1314 struct dc_state *context)
19f89e23
AG
1315{
1316 int i;
1317 struct dc_stream_status *stream_status = NULL;
1318 struct resource_pool *pool = dc->res_pool;
1319
ab2541b6 1320 for (i = 0; i < context->stream_count; i++)
4fa086b9 1321 if (context->streams[i] == stream) {
ab2541b6 1322 stream_status = &context->stream_status[i];
4562236b
HW
1323 break;
1324 }
19f89e23 1325
ab2541b6 1326 if (stream_status == NULL) {
19f89e23 1327 dm_error("Existing stream not found; failed to remove plane.\n");
4562236b
HW
1328 return false;
1329 }
1330
19f89e23
AG
1331 /* release pipe for plane*/
1332 for (i = pool->pipe_count - 1; i >= 0; i--) {
6ffaa6fc 1333 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
4562236b 1334
6ffaa6fc 1335 if (pipe_ctx->plane_state == plane_state) {
19f89e23
AG
1336 if (pipe_ctx->top_pipe)
1337 pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;
4562236b 1338
19f89e23
AG
1339 /* Second condition is to avoid setting NULL to top pipe
1340 * of tail pipe making it look like head pipe in subsequent
1341 * deletes
1342 */
1343 if (pipe_ctx->bottom_pipe && pipe_ctx->top_pipe)
1344 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;
4562236b 1345
19f89e23
AG
1346 /*
1347 * For head pipe detach surfaces from pipe for tail
1348 * pipe just zero it out
1349 */
b1f6d01c 1350 if (!pipe_ctx->top_pipe)
19f89e23 1351 pipe_ctx->plane_state = NULL;
b1f6d01c 1352 else
19f89e23 1353 memset(pipe_ctx, 0, sizeof(*pipe_ctx));
4562236b 1354 }
19f89e23 1355 }
4562236b 1356
4562236b 1357
19f89e23
AG
1358 for (i = 0; i < stream_status->plane_count; i++) {
1359 if (stream_status->plane_states[i] == plane_state) {
1360
1361 dc_plane_state_release(stream_status->plane_states[i]);
1362 break;
4562236b 1363 }
19f89e23 1364 }
4562236b 1365
19f89e23
AG
1366 if (i == stream_status->plane_count) {
1367 dm_error("Existing plane_state not found; failed to detach it!\n");
1368 return false;
4562236b
HW
1369 }
1370
19f89e23 1371 stream_status->plane_count--;
4562236b 1372
abb4986e
AJ
1373 /* Start at the plane we've just released, and move all the planes one index forward to "trim" the array */
1374 for (; i < stream_status->plane_count; i++)
19f89e23
AG
1375 stream_status->plane_states[i] = stream_status->plane_states[i + 1];
1376
1377 stream_status->plane_states[stream_status->plane_count] = NULL;
1378
1379 return true;
1380}
1381
1382bool dc_rem_all_planes_for_stream(
1383 const struct dc *dc,
1384 struct dc_stream_state *stream,
608ac7bb 1385 struct dc_state *context)
19f89e23
AG
1386{
1387 int i, old_plane_count;
1388 struct dc_stream_status *stream_status = NULL;
1389 struct dc_plane_state *del_planes[MAX_SURFACE_NUM] = { 0 };
1390
1391 for (i = 0; i < context->stream_count; i++)
1392 if (context->streams[i] == stream) {
1393 stream_status = &context->stream_status[i];
1394 break;
1395 }
1396
1397 if (stream_status == NULL) {
1398 dm_error("Existing stream %p not found!\n", stream);
1399 return false;
1400 }
1401
1402 old_plane_count = stream_status->plane_count;
1403
1404 for (i = 0; i < old_plane_count; i++)
1405 del_planes[i] = stream_status->plane_states[i];
1406
1407 for (i = 0; i < old_plane_count; i++)
1408 if (!dc_remove_plane_from_context(dc, stream, del_planes[i], context))
1409 return false;
1410
1411 return true;
1412}
1413
1414static bool add_all_planes_for_stream(
1415 const struct dc *dc,
1416 struct dc_stream_state *stream,
1417 const struct dc_validation_set set[],
1418 int set_count,
608ac7bb 1419 struct dc_state *context)
19f89e23
AG
1420{
1421 int i, j;
1422
1423 for (i = 0; i < set_count; i++)
1424 if (set[i].stream == stream)
1425 break;
1426
1427 if (i == set_count) {
1428 dm_error("Stream %p not found in set!\n", stream);
1429 return false;
1430 }
4562236b 1431
19f89e23
AG
1432 for (j = 0; j < set[i].plane_count; j++)
1433 if (!dc_add_plane_to_context(dc, stream, set[i].plane_states[j], context))
1434 return false;
4562236b
HW
1435
1436 return true;
1437}
1438
19f89e23
AG
1439bool dc_add_all_planes_for_stream(
1440 const struct dc *dc,
1441 struct dc_stream_state *stream,
1442 struct dc_plane_state * const *plane_states,
1443 int plane_count,
608ac7bb 1444 struct dc_state *context)
19f89e23
AG
1445{
1446 struct dc_validation_set set;
1447 int i;
1448
1449 set.stream = stream;
1450 set.plane_count = plane_count;
1451
1452 for (i = 0; i < plane_count; i++)
1453 set.plane_states[i] = plane_states[i];
1454
1455 return add_all_planes_for_stream(dc, stream, &set, 1, context);
1456}
1457
1458
6b622181
JP
1459static bool is_hdr_static_meta_changed(struct dc_stream_state *cur_stream,
1460 struct dc_stream_state *new_stream)
1461{
1462 if (cur_stream == NULL)
1463 return true;
1464
1465 if (memcmp(&cur_stream->hdr_static_metadata,
1466 &new_stream->hdr_static_metadata,
1467 sizeof(struct dc_info_packet)) != 0)
1468 return true;
1469
1470 return false;
1471}
4562236b 1472
1336926f
A
1473static bool is_vsc_info_packet_changed(struct dc_stream_state *cur_stream,
1474 struct dc_stream_state *new_stream)
1475{
1476 if (cur_stream == NULL)
1477 return true;
1478
1479 if (memcmp(&cur_stream->vsc_infopacket,
1480 &new_stream->vsc_infopacket,
1481 sizeof(struct dc_info_packet)) != 0)
1482 return true;
1483
1484 return false;
1485}
1486
0971c40e
HW
1487static bool is_timing_changed(struct dc_stream_state *cur_stream,
1488 struct dc_stream_state *new_stream)
4562236b
HW
1489{
1490 if (cur_stream == NULL)
1491 return true;
1492
1493 /* If sink pointer changed, it means this is a hotplug, we should do
1494 * full hw setting.
1495 */
1496 if (cur_stream->sink != new_stream->sink)
1497 return true;
1498
1499 /* If output color space is changed, need to reprogram info frames */
4fa086b9 1500 if (cur_stream->output_color_space != new_stream->output_color_space)
4562236b
HW
1501 return true;
1502
1503 return memcmp(
4fa086b9
LSL
1504 &cur_stream->timing,
1505 &new_stream->timing,
4562236b
HW
1506 sizeof(struct dc_crtc_timing)) != 0;
1507}
1508
1509static bool are_stream_backends_same(
0971c40e 1510 struct dc_stream_state *stream_a, struct dc_stream_state *stream_b)
4562236b
HW
1511{
1512 if (stream_a == stream_b)
1513 return true;
1514
1515 if (stream_a == NULL || stream_b == NULL)
1516 return false;
1517
1518 if (is_timing_changed(stream_a, stream_b))
1519 return false;
1520
6b622181
JP
1521 if (is_hdr_static_meta_changed(stream_a, stream_b))
1522 return false;
1523
1e7e86c4
ST
1524 if (stream_a->dpms_off != stream_b->dpms_off)
1525 return false;
1526
1336926f
A
1527 if (is_vsc_info_packet_changed(stream_a, stream_b))
1528 return false;
1529
4562236b
HW
1530 return true;
1531}
1532
2119aa17
DF
1533/**
1534 * dc_is_stream_unchanged() - Compare two stream states for equivalence.
1535 *
1536 * Checks if there a difference between the two states
1537 * that would require a mode change.
1538 *
1539 * Does not compare cursor position or attributes.
1540 */
d54d29db 1541bool dc_is_stream_unchanged(
0971c40e 1542 struct dc_stream_state *old_stream, struct dc_stream_state *stream)
4562236b 1543{
4562236b 1544
ab2541b6
AC
1545 if (!are_stream_backends_same(old_stream, stream))
1546 return false;
4562236b 1547
0460f9ab
JL
1548 if (old_stream->ignore_msa_timing_param != stream->ignore_msa_timing_param)
1549 return false;
1550
4562236b
HW
1551 return true;
1552}
1553
2119aa17
DF
1554/**
1555 * dc_is_stream_scaling_unchanged() - Compare scaling rectangles of two streams.
1556 */
9a5d9c48
LSL
1557bool dc_is_stream_scaling_unchanged(
1558 struct dc_stream_state *old_stream, struct dc_stream_state *stream)
1559{
1560 if (old_stream == stream)
1561 return true;
1562
1563 if (old_stream == NULL || stream == NULL)
1564 return false;
1565
1566 if (memcmp(&old_stream->src,
1567 &stream->src,
1568 sizeof(struct rect)) != 0)
1569 return false;
1570
1571 if (memcmp(&old_stream->dst,
1572 &stream->dst,
1573 sizeof(struct rect)) != 0)
1574 return false;
1575
1576 return true;
1577}
1578
1dc90497 1579static void update_stream_engine_usage(
4562236b 1580 struct resource_context *res_ctx,
a2b8659d 1581 const struct resource_pool *pool,
1dc90497
AG
1582 struct stream_encoder *stream_enc,
1583 bool acquired)
4562236b
HW
1584{
1585 int i;
1586
a2b8659d
TC
1587 for (i = 0; i < pool->stream_enc_count; i++) {
1588 if (pool->stream_enc[i] == stream_enc)
1dc90497 1589 res_ctx->is_stream_enc_acquired[i] = acquired;
4562236b
HW
1590 }
1591}
1592
1593/* TODO: release audio object */
4176664b 1594void update_audio_usage(
4562236b 1595 struct resource_context *res_ctx,
a2b8659d 1596 const struct resource_pool *pool,
1dc90497
AG
1597 struct audio *audio,
1598 bool acquired)
4562236b
HW
1599{
1600 int i;
a2b8659d
TC
1601 for (i = 0; i < pool->audio_count; i++) {
1602 if (pool->audios[i] == audio)
1dc90497 1603 res_ctx->is_audio_acquired[i] = acquired;
4562236b
HW
1604 }
1605}
1606
1607static int acquire_first_free_pipe(
1608 struct resource_context *res_ctx,
a2b8659d 1609 const struct resource_pool *pool,
0971c40e 1610 struct dc_stream_state *stream)
4562236b
HW
1611{
1612 int i;
1613
a2b8659d 1614 for (i = 0; i < pool->pipe_count; i++) {
4562236b
HW
1615 if (!res_ctx->pipe_ctx[i].stream) {
1616 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
1617
6b670fa9 1618 pipe_ctx->stream_res.tg = pool->timing_generators[i];
86a66c4e 1619 pipe_ctx->plane_res.mi = pool->mis[i];
8feabd03 1620 pipe_ctx->plane_res.hubp = pool->hubps[i];
86a66c4e
HW
1621 pipe_ctx->plane_res.ipp = pool->ipps[i];
1622 pipe_ctx->plane_res.xfm = pool->transforms[i];
d94585a0 1623 pipe_ctx->plane_res.dpp = pool->dpps[i];
a6a6cb34 1624 pipe_ctx->stream_res.opp = pool->opps[i];
bc373a89
RL
1625 if (pool->dpps[i])
1626 pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst;
4562236b
HW
1627 pipe_ctx->pipe_idx = i;
1628
ff5ef992 1629
4562236b
HW
1630 pipe_ctx->stream = stream;
1631 return i;
1632 }
1633 }
1634 return -1;
1635}
1636
a2b8659d
TC
1637static struct audio *find_first_free_audio(
1638 struct resource_context *res_ctx,
cfb071f7 1639 const struct resource_pool *pool,
f24b0522
PH
1640 enum engine_id id,
1641 enum dce_version dc_version)
4562236b 1642{
b5a41620
CL
1643 int i, available_audio_count;
1644
1645 available_audio_count = pool->audio_count;
1646
1647 for (i = 0; i < available_audio_count; i++) {
66bfd4fd 1648 if ((res_ctx->is_audio_acquired[i] == false) && (res_ctx->is_stream_enc_acquired[i] == true)) {
cfb071f7
CL
1649 /*we have enough audio endpoint, find the matching inst*/
1650 if (id != i)
1651 continue;
66bfd4fd 1652 return pool->audios[i];
4562236b 1653 }
66bfd4fd 1654 }
5feb9f07 1655
b5a41620
CL
1656 /* use engine id to find free audio */
1657 if ((id < available_audio_count) && (res_ctx->is_audio_acquired[id] == false)) {
5feb9f07
TM
1658 return pool->audios[id];
1659 }
66bfd4fd 1660 /*not found the matching one, first come first serve*/
b5a41620 1661 for (i = 0; i < available_audio_count; i++) {
66bfd4fd
CL
1662 if (res_ctx->is_audio_acquired[i] == false) {
1663 return pool->audios[i];
4176664b
CL
1664 }
1665 }
4562236b
HW
1666 return 0;
1667}
1668
4562236b 1669bool resource_is_stream_unchanged(
608ac7bb 1670 struct dc_state *old_context, struct dc_stream_state *stream)
4562236b 1671{
ab2541b6 1672 int i;
4562236b 1673
ab2541b6 1674 for (i = 0; i < old_context->stream_count; i++) {
0971c40e 1675 struct dc_stream_state *old_stream = old_context->streams[i];
4562236b 1676
ab2541b6 1677 if (are_stream_backends_same(old_stream, stream))
4562236b 1678 return true;
4562236b
HW
1679 }
1680
1681 return false;
1682}
1683
2119aa17
DF
1684/**
1685 * dc_add_stream_to_ctx() - Add a new dc_stream_state to a dc_state.
1686 */
13ab1b44 1687enum dc_status dc_add_stream_to_ctx(
1dc90497 1688 struct dc *dc,
608ac7bb 1689 struct dc_state *new_ctx,
1dc90497
AG
1690 struct dc_stream_state *stream)
1691{
1dc90497 1692 enum dc_status res;
eb9714a2 1693 DC_LOGGER_INIT(dc->ctx->logger);
1dc90497 1694
ece4147f 1695 if (new_ctx->stream_count >= dc->res_pool->timing_generator_count) {
eb9714a2 1696 DC_LOG_WARNING("Max streams reached, can't add stream %p !\n", stream);
1dc90497
AG
1697 return DC_ERROR_UNEXPECTED;
1698 }
1699
1700 new_ctx->streams[new_ctx->stream_count] = stream;
1701 dc_stream_retain(stream);
1702 new_ctx->stream_count++;
1703
1704 res = dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream);
1705 if (res != DC_OK)
eb9714a2 1706 DC_LOG_WARNING("Adding stream %p to context failed with err %d!\n", stream, res);
1dc90497 1707
13ab1b44 1708 return res;
1dc90497
AG
1709}
1710
2119aa17
DF
1711/**
1712 * dc_remove_stream_from_ctx() - Remove a stream from a dc_state.
1713 */
62c933f9 1714enum dc_status dc_remove_stream_from_ctx(
1dc90497 1715 struct dc *dc,
608ac7bb 1716 struct dc_state *new_ctx,
1dc90497
AG
1717 struct dc_stream_state *stream)
1718{
19f89e23 1719 int i;
1dc90497 1720 struct dc_context *dc_ctx = dc->ctx;
22498036
DL
1721 struct pipe_ctx *del_pipe = resource_get_head_pipe_for_stream(&new_ctx->res_ctx, stream);
1722 struct pipe_ctx *odm_pipe;
1dc90497
AG
1723
1724 if (!del_pipe) {
1725 DC_ERROR("Pipe not found for stream %p !\n", stream);
1726 return DC_ERROR_UNEXPECTED;
1727 }
1728
22498036
DL
1729 odm_pipe = del_pipe->next_odm_pipe;
1730
1731 /* Release primary pipe */
1732 ASSERT(del_pipe->stream_res.stream_enc);
1733 update_stream_engine_usage(
1734 &new_ctx->res_ctx,
1735 dc->res_pool,
1736 del_pipe->stream_res.stream_enc,
1737 false);
1738
1739 if (del_pipe->stream_res.audio)
1740 update_audio_usage(
1741 &new_ctx->res_ctx,
1742 dc->res_pool,
1743 del_pipe->stream_res.audio,
1744 false);
1745
1746 resource_unreference_clock_source(&new_ctx->res_ctx,
1747 dc->res_pool,
1748 del_pipe->clock_source);
1749
1750 if (dc->res_pool->funcs->remove_stream_from_ctx)
1751 dc->res_pool->funcs->remove_stream_from_ctx(dc, new_ctx, stream);
1752
1753 while (odm_pipe) {
1754 struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe;
1755
1756 memset(odm_pipe, 0, sizeof(*odm_pipe));
1757 odm_pipe = next_odm_pipe;
1758 }
1759 memset(del_pipe, 0, sizeof(*del_pipe));
1760
1dc90497
AG
1761 for (i = 0; i < new_ctx->stream_count; i++)
1762 if (new_ctx->streams[i] == stream)
1763 break;
1764
1765 if (new_ctx->streams[i] != stream) {
1766 DC_ERROR("Context doesn't have stream %p !\n", stream);
1767 return DC_ERROR_UNEXPECTED;
1768 }
1769
1770 dc_stream_release(new_ctx->streams[i]);
1771 new_ctx->stream_count--;
1772
1dc90497
AG
1773 /* Trim back arrays */
1774 for (; i < new_ctx->stream_count; i++) {
1775 new_ctx->streams[i] = new_ctx->streams[i + 1];
1776 new_ctx->stream_status[i] = new_ctx->stream_status[i + 1];
1777 }
1778
1779 new_ctx->streams[new_ctx->stream_count] = NULL;
1780 memset(
1781 &new_ctx->stream_status[new_ctx->stream_count],
1782 0,
1783 sizeof(new_ctx->stream_status[0]));
1784
1785 return DC_OK;
1786}
1787
0971c40e
HW
1788static struct dc_stream_state *find_pll_sharable_stream(
1789 struct dc_stream_state *stream_needs_pll,
608ac7bb 1790 struct dc_state *context)
4562236b 1791{
ab2541b6 1792 int i;
4562236b 1793
ab2541b6 1794 for (i = 0; i < context->stream_count; i++) {
0971c40e 1795 struct dc_stream_state *stream_has_pll = context->streams[i];
4562236b 1796
ab2541b6
AC
1797 /* We are looking for non dp, non virtual stream */
1798 if (resource_are_streams_timing_synchronizable(
1799 stream_needs_pll, stream_has_pll)
1800 && !dc_is_dp_signal(stream_has_pll->signal)
ceb3dbb4 1801 && stream_has_pll->link->connector_signal
ab2541b6
AC
1802 != SIGNAL_TYPE_VIRTUAL)
1803 return stream_has_pll;
4562236b 1804
4562236b
HW
1805 }
1806
1807 return NULL;
1808}
1809
1810static int get_norm_pix_clk(const struct dc_crtc_timing *timing)
1811{
380604e2 1812 uint32_t pix_clk = timing->pix_clk_100hz;
4562236b
HW
1813 uint32_t normalized_pix_clk = pix_clk;
1814
1815 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
1816 pix_clk /= 2;
cc4d99b8
CL
1817 if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) {
1818 switch (timing->display_color_depth) {
8897810a 1819 case COLOR_DEPTH_666:
cc4d99b8
CL
1820 case COLOR_DEPTH_888:
1821 normalized_pix_clk = pix_clk;
1822 break;
1823 case COLOR_DEPTH_101010:
1824 normalized_pix_clk = (pix_clk * 30) / 24;
1825 break;
1826 case COLOR_DEPTH_121212:
1827 normalized_pix_clk = (pix_clk * 36) / 24;
4562236b 1828 break;
cc4d99b8
CL
1829 case COLOR_DEPTH_161616:
1830 normalized_pix_clk = (pix_clk * 48) / 24;
4562236b 1831 break;
cc4d99b8
CL
1832 default:
1833 ASSERT(0);
4562236b 1834 break;
cc4d99b8 1835 }
4562236b 1836 }
4562236b
HW
1837 return normalized_pix_clk;
1838}
1839
0971c40e 1840static void calculate_phy_pix_clks(struct dc_stream_state *stream)
4562236b 1841{
9345d987
AG
1842 /* update actual pixel clock on all streams */
1843 if (dc_is_hdmi_signal(stream->signal))
1844 stream->phy_pix_clk = get_norm_pix_clk(
380604e2 1845 &stream->timing) / 10;
9345d987
AG
1846 else
1847 stream->phy_pix_clk =
380604e2 1848 stream->timing.pix_clk_100hz / 10;
39c03e00
CL
1849
1850 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1851 stream->phy_pix_clk *= 2;
4562236b
HW
1852}
1853
d2d7885f
AK
1854static int acquire_resource_from_hw_enabled_state(
1855 struct resource_context *res_ctx,
1856 const struct resource_pool *pool,
1857 struct dc_stream_state *stream)
1858{
1859 struct dc_link *link = stream->link;
08b66279 1860 unsigned int i, inst, tg_inst = 0;
d2d7885f
AK
1861
1862 /* Check for enabled DIG to identify enabled display */
1863 if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
1864 return -1;
1865
5ec43eda 1866 inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
d2d7885f 1867
7f7652ee 1868 if (inst == ENGINE_ID_UNKNOWN)
75441d9d 1869 return -1;
d2d7885f 1870
7f7652ee
ML
1871 for (i = 0; i < pool->stream_enc_count; i++) {
1872 if (pool->stream_enc[i]->id == inst) {
1873 tg_inst = pool->stream_enc[i]->funcs->dig_source_otg(
1874 pool->stream_enc[i]);
1875 break;
1876 }
1877 }
5ec43eda 1878
7f7652ee
ML
1879 // tg_inst not found
1880 if (i == pool->stream_enc_count)
75441d9d 1881 return -1;
5ec43eda
ML
1882
1883 if (tg_inst >= pool->timing_generator_count)
75441d9d 1884 return -1;
5ec43eda
ML
1885
1886 if (!res_ctx->pipe_ctx[tg_inst].stream) {
1887 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[tg_inst];
1888
1889 pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];
1890 pipe_ctx->plane_res.mi = pool->mis[tg_inst];
1891 pipe_ctx->plane_res.hubp = pool->hubps[tg_inst];
1892 pipe_ctx->plane_res.ipp = pool->ipps[tg_inst];
1893 pipe_ctx->plane_res.xfm = pool->transforms[tg_inst];
1894 pipe_ctx->plane_res.dpp = pool->dpps[tg_inst];
1895 pipe_ctx->stream_res.opp = pool->opps[tg_inst];
d2d7885f 1896
5ec43eda
ML
1897 if (pool->dpps[tg_inst])
1898 pipe_ctx->plane_res.mpcc_inst = pool->dpps[tg_inst]->inst;
1899 pipe_ctx->pipe_idx = tg_inst;
d2d7885f
AK
1900
1901 pipe_ctx->stream = stream;
5ec43eda 1902 return tg_inst;
d2d7885f
AK
1903 }
1904
1905 return -1;
1906}
1907
4562236b 1908enum dc_status resource_map_pool_resources(
fb3466a4 1909 const struct dc *dc,
608ac7bb 1910 struct dc_state *context,
1dc90497 1911 struct dc_stream_state *stream)
4562236b 1912{
a2b8659d 1913 const struct resource_pool *pool = dc->res_pool;
1dc90497
AG
1914 int i;
1915 struct dc_context *dc_ctx = dc->ctx;
1916 struct pipe_ctx *pipe_ctx = NULL;
1917 int pipe_idx = -1;
46570f09 1918 struct dc_bios *dcb = dc->ctx->dc_bios;
4562236b 1919
1dc90497
AG
1920 /* TODO Check if this is needed */
1921 /*if (!resource_is_stream_unchanged(old_context, stream)) {
430ef426 1922 if (stream != NULL && old_context->streams[i] != NULL) {
4b679bc3 1923 stream->bit_depth_params =
430ef426
DL
1924 old_context->streams[i]->bit_depth_params;
1925 stream->clamping = old_context->streams[i]->clamping;
a2b8659d
TC
1926 continue;
1927 }
4b679bc3 1928 }
1dc90497 1929 */
7e2fe319 1930
08e1c28d
YMM
1931 calculate_phy_pix_clks(stream);
1932
46570f09
AK
1933 /* TODO: Check Linux */
1934 if (dc->config.allow_seamless_boot_optimization &&
1935 !dcb->funcs->is_accelerated_mode(dcb)) {
1936 if (dc_validate_seamless_boot_timing(dc, stream->sink, &stream->timing))
1937 stream->apply_seamless_boot_optimization = true;
1938 }
1939
d2d7885f
AK
1940 if (stream->apply_seamless_boot_optimization)
1941 pipe_idx = acquire_resource_from_hw_enabled_state(
1942 &context->res_ctx,
1943 pool,
1944 stream);
1945
1946 if (pipe_idx < 0)
1947 /* acquire new resources */
1948 pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream);
8c737fcc 1949
b86a1aa3 1950#ifdef CONFIG_DRM_AMD_DC_DCN
1dc90497 1951 if (pipe_idx < 0)
13ab1b44 1952 pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
94c6d735 1953#endif
13ab1b44 1954
c5b38aec 1955 if (pipe_idx < 0 || context->res_ctx.pipe_ctx[pipe_idx].stream_res.tg == NULL)
1dc90497
AG
1956 return DC_NO_CONTROLLER_RESOURCE;
1957
1958 pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
1959
1960 pipe_ctx->stream_res.stream_enc =
78cc70b1 1961 dc->res_pool->funcs->find_first_free_match_stream_enc_for_link(
1dc90497
AG
1962 &context->res_ctx, pool, stream);
1963
1964 if (!pipe_ctx->stream_res.stream_enc)
38684e46 1965 return DC_NO_STREAM_ENC_RESOURCE;
1dc90497
AG
1966
1967 update_stream_engine_usage(
1968 &context->res_ctx, pool,
1969 pipe_ctx->stream_res.stream_enc,
1970 true);
1971
1972 /* TODO: Add check if ASIC support and EDID audio */
ceb3dbb4 1973 if (!stream->converter_disable_audio &&
1dc90497 1974 dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&
ce08aad3 1975 stream->audio_info.mode_count && stream->audio_info.flags.all) {
1dc90497 1976 pipe_ctx->stream_res.audio = find_first_free_audio(
f24b0522 1977 &context->res_ctx, pool, pipe_ctx->stream_res.stream_enc->id, dc_ctx->dce_version);
1dc90497
AG
1978
1979 /*
1980 * Audio assigned in order first come first get.
1981 * There are asics which has number of audio
1982 * resources less then number of pipes
1983 */
1984 if (pipe_ctx->stream_res.audio)
1985 update_audio_usage(&context->res_ctx, pool,
1986 pipe_ctx->stream_res.audio, true);
1987 }
268cadbd 1988
9aef1a31
S
1989 /* Add ABM to the resource if on EDP */
1990 if (pipe_ctx->stream && dc_is_embedded_signal(pipe_ctx->stream->signal))
1991 pipe_ctx->stream_res.abm = pool->abm;
1992
1dc90497
AG
1993 for (i = 0; i < context->stream_count; i++)
1994 if (context->streams[i] == stream) {
1995 context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst;
0f0bdca5 1996 context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.stream_enc->id;
5fdb7c4c
NK
1997 context->stream_status[i].audio_inst =
1998 pipe_ctx->stream_res.audio ? pipe_ctx->stream_res.audio->inst : -1;
1999
1dc90497
AG
2000 return DC_OK;
2001 }
4562236b 2002
1dc90497
AG
2003 DC_ERROR("Stream %p not found in new ctx!\n", stream);
2004 return DC_ERROR_UNEXPECTED;
2005}
4562236b 2006
2119aa17
DF
2007/**
2008 * dc_resource_state_copy_construct_current() - Creates a new dc_state from existing state
2009 * Is a shallow copy. Increments refcounts on existing streams and planes.
2010 * @dc: copy out of dc->current_state
2011 * @dst_ctx: copy into this
2012 */
f36cc577 2013void dc_resource_state_copy_construct_current(
1dc90497 2014 const struct dc *dc,
608ac7bb 2015 struct dc_state *dst_ctx)
1dc90497 2016{
f36cc577 2017 dc_resource_state_copy_construct(dc->current_state, dst_ctx);
1dc90497
AG
2018}
2019
ab8db3e1
AG
2020
2021void dc_resource_state_construct(
2022 const struct dc *dc,
2023 struct dc_state *dst_ctx)
2024{
dc88b4a6 2025 dst_ctx->clk_mgr = dc->clk_mgr;
ab8db3e1
AG
2026}
2027
2119aa17
DF
2028/**
2029 * dc_validate_global_state() - Determine if HW can support a given state
2030 * Checks HW resource availability and bandwidth requirement.
2031 * @dc: dc struct for this driver
2032 * @new_ctx: state to be validated
afcd526b 2033 * @fast_validate: set to true if only yes/no to support matters
2119aa17
DF
2034 *
2035 * Return: DC_OK if the result can be programmed. Otherwise, an error code.
2036 */
e750d56d 2037enum dc_status dc_validate_global_state(
1dc90497 2038 struct dc *dc,
afcd526b
JA
2039 struct dc_state *new_ctx,
2040 bool fast_validate)
4562236b 2041{
1dc90497 2042 enum dc_status result = DC_ERROR_UNEXPECTED;
1dc90497 2043 int i, j;
4562236b 2044
e41ab030
HW
2045 if (!new_ctx)
2046 return DC_ERROR_UNEXPECTED;
2047
d596e5d0 2048 if (dc->res_pool->funcs->validate_global) {
ada8ce15
HW
2049 result = dc->res_pool->funcs->validate_global(dc, new_ctx);
2050 if (result != DC_OK)
2051 return result;
d596e5d0 2052 }
4562236b 2053
e41ab030 2054 for (i = 0; i < new_ctx->stream_count; i++) {
1dc90497
AG
2055 struct dc_stream_state *stream = new_ctx->streams[i];
2056
2057 for (j = 0; j < dc->res_pool->pipe_count; j++) {
2058 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[j];
2059
2060 if (pipe_ctx->stream != stream)
2061 continue;
2062
74eac5f3
SSC
2063 if (dc->res_pool->funcs->get_default_swizzle_mode &&
2064 pipe_ctx->plane_state &&
2065 pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) {
2066 result = dc->res_pool->funcs->get_default_swizzle_mode(pipe_ctx->plane_state);
2067 if (result != DC_OK)
2068 return result;
2069 }
2070
1dc90497
AG
2071 /* Switch to dp clock source only if there is
2072 * no non dp stream that shares the same timing
2073 * with the dp stream.
2074 */
2075 if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
2076 !find_pll_sharable_stream(stream, new_ctx)) {
2077
9d0dcecd 2078 resource_unreference_clock_source(
1dc90497
AG
2079 &new_ctx->res_ctx,
2080 dc->res_pool,
9d0dcecd 2081 pipe_ctx->clock_source);
4a629536 2082
1dc90497
AG
2083 pipe_ctx->clock_source = dc->res_pool->dp_clock_source;
2084 resource_reference_clock_source(
2085 &new_ctx->res_ctx,
2086 dc->res_pool,
2087 pipe_ctx->clock_source);
2088 }
2089 }
2090 }
2091
1dc90497
AG
2092 result = resource_build_scaling_params_for_context(dc, new_ctx);
2093
2094 if (result == DC_OK)
afcd526b 2095 if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx, fast_validate))
1dc90497
AG
2096 result = DC_FAIL_BANDWIDTH_VALIDATE;
2097
2098 return result;
4562236b
HW
2099}
2100
6e4d6bee 2101static void patch_gamut_packet_checksum(
e09b6473 2102 struct dc_info_packet *gamut_packet)
4562236b 2103{
4562236b 2104 /* For gamut we recalc checksum */
6e4d6bee 2105 if (gamut_packet->valid) {
4562236b
HW
2106 uint8_t chk_sum = 0;
2107 uint8_t *ptr;
2108 uint8_t i;
2109
4562236b 2110 /*start of the Gamut data. */
6e4d6bee 2111 ptr = &gamut_packet->sb[3];
4562236b 2112
6e4d6bee 2113 for (i = 0; i <= gamut_packet->sb[1]; i++)
4562236b
HW
2114 chk_sum += ptr[i];
2115
6e4d6bee 2116 gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum);
1646a6fe 2117 }
4562236b
HW
2118}
2119
2120static void set_avi_info_frame(
e09b6473 2121 struct dc_info_packet *info_packet,
4562236b
HW
2122 struct pipe_ctx *pipe_ctx)
2123{
0971c40e 2124 struct dc_stream_state *stream = pipe_ctx->stream;
4562236b 2125 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
4562236b
HW
2126 uint32_t pixel_encoding = 0;
2127 enum scanning_type scan_type = SCANNING_TYPE_NODATA;
2128 enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA;
2129 bool itc = false;
50e27654 2130 uint8_t itc_value = 0;
4562236b 2131 uint8_t cn0_cn1 = 0;
50e27654 2132 unsigned int cn0_cn1_value = 0;
4562236b
HW
2133 uint8_t *check_sum = NULL;
2134 uint8_t byte_index = 0;
754e3673 2135 union hdmi_info_packet hdmi_info;
50e27654 2136 union display_content_support support = {0};
4fa086b9 2137 unsigned int vic = pipe_ctx->stream->timing.vic;
15e17335 2138 enum dc_timing_3d_format format;
4562236b 2139
754e3673
AK
2140 memset(&hdmi_info, 0, sizeof(union hdmi_info_packet));
2141
4fa086b9 2142 color_space = pipe_ctx->stream->output_color_space;
e5f2038e 2143 if (color_space == COLOR_SPACE_UNKNOWN)
4fa086b9 2144 color_space = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ?
e5f2038e 2145 COLOR_SPACE_SRGB:COLOR_SPACE_YCBCR709;
4562236b
HW
2146
2147 /* Initialize header */
e09b6473 2148 hdmi_info.bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI;
4562236b
HW
2149 /* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall
2150 * not be used in HDMI 2.0 (Section 10.1) */
e09b6473
AK
2151 hdmi_info.bits.header.version = 2;
2152 hdmi_info.bits.header.length = HDMI_AVI_INFOFRAME_SIZE;
4562236b
HW
2153
2154 /*
2155 * IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built
2156 * according to HDMI 2.0 spec (Section 10.1)
2157 */
2158
4fa086b9 2159 switch (stream->timing.pixel_encoding) {
4562236b
HW
2160 case PIXEL_ENCODING_YCBCR422:
2161 pixel_encoding = 1;
2162 break;
2163
2164 case PIXEL_ENCODING_YCBCR444:
2165 pixel_encoding = 2;
2166 break;
2167 case PIXEL_ENCODING_YCBCR420:
2168 pixel_encoding = 3;
2169 break;
2170
2171 case PIXEL_ENCODING_RGB:
2172 default:
2173 pixel_encoding = 0;
2174 }
2175
2176 /* Y0_Y1_Y2 : The pixel encoding */
2177 /* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */
e09b6473 2178 hdmi_info.bits.Y0_Y1_Y2 = pixel_encoding;
4562236b
HW
2179
2180 /* A0 = 1 Active Format Information valid */
e09b6473 2181 hdmi_info.bits.A0 = ACTIVE_FORMAT_VALID;
4562236b
HW
2182
2183 /* B0, B1 = 3; Bar info data is valid */
e09b6473 2184 hdmi_info.bits.B0_B1 = BAR_INFO_BOTH_VALID;
4562236b 2185
e09b6473 2186 hdmi_info.bits.SC0_SC1 = PICTURE_SCALING_UNIFORM;
4562236b
HW
2187
2188 /* S0, S1 : Underscan / Overscan */
2189 /* TODO: un-hardcode scan type */
2190 scan_type = SCANNING_TYPE_UNDERSCAN;
e09b6473 2191 hdmi_info.bits.S0_S1 = scan_type;
4562236b
HW
2192
2193 /* C0, C1 : Colorimetry */
8fde5884 2194 if (color_space == COLOR_SPACE_YCBCR709 ||
15e17335 2195 color_space == COLOR_SPACE_YCBCR709_LIMITED)
e09b6473 2196 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU709;
8fde5884
CL
2197 else if (color_space == COLOR_SPACE_YCBCR601 ||
2198 color_space == COLOR_SPACE_YCBCR601_LIMITED)
e09b6473 2199 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU601;
8fde5884 2200 else {
e09b6473 2201 hdmi_info.bits.C0_C1 = COLORIMETRY_NO_DATA;
8fde5884 2202 }
534db198 2203 if (color_space == COLOR_SPACE_2020_RGB_FULLRANGE ||
8fde5884
CL
2204 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE ||
2205 color_space == COLOR_SPACE_2020_YCBCR) {
e09b6473
AK
2206 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR;
2207 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
534db198 2208 } else if (color_space == COLOR_SPACE_ADOBERGB) {
e09b6473
AK
2209 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB;
2210 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
534db198
AZ
2211 }
2212
4562236b 2213 /* TODO: un-hardcode aspect ratio */
4fa086b9 2214 aspect = stream->timing.aspect_ratio;
4562236b
HW
2215
2216 switch (aspect) {
2217 case ASPECT_RATIO_4_3:
2218 case ASPECT_RATIO_16_9:
e09b6473 2219 hdmi_info.bits.M0_M1 = aspect;
4562236b
HW
2220 break;
2221
2222 case ASPECT_RATIO_NO_DATA:
2223 case ASPECT_RATIO_64_27:
2224 case ASPECT_RATIO_256_135:
2225 default:
e09b6473 2226 hdmi_info.bits.M0_M1 = 0;
4562236b
HW
2227 }
2228
2229 /* Active Format Aspect ratio - same as Picture Aspect Ratio. */
e09b6473 2230 hdmi_info.bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE;
4562236b
HW
2231
2232 /* TODO: un-hardcode cn0_cn1 and itc */
50e27654 2233
4562236b 2234 cn0_cn1 = 0;
50e27654
ZF
2235 cn0_cn1_value = 0;
2236
2237 itc = true;
2238 itc_value = 1;
2239
ceb3dbb4 2240 support = stream->content_support;
4562236b
HW
2241
2242 if (itc) {
50e27654
ZF
2243 if (!support.bits.valid_content_type) {
2244 cn0_cn1_value = 0;
2245 } else {
2246 if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GRAPHICS) {
2247 if (support.bits.graphics_content == 1) {
2248 cn0_cn1_value = 0;
2249 }
2250 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_PHOTO) {
2251 if (support.bits.photo_content == 1) {
2252 cn0_cn1_value = 1;
2253 } else {
2254 cn0_cn1_value = 0;
2255 itc_value = 0;
2256 }
2257 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_CINEMA) {
2258 if (support.bits.cinema_content == 1) {
2259 cn0_cn1_value = 2;
2260 } else {
2261 cn0_cn1_value = 0;
2262 itc_value = 0;
2263 }
2264 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GAME) {
2265 if (support.bits.game_content == 1) {
2266 cn0_cn1_value = 3;
2267 } else {
2268 cn0_cn1_value = 0;
2269 itc_value = 0;
2270 }
2271 }
2272 }
e09b6473
AK
2273 hdmi_info.bits.CN0_CN1 = cn0_cn1_value;
2274 hdmi_info.bits.ITC = itc_value;
4562236b
HW
2275 }
2276
2277 /* TODO : We should handle YCC quantization */
2278 /* but we do not have matrix calculation */
ceb3dbb4
JL
2279 if (stream->qs_bit == 1 &&
2280 stream->qy_bit == 1) {
50e27654
ZF
2281 if (color_space == COLOR_SPACE_SRGB ||
2282 color_space == COLOR_SPACE_2020_RGB_FULLRANGE) {
e09b6473
AK
2283 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_FULL_RANGE;
2284 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_FULL_RANGE;
50e27654
ZF
2285 } else if (color_space == COLOR_SPACE_SRGB_LIMITED ||
2286 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE) {
e09b6473
AK
2287 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_LIMITED_RANGE;
2288 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
50e27654 2289 } else {
e09b6473
AK
2290 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
2291 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
50e27654 2292 }
4562236b 2293 } else {
e09b6473
AK
2294 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
2295 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
4562236b 2296 }
50e27654 2297
15e17335 2298 ///VIC
4fa086b9 2299 format = stream->timing.timing_3d_format;
15e17335
CL
2300 /*todo, add 3DStereo support*/
2301 if (format != TIMING_3D_FORMAT_NONE) {
2302 // Based on HDMI specs hdmi vic needs to be converted to cea vic when 3D is enabled
4fa086b9 2303 switch (pipe_ctx->stream->timing.hdmi_vic) {
15e17335
CL
2304 case 1:
2305 vic = 95;
2306 break;
2307 case 2:
2308 vic = 94;
2309 break;
2310 case 3:
2311 vic = 93;
2312 break;
2313 case 4:
2314 vic = 98;
2315 break;
2316 default:
2317 break;
2318 }
2319 }
efa02336 2320 /* If VIC >= 128, the Source shall use AVI InfoFrame Version 3*/
e09b6473 2321 hdmi_info.bits.VIC0_VIC7 = vic;
efa02336
CP
2322 if (vic >= 128)
2323 hdmi_info.bits.header.version = 3;
2324 /* If (C1, C0)=(1, 1) and (EC2, EC1, EC0)=(1, 1, 1),
2325 * the Source shall use 20 AVI InfoFrame Version 4
2326 */
2327 if (hdmi_info.bits.C0_C1 == COLORIMETRY_EXTENDED &&
2328 hdmi_info.bits.EC0_EC2 == COLORIMETRYEX_RESERVED) {
2329 hdmi_info.bits.header.version = 4;
2330 hdmi_info.bits.header.length = 14;
2331 }
4562236b
HW
2332
2333 /* pixel repetition
2334 * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel
2335 * repetition start from 1 */
e09b6473 2336 hdmi_info.bits.PR0_PR3 = 0;
4562236b
HW
2337
2338 /* Bar Info
2339 * barTop: Line Number of End of Top Bar.
2340 * barBottom: Line Number of Start of Bottom Bar.
2341 * barLeft: Pixel Number of End of Left Bar.
2342 * barRight: Pixel Number of Start of Right Bar. */
e09b6473
AK
2343 hdmi_info.bits.bar_top = stream->timing.v_border_top;
2344 hdmi_info.bits.bar_bottom = (stream->timing.v_total
4fa086b9 2345 - stream->timing.v_border_bottom + 1);
e09b6473
AK
2346 hdmi_info.bits.bar_left = stream->timing.h_border_left;
2347 hdmi_info.bits.bar_right = (stream->timing.h_total
4fa086b9 2348 - stream->timing.h_border_right + 1);
4562236b 2349
2f482c4f
CP
2350 /* Additional Colorimetry Extension
2351 * Used in conduction with C0-C1 and EC0-EC2
2352 * 0 = DCI-P3 RGB (D65)
2353 * 1 = DCI-P3 RGB (theater)
2354 */
2355 hdmi_info.bits.ACE0_ACE3 = 0;
2356
4562236b 2357 /* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */
e09b6473 2358 check_sum = &hdmi_info.packet_raw_data.sb[0];
e8d726b7 2359
efa02336 2360 *check_sum = HDMI_INFOFRAME_TYPE_AVI + hdmi_info.bits.header.length + hdmi_info.bits.header.version;
4562236b 2361
efa02336 2362 for (byte_index = 1; byte_index <= hdmi_info.bits.header.length; byte_index++)
e09b6473 2363 *check_sum += hdmi_info.packet_raw_data.sb[byte_index];
4562236b
HW
2364
2365 /* one byte complement */
2366 *check_sum = (uint8_t) (0x100 - *check_sum);
2367
2368 /* Store in hw_path_mode */
e09b6473
AK
2369 info_packet->hb0 = hdmi_info.packet_raw_data.hb0;
2370 info_packet->hb1 = hdmi_info.packet_raw_data.hb1;
2371 info_packet->hb2 = hdmi_info.packet_raw_data.hb2;
4562236b 2372
e09b6473
AK
2373 for (byte_index = 0; byte_index < sizeof(hdmi_info.packet_raw_data.sb); byte_index++)
2374 info_packet->sb[byte_index] = hdmi_info.packet_raw_data.sb[byte_index];
4562236b
HW
2375
2376 info_packet->valid = true;
2377}
2378
6e4d6bee 2379static void set_vendor_info_packet(
e09b6473 2380 struct dc_info_packet *info_packet,
0971c40e 2381 struct dc_stream_state *stream)
4562236b 2382{
ecd0136b 2383 /* SPD info packet for FreeSync */
4562236b 2384
ecd0136b
HT
2385 /* Check if Freesync is supported. Return if false. If true,
2386 * set the corresponding bit in the info packet
2387 */
2388 if (!stream->vsp_infopacket.valid)
4562236b
HW
2389 return;
2390
ecd0136b 2391 *info_packet = stream->vsp_infopacket;
4562236b
HW
2392}
2393
6e4d6bee 2394static void set_spd_info_packet(
e09b6473 2395 struct dc_info_packet *info_packet,
0971c40e 2396 struct dc_stream_state *stream)
4562236b
HW
2397{
2398 /* SPD info packet for FreeSync */
2399
4562236b
HW
2400 /* Check if Freesync is supported. Return if false. If true,
2401 * set the corresponding bit in the info packet
2402 */
98e6436d 2403 if (!stream->vrr_infopacket.valid)
4562236b
HW
2404 return;
2405
98e6436d 2406 *info_packet = stream->vrr_infopacket;
4562236b
HW
2407}
2408
1646a6fe 2409static void set_hdr_static_info_packet(
e09b6473 2410 struct dc_info_packet *info_packet,
0971c40e 2411 struct dc_stream_state *stream)
1646a6fe 2412{
0eeef690 2413 /* HDR Static Metadata info packet for HDR10 */
1646a6fe 2414
a10dc97a
KK
2415 if (!stream->hdr_static_metadata.valid ||
2416 stream->use_dynamic_meta)
10bff005
YS
2417 return;
2418
0eeef690 2419 *info_packet = stream->hdr_static_metadata;
1646a6fe
AW
2420}
2421
6e4d6bee 2422static void set_vsc_info_packet(
e09b6473 2423 struct dc_info_packet *info_packet,
0971c40e 2424 struct dc_stream_state *stream)
4562236b 2425{
1336926f 2426 if (!stream->vsc_infopacket.valid)
4562236b
HW
2427 return;
2428
1336926f 2429 *info_packet = stream->vsc_infopacket;
4562236b
HW
2430}
2431
f36cc577 2432void dc_resource_state_destruct(struct dc_state *context)
4562236b
HW
2433{
2434 int i, j;
2435
ab2541b6 2436 for (i = 0; i < context->stream_count; i++) {
3be5262e
HW
2437 for (j = 0; j < context->stream_status[i].plane_count; j++)
2438 dc_plane_state_release(
2439 context->stream_status[i].plane_states[j]);
4562236b 2440
3be5262e 2441 context->stream_status[i].plane_count = 0;
4fa086b9 2442 dc_stream_release(context->streams[i]);
ab2541b6 2443 context->streams[i] = NULL;
4562236b
HW
2444 }
2445}
2446
f36cc577 2447void dc_resource_state_copy_construct(
608ac7bb
JZ
2448 const struct dc_state *src_ctx,
2449 struct dc_state *dst_ctx)
4562236b
HW
2450{
2451 int i, j;
8ee5702a 2452 struct kref refcount = dst_ctx->refcount;
4562236b
HW
2453
2454 *dst_ctx = *src_ctx;
2455
a2b8659d 2456 for (i = 0; i < MAX_PIPES; i++) {
4562236b
HW
2457 struct pipe_ctx *cur_pipe = &dst_ctx->res_ctx.pipe_ctx[i];
2458
2459 if (cur_pipe->top_pipe)
2460 cur_pipe->top_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
2461
2462 if (cur_pipe->bottom_pipe)
2463 cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
b1f6d01c
DL
2464
2465 if (cur_pipe->next_odm_pipe)
2466 cur_pipe->next_odm_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx];
2467
2468 if (cur_pipe->prev_odm_pipe)
2469 cur_pipe->prev_odm_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx];
4562236b
HW
2470 }
2471
ab2541b6 2472 for (i = 0; i < dst_ctx->stream_count; i++) {
4fa086b9 2473 dc_stream_retain(dst_ctx->streams[i]);
3be5262e
HW
2474 for (j = 0; j < dst_ctx->stream_status[i].plane_count; j++)
2475 dc_plane_state_retain(
2476 dst_ctx->stream_status[i].plane_states[j]);
4562236b 2477 }
9a3afbb3
AG
2478
2479 /* context refcount should not be overridden */
8ee5702a 2480 dst_ctx->refcount = refcount;
9a3afbb3 2481
4562236b
HW
2482}
2483
2484struct clock_source *dc_resource_find_first_free_pll(
a2b8659d
TC
2485 struct resource_context *res_ctx,
2486 const struct resource_pool *pool)
4562236b
HW
2487{
2488 int i;
2489
a2b8659d 2490 for (i = 0; i < pool->clk_src_count; ++i) {
4562236b 2491 if (res_ctx->clock_source_ref_count[i] == 0)
a2b8659d 2492 return pool->clock_sources[i];
4562236b
HW
2493 }
2494
2495 return NULL;
2496}
2497
2498void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
2499{
2500 enum signal_type signal = SIGNAL_TYPE_NONE;
96c50c0d 2501 struct encoder_info_frame *info = &pipe_ctx->stream_res.encoder_info_frame;
4562236b
HW
2502
2503 /* default all packets to invalid */
6e4d6bee
TC
2504 info->avi.valid = false;
2505 info->gamut.valid = false;
2506 info->vendor.valid = false;
630e3573 2507 info->spd.valid = false;
6e4d6bee
TC
2508 info->hdrsmd.valid = false;
2509 info->vsc.valid = false;
4562236b
HW
2510
2511 signal = pipe_ctx->stream->signal;
2512
2513 /* HDMi and DP have different info packets*/
2514 if (dc_is_hdmi_signal(signal)) {
6e4d6bee
TC
2515 set_avi_info_frame(&info->avi, pipe_ctx);
2516
2517 set_vendor_info_packet(&info->vendor, pipe_ctx->stream);
2518
2519 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2520
56ef6ed9 2521 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
6e4d6bee 2522
a33fa99d 2523 } else if (dc_is_dp_signal(signal)) {
6e4d6bee
TC
2524 set_vsc_info_packet(&info->vsc, pipe_ctx->stream);
2525
2526 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2527
56ef6ed9 2528 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
a33fa99d 2529 }
4562236b 2530
6e4d6bee 2531 patch_gamut_packet_checksum(&info->gamut);
4562236b
HW
2532}
2533
2534enum dc_status resource_map_clock_resources(
fb3466a4 2535 const struct dc *dc,
608ac7bb 2536 struct dc_state *context,
1dc90497 2537 struct dc_stream_state *stream)
4562236b 2538{
4562236b 2539 /* acquire new resources */
1dc90497
AG
2540 const struct resource_pool *pool = dc->res_pool;
2541 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(
2542 &context->res_ctx, stream);
ab2541b6 2543
1dc90497
AG
2544 if (!pipe_ctx)
2545 return DC_ERROR_UNEXPECTED;
4562236b 2546
1dc90497
AG
2547 if (dc_is_dp_signal(pipe_ctx->stream->signal)
2548 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)
2549 pipe_ctx->clock_source = pool->dp_clock_source;
2550 else {
2551 pipe_ctx->clock_source = NULL;
4562236b 2552
1dc90497 2553 if (!dc->config.disable_disp_pll_sharing)
4ed4e51b 2554 pipe_ctx->clock_source = resource_find_used_clk_src_for_sharing(
1dc90497
AG
2555 &context->res_ctx,
2556 pipe_ctx);
4562236b 2557
1dc90497
AG
2558 if (pipe_ctx->clock_source == NULL)
2559 pipe_ctx->clock_source =
2560 dc_resource_find_first_free_pll(
2561 &context->res_ctx,
2562 pool);
2563 }
4562236b 2564
1dc90497
AG
2565 if (pipe_ctx->clock_source == NULL)
2566 return DC_NO_CLOCK_SOURCE_RESOURCE;
4562236b 2567
1dc90497
AG
2568 resource_reference_clock_source(
2569 &context->res_ctx, pool,
2570 pipe_ctx->clock_source);
4562236b
HW
2571
2572 return DC_OK;
2573}
2574
2575/*
2576 * Note: We need to disable output if clock sources change,
2577 * since bios does optimization and doesn't apply if changing
2578 * PHY when not already disabled.
2579 */
2580bool pipe_need_reprogram(
2581 struct pipe_ctx *pipe_ctx_old,
2582 struct pipe_ctx *pipe_ctx)
2583{
cfe4645e
DL
2584 if (!pipe_ctx_old->stream)
2585 return false;
2586
4562236b
HW
2587 if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink)
2588 return true;
2589
2590 if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal)
2591 return true;
2592
afaacef4 2593 if (pipe_ctx_old->stream_res.audio != pipe_ctx->stream_res.audio)
4562236b
HW
2594 return true;
2595
2596 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source
2597 && pipe_ctx_old->stream != pipe_ctx->stream)
2598 return true;
2599
8e9c4c8c 2600 if (pipe_ctx_old->stream_res.stream_enc != pipe_ctx->stream_res.stream_enc)
4562236b
HW
2601 return true;
2602
2603 if (is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2604 return true;
2605
6b622181
JP
2606 if (is_hdr_static_meta_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2607 return true;
4562236b 2608
1e7e86c4
ST
2609 if (pipe_ctx_old->stream->dpms_off != pipe_ctx->stream->dpms_off)
2610 return true;
2611
1336926f
A
2612 if (is_vsc_info_packet_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2613 return true;
2614
eed928dc
CL
2615 if (false == pipe_ctx_old->stream->link->link_state_valid &&
2616 false == pipe_ctx_old->stream->dpms_off)
2617 return true;
2618
4562236b
HW
2619 return false;
2620}
529cad0f 2621
0971c40e 2622void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream,
529cad0f
DW
2623 struct bit_depth_reduction_params *fmt_bit_depth)
2624{
4fa086b9 2625 enum dc_dither_option option = stream->dither_option;
529cad0f 2626 enum dc_pixel_encoding pixel_encoding =
4fa086b9 2627 stream->timing.pixel_encoding;
529cad0f
DW
2628
2629 memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth));
2630
603767f9
TC
2631 if (option == DITHER_OPTION_DEFAULT) {
2632 switch (stream->timing.display_color_depth) {
2633 case COLOR_DEPTH_666:
2634 option = DITHER_OPTION_SPATIAL6;
2635 break;
2636 case COLOR_DEPTH_888:
2637 option = DITHER_OPTION_SPATIAL8;
2638 break;
2639 case COLOR_DEPTH_101010:
2640 option = DITHER_OPTION_SPATIAL10;
2641 break;
2642 default:
2643 option = DITHER_OPTION_DISABLE;
2644 }
2645 }
2646
529cad0f
DW
2647 if (option == DITHER_OPTION_DISABLE)
2648 return;
2649
2650 if (option == DITHER_OPTION_TRUN6) {
2651 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2652 fmt_bit_depth->flags.TRUNCATE_DEPTH = 0;
2653 } else if (option == DITHER_OPTION_TRUN8 ||
2654 option == DITHER_OPTION_TRUN8_SPATIAL6 ||
2655 option == DITHER_OPTION_TRUN8_FM6) {
2656 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2657 fmt_bit_depth->flags.TRUNCATE_DEPTH = 1;
2658 } else if (option == DITHER_OPTION_TRUN10 ||
2659 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
2660 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
2661 option == DITHER_OPTION_TRUN10_FM8 ||
2662 option == DITHER_OPTION_TRUN10_FM6 ||
2663 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2664 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2665 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2666 }
2667
2668 /* special case - Formatter can only reduce by 4 bits at most.
2669 * When reducing from 12 to 6 bits,
2670 * HW recommends we use trunc with round mode
2671 * (if we did nothing, trunc to 10 bits would be used)
2672 * note that any 12->10 bit reduction is ignored prior to DCE8,
2673 * as the input was 10 bits.
2674 */
2675 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2676 option == DITHER_OPTION_SPATIAL6 ||
2677 option == DITHER_OPTION_FM6) {
2678 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2679 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2680 fmt_bit_depth->flags.TRUNCATE_MODE = 1;
2681 }
2682
2683 /* spatial dither
2684 * note that spatial modes 1-3 are never used
2685 */
2686 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2687 option == DITHER_OPTION_SPATIAL6 ||
2688 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
2689 option == DITHER_OPTION_TRUN8_SPATIAL6) {
2690 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2691 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 0;
2692 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2693 fmt_bit_depth->flags.RGB_RANDOM =
2694 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2695 } else if (option == DITHER_OPTION_SPATIAL8_FRAME_RANDOM ||
2696 option == DITHER_OPTION_SPATIAL8 ||
2697 option == DITHER_OPTION_SPATIAL8_FM6 ||
2698 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
2699 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2700 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2701 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 1;
2702 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2703 fmt_bit_depth->flags.RGB_RANDOM =
2704 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2705 } else if (option == DITHER_OPTION_SPATIAL10_FRAME_RANDOM ||
2706 option == DITHER_OPTION_SPATIAL10 ||
2707 option == DITHER_OPTION_SPATIAL10_FM8 ||
2708 option == DITHER_OPTION_SPATIAL10_FM6) {
2709 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2710 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 2;
2711 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2712 fmt_bit_depth->flags.RGB_RANDOM =
2713 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2714 }
2715
2716 if (option == DITHER_OPTION_SPATIAL6 ||
2717 option == DITHER_OPTION_SPATIAL8 ||
2718 option == DITHER_OPTION_SPATIAL10) {
2719 fmt_bit_depth->flags.FRAME_RANDOM = 0;
2720 } else {
2721 fmt_bit_depth->flags.FRAME_RANDOM = 1;
2722 }
2723
2724 //////////////////////
2725 //// temporal dither
2726 //////////////////////
2727 if (option == DITHER_OPTION_FM6 ||
2728 option == DITHER_OPTION_SPATIAL8_FM6 ||
2729 option == DITHER_OPTION_SPATIAL10_FM6 ||
2730 option == DITHER_OPTION_TRUN10_FM6 ||
2731 option == DITHER_OPTION_TRUN8_FM6 ||
2732 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2733 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2734 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 0;
2735 } else if (option == DITHER_OPTION_FM8 ||
2736 option == DITHER_OPTION_SPATIAL10_FM8 ||
2737 option == DITHER_OPTION_TRUN10_FM8) {
2738 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2739 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 1;
2740 } else if (option == DITHER_OPTION_FM10) {
2741 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2742 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 2;
2743 }
2744
2745 fmt_bit_depth->pixel_encoding = pixel_encoding;
2746}
9345d987 2747
62c933f9 2748enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream)
9345d987 2749{
ceb3dbb4 2750 struct dc_link *link = stream->link;
2b77dcc5 2751 struct timing_generator *tg = dc->res_pool->timing_generators[0];
9345d987
AG
2752 enum dc_status res = DC_OK;
2753
4fa086b9 2754 calculate_phy_pix_clks(stream);
9345d987 2755
4fa086b9 2756 if (!tg->funcs->validate_timing(tg, &stream->timing))
9345d987
AG
2757 res = DC_FAIL_CONTROLLER_VALIDATE;
2758
248cbed6 2759 if (res == DC_OK) {
9345d987 2760 if (!link->link_enc->funcs->validate_output_with_stream(
4fa086b9 2761 link->link_enc, stream))
9345d987 2762 res = DC_FAIL_ENC_VALIDATE;
248cbed6 2763 }
9345d987
AG
2764
2765 /* TODO: validate audio ASIC caps, encoder */
2766
2767 if (res == DC_OK)
4fa086b9 2768 res = dc_link_validate_mode_timing(stream,
9345d987 2769 link,
4fa086b9 2770 &stream->timing);
9345d987 2771
62c933f9 2772 return res;
9345d987 2773}
792671d7 2774
62c933f9 2775enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state)
792671d7 2776{
62c933f9
YS
2777 enum dc_status res = DC_OK;
2778
792671d7 2779 /* TODO For now validates pixel format only */
8e7095b9 2780 if (dc->res_pool->funcs->validate_plane)
62c933f9 2781 return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps);
792671d7 2782
62c933f9 2783 return res;
792671d7 2784}
74eac5f3
SSC
2785
2786unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format)
2787{
2788 switch (format) {
2789 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
2790 return 8;
2791 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
2792 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
2793 return 12;
2794 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
2795 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
2796 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
2797 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
2798 return 16;
2799 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
2800 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
2801 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
2802 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
2803 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
2804 return 32;
2805 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
2806 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
2807 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
2808 return 64;
2809 default:
2810 ASSERT_CRITICAL(false);
2811 return -1;
2812 }
2813}